1*6bbbd442SRobert Mustacchi /*-
2*6bbbd442SRobert Mustacchi * Copyright 2021 Intel Corp
3*6bbbd442SRobert Mustacchi * Copyright 2021 Rubicon Communications, LLC (Netgate)
4*6bbbd442SRobert Mustacchi * SPDX-License-Identifier: BSD-3-Clause
5*6bbbd442SRobert Mustacchi */
6*6bbbd442SRobert Mustacchi
7*6bbbd442SRobert Mustacchi #include "igc_hw.h"
8*6bbbd442SRobert Mustacchi #include "igc_i225.h"
9*6bbbd442SRobert Mustacchi #include "igc_mac.h"
10*6bbbd442SRobert Mustacchi #include "igc_base.h"
11*6bbbd442SRobert Mustacchi
12*6bbbd442SRobert Mustacchi /**
13*6bbbd442SRobert Mustacchi * igc_acquire_phy_base - Acquire rights to access PHY
14*6bbbd442SRobert Mustacchi * @hw: pointer to the HW structure
15*6bbbd442SRobert Mustacchi *
16*6bbbd442SRobert Mustacchi * Acquire access rights to the correct PHY.
17*6bbbd442SRobert Mustacchi **/
igc_acquire_phy_base(struct igc_hw * hw)18*6bbbd442SRobert Mustacchi s32 igc_acquire_phy_base(struct igc_hw *hw)
19*6bbbd442SRobert Mustacchi {
20*6bbbd442SRobert Mustacchi u16 mask = IGC_SWFW_PHY0_SM;
21*6bbbd442SRobert Mustacchi
22*6bbbd442SRobert Mustacchi DEBUGFUNC("igc_acquire_phy_base");
23*6bbbd442SRobert Mustacchi
24*6bbbd442SRobert Mustacchi if (hw->bus.func == IGC_FUNC_1)
25*6bbbd442SRobert Mustacchi mask = IGC_SWFW_PHY1_SM;
26*6bbbd442SRobert Mustacchi
27*6bbbd442SRobert Mustacchi return hw->mac.ops.acquire_swfw_sync(hw, mask);
28*6bbbd442SRobert Mustacchi }
29*6bbbd442SRobert Mustacchi
30*6bbbd442SRobert Mustacchi /**
31*6bbbd442SRobert Mustacchi * igc_release_phy_base - Release rights to access PHY
32*6bbbd442SRobert Mustacchi * @hw: pointer to the HW structure
33*6bbbd442SRobert Mustacchi *
34*6bbbd442SRobert Mustacchi * A wrapper to release access rights to the correct PHY.
35*6bbbd442SRobert Mustacchi **/
igc_release_phy_base(struct igc_hw * hw)36*6bbbd442SRobert Mustacchi void igc_release_phy_base(struct igc_hw *hw)
37*6bbbd442SRobert Mustacchi {
38*6bbbd442SRobert Mustacchi u16 mask = IGC_SWFW_PHY0_SM;
39*6bbbd442SRobert Mustacchi
40*6bbbd442SRobert Mustacchi DEBUGFUNC("igc_release_phy_base");
41*6bbbd442SRobert Mustacchi
42*6bbbd442SRobert Mustacchi if (hw->bus.func == IGC_FUNC_1)
43*6bbbd442SRobert Mustacchi mask = IGC_SWFW_PHY1_SM;
44*6bbbd442SRobert Mustacchi
45*6bbbd442SRobert Mustacchi hw->mac.ops.release_swfw_sync(hw, mask);
46*6bbbd442SRobert Mustacchi }
47*6bbbd442SRobert Mustacchi
48*6bbbd442SRobert Mustacchi /**
49*6bbbd442SRobert Mustacchi * igc_init_hw_base - Initialize hardware
50*6bbbd442SRobert Mustacchi * @hw: pointer to the HW structure
51*6bbbd442SRobert Mustacchi *
52*6bbbd442SRobert Mustacchi * This inits the hardware readying it for operation.
53*6bbbd442SRobert Mustacchi **/
igc_init_hw_base(struct igc_hw * hw)54*6bbbd442SRobert Mustacchi s32 igc_init_hw_base(struct igc_hw *hw)
55*6bbbd442SRobert Mustacchi {
56*6bbbd442SRobert Mustacchi struct igc_mac_info *mac = &hw->mac;
57*6bbbd442SRobert Mustacchi s32 ret_val;
58*6bbbd442SRobert Mustacchi u16 i, rar_count = mac->rar_entry_count;
59*6bbbd442SRobert Mustacchi
60*6bbbd442SRobert Mustacchi DEBUGFUNC("igc_init_hw_base");
61*6bbbd442SRobert Mustacchi
62*6bbbd442SRobert Mustacchi /* Setup the receive address */
63*6bbbd442SRobert Mustacchi igc_init_rx_addrs_generic(hw, rar_count);
64*6bbbd442SRobert Mustacchi
65*6bbbd442SRobert Mustacchi /* Zero out the Multicast HASH table */
66*6bbbd442SRobert Mustacchi DEBUGOUT("Zeroing the MTA\n");
67*6bbbd442SRobert Mustacchi for (i = 0; i < mac->mta_reg_count; i++)
68*6bbbd442SRobert Mustacchi IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, 0);
69*6bbbd442SRobert Mustacchi
70*6bbbd442SRobert Mustacchi /* Zero out the Unicast HASH table */
71*6bbbd442SRobert Mustacchi DEBUGOUT("Zeroing the UTA\n");
72*6bbbd442SRobert Mustacchi for (i = 0; i < mac->uta_reg_count; i++)
73*6bbbd442SRobert Mustacchi IGC_WRITE_REG_ARRAY(hw, IGC_UTA, i, 0);
74*6bbbd442SRobert Mustacchi
75*6bbbd442SRobert Mustacchi /* Setup link and flow control */
76*6bbbd442SRobert Mustacchi ret_val = mac->ops.setup_link(hw);
77*6bbbd442SRobert Mustacchi /*
78*6bbbd442SRobert Mustacchi * Clear all of the statistics registers (clear on read). It is
79*6bbbd442SRobert Mustacchi * important that we do this after we have tried to establish link
80*6bbbd442SRobert Mustacchi * because the symbol error count will increment wildly if there
81*6bbbd442SRobert Mustacchi * is no link.
82*6bbbd442SRobert Mustacchi */
83*6bbbd442SRobert Mustacchi igc_clear_hw_cntrs_base_generic(hw);
84*6bbbd442SRobert Mustacchi
85*6bbbd442SRobert Mustacchi return ret_val;
86*6bbbd442SRobert Mustacchi }
87*6bbbd442SRobert Mustacchi
88*6bbbd442SRobert Mustacchi /**
89*6bbbd442SRobert Mustacchi * igc_power_down_phy_copper_base - Remove link during PHY power down
90*6bbbd442SRobert Mustacchi * @hw: pointer to the HW structure
91*6bbbd442SRobert Mustacchi *
92*6bbbd442SRobert Mustacchi * In the case of a PHY power down to save power, or to turn off link during a
93*6bbbd442SRobert Mustacchi * driver unload, or wake on lan is not enabled, remove the link.
94*6bbbd442SRobert Mustacchi **/
igc_power_down_phy_copper_base(struct igc_hw * hw)95*6bbbd442SRobert Mustacchi void igc_power_down_phy_copper_base(struct igc_hw *hw)
96*6bbbd442SRobert Mustacchi {
97*6bbbd442SRobert Mustacchi struct igc_phy_info *phy = &hw->phy;
98*6bbbd442SRobert Mustacchi
99*6bbbd442SRobert Mustacchi if (!(phy->ops.check_reset_block))
100*6bbbd442SRobert Mustacchi return;
101*6bbbd442SRobert Mustacchi
102*6bbbd442SRobert Mustacchi /* If the management interface is not enabled, then power down */
103*6bbbd442SRobert Mustacchi if (phy->ops.check_reset_block(hw))
104*6bbbd442SRobert Mustacchi igc_power_down_phy_copper(hw);
105*6bbbd442SRobert Mustacchi
106*6bbbd442SRobert Mustacchi return;
107*6bbbd442SRobert Mustacchi }
108*6bbbd442SRobert Mustacchi
109*6bbbd442SRobert Mustacchi /**
110*6bbbd442SRobert Mustacchi * igc_rx_fifo_flush_base - Clean Rx FIFO after Rx enable
111*6bbbd442SRobert Mustacchi * @hw: pointer to the HW structure
112*6bbbd442SRobert Mustacchi *
113*6bbbd442SRobert Mustacchi * After Rx enable, if manageability is enabled then there is likely some
114*6bbbd442SRobert Mustacchi * bad data at the start of the FIFO and possibly in the DMA FIFO. This
115*6bbbd442SRobert Mustacchi * function clears the FIFOs and flushes any packets that came in as Rx was
116*6bbbd442SRobert Mustacchi * being enabled.
117*6bbbd442SRobert Mustacchi **/
igc_rx_fifo_flush_base(struct igc_hw * hw)118*6bbbd442SRobert Mustacchi void igc_rx_fifo_flush_base(struct igc_hw *hw)
119*6bbbd442SRobert Mustacchi {
120*6bbbd442SRobert Mustacchi u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
121*6bbbd442SRobert Mustacchi int i, ms_wait;
122*6bbbd442SRobert Mustacchi
123*6bbbd442SRobert Mustacchi DEBUGFUNC("igc_rx_fifo_flush_base");
124*6bbbd442SRobert Mustacchi
125*6bbbd442SRobert Mustacchi /* disable IPv6 options as per hardware errata */
126*6bbbd442SRobert Mustacchi rfctl = IGC_READ_REG(hw, IGC_RFCTL);
127*6bbbd442SRobert Mustacchi rfctl |= IGC_RFCTL_IPV6_EX_DIS;
128*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
129*6bbbd442SRobert Mustacchi
130*6bbbd442SRobert Mustacchi if (!(IGC_READ_REG(hw, IGC_MANC) & IGC_MANC_RCV_TCO_EN))
131*6bbbd442SRobert Mustacchi return;
132*6bbbd442SRobert Mustacchi
133*6bbbd442SRobert Mustacchi /* Disable all Rx queues */
134*6bbbd442SRobert Mustacchi for (i = 0; i < 4; i++) {
135*6bbbd442SRobert Mustacchi rxdctl[i] = IGC_READ_REG(hw, IGC_RXDCTL(i));
136*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RXDCTL(i),
137*6bbbd442SRobert Mustacchi rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
138*6bbbd442SRobert Mustacchi }
139*6bbbd442SRobert Mustacchi /* Poll all queues to verify they have shut down */
140*6bbbd442SRobert Mustacchi for (ms_wait = 0; ms_wait < 10; ms_wait++) {
141*6bbbd442SRobert Mustacchi msec_delay(1);
142*6bbbd442SRobert Mustacchi rx_enabled = 0;
143*6bbbd442SRobert Mustacchi for (i = 0; i < 4; i++)
144*6bbbd442SRobert Mustacchi rx_enabled |= IGC_READ_REG(hw, IGC_RXDCTL(i));
145*6bbbd442SRobert Mustacchi if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
146*6bbbd442SRobert Mustacchi break;
147*6bbbd442SRobert Mustacchi }
148*6bbbd442SRobert Mustacchi
149*6bbbd442SRobert Mustacchi if (ms_wait == 10)
150*6bbbd442SRobert Mustacchi DEBUGOUT("Queue disable timed out after 10ms\n");
151*6bbbd442SRobert Mustacchi
152*6bbbd442SRobert Mustacchi /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
153*6bbbd442SRobert Mustacchi * incoming packets are rejected. Set enable and wait 2ms so that
154*6bbbd442SRobert Mustacchi * any packet that was coming in as RCTL.EN was set is flushed
155*6bbbd442SRobert Mustacchi */
156*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
157*6bbbd442SRobert Mustacchi
158*6bbbd442SRobert Mustacchi rlpml = IGC_READ_REG(hw, IGC_RLPML);
159*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RLPML, 0);
160*6bbbd442SRobert Mustacchi
161*6bbbd442SRobert Mustacchi rctl = IGC_READ_REG(hw, IGC_RCTL);
162*6bbbd442SRobert Mustacchi temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
163*6bbbd442SRobert Mustacchi temp_rctl |= IGC_RCTL_LPE;
164*6bbbd442SRobert Mustacchi
165*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl);
166*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RCTL, temp_rctl | IGC_RCTL_EN);
167*6bbbd442SRobert Mustacchi IGC_WRITE_FLUSH(hw);
168*6bbbd442SRobert Mustacchi msec_delay(2);
169*6bbbd442SRobert Mustacchi
170*6bbbd442SRobert Mustacchi /* Enable Rx queues that were previously enabled and restore our
171*6bbbd442SRobert Mustacchi * previous state
172*6bbbd442SRobert Mustacchi */
173*6bbbd442SRobert Mustacchi for (i = 0; i < 4; i++)
174*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl[i]);
175*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RCTL, rctl);
176*6bbbd442SRobert Mustacchi IGC_WRITE_FLUSH(hw);
177*6bbbd442SRobert Mustacchi
178*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RLPML, rlpml);
179*6bbbd442SRobert Mustacchi IGC_WRITE_REG(hw, IGC_RFCTL, rfctl);
180*6bbbd442SRobert Mustacchi
181*6bbbd442SRobert Mustacchi /* Flush receive errors generated by workaround */
182*6bbbd442SRobert Mustacchi IGC_READ_REG(hw, IGC_ROC);
183*6bbbd442SRobert Mustacchi IGC_READ_REG(hw, IGC_RNBC);
184*6bbbd442SRobert Mustacchi IGC_READ_REG(hw, IGC_MPC);
185*6bbbd442SRobert Mustacchi }
186