19d26e4fcSRobert Mustacchi /* 29d26e4fcSRobert Mustacchi * This file and its contents are supplied under the terms of the 39d26e4fcSRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 49d26e4fcSRobert Mustacchi * You may only use this file in accordance with the terms of version 59d26e4fcSRobert Mustacchi * 1.0 of the CDDL. 69d26e4fcSRobert Mustacchi * 79d26e4fcSRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 89d26e4fcSRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 99d26e4fcSRobert Mustacchi * http://www.illumos.org/license/CDDL. 109d26e4fcSRobert Mustacchi */ 119d26e4fcSRobert Mustacchi 129d26e4fcSRobert Mustacchi /* 139d26e4fcSRobert Mustacchi * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 1409aee612SRyan Zezeski * Copyright 2019 Joyent, Inc. 15396505afSPaul Winder * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16*88628b1bSRyan Zezeski * Copyright 2020 Ryan Zezeski 179d26e4fcSRobert Mustacchi */ 189d26e4fcSRobert Mustacchi 199d26e4fcSRobert Mustacchi /* 209d26e4fcSRobert Mustacchi * Please see i40e_main.c for an introduction to the device driver, its layout, 219d26e4fcSRobert Mustacchi * and more. 229d26e4fcSRobert Mustacchi */ 239d26e4fcSRobert Mustacchi 249d26e4fcSRobert Mustacchi #ifndef _I40E_SW_H 259d26e4fcSRobert Mustacchi #define _I40E_SW_H 269d26e4fcSRobert Mustacchi 279d26e4fcSRobert Mustacchi #ifdef __cplusplus 289d26e4fcSRobert Mustacchi extern "C" { 299d26e4fcSRobert Mustacchi #endif 309d26e4fcSRobert Mustacchi 319d26e4fcSRobert Mustacchi #include <sys/types.h> 329d26e4fcSRobert Mustacchi #include <sys/conf.h> 339d26e4fcSRobert Mustacchi #include <sys/debug.h> 349d26e4fcSRobert Mustacchi #include <sys/stropts.h> 359d26e4fcSRobert Mustacchi #include <sys/stream.h> 369d26e4fcSRobert Mustacchi #include <sys/strsun.h> 379d26e4fcSRobert Mustacchi #include <sys/strlog.h> 389d26e4fcSRobert Mustacchi #include <sys/kmem.h> 399d26e4fcSRobert Mustacchi #include <sys/stat.h> 409d26e4fcSRobert Mustacchi #include <sys/kstat.h> 419d26e4fcSRobert Mustacchi #include <sys/modctl.h> 429d26e4fcSRobert Mustacchi #include <sys/errno.h> 439d26e4fcSRobert Mustacchi #include <sys/dlpi.h> 449d26e4fcSRobert Mustacchi #include <sys/mac_provider.h> 459d26e4fcSRobert Mustacchi #include <sys/mac_ether.h> 469d26e4fcSRobert Mustacchi #include <sys/vlan.h> 479d26e4fcSRobert Mustacchi #include <sys/ddi.h> 489d26e4fcSRobert Mustacchi #include <sys/sunddi.h> 499d26e4fcSRobert Mustacchi #include <sys/pci.h> 509d26e4fcSRobert Mustacchi #include <sys/pcie.h> 519d26e4fcSRobert Mustacchi #include <sys/sdt.h> 529d26e4fcSRobert Mustacchi #include <sys/ethernet.h> 539d26e4fcSRobert Mustacchi #include <sys/pattr.h> 549d26e4fcSRobert Mustacchi #include <sys/strsubr.h> 559d26e4fcSRobert Mustacchi #include <sys/netlb.h> 569d26e4fcSRobert Mustacchi #include <sys/random.h> 579d26e4fcSRobert Mustacchi #include <inet/common.h> 589d26e4fcSRobert Mustacchi #include <inet/tcp.h> 599d26e4fcSRobert Mustacchi #include <inet/ip.h> 609d26e4fcSRobert Mustacchi #include <inet/mi.h> 619d26e4fcSRobert Mustacchi #include <inet/nd.h> 629d26e4fcSRobert Mustacchi #include <netinet/udp.h> 639d26e4fcSRobert Mustacchi #include <netinet/sctp.h> 649d26e4fcSRobert Mustacchi #include <sys/bitmap.h> 659d26e4fcSRobert Mustacchi #include <sys/cpuvar.h> 669d26e4fcSRobert Mustacchi #include <sys/ddifm.h> 679d26e4fcSRobert Mustacchi #include <sys/fm/protocol.h> 689d26e4fcSRobert Mustacchi #include <sys/fm/util.h> 699d26e4fcSRobert Mustacchi #include <sys/disp.h> 709d26e4fcSRobert Mustacchi #include <sys/fm/io/ddi.h> 719d26e4fcSRobert Mustacchi #include <sys/list.h> 729d26e4fcSRobert Mustacchi #include <sys/debug.h> 739d26e4fcSRobert Mustacchi #include <sys/sdt.h> 74508a0e8cSRob Johnston #include <sys/ddi_ufm.h> 759d26e4fcSRobert Mustacchi #include "i40e_type.h" 769d26e4fcSRobert Mustacchi #include "i40e_osdep.h" 779d26e4fcSRobert Mustacchi #include "i40e_prototype.h" 789d26e4fcSRobert Mustacchi #include "i40e_xregs.h" 799d26e4fcSRobert Mustacchi 809d26e4fcSRobert Mustacchi #define I40E_MODULE_NAME "i40e" 819d26e4fcSRobert Mustacchi 829d26e4fcSRobert Mustacchi #define I40E_ADAPTER_REGSET 1 839d26e4fcSRobert Mustacchi 849d26e4fcSRobert Mustacchi /* 859d26e4fcSRobert Mustacchi * Configuration constants. Note that the hardware defines a minimum bound of 32 869d26e4fcSRobert Mustacchi * descriptors and requires that the programming of the descriptor lengths be 879d26e4fcSRobert Mustacchi * aligned in units of 32 descriptors. 889d26e4fcSRobert Mustacchi */ 899d26e4fcSRobert Mustacchi #define I40E_MIN_TX_RING_SIZE 64 909d26e4fcSRobert Mustacchi #define I40E_MAX_TX_RING_SIZE 4096 919d26e4fcSRobert Mustacchi #define I40E_DEF_TX_RING_SIZE 1024 929d26e4fcSRobert Mustacchi 93*88628b1bSRyan Zezeski /* 94*88628b1bSRyan Zezeski * Place an artificial limit on the max number of groups. The X710 95*88628b1bSRyan Zezeski * series supports up to 384 VSIs to be partitioned across PFs as the 96*88628b1bSRyan Zezeski * driver sees fit. But until we support more interrupts this seems 97*88628b1bSRyan Zezeski * like a good place to start. 98*88628b1bSRyan Zezeski */ 99*88628b1bSRyan Zezeski #define I40E_MIN_NUM_RX_GROUPS 1 100*88628b1bSRyan Zezeski #define I40E_MAX_NUM_RX_GROUPS 32 101*88628b1bSRyan Zezeski #define I40E_DEF_NUM_RX_GROUPS 16 102*88628b1bSRyan Zezeski 1039d26e4fcSRobert Mustacchi #define I40E_MIN_RX_RING_SIZE 64 1049d26e4fcSRobert Mustacchi #define I40E_MAX_RX_RING_SIZE 4096 1059d26e4fcSRobert Mustacchi #define I40E_DEF_RX_RING_SIZE 1024 1069d26e4fcSRobert Mustacchi 1079d26e4fcSRobert Mustacchi #define I40E_DESC_ALIGN 32 1089d26e4fcSRobert Mustacchi 1099d26e4fcSRobert Mustacchi /* 1109d26e4fcSRobert Mustacchi * Sizes used for asynchronous processing of the adminq. We allocate a fixed 1119d26e4fcSRobert Mustacchi * size buffer for each instance of the device during attach time, rather than 1129d26e4fcSRobert Mustacchi * allocating and freeing one during interrupt processing. 1139d26e4fcSRobert Mustacchi * 1149d26e4fcSRobert Mustacchi * We also define the descriptor size of the admin queue here. 1159d26e4fcSRobert Mustacchi */ 1169d26e4fcSRobert Mustacchi #define I40E_ADMINQ_BUFSZ 4096 1179d26e4fcSRobert Mustacchi #define I40E_MAX_ADMINQ_SIZE 1024 1189d26e4fcSRobert Mustacchi #define I40E_DEF_ADMINQ_SIZE 256 1199d26e4fcSRobert Mustacchi 1209d26e4fcSRobert Mustacchi /* 1219d26e4fcSRobert Mustacchi * Note, while the min and maximum values are based upon the sizing of the ring 1229d26e4fcSRobert Mustacchi * itself, the default is taken from ixgbe without much thought. It's basically 1239d26e4fcSRobert Mustacchi * been cargo culted. See i40e_transceiver.c for a bit more information. 1249d26e4fcSRobert Mustacchi */ 1259d26e4fcSRobert Mustacchi #define I40E_MIN_RX_LIMIT_PER_INTR 16 1269d26e4fcSRobert Mustacchi #define I40E_MAX_RX_LIMIT_PER_INTR 4096 1279d26e4fcSRobert Mustacchi #define I40E_DEF_RX_LIMIT_PER_INTR 256 1289d26e4fcSRobert Mustacchi 1299d26e4fcSRobert Mustacchi /* 1309d26e4fcSRobert Mustacchi * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 1319d26e4fcSRobert Mustacchi * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 1329d26e4fcSRobert Mustacchi * header size (18 bytes) to get the actual maximum frame we can use. If 1339d26e4fcSRobert Mustacchi * different adapters end up with different sizes, we should make this value a 1349d26e4fcSRobert Mustacchi * bit more dynamic. 1359d26e4fcSRobert Mustacchi */ 1369d26e4fcSRobert Mustacchi #define I40E_MAX_MTU 9706 1379d26e4fcSRobert Mustacchi #define I40E_MIN_MTU ETHERMIN 1389d26e4fcSRobert Mustacchi #define I40E_DEF_MTU ETHERMTU 1399d26e4fcSRobert Mustacchi 1409d26e4fcSRobert Mustacchi /* 1419d26e4fcSRobert Mustacchi * Interrupt throttling related values. Interrupt throttling values are defined 1429d26e4fcSRobert Mustacchi * in two microsecond increments. Note that a value of zero basically says do no 1439d26e4fcSRobert Mustacchi * ITR activity. A helpful way to think about these is that setting the ITR to a 1449d26e4fcSRobert Mustacchi * value will allow a certain number of interrupts per second. 1459d26e4fcSRobert Mustacchi * 1469d26e4fcSRobert Mustacchi * Our default values for RX allow 20k interrupts per second while our default 1479d26e4fcSRobert Mustacchi * values for TX allow for 5k interrupts per second. For other class interrupts, 1489d26e4fcSRobert Mustacchi * we limit ourselves to a rate of 2k/s. 1499d26e4fcSRobert Mustacchi */ 1509d26e4fcSRobert Mustacchi #define I40E_MIN_ITR 0x0000 1519d26e4fcSRobert Mustacchi #define I40E_MAX_ITR 0x0FF0 1529d26e4fcSRobert Mustacchi #define I40E_DEF_RX_ITR 0x0019 1539d26e4fcSRobert Mustacchi #define I40E_DEF_TX_ITR 0x0064 1549d26e4fcSRobert Mustacchi #define I40E_DEF_OTHER_ITR 0x00FA 1559d26e4fcSRobert Mustacchi 1569d26e4fcSRobert Mustacchi /* 1579d26e4fcSRobert Mustacchi * Indexes into the three ITR registers that we have. 1589d26e4fcSRobert Mustacchi */ 1599d26e4fcSRobert Mustacchi typedef enum i40e_itr_index { 1609d26e4fcSRobert Mustacchi I40E_ITR_INDEX_RX = 0x0, 1619d26e4fcSRobert Mustacchi I40E_ITR_INDEX_TX = 0x1, 1629d26e4fcSRobert Mustacchi I40E_ITR_INDEX_OTHER = 0x2, 163508a0e8cSRob Johnston I40E_ITR_INDEX_NONE = 0x3 1649d26e4fcSRobert Mustacchi } i40e_itr_index_t; 1659d26e4fcSRobert Mustacchi 1669d26e4fcSRobert Mustacchi /* 16709aee612SRyan Zezeski * The hardware claims to support LSO up to 256 KB, but due to the limitations 16809aee612SRyan Zezeski * imposed by the IP header for non-jumbo frames, we cap it at 64 KB. 1699d26e4fcSRobert Mustacchi */ 17009aee612SRyan Zezeski #define I40E_LSO_MAXLEN (64 * 1024) 1719d26e4fcSRobert Mustacchi 1729d26e4fcSRobert Mustacchi #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 1739d26e4fcSRobert Mustacchi #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 1749d26e4fcSRobert Mustacchi 1759d26e4fcSRobert Mustacchi /* 1769d26e4fcSRobert Mustacchi * All the other queue types for are defined by the common code. However, this 1779d26e4fcSRobert Mustacchi * is the constant to indicate that it's terminated. 1789d26e4fcSRobert Mustacchi */ 1799d26e4fcSRobert Mustacchi #define I40E_QUEUE_TYPE_EOL 0x7FF 1809d26e4fcSRobert Mustacchi 1819d26e4fcSRobert Mustacchi /* 1829d26e4fcSRobert Mustacchi * See the comments in i40e_transceiver.c as to the purpose of this value and 1839d26e4fcSRobert Mustacchi * how it's used to ensure that the IP header is eventually aligned when it's 1849d26e4fcSRobert Mustacchi * received by the OS. 1859d26e4fcSRobert Mustacchi */ 1869d26e4fcSRobert Mustacchi #define I40E_BUF_IPHDR_ALIGNMENT 2 1879d26e4fcSRobert Mustacchi 1889d26e4fcSRobert Mustacchi /* 18909aee612SRyan Zezeski * The XL710 controller has a total of eight buffers available for the 19009aee612SRyan Zezeski * transmission of any single frame. This is defined in 8.4.1 - Transmit 1919d26e4fcSRobert Mustacchi * Packet in System Memory. 1929d26e4fcSRobert Mustacchi */ 1939d26e4fcSRobert Mustacchi #define I40E_TX_MAX_COOKIE 8 1949d26e4fcSRobert Mustacchi 19509aee612SRyan Zezeski /* 19609aee612SRyan Zezeski * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more 19709aee612SRyan Zezeski * cookies than a non-LSO frame. The key here to is to select a value such 19809aee612SRyan Zezeski * that once the HW has chunked up the LSO frame into MSS-sized segments that no 19909aee612SRyan Zezeski * single segment spans more than 8 cookies (see comments for 20009aee612SRyan Zezeski * I40E_TX_MAX_COOKIE) 20109aee612SRyan Zezeski */ 20209aee612SRyan Zezeski #define I40E_TX_LSO_MAX_COOKIE 32 20309aee612SRyan Zezeski 2049d26e4fcSRobert Mustacchi /* 2059d26e4fcSRobert Mustacchi * Sizing to determine the amount of available descriptors at which we'll 2069d26e4fcSRobert Mustacchi * consider ourselves blocked. Also, when we have these available, we'll then 2079d26e4fcSRobert Mustacchi * consider ourselves available to transmit to MAC again. Strictly speaking, the 2089d26e4fcSRobert Mustacchi * MAX is based on the ring size. The default sizing is based on ixgbe. 2099d26e4fcSRobert Mustacchi */ 2109d26e4fcSRobert Mustacchi #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 2119d26e4fcSRobert Mustacchi #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 2129d26e4fcSRobert Mustacchi 2139d26e4fcSRobert Mustacchi /* 2149d26e4fcSRobert Mustacchi * Sizing for DMA thresholds. These are used to indicate whether or not we 2159d26e4fcSRobert Mustacchi * should perform a bcopy or a DMA binding of a given message block. The range 2169d26e4fcSRobert Mustacchi * allows for setting things such that we'll always do a bcopy (a high value) or 2179d26e4fcSRobert Mustacchi * always perform a DMA binding (a low value). 2189d26e4fcSRobert Mustacchi */ 2199d26e4fcSRobert Mustacchi #define I40E_MIN_RX_DMA_THRESH 0 2209d26e4fcSRobert Mustacchi #define I40E_DEF_RX_DMA_THRESH 256 2219d26e4fcSRobert Mustacchi #define I40E_MAX_RX_DMA_THRESH INT32_MAX 2229d26e4fcSRobert Mustacchi 2239d26e4fcSRobert Mustacchi #define I40E_MIN_TX_DMA_THRESH 0 2249d26e4fcSRobert Mustacchi #define I40E_DEF_TX_DMA_THRESH 256 2259d26e4fcSRobert Mustacchi #define I40E_MAX_TX_DMA_THRESH INT32_MAX 2269d26e4fcSRobert Mustacchi 22709aee612SRyan Zezeski /* 22809aee612SRyan Zezeski * The max size of each individual tx buffer is 16KB - 1. 22909aee612SRyan Zezeski * See table 8-17 23009aee612SRyan Zezeski */ 23109aee612SRyan Zezeski #define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull 23209aee612SRyan Zezeski 2339d26e4fcSRobert Mustacchi /* 2349d26e4fcSRobert Mustacchi * Resource sizing counts. There are various aspects of hardware where we may 2359d26e4fcSRobert Mustacchi * have some variable number of elements that we need to handle. Such as the 2369d26e4fcSRobert Mustacchi * hardware capabilities and switch capacities. We cannot know a priori how many 2379d26e4fcSRobert Mustacchi * elements to do, so instead we take a starting guess and then will grow it up 2389d26e4fcSRobert Mustacchi * to an upper bound on a number of elements, to limit memory consumption in 2399d26e4fcSRobert Mustacchi * case of a hardware bug. 2409d26e4fcSRobert Mustacchi */ 2419d26e4fcSRobert Mustacchi #define I40E_HW_CAP_DEFAULT 40 2429d26e4fcSRobert Mustacchi #define I40E_SWITCH_CAP_DEFAULT 25 2439d26e4fcSRobert Mustacchi 2449d26e4fcSRobert Mustacchi /* 2459d26e4fcSRobert Mustacchi * Host Memory Context related constants. 2469d26e4fcSRobert Mustacchi */ 2479d26e4fcSRobert Mustacchi #define I40E_HMC_RX_CTX_UNIT 128 2489d26e4fcSRobert Mustacchi #define I40E_HMC_RX_DBUFF_MIN 1024 2499d26e4fcSRobert Mustacchi #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 2509d26e4fcSRobert Mustacchi #define I40E_HMC_RX_DTYPE_NOSPLIT 0 2519d26e4fcSRobert Mustacchi #define I40E_HMC_RX_DSIZE_32BYTE 1 2529d26e4fcSRobert Mustacchi #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 2539d26e4fcSRobert Mustacchi #define I40E_HMC_RX_FC_DISABLE 0 2549d26e4fcSRobert Mustacchi #define I40E_HMC_RX_L2TAGORDER 1 2559d26e4fcSRobert Mustacchi #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 2569d26e4fcSRobert Mustacchi #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 2579d26e4fcSRobert Mustacchi #define I40E_HMC_RX_TPH_DISABLE 0 2589d26e4fcSRobert Mustacchi #define I40E_HMC_RX_LOWRXQ_NOINTR 0 2599d26e4fcSRobert Mustacchi #define I40E_HMC_RX_PREFENA 1 2609d26e4fcSRobert Mustacchi 2619d26e4fcSRobert Mustacchi #define I40E_HMC_TX_CTX_UNIT 128 2629d26e4fcSRobert Mustacchi #define I40E_HMC_TX_NEW_CONTEXT 1 2639d26e4fcSRobert Mustacchi #define I40E_HMC_TX_FC_DISABLE 0 2649d26e4fcSRobert Mustacchi #define I40E_HMC_TX_TS_DISABLE 0 2659d26e4fcSRobert Mustacchi #define I40E_HMC_TX_FD_DISABLE 0 2669d26e4fcSRobert Mustacchi #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 2679d26e4fcSRobert Mustacchi #define I40E_HMC_TX_WB_ENABLE 1 2689d26e4fcSRobert Mustacchi #define I40E_HMC_TX_TPH_DISABLE 0 2699d26e4fcSRobert Mustacchi 2709d26e4fcSRobert Mustacchi /* 2719d26e4fcSRobert Mustacchi * This defines the error mask that we care about from rx descriptors. Currently 2729d26e4fcSRobert Mustacchi * we're only concerned with the general errors and oversize errors. 2739d26e4fcSRobert Mustacchi */ 2749d26e4fcSRobert Mustacchi #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 2759d26e4fcSRobert Mustacchi (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 2769d26e4fcSRobert Mustacchi 2779d26e4fcSRobert Mustacchi /* 2789d26e4fcSRobert Mustacchi * Property sizing macros for firmware versions, etc. They need to be large 2799d26e4fcSRobert Mustacchi * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 2809d26e4fcSRobert Mustacchi */ 2819d26e4fcSRobert Mustacchi #define I40E_DDI_PROP_LEN 64 2829d26e4fcSRobert Mustacchi 2839d26e4fcSRobert Mustacchi #define I40E_GROUP_NOMSIX 1 2849d26e4fcSRobert Mustacchi #define I40E_TRQPAIR_NOMSIX 1 2859d26e4fcSRobert Mustacchi 2869d26e4fcSRobert Mustacchi /* 2879d26e4fcSRobert Mustacchi * It seems reasonable to cast this to void because the only reason that we 2889d26e4fcSRobert Mustacchi * should be getting a DDI_FAILURE is due to the fact that we specify addresses 2899d26e4fcSRobert Mustacchi * out of range. Because we specify no offset or address, it shouldn't happen. 2909d26e4fcSRobert Mustacchi */ 2919d26e4fcSRobert Mustacchi #ifdef DEBUG 2929d26e4fcSRobert Mustacchi #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 2939d26e4fcSRobert Mustacchi (handle)->dmab_dma_handle, 0, 0, \ 2949d26e4fcSRobert Mustacchi (flag))) 2959d26e4fcSRobert Mustacchi #else /* !DEBUG */ 2969d26e4fcSRobert Mustacchi #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 2979d26e4fcSRobert Mustacchi (handle)->dmab_dma_handle, 0, 0, \ 2989d26e4fcSRobert Mustacchi (flag))) 2999d26e4fcSRobert Mustacchi #endif /* DEBUG */ 3009d26e4fcSRobert Mustacchi 3019d26e4fcSRobert Mustacchi /* 3029d26e4fcSRobert Mustacchi * Constants related to ring startup and teardown. These refer to the amount of 3039d26e4fcSRobert Mustacchi * time that we're willing to wait for a ring to spin up and spin down. 3049d26e4fcSRobert Mustacchi */ 3059d26e4fcSRobert Mustacchi #define I40E_RING_WAIT_NTRIES 10 3069d26e4fcSRobert Mustacchi #define I40E_RING_WAIT_PAUSE 10 /* ms */ 3079d26e4fcSRobert Mustacchi 3083d75a287SRobert Mustacchi /* 3093d75a287SRobert Mustacchi * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 3103d75a287SRobert Mustacchi */ 3113d75a287SRobert Mustacchi #define I40E_PBANUM_LENGTH 12 3123d75a287SRobert Mustacchi #define I40E_PBANUM_STRLEN 13 3133d75a287SRobert Mustacchi 3143d75a287SRobert Mustacchi /* 315b9d34b9dSRobert Mustacchi * Define the maximum number of queues for a traffic class. These values come 316b9d34b9dSRobert Mustacchi * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI 317b9d34b9dSRobert Mustacchi * Command Buffer' table. For the 710 controller family this is table 7-62 318b9d34b9dSRobert Mustacchi * (r2.5) and for the 722 this is table 38-216 (r2.0). 319b9d34b9dSRobert Mustacchi */ 320b9d34b9dSRobert Mustacchi #define I40E_710_MAX_TC_QUEUES 64 321b9d34b9dSRobert Mustacchi #define I40E_722_MAX_TC_QUEUES 128 322b9d34b9dSRobert Mustacchi 323b9d34b9dSRobert Mustacchi /* 324b9d34b9dSRobert Mustacchi * Define the size of the HLUT table size. The HLUT table can either be 128 or 325b9d34b9dSRobert Mustacchi * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start(). 326b9d34b9dSRobert Mustacchi * Note, this should not be confused with the common code's macro 327b9d34b9dSRobert Mustacchi * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to 328b9d34b9dSRobert Mustacchi * use a 512 byte HLUT. 3293d75a287SRobert Mustacchi */ 330b9d34b9dSRobert Mustacchi #define I40E_HLUT_TABLE_SIZE 512 3313d75a287SRobert Mustacchi 3329d26e4fcSRobert Mustacchi /* 3339d26e4fcSRobert Mustacchi * Bit flags for attach_progress 3349d26e4fcSRobert Mustacchi */ 3359d26e4fcSRobert Mustacchi typedef enum i40e_attach_state { 3369d26e4fcSRobert Mustacchi I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 3379d26e4fcSRobert Mustacchi I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 3389d26e4fcSRobert Mustacchi I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 3399d26e4fcSRobert Mustacchi I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 3409d26e4fcSRobert Mustacchi I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 3419d26e4fcSRobert Mustacchi I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 342508a0e8cSRob Johnston I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 3439d26e4fcSRobert Mustacchi I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 3449d26e4fcSRobert Mustacchi I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 3459d26e4fcSRobert Mustacchi I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 3469d26e4fcSRobert Mustacchi I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 3479d26e4fcSRobert Mustacchi I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 3489d26e4fcSRobert Mustacchi I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 349508a0e8cSRob Johnston I40E_ATTACH_UFM_INIT = 0x8000, /* DDI UFM initialized */ 3509d26e4fcSRobert Mustacchi } i40e_attach_state_t; 3519d26e4fcSRobert Mustacchi 3529d26e4fcSRobert Mustacchi 3539d26e4fcSRobert Mustacchi /* 3549d26e4fcSRobert Mustacchi * State flags that what's going on in in the device. Some of these state flags 3559d26e4fcSRobert Mustacchi * indicate some aspirational work that needs to happen in the driver. 3569d26e4fcSRobert Mustacchi * 3579d26e4fcSRobert Mustacchi * I40E_UNKNOWN: The device has yet to be started. 3589d26e4fcSRobert Mustacchi * I40E_INITIALIZED: The device has been fully attached. 3599d26e4fcSRobert Mustacchi * I40E_STARTED: The device has come out of the GLDV3 start routine. 3609d26e4fcSRobert Mustacchi * I40E_SUSPENDED: The device is suspended and I/O among other things 361508a0e8cSRob Johnston * should not occur. This happens because of an actual 362508a0e8cSRob Johnston * DDI_SUSPEND or interrupt adjustments. 3639d26e4fcSRobert Mustacchi * I40E_STALL: The tx stall detection logic has found a stall. 3649d26e4fcSRobert Mustacchi * I40E_OVERTEMP: The device has encountered a temperature alarm. 3659d26e4fcSRobert Mustacchi * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 366508a0e8cSRob Johnston * shouldn't be manipulating their state. 3679d26e4fcSRobert Mustacchi * I40E_ERROR: We've detected an FM error and degraded the device. 3689d26e4fcSRobert Mustacchi */ 3699d26e4fcSRobert Mustacchi typedef enum i40e_state { 3709d26e4fcSRobert Mustacchi I40E_UNKNOWN = 0x00, 3719d26e4fcSRobert Mustacchi I40E_INITIALIZED = 0x01, 3729d26e4fcSRobert Mustacchi I40E_STARTED = 0x02, 3739d26e4fcSRobert Mustacchi I40E_SUSPENDED = 0x04, 3749d26e4fcSRobert Mustacchi I40E_STALL = 0x08, 3759d26e4fcSRobert Mustacchi I40E_OVERTEMP = 0x20, 3769d26e4fcSRobert Mustacchi I40E_INTR_ADJUST = 0x40, 3779d26e4fcSRobert Mustacchi I40E_ERROR = 0x80 3789d26e4fcSRobert Mustacchi } i40e_state_t; 3799d26e4fcSRobert Mustacchi 3809d26e4fcSRobert Mustacchi 3819d26e4fcSRobert Mustacchi /* 3829d26e4fcSRobert Mustacchi * Definitions for common Intel things that we use and some slightly more usable 3839d26e4fcSRobert Mustacchi * names. 3849d26e4fcSRobert Mustacchi */ 3859d26e4fcSRobert Mustacchi typedef struct i40e_hw i40e_hw_t; 3869d26e4fcSRobert Mustacchi typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 3879d26e4fcSRobert Mustacchi 3889d26e4fcSRobert Mustacchi /* 3899d26e4fcSRobert Mustacchi * Handles and addresses of DMA buffers. 3909d26e4fcSRobert Mustacchi */ 3919d26e4fcSRobert Mustacchi typedef struct i40e_dma_buffer { 3929d26e4fcSRobert Mustacchi caddr_t dmab_address; /* Virtual address */ 3939d26e4fcSRobert Mustacchi uint64_t dmab_dma_address; /* DMA (Hardware) address */ 3949d26e4fcSRobert Mustacchi ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 3959d26e4fcSRobert Mustacchi ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 3969d26e4fcSRobert Mustacchi size_t dmab_size; /* Buffer size */ 3979d26e4fcSRobert Mustacchi size_t dmab_len; /* Data length in the buffer */ 3989d26e4fcSRobert Mustacchi } i40e_dma_buffer_t; 3999d26e4fcSRobert Mustacchi 4009d26e4fcSRobert Mustacchi /* 4019d26e4fcSRobert Mustacchi * RX Control Block 4029d26e4fcSRobert Mustacchi */ 4039d26e4fcSRobert Mustacchi typedef struct i40e_rx_control_block { 4049d26e4fcSRobert Mustacchi mblk_t *rcb_mp; 4059d26e4fcSRobert Mustacchi uint32_t rcb_ref; 4069d26e4fcSRobert Mustacchi i40e_dma_buffer_t rcb_dma; 4079d26e4fcSRobert Mustacchi frtn_t rcb_free_rtn; 4089d26e4fcSRobert Mustacchi struct i40e_rx_data *rcb_rxd; 4099d26e4fcSRobert Mustacchi } i40e_rx_control_block_t; 4109d26e4fcSRobert Mustacchi 4119d26e4fcSRobert Mustacchi typedef enum { 4129d26e4fcSRobert Mustacchi I40E_TX_NONE, 4139d26e4fcSRobert Mustacchi I40E_TX_COPY, 41409aee612SRyan Zezeski I40E_TX_DMA, 41509aee612SRyan Zezeski I40E_TX_DESC, 4169d26e4fcSRobert Mustacchi } i40e_tx_type_t; 4179d26e4fcSRobert Mustacchi 4189d26e4fcSRobert Mustacchi typedef struct i40e_tx_desc i40e_tx_desc_t; 41909aee612SRyan Zezeski typedef struct i40e_tx_context_desc i40e_tx_context_desc_t; 4209d26e4fcSRobert Mustacchi typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 4219d26e4fcSRobert Mustacchi 42209aee612SRyan Zezeski struct i40e_dma_bind_info { 42309aee612SRyan Zezeski caddr_t dbi_paddr; 42409aee612SRyan Zezeski size_t dbi_len; 42509aee612SRyan Zezeski }; 42609aee612SRyan Zezeski 4279d26e4fcSRobert Mustacchi typedef struct i40e_tx_control_block { 4289d26e4fcSRobert Mustacchi struct i40e_tx_control_block *tcb_next; 4299d26e4fcSRobert Mustacchi mblk_t *tcb_mp; 4309d26e4fcSRobert Mustacchi i40e_tx_type_t tcb_type; 4319d26e4fcSRobert Mustacchi ddi_dma_handle_t tcb_dma_handle; 43209aee612SRyan Zezeski ddi_dma_handle_t tcb_lso_dma_handle; 4339d26e4fcSRobert Mustacchi i40e_dma_buffer_t tcb_dma; 43409aee612SRyan Zezeski struct i40e_dma_bind_info *tcb_bind_info; 43509aee612SRyan Zezeski uint_t tcb_bind_ncookies; 43609aee612SRyan Zezeski boolean_t tcb_used_lso; 4379d26e4fcSRobert Mustacchi } i40e_tx_control_block_t; 4389d26e4fcSRobert Mustacchi 4399d26e4fcSRobert Mustacchi /* 4409d26e4fcSRobert Mustacchi * Receive ring data (used below). 4419d26e4fcSRobert Mustacchi */ 4429d26e4fcSRobert Mustacchi typedef struct i40e_rx_data { 4439d26e4fcSRobert Mustacchi struct i40e *rxd_i40e; 4449d26e4fcSRobert Mustacchi 4459d26e4fcSRobert Mustacchi /* 4469d26e4fcSRobert Mustacchi * RX descriptor ring definitions 4479d26e4fcSRobert Mustacchi */ 4489d26e4fcSRobert Mustacchi i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 4499d26e4fcSRobert Mustacchi i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 4509d26e4fcSRobert Mustacchi uint32_t rxd_desc_next; /* Index of next rx desc */ 4519d26e4fcSRobert Mustacchi 4529d26e4fcSRobert Mustacchi /* 4539d26e4fcSRobert Mustacchi * RX control block list definitions 4549d26e4fcSRobert Mustacchi */ 4559d26e4fcSRobert Mustacchi kmutex_t rxd_free_lock; /* Lock to protect free data */ 4569d26e4fcSRobert Mustacchi i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 4579d26e4fcSRobert Mustacchi i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 4589d26e4fcSRobert Mustacchi i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 4599d26e4fcSRobert Mustacchi uint32_t rxd_rcb_free; /* Number of free rcbs */ 4609d26e4fcSRobert Mustacchi 4619d26e4fcSRobert Mustacchi /* 4629d26e4fcSRobert Mustacchi * RX software ring settings 4639d26e4fcSRobert Mustacchi */ 4649d26e4fcSRobert Mustacchi uint32_t rxd_ring_size; /* Rx descriptor ring size */ 4659d26e4fcSRobert Mustacchi uint32_t rxd_free_list_size; /* Rx free list size */ 4669d26e4fcSRobert Mustacchi 4679d26e4fcSRobert Mustacchi /* 4689d26e4fcSRobert Mustacchi * RX outstanding data. This is used to keep track of outstanding loaned 4699d26e4fcSRobert Mustacchi * descriptors after we've shut down receiving information. Note these 4709d26e4fcSRobert Mustacchi * are protected by the i40e_t`i40e_rx_pending_lock. 4719d26e4fcSRobert Mustacchi */ 4729d26e4fcSRobert Mustacchi uint32_t rxd_rcb_pending; 4739d26e4fcSRobert Mustacchi boolean_t rxd_shutdown; 4749d26e4fcSRobert Mustacchi } i40e_rx_data_t; 4759d26e4fcSRobert Mustacchi 4769d26e4fcSRobert Mustacchi /* 4779d26e4fcSRobert Mustacchi * Structures for unicast and multicast addresses. Note that we keep the VSI id 4789d26e4fcSRobert Mustacchi * around for unicast addresses, since they may belong to different VSIs. 4799d26e4fcSRobert Mustacchi * However, since all multicast addresses belong to the default VSI, we don't 4809d26e4fcSRobert Mustacchi * duplicate that information. 4819d26e4fcSRobert Mustacchi */ 4829d26e4fcSRobert Mustacchi typedef struct i40e_uaddr { 4839d26e4fcSRobert Mustacchi uint8_t iua_mac[ETHERADDRL]; 4849d26e4fcSRobert Mustacchi int iua_vsi; 4859d26e4fcSRobert Mustacchi } i40e_uaddr_t; 4869d26e4fcSRobert Mustacchi 4879d26e4fcSRobert Mustacchi typedef struct i40e_maddr { 4889d26e4fcSRobert Mustacchi uint8_t ima_mac[ETHERADDRL]; 4899d26e4fcSRobert Mustacchi } i40e_maddr_t; 4909d26e4fcSRobert Mustacchi 4919d26e4fcSRobert Mustacchi /* 4929d26e4fcSRobert Mustacchi * Collection of RX statistics on a given queue. 4939d26e4fcSRobert Mustacchi */ 4949d26e4fcSRobert Mustacchi typedef struct i40e_rxq_stat { 4959d26e4fcSRobert Mustacchi /* 4969d26e4fcSRobert Mustacchi * The i40e hardware does not maintain statistics on a per-ring basis, 4979d26e4fcSRobert Mustacchi * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 4989d26e4fcSRobert Mustacchi * need to maintain our own stats for packets and bytes. 4999d26e4fcSRobert Mustacchi */ 5009d26e4fcSRobert Mustacchi kstat_named_t irxs_bytes; /* Bytes in on queue */ 5019d26e4fcSRobert Mustacchi kstat_named_t irxs_packets; /* Packets in on queue */ 5029d26e4fcSRobert Mustacchi 5039d26e4fcSRobert Mustacchi /* 5049d26e4fcSRobert Mustacchi * The following set of stats cover non-checksum data path issues. 5059d26e4fcSRobert Mustacchi */ 5069d26e4fcSRobert Mustacchi kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 5079d26e4fcSRobert Mustacchi kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 5089d26e4fcSRobert Mustacchi kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 5099d26e4fcSRobert Mustacchi kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 5109d26e4fcSRobert Mustacchi kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 5119d26e4fcSRobert Mustacchi 5129d26e4fcSRobert Mustacchi /* 5139d26e4fcSRobert Mustacchi * The following set of statistics covers rx checksum related activity. 5149d26e4fcSRobert Mustacchi * These are all primarily set in i40e_rx_hcksum. If rx checksum 5159d26e4fcSRobert Mustacchi * activity is disabled, then these should all be zero. 5169d26e4fcSRobert Mustacchi */ 5179d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 5189d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 5199d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 5209d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 5219d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 5229d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 5239d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 5249d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 5259d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_set; /* Total times we set cksum */ 5269d26e4fcSRobert Mustacchi kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 5279d26e4fcSRobert Mustacchi } i40e_rxq_stat_t; 5289d26e4fcSRobert Mustacchi 5299d26e4fcSRobert Mustacchi /* 5309d26e4fcSRobert Mustacchi * Collection of TX Statistics on a given queue 5319d26e4fcSRobert Mustacchi */ 5329d26e4fcSRobert Mustacchi typedef struct i40e_txq_stat { 5339d26e4fcSRobert Mustacchi kstat_named_t itxs_bytes; /* Bytes out on queue */ 5349d26e4fcSRobert Mustacchi kstat_named_t itxs_packets; /* Packets out on queue */ 5359d26e4fcSRobert Mustacchi kstat_named_t itxs_descriptors; /* Descriptors issued */ 5369d26e4fcSRobert Mustacchi kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 53709aee612SRyan Zezeski kstat_named_t itxs_force_copy; /* non-TSO force copy */ 53809aee612SRyan Zezeski kstat_named_t itxs_tso_force_copy; /* TSO force copy */ 5399d26e4fcSRobert Mustacchi /* 5409d26e4fcSRobert Mustacchi * Various failure conditions. 5419d26e4fcSRobert Mustacchi */ 5429d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_meoifail; /* ether offload failures */ 5439d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 5449d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 5459d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 5469d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 5479d26e4fcSRobert Mustacchi kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 54809aee612SRyan Zezeski kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */ 54909aee612SRyan Zezeski kstat_named_t itxs_bind_fails; /* DMA bind failures */ 55009aee612SRyan Zezeski kstat_named_t itxs_tx_short; /* Tx chain too short */ 5519d26e4fcSRobert Mustacchi 5529d26e4fcSRobert Mustacchi kstat_named_t itxs_err_notcb; /* No tcb's available */ 5539d26e4fcSRobert Mustacchi kstat_named_t itxs_err_nodescs; /* No tcb's available */ 5549d26e4fcSRobert Mustacchi kstat_named_t itxs_err_context; /* Total context failures */ 5559d26e4fcSRobert Mustacchi 5569d26e4fcSRobert Mustacchi kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 5579d26e4fcSRobert Mustacchi } i40e_txq_stat_t; 5589d26e4fcSRobert Mustacchi 5599d26e4fcSRobert Mustacchi /* 5609d26e4fcSRobert Mustacchi * An instance of an XL710 transmit/receive queue pair. This currently 5619d26e4fcSRobert Mustacchi * represents a combination of both a transmit and receive ring, though they 5629d26e4fcSRobert Mustacchi * should really be split apart into separate logical structures. Unfortunately, 5639d26e4fcSRobert Mustacchi * during initial work we mistakenly joined them together. 5649d26e4fcSRobert Mustacchi */ 5659d26e4fcSRobert Mustacchi typedef struct i40e_trqpair { 5669d26e4fcSRobert Mustacchi struct i40e *itrq_i40e; 5679d26e4fcSRobert Mustacchi 5689d26e4fcSRobert Mustacchi /* Receive-side structures. */ 5699d26e4fcSRobert Mustacchi kmutex_t itrq_rx_lock; 5709d26e4fcSRobert Mustacchi mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 5719d26e4fcSRobert Mustacchi i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 5729d26e4fcSRobert Mustacchi uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 5739d26e4fcSRobert Mustacchi uint32_t itrq_index; /* Queue index in the PF */ 5749d26e4fcSRobert Mustacchi uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 575396505afSPaul Winder boolean_t itrq_intr_poll; /* True when polling */ 5769d26e4fcSRobert Mustacchi 5779d26e4fcSRobert Mustacchi /* Receive-side stats. */ 5789d26e4fcSRobert Mustacchi i40e_rxq_stat_t itrq_rxstat; 5799d26e4fcSRobert Mustacchi kstat_t *itrq_rxkstat; 5809d26e4fcSRobert Mustacchi 5819d26e4fcSRobert Mustacchi /* Transmit-side structures. */ 5829d26e4fcSRobert Mustacchi kmutex_t itrq_tx_lock; 5839d26e4fcSRobert Mustacchi mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 5849d26e4fcSRobert Mustacchi uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 5859d26e4fcSRobert Mustacchi boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 5869d26e4fcSRobert Mustacchi 5879d26e4fcSRobert Mustacchi /* 5889d26e4fcSRobert Mustacchi * TX data sizing 5899d26e4fcSRobert Mustacchi */ 5909d26e4fcSRobert Mustacchi uint32_t itrq_tx_ring_size; 5919d26e4fcSRobert Mustacchi uint32_t itrq_tx_free_list_size; 5929d26e4fcSRobert Mustacchi 5939d26e4fcSRobert Mustacchi /* 5949d26e4fcSRobert Mustacchi * TX descriptor ring data 5959d26e4fcSRobert Mustacchi */ 5969d26e4fcSRobert Mustacchi i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 5979d26e4fcSRobert Mustacchi i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 598508a0e8cSRob Johnston volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 5999d26e4fcSRobert Mustacchi uint32_t itrq_desc_head; /* Last index hw freed */ 6009d26e4fcSRobert Mustacchi uint32_t itrq_desc_tail; /* Index of next free desc */ 6019d26e4fcSRobert Mustacchi uint32_t itrq_desc_free; /* Number of free descriptors */ 6029d26e4fcSRobert Mustacchi 6039d26e4fcSRobert Mustacchi /* 6049d26e4fcSRobert Mustacchi * TX control block (tcb) data 6059d26e4fcSRobert Mustacchi */ 6069d26e4fcSRobert Mustacchi kmutex_t itrq_tcb_lock; 6079d26e4fcSRobert Mustacchi i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 6089d26e4fcSRobert Mustacchi i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 6099d26e4fcSRobert Mustacchi i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 6109d26e4fcSRobert Mustacchi uint32_t itrq_tcb_free; /* Count of free tcb */ 6119d26e4fcSRobert Mustacchi 6129d26e4fcSRobert Mustacchi /* Transmit-side stats. */ 6139d26e4fcSRobert Mustacchi i40e_txq_stat_t itrq_txstat; 6149d26e4fcSRobert Mustacchi kstat_t *itrq_txkstat; 6159d26e4fcSRobert Mustacchi 6169d26e4fcSRobert Mustacchi } i40e_trqpair_t; 6179d26e4fcSRobert Mustacchi 6189d26e4fcSRobert Mustacchi /* 6199d26e4fcSRobert Mustacchi * VSI statistics. 6209d26e4fcSRobert Mustacchi * 6219d26e4fcSRobert Mustacchi * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 6229d26e4fcSRobert Mustacchi * Note that the stock statistic structure also includes entries for tx 6239d26e4fcSRobert Mustacchi * discards. However, this is not actually implemented for the VSI (see Table 6249d26e4fcSRobert Mustacchi * 7-221), hence why we don't include the member which would always have a value 6259d26e4fcSRobert Mustacchi * of zero. This choice was made to minimize confusion to someone looking at 6269d26e4fcSRobert Mustacchi * these, as a value of zero does not necessarily equate to the fact that it's 6279d26e4fcSRobert Mustacchi * not implemented. 6289d26e4fcSRobert Mustacchi */ 6299d26e4fcSRobert Mustacchi typedef struct i40e_vsi_stats { 6309d26e4fcSRobert Mustacchi uint64_t ivs_rx_bytes; /* gorc */ 6319d26e4fcSRobert Mustacchi uint64_t ivs_rx_unicast; /* uprc */ 6329d26e4fcSRobert Mustacchi uint64_t ivs_rx_multicast; /* mprc */ 6339d26e4fcSRobert Mustacchi uint64_t ivs_rx_broadcast; /* bprc */ 6349d26e4fcSRobert Mustacchi uint64_t ivs_rx_discards; /* rdpc */ 6359d26e4fcSRobert Mustacchi uint64_t ivs_rx_unknown_protocol; /* rupp */ 6369d26e4fcSRobert Mustacchi uint64_t ivs_tx_bytes; /* gotc */ 6379d26e4fcSRobert Mustacchi uint64_t ivs_tx_unicast; /* uptc */ 6389d26e4fcSRobert Mustacchi uint64_t ivs_tx_multicast; /* mptc */ 6399d26e4fcSRobert Mustacchi uint64_t ivs_tx_broadcast; /* bptc */ 6409d26e4fcSRobert Mustacchi uint64_t ivs_tx_errors; /* tepc */ 6419d26e4fcSRobert Mustacchi } i40e_vsi_stats_t; 6429d26e4fcSRobert Mustacchi 6439d26e4fcSRobert Mustacchi typedef struct i40e_vsi_kstats { 6449d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_bytes; 6459d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_unicast; 6469d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_multicast; 6479d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_broadcast; 6489d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_discards; 6499d26e4fcSRobert Mustacchi kstat_named_t ivk_rx_unknown_protocol; 6509d26e4fcSRobert Mustacchi kstat_named_t ivk_tx_bytes; 6519d26e4fcSRobert Mustacchi kstat_named_t ivk_tx_unicast; 6529d26e4fcSRobert Mustacchi kstat_named_t ivk_tx_multicast; 6539d26e4fcSRobert Mustacchi kstat_named_t ivk_tx_broadcast; 6549d26e4fcSRobert Mustacchi kstat_named_t ivk_tx_errors; 6559d26e4fcSRobert Mustacchi } i40e_vsi_kstats_t; 6569d26e4fcSRobert Mustacchi 6579d26e4fcSRobert Mustacchi /* 6589d26e4fcSRobert Mustacchi * For pf statistics, we opt not to use the standard statistics as defined by 6599d26e4fcSRobert Mustacchi * the Intel common code. This also currently combines statistics that are 6609d26e4fcSRobert Mustacchi * global across the entire device. 6619d26e4fcSRobert Mustacchi */ 6629d26e4fcSRobert Mustacchi typedef struct i40e_pf_stats { 6639d26e4fcSRobert Mustacchi uint64_t ips_rx_bytes; /* gorc */ 6649d26e4fcSRobert Mustacchi uint64_t ips_rx_unicast; /* uprc */ 6659d26e4fcSRobert Mustacchi uint64_t ips_rx_multicast; /* mprc */ 6669d26e4fcSRobert Mustacchi uint64_t ips_rx_broadcast; /* bprc */ 6679d26e4fcSRobert Mustacchi uint64_t ips_tx_bytes; /* gotc */ 6689d26e4fcSRobert Mustacchi uint64_t ips_tx_unicast; /* uptc */ 6699d26e4fcSRobert Mustacchi uint64_t ips_tx_multicast; /* mptc */ 6709d26e4fcSRobert Mustacchi uint64_t ips_tx_broadcast; /* bptc */ 6719d26e4fcSRobert Mustacchi 6729d26e4fcSRobert Mustacchi uint64_t ips_rx_size_64; /* prc64 */ 6739d26e4fcSRobert Mustacchi uint64_t ips_rx_size_127; /* prc127 */ 6749d26e4fcSRobert Mustacchi uint64_t ips_rx_size_255; /* prc255 */ 6759d26e4fcSRobert Mustacchi uint64_t ips_rx_size_511; /* prc511 */ 6769d26e4fcSRobert Mustacchi uint64_t ips_rx_size_1023; /* prc1023 */ 6779d26e4fcSRobert Mustacchi uint64_t ips_rx_size_1522; /* prc1522 */ 6789d26e4fcSRobert Mustacchi uint64_t ips_rx_size_9522; /* prc9522 */ 6799d26e4fcSRobert Mustacchi 6809d26e4fcSRobert Mustacchi uint64_t ips_tx_size_64; /* ptc64 */ 6819d26e4fcSRobert Mustacchi uint64_t ips_tx_size_127; /* ptc127 */ 6829d26e4fcSRobert Mustacchi uint64_t ips_tx_size_255; /* ptc255 */ 6839d26e4fcSRobert Mustacchi uint64_t ips_tx_size_511; /* ptc511 */ 6849d26e4fcSRobert Mustacchi uint64_t ips_tx_size_1023; /* ptc1023 */ 6859d26e4fcSRobert Mustacchi uint64_t ips_tx_size_1522; /* ptc1522 */ 6869d26e4fcSRobert Mustacchi uint64_t ips_tx_size_9522; /* ptc9522 */ 6879d26e4fcSRobert Mustacchi 6889d26e4fcSRobert Mustacchi uint64_t ips_link_xon_rx; /* lxonrxc */ 6899d26e4fcSRobert Mustacchi uint64_t ips_link_xoff_rx; /* lxoffrxc */ 6909d26e4fcSRobert Mustacchi uint64_t ips_link_xon_tx; /* lxontxc */ 6919d26e4fcSRobert Mustacchi uint64_t ips_link_xoff_tx; /* lxofftxc */ 6929d26e4fcSRobert Mustacchi uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 6939d26e4fcSRobert Mustacchi uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 6949d26e4fcSRobert Mustacchi uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 6959d26e4fcSRobert Mustacchi uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 6969d26e4fcSRobert Mustacchi uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 6979d26e4fcSRobert Mustacchi 6989d26e4fcSRobert Mustacchi uint64_t ips_crc_errors; /* crcerrs */ 6999d26e4fcSRobert Mustacchi uint64_t ips_illegal_bytes; /* illerrc */ 7009d26e4fcSRobert Mustacchi uint64_t ips_mac_local_faults; /* mlfc */ 7019d26e4fcSRobert Mustacchi uint64_t ips_mac_remote_faults; /* mrfc */ 7029d26e4fcSRobert Mustacchi uint64_t ips_rx_length_errors; /* rlec */ 7039d26e4fcSRobert Mustacchi uint64_t ips_rx_undersize; /* ruc */ 7049d26e4fcSRobert Mustacchi uint64_t ips_rx_fragments; /* rfc */ 7059d26e4fcSRobert Mustacchi uint64_t ips_rx_oversize; /* roc */ 7069d26e4fcSRobert Mustacchi uint64_t ips_rx_jabber; /* rjc */ 7079d26e4fcSRobert Mustacchi uint64_t ips_rx_discards; /* rdpc */ 7089d26e4fcSRobert Mustacchi uint64_t ips_rx_vm_discards; /* ldpc */ 7099d26e4fcSRobert Mustacchi uint64_t ips_rx_short_discards; /* mspdc */ 7109d26e4fcSRobert Mustacchi uint64_t ips_tx_dropped_link_down; /* tdold */ 7119d26e4fcSRobert Mustacchi uint64_t ips_rx_unknown_protocol; /* rupp */ 7129d26e4fcSRobert Mustacchi uint64_t ips_rx_err1; /* rxerr1 */ 7139d26e4fcSRobert Mustacchi uint64_t ips_rx_err2; /* rxerr2 */ 7149d26e4fcSRobert Mustacchi } i40e_pf_stats_t; 7159d26e4fcSRobert Mustacchi 7169d26e4fcSRobert Mustacchi typedef struct i40e_pf_kstats { 7179d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_bytes; /* gorc */ 7189d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_unicast; /* uprc */ 7199d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_multicast; /* mprc */ 7209d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_broadcast; /* bprc */ 7219d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_bytes; /* gotc */ 7229d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_unicast; /* uptc */ 7239d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_multicast; /* mptc */ 7249d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_broadcast; /* bptc */ 7259d26e4fcSRobert Mustacchi 7269d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_64; /* prc64 */ 7279d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_127; /* prc127 */ 7289d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_255; /* prc255 */ 7299d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_511; /* prc511 */ 7309d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_1023; /* prc1023 */ 7319d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_1522; /* prc1522 */ 7329d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_size_9522; /* prc9522 */ 7339d26e4fcSRobert Mustacchi 7349d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_64; /* ptc64 */ 7359d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_127; /* ptc127 */ 7369d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_255; /* ptc255 */ 7379d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_511; /* ptc511 */ 7389d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 7399d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 7409d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 7419d26e4fcSRobert Mustacchi 7429d26e4fcSRobert Mustacchi kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 7439d26e4fcSRobert Mustacchi kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 7449d26e4fcSRobert Mustacchi kstat_named_t ipk_link_xon_tx; /* lxontxc */ 7459d26e4fcSRobert Mustacchi kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 7469d26e4fcSRobert Mustacchi kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 7479d26e4fcSRobert Mustacchi kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 7489d26e4fcSRobert Mustacchi kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 7499d26e4fcSRobert Mustacchi kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 7509d26e4fcSRobert Mustacchi kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 7519d26e4fcSRobert Mustacchi 7529d26e4fcSRobert Mustacchi kstat_named_t ipk_crc_errors; /* crcerrs */ 7539d26e4fcSRobert Mustacchi kstat_named_t ipk_illegal_bytes; /* illerrc */ 7549d26e4fcSRobert Mustacchi kstat_named_t ipk_mac_local_faults; /* mlfc */ 7559d26e4fcSRobert Mustacchi kstat_named_t ipk_mac_remote_faults; /* mrfc */ 7569d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_length_errors; /* rlec */ 7579d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_undersize; /* ruc */ 7589d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_fragments; /* rfc */ 7599d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_oversize; /* roc */ 7609d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_jabber; /* rjc */ 7619d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_discards; /* rdpc */ 7629d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_vm_discards; /* ldpc */ 7639d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_short_discards; /* mspdc */ 7649d26e4fcSRobert Mustacchi kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 7659d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 7669d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_err1; /* rxerr1 */ 7679d26e4fcSRobert Mustacchi kstat_named_t ipk_rx_err2; /* rxerr2 */ 7689d26e4fcSRobert Mustacchi } i40e_pf_kstats_t; 7699d26e4fcSRobert Mustacchi 7709d26e4fcSRobert Mustacchi /* 7719d26e4fcSRobert Mustacchi * Resources that are pooled and specific to a given i40e_t. 7729d26e4fcSRobert Mustacchi */ 7739d26e4fcSRobert Mustacchi typedef struct i40e_func_rsrc { 7749d26e4fcSRobert Mustacchi uint_t ifr_nrx_queue; 7759d26e4fcSRobert Mustacchi uint_t ifr_nrx_queue_used; 7769d26e4fcSRobert Mustacchi uint_t ifr_ntx_queue; 7779d26e4fcSRobert Mustacchi uint_t ifr_trx_queue_used; 7789d26e4fcSRobert Mustacchi uint_t ifr_nvsis; 7799d26e4fcSRobert Mustacchi uint_t ifr_nvsis_used; 7809d26e4fcSRobert Mustacchi uint_t ifr_nmacfilt; 7819d26e4fcSRobert Mustacchi uint_t ifr_nmacfilt_used; 7829d26e4fcSRobert Mustacchi uint_t ifr_nmcastfilt; 7839d26e4fcSRobert Mustacchi uint_t ifr_nmcastfilt_used; 7849d26e4fcSRobert Mustacchi } i40e_func_rsrc_t; 7859d26e4fcSRobert Mustacchi 78609aee612SRyan Zezeski typedef struct i40e_vsi { 78709aee612SRyan Zezeski uint16_t iv_seid; 78809aee612SRyan Zezeski uint16_t iv_number; 78909aee612SRyan Zezeski kstat_t *iv_kstats; 79009aee612SRyan Zezeski i40e_vsi_stats_t iv_stats; 79109aee612SRyan Zezeski uint16_t iv_stats_id; 79209aee612SRyan Zezeski } i40e_vsi_t; 79309aee612SRyan Zezeski 79409aee612SRyan Zezeski /* 79509aee612SRyan Zezeski * While irg_index and irg_grp_hdl aren't used anywhere, they are 79609aee612SRyan Zezeski * still useful for debugging. 79709aee612SRyan Zezeski */ 79809aee612SRyan Zezeski typedef struct i40e_rx_group { 79909aee612SRyan Zezeski uint32_t irg_index; /* index in i40e_rx_groups[] */ 80009aee612SRyan Zezeski uint16_t irg_vsi_seid; /* SEID of VSI for this group */ 80109aee612SRyan Zezeski mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */ 80209aee612SRyan Zezeski struct i40e *irg_i40e; /* ref to i40e_t */ 80309aee612SRyan Zezeski } i40e_rx_group_t; 80409aee612SRyan Zezeski 8059d26e4fcSRobert Mustacchi /* 8069d26e4fcSRobert Mustacchi * Main i40e per-instance state. 8079d26e4fcSRobert Mustacchi */ 8089d26e4fcSRobert Mustacchi typedef struct i40e { 8099d26e4fcSRobert Mustacchi list_node_t i40e_glink; /* Global list link */ 8109d26e4fcSRobert Mustacchi list_node_t i40e_dlink; /* Device list link */ 8119d26e4fcSRobert Mustacchi kmutex_t i40e_general_lock; /* General device lock */ 8129d26e4fcSRobert Mustacchi 8139d26e4fcSRobert Mustacchi /* 8149d26e4fcSRobert Mustacchi * General Data and management 8159d26e4fcSRobert Mustacchi */ 8169d26e4fcSRobert Mustacchi dev_info_t *i40e_dip; 8179d26e4fcSRobert Mustacchi int i40e_instance; 8189d26e4fcSRobert Mustacchi int i40e_fm_capabilities; 8199d26e4fcSRobert Mustacchi uint_t i40e_state; 8209d26e4fcSRobert Mustacchi i40e_attach_state_t i40e_attach_progress; 8219d26e4fcSRobert Mustacchi mac_handle_t i40e_mac_hdl; 8229d26e4fcSRobert Mustacchi ddi_periodic_t i40e_periodic_id; 8239d26e4fcSRobert Mustacchi 8249d26e4fcSRobert Mustacchi /* 8259d26e4fcSRobert Mustacchi * Pointers to common code data structures and memory for the common 8269d26e4fcSRobert Mustacchi * code. 8279d26e4fcSRobert Mustacchi */ 8289d26e4fcSRobert Mustacchi struct i40e_hw i40e_hw_space; 8299d26e4fcSRobert Mustacchi struct i40e_osdep i40e_osdep_space; 8309d26e4fcSRobert Mustacchi struct i40e_aq_get_phy_abilities_resp i40e_phy; 831508a0e8cSRob Johnston void *i40e_aqbuf; 8329d26e4fcSRobert Mustacchi 83309aee612SRyan Zezeski #define I40E_DEF_VSI_IDX 0 83409aee612SRyan Zezeski #define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX]) 83509aee612SRyan Zezeski #define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid) 83609aee612SRyan Zezeski 8379d26e4fcSRobert Mustacchi /* 8389d26e4fcSRobert Mustacchi * Device state, switch information, and resources. 8399d26e4fcSRobert Mustacchi */ 840*88628b1bSRyan Zezeski i40e_vsi_t i40e_vsis[I40E_MAX_NUM_RX_GROUPS]; 84109aee612SRyan Zezeski uint16_t i40e_mac_seid; /* SEID of physical MAC */ 84209aee612SRyan Zezeski uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */ 84309aee612SRyan Zezeski uint16_t i40e_vsi_avail; /* VSIs avail to this PF */ 84409aee612SRyan Zezeski uint16_t i40e_vsi_used; /* VSIs used by this PF */ 8459d26e4fcSRobert Mustacchi struct i40e_device *i40e_device; 8469d26e4fcSRobert Mustacchi i40e_func_rsrc_t i40e_resources; 8479d26e4fcSRobert Mustacchi uint16_t i40e_switch_rsrc_alloc; 8489d26e4fcSRobert Mustacchi uint16_t i40e_switch_rsrc_actual; 8499d26e4fcSRobert Mustacchi i40e_switch_rsrc_t *i40e_switch_rsrcs; 8509d26e4fcSRobert Mustacchi i40e_uaddr_t *i40e_uaddrs; 8519d26e4fcSRobert Mustacchi i40e_maddr_t *i40e_maddrs; 8529d26e4fcSRobert Mustacchi int i40e_mcast_promisc_count; 8539d26e4fcSRobert Mustacchi boolean_t i40e_promisc_on; 8549d26e4fcSRobert Mustacchi link_state_t i40e_link_state; 8559d26e4fcSRobert Mustacchi uint32_t i40e_link_speed; /* In Mbps */ 8569d26e4fcSRobert Mustacchi link_duplex_t i40e_link_duplex; 8579d26e4fcSRobert Mustacchi uint_t i40e_sdu; 8589d26e4fcSRobert Mustacchi uint_t i40e_frame_max; 8599d26e4fcSRobert Mustacchi 8609d26e4fcSRobert Mustacchi /* 8619d26e4fcSRobert Mustacchi * Transmit and receive information, tunables, and MAC info. 8629d26e4fcSRobert Mustacchi */ 8639d26e4fcSRobert Mustacchi i40e_trqpair_t *i40e_trqpairs; 864508a0e8cSRob Johnston boolean_t i40e_mr_enable; 86509aee612SRyan Zezeski uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */ 86609aee612SRyan Zezeski uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */ 8679d26e4fcSRobert Mustacchi uint_t i40e_other_itr; 8689d26e4fcSRobert Mustacchi 86909aee612SRyan Zezeski i40e_rx_group_t *i40e_rx_groups; 87009aee612SRyan Zezeski uint_t i40e_num_rx_groups; 8719d26e4fcSRobert Mustacchi int i40e_num_rx_descs; 8729d26e4fcSRobert Mustacchi uint32_t i40e_rx_ring_size; 8739d26e4fcSRobert Mustacchi uint32_t i40e_rx_buf_size; 8749d26e4fcSRobert Mustacchi boolean_t i40e_rx_hcksum_enable; 8759d26e4fcSRobert Mustacchi uint32_t i40e_rx_dma_min; 8769d26e4fcSRobert Mustacchi uint32_t i40e_rx_limit_per_intr; 8779d26e4fcSRobert Mustacchi uint_t i40e_rx_itr; 8789d26e4fcSRobert Mustacchi 8799d26e4fcSRobert Mustacchi int i40e_num_tx_descs; 8809d26e4fcSRobert Mustacchi uint32_t i40e_tx_ring_size; 8819d26e4fcSRobert Mustacchi uint32_t i40e_tx_buf_size; 8829d26e4fcSRobert Mustacchi uint32_t i40e_tx_block_thresh; 8839d26e4fcSRobert Mustacchi boolean_t i40e_tx_hcksum_enable; 88409aee612SRyan Zezeski boolean_t i40e_tx_lso_enable; 8859d26e4fcSRobert Mustacchi uint32_t i40e_tx_dma_min; 8869d26e4fcSRobert Mustacchi uint_t i40e_tx_itr; 8879d26e4fcSRobert Mustacchi 8889d26e4fcSRobert Mustacchi /* 8899d26e4fcSRobert Mustacchi * Interrupt state 8909d26e4fcSRobert Mustacchi */ 8919d26e4fcSRobert Mustacchi uint_t i40e_intr_pri; 8929d26e4fcSRobert Mustacchi uint_t i40e_intr_force; 8939d26e4fcSRobert Mustacchi uint_t i40e_intr_type; 8949d26e4fcSRobert Mustacchi int i40e_intr_cap; 8959d26e4fcSRobert Mustacchi uint32_t i40e_intr_count; 8969d26e4fcSRobert Mustacchi uint32_t i40e_intr_count_max; 8979d26e4fcSRobert Mustacchi uint32_t i40e_intr_count_min; 8989d26e4fcSRobert Mustacchi size_t i40e_intr_size; 8999d26e4fcSRobert Mustacchi ddi_intr_handle_t *i40e_intr_handles; 9009d26e4fcSRobert Mustacchi ddi_cb_handle_t i40e_callback_handle; 9019d26e4fcSRobert Mustacchi 9029d26e4fcSRobert Mustacchi /* 9039d26e4fcSRobert Mustacchi * DMA attributes. See i40e_transceiver.c for why we have copies of them 9049d26e4fcSRobert Mustacchi * in the i40e_t. 9059d26e4fcSRobert Mustacchi */ 9069d26e4fcSRobert Mustacchi ddi_dma_attr_t i40e_static_dma_attr; 9079d26e4fcSRobert Mustacchi ddi_dma_attr_t i40e_txbind_dma_attr; 90809aee612SRyan Zezeski ddi_dma_attr_t i40e_txbind_lso_dma_attr; 9099d26e4fcSRobert Mustacchi ddi_device_acc_attr_t i40e_desc_acc_attr; 9109d26e4fcSRobert Mustacchi ddi_device_acc_attr_t i40e_buf_acc_attr; 9119d26e4fcSRobert Mustacchi 9129d26e4fcSRobert Mustacchi /* 9139d26e4fcSRobert Mustacchi * The following two fields are used to protect and keep track of 9149d26e4fcSRobert Mustacchi * outstanding, loaned buffers to MAC. If we have these, we can't 9159d26e4fcSRobert Mustacchi * detach as we have active DMA memory outstanding. 9169d26e4fcSRobert Mustacchi */ 9179d26e4fcSRobert Mustacchi kmutex_t i40e_rx_pending_lock; 9189d26e4fcSRobert Mustacchi kcondvar_t i40e_rx_pending_cv; 9199d26e4fcSRobert Mustacchi uint32_t i40e_rx_pending; 9209d26e4fcSRobert Mustacchi 9219d26e4fcSRobert Mustacchi /* 9229d26e4fcSRobert Mustacchi * PF statistics and VSI statistics. 9239d26e4fcSRobert Mustacchi */ 9249d26e4fcSRobert Mustacchi kmutex_t i40e_stat_lock; 9259d26e4fcSRobert Mustacchi kstat_t *i40e_pf_kstat; 9269d26e4fcSRobert Mustacchi i40e_pf_stats_t i40e_pf_stat; 9279d26e4fcSRobert Mustacchi 9289d26e4fcSRobert Mustacchi /* 9299d26e4fcSRobert Mustacchi * Misc. stats and counters that should maybe one day be kstats. 9309d26e4fcSRobert Mustacchi */ 9319d26e4fcSRobert Mustacchi uint64_t i40e_s_link_status_errs; 9329d26e4fcSRobert Mustacchi uint32_t i40e_s_link_status_lasterr; 933c1e9c696SRobert Mustacchi 934c1e9c696SRobert Mustacchi /* 935c1e9c696SRobert Mustacchi * LED information. Note this state is only modified in 936c1e9c696SRobert Mustacchi * i40e_gld_set_led() which is protected by MAC's serializer lock. 937c1e9c696SRobert Mustacchi */ 938c1e9c696SRobert Mustacchi uint32_t i40e_led_status; 939c1e9c696SRobert Mustacchi boolean_t i40e_led_saved; 940508a0e8cSRob Johnston 941508a0e8cSRob Johnston /* DDI UFM handle */ 942508a0e8cSRob Johnston ddi_ufm_handle_t *i40e_ufmh; 9439d26e4fcSRobert Mustacchi } i40e_t; 9449d26e4fcSRobert Mustacchi 9459d26e4fcSRobert Mustacchi /* 9469d26e4fcSRobert Mustacchi * The i40e_device represents a PCI device which encapsulates multiple physical 9479d26e4fcSRobert Mustacchi * functions which are represented as an i40e_t. This is used to track the use 9489d26e4fcSRobert Mustacchi * of pooled resources throughout all of the various devices. 9499d26e4fcSRobert Mustacchi */ 9509d26e4fcSRobert Mustacchi typedef struct i40e_device { 9519d26e4fcSRobert Mustacchi list_node_t id_link; 9529d26e4fcSRobert Mustacchi dev_info_t *id_parent; 9539d26e4fcSRobert Mustacchi uint_t id_pci_bus; 9549d26e4fcSRobert Mustacchi uint_t id_pci_device; 9559d26e4fcSRobert Mustacchi uint_t id_nfuncs; /* Total number of functions */ 9569d26e4fcSRobert Mustacchi uint_t id_nreg; /* Total number present */ 9579d26e4fcSRobert Mustacchi list_t id_i40e_list; /* List of i40e_t's registered */ 9589d26e4fcSRobert Mustacchi i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 9599d26e4fcSRobert Mustacchi uint_t id_rsrcs_alloc; /* Total allocated resources */ 9609d26e4fcSRobert Mustacchi uint_t id_rsrcs_act; /* Actual number of resources */ 9619d26e4fcSRobert Mustacchi } i40e_device_t; 9629d26e4fcSRobert Mustacchi 9639d26e4fcSRobert Mustacchi /* Values for the interrupt forcing on the NIC. */ 9649d26e4fcSRobert Mustacchi #define I40E_INTR_NONE 0 9659d26e4fcSRobert Mustacchi #define I40E_INTR_MSIX 1 9669d26e4fcSRobert Mustacchi #define I40E_INTR_MSI 2 9679d26e4fcSRobert Mustacchi #define I40E_INTR_LEGACY 3 9689d26e4fcSRobert Mustacchi 9699d26e4fcSRobert Mustacchi /* Hint that we don't want to do any polling... */ 9709d26e4fcSRobert Mustacchi #define I40E_POLL_NULL -1 9719d26e4fcSRobert Mustacchi 9729d26e4fcSRobert Mustacchi /* 9739d26e4fcSRobert Mustacchi * Logging functions. 9749d26e4fcSRobert Mustacchi */ 9759d26e4fcSRobert Mustacchi /*PRINTFLIKE2*/ 9769d26e4fcSRobert Mustacchi extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 9779d26e4fcSRobert Mustacchi /*PRINTFLIKE2*/ 9789d26e4fcSRobert Mustacchi extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 9799d26e4fcSRobert Mustacchi /*PRINTFLIKE2*/ 9809d26e4fcSRobert Mustacchi extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 9819d26e4fcSRobert Mustacchi 9829d26e4fcSRobert Mustacchi /* 9839d26e4fcSRobert Mustacchi * General link handling functions. 9849d26e4fcSRobert Mustacchi */ 9859d26e4fcSRobert Mustacchi extern void i40e_link_check(i40e_t *); 9869d26e4fcSRobert Mustacchi extern void i40e_update_mtu(i40e_t *); 9879d26e4fcSRobert Mustacchi 9889d26e4fcSRobert Mustacchi /* 9899d26e4fcSRobert Mustacchi * FMA functions. 9909d26e4fcSRobert Mustacchi */ 9919d26e4fcSRobert Mustacchi extern int i40e_check_acc_handle(ddi_acc_handle_t); 9929d26e4fcSRobert Mustacchi extern int i40e_check_dma_handle(ddi_dma_handle_t); 9939d26e4fcSRobert Mustacchi extern void i40e_fm_ereport(i40e_t *, char *); 9949d26e4fcSRobert Mustacchi 9959d26e4fcSRobert Mustacchi /* 9969d26e4fcSRobert Mustacchi * Interrupt handlers and interrupt handler setup. 9979d26e4fcSRobert Mustacchi */ 9989d26e4fcSRobert Mustacchi extern void i40e_intr_chip_init(i40e_t *); 9999d26e4fcSRobert Mustacchi extern void i40e_intr_chip_fini(i40e_t *); 10009d26e4fcSRobert Mustacchi extern uint_t i40e_intr_msix(void *, void *); 10019d26e4fcSRobert Mustacchi extern uint_t i40e_intr_msi(void *, void *); 10029d26e4fcSRobert Mustacchi extern uint_t i40e_intr_legacy(void *, void *); 10039d26e4fcSRobert Mustacchi extern void i40e_intr_io_enable_all(i40e_t *); 10049d26e4fcSRobert Mustacchi extern void i40e_intr_io_disable_all(i40e_t *); 10059d26e4fcSRobert Mustacchi extern void i40e_intr_io_clear_cause(i40e_t *); 1006338749cbSRobert Mustacchi extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 1007338749cbSRobert Mustacchi extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 10089d26e4fcSRobert Mustacchi extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 10099d26e4fcSRobert Mustacchi 10109d26e4fcSRobert Mustacchi /* 10119d26e4fcSRobert Mustacchi * Receive-side functions 10129d26e4fcSRobert Mustacchi */ 10139d26e4fcSRobert Mustacchi extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 10149d26e4fcSRobert Mustacchi extern mblk_t *i40e_ring_rx_poll(void *, int); 10159d26e4fcSRobert Mustacchi extern void i40e_rx_recycle(caddr_t); 10169d26e4fcSRobert Mustacchi 10179d26e4fcSRobert Mustacchi /* 10189d26e4fcSRobert Mustacchi * Transmit-side functions 10199d26e4fcSRobert Mustacchi */ 10209d26e4fcSRobert Mustacchi mblk_t *i40e_ring_tx(void *, mblk_t *); 10219d26e4fcSRobert Mustacchi extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 10229d26e4fcSRobert Mustacchi extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 10239d26e4fcSRobert Mustacchi 10249d26e4fcSRobert Mustacchi /* 10259d26e4fcSRobert Mustacchi * Statistics functions. 10269d26e4fcSRobert Mustacchi */ 10279d26e4fcSRobert Mustacchi extern boolean_t i40e_stats_init(i40e_t *); 10289d26e4fcSRobert Mustacchi extern void i40e_stats_fini(i40e_t *); 102909aee612SRyan Zezeski extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t); 103009aee612SRyan Zezeski extern void i40e_stat_vsi_fini(i40e_t *, uint_t); 10319d26e4fcSRobert Mustacchi extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 10329d26e4fcSRobert Mustacchi extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 10339d26e4fcSRobert Mustacchi extern int i40e_m_stat(void *, uint_t, uint64_t *); 10349d26e4fcSRobert Mustacchi extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 10359d26e4fcSRobert Mustacchi extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 10369d26e4fcSRobert Mustacchi 10379d26e4fcSRobert Mustacchi /* 10389d26e4fcSRobert Mustacchi * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 10399d26e4fcSRobert Mustacchi */ 10409d26e4fcSRobert Mustacchi extern boolean_t i40e_register_mac(i40e_t *); 10419d26e4fcSRobert Mustacchi extern boolean_t i40e_start(i40e_t *, boolean_t); 10429d26e4fcSRobert Mustacchi extern void i40e_stop(i40e_t *, boolean_t); 10439d26e4fcSRobert Mustacchi 10449d26e4fcSRobert Mustacchi /* 10459d26e4fcSRobert Mustacchi * DMA & buffer functions and attributes 10469d26e4fcSRobert Mustacchi */ 10479d26e4fcSRobert Mustacchi extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 10489d26e4fcSRobert Mustacchi extern boolean_t i40e_alloc_ring_mem(i40e_t *); 10499d26e4fcSRobert Mustacchi extern void i40e_free_ring_mem(i40e_t *, boolean_t); 10509d26e4fcSRobert Mustacchi 10519d26e4fcSRobert Mustacchi #ifdef __cplusplus 10529d26e4fcSRobert Mustacchi } 10539d26e4fcSRobert Mustacchi #endif 10549d26e4fcSRobert Mustacchi 10559d26e4fcSRobert Mustacchi #endif /* _I40E_SW_H */ 1056