1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: head/sys/dev/ixl/i40e_type.h 284049 2015-06-05 22:52:42Z jfv $*/ 34 35 #ifndef _I40E_TYPE_H_ 36 #define _I40E_TYPE_H_ 37 38 #include "i40e_status.h" 39 #include "i40e_osdep.h" 40 #include "i40e_register.h" 41 #include "i40e_adminq.h" 42 #include "i40e_hmc.h" 43 #include "i40e_lan_hmc.h" 44 #include "i40e_devids.h" 45 46 #define UNREFERENCED_XPARAMETER 47 48 #define BIT(a) (1UL << (a)) 49 #define BIT_ULL(a) (1ULL << (a)) 50 51 #ifndef I40E_MASK 52 /* I40E_MASK is a macro used on 32 bit registers */ 53 #define I40E_MASK(mask, shift) (((uint32_t)(mask)) << ((uint32_t)(shift))) 54 #endif 55 56 #define I40E_MAX_PF 16 57 #define I40E_MAX_PF_VSI 64 58 #define I40E_MAX_PF_QP 128 59 #define I40E_MAX_VSI_QP 16 60 #define I40E_MAX_VF_VSI 3 61 #define I40E_MAX_CHAINED_RX_BUFFERS 5 62 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 63 64 /* something less than 1 minute */ 65 #define I40E_HEARTBEAT_TIMEOUT (HZ * 50) 66 67 /* Max default timeout in ms, */ 68 #define I40E_MAX_NVM_TIMEOUT 18000 69 70 /* Check whether address is multicast. */ 71 #define I40E_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 72 73 /* Check whether an address is broadcast. */ 74 #define I40E_IS_BROADCAST(address) \ 75 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 76 (((u8 *)(address))[1] == ((u8)0xff))) 77 78 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */ 79 #define I40E_MS_TO_GTIME(time) ((time) * 1000) 80 81 /* forward declaration */ 82 struct i40e_hw; 83 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *); 84 85 #define I40E_ETH_LENGTH_OF_ADDRESS 6 86 /* Data type manipulation macros. */ 87 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 88 #define I40E_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 89 90 #define I40E_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 91 #define I40E_LO_WORD(x) ((u16)((x) & 0xFFFF)) 92 93 #define I40E_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 94 #define I40E_LO_BYTE(x) ((u8)((x) & 0xFF)) 95 96 /* Number of Transmit Descriptors must be a multiple of 8. */ 97 #define I40E_REQ_TX_DESCRIPTOR_MULTIPLE 8 98 /* Number of Receive Descriptors must be a multiple of 32 if 99 * the number of descriptors is greater than 32. 100 */ 101 #define I40E_REQ_RX_DESCRIPTOR_MULTIPLE 32 102 103 #define I40E_DESC_UNUSED(R) \ 104 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 105 (R)->next_to_clean - (R)->next_to_use - 1) 106 107 /* bitfields for Tx queue mapping in QTX_CTL */ 108 #define I40E_QTX_CTL_VF_QUEUE 0x0 109 #define I40E_QTX_CTL_VM_QUEUE 0x1 110 #define I40E_QTX_CTL_PF_QUEUE 0x2 111 112 /* debug masks - set these bits in hw->debug_mask to control output */ 113 enum i40e_debug_mask { 114 I40E_DEBUG_INIT = 0x00000001, 115 I40E_DEBUG_RELEASE = 0x00000002, 116 117 I40E_DEBUG_LINK = 0x00000010, 118 I40E_DEBUG_PHY = 0x00000020, 119 I40E_DEBUG_HMC = 0x00000040, 120 I40E_DEBUG_NVM = 0x00000080, 121 I40E_DEBUG_LAN = 0x00000100, 122 I40E_DEBUG_FLOW = 0x00000200, 123 I40E_DEBUG_DCB = 0x00000400, 124 I40E_DEBUG_DIAG = 0x00000800, 125 I40E_DEBUG_FD = 0x00001000, 126 127 I40E_DEBUG_AQ_MESSAGE = 0x01000000, 128 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000, 129 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000, 130 I40E_DEBUG_AQ_COMMAND = 0x06000000, 131 I40E_DEBUG_AQ = 0x0F000000, 132 133 /* 134 * Ugggh, have to cast these because of enums being "int" and these 135 * overflow int. 136 */ 137 I40E_DEBUG_USER = (int)0xF0000000, 138 139 I40E_DEBUG_ALL = (int)0xFFFFFFFF 140 }; 141 142 /* PCI Bus Info */ 143 #define I40E_PCI_LINK_STATUS 0xB2 144 #define I40E_PCI_LINK_WIDTH 0x3F0 145 #define I40E_PCI_LINK_WIDTH_1 0x10 146 #define I40E_PCI_LINK_WIDTH_2 0x20 147 #define I40E_PCI_LINK_WIDTH_4 0x40 148 #define I40E_PCI_LINK_WIDTH_8 0x80 149 #define I40E_PCI_LINK_SPEED 0xF 150 #define I40E_PCI_LINK_SPEED_2500 0x1 151 #define I40E_PCI_LINK_SPEED_5000 0x2 152 #define I40E_PCI_LINK_SPEED_8000 0x3 153 154 /* Memory types */ 155 enum i40e_memset_type { 156 I40E_NONDMA_MEM = 0, 157 I40E_DMA_MEM 158 }; 159 160 /* Memcpy types */ 161 enum i40e_memcpy_type { 162 I40E_NONDMA_TO_NONDMA = 0, 163 I40E_NONDMA_TO_DMA, 164 I40E_DMA_TO_DMA, 165 I40E_DMA_TO_NONDMA 166 }; 167 168 /* These are structs for managing the hardware information and the operations. 169 * The structures of function pointers are filled out at init time when we 170 * know for sure exactly which hardware we're working with. This gives us the 171 * flexibility of using the same main driver code but adapting to slightly 172 * different hardware needs as new parts are developed. For this architecture, 173 * the Firmware and AdminQ are intended to insulate the driver from most of the 174 * future changes, but these structures will also do part of the job. 175 */ 176 enum i40e_mac_type { 177 I40E_MAC_UNKNOWN = 0, 178 I40E_MAC_X710, 179 I40E_MAC_XL710, 180 I40E_MAC_VF, 181 #ifdef X722_SUPPORT 182 I40E_MAC_X722, 183 I40E_MAC_X722_VF, 184 #endif 185 I40E_MAC_GENERIC, 186 }; 187 188 enum i40e_media_type { 189 I40E_MEDIA_TYPE_UNKNOWN = 0, 190 I40E_MEDIA_TYPE_FIBER, 191 I40E_MEDIA_TYPE_BASET, 192 I40E_MEDIA_TYPE_BACKPLANE, 193 I40E_MEDIA_TYPE_CX4, 194 I40E_MEDIA_TYPE_DA, 195 I40E_MEDIA_TYPE_VIRTUAL 196 }; 197 198 enum i40e_fc_mode { 199 I40E_FC_NONE = 0, 200 I40E_FC_RX_PAUSE, 201 I40E_FC_TX_PAUSE, 202 I40E_FC_FULL, 203 I40E_FC_PFC, 204 I40E_FC_DEFAULT 205 }; 206 207 enum i40e_set_fc_aq_failures { 208 I40E_SET_FC_AQ_FAIL_NONE = 0, 209 I40E_SET_FC_AQ_FAIL_GET = 1, 210 I40E_SET_FC_AQ_FAIL_SET = 2, 211 I40E_SET_FC_AQ_FAIL_UPDATE = 4, 212 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 213 }; 214 215 enum i40e_vsi_type { 216 I40E_VSI_MAIN = 0, 217 I40E_VSI_VMDQ1 = 1, 218 I40E_VSI_VMDQ2 = 2, 219 I40E_VSI_CTRL = 3, 220 I40E_VSI_FCOE = 4, 221 I40E_VSI_MIRROR = 5, 222 I40E_VSI_SRIOV = 6, 223 I40E_VSI_FDIR = 7, 224 I40E_VSI_TYPE_UNKNOWN 225 }; 226 227 enum i40e_queue_type { 228 I40E_QUEUE_TYPE_RX = 0, 229 I40E_QUEUE_TYPE_TX, 230 I40E_QUEUE_TYPE_PE_CEQ, 231 I40E_QUEUE_TYPE_UNKNOWN 232 }; 233 234 struct i40e_link_status { 235 enum i40e_aq_phy_type phy_type; 236 enum i40e_aq_link_speed link_speed; 237 u8 link_info; 238 u8 an_info; 239 u8 ext_info; 240 u8 loopback; 241 /* is Link Status Event notification to SW enabled */ 242 bool lse_enable; 243 u16 max_frame_size; 244 bool crc_enable; 245 u8 pacing; 246 u8 requested_speeds; 247 u8 module_type[3]; 248 /* 1st byte: module identifier */ 249 #define I40E_MODULE_TYPE_SFP 0x03 250 #define I40E_MODULE_TYPE_QSFP 0x0D 251 /* 2nd byte: ethernet compliance codes for 10/40G */ 252 #define I40E_MODULE_TYPE_40G_ACTIVE 0x01 253 #define I40E_MODULE_TYPE_40G_LR4 0x02 254 #define I40E_MODULE_TYPE_40G_SR4 0x04 255 #define I40E_MODULE_TYPE_40G_CR4 0x08 256 #define I40E_MODULE_TYPE_10G_BASE_SR 0x10 257 #define I40E_MODULE_TYPE_10G_BASE_LR 0x20 258 #define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 259 #define I40E_MODULE_TYPE_10G_BASE_ER 0x80 260 /* 3rd byte: ethernet compliance codes for 1G */ 261 #define I40E_MODULE_TYPE_1000BASE_SX 0x01 262 #define I40E_MODULE_TYPE_1000BASE_LX 0x02 263 #define I40E_MODULE_TYPE_1000BASE_CX 0x04 264 #define I40E_MODULE_TYPE_1000BASE_T 0x08 265 }; 266 267 enum i40e_aq_capabilities_phy_type { 268 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII), 269 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX), 270 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4), 271 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR), 272 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4), 273 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI), 274 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI), 275 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI), 276 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI), 277 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI), 278 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU), 279 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU), 280 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC), 281 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC), 282 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX), 283 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T), 284 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T), 285 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR), 286 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR), 287 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU), 288 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1), 289 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4), 290 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4), 291 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4), 292 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX), 293 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX), 294 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL = BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL), 295 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2) 296 }; 297 298 struct i40e_phy_info { 299 struct i40e_link_status link_info; 300 struct i40e_link_status link_info_old; 301 bool get_link_info; 302 enum i40e_media_type media_type; 303 /* all the phy types the NVM is capable of */ 304 enum i40e_aq_capabilities_phy_type phy_types; 305 }; 306 307 #define I40E_HW_CAP_MAX_GPIO 30 308 #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO 0 309 #define I40E_HW_CAP_MDIO_PORT_MODE_I2C 1 310 311 /* Capabilities of a PF or a VF or the whole device */ 312 struct i40e_hw_capabilities { 313 u32 switch_mode; 314 #define I40E_NVM_IMAGE_TYPE_EVB 0x0 315 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 316 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 317 318 u32 management_mode; 319 u32 npar_enable; 320 u32 os2bmc; 321 u32 valid_functions; 322 bool sr_iov_1_1; 323 bool vmdq; 324 bool evb_802_1_qbg; /* Edge Virtual Bridging */ 325 bool evb_802_1_qbh; /* Bridge Port Extension */ 326 bool dcb; 327 bool fcoe; 328 bool iscsi; /* Indicates iSCSI enabled */ 329 bool flex10_enable; 330 bool flex10_capable; 331 u32 flex10_mode; 332 #define I40E_FLEX10_MODE_UNKNOWN 0x0 333 #define I40E_FLEX10_MODE_DCC 0x1 334 #define I40E_FLEX10_MODE_DCI 0x2 335 336 u32 flex10_status; 337 #define I40E_FLEX10_STATUS_DCC_ERROR 0x1 338 #define I40E_FLEX10_STATUS_VC_MODE 0x2 339 340 bool mgmt_cem; 341 bool ieee_1588; 342 bool iwarp; 343 bool fd; 344 u32 fd_filters_guaranteed; 345 u32 fd_filters_best_effort; 346 bool rss; 347 u32 rss_table_size; 348 u32 rss_table_entry_width; 349 bool led[I40E_HW_CAP_MAX_GPIO]; 350 bool sdp[I40E_HW_CAP_MAX_GPIO]; 351 u32 nvm_image_type; 352 u32 num_flow_director_filters; 353 u32 num_vfs; 354 u32 vf_base_id; 355 u32 num_vsis; 356 u32 num_rx_qp; 357 u32 num_tx_qp; 358 u32 base_queue; 359 u32 num_msix_vectors; 360 u32 num_msix_vectors_vf; 361 u32 led_pin_num; 362 u32 sdp_pin_num; 363 u32 mdio_port_num; 364 u32 mdio_port_mode; 365 u8 rx_buf_chain_len; 366 u32 enabled_tcmap; 367 u32 maxtc; 368 u64 wr_csr_prot; 369 }; 370 371 struct i40e_mac_info { 372 enum i40e_mac_type type; 373 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS]; 374 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 375 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 376 u8 port_addr[I40E_ETH_LENGTH_OF_ADDRESS]; 377 u16 max_fcoeq; 378 }; 379 380 enum i40e_aq_resources_ids { 381 I40E_NVM_RESOURCE_ID = 1 382 }; 383 384 enum i40e_aq_resource_access_type { 385 I40E_RESOURCE_READ = 1, 386 I40E_RESOURCE_WRITE 387 }; 388 389 struct i40e_nvm_info { 390 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ 391 u32 timeout; /* [ms] */ 392 u16 sr_size; /* Shadow RAM size in words */ 393 bool blank_nvm_mode; /* is NVM empty (no FW present)*/ 394 u16 version; /* NVM package version */ 395 u32 eetrack; /* NVM data version */ 396 u32 oem_ver; /* OEM version info */ 397 }; 398 399 /* definitions used in NVM update support */ 400 401 enum i40e_nvmupd_cmd { 402 I40E_NVMUPD_INVALID, 403 I40E_NVMUPD_READ_CON, 404 I40E_NVMUPD_READ_SNT, 405 I40E_NVMUPD_READ_LCB, 406 I40E_NVMUPD_READ_SA, 407 I40E_NVMUPD_WRITE_ERA, 408 I40E_NVMUPD_WRITE_CON, 409 I40E_NVMUPD_WRITE_SNT, 410 I40E_NVMUPD_WRITE_LCB, 411 I40E_NVMUPD_WRITE_SA, 412 I40E_NVMUPD_CSUM_CON, 413 I40E_NVMUPD_CSUM_SA, 414 I40E_NVMUPD_CSUM_LCB, 415 I40E_NVMUPD_STATUS, 416 I40E_NVMUPD_EXEC_AQ, 417 I40E_NVMUPD_GET_AQ_RESULT, 418 }; 419 420 enum i40e_nvmupd_state { 421 I40E_NVMUPD_STATE_INIT, 422 I40E_NVMUPD_STATE_READING, 423 I40E_NVMUPD_STATE_WRITING, 424 I40E_NVMUPD_STATE_INIT_WAIT, 425 I40E_NVMUPD_STATE_WRITE_WAIT, 426 }; 427 428 /* nvm_access definition and its masks/shifts need to be accessible to 429 * application, core driver, and shared code. Where is the right file? 430 */ 431 #define I40E_NVM_READ 0xB 432 #define I40E_NVM_WRITE 0xC 433 434 #define I40E_NVM_MOD_PNT_MASK 0xFF 435 436 #define I40E_NVM_TRANS_SHIFT 8 437 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) 438 #define I40E_NVM_CON 0x0 439 #define I40E_NVM_SNT 0x1 440 #define I40E_NVM_LCB 0x2 441 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) 442 #define I40E_NVM_ERA 0x4 443 #define I40E_NVM_CSUM 0x8 444 #define I40E_NVM_EXEC 0xf 445 446 #define I40E_NVM_ADAPT_SHIFT 16 447 #define I40E_NVM_ADAPT_MASK (0xffffULL << I40E_NVM_ADAPT_SHIFT) 448 449 #define I40E_NVMUPD_MAX_DATA 4096 450 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ 451 452 struct i40e_nvm_access { 453 u32 command; 454 u32 config; 455 u32 offset; /* in bytes */ 456 u32 data_size; /* in bytes */ 457 u8 data[1]; 458 }; 459 460 /* PCI bus types */ 461 enum i40e_bus_type { 462 i40e_bus_type_unknown = 0, 463 i40e_bus_type_pci, 464 i40e_bus_type_pcix, 465 i40e_bus_type_pci_express, 466 i40e_bus_type_reserved 467 }; 468 469 /* PCI bus speeds */ 470 enum i40e_bus_speed { 471 i40e_bus_speed_unknown = 0, 472 i40e_bus_speed_33 = 33, 473 i40e_bus_speed_66 = 66, 474 i40e_bus_speed_100 = 100, 475 i40e_bus_speed_120 = 120, 476 i40e_bus_speed_133 = 133, 477 i40e_bus_speed_2500 = 2500, 478 i40e_bus_speed_5000 = 5000, 479 i40e_bus_speed_8000 = 8000, 480 i40e_bus_speed_reserved 481 }; 482 483 /* PCI bus widths */ 484 enum i40e_bus_width { 485 i40e_bus_width_unknown = 0, 486 i40e_bus_width_pcie_x1 = 1, 487 i40e_bus_width_pcie_x2 = 2, 488 i40e_bus_width_pcie_x4 = 4, 489 i40e_bus_width_pcie_x8 = 8, 490 i40e_bus_width_32 = 32, 491 i40e_bus_width_64 = 64, 492 i40e_bus_width_reserved 493 }; 494 495 /* Bus parameters */ 496 struct i40e_bus_info { 497 enum i40e_bus_speed speed; 498 enum i40e_bus_width width; 499 enum i40e_bus_type type; 500 501 u16 func; 502 u16 device; 503 u16 lan_id; 504 }; 505 506 /* Flow control (FC) parameters */ 507 struct i40e_fc_info { 508 enum i40e_fc_mode current_mode; /* FC mode in effect */ 509 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ 510 }; 511 512 #define I40E_MAX_TRAFFIC_CLASS 8 513 #define I40E_MAX_USER_PRIORITY 8 514 #define I40E_DCBX_MAX_APPS 32 515 #define I40E_LLDPDU_SIZE 1500 516 #define I40E_TLV_STATUS_OPER 0x1 517 #define I40E_TLV_STATUS_SYNC 0x2 518 #define I40E_TLV_STATUS_ERR 0x4 519 #define I40E_CEE_OPER_MAX_APPS 3 520 #define I40E_APP_PROTOID_FCOE 0x8906 521 #define I40E_APP_PROTOID_ISCSI 0x0cbc 522 #define I40E_APP_PROTOID_FIP 0x8914 523 #define I40E_APP_SEL_ETHTYPE 0x1 524 #define I40E_APP_SEL_TCPIP 0x2 525 #define I40E_CEE_APP_SEL_ETHTYPE 0x0 526 #define I40E_CEE_APP_SEL_TCPIP 0x1 527 528 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 529 struct i40e_dcb_ets_config { 530 u8 willing; 531 u8 cbs; 532 u8 maxtcs; 533 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; 534 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; 535 u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; 536 }; 537 538 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 539 struct i40e_dcb_pfc_config { 540 u8 willing; 541 u8 mbc; 542 u8 pfccap; 543 u8 pfcenable; 544 }; 545 546 /* CEE or IEEE 802.1Qaz Application Priority data */ 547 struct i40e_dcb_app_priority_table { 548 u8 priority; 549 u8 selector; 550 u16 protocolid; 551 }; 552 553 struct i40e_dcbx_config { 554 u8 dcbx_mode; 555 #define I40E_DCBX_MODE_CEE 0x1 556 #define I40E_DCBX_MODE_IEEE 0x2 557 u32 numapps; 558 u32 tlv_status; /* CEE mode TLV status */ 559 struct i40e_dcb_ets_config etscfg; 560 struct i40e_dcb_ets_config etsrec; 561 struct i40e_dcb_pfc_config pfc; 562 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS]; 563 }; 564 565 /* Port hardware description */ 566 struct i40e_hw { 567 u8 *hw_addr; 568 void *back; 569 570 /* subsystem structs */ 571 struct i40e_phy_info phy; 572 struct i40e_mac_info mac; 573 struct i40e_bus_info bus; 574 struct i40e_nvm_info nvm; 575 struct i40e_fc_info fc; 576 577 /* pci info */ 578 u16 device_id; 579 u16 vendor_id; 580 u16 subsystem_device_id; 581 u16 subsystem_vendor_id; 582 u8 revision_id; 583 u8 port; 584 bool adapter_stopped; 585 586 /* capabilities for entire device and PCI func */ 587 struct i40e_hw_capabilities dev_caps; 588 struct i40e_hw_capabilities func_caps; 589 590 /* Flow Director shared filter space */ 591 u16 fdir_shared_filter_count; 592 593 /* device profile info */ 594 u8 pf_id; 595 u16 main_vsi_seid; 596 597 /* for multi-function MACs */ 598 u16 partition_id; 599 u16 num_partitions; 600 u16 num_ports; 601 602 /* Closest numa node to the device */ 603 u16 numa_node; 604 605 /* Admin Queue info */ 606 struct i40e_adminq_info aq; 607 608 /* state of nvm update process */ 609 enum i40e_nvmupd_state nvmupd_state; 610 struct i40e_aq_desc nvm_wb_desc; 611 struct i40e_virt_mem nvm_buff; 612 613 /* HMC info */ 614 struct i40e_hmc_info hmc; /* HMC info struct */ 615 616 /* LLDP/DCBX Status */ 617 u16 dcbx_status; 618 619 /* DCBX info */ 620 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ 621 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ 622 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ 623 624 /* debug mask */ 625 u32 debug_mask; 626 char err_str[16]; 627 }; 628 629 static INLINE bool i40e_is_vf(struct i40e_hw *hw) 630 { 631 #ifdef X722_SUPPORT 632 return (hw->mac.type == I40E_MAC_VF || 633 hw->mac.type == I40E_MAC_X722_VF); 634 #else 635 return hw->mac.type == I40E_MAC_VF; 636 #endif 637 } 638 639 struct i40e_driver_version { 640 u8 major_version; 641 u8 minor_version; 642 u8 build_version; 643 u8 subbuild_version; 644 u8 driver_string[32]; 645 }; 646 647 /* RX Descriptors */ 648 union i40e_16byte_rx_desc { 649 struct { 650 __le64 pkt_addr; /* Packet buffer address */ 651 __le64 hdr_addr; /* Header buffer address */ 652 } read; 653 struct { 654 struct { 655 struct { 656 union { 657 __le16 mirroring_status; 658 __le16 fcoe_ctx_id; 659 } mirr_fcoe; 660 __le16 l2tag1; 661 } lo_dword; 662 union { 663 __le32 rss; /* RSS Hash */ 664 __le32 fd_id; /* Flow director filter id */ 665 __le32 fcoe_param; /* FCoE DDP Context id */ 666 } hi_dword; 667 } qword0; 668 struct { 669 /* ext status/error/pktype/length */ 670 __le64 status_error_len; 671 } qword1; 672 } wb; /* writeback */ 673 }; 674 675 union i40e_32byte_rx_desc { 676 struct { 677 __le64 pkt_addr; /* Packet buffer address */ 678 __le64 hdr_addr; /* Header buffer address */ 679 /* bit 0 of hdr_buffer_addr is DD bit */ 680 __le64 rsvd1; 681 __le64 rsvd2; 682 } read; 683 struct { 684 struct { 685 struct { 686 union { 687 __le16 mirroring_status; 688 __le16 fcoe_ctx_id; 689 } mirr_fcoe; 690 __le16 l2tag1; 691 } lo_dword; 692 union { 693 __le32 rss; /* RSS Hash */ 694 __le32 fcoe_param; /* FCoE DDP Context id */ 695 /* Flow director filter id in case of 696 * Programming status desc WB 697 */ 698 __le32 fd_id; 699 } hi_dword; 700 } qword0; 701 struct { 702 /* status/error/pktype/length */ 703 __le64 status_error_len; 704 } qword1; 705 struct { 706 __le16 ext_status; /* extended status */ 707 __le16 rsvd; 708 __le16 l2tag2_1; 709 __le16 l2tag2_2; 710 } qword2; 711 struct { 712 union { 713 __le32 flex_bytes_lo; 714 __le32 pe_status; 715 } lo_dword; 716 union { 717 __le32 flex_bytes_hi; 718 __le32 fd_id; 719 } hi_dword; 720 } qword3; 721 } wb; /* writeback */ 722 }; 723 724 #define I40E_RXD_QW0_MIRROR_STATUS_SHIFT 8 725 #define I40E_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 726 I40E_RXD_QW0_MIRROR_STATUS_SHIFT) 727 #define I40E_RXD_QW0_FCOEINDX_SHIFT 0 728 #define I40E_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 729 I40E_RXD_QW0_FCOEINDX_SHIFT) 730 731 enum i40e_rx_desc_status_bits { 732 /* Note: These are predefined bit offsets */ 733 I40E_RX_DESC_STATUS_DD_SHIFT = 0, 734 I40E_RX_DESC_STATUS_EOF_SHIFT = 1, 735 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 736 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3, 737 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4, 738 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 739 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 740 #ifdef X722_SUPPORT 741 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 742 #else 743 I40E_RX_DESC_STATUS_RESERVED1_SHIFT = 8, 744 #endif 745 746 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 747 I40E_RX_DESC_STATUS_FLM_SHIFT = 11, 748 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 749 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14, 750 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 751 I40E_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */ 752 #ifdef X722_SUPPORT 753 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 754 #else 755 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18, 756 #endif 757 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 758 }; 759 760 #define I40E_RXD_QW1_STATUS_SHIFT 0 761 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) << \ 762 I40E_RXD_QW1_STATUS_SHIFT) 763 764 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT 765 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 766 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT) 767 768 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT 769 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT) 770 771 #define I40E_RXD_QW1_STATUS_UMBCAST_SHIFT I40E_RX_DESC_STATUS_UMBCAST 772 #define I40E_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 773 I40E_RXD_QW1_STATUS_UMBCAST_SHIFT) 774 775 enum i40e_rx_desc_fltstat_values { 776 I40E_RX_DESC_FLTSTAT_NO_DATA = 0, 777 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 778 I40E_RX_DESC_FLTSTAT_RSV = 2, 779 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3, 780 }; 781 782 #define I40E_RXD_PACKET_TYPE_UNICAST 0 783 #define I40E_RXD_PACKET_TYPE_MULTICAST 1 784 #define I40E_RXD_PACKET_TYPE_BROADCAST 2 785 #define I40E_RXD_PACKET_TYPE_MIRRORED 3 786 787 #define I40E_RXD_QW1_ERROR_SHIFT 19 788 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT) 789 790 enum i40e_rx_desc_error_bits { 791 /* Note: These are predefined bit offsets */ 792 I40E_RX_DESC_ERROR_RXE_SHIFT = 0, 793 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1, 794 I40E_RX_DESC_ERROR_HBO_SHIFT = 2, 795 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 796 I40E_RX_DESC_ERROR_IPE_SHIFT = 3, 797 I40E_RX_DESC_ERROR_L4E_SHIFT = 4, 798 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5, 799 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 800 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7 801 }; 802 803 enum i40e_rx_desc_error_l3l4e_fcoe_masks { 804 I40E_RX_DESC_ERROR_L3L4E_NONE = 0, 805 I40E_RX_DESC_ERROR_L3L4E_PROT = 1, 806 I40E_RX_DESC_ERROR_L3L4E_FC = 2, 807 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 808 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 809 }; 810 811 #define I40E_RXD_QW1_PTYPE_SHIFT 30 812 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT) 813 814 /* Packet type non-ip values */ 815 enum i40e_rx_l2_ptype { 816 I40E_RX_PTYPE_L2_RESERVED = 0, 817 I40E_RX_PTYPE_L2_MAC_PAY2 = 1, 818 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 819 I40E_RX_PTYPE_L2_FIP_PAY2 = 3, 820 I40E_RX_PTYPE_L2_OUI_PAY2 = 4, 821 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 822 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6, 823 I40E_RX_PTYPE_L2_ECP_PAY2 = 7, 824 I40E_RX_PTYPE_L2_EVB_PAY2 = 8, 825 I40E_RX_PTYPE_L2_QCN_PAY2 = 9, 826 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10, 827 I40E_RX_PTYPE_L2_ARP = 11, 828 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12, 829 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 830 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 831 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 832 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 833 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 834 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 835 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 836 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 837 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 838 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 839 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 840 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 841 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153 842 }; 843 844 struct i40e_rx_ptype_decoded { 845 u32 ptype:8; 846 u32 known:1; 847 u32 outer_ip:1; 848 u32 outer_ip_ver:1; 849 u32 outer_frag:1; 850 u32 tunnel_type:3; 851 u32 tunnel_end_prot:2; 852 u32 tunnel_end_frag:1; 853 u32 inner_prot:4; 854 u32 payload_layer:3; 855 }; 856 857 enum i40e_rx_ptype_outer_ip { 858 I40E_RX_PTYPE_OUTER_L2 = 0, 859 I40E_RX_PTYPE_OUTER_IP = 1 860 }; 861 862 enum i40e_rx_ptype_outer_ip_ver { 863 I40E_RX_PTYPE_OUTER_NONE = 0, 864 I40E_RX_PTYPE_OUTER_IPV4 = 0, 865 I40E_RX_PTYPE_OUTER_IPV6 = 1 866 }; 867 868 enum i40e_rx_ptype_outer_fragmented { 869 I40E_RX_PTYPE_NOT_FRAG = 0, 870 I40E_RX_PTYPE_FRAG = 1 871 }; 872 873 enum i40e_rx_ptype_tunnel_type { 874 I40E_RX_PTYPE_TUNNEL_NONE = 0, 875 I40E_RX_PTYPE_TUNNEL_IP_IP = 1, 876 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 877 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 878 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 879 }; 880 881 enum i40e_rx_ptype_tunnel_end_prot { 882 I40E_RX_PTYPE_TUNNEL_END_NONE = 0, 883 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1, 884 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2, 885 }; 886 887 enum i40e_rx_ptype_inner_prot { 888 I40E_RX_PTYPE_INNER_PROT_NONE = 0, 889 I40E_RX_PTYPE_INNER_PROT_UDP = 1, 890 I40E_RX_PTYPE_INNER_PROT_TCP = 2, 891 I40E_RX_PTYPE_INNER_PROT_SCTP = 3, 892 I40E_RX_PTYPE_INNER_PROT_ICMP = 4, 893 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5 894 }; 895 896 enum i40e_rx_ptype_payload_layer { 897 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 898 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 899 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 900 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 901 }; 902 903 #define I40E_RX_PTYPE_BIT_MASK 0x0FFFFFFF 904 #define I40E_RX_PTYPE_SHIFT 56 905 906 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38 907 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 908 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) 909 910 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52 911 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 912 I40E_RXD_QW1_LENGTH_HBUF_SHIFT) 913 914 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63 915 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT) 916 917 #define I40E_RXD_QW1_NEXTP_SHIFT 38 918 #define I40E_RXD_QW1_NEXTP_MASK (0x1FFFULL << I40E_RXD_QW1_NEXTP_SHIFT) 919 920 #define I40E_RXD_QW2_EXT_STATUS_SHIFT 0 921 #define I40E_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 922 I40E_RXD_QW2_EXT_STATUS_SHIFT) 923 924 enum i40e_rx_desc_ext_status_bits { 925 /* Note: These are predefined bit offsets */ 926 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 927 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 928 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 929 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 930 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 931 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 932 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 933 }; 934 935 #define I40E_RXD_QW2_L2TAG2_SHIFT 0 936 #define I40E_RXD_QW2_L2TAG2_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG2_SHIFT) 937 938 #define I40E_RXD_QW2_L2TAG3_SHIFT 16 939 #define I40E_RXD_QW2_L2TAG3_MASK (0xFFFFUL << I40E_RXD_QW2_L2TAG3_SHIFT) 940 941 enum i40e_rx_desc_pe_status_bits { 942 /* Note: These are predefined bit offsets */ 943 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 944 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 945 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 946 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 947 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 948 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 949 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27, 950 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 951 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 952 }; 953 954 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 955 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000 956 957 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 958 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 959 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 960 961 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 962 #define I40E_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 963 I40E_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 964 965 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 966 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 967 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 968 969 enum i40e_rx_prog_status_desc_status_bits { 970 /* Note: These are predefined bit offsets */ 971 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 972 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 973 }; 974 975 enum i40e_rx_prog_status_desc_prog_id_masks { 976 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 977 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 978 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 979 }; 980 981 enum i40e_rx_prog_status_desc_error_bits { 982 /* Note: These are predefined bit offsets */ 983 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 984 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 985 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 986 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 987 }; 988 989 #define I40E_TWO_BIT_MASK 0x3 990 #define I40E_THREE_BIT_MASK 0x7 991 #define I40E_FOUR_BIT_MASK 0xF 992 #define I40E_EIGHTEEN_BIT_MASK 0x3FFFF 993 994 /* TX Descriptor */ 995 struct i40e_tx_desc { 996 __le64 buffer_addr; /* Address of descriptor's data buf */ 997 __le64 cmd_type_offset_bsz; 998 }; 999 1000 #define I40E_TXD_QW1_DTYPE_SHIFT 0 1001 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT) 1002 1003 enum i40e_tx_desc_dtype_value { 1004 I40E_TX_DESC_DTYPE_DATA = 0x0, 1005 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 1006 I40E_TX_DESC_DTYPE_CONTEXT = 0x1, 1007 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2, 1008 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8, 1009 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9, 1010 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB, 1011 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 1012 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 1013 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF 1014 }; 1015 1016 #define I40E_TXD_QW1_CMD_SHIFT 4 1017 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT) 1018 1019 enum i40e_tx_desc_cmd_bits { 1020 I40E_TX_DESC_CMD_EOP = 0x0001, 1021 I40E_TX_DESC_CMD_RS = 0x0002, 1022 I40E_TX_DESC_CMD_ICRC = 0x0004, 1023 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008, 1024 I40E_TX_DESC_CMD_DUMMY = 0x0010, 1025 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 1026 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 1027 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 1028 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 1029 I40E_TX_DESC_CMD_FCOET = 0x0080, 1030 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 1031 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 1032 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 1033 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 1034 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 1035 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 1036 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 1037 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 1038 }; 1039 1040 #define I40E_TXD_QW1_OFFSET_SHIFT 16 1041 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 1042 I40E_TXD_QW1_OFFSET_SHIFT) 1043 1044 enum i40e_tx_desc_length_fields { 1045 /* Note: These are predefined bit offsets */ 1046 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 1047 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 1048 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 1049 }; 1050 1051 #define I40E_TXD_QW1_MACLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_MACLEN_SHIFT) 1052 #define I40E_TXD_QW1_IPLEN_MASK (0x7FUL << I40E_TX_DESC_LENGTH_IPLEN_SHIFT) 1053 #define I40E_TXD_QW1_L4LEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1054 #define I40E_TXD_QW1_FCLEN_MASK (0xFUL << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 1055 1056 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34 1057 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 1058 I40E_TXD_QW1_TX_BUF_SZ_SHIFT) 1059 1060 #define I40E_TXD_QW1_L2TAG1_SHIFT 48 1061 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT) 1062 1063 /* Context descriptors */ 1064 struct i40e_tx_context_desc { 1065 __le32 tunneling_params; 1066 __le16 l2tag2; 1067 __le16 rsvd; 1068 __le64 type_cmd_tso_mss; 1069 }; 1070 1071 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 1072 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) 1073 1074 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 1075 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) 1076 1077 enum i40e_tx_ctx_desc_cmd_bits { 1078 I40E_TX_CTX_DESC_TSO = 0x01, 1079 I40E_TX_CTX_DESC_TSYN = 0x02, 1080 I40E_TX_CTX_DESC_IL2TAG2 = 0x04, 1081 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 1082 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 1083 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 1084 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 1085 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30, 1086 I40E_TX_CTX_DESC_SWPE = 0x40 1087 }; 1088 1089 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30 1090 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 1091 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) 1092 1093 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50 1094 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 1095 I40E_TXD_CTX_QW1_MSS_SHIFT) 1096 1097 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50 1098 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT) 1099 1100 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0 1101 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 1102 I40E_TXD_CTX_QW0_EXT_IP_SHIFT) 1103 1104 enum i40e_tx_ctx_desc_eipt_offload { 1105 I40E_TX_CTX_EXT_IP_NONE = 0x0, 1106 I40E_TX_CTX_EXT_IP_IPV6 = 0x1, 1107 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 1108 I40E_TX_CTX_EXT_IP_IPV4 = 0x3 1109 }; 1110 1111 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 1112 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 1113 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 1114 1115 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9 1116 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1117 1118 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT) 1119 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT) 1120 1121 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 1122 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT) 1123 1124 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK 1125 1126 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12 1127 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 1128 I40E_TXD_CTX_QW0_NATLEN_SHIFT) 1129 1130 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19 1131 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 1132 I40E_TXD_CTX_QW0_DECTTL_SHIFT) 1133 1134 #ifdef X722_SUPPORT 1135 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 1136 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) 1137 #endif 1138 struct i40e_nop_desc { 1139 __le64 rsvd; 1140 __le64 dtype_cmd; 1141 }; 1142 1143 #define I40E_TXD_NOP_QW1_DTYPE_SHIFT 0 1144 #define I40E_TXD_NOP_QW1_DTYPE_MASK (0xFUL << I40E_TXD_NOP_QW1_DTYPE_SHIFT) 1145 1146 #define I40E_TXD_NOP_QW1_CMD_SHIFT 4 1147 #define I40E_TXD_NOP_QW1_CMD_MASK (0x7FUL << I40E_TXD_NOP_QW1_CMD_SHIFT) 1148 1149 enum i40e_tx_nop_desc_cmd_bits { 1150 /* Note: These are predefined bit offsets */ 1151 I40E_TX_NOP_DESC_EOP_SHIFT = 0, 1152 I40E_TX_NOP_DESC_RS_SHIFT = 1, 1153 I40E_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 1154 }; 1155 1156 struct i40e_filter_program_desc { 1157 __le32 qindex_flex_ptype_vsi; 1158 __le32 rsvd; 1159 __le32 dtype_cmd_cntindex; 1160 __le32 fd_id; 1161 }; 1162 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 1163 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ 1164 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) 1165 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 1166 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ 1167 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) 1168 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 1169 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ 1170 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) 1171 1172 /* Packet Classifier Types for filters */ 1173 enum i40e_filter_pctype { 1174 #ifdef X722_SUPPORT 1175 /* Note: Values 0-28 are reserved for future use. 1176 * Value 29, 30, 32 are not supported on XL710 and X710. 1177 */ 1178 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 1179 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 1180 #else 1181 /* Note: Values 0-30 are reserved for future use */ 1182 #endif 1183 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 1184 #ifdef X722_SUPPORT 1185 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 1186 #else 1187 /* Note: Value 32 is reserved for future use */ 1188 #endif 1189 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 1190 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 1191 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 1192 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36, 1193 #ifdef X722_SUPPORT 1194 /* Note: Values 37-38 are reserved for future use. 1195 * Value 39, 40, 42 are not supported on XL710 and X710. 1196 */ 1197 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 1198 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 1199 #else 1200 /* Note: Values 37-40 are reserved for future use */ 1201 #endif 1202 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 1203 #ifdef X722_SUPPORT 1204 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 1205 #endif 1206 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 1207 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 1208 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 1209 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46, 1210 /* Note: Value 47 is reserved for future use */ 1211 I40E_FILTER_PCTYPE_FCOE_OX = 48, 1212 I40E_FILTER_PCTYPE_FCOE_RX = 49, 1213 I40E_FILTER_PCTYPE_FCOE_OTHER = 50, 1214 /* Note: Values 51-62 are reserved for future use */ 1215 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, 1216 }; 1217 1218 enum i40e_filter_program_desc_dest { 1219 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, 1220 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, 1221 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, 1222 }; 1223 1224 enum i40e_filter_program_desc_fd_status { 1225 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, 1226 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, 1227 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, 1228 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, 1229 }; 1230 1231 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 1232 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) 1233 1234 #define I40E_TXD_FLTR_QW1_DTYPE_SHIFT 0 1235 #define I40E_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << I40E_TXD_FLTR_QW1_DTYPE_SHIFT) 1236 1237 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 1238 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ 1239 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1240 1241 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1242 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) 1243 1244 enum i40e_filter_program_desc_pcmd { 1245 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, 1246 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, 1247 }; 1248 1249 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1250 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) 1251 1252 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) 1253 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) 1254 1255 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ 1256 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1257 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ 1258 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) 1259 #ifdef X722_SUPPORT 1260 1261 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 1262 I40E_TXD_FLTR_QW1_CMD_SHIFT) 1263 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT) 1264 #endif 1265 1266 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 1267 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ 1268 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) 1269 1270 enum i40e_filter_type { 1271 I40E_FLOW_DIRECTOR_FLTR = 0, 1272 I40E_PE_QUAD_HASH_FLTR = 1, 1273 I40E_ETHERTYPE_FLTR, 1274 I40E_FCOE_CTX_FLTR, 1275 I40E_MAC_VLAN_FLTR, 1276 I40E_HASH_FLTR 1277 }; 1278 1279 struct i40e_vsi_context { 1280 u16 seid; 1281 u16 uplink_seid; 1282 u16 vsi_number; 1283 u16 vsis_allocated; 1284 u16 vsis_unallocated; 1285 u16 flags; 1286 u8 pf_num; 1287 u8 vf_num; 1288 u8 connection_type; 1289 struct i40e_aqc_vsi_properties_data info; 1290 }; 1291 1292 struct i40e_veb_context { 1293 u16 seid; 1294 u16 uplink_seid; 1295 u16 veb_number; 1296 u16 vebs_allocated; 1297 u16 vebs_unallocated; 1298 u16 flags; 1299 struct i40e_aqc_get_veb_parameters_completion info; 1300 }; 1301 1302 /* Statistics collected by each port, VSI, VEB, and S-channel */ 1303 struct i40e_eth_stats { 1304 u64 rx_bytes; /* gorc */ 1305 u64 rx_unicast; /* uprc */ 1306 u64 rx_multicast; /* mprc */ 1307 u64 rx_broadcast; /* bprc */ 1308 u64 rx_discards; /* rdpc */ 1309 u64 rx_unknown_protocol; /* rupp */ 1310 u64 tx_bytes; /* gotc */ 1311 u64 tx_unicast; /* uptc */ 1312 u64 tx_multicast; /* mptc */ 1313 u64 tx_broadcast; /* bptc */ 1314 u64 tx_discards; /* tdpc */ 1315 u64 tx_errors; /* tepc */ 1316 }; 1317 1318 /* Statistics collected per VEB per TC */ 1319 struct i40e_veb_tc_stats { 1320 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; 1321 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1322 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; 1323 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; 1324 }; 1325 1326 /* Statistics collected by the MAC */ 1327 struct i40e_hw_port_stats { 1328 /* eth stats collected by the port */ 1329 struct i40e_eth_stats eth; 1330 1331 /* additional port specific stats */ 1332 u64 tx_dropped_link_down; /* tdold */ 1333 u64 crc_errors; /* crcerrs */ 1334 u64 illegal_bytes; /* illerrc */ 1335 u64 error_bytes; /* errbc */ 1336 u64 mac_local_faults; /* mlfc */ 1337 u64 mac_remote_faults; /* mrfc */ 1338 u64 rx_length_errors; /* rlec */ 1339 u64 link_xon_rx; /* lxonrxc */ 1340 u64 link_xoff_rx; /* lxoffrxc */ 1341 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1342 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1343 u64 link_xon_tx; /* lxontxc */ 1344 u64 link_xoff_tx; /* lxofftxc */ 1345 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1346 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1347 u64 priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 1348 u64 rx_size_64; /* prc64 */ 1349 u64 rx_size_127; /* prc127 */ 1350 u64 rx_size_255; /* prc255 */ 1351 u64 rx_size_511; /* prc511 */ 1352 u64 rx_size_1023; /* prc1023 */ 1353 u64 rx_size_1522; /* prc1522 */ 1354 u64 rx_size_big; /* prc9522 */ 1355 u64 rx_undersize; /* ruc */ 1356 u64 rx_fragments; /* rfc */ 1357 u64 rx_oversize; /* roc */ 1358 u64 rx_jabber; /* rjc */ 1359 u64 tx_size_64; /* ptc64 */ 1360 u64 tx_size_127; /* ptc127 */ 1361 u64 tx_size_255; /* ptc255 */ 1362 u64 tx_size_511; /* ptc511 */ 1363 u64 tx_size_1023; /* ptc1023 */ 1364 u64 tx_size_1522; /* ptc1522 */ 1365 u64 tx_size_big; /* ptc9522 */ 1366 u64 mac_short_packet_dropped; /* mspdc */ 1367 u64 checksum_error; /* xec */ 1368 /* flow director stats */ 1369 u64 fd_atr_match; 1370 u64 fd_sb_match; 1371 u64 fd_atr_tunnel_match; 1372 u32 fd_atr_status; 1373 u32 fd_sb_status; 1374 /* EEE LPI */ 1375 u32 tx_lpi_status; 1376 u32 rx_lpi_status; 1377 u64 tx_lpi_count; /* etlpic */ 1378 u64 rx_lpi_count; /* erlpic */ 1379 }; 1380 1381 /* Checksum and Shadow RAM pointers */ 1382 #define I40E_SR_NVM_CONTROL_WORD 0x00 1383 #define I40E_SR_PCIE_ANALOG_CONFIG_PTR 0x03 1384 #define I40E_SR_PHY_ANALOG_CONFIG_PTR 0x04 1385 #define I40E_SR_OPTION_ROM_PTR 0x05 1386 #define I40E_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 1387 #define I40E_SR_AUTO_GENERATED_POINTERS_PTR 0x07 1388 #define I40E_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 1389 #define I40E_SR_EMP_GLOBAL_MODULE_PTR 0x09 1390 #define I40E_SR_RO_PCIE_LCB_PTR 0x0A 1391 #define I40E_SR_EMP_IMAGE_PTR 0x0B 1392 #define I40E_SR_PE_IMAGE_PTR 0x0C 1393 #define I40E_SR_CSR_PROTECTED_LIST_PTR 0x0D 1394 #define I40E_SR_MNG_CONFIG_PTR 0x0E 1395 #define I40E_SR_EMP_MODULE_PTR 0x0F 1396 #define I40E_SR_PBA_FLAGS 0x15 1397 #define I40E_SR_PBA_BLOCK_PTR 0x16 1398 #define I40E_SR_BOOT_CONFIG_PTR 0x17 1399 #define I40E_NVM_OEM_VER_OFF 0x83 1400 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 1401 #define I40E_SR_NVM_WAKE_ON_LAN 0x19 1402 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 1403 #define I40E_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 1404 #define I40E_SR_NVM_MAP_VERSION 0x29 1405 #define I40E_SR_NVM_IMAGE_VERSION 0x2A 1406 #define I40E_SR_NVM_STRUCTURE_VERSION 0x2B 1407 #define I40E_SR_NVM_EETRACK_LO 0x2D 1408 #define I40E_SR_NVM_EETRACK_HI 0x2E 1409 #define I40E_SR_VPD_PTR 0x2F 1410 #define I40E_SR_PXE_SETUP_PTR 0x30 1411 #define I40E_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 1412 #define I40E_SR_NVM_ORIGINAL_EETRACK_LO 0x34 1413 #define I40E_SR_NVM_ORIGINAL_EETRACK_HI 0x35 1414 #define I40E_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 1415 #define I40E_SR_POR_REGS_AUTO_LOAD_PTR 0x38 1416 #define I40E_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 1417 #define I40E_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 1418 #define I40E_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 1419 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E 1420 #define I40E_SR_SW_CHECKSUM_WORD 0x3F 1421 #define I40E_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 1422 #define I40E_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 1423 #define I40E_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 1424 #define I40E_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 1425 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48 1426 #define I40E_SR_FEATURE_CONFIGURATION_PTR 0x49 1427 #define I40E_SR_CONFIGURATION_METADATA_PTR 0x4D 1428 #define I40E_SR_IMMEDIATE_VALUES_PTR 0x4E 1429 1430 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ 1431 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024 1432 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 1433 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 1434 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) 1435 1436 /* Shadow RAM related */ 1437 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 1438 #define I40E_SR_BUF_ALIGNMENT 4096 1439 #define I40E_SR_WORDS_IN_1KB 512 1440 /* Checksum should be calculated such that after adding all the words, 1441 * including the checksum word itself, the sum should be 0xBABA. 1442 */ 1443 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA 1444 1445 #define I40E_SRRD_SRCTL_ATTEMPTS 100000 1446 1447 enum i40e_switch_element_types { 1448 I40E_SWITCH_ELEMENT_TYPE_MAC = 1, 1449 I40E_SWITCH_ELEMENT_TYPE_PF = 2, 1450 I40E_SWITCH_ELEMENT_TYPE_VF = 3, 1451 I40E_SWITCH_ELEMENT_TYPE_EMP = 4, 1452 I40E_SWITCH_ELEMENT_TYPE_BMC = 6, 1453 I40E_SWITCH_ELEMENT_TYPE_PE = 16, 1454 I40E_SWITCH_ELEMENT_TYPE_VEB = 17, 1455 I40E_SWITCH_ELEMENT_TYPE_PA = 18, 1456 I40E_SWITCH_ELEMENT_TYPE_VSI = 19, 1457 }; 1458 1459 /* Supported EtherType filters */ 1460 enum i40e_ether_type_index { 1461 I40E_ETHER_TYPE_1588 = 0, 1462 I40E_ETHER_TYPE_FIP = 1, 1463 I40E_ETHER_TYPE_OUI_EXTENDED = 2, 1464 I40E_ETHER_TYPE_MAC_CONTROL = 3, 1465 I40E_ETHER_TYPE_LLDP = 4, 1466 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, 1467 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, 1468 I40E_ETHER_TYPE_QCN_CNM = 7, 1469 I40E_ETHER_TYPE_8021X = 8, 1470 I40E_ETHER_TYPE_ARP = 9, 1471 I40E_ETHER_TYPE_RSV1 = 10, 1472 I40E_ETHER_TYPE_RSV2 = 11, 1473 }; 1474 1475 /* Filter context base size is 1K */ 1476 #define I40E_HASH_FILTER_BASE_SIZE 1024 1477 /* Supported Hash filter values */ 1478 enum i40e_hash_filter_size { 1479 I40E_HASH_FILTER_SIZE_1K = 0, 1480 I40E_HASH_FILTER_SIZE_2K = 1, 1481 I40E_HASH_FILTER_SIZE_4K = 2, 1482 I40E_HASH_FILTER_SIZE_8K = 3, 1483 I40E_HASH_FILTER_SIZE_16K = 4, 1484 I40E_HASH_FILTER_SIZE_32K = 5, 1485 I40E_HASH_FILTER_SIZE_64K = 6, 1486 I40E_HASH_FILTER_SIZE_128K = 7, 1487 I40E_HASH_FILTER_SIZE_256K = 8, 1488 I40E_HASH_FILTER_SIZE_512K = 9, 1489 I40E_HASH_FILTER_SIZE_1M = 10, 1490 }; 1491 1492 /* DMA context base size is 0.5K */ 1493 #define I40E_DMA_CNTX_BASE_SIZE 512 1494 /* Supported DMA context values */ 1495 enum i40e_dma_cntx_size { 1496 I40E_DMA_CNTX_SIZE_512 = 0, 1497 I40E_DMA_CNTX_SIZE_1K = 1, 1498 I40E_DMA_CNTX_SIZE_2K = 2, 1499 I40E_DMA_CNTX_SIZE_4K = 3, 1500 I40E_DMA_CNTX_SIZE_8K = 4, 1501 I40E_DMA_CNTX_SIZE_16K = 5, 1502 I40E_DMA_CNTX_SIZE_32K = 6, 1503 I40E_DMA_CNTX_SIZE_64K = 7, 1504 I40E_DMA_CNTX_SIZE_128K = 8, 1505 I40E_DMA_CNTX_SIZE_256K = 9, 1506 }; 1507 1508 /* Supported Hash look up table (LUT) sizes */ 1509 enum i40e_hash_lut_size { 1510 I40E_HASH_LUT_SIZE_128 = 0, 1511 I40E_HASH_LUT_SIZE_512 = 1, 1512 }; 1513 1514 /* Structure to hold a per PF filter control settings */ 1515 struct i40e_filter_control_settings { 1516 /* number of PE Quad Hash filter buckets */ 1517 enum i40e_hash_filter_size pe_filt_num; 1518 /* number of PE Quad Hash contexts */ 1519 enum i40e_dma_cntx_size pe_cntx_num; 1520 /* number of FCoE filter buckets */ 1521 enum i40e_hash_filter_size fcoe_filt_num; 1522 /* number of FCoE DDP contexts */ 1523 enum i40e_dma_cntx_size fcoe_cntx_num; 1524 /* size of the Hash LUT */ 1525 enum i40e_hash_lut_size hash_lut_size; 1526 /* enable FDIR filters for PF and its VFs */ 1527 bool enable_fdir; 1528 /* enable Ethertype filters for PF and its VFs */ 1529 bool enable_ethtype; 1530 /* enable MAC/VLAN filters for PF and its VFs */ 1531 bool enable_macvlan; 1532 }; 1533 1534 /* Structure to hold device level control filter counts */ 1535 struct i40e_control_filter_stats { 1536 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ 1537 u16 etype_used; /* Used perfect EtherType filters */ 1538 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ 1539 u16 etype_free; /* Un-used perfect EtherType filters */ 1540 }; 1541 1542 enum i40e_reset_type { 1543 I40E_RESET_POR = 0, 1544 I40E_RESET_CORER = 1, 1545 I40E_RESET_GLOBR = 2, 1546 I40E_RESET_EMPR = 3, 1547 }; 1548 1549 /* IEEE 802.1AB LLDP Agent Variables from NVM */ 1550 #define I40E_NVM_LLDP_CFG_PTR 0xD 1551 struct i40e_lldp_variables { 1552 u16 length; 1553 u16 adminstatus; 1554 u16 msgfasttx; 1555 u16 msgtxinterval; 1556 u16 txparams; 1557 u16 timers; 1558 u16 crc8; 1559 }; 1560 1561 /* Offsets into Alternate Ram */ 1562 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1563 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1564 #define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1565 #define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1566 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1567 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1568 1569 /* Alternate Ram Bandwidth Masks */ 1570 #define I40E_ALT_BW_VALUE_MASK 0xFF 1571 #define I40E_ALT_BW_RELATIVE_MASK 0x40000000 1572 #define I40E_ALT_BW_VALID_MASK 0x80000000 1573 1574 /* RSS Hash Table Size */ 1575 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 1576 1577 /* PBA length (and one with additional zero-padding byte), see Table 6-2. */ 1578 #define I40E_PBANUM_LENGTH 12 1579 #define I40E_PBANUM_STRLEN 13 1580 1581 #endif /* _I40E_TYPE_H_ */ 1582