1 /******************************************************************************
2 
3   Copyright (c) 2013-2017, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
15 
16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30   POSSIBILITY OF SUCH DAMAGE.
31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _I40E_REGISTER_H_
36 #define _I40E_REGISTER_H_
37 
38 
39 #define I40E_GL_ARQBAH              0x000801C0 /* Reset: EMPR */
40 #define I40E_GL_ARQBAH_ARQBAH_SHIFT 0
41 #define I40E_GL_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT)
42 #define I40E_GL_ARQBAL              0x000800C0 /* Reset: EMPR */
43 #define I40E_GL_ARQBAL_ARQBAL_SHIFT 0
44 #define I40E_GL_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT)
45 #define I40E_GL_ARQH            0x000803C0 /* Reset: EMPR */
46 #define I40E_GL_ARQH_ARQH_SHIFT 0
47 #define I40E_GL_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT)
48 #define I40E_GL_ARQT            0x000804C0 /* Reset: EMPR */
49 #define I40E_GL_ARQT_ARQT_SHIFT 0
50 #define I40E_GL_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT)
51 #define I40E_GL_ATQBAH              0x00080140 /* Reset: EMPR */
52 #define I40E_GL_ATQBAH_ATQBAH_SHIFT 0
53 #define I40E_GL_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT)
54 #define I40E_GL_ATQBAL              0x00080040 /* Reset: EMPR */
55 #define I40E_GL_ATQBAL_ATQBAL_SHIFT 0
56 #define I40E_GL_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT)
57 #define I40E_GL_ATQH            0x00080340 /* Reset: EMPR */
58 #define I40E_GL_ATQH_ATQH_SHIFT 0
59 #define I40E_GL_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT)
60 #define I40E_GL_ATQLEN                 0x00080240 /* Reset: EMPR */
61 #define I40E_GL_ATQLEN_ATQLEN_SHIFT    0
62 #define I40E_GL_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT)
63 #define I40E_GL_ATQLEN_ATQVFE_SHIFT    28
64 #define I40E_GL_ATQLEN_ATQVFE_MASK     I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT)
65 #define I40E_GL_ATQLEN_ATQOVFL_SHIFT   29
66 #define I40E_GL_ATQLEN_ATQOVFL_MASK    I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT)
67 #define I40E_GL_ATQLEN_ATQCRIT_SHIFT   30
68 #define I40E_GL_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT)
69 #define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31
70 #define I40E_GL_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT)
71 #define I40E_GL_ATQT            0x00080440 /* Reset: EMPR */
72 #define I40E_GL_ATQT_ATQT_SHIFT 0
73 #define I40E_GL_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT)
74 #define I40E_PF_ARQBAH              0x00080180 /* Reset: EMPR */
75 #define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
76 #define I40E_PF_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT)
77 #define I40E_PF_ARQBAL              0x00080080 /* Reset: EMPR */
78 #define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
79 #define I40E_PF_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT)
80 #define I40E_PF_ARQH            0x00080380 /* Reset: EMPR */
81 #define I40E_PF_ARQH_ARQH_SHIFT 0
82 #define I40E_PF_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT)
83 #define I40E_PF_ARQLEN                 0x00080280 /* Reset: EMPR */
84 #define I40E_PF_ARQLEN_ARQLEN_SHIFT    0
85 #define I40E_PF_ARQLEN_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT)
86 #define I40E_PF_ARQLEN_ARQVFE_SHIFT    28
87 #define I40E_PF_ARQLEN_ARQVFE_MASK     I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT)
88 #define I40E_PF_ARQLEN_ARQOVFL_SHIFT   29
89 #define I40E_PF_ARQLEN_ARQOVFL_MASK    I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT)
90 #define I40E_PF_ARQLEN_ARQCRIT_SHIFT   30
91 #define I40E_PF_ARQLEN_ARQCRIT_MASK    I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
92 #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
93 #define I40E_PF_ARQLEN_ARQENABLE_MASK  I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
94 #define I40E_PF_ARQT            0x00080480 /* Reset: EMPR */
95 #define I40E_PF_ARQT_ARQT_SHIFT 0
96 #define I40E_PF_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
97 #define I40E_PF_ATQBAH              0x00080100 /* Reset: EMPR */
98 #define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
99 #define I40E_PF_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT)
100 #define I40E_PF_ATQBAL              0x00080000 /* Reset: EMPR */
101 #define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
102 #define I40E_PF_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT)
103 #define I40E_PF_ATQH            0x00080300 /* Reset: EMPR */
104 #define I40E_PF_ATQH_ATQH_SHIFT 0
105 #define I40E_PF_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT)
106 #define I40E_PF_ATQLEN                 0x00080200 /* Reset: EMPR */
107 #define I40E_PF_ATQLEN_ATQLEN_SHIFT    0
108 #define I40E_PF_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT)
109 #define I40E_PF_ATQLEN_ATQVFE_SHIFT    28
110 #define I40E_PF_ATQLEN_ATQVFE_MASK     I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT)
111 #define I40E_PF_ATQLEN_ATQOVFL_SHIFT   29
112 #define I40E_PF_ATQLEN_ATQOVFL_MASK    I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT)
113 #define I40E_PF_ATQLEN_ATQCRIT_SHIFT   30
114 #define I40E_PF_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
115 #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
116 #define I40E_PF_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1UL, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
117 #define I40E_PF_ATQT            0x00080400 /* Reset: EMPR */
118 #define I40E_PF_ATQT_ATQT_SHIFT 0
119 #define I40E_PF_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
120 #define I40E_VF_ARQBAH(_VF)         (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
121 #define I40E_VF_ARQBAH_MAX_INDEX    127
122 #define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
123 #define I40E_VF_ARQBAH_ARQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT)
124 #define I40E_VF_ARQBAL(_VF)         (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
125 #define I40E_VF_ARQBAL_MAX_INDEX    127
126 #define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
127 #define I40E_VF_ARQBAL_ARQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT)
128 #define I40E_VF_ARQH(_VF)       (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
129 #define I40E_VF_ARQH_MAX_INDEX  127
130 #define I40E_VF_ARQH_ARQH_SHIFT 0
131 #define I40E_VF_ARQH_ARQH_MASK  I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT)
132 #define I40E_VF_ARQLEN(_VF)            (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
133 #define I40E_VF_ARQLEN_MAX_INDEX       127
134 #define I40E_VF_ARQLEN_ARQLEN_SHIFT    0
135 #define I40E_VF_ARQLEN_ARQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT)
136 #define I40E_VF_ARQLEN_ARQVFE_SHIFT    28
137 #define I40E_VF_ARQLEN_ARQVFE_MASK     I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT)
138 #define I40E_VF_ARQLEN_ARQOVFL_SHIFT   29
139 #define I40E_VF_ARQLEN_ARQOVFL_MASK    I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT)
140 #define I40E_VF_ARQLEN_ARQCRIT_SHIFT   30
141 #define I40E_VF_ARQLEN_ARQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
142 #define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
143 #define I40E_VF_ARQLEN_ARQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
144 #define I40E_VF_ARQT(_VF)       (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
145 #define I40E_VF_ARQT_MAX_INDEX  127
146 #define I40E_VF_ARQT_ARQT_SHIFT 0
147 #define I40E_VF_ARQT_ARQT_MASK  I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT)
148 #define I40E_VF_ATQBAH(_VF)         (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
149 #define I40E_VF_ATQBAH_MAX_INDEX    127
150 #define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
151 #define I40E_VF_ATQBAH_ATQBAH_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT)
152 #define I40E_VF_ATQBAL(_VF)         (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
153 #define I40E_VF_ATQBAL_MAX_INDEX    127
154 #define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
155 #define I40E_VF_ATQBAL_ATQBAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT)
156 #define I40E_VF_ATQH(_VF)       (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
157 #define I40E_VF_ATQH_MAX_INDEX  127
158 #define I40E_VF_ATQH_ATQH_SHIFT 0
159 #define I40E_VF_ATQH_ATQH_MASK  I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT)
160 #define I40E_VF_ATQLEN(_VF)            (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
161 #define I40E_VF_ATQLEN_MAX_INDEX       127
162 #define I40E_VF_ATQLEN_ATQLEN_SHIFT    0
163 #define I40E_VF_ATQLEN_ATQLEN_MASK     I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT)
164 #define I40E_VF_ATQLEN_ATQVFE_SHIFT    28
165 #define I40E_VF_ATQLEN_ATQVFE_MASK     I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT)
166 #define I40E_VF_ATQLEN_ATQOVFL_SHIFT   29
167 #define I40E_VF_ATQLEN_ATQOVFL_MASK    I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT)
168 #define I40E_VF_ATQLEN_ATQCRIT_SHIFT   30
169 #define I40E_VF_ATQLEN_ATQCRIT_MASK    I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
170 #define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
171 #define I40E_VF_ATQLEN_ATQENABLE_MASK  I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
172 #define I40E_VF_ATQT(_VF)       (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
173 #define I40E_VF_ATQT_MAX_INDEX  127
174 #define I40E_VF_ATQT_ATQT_SHIFT 0
175 #define I40E_VF_ATQT_ATQT_MASK  I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT)
176 #define I40E_PRT_L2TAGSEN              0x001C0B20 /* Reset: CORER */
177 #define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
178 #define I40E_PRT_L2TAGSEN_ENABLE_MASK  I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
179 #define I40E_PFCM_LAN_ERRDATA                  0x0010C080 /* Reset: PFR */
180 #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
181 #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK  I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
182 #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT     4
183 #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK      I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
184 #define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT      8
185 #define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK       I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
186 #define I40E_PFCM_LAN_ERRINFO                     0x0010C000 /* Reset: PFR */
187 #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT   0
188 #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK    I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
189 #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT    4
190 #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK     I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
191 #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8
192 #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
193 #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16
194 #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
195 #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
196 #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
197 #define I40E_PFCM_LANCTXCTL                  0x0010C300 /* Reset: CORER */
198 #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT  0
199 #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK   I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
200 #define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT   12
201 #define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK    I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
202 #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15
203 #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK  I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
204 #define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT    17
205 #define I40E_PFCM_LANCTXCTL_OP_CODE_MASK     I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
206 #define I40E_PFCM_LANCTXDATA(_i)        (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */
207 #define I40E_PFCM_LANCTXDATA_MAX_INDEX  3
208 #define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
209 #define I40E_PFCM_LANCTXDATA_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT)
210 #define I40E_PFCM_LANCTXSTAT                0x0010C380 /* Reset: CORER */
211 #define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
212 #define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK  I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
213 #define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
214 #define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK  I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
215 #define I40E_VFCM_PE_ERRDATA1(_VF)             (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
216 #define I40E_VFCM_PE_ERRDATA1_MAX_INDEX        127
217 #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
218 #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK  I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
219 #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT     4
220 #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK      I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
221 #define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT      8
222 #define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK       I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
223 #define I40E_VFCM_PE_ERRINFO1(_VF)                (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
224 #define I40E_VFCM_PE_ERRINFO1_MAX_INDEX           127
225 #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT   0
226 #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK    I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
227 #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT    4
228 #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK     I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
229 #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8
230 #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
231 #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16
232 #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
233 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
234 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK  I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
235 #define I40E_GLDCB_GENC              0x00083044 /* Reset: CORER */
236 #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
237 #define I40E_GLDCB_GENC_PCIRTT_MASK  I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT)
238 #define I40E_GLDCB_RUPTI                     0x00122618 /* Reset: CORER */
239 #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
240 #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
241 #define I40E_PRTDCB_FCCFG            0x001E4640 /* Reset: GLOBR */
242 #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
243 #define I40E_PRTDCB_FCCFG_TFCE_MASK  I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT)
244 #define I40E_PRTDCB_FCRTV                     0x001E4600 /* Reset: GLOBR */
245 #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
246 #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
247 #define I40E_PRTDCB_FCTTVN(_i)             (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */
248 #define I40E_PRTDCB_FCTTVN_MAX_INDEX       3
249 #define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT    0
250 #define I40E_PRTDCB_FCTTVN_TTV_2N_MASK     I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
251 #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
252 #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK  I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
253 #define I40E_PRTDCB_GENC                    0x00083000 /* Reset: CORER */
254 #define I40E_PRTDCB_GENC_RESERVED_1_SHIFT   0
255 #define I40E_PRTDCB_GENC_RESERVED_1_MASK    I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
256 #define I40E_PRTDCB_GENC_NUMTC_SHIFT        2
257 #define I40E_PRTDCB_GENC_NUMTC_MASK         I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT)
258 #define I40E_PRTDCB_GENC_FCOEUP_SHIFT       6
259 #define I40E_PRTDCB_GENC_FCOEUP_MASK        I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT)
260 #define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
261 #define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK  I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
262 #define I40E_PRTDCB_GENC_PFCLDA_SHIFT       16
263 #define I40E_PRTDCB_GENC_PFCLDA_MASK        I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT)
264 #define I40E_PRTDCB_GENS                   0x00083020 /* Reset: CORER */
265 #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
266 #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK  I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
267 #define I40E_PRTDCB_MFLCN             0x001E2400 /* Reset: GLOBR */
268 #define I40E_PRTDCB_MFLCN_PMCF_SHIFT  0
269 #define I40E_PRTDCB_MFLCN_PMCF_MASK   I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT)
270 #define I40E_PRTDCB_MFLCN_DPF_SHIFT   1
271 #define I40E_PRTDCB_MFLCN_DPF_MASK    I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT)
272 #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
273 #define I40E_PRTDCB_MFLCN_RPFCM_MASK  I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
274 #define I40E_PRTDCB_MFLCN_RFCE_SHIFT  3
275 #define I40E_PRTDCB_MFLCN_RFCE_MASK   I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT)
276 #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
277 #define I40E_PRTDCB_MFLCN_RPFCE_MASK  I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
278 #define I40E_PRTDCB_RETSC                    0x001223E0 /* Reset: CORER */
279 #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT     0
280 #define I40E_PRTDCB_RETSC_ETS_MODE_MASK      I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
281 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
282 #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
283 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT  2
284 #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK   I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
285 #define I40E_PRTDCB_RETSC_LLTC_SHIFT         8
286 #define I40E_PRTDCB_RETSC_LLTC_MASK          I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT)
287 #define I40E_PRTDCB_RETSTCC(_i)               (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
288 #define I40E_PRTDCB_RETSTCC_MAX_INDEX         7
289 #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT     0
290 #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK      I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
291 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
292 #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
293 #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT       31
294 #define I40E_PRTDCB_RETSTCC_ETSTC_MASK        I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
295 #define I40E_PRTDCB_RPPMC                    0x001223A0 /* Reset: CORER */
296 #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT      0
297 #define I40E_PRTDCB_RPPMC_LANRPPM_MASK       I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
298 #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT     8
299 #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK      I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
300 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
301 #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK  I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
302 #define I40E_PRTDCB_RUP                0x001C0B00 /* Reset: CORER */
303 #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
304 #define I40E_PRTDCB_RUP_NOVLANUP_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
305 #define I40E_PRTDCB_RUP2TC             0x001C09A0 /* Reset: CORER */
306 #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
307 #define I40E_PRTDCB_RUP2TC_UP0TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
308 #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
309 #define I40E_PRTDCB_RUP2TC_UP1TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
310 #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
311 #define I40E_PRTDCB_RUP2TC_UP2TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
312 #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
313 #define I40E_PRTDCB_RUP2TC_UP3TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
314 #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
315 #define I40E_PRTDCB_RUP2TC_UP4TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
316 #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
317 #define I40E_PRTDCB_RUP2TC_UP5TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
318 #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
319 #define I40E_PRTDCB_RUP2TC_UP6TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
320 #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
321 #define I40E_PRTDCB_RUP2TC_UP7TC_MASK  I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
322 #define I40E_PRTDCB_RUPTQ(_i)          (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
323 #define I40E_PRTDCB_RUPTQ_MAX_INDEX    7
324 #define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0
325 #define I40E_PRTDCB_RUPTQ_RXQNUM_MASK  I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT)
326 #define I40E_PRTDCB_TC2PFC              0x001C0980 /* Reset: CORER */
327 #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
328 #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK  I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
329 #define I40E_PRTDCB_TCMSTC(_i)        (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
330 #define I40E_PRTDCB_TCMSTC_MAX_INDEX  7
331 #define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0
332 #define I40E_PRTDCB_TCMSTC_MSTC_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT)
333 #define I40E_PRTDCB_TCPMC                 0x000A21A0 /* Reset: CORER */
334 #define I40E_PRTDCB_TCPMC_CPM_SHIFT       0
335 #define I40E_PRTDCB_TCPMC_CPM_MASK        I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT)
336 #define I40E_PRTDCB_TCPMC_LLTC_SHIFT      13
337 #define I40E_PRTDCB_TCPMC_LLTC_MASK       I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT)
338 #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
339 #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
340 #define I40E_PRTDCB_TCWSTC(_i)        (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
341 #define I40E_PRTDCB_TCWSTC_MAX_INDEX  7
342 #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
343 #define I40E_PRTDCB_TCWSTC_MSTC_MASK  I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
344 #define I40E_PRTDCB_TDPMC                 0x000A0180 /* Reset: CORER */
345 #define I40E_PRTDCB_TDPMC_DPM_SHIFT       0
346 #define I40E_PRTDCB_TDPMC_DPM_MASK        I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT)
347 #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
348 #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK  I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
349 #define I40E_PRTDCB_TETSC_TCB                             0x000AE060 /* Reset: CORER */
350 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
351 #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK  I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
352 #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT                  8
353 #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK                   I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
354 #define I40E_PRTDCB_TETSC_TPB                             0x00098060 /* Reset: CORER */
355 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
356 #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK  I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
357 #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT                  8
358 #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK                   I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
359 #define I40E_PRTDCB_TFCS              0x001E4560 /* Reset: GLOBR */
360 #define I40E_PRTDCB_TFCS_TXOFF_SHIFT  0
361 #define I40E_PRTDCB_TFCS_TXOFF_MASK   I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT)
362 #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
363 #define I40E_PRTDCB_TFCS_TXOFF0_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
364 #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
365 #define I40E_PRTDCB_TFCS_TXOFF1_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
366 #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
367 #define I40E_PRTDCB_TFCS_TXOFF2_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
368 #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
369 #define I40E_PRTDCB_TFCS_TXOFF3_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
370 #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
371 #define I40E_PRTDCB_TFCS_TXOFF4_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
372 #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
373 #define I40E_PRTDCB_TFCS_TXOFF5_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
374 #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
375 #define I40E_PRTDCB_TFCS_TXOFF6_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
376 #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
377 #define I40E_PRTDCB_TFCS_TXOFF7_MASK  I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
378 #define I40E_PRTDCB_TPFCTS(_i)            (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */
379 #define I40E_PRTDCB_TPFCTS_MAX_INDEX      7
380 #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
381 #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK  I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
382 #define I40E_GLFCOE_RCTL                0x00269B94 /* Reset: CORER */
383 #define I40E_GLFCOE_RCTL_FCOEVER_SHIFT  0
384 #define I40E_GLFCOE_RCTL_FCOEVER_MASK   I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
385 #define I40E_GLFCOE_RCTL_SAVBAD_SHIFT   4
386 #define I40E_GLFCOE_RCTL_SAVBAD_MASK    I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
387 #define I40E_GLFCOE_RCTL_ICRC_SHIFT     5
388 #define I40E_GLFCOE_RCTL_ICRC_MASK      I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT)
389 #define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
390 #define I40E_GLFCOE_RCTL_MAX_SIZE_MASK  I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
391 #define I40E_GL_FWSTS             0x00083048 /* Reset: POR */
392 #define I40E_GL_FWSTS_FWS0B_SHIFT 0
393 #define I40E_GL_FWSTS_FWS0B_MASK  I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT)
394 #define I40E_GL_FWSTS_FWRI_SHIFT  9
395 #define I40E_GL_FWSTS_FWRI_MASK   I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT)
396 #define I40E_GL_FWSTS_FWS1B_SHIFT 16
397 #define I40E_GL_FWSTS_FWS1B_MASK  I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT)
398 #define I40E_GLGEN_CLKSTAT                    0x000B8184 /* Reset: POR */
399 #define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT      0
400 #define I40E_GLGEN_CLKSTAT_CLKMODE_MASK       I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
401 #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT  4
402 #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK   I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
403 #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
404 #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
405 #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
406 #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
407 #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16
408 #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
409 #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
410 #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK  I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
411 #define I40E_GLGEN_GPIO_CTL(_i)                (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */
412 #define I40E_GLGEN_GPIO_CTL_MAX_INDEX          29
413 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT      0
414 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK       I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
415 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT   3
416 #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK    I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
417 #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT      4
418 #define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK       I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
419 #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT      5
420 #define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK       I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
421 #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT      6
422 #define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK       I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
423 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT     7
424 #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK      I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
425 #define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT    10
426 #define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK     I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
427 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT    11
428 #define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK     I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
429 #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT     12
430 #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK      I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
431 #define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT     17
432 #define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK      I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
433 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT  19
434 #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
435 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
436 #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK  I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
437 #define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT  26
438 #define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK   I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT)
439 #define I40E_GLGEN_GPIO_SET                 0x00088184 /* Reset: POR */
440 #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
441 #define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK  I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
442 #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT  5
443 #define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK   I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
444 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
445 #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK  I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
446 #define I40E_GLGEN_GPIO_STAT                  0x0008817C /* Reset: POR */
447 #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
448 #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK  I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
449 #define I40E_GLGEN_GPIO_TRANSIT                       0x00088180 /* Reset: POR */
450 #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
451 #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK  I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
452 #define I40E_GLGEN_I2CCMD(_i)          (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
453 #define I40E_GLGEN_I2CCMD_MAX_INDEX    3
454 #define I40E_GLGEN_I2CCMD_DATA_SHIFT   0
455 #define I40E_GLGEN_I2CCMD_DATA_MASK    I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT)
456 #define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16
457 #define I40E_GLGEN_I2CCMD_REGADD_MASK  I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT)
458 #define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24
459 #define I40E_GLGEN_I2CCMD_PHYADD_MASK  I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
460 #define I40E_GLGEN_I2CCMD_OP_SHIFT     27
461 #define I40E_GLGEN_I2CCMD_OP_MASK      I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT)
462 #define I40E_GLGEN_I2CCMD_RESET_SHIFT  28
463 #define I40E_GLGEN_I2CCMD_RESET_MASK   I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT)
464 #define I40E_GLGEN_I2CCMD_R_SHIFT      29
465 #define I40E_GLGEN_I2CCMD_R_MASK       I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT)
466 #define I40E_GLGEN_I2CCMD_E_SHIFT      31
467 #define I40E_GLGEN_I2CCMD_E_MASK       I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT)
468 #define I40E_GLGEN_I2CPARAMS(_i)                   (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
469 #define I40E_GLGEN_I2CPARAMS_MAX_INDEX             3
470 #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT      0
471 #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK       I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
472 #define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT       5
473 #define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK        I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
474 #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT        8
475 #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK         I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
476 #define I40E_GLGEN_I2CPARAMS_CLK_SHIFT             9
477 #define I40E_GLGEN_I2CPARAMS_CLK_MASK              I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
478 #define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT        10
479 #define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK         I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
480 #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT       11
481 #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK        I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
482 #define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT         12
483 #define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK          I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
484 #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT        13
485 #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK         I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
486 #define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT          14
487 #define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK           I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
488 #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15
489 #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK  I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
490 #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT  31
491 #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK   I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
492 #define I40E_GLGEN_LED_CTL                          0x00088178 /* Reset: POR */
493 #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT  0
494 #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK   I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
495 #define I40E_GLGEN_MDIO_CTRL(_i)                (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
496 #define I40E_GLGEN_MDIO_CTRL_MAX_INDEX          3
497 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
498 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK  I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
499 #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT      17
500 #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK       I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
501 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
502 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK  I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
503 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29
504 #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK  I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT)
505 #define I40E_GLGEN_MDIO_I2C_SEL(_i)                (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
506 #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX          3
507 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
508 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK  I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
509 #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1
510 #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK  I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
511 #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5
512 #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK  I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
513 #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10
514 #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK  I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
515 #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15
516 #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK  I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
517 #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20
518 #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK  I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
519 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25
520 #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK  I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
521 #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
522 #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK  I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
523 #define I40E_GLGEN_MSCA(_i)               (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
524 #define I40E_GLGEN_MSCA_MAX_INDEX         3
525 #define I40E_GLGEN_MSCA_MDIADD_SHIFT      0
526 #define I40E_GLGEN_MSCA_MDIADD_MASK       I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT)
527 #define I40E_GLGEN_MSCA_DEVADD_SHIFT      16
528 #define I40E_GLGEN_MSCA_DEVADD_MASK       I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT)
529 #define I40E_GLGEN_MSCA_PHYADD_SHIFT      21
530 #define I40E_GLGEN_MSCA_PHYADD_MASK       I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT)
531 #define I40E_GLGEN_MSCA_OPCODE_SHIFT      26
532 #define I40E_GLGEN_MSCA_OPCODE_MASK       I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT)
533 #define I40E_GLGEN_MSCA_STCODE_SHIFT      28
534 #define I40E_GLGEN_MSCA_STCODE_MASK       I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT)
535 #define I40E_GLGEN_MSCA_MDICMD_SHIFT      30
536 #define I40E_GLGEN_MSCA_MDICMD_MASK       I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
537 #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
538 #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK  I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
539 #define I40E_GLGEN_MSRWD(_i)             (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
540 #define I40E_GLGEN_MSRWD_MAX_INDEX       3
541 #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
542 #define I40E_GLGEN_MSRWD_MDIWRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
543 #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
544 #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
545 #define I40E_GLGEN_PCIFCNCNT                0x001C0AB4 /* Reset: PCIR */
546 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
547 #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK  I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
548 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
549 #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK  I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
550 #define I40E_GLGEN_RSTAT                   0x000B8188 /* Reset: POR */
551 #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT    0
552 #define I40E_GLGEN_RSTAT_DEVSTATE_MASK     I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
553 #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT  2
554 #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK   I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
555 #define I40E_GLGEN_RSTAT_CORERCNT_SHIFT    4
556 #define I40E_GLGEN_RSTAT_CORERCNT_MASK     I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
557 #define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT    6
558 #define I40E_GLGEN_RSTAT_GLOBRCNT_MASK     I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
559 #define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT     8
560 #define I40E_GLGEN_RSTAT_EMPRCNT_MASK      I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
561 #define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
562 #define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK  I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
563 #define I40E_GLGEN_RSTCTL                   0x000B8180 /* Reset: POR */
564 #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT     0
565 #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK      I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
566 #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
567 #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK  I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
568 #define I40E_GLGEN_RTRIG              0x000B8190 /* Reset: CORER */
569 #define I40E_GLGEN_RTRIG_CORER_SHIFT  0
570 #define I40E_GLGEN_RTRIG_CORER_MASK   I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT)
571 #define I40E_GLGEN_RTRIG_GLOBR_SHIFT  1
572 #define I40E_GLGEN_RTRIG_GLOBR_MASK   I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT)
573 #define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
574 #define I40E_GLGEN_RTRIG_EMPFWR_MASK  I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
575 #define I40E_GLGEN_STAT               0x000B612C /* Reset: POR */
576 #define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
577 #define I40E_GLGEN_STAT_HWRSVD0_MASK  I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT)
578 #define I40E_GLGEN_STAT_DCBEN_SHIFT   2
579 #define I40E_GLGEN_STAT_DCBEN_MASK    I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT)
580 #define I40E_GLGEN_STAT_VTEN_SHIFT    3
581 #define I40E_GLGEN_STAT_VTEN_MASK     I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT)
582 #define I40E_GLGEN_STAT_FCOEN_SHIFT   4
583 #define I40E_GLGEN_STAT_FCOEN_MASK    I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT)
584 #define I40E_GLGEN_STAT_EVBEN_SHIFT   5
585 #define I40E_GLGEN_STAT_EVBEN_MASK    I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT)
586 #define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
587 #define I40E_GLGEN_STAT_HWRSVD1_MASK  I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT)
588 #define I40E_GLGEN_VFLRSTAT(_i)         (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
589 #define I40E_GLGEN_VFLRSTAT_MAX_INDEX   3
590 #define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
591 #define I40E_GLGEN_VFLRSTAT_VFLRE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
592 #define I40E_GLVFGEN_TIMER             0x000881BC /* Reset: CORER */
593 #define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
594 #define I40E_GLVFGEN_TIMER_GTIME_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT)
595 #define I40E_PFGEN_CTRL             0x00092400 /* Reset: PFR */
596 #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
597 #define I40E_PFGEN_CTRL_PFSWR_MASK  I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT)
598 #define I40E_PFGEN_DRUN               0x00092500 /* Reset: CORER */
599 #define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
600 #define I40E_PFGEN_DRUN_DRVUNLD_MASK  I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
601 #define I40E_PFGEN_PORTNUM                0x001C0480 /* Reset: CORER */
602 #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
603 #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK  I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
604 #define I40E_PFGEN_STATE                  0x00088000 /* Reset: CORER */
605 #define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0
606 #define I40E_PFGEN_STATE_RESERVED_0_MASK  I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT)
607 #define I40E_PFGEN_STATE_PFFCEN_SHIFT     1
608 #define I40E_PFGEN_STATE_PFFCEN_MASK      I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT)
609 #define I40E_PFGEN_STATE_PFLINKEN_SHIFT   2
610 #define I40E_PFGEN_STATE_PFLINKEN_MASK    I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT)
611 #define I40E_PFGEN_STATE_PFSCEN_SHIFT     3
612 #define I40E_PFGEN_STATE_PFSCEN_MASK      I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT)
613 #define I40E_PRTGEN_CNF                      0x000B8120 /* Reset: POR */
614 #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT       0
615 #define I40E_PRTGEN_CNF_PORT_DIS_MASK        I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
616 #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
617 #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK  I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
618 #define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT   2
619 #define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK    I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
620 #define I40E_PRTGEN_CNF2                          0x000B8160 /* Reset: POR */
621 #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
622 #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK  I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
623 #define I40E_PRTGEN_STATUS                   0x000B8100 /* Reset: POR */
624 #define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT  0
625 #define I40E_PRTGEN_STATUS_PORT_VALID_MASK   I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
626 #define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
627 #define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK  I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
628 #define I40E_VFGEN_RSTAT1(_VF)            (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
629 #define I40E_VFGEN_RSTAT1_MAX_INDEX       127
630 #define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
631 #define I40E_VFGEN_RSTAT1_VFR_STATE_MASK  I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
632 #define I40E_VPGEN_VFRSTAT(_VF)       (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
633 #define I40E_VPGEN_VFRSTAT_MAX_INDEX  127
634 #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
635 #define I40E_VPGEN_VFRSTAT_VFRD_MASK  I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
636 #define I40E_VPGEN_VFRTRIG(_VF)        (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
637 #define I40E_VPGEN_VFRTRIG_MAX_INDEX   127
638 #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
639 #define I40E_VPGEN_VFRTRIG_VFSWR_MASK  I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
640 #define I40E_VSIGEN_RSTAT(_VSI)      (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
641 #define I40E_VSIGEN_RSTAT_MAX_INDEX  383
642 #define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
643 #define I40E_VSIGEN_RSTAT_VMRD_MASK  I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT)
644 #define I40E_VSIGEN_RTRIG(_VSI)       (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */
645 #define I40E_VSIGEN_RTRIG_MAX_INDEX   383
646 #define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
647 #define I40E_VSIGEN_RTRIG_VMSWR_MASK  I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
648 #define I40E_GLHMC_FCOEDDPBASE(_i)                  (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
649 #define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX            15
650 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
651 #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
652 #define I40E_GLHMC_FCOEDDPCNT(_i)                 (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
653 #define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX           15
654 #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
655 #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK  I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
656 #define I40E_GLHMC_FCOEDDPOBJSZ                      0x000C2010 /* Reset: CORER */
657 #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
658 #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
659 #define I40E_GLHMC_FCOEFBASE(_i)                (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
660 #define I40E_GLHMC_FCOEFBASE_MAX_INDEX          15
661 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
662 #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
663 #define I40E_GLHMC_FCOEFCNT(_i)               (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
664 #define I40E_GLHMC_FCOEFCNT_MAX_INDEX         15
665 #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
666 #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK  I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
667 #define I40E_GLHMC_FCOEFMAX                  0x000C20D0 /* Reset: CORER */
668 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
669 #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK  I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
670 #define I40E_GLHMC_FCOEFOBJSZ                    0x000C2018 /* Reset: CORER */
671 #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
672 #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
673 #define I40E_GLHMC_FCOEMAX                 0x000C2014 /* Reset: CORER */
674 #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
675 #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK  I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
676 #define I40E_GLHMC_FSIAVBASE(_i)                (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
677 #define I40E_GLHMC_FSIAVBASE_MAX_INDEX          15
678 #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
679 #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
680 #define I40E_GLHMC_FSIAVCNT(_i)               (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
681 #define I40E_GLHMC_FSIAVCNT_MAX_INDEX         15
682 #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
683 #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
684 #define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT        29
685 #define I40E_GLHMC_FSIAVCNT_RSVD_MASK         I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
686 #define I40E_GLHMC_FSIAVMAX                  0x000C2068 /* Reset: CORER */
687 #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
688 #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK  I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
689 #define I40E_GLHMC_FSIAVOBJSZ                    0x000C2064 /* Reset: CORER */
690 #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
691 #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
692 #define I40E_GLHMC_FSIMCBASE(_i)                (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
693 #define I40E_GLHMC_FSIMCBASE_MAX_INDEX          15
694 #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
695 #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
696 #define I40E_GLHMC_FSIMCCNT(_i)              (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
697 #define I40E_GLHMC_FSIMCCNT_MAX_INDEX        15
698 #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
699 #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK  I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
700 #define I40E_GLHMC_FSIMCMAX                  0x000C2060 /* Reset: CORER */
701 #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
702 #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK  I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
703 #define I40E_GLHMC_FSIMCOBJSZ                    0x000C205c /* Reset: CORER */
704 #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
705 #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
706 #define I40E_GLHMC_LANQMAX                 0x000C2008 /* Reset: CORER */
707 #define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
708 #define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
709 #define I40E_GLHMC_LANRXBASE(_i)                (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
710 #define I40E_GLHMC_LANRXBASE_MAX_INDEX          15
711 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
712 #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
713 #define I40E_GLHMC_LANRXCNT(_i)               (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
714 #define I40E_GLHMC_LANRXCNT_MAX_INDEX         15
715 #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
716 #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
717 #define I40E_GLHMC_LANRXOBJSZ                    0x000C200c /* Reset: CORER */
718 #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
719 #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
720 #define I40E_GLHMC_LANTXBASE(_i)                (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
721 #define I40E_GLHMC_LANTXBASE_MAX_INDEX          15
722 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
723 #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK  I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
724 #define I40E_GLHMC_LANTXBASE_RSVD_SHIFT         24
725 #define I40E_GLHMC_LANTXBASE_RSVD_MASK          I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
726 #define I40E_GLHMC_LANTXCNT(_i)               (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
727 #define I40E_GLHMC_LANTXCNT_MAX_INDEX         15
728 #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
729 #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK  I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
730 #define I40E_GLHMC_LANTXOBJSZ                    0x000C2004 /* Reset: CORER */
731 #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
732 #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK  I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
733 #define I40E_GLHMC_PFASSIGN(_i)                 (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
734 #define I40E_GLHMC_PFASSIGN_MAX_INDEX           15
735 #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
736 #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK  I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
737 #define I40E_GLHMC_SDPART(_i)            (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
738 #define I40E_GLHMC_SDPART_MAX_INDEX      15
739 #define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
740 #define I40E_GLHMC_SDPART_PMSDBASE_MASK  I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
741 #define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
742 #define I40E_GLHMC_SDPART_PMSDSIZE_MASK  I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
743 #define I40E_PFHMC_ERRORDATA                      0x000C0500 /* Reset: PFR */
744 #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
745 #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK  I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
746 #define I40E_PFHMC_ERRORINFO                       0x000C0400 /* Reset: PFR */
747 #define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT       0
748 #define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK        I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
749 #define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT        7
750 #define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK         I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
751 #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT  8
752 #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK   I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
753 #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16
754 #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK  I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
755 #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT  31
756 #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK   I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
757 #define I40E_PFHMC_PDINV               0x000C0300 /* Reset: PFR */
758 #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
759 #define I40E_PFHMC_PDINV_PMSDIDX_MASK  I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
760 #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
761 #define I40E_PFHMC_PDINV_PMPDIDX_MASK  I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
762 #define I40E_PFHMC_SDCMD               0x000C0000 /* Reset: PFR */
763 #define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
764 #define I40E_PFHMC_SDCMD_PMSDIDX_MASK  I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
765 #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT  31
766 #define I40E_PFHMC_SDCMD_PMSDWR_MASK   I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
767 #define I40E_PFHMC_SDDATAHIGH                    0x000C0200 /* Reset: PFR */
768 #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
769 #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
770 #define I40E_PFHMC_SDDATALOW                   0x000C0100 /* Reset: PFR */
771 #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT   0
772 #define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK    I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
773 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT    1
774 #define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK     I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
775 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
776 #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK  I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
777 #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
778 #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK  I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
779 #define I40E_GL_GP_FUSE(_i)              (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */
780 #define I40E_GL_GP_FUSE_MAX_INDEX        28
781 #define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0
782 #define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT)
783 #define I40E_GL_UFUSE                        0x00094008 /* Reset: POR */
784 #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
785 #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK  I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
786 #define I40E_GL_UFUSE_NIC_ID_SHIFT           2
787 #define I40E_GL_UFUSE_NIC_ID_MASK            I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT)
788 #define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT      10
789 #define I40E_GL_UFUSE_ULT_LOCKOUT_MASK       I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
790 #define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT      11
791 #define I40E_GL_UFUSE_CLS_LOCKOUT_MASK       I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
792 #define I40E_EMPINT_GPIO_ENA                  0x00088188 /* Reset: POR */
793 #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT  0
794 #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
795 #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT  1
796 #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
797 #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT  2
798 #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
799 #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT  3
800 #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
801 #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT  4
802 #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
803 #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT  5
804 #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
805 #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT  6
806 #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
807 #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT  7
808 #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
809 #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT  8
810 #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
811 #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT  9
812 #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK   I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
813 #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
814 #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
815 #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
816 #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
817 #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
818 #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
819 #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
820 #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
821 #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
822 #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
823 #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
824 #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
825 #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
826 #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
827 #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
828 #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
829 #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
830 #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
831 #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
832 #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
833 #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
834 #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
835 #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
836 #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
837 #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
838 #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
839 #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
840 #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
841 #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
842 #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
843 #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
844 #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
845 #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
846 #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
847 #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
848 #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
849 #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
850 #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
851 #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
852 #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK  I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
853 #define I40E_PFGEN_PORTMDIO_NUM                       0x0003F100 /* Reset: CORER */
854 #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT        0
855 #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK         I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
856 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
857 #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK  I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
858 #define I40E_PFINT_AEQCTL                  0x00038700 /* Reset: CORER */
859 #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT  0
860 #define I40E_PFINT_AEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
861 #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT   11
862 #define I40E_PFINT_AEQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
863 #define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13
864 #define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
865 #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT  30
866 #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
867 #define I40E_PFINT_AEQCTL_INTEVENT_SHIFT   31
868 #define I40E_PFINT_AEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
869 #define I40E_PFINT_CEQCTL(_INTPF)          (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */
870 #define I40E_PFINT_CEQCTL_MAX_INDEX        511
871 #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT  0
872 #define I40E_PFINT_CEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
873 #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT   11
874 #define I40E_PFINT_CEQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
875 #define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13
876 #define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
877 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
878 #define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
879 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
880 #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK  I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
881 #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT  30
882 #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
883 #define I40E_PFINT_CEQCTL_INTEVENT_SHIFT   31
884 #define I40E_PFINT_CEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
885 #define I40E_GLINT_CTL				0x0003F800 /* Reset: CORER */
886 #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT	0
887 #define I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK	I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_PF0_SHIFT)
888 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT	1
889 #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK	I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT)
890 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT	2
891 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK	I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_N_SHIFT)
892 #define I40E_PFINT_DYN_CTL0                       0x00038480 /* Reset: PFR */
893 #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT          0
894 #define I40E_PFINT_DYN_CTL0_INTENA_MASK           I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
895 #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT        1
896 #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK         I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
897 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT      2
898 #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
899 #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT        3
900 #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK         I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
901 #define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT        5
902 #define I40E_PFINT_DYN_CTL0_INTERVAL_MASK         I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
903 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
904 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
905 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT     25
906 #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
907 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT      31
908 #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
909 #define I40E_PFINT_DYN_CTLN(_INTPF)               (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
910 #define I40E_PFINT_DYN_CTLN_MAX_INDEX             511
911 #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT          0
912 #define I40E_PFINT_DYN_CTLN_INTENA_MASK           I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
913 #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT        1
914 #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK         I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
915 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT      2
916 #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
917 #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT        3
918 #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK         I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
919 #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT        5
920 #define I40E_PFINT_DYN_CTLN_INTERVAL_MASK         I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
921 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
922 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
923 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT     25
924 #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
925 #define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT      31
926 #define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
927 #define I40E_PFINT_GPIO_ENA                  0x00088080 /* Reset: CORER */
928 #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT  0
929 #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
930 #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT  1
931 #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
932 #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT  2
933 #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
934 #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT  3
935 #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
936 #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT  4
937 #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
938 #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT  5
939 #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
940 #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT  6
941 #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
942 #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT  7
943 #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
944 #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT  8
945 #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
946 #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT  9
947 #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK   I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
948 #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
949 #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
950 #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
951 #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
952 #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
953 #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
954 #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
955 #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
956 #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
957 #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
958 #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
959 #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
960 #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
961 #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
962 #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
963 #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
964 #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
965 #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
966 #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
967 #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
968 #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
969 #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
970 #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
971 #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
972 #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
973 #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
974 #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
975 #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
976 #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
977 #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
978 #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
979 #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
980 #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
981 #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
982 #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
983 #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
984 #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
985 #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
986 #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
987 #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
988 #define I40E_PFINT_ICR0                        0x00038780 /* Reset: CORER */
989 #define I40E_PFINT_ICR0_INTEVENT_SHIFT         0
990 #define I40E_PFINT_ICR0_INTEVENT_MASK          I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT)
991 #define I40E_PFINT_ICR0_QUEUE_0_SHIFT          1
992 #define I40E_PFINT_ICR0_QUEUE_0_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT)
993 #define I40E_PFINT_ICR0_QUEUE_1_SHIFT          2
994 #define I40E_PFINT_ICR0_QUEUE_1_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT)
995 #define I40E_PFINT_ICR0_QUEUE_2_SHIFT          3
996 #define I40E_PFINT_ICR0_QUEUE_2_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT)
997 #define I40E_PFINT_ICR0_QUEUE_3_SHIFT          4
998 #define I40E_PFINT_ICR0_QUEUE_3_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT)
999 #define I40E_PFINT_ICR0_QUEUE_4_SHIFT          5
1000 #define I40E_PFINT_ICR0_QUEUE_4_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT)
1001 #define I40E_PFINT_ICR0_QUEUE_5_SHIFT          6
1002 #define I40E_PFINT_ICR0_QUEUE_5_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT)
1003 #define I40E_PFINT_ICR0_QUEUE_6_SHIFT          7
1004 #define I40E_PFINT_ICR0_QUEUE_6_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT)
1005 #define I40E_PFINT_ICR0_QUEUE_7_SHIFT          8
1006 #define I40E_PFINT_ICR0_QUEUE_7_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT)
1007 #define I40E_PFINT_ICR0_ECC_ERR_SHIFT          16
1008 #define I40E_PFINT_ICR0_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT)
1009 #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT       19
1010 #define I40E_PFINT_ICR0_MAL_DETECT_MASK        I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
1011 #define I40E_PFINT_ICR0_GRST_SHIFT             20
1012 #define I40E_PFINT_ICR0_GRST_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT)
1013 #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT    21
1014 #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK     I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
1015 #define I40E_PFINT_ICR0_GPIO_SHIFT             22
1016 #define I40E_PFINT_ICR0_GPIO_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT)
1017 #define I40E_PFINT_ICR0_TIMESYNC_SHIFT         23
1018 #define I40E_PFINT_ICR0_TIMESYNC_MASK          I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT)
1019 #define I40E_PFINT_ICR0_STORM_DETECT_SHIFT     24
1020 #define I40E_PFINT_ICR0_STORM_DETECT_MASK      I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
1021 #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1022 #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1023 #define I40E_PFINT_ICR0_HMC_ERR_SHIFT          26
1024 #define I40E_PFINT_ICR0_HMC_ERR_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT)
1025 #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT       28
1026 #define I40E_PFINT_ICR0_PE_CRITERR_MASK        I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
1027 #define I40E_PFINT_ICR0_VFLR_SHIFT             29
1028 #define I40E_PFINT_ICR0_VFLR_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT)
1029 #define I40E_PFINT_ICR0_ADMINQ_SHIFT           30
1030 #define I40E_PFINT_ICR0_ADMINQ_MASK            I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT)
1031 #define I40E_PFINT_ICR0_SWINT_SHIFT            31
1032 #define I40E_PFINT_ICR0_SWINT_MASK             I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT)
1033 #define I40E_PFINT_ICR0_ENA                        0x00038800 /* Reset: CORER */
1034 #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT          16
1035 #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
1036 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT       19
1037 #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK        I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
1038 #define I40E_PFINT_ICR0_ENA_GRST_SHIFT             20
1039 #define I40E_PFINT_ICR0_ENA_GRST_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT)
1040 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT    21
1041 #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK     I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
1042 #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT             22
1043 #define I40E_PFINT_ICR0_ENA_GPIO_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
1044 #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT         23
1045 #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK          I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
1046 #define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT     24
1047 #define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK      I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
1048 #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1049 #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1050 #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT          26
1051 #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK           I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
1052 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT       28
1053 #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK        I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
1054 #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT             29
1055 #define I40E_PFINT_ICR0_ENA_VFLR_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
1056 #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT           30
1057 #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK            I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
1058 #define I40E_PFINT_ICR0_ENA_RSVD_SHIFT             31
1059 #define I40E_PFINT_ICR0_ENA_RSVD_MASK              I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
1060 #define I40E_PFINT_ITR0(_i)            (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */
1061 #define I40E_PFINT_ITR0_MAX_INDEX      2
1062 #define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
1063 #define I40E_PFINT_ITR0_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT)
1064 #define I40E_PFINT_ITRN(_i, _INTPF)     (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */
1065 #define I40E_PFINT_ITRN_MAX_INDEX      2
1066 #define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
1067 #define I40E_PFINT_ITRN_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT)
1068 #define I40E_PFINT_LNKLST0                   0x00038500 /* Reset: PFR */
1069 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1070 #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1071 #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1072 #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1073 #define I40E_PFINT_LNKLSTN(_INTPF)           (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1074 #define I40E_PFINT_LNKLSTN_MAX_INDEX         511
1075 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1076 #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1077 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1078 #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1079 #define I40E_PFINT_RATE0                 0x00038580 /* Reset: PFR */
1080 #define I40E_PFINT_RATE0_INTERVAL_SHIFT  0
1081 #define I40E_PFINT_RATE0_INTERVAL_MASK   I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT)
1082 #define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
1083 #define I40E_PFINT_RATE0_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
1084 #define I40E_PFINT_RATEN(_INTPF)         (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */
1085 #define I40E_PFINT_RATEN_MAX_INDEX       511
1086 #define I40E_PFINT_RATEN_INTERVAL_SHIFT  0
1087 #define I40E_PFINT_RATEN_INTERVAL_MASK   I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT)
1088 #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
1089 #define I40E_PFINT_RATEN_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
1090 #define I40E_PFINT_STAT_CTL0                      0x00038400 /* Reset: CORER */
1091 #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1092 #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK  I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1093 #define I40E_QINT_RQCTL(_Q)              (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1094 #define I40E_QINT_RQCTL_MAX_INDEX        1535
1095 #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT  0
1096 #define I40E_QINT_RQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
1097 #define I40E_QINT_RQCTL_ITR_INDX_SHIFT   11
1098 #define I40E_QINT_RQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT)
1099 #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13
1100 #define I40E_QINT_RQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
1101 #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
1102 #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
1103 #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
1104 #define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK  I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
1105 #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT  30
1106 #define I40E_QINT_RQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
1107 #define I40E_QINT_RQCTL_INTEVENT_SHIFT   31
1108 #define I40E_QINT_RQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT)
1109 #define I40E_QINT_TQCTL(_Q)              (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1110 #define I40E_QINT_TQCTL_MAX_INDEX        1535
1111 #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT  0
1112 #define I40E_QINT_TQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
1113 #define I40E_QINT_TQCTL_ITR_INDX_SHIFT   11
1114 #define I40E_QINT_TQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT)
1115 #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13
1116 #define I40E_QINT_TQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
1117 #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
1118 #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
1119 #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
1120 #define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK  I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
1121 #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT  30
1122 #define I40E_QINT_TQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
1123 #define I40E_QINT_TQCTL_INTEVENT_SHIFT   31
1124 #define I40E_QINT_TQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT)
1125 #define I40E_VFINT_DYN_CTL0(_VF)                  (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1126 #define I40E_VFINT_DYN_CTL0_MAX_INDEX             127
1127 #define I40E_VFINT_DYN_CTL0_INTENA_SHIFT          0
1128 #define I40E_VFINT_DYN_CTL0_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
1129 #define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT        1
1130 #define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK         I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
1131 #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT      2
1132 #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1133 #define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT        3
1134 #define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK         I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
1135 #define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT        5
1136 #define I40E_VFINT_DYN_CTL0_INTERVAL_MASK         I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
1137 #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1138 #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK  I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1139 #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT     25
1140 #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1141 #define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT      31
1142 #define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1143 #define I40E_VFINT_DYN_CTLN(_INTVF)               (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1144 #define I40E_VFINT_DYN_CTLN_MAX_INDEX             511
1145 #define I40E_VFINT_DYN_CTLN_INTENA_SHIFT          0
1146 #define I40E_VFINT_DYN_CTLN_INTENA_MASK           I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
1147 #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT        1
1148 #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK         I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
1149 #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT      2
1150 #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1151 #define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT        3
1152 #define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK         I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
1153 #define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT        5
1154 #define I40E_VFINT_DYN_CTLN_INTERVAL_MASK         I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
1155 #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1156 #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK  I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1157 #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT     25
1158 #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK      I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1159 #define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT      31
1160 #define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK       I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1161 #define I40E_VFINT_ICR0(_VF)                   (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1162 #define I40E_VFINT_ICR0_MAX_INDEX              127
1163 #define I40E_VFINT_ICR0_INTEVENT_SHIFT         0
1164 #define I40E_VFINT_ICR0_INTEVENT_MASK          I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT)
1165 #define I40E_VFINT_ICR0_QUEUE_0_SHIFT          1
1166 #define I40E_VFINT_ICR0_QUEUE_0_MASK           I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT)
1167 #define I40E_VFINT_ICR0_QUEUE_1_SHIFT          2
1168 #define I40E_VFINT_ICR0_QUEUE_1_MASK           I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT)
1169 #define I40E_VFINT_ICR0_QUEUE_2_SHIFT          3
1170 #define I40E_VFINT_ICR0_QUEUE_2_MASK           I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT)
1171 #define I40E_VFINT_ICR0_QUEUE_3_SHIFT          4
1172 #define I40E_VFINT_ICR0_QUEUE_3_MASK           I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT)
1173 #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1174 #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1175 #define I40E_VFINT_ICR0_ADMINQ_SHIFT           30
1176 #define I40E_VFINT_ICR0_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT)
1177 #define I40E_VFINT_ICR0_SWINT_SHIFT            31
1178 #define I40E_VFINT_ICR0_SWINT_MASK             I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT)
1179 #define I40E_VFINT_ICR0_ENA(_VF)                   (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1180 #define I40E_VFINT_ICR0_ENA_MAX_INDEX              127
1181 #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1182 #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK  I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1183 #define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT           30
1184 #define I40E_VFINT_ICR0_ENA_ADMINQ_MASK            I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
1185 #define I40E_VFINT_ICR0_ENA_RSVD_SHIFT             31
1186 #define I40E_VFINT_ICR0_ENA_RSVD_MASK              I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
1187 #define I40E_VFINT_ITR0(_i, _VF)        (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */
1188 #define I40E_VFINT_ITR0_MAX_INDEX      2
1189 #define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
1190 #define I40E_VFINT_ITR0_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT)
1191 #define I40E_VFINT_ITRN(_i, _INTVF)     (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */
1192 #define I40E_VFINT_ITRN_MAX_INDEX      2
1193 #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
1194 #define I40E_VFINT_ITRN_INTERVAL_MASK  I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT)
1195 #define I40E_VFINT_STAT_CTL0(_VF)                 (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1196 #define I40E_VFINT_STAT_CTL0_MAX_INDEX            127
1197 #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1198 #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK  I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1199 #define I40E_VPINT_AEQCTL(_VF)             (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
1200 #define I40E_VPINT_AEQCTL_MAX_INDEX        127
1201 #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT  0
1202 #define I40E_VPINT_AEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
1203 #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT   11
1204 #define I40E_VPINT_AEQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
1205 #define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13
1206 #define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
1207 #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT  30
1208 #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
1209 #define I40E_VPINT_AEQCTL_INTEVENT_SHIFT   31
1210 #define I40E_VPINT_AEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
1211 #define I40E_VPINT_CEQCTL(_INTVF)          (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */
1212 #define I40E_VPINT_CEQCTL_MAX_INDEX        511
1213 #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT  0
1214 #define I40E_VPINT_CEQCTL_MSIX_INDX_MASK   I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
1215 #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT   11
1216 #define I40E_VPINT_CEQCTL_ITR_INDX_MASK    I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
1217 #define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13
1218 #define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK  I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
1219 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1220 #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
1221 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1222 #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK  I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1223 #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT  30
1224 #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK   I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
1225 #define I40E_VPINT_CEQCTL_INTEVENT_SHIFT   31
1226 #define I40E_VPINT_CEQCTL_INTEVENT_MASK    I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
1227 #define I40E_VPINT_LNKLST0(_VF)              (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1228 #define I40E_VPINT_LNKLST0_MAX_INDEX         127
1229 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1230 #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1231 #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1232 #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1233 #define I40E_VPINT_LNKLSTN(_INTVF)           (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1234 #define I40E_VPINT_LNKLSTN_MAX_INDEX         511
1235 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1236 #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK  I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1237 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1238 #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK  I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1239 #define I40E_VPINT_RATE0(_VF)            (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1240 #define I40E_VPINT_RATE0_MAX_INDEX       127
1241 #define I40E_VPINT_RATE0_INTERVAL_SHIFT  0
1242 #define I40E_VPINT_RATE0_INTERVAL_MASK   I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT)
1243 #define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
1244 #define I40E_VPINT_RATE0_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
1245 #define I40E_VPINT_RATEN(_INTVF)         (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */
1246 #define I40E_VPINT_RATEN_MAX_INDEX       511
1247 #define I40E_VPINT_RATEN_INTERVAL_SHIFT  0
1248 #define I40E_VPINT_RATEN_INTERVAL_MASK   I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT)
1249 #define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
1250 #define I40E_VPINT_RATEN_INTRL_ENA_MASK  I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
1251 #define I40E_GL_RDPU_CNTRL                 0x00051060 /* Reset: CORER */
1252 #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
1253 #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK  I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
1254 #define I40E_GL_RDPU_CNTRL_ECO_SHIFT       1
1255 #define I40E_GL_RDPU_CNTRL_ECO_MASK        I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT)
1256 #define I40E_GLLAN_RCTL_0                0x0012A500 /* Reset: CORER */
1257 #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
1258 #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK  I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
1259 #define I40E_GLLAN_TSOMSK_F               0x000442D8 /* Reset: CORER */
1260 #define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
1261 #define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
1262 #define I40E_GLLAN_TSOMSK_L               0x000442E0 /* Reset: CORER */
1263 #define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
1264 #define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
1265 #define I40E_GLLAN_TSOMSK_M               0x000442DC /* Reset: CORER */
1266 #define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
1267 #define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK  I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
1268 #define I40E_GLLAN_TXPRE_QDIS(_i)              (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */
1269 #define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX        11
1270 #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT      0
1271 #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK       I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT)
1272 #define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT  16
1273 #define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK   I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT)
1274 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT   30
1275 #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK    I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
1276 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
1277 #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK  I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
1278 #define I40E_PFLAN_QALLOC              0x001C0400 /* Reset: CORER */
1279 #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
1280 #define I40E_PFLAN_QALLOC_FIRSTQ_MASK  I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
1281 #define I40E_PFLAN_QALLOC_LASTQ_SHIFT  16
1282 #define I40E_PFLAN_QALLOC_LASTQ_MASK   I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
1283 #define I40E_PFLAN_QALLOC_VALID_SHIFT  31
1284 #define I40E_PFLAN_QALLOC_VALID_MASK   I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
1285 #define I40E_QRX_ENA(_Q)             (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1286 #define I40E_QRX_ENA_MAX_INDEX       1535
1287 #define I40E_QRX_ENA_QENA_REQ_SHIFT  0
1288 #define I40E_QRX_ENA_QENA_REQ_MASK   I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT)
1289 #define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
1290 #define I40E_QRX_ENA_FAST_QDIS_MASK  I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT)
1291 #define I40E_QRX_ENA_QENA_STAT_SHIFT 2
1292 #define I40E_QRX_ENA_QENA_STAT_MASK  I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT)
1293 #define I40E_QRX_TAIL(_Q)        (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1294 #define I40E_QRX_TAIL_MAX_INDEX  1535
1295 #define I40E_QRX_TAIL_TAIL_SHIFT 0
1296 #define I40E_QRX_TAIL_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT)
1297 #define I40E_QTX_CTL(_Q)             (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1298 #define I40E_QTX_CTL_MAX_INDEX       1535
1299 #define I40E_QTX_CTL_PFVF_Q_SHIFT    0
1300 #define I40E_QTX_CTL_PFVF_Q_MASK     I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT)
1301 #define I40E_QTX_CTL_PF_INDX_SHIFT   2
1302 #define I40E_QTX_CTL_PF_INDX_MASK    I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT)
1303 #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
1304 #define I40E_QTX_CTL_VFVM_INDX_MASK  I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT)
1305 #define I40E_QTX_ENA(_Q)             (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1306 #define I40E_QTX_ENA_MAX_INDEX       1535
1307 #define I40E_QTX_ENA_QENA_REQ_SHIFT  0
1308 #define I40E_QTX_ENA_QENA_REQ_MASK   I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT)
1309 #define I40E_QTX_ENA_FAST_QDIS_SHIFT 1
1310 #define I40E_QTX_ENA_FAST_QDIS_MASK  I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT)
1311 #define I40E_QTX_ENA_QENA_STAT_SHIFT 2
1312 #define I40E_QTX_ENA_QENA_STAT_MASK  I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT)
1313 #define I40E_QTX_HEAD(_Q)              (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */
1314 #define I40E_QTX_HEAD_MAX_INDEX        1535
1315 #define I40E_QTX_HEAD_HEAD_SHIFT       0
1316 #define I40E_QTX_HEAD_HEAD_MASK        I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT)
1317 #define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
1318 #define I40E_QTX_HEAD_RS_PENDING_MASK  I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT)
1319 #define I40E_QTX_TAIL(_Q)        (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
1320 #define I40E_QTX_TAIL_MAX_INDEX  1535
1321 #define I40E_QTX_TAIL_TAIL_SHIFT 0
1322 #define I40E_QTX_TAIL_TAIL_MASK  I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT)
1323 #define I40E_VPLAN_MAPENA(_VF)           (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */
1324 #define I40E_VPLAN_MAPENA_MAX_INDEX      127
1325 #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
1326 #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK  I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
1327 #define I40E_VPLAN_QTABLE(_i, _VF)      (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */
1328 #define I40E_VPLAN_QTABLE_MAX_INDEX    15
1329 #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
1330 #define I40E_VPLAN_QTABLE_QINDEX_MASK  I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT)
1331 #define I40E_VSILAN_QBASE(_VSI)               (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */
1332 #define I40E_VSILAN_QBASE_MAX_INDEX           383
1333 #define I40E_VSILAN_QBASE_VSIBASE_SHIFT       0
1334 #define I40E_VSILAN_QBASE_VSIBASE_MASK        I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT)
1335 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
1336 #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK  I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
1337 #define I40E_VSILAN_QTABLE(_i, _VSI)       (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */
1338 #define I40E_VSILAN_QTABLE_MAX_INDEX      7
1339 #define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
1340 #define I40E_VSILAN_QTABLE_QINDEX_0_MASK  I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
1341 #define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
1342 #define I40E_VSILAN_QTABLE_QINDEX_1_MASK  I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
1343 #define I40E_PRTGL_SAH              0x001E2140 /* Reset: GLOBR */
1344 #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
1345 #define I40E_PRTGL_SAH_FC_SAH_MASK  I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT)
1346 #define I40E_PRTGL_SAH_MFS_SHIFT    16
1347 #define I40E_PRTGL_SAH_MFS_MASK     I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT)
1348 #define I40E_PRTGL_SAL              0x001E2120 /* Reset: GLOBR */
1349 #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
1350 #define I40E_PRTGL_SAL_FC_SAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT)
1351 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP                              0x001E30E0 /* Reset: GLOBR */
1352 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
1353 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
1354 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP                              0x001E3260 /* Reset: GLOBR */
1355 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
1356 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
1357 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP                              0x001E32E0 /* Reset: GLOBR */
1358 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
1359 #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
1360 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL                                   0x001E3360 /* Reset: GLOBR */
1361 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
1362 #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK  I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
1363 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1                                        0x001E3110 /* Reset: GLOBR */
1364 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
1365 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
1366 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2                                        0x001E3120 /* Reset: GLOBR */
1367 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
1368 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
1369 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE                                0x001E30C0 /* Reset: GLOBR */
1370 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
1371 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK  I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
1372 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1                                  0x001E3140 /* Reset: GLOBR */
1373 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
1374 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
1375 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2                                  0x001E3150 /* Reset: GLOBR */
1376 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
1377 #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
1378 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE                                0x001E30D0 /* Reset: GLOBR */
1379 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
1380 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK  I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
1381 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i)                            (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1382 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX                      8
1383 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
1384 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
1385 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i)                                   (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */
1386 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX                             8
1387 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
1388 #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
1389 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1                            0x001E34B0 /* Reset: GLOBR */
1390 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
1391 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
1392 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2                            0x001E34C0 /* Reset: GLOBR */
1393 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
1394 #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK  I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
1395 #define I40E_PRTMAC_PCS_XAUI_SWAP_A                     0x0008C480 /* Reset: GLOBR */
1396 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
1397 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
1398 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
1399 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
1400 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4
1401 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
1402 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6
1403 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
1404 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8
1405 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
1406 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10
1407 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
1408 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12
1409 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
1410 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
1411 #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
1412 #define I40E_PRTMAC_PCS_XAUI_SWAP_B                     0x0008C484 /* Reset: GLOBR */
1413 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
1414 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
1415 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
1416 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
1417 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4
1418 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
1419 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6
1420 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
1421 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8
1422 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
1423 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10
1424 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
1425 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12
1426 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
1427 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
1428 #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK  I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
1429 #define I40E_GL_FWRESETCNT                  0x00083100 /* Reset: POR */
1430 #define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0
1431 #define I40E_GL_FWRESETCNT_FWRESETCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT)
1432 #define I40E_GL_MNG_FWSM                              0x000B6134 /* Reset: POR */
1433 #define I40E_GL_MNG_FWSM_FW_MODES_SHIFT               0
1434 #define I40E_GL_MNG_FWSM_FW_MODES_MASK                I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
1435 #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT         10
1436 #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK          I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
1437 #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT       11
1438 #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK        I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
1439 #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT        15
1440 #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK         I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
1441 #define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT              16
1442 #define I40E_GL_MNG_FWSM_RESET_CNT_MASK               I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT)
1443 #define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT            19
1444 #define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK             I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
1445 #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
1446 #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
1447 #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
1448 #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
1449 #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28
1450 #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
1451 #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
1452 #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK  I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
1453 #define I40E_GL_MNG_HWARB_CTRL                   0x000B6130 /* Reset: POR */
1454 #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
1455 #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK  I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
1456 #define I40E_PRT_MNG_FTFT_DATA(_i)         (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */
1457 #define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX   31
1458 #define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
1459 #define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
1460 #define I40E_PRT_MNG_FTFT_LENGTH              0x00085260 /* Reset: POR */
1461 #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
1462 #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK  I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
1463 #define I40E_PRT_MNG_FTFT_MASK(_i)        (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1464 #define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX  7
1465 #define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
1466 #define I40E_PRT_MNG_FTFT_MASK_MASK_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
1467 #define I40E_PRT_MNG_MANC                            0x00256A20 /* Reset: POR */
1468 #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
1469 #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
1470 #define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT         1
1471 #define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK          I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
1472 #define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT           17
1473 #define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK            I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
1474 #define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT              19
1475 #define I40E_PRT_MNG_MANC_RCV_ALL_MASK               I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
1476 #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT       25
1477 #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK        I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
1478 #define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT             26
1479 #define I40E_PRT_MNG_MANC_NET_TYPE_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
1480 #define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT            28
1481 #define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK             I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
1482 #define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT           29
1483 #define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK            I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
1484 #define I40E_PRT_MNG_MAVTV(_i)       (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1485 #define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
1486 #define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
1487 #define I40E_PRT_MNG_MAVTV_VID_MASK  I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT)
1488 #define I40E_PRT_MNG_MDEF(_i)                             (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1489 #define I40E_PRT_MNG_MDEF_MAX_INDEX                       7
1490 #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT             0
1491 #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK              I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
1492 #define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT             4
1493 #define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
1494 #define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT                  5
1495 #define I40E_PRT_MNG_MDEF_VLAN_AND_MASK                   I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
1496 #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT          13
1497 #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK           I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
1498 #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT          17
1499 #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK           I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
1500 #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT              21
1501 #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK               I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
1502 #define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT              25
1503 #define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK               I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
1504 #define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT             26
1505 #define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
1506 #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT            27
1507 #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK             I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
1508 #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT           28
1509 #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK            I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
1510 #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29
1511 #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
1512 #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT             30
1513 #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
1514 #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT             31
1515 #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK              I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
1516 #define I40E_PRT_MNG_MDEF_EXT(_i)                             (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */
1517 #define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX                       7
1518 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT          0
1519 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK           I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
1520 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT           4
1521 #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK            I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
1522 #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT              8
1523 #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK               I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
1524 #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT                  24
1525 #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK                   I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
1526 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25
1527 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
1528 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26
1529 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
1530 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27
1531 #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
1532 #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT                   28
1533 #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK                    I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
1534 #define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT                       29
1535 #define I40E_PRT_MNG_MDEF_EXT_MLD_MASK                        I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
1536 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT  30
1537 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
1538 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT     31
1539 #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK      I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
1540 #define I40E_PRT_MNG_MDEFVSI(_i)                (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1541 #define I40E_PRT_MNG_MDEFVSI_MAX_INDEX          3
1542 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT   0
1543 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK    I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
1544 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
1545 #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
1546 #define I40E_PRT_MNG_METF(_i)            (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1547 #define I40E_PRT_MNG_METF_MAX_INDEX      3
1548 #define I40E_PRT_MNG_METF_ETYPE_SHIFT    0
1549 #define I40E_PRT_MNG_METF_ETYPE_MASK     I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT)
1550 #define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
1551 #define I40E_PRT_MNG_METF_POLARITY_MASK  I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT)
1552 #define I40E_PRT_MNG_MFUTP(_i)                      (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1553 #define I40E_PRT_MNG_MFUTP_MAX_INDEX                15
1554 #define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT            0
1555 #define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK             I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
1556 #define I40E_PRT_MNG_MFUTP_UDP_SHIFT                16
1557 #define I40E_PRT_MNG_MFUTP_UDP_MASK                 I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT)
1558 #define I40E_PRT_MNG_MFUTP_TCP_SHIFT                17
1559 #define I40E_PRT_MNG_MFUTP_TCP_MASK                 I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT)
1560 #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
1561 #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
1562 #define I40E_PRT_MNG_MIPAF4(_i)         (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1563 #define I40E_PRT_MNG_MIPAF4_MAX_INDEX   3
1564 #define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
1565 #define I40E_PRT_MNG_MIPAF4_MIPAF_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
1566 #define I40E_PRT_MNG_MIPAF6(_i)         (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */
1567 #define I40E_PRT_MNG_MIPAF6_MAX_INDEX   15
1568 #define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
1569 #define I40E_PRT_MNG_MIPAF6_MIPAF_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
1570 #define I40E_PRT_MNG_MMAH(_i)        (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1571 #define I40E_PRT_MNG_MMAH_MAX_INDEX  3
1572 #define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
1573 #define I40E_PRT_MNG_MMAH_MMAH_MASK  I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT)
1574 #define I40E_PRT_MNG_MMAL(_i)        (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */
1575 #define I40E_PRT_MNG_MMAL_MAX_INDEX  3
1576 #define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
1577 #define I40E_PRT_MNG_MMAL_MMAL_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT)
1578 #define I40E_PRT_MNG_MNGONLY                                  0x00256A60 /* Reset: POR */
1579 #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
1580 #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK  I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
1581 #define I40E_PRT_MNG_MSFM                    0x00256AA0 /* Reset: POR */
1582 #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
1583 #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
1584 #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
1585 #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
1586 #define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2
1587 #define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
1588 #define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3
1589 #define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK  I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
1590 #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT  4
1591 #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
1592 #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT  5
1593 #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
1594 #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT  6
1595 #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
1596 #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT  7
1597 #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK   I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
1598 #define I40E_MSIX_PBA(_i)          (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */
1599 #define I40E_MSIX_PBA_MAX_INDEX    5
1600 #define I40E_MSIX_PBA_PENBIT_SHIFT 0
1601 #define I40E_MSIX_PBA_PENBIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT)
1602 #define I40E_MSIX_TADD(_i)              (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1603 #define I40E_MSIX_TADD_MAX_INDEX        128
1604 #define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
1605 #define I40E_MSIX_TADD_MSIXTADD10_MASK  I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT)
1606 #define I40E_MSIX_TADD_MSIXTADD_SHIFT   2
1607 #define I40E_MSIX_TADD_MSIXTADD_MASK    I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT)
1608 #define I40E_MSIX_TMSG(_i)            (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1609 #define I40E_MSIX_TMSG_MAX_INDEX      128
1610 #define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
1611 #define I40E_MSIX_TMSG_MSIXTMSG_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
1612 #define I40E_MSIX_TUADD(_i)             (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1613 #define I40E_MSIX_TUADD_MAX_INDEX       128
1614 #define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
1615 #define I40E_MSIX_TUADD_MSIXTUADD_MASK  I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
1616 #define I40E_MSIX_TVCTRL(_i)        (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */
1617 #define I40E_MSIX_TVCTRL_MAX_INDEX  128
1618 #define I40E_MSIX_TVCTRL_MASK_SHIFT 0
1619 #define I40E_MSIX_TVCTRL_MASK_MASK  I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT)
1620 #define I40E_VFMSIX_PBA1(_i)          (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
1621 #define I40E_VFMSIX_PBA1_MAX_INDEX    19
1622 #define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
1623 #define I40E_VFMSIX_PBA1_PENBIT_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
1624 #define I40E_VFMSIX_TADD1(_i)              (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1625 #define I40E_VFMSIX_TADD1_MAX_INDEX        639
1626 #define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
1627 #define I40E_VFMSIX_TADD1_MSIXTADD10_MASK  I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
1628 #define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT   2
1629 #define I40E_VFMSIX_TADD1_MSIXTADD_MASK    I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
1630 #define I40E_VFMSIX_TMSG1(_i)            (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1631 #define I40E_VFMSIX_TMSG1_MAX_INDEX      639
1632 #define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
1633 #define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
1634 #define I40E_VFMSIX_TUADD1(_i)             (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1635 #define I40E_VFMSIX_TUADD1_MAX_INDEX       639
1636 #define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
1637 #define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK  I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
1638 #define I40E_VFMSIX_TVCTRL1(_i)        (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
1639 #define I40E_VFMSIX_TVCTRL1_MAX_INDEX  639
1640 #define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
1641 #define I40E_VFMSIX_TVCTRL1_MASK_MASK  I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
1642 #define I40E_GLNVM_FLA                0x000B6108 /* Reset: POR */
1643 #define I40E_GLNVM_FLA_FL_SCK_SHIFT   0
1644 #define I40E_GLNVM_FLA_FL_SCK_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT)
1645 #define I40E_GLNVM_FLA_FL_CE_SHIFT    1
1646 #define I40E_GLNVM_FLA_FL_CE_MASK     I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT)
1647 #define I40E_GLNVM_FLA_FL_SI_SHIFT    2
1648 #define I40E_GLNVM_FLA_FL_SI_MASK     I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT)
1649 #define I40E_GLNVM_FLA_FL_SO_SHIFT    3
1650 #define I40E_GLNVM_FLA_FL_SO_MASK     I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT)
1651 #define I40E_GLNVM_FLA_FL_REQ_SHIFT   4
1652 #define I40E_GLNVM_FLA_FL_REQ_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT)
1653 #define I40E_GLNVM_FLA_FL_GNT_SHIFT   5
1654 #define I40E_GLNVM_FLA_FL_GNT_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT)
1655 #define I40E_GLNVM_FLA_LOCKED_SHIFT   6
1656 #define I40E_GLNVM_FLA_LOCKED_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT)
1657 #define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18
1658 #define I40E_GLNVM_FLA_FL_SADDR_MASK  I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT)
1659 #define I40E_GLNVM_FLA_FL_BUSY_SHIFT  30
1660 #define I40E_GLNVM_FLA_FL_BUSY_MASK   I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT)
1661 #define I40E_GLNVM_FLA_FL_DER_SHIFT   31
1662 #define I40E_GLNVM_FLA_FL_DER_MASK    I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT)
1663 #define I40E_GLNVM_FLASHID                  0x000B6104 /* Reset: POR */
1664 #define I40E_GLNVM_FLASHID_FLASHID_SHIFT    0
1665 #define I40E_GLNVM_FLASHID_FLASHID_MASK     I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT)
1666 #define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31
1667 #define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK  I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT)
1668 #define I40E_GLNVM_GENS                  0x000B6100 /* Reset: POR */
1669 #define I40E_GLNVM_GENS_NVM_PRES_SHIFT   0
1670 #define I40E_GLNVM_GENS_NVM_PRES_MASK    I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT)
1671 #define I40E_GLNVM_GENS_SR_SIZE_SHIFT    5
1672 #define I40E_GLNVM_GENS_SR_SIZE_MASK     I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT)
1673 #define I40E_GLNVM_GENS_BANK1VAL_SHIFT   8
1674 #define I40E_GLNVM_GENS_BANK1VAL_MASK    I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT)
1675 #define I40E_GLNVM_GENS_ALT_PRST_SHIFT   23
1676 #define I40E_GLNVM_GENS_ALT_PRST_MASK    I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT)
1677 #define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
1678 #define I40E_GLNVM_GENS_FL_AUTO_RD_MASK  I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
1679 #define I40E_GLNVM_PROTCSR(_i)              (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */
1680 #define I40E_GLNVM_PROTCSR_MAX_INDEX        59
1681 #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
1682 #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK  I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
1683 #define I40E_GLNVM_SRCTL              0x000B6110 /* Reset: POR */
1684 #define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
1685 #define I40E_GLNVM_SRCTL_SRBUSY_MASK  I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
1686 #define I40E_GLNVM_SRCTL_ADDR_SHIFT   14
1687 #define I40E_GLNVM_SRCTL_ADDR_MASK    I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT)
1688 #define I40E_GLNVM_SRCTL_WRITE_SHIFT  29
1689 #define I40E_GLNVM_SRCTL_WRITE_MASK   I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT)
1690 #define I40E_GLNVM_SRCTL_START_SHIFT  30
1691 #define I40E_GLNVM_SRCTL_START_MASK   I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
1692 #define I40E_GLNVM_SRCTL_DONE_SHIFT   31
1693 #define I40E_GLNVM_SRCTL_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
1694 #define I40E_GLNVM_SRDATA              0x000B6114 /* Reset: POR */
1695 #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
1696 #define I40E_GLNVM_SRDATA_WRDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
1697 #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
1698 #define I40E_GLNVM_SRDATA_RDDATA_MASK  I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT)
1699 #define I40E_GLNVM_ULD                          0x000B6008 /* Reset: POR */
1700 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT     0
1701 #define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK      I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT)
1702 #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT   1
1703 #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT)
1704 #define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT      2
1705 #define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK       I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT)
1706 #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT     3
1707 #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK      I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT)
1708 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT   4
1709 #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT)
1710 #define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT      5
1711 #define I40E_GLNVM_ULD_CONF_POR_DONE_MASK       I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT)
1712 #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6
1713 #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK  I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT)
1714 #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT  7
1715 #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK   I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT)
1716 #define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT      8
1717 #define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK       I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT)
1718 #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT   9
1719 #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK    I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT)
1720 #define I40E_GLPCI_BYTCTH                        0x0009C484 /* Reset: PCIR */
1721 #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
1722 #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
1723 #define I40E_GLPCI_BYTCTL                        0x0009C488 /* Reset: PCIR */
1724 #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
1725 #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
1726 #define I40E_GLPCI_CAPCTRL              0x000BE4A4 /* Reset: PCIR */
1727 #define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
1728 #define I40E_GLPCI_CAPCTRL_VPD_EN_MASK  I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
1729 #define I40E_GLPCI_CAPSUP                      0x000BE4A8 /* Reset: PCIR */
1730 #define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT       0
1731 #define I40E_GLPCI_CAPSUP_PCIE_VER_MASK        I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
1732 #define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT         2
1733 #define I40E_GLPCI_CAPSUP_LTR_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
1734 #define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT         3
1735 #define I40E_GLPCI_CAPSUP_TPH_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
1736 #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT         4
1737 #define I40E_GLPCI_CAPSUP_ARI_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
1738 #define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT         5
1739 #define I40E_GLPCI_CAPSUP_IOV_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
1740 #define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT         6
1741 #define I40E_GLPCI_CAPSUP_ACS_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
1742 #define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT         7
1743 #define I40E_GLPCI_CAPSUP_SEC_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
1744 #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT    16
1745 #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK     I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
1746 #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT    17
1747 #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK     I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
1748 #define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT         18
1749 #define I40E_GLPCI_CAPSUP_IDO_EN_MASK          I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
1750 #define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT       19
1751 #define I40E_GLPCI_CAPSUP_MSI_MASK_MASK        I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
1752 #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT    20
1753 #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK     I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
1754 #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30
1755 #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK  I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
1756 #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT    31
1757 #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK     I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
1758 #define I40E_GLPCI_CNF                   0x000BE4C0 /* Reset: POR */
1759 #define I40E_GLPCI_CNF_FLEX10_SHIFT      1
1760 #define I40E_GLPCI_CNF_FLEX10_MASK       I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT)
1761 #define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
1762 #define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK  I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
1763 #define I40E_GLPCI_CNF2                      0x000BE494 /* Reset: PCIR */
1764 #define I40E_GLPCI_CNF2_RO_DIS_SHIFT         0
1765 #define I40E_GLPCI_CNF2_RO_DIS_MASK          I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT)
1766 #define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
1767 #define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK  I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
1768 #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT     2
1769 #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK      I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
1770 #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT     13
1771 #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK      I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
1772 #define I40E_GLPCI_DREVID                     0x0009C480 /* Reset: PCIR */
1773 #define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
1774 #define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK  I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
1775 #define I40E_GLPCI_GSCL_1                        0x0009C48C /* Reset: PCIR */
1776 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT   0
1777 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
1778 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT   1
1779 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
1780 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT   2
1781 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
1782 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT   3
1783 #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
1784 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT     4
1785 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK      I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
1786 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT     5
1787 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK      I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
1788 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT     6
1789 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK      I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
1790 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT     7
1791 #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK      I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
1792 #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8
1793 #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK  I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
1794 #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9
1795 #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK  I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
1796 #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT  14
1797 #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK   I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
1798 #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT  15
1799 #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK   I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
1800 #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT    28
1801 #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK     I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
1802 #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT  29
1803 #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK   I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
1804 #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT   30
1805 #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK    I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
1806 #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT  31
1807 #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK   I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
1808 #define I40E_GLPCI_GSCL_2                       0x0009C490 /* Reset: PCIR */
1809 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
1810 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
1811 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
1812 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
1813 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16
1814 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
1815 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
1816 #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK  I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
1817 #define I40E_GLPCI_GSCL_5_8(_i)                   (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
1818 #define I40E_GLPCI_GSCL_5_8_MAX_INDEX             3
1819 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
1820 #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
1821 #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT     16
1822 #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK      I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
1823 #define I40E_GLPCI_GSCN_0_3(_i)                 (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */
1824 #define I40E_GLPCI_GSCN_0_3_MAX_INDEX           3
1825 #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
1826 #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
1827 #define I40E_GLPCI_LBARCTRL                    0x000BE484 /* Reset: POR */
1828 #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT      0
1829 #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK       I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
1830 #define I40E_GLPCI_LBARCTRL_BAR32_SHIFT        1
1831 #define I40E_GLPCI_LBARCTRL_BAR32_MASK         I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
1832 #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3
1833 #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK  I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
1834 #define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT       4
1835 #define I40E_GLPCI_LBARCTRL_RSVD_4_MASK        I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT)
1836 #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT      6
1837 #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK       I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
1838 #define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT      10
1839 #define I40E_GLPCI_LBARCTRL_RSVD_10_MASK       I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT)
1840 #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT   11
1841 #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK    I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
1842 #define I40E_GLPCI_LINKCAP                          0x000BE4AC /* Reset: PCIR */
1843 #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
1844 #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK  I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
1845 #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT        6
1846 #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK         I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
1847 #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT     9
1848 #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK      I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
1849 #define I40E_GLPCI_PCIERR                    0x000BE4FC /* Reset: PCIR */
1850 #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
1851 #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
1852 #define I40E_GLPCI_PKTCT                        0x0009C4BC /* Reset: PCIR */
1853 #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
1854 #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
1855 #define I40E_GLPCI_PM_MUX_NPQ                        0x0009C4F4 /* Reset: PCIR */
1856 #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
1857 #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK  I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
1858 #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT    16
1859 #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK     I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
1860 #define I40E_GLPCI_PM_MUX_PFB                      0x0009C4F0 /* Reset: PCIR */
1861 #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT   0
1862 #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK    I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
1863 #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
1864 #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK  I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
1865 #define I40E_GLPCI_PMSUP                    0x000BE4B0 /* Reset: PCIR */
1866 #define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT     0
1867 #define I40E_GLPCI_PMSUP_ASPM_SUP_MASK      I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
1868 #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
1869 #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK  I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
1870 #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT  5
1871 #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK   I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
1872 #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT  8
1873 #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK   I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
1874 #define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT   11
1875 #define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK    I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
1876 #define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT     14
1877 #define I40E_GLPCI_PMSUP_SLOT_CLK_MASK      I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
1878 #define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT     15
1879 #define I40E_GLPCI_PMSUP_OBFF_SUP_MASK      I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
1880 #define I40E_GLPCI_PQ_MAX_USED_SPC                                0x0009C4EC /* Reset: PCIR */
1881 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0
1882 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK  I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT)
1883 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8
1884 #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK  I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT)
1885 #define I40E_GLPCI_PWRDATA                  0x000BE490 /* Reset: PCIR */
1886 #define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT   0
1887 #define I40E_GLPCI_PWRDATA_D0_POWER_MASK    I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
1888 #define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
1889 #define I40E_GLPCI_PWRDATA_COMM_POWER_MASK  I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
1890 #define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT   16
1891 #define I40E_GLPCI_PWRDATA_D3_POWER_MASK    I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
1892 #define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
1893 #define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK  I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
1894 #define I40E_GLPCI_REVID                 0x000BE4B4 /* Reset: PCIR */
1895 #define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
1896 #define I40E_GLPCI_REVID_NVM_REVID_MASK  I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT)
1897 #define I40E_GLPCI_SERH                 0x000BE49C /* Reset: PCIR */
1898 #define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
1899 #define I40E_GLPCI_SERH_SER_NUM_H_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
1900 #define I40E_GLPCI_SERL                 0x000BE498 /* Reset: PCIR */
1901 #define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
1902 #define I40E_GLPCI_SERL_SER_NUM_L_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
1903 #define I40E_GLPCI_SPARE_BITS_0                  0x0009C4F8 /* Reset: PCIR */
1904 #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
1905 #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
1906 #define I40E_GLPCI_SPARE_BITS_1                  0x0009C4FC /* Reset: PCIR */
1907 #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
1908 #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
1909 #define I40E_GLPCI_SUBVENID                  0x000BE48C /* Reset: PCIR */
1910 #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0
1911 #define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT)
1912 #define I40E_GLPCI_UPADD               0x000BE4F8 /* Reset: PCIR */
1913 #define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
1914 #define I40E_GLPCI_UPADD_ADDRESS_MASK  I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT)
1915 #define I40E_GLPCI_VENDORID                0x000BE518 /* Reset: PCIR */
1916 #define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0
1917 #define I40E_GLPCI_VENDORID_VENDORID_MASK  I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT)
1918 #define I40E_GLPCI_VFSUP                   0x000BE4B8 /* Reset: PCIR */
1919 #define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
1920 #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK  I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
1921 #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
1922 #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK  I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
1923 #define I40E_GLTPH_CTRL                         0x000BE480 /* Reset: PCIR */
1924 #define I40E_GLTPH_CTRL_DESC_PH_SHIFT           9
1925 #define I40E_GLTPH_CTRL_DESC_PH_MASK            I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT)
1926 #define I40E_GLTPH_CTRL_DATA_PH_SHIFT           11
1927 #define I40E_GLTPH_CTRL_DATA_PH_MASK            I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT)
1928 #define I40E_PF_FUNC_RID                       0x0009C000 /* Reset: PCIR */
1929 #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
1930 #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK  I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
1931 #define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT   3
1932 #define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK    I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
1933 #define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT      8
1934 #define I40E_PF_FUNC_RID_BUS_NUMBER_MASK       I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
1935 #define I40E_PF_PCI_CIAA               0x0009C080 /* Reset: FLR */
1936 #define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
1937 #define I40E_PF_PCI_CIAA_ADDRESS_MASK  I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
1938 #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT  12
1939 #define I40E_PF_PCI_CIAA_VF_NUM_MASK   I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
1940 #define I40E_PF_PCI_CIAD            0x0009C100 /* Reset: FLR */
1941 #define I40E_PF_PCI_CIAD_DATA_SHIFT 0
1942 #define I40E_PF_PCI_CIAD_DATA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT)
1943 #define I40E_PFPCI_CLASS                     0x000BE400 /* Reset: PCIR */
1944 #define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
1945 #define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK  I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
1946 #define I40E_PFPCI_CLASS_RESERVED_1_SHIFT    1
1947 #define I40E_PFPCI_CLASS_RESERVED_1_MASK     I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT)
1948 #define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT     2
1949 #define I40E_PFPCI_CLASS_PF_IS_LAN_MASK      I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT)
1950 #define I40E_PFPCI_CNF                 0x000BE000 /* Reset: PCIR */
1951 #define I40E_PFPCI_CNF_MSI_EN_SHIFT    2
1952 #define I40E_PFPCI_CNF_MSI_EN_MASK     I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT)
1953 #define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
1954 #define I40E_PFPCI_CNF_EXROM_DIS_MASK  I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
1955 #define I40E_PFPCI_CNF_IO_BAR_SHIFT    4
1956 #define I40E_PFPCI_CNF_IO_BAR_MASK     I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT)
1957 #define I40E_PFPCI_CNF_INT_PIN_SHIFT   5
1958 #define I40E_PFPCI_CNF_INT_PIN_MASK    I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT)
1959 #define I40E_PFPCI_DEVID                 0x000BE080 /* Reset: PCIR */
1960 #define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0
1961 #define I40E_PFPCI_DEVID_PF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT)
1962 #define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16
1963 #define I40E_PFPCI_DEVID_VF_DEV_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT)
1964 #define I40E_PFPCI_FACTPS                        0x0009C180 /* Reset: FLR */
1965 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
1966 #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK  I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
1967 #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT      3
1968 #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK       I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
1969 #define I40E_PFPCI_FUNC                            0x000BE200 /* Reset: POR */
1970 #define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT             0
1971 #define I40E_PFPCI_FUNC_FUNC_DIS_MASK              I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
1972 #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT       1
1973 #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK        I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
1974 #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
1975 #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK  I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
1976 #define I40E_PFPCI_FUNC2                    0x000BE180 /* Reset: PCIR */
1977 #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
1978 #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK  I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
1979 #define I40E_PFPCI_ICAUSE                      0x0009C200 /* Reset: PFR */
1980 #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
1981 #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
1982 #define I40E_PFPCI_IENA                   0x0009C280 /* Reset: PFR */
1983 #define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
1984 #define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
1985 #define I40E_PFPCI_PF_FLUSH_DONE                  0x0009C800 /* Reset: PCIR */
1986 #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
1987 #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
1988 #define I40E_PFPCI_PM              0x000BE300 /* Reset: POR */
1989 #define I40E_PFPCI_PM_PME_EN_SHIFT 0
1990 #define I40E_PFPCI_PM_PME_EN_MASK  I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT)
1991 #define I40E_PFPCI_STATUS1                  0x000BE280 /* Reset: POR */
1992 #define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
1993 #define I40E_PFPCI_STATUS1_FUNC_VALID_MASK  I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
1994 #define I40E_PFPCI_SUBSYSID                    0x000BE100 /* Reset: PCIR */
1995 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0
1996 #define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT)
1997 #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16
1998 #define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK  I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT)
1999 #define I40E_PFPCI_VF_FLUSH_DONE                  0x0000E400 /* Reset: PCIR */
2000 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
2001 #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
2002 #define I40E_PFPCI_VF_FLUSH_DONE1(_VF)             (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */
2003 #define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX        127
2004 #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0
2005 #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT)
2006 #define I40E_PFPCI_VM_FLUSH_DONE                  0x0009C880 /* Reset: PCIR */
2007 #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
2008 #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK  I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
2009 #define I40E_PFPCI_VMINDEX               0x0009C300 /* Reset: PCIR */
2010 #define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
2011 #define I40E_PFPCI_VMINDEX_VMINDEX_MASK  I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
2012 #define I40E_PFPCI_VMPEND               0x0009C380 /* Reset: PCIR */
2013 #define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
2014 #define I40E_PFPCI_VMPEND_PENDING_MASK  I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT)
2015 #define I40E_PRTPM_EEE_STAT                     0x001E4320 /* Reset: GLOBR */
2016 #define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT       29
2017 #define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK        I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
2018 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
2019 #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK  I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
2020 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
2021 #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK  I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
2022 #define I40E_PRTPM_EEEC                     0x001E4380 /* Reset: GLOBR */
2023 #define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT   16
2024 #define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK    I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
2025 #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
2026 #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK  I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
2027 #define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT      26
2028 #define I40E_PRTPM_EEEC_TEEE_DLY_MASK       I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
2029 #define I40E_PRTPM_EEEFWD                          0x001E4400 /* Reset: GLOBR */
2030 #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
2031 #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK  I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
2032 #define I40E_PRTPM_EEER                 0x001E4360 /* Reset: GLOBR */
2033 #define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
2034 #define I40E_PRTPM_EEER_TW_SYSTEM_MASK  I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
2035 #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
2036 #define I40E_PRTPM_EEER_TX_LPI_EN_MASK  I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
2037 #define I40E_PRTPM_EEETXC              0x001E43E0 /* Reset: GLOBR */
2038 #define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
2039 #define I40E_PRTPM_EEETXC_TW_PHY_MASK  I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
2040 #define I40E_PRTPM_GC                     0x000B8140 /* Reset: POR */
2041 #define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT   0
2042 #define I40E_PRTPM_GC_EMP_LINK_ON_MASK    I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
2043 #define I40E_PRTPM_GC_MNG_VETO_SHIFT      1
2044 #define I40E_PRTPM_GC_MNG_VETO_MASK       I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT)
2045 #define I40E_PRTPM_GC_RATD_SHIFT          2
2046 #define I40E_PRTPM_GC_RATD_MASK           I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT)
2047 #define I40E_PRTPM_GC_LCDMP_SHIFT         3
2048 #define I40E_PRTPM_GC_LCDMP_MASK          I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT)
2049 #define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
2050 #define I40E_PRTPM_GC_LPLU_ASSERTED_MASK  I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
2051 #define I40E_PRTPM_RLPIC              0x001E43A0 /* Reset: GLOBR */
2052 #define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
2053 #define I40E_PRTPM_RLPIC_ERLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
2054 #define I40E_PRTPM_TLPIC              0x001E43C0 /* Reset: GLOBR */
2055 #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
2056 #define I40E_PRTPM_TLPIC_ETLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
2057 #define I40E_GL_PRS_FVBM(_i)                 (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
2058 #define I40E_GL_PRS_FVBM_MAX_INDEX           3
2059 #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT  0
2060 #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_MASK   I40E_MASK(0x7F, I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT)
2061 #define I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT 8
2062 #define I40E_GL_PRS_FVBM_RULE_BUS_INDX_MASK  I40E_MASK(0x3F, I40E_GL_PRS_FVBM_RULE_BUS_INDX_SHIFT)
2063 #define I40E_GL_PRS_FVBM_MSK_ENA_SHIFT       31
2064 #define I40E_GL_PRS_FVBM_MSK_ENA_MASK        I40E_MASK(0x1, I40E_GL_PRS_FVBM_MSK_ENA_SHIFT)
2065 #define I40E_GLRPB_DPSS               0x000AC828 /* Reset: CORER */
2066 #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
2067 #define I40E_GLRPB_DPSS_DPS_TCN_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
2068 #define I40E_GLRPB_GHW           0x000AC830 /* Reset: CORER */
2069 #define I40E_GLRPB_GHW_GHW_SHIFT 0
2070 #define I40E_GLRPB_GHW_GHW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT)
2071 #define I40E_GLRPB_GLW           0x000AC834 /* Reset: CORER */
2072 #define I40E_GLRPB_GLW_GLW_SHIFT 0
2073 #define I40E_GLRPB_GLW_GLW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT)
2074 #define I40E_GLRPB_PHW           0x000AC844 /* Reset: CORER */
2075 #define I40E_GLRPB_PHW_PHW_SHIFT 0
2076 #define I40E_GLRPB_PHW_PHW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT)
2077 #define I40E_GLRPB_PLW           0x000AC848 /* Reset: CORER */
2078 #define I40E_GLRPB_PLW_PLW_SHIFT 0
2079 #define I40E_GLRPB_PLW_PLW_MASK  I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT)
2080 #define I40E_PRTRPB_DHW(_i)           (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2081 #define I40E_PRTRPB_DHW_MAX_INDEX     7
2082 #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
2083 #define I40E_PRTRPB_DHW_DHW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
2084 #define I40E_PRTRPB_DLW(_i)           (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2085 #define I40E_PRTRPB_DLW_MAX_INDEX     7
2086 #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
2087 #define I40E_PRTRPB_DLW_DLW_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
2088 #define I40E_PRTRPB_DPS(_i)           (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2089 #define I40E_PRTRPB_DPS_MAX_INDEX     7
2090 #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
2091 #define I40E_PRTRPB_DPS_DPS_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
2092 #define I40E_PRTRPB_SHT(_i)           (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2093 #define I40E_PRTRPB_SHT_MAX_INDEX     7
2094 #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
2095 #define I40E_PRTRPB_SHT_SHT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
2096 #define I40E_PRTRPB_SHW           0x000AC580 /* Reset: CORER */
2097 #define I40E_PRTRPB_SHW_SHW_SHIFT 0
2098 #define I40E_PRTRPB_SHW_SHW_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT)
2099 #define I40E_PRTRPB_SLT(_i)           (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */
2100 #define I40E_PRTRPB_SLT_MAX_INDEX     7
2101 #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
2102 #define I40E_PRTRPB_SLT_SLT_TCN_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
2103 #define I40E_PRTRPB_SLW           0x000AC6A0 /* Reset: CORER */
2104 #define I40E_PRTRPB_SLW_SLW_SHIFT 0
2105 #define I40E_PRTRPB_SLW_SLW_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT)
2106 #define I40E_PRTRPB_SPS           0x000AC7C0 /* Reset: CORER */
2107 #define I40E_PRTRPB_SPS_SPS_SHIFT 0
2108 #define I40E_PRTRPB_SPS_SPS_MASK  I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT)
2109 #define I40E_GLQF_CTL                      0x00269BA4 /* Reset: CORER */
2110 #define I40E_GLQF_CTL_HTOEP_SHIFT          1
2111 #define I40E_GLQF_CTL_HTOEP_MASK           I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT)
2112 #define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT     2
2113 #define I40E_GLQF_CTL_HTOEP_FCOE_MASK      I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
2114 #define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT     3
2115 #define I40E_GLQF_CTL_PCNT_ALLOC_MASK      I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
2116 #define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6
2117 #define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK  I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT)
2118 #define I40E_GLQF_CTL_RSVD_SHIFT           7
2119 #define I40E_GLQF_CTL_RSVD_MASK            I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT)
2120 #define I40E_GLQF_CTL_MAXPEBLEN_SHIFT      8
2121 #define I40E_GLQF_CTL_MAXPEBLEN_MASK       I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
2122 #define I40E_GLQF_CTL_MAXFCBLEN_SHIFT      11
2123 #define I40E_GLQF_CTL_MAXFCBLEN_MASK       I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
2124 #define I40E_GLQF_CTL_MAXFDBLEN_SHIFT      14
2125 #define I40E_GLQF_CTL_MAXFDBLEN_MASK       I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
2126 #define I40E_GLQF_CTL_FDBEST_SHIFT         17
2127 #define I40E_GLQF_CTL_FDBEST_MASK          I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT)
2128 #define I40E_GLQF_CTL_PROGPRIO_SHIFT       25
2129 #define I40E_GLQF_CTL_PROGPRIO_MASK        I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT)
2130 #define I40E_GLQF_CTL_INVALPRIO_SHIFT      26
2131 #define I40E_GLQF_CTL_INVALPRIO_MASK       I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT)
2132 #define I40E_GLQF_CTL_IGNORE_IP_SHIFT      27
2133 #define I40E_GLQF_CTL_IGNORE_IP_MASK       I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT)
2134 #define I40E_GLQF_FDCNT_0                   0x00269BAC /* Reset: CORER */
2135 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
2136 #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK  I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
2137 #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT     13
2138 #define I40E_GLQF_FDCNT_0_BESTCNT_MASK      I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
2139 #define I40E_GLQF_HKEY(_i)         (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
2140 #define I40E_GLQF_HKEY_MAX_INDEX   12
2141 #define I40E_GLQF_HKEY_KEY_0_SHIFT 0
2142 #define I40E_GLQF_HKEY_KEY_0_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT)
2143 #define I40E_GLQF_HKEY_KEY_1_SHIFT 8
2144 #define I40E_GLQF_HKEY_KEY_1_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT)
2145 #define I40E_GLQF_HKEY_KEY_2_SHIFT 16
2146 #define I40E_GLQF_HKEY_KEY_2_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT)
2147 #define I40E_GLQF_HKEY_KEY_3_SHIFT 24
2148 #define I40E_GLQF_HKEY_KEY_3_MASK  I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT)
2149 #define I40E_GLQF_HSYM(_i)            (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */
2150 #define I40E_GLQF_HSYM_MAX_INDEX      63
2151 #define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
2152 #define I40E_GLQF_HSYM_SYMH_ENA_MASK  I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
2153 #define I40E_GLQF_PCNT(_i)        (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */
2154 #define I40E_GLQF_PCNT_MAX_INDEX  511
2155 #define I40E_GLQF_PCNT_PCNT_SHIFT 0
2156 #define I40E_GLQF_PCNT_PCNT_MASK  I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT)
2157 #define I40E_GLQF_SWAP(_i, _j)          (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */
2158 #define I40E_GLQF_SWAP_MAX_INDEX       1
2159 #define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
2160 #define I40E_GLQF_SWAP_OFF0_SRC0_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
2161 #define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6
2162 #define I40E_GLQF_SWAP_OFF0_SRC1_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
2163 #define I40E_GLQF_SWAP_FLEN0_SHIFT     12
2164 #define I40E_GLQF_SWAP_FLEN0_MASK      I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT)
2165 #define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16
2166 #define I40E_GLQF_SWAP_OFF1_SRC0_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
2167 #define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22
2168 #define I40E_GLQF_SWAP_OFF1_SRC1_MASK  I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
2169 #define I40E_GLQF_SWAP_FLEN1_SHIFT     28
2170 #define I40E_GLQF_SWAP_FLEN1_MASK      I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT)
2171 #define I40E_PFQF_CTL_0                   0x001C0AC0 /* Reset: CORER */
2172 #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT     0
2173 #define I40E_PFQF_CTL_0_PEHSIZE_MASK      I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
2174 #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT     5
2175 #define I40E_PFQF_CTL_0_PEDSIZE_MASK      I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
2176 #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT   10
2177 #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK    I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
2178 #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT   14
2179 #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK    I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
2180 #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16
2181 #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK  I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
2182 #define I40E_PFQF_CTL_0_FD_ENA_SHIFT      17
2183 #define I40E_PFQF_CTL_0_FD_ENA_MASK       I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT)
2184 #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT   18
2185 #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK    I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
2186 #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
2187 #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK  I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
2188 #define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT   20
2189 #define I40E_PFQF_CTL_0_VFFCHSIZE_MASK    I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
2190 #define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT   24
2191 #define I40E_PFQF_CTL_0_VFFCDSIZE_MASK    I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
2192 #define I40E_PFQF_CTL_1                    0x00245D80 /* Reset: CORER */
2193 #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
2194 #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK  I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
2195 #define I40E_PFQF_FDALLOC               0x00246280 /* Reset: CORER */
2196 #define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
2197 #define I40E_PFQF_FDALLOC_FDALLOC_MASK  I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
2198 #define I40E_PFQF_FDALLOC_FDBEST_SHIFT  8
2199 #define I40E_PFQF_FDALLOC_FDBEST_MASK   I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT)
2200 #define I40E_PFQF_FDSTAT                   0x00246380 /* Reset: CORER */
2201 #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
2202 #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK  I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
2203 #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT    16
2204 #define I40E_PFQF_FDSTAT_BEST_CNT_MASK     I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
2205 #define I40E_PFQF_HENA(_i)             (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */
2206 #define I40E_PFQF_HENA_MAX_INDEX       1
2207 #define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
2208 #define I40E_PFQF_HENA_PTYPE_ENA_MASK  I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
2209 #define