1 /******************************************************************************
2
3 Copyright (c) 2013-2018, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "virtchnl.h"
39
40
41 /**
42 * i40e_set_mac_type - Sets MAC type
43 * @hw: pointer to the HW structure
44 *
45 * This function sets the mac type of the adapter based on the
46 * vendor ID and device ID stored in the hw structure.
47 **/
i40e_set_mac_type(struct i40e_hw * hw)48 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 {
50 enum i40e_status_code status = I40E_SUCCESS;
51
52 DEBUGFUNC("i40e_set_mac_type\n");
53
54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 switch (hw->device_id) {
56 case I40E_DEV_ID_SFP_XL710:
57 case I40E_DEV_ID_QEMU:
58 case I40E_DEV_ID_KX_B:
59 case I40E_DEV_ID_KX_C:
60 case I40E_DEV_ID_QSFP_A:
61 case I40E_DEV_ID_QSFP_B:
62 case I40E_DEV_ID_QSFP_C:
63 case I40E_DEV_ID_10G_BASE_T:
64 case I40E_DEV_ID_10G_BASE_T4:
65 case I40E_DEV_ID_10G_BASE_T_BC:
66 case I40E_DEV_ID_10G_B:
67 case I40E_DEV_ID_10G_SFP:
68 case I40E_DEV_ID_5G_BASE_T_BC:
69 case I40E_DEV_ID_20G_KR2:
70 case I40E_DEV_ID_20G_KR2_A:
71 case I40E_DEV_ID_25G_B:
72 case I40E_DEV_ID_25G_SFP28:
73 case I40E_DEV_ID_X710_N3000:
74 case I40E_DEV_ID_XXV710_N3000:
75 hw->mac.type = I40E_MAC_XL710;
76 break;
77 case I40E_DEV_ID_KX_X722:
78 case I40E_DEV_ID_QSFP_X722:
79 case I40E_DEV_ID_SFP_X722:
80 case I40E_DEV_ID_1G_BASE_T_X722:
81 case I40E_DEV_ID_10G_BASE_T_X722:
82 case I40E_DEV_ID_SFP_I_X722:
83 hw->mac.type = I40E_MAC_X722;
84 break;
85 case I40E_DEV_ID_X722_VF:
86 hw->mac.type = I40E_MAC_X722_VF;
87 break;
88 case I40E_DEV_ID_VF:
89 case I40E_DEV_ID_VF_HV:
90 case I40E_DEV_ID_ADAPTIVE_VF:
91 hw->mac.type = I40E_MAC_VF;
92 break;
93 default:
94 hw->mac.type = I40E_MAC_GENERIC;
95 break;
96 }
97 } else {
98 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
99 }
100
101 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
102 hw->mac.type, status);
103 return status;
104 }
105
106 /**
107 * i40e_aq_str - convert AQ err code to a string
108 * @hw: pointer to the HW structure
109 * @aq_err: the AQ error code to convert
110 **/
i40e_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)111 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
112 {
113 switch (aq_err) {
114 case I40E_AQ_RC_OK:
115 return "OK";
116 case I40E_AQ_RC_EPERM:
117 return "I40E_AQ_RC_EPERM";
118 case I40E_AQ_RC_ENOENT:
119 return "I40E_AQ_RC_ENOENT";
120 case I40E_AQ_RC_ESRCH:
121 return "I40E_AQ_RC_ESRCH";
122 case I40E_AQ_RC_EINTR:
123 return "I40E_AQ_RC_EINTR";
124 case I40E_AQ_RC_EIO:
125 return "I40E_AQ_RC_EIO";
126 case I40E_AQ_RC_ENXIO:
127 return "I40E_AQ_RC_ENXIO";
128 case I40E_AQ_RC_E2BIG:
129 return "I40E_AQ_RC_E2BIG";
130 case I40E_AQ_RC_EAGAIN:
131 return "I40E_AQ_RC_EAGAIN";
132 case I40E_AQ_RC_ENOMEM:
133 return "I40E_AQ_RC_ENOMEM";
134 case I40E_AQ_RC_EACCES:
135 return "I40E_AQ_RC_EACCES";
136 case I40E_AQ_RC_EFAULT:
137 return "I40E_AQ_RC_EFAULT";
138 case I40E_AQ_RC_EBUSY:
139 return "I40E_AQ_RC_EBUSY";
140 case I40E_AQ_RC_EEXIST:
141 return "I40E_AQ_RC_EEXIST";
142 case I40E_AQ_RC_EINVAL:
143 return "I40E_AQ_RC_EINVAL";
144 case I40E_AQ_RC_ENOTTY:
145 return "I40E_AQ_RC_ENOTTY";
146 case I40E_AQ_RC_ENOSPC:
147 return "I40E_AQ_RC_ENOSPC";
148 case I40E_AQ_RC_ENOSYS:
149 return "I40E_AQ_RC_ENOSYS";
150 case I40E_AQ_RC_ERANGE:
151 return "I40E_AQ_RC_ERANGE";
152 case I40E_AQ_RC_EFLUSHED:
153 return "I40E_AQ_RC_EFLUSHED";
154 case I40E_AQ_RC_BAD_ADDR:
155 return "I40E_AQ_RC_BAD_ADDR";
156 case I40E_AQ_RC_EMODE:
157 return "I40E_AQ_RC_EMODE";
158 case I40E_AQ_RC_EFBIG:
159 return "I40E_AQ_RC_EFBIG";
160 }
161
162 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
163 return hw->err_str;
164 }
165
166 /**
167 * i40e_stat_str - convert status err code to a string
168 * @hw: pointer to the HW structure
169 * @stat_err: the status error code to convert
170 **/
i40e_stat_str(struct i40e_hw * hw,enum i40e_status_code stat_err)171 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
172 {
173 switch (stat_err) {
174 case I40E_SUCCESS:
175 return "OK";
176 case I40E_ERR_NVM:
177 return "I40E_ERR_NVM";
178 case I40E_ERR_NVM_CHECKSUM:
179 return "I40E_ERR_NVM_CHECKSUM";
180 case I40E_ERR_PHY:
181 return "I40E_ERR_PHY";
182 case I40E_ERR_CONFIG:
183 return "I40E_ERR_CONFIG";
184 case I40E_ERR_PARAM:
185 return "I40E_ERR_PARAM";
186 case I40E_ERR_MAC_TYPE:
187 return "I40E_ERR_MAC_TYPE";
188 case I40E_ERR_UNKNOWN_PHY:
189 return "I40E_ERR_UNKNOWN_PHY";
190 case I40E_ERR_LINK_SETUP:
191 return "I40E_ERR_LINK_SETUP";
192 case I40E_ERR_ADAPTER_STOPPED:
193 return "I40E_ERR_ADAPTER_STOPPED";
194 case I40E_ERR_INVALID_MAC_ADDR:
195 return "I40E_ERR_INVALID_MAC_ADDR";
196 case I40E_ERR_DEVICE_NOT_SUPPORTED:
197 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
198 case I40E_ERR_MASTER_REQUESTS_PENDING:
199 return "I40E_ERR_MASTER_REQUESTS_PENDING";
200 case I40E_ERR_INVALID_LINK_SETTINGS:
201 return "I40E_ERR_INVALID_LINK_SETTINGS";
202 case I40E_ERR_AUTONEG_NOT_COMPLETE:
203 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
204 case I40E_ERR_RESET_FAILED:
205 return "I40E_ERR_RESET_FAILED";
206 case I40E_ERR_SWFW_SYNC:
207 return "I40E_ERR_SWFW_SYNC";
208 case I40E_ERR_NO_AVAILABLE_VSI:
209 return "I40E_ERR_NO_AVAILABLE_VSI";
210 case I40E_ERR_NO_MEMORY:
211 return "I40E_ERR_NO_MEMORY";
212 case I40E_ERR_BAD_PTR:
213 return "I40E_ERR_BAD_PTR";
214 case I40E_ERR_RING_FULL:
215 return "I40E_ERR_RING_FULL";
216 case I40E_ERR_INVALID_PD_ID:
217 return "I40E_ERR_INVALID_PD_ID";
218 case I40E_ERR_INVALID_QP_ID:
219 return "I40E_ERR_INVALID_QP_ID";
220 case I40E_ERR_INVALID_CQ_ID:
221 return "I40E_ERR_INVALID_CQ_ID";
222 case I40E_ERR_INVALID_CEQ_ID:
223 return "I40E_ERR_INVALID_CEQ_ID";
224 case I40E_ERR_INVALID_AEQ_ID:
225 return "I40E_ERR_INVALID_AEQ_ID";
226 case I40E_ERR_INVALID_SIZE:
227 return "I40E_ERR_INVALID_SIZE";
228 case I40E_ERR_INVALID_ARP_INDEX:
229 return "I40E_ERR_INVALID_ARP_INDEX";
230 case I40E_ERR_INVALID_FPM_FUNC_ID:
231 return "I40E_ERR_INVALID_FPM_FUNC_ID";
232 case I40E_ERR_QP_INVALID_MSG_SIZE:
233 return "I40E_ERR_QP_INVALID_MSG_SIZE";
234 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
235 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
236 case I40E_ERR_INVALID_FRAG_COUNT:
237 return "I40E_ERR_INVALID_FRAG_COUNT";
238 case I40E_ERR_QUEUE_EMPTY:
239 return "I40E_ERR_QUEUE_EMPTY";
240 case I40E_ERR_INVALID_ALIGNMENT:
241 return "I40E_ERR_INVALID_ALIGNMENT";
242 case I40E_ERR_FLUSHED_QUEUE:
243 return "I40E_ERR_FLUSHED_QUEUE";
244 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
245 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
246 case I40E_ERR_INVALID_IMM_DATA_SIZE:
247 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
248 case I40E_ERR_TIMEOUT:
249 return "I40E_ERR_TIMEOUT";
250 case I40E_ERR_OPCODE_MISMATCH:
251 return "I40E_ERR_OPCODE_MISMATCH";
252 case I40E_ERR_CQP_COMPL_ERROR:
253 return "I40E_ERR_CQP_COMPL_ERROR";
254 case I40E_ERR_INVALID_VF_ID:
255 return "I40E_ERR_INVALID_VF_ID";
256 case I40E_ERR_INVALID_HMCFN_ID:
257 return "I40E_ERR_INVALID_HMCFN_ID";
258 case I40E_ERR_BACKING_PAGE_ERROR:
259 return "I40E_ERR_BACKING_PAGE_ERROR";
260 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
261 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
262 case I40E_ERR_INVALID_PBLE_INDEX:
263 return "I40E_ERR_INVALID_PBLE_INDEX";
264 case I40E_ERR_INVALID_SD_INDEX:
265 return "I40E_ERR_INVALID_SD_INDEX";
266 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
267 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
268 case I40E_ERR_INVALID_SD_TYPE:
269 return "I40E_ERR_INVALID_SD_TYPE";
270 case I40E_ERR_MEMCPY_FAILED:
271 return "I40E_ERR_MEMCPY_FAILED";
272 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
273 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
274 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
275 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
276 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
277 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
278 case I40E_ERR_SRQ_ENABLED:
279 return "I40E_ERR_SRQ_ENABLED";
280 case I40E_ERR_ADMIN_QUEUE_ERROR:
281 return "I40E_ERR_ADMIN_QUEUE_ERROR";
282 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
283 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
284 case I40E_ERR_BUF_TOO_SHORT:
285 return "I40E_ERR_BUF_TOO_SHORT";
286 case I40E_ERR_ADMIN_QUEUE_FULL:
287 return "I40E_ERR_ADMIN_QUEUE_FULL";
288 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
289 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
290 case I40E_ERR_BAD_IWARP_CQE:
291 return "I40E_ERR_BAD_IWARP_CQE";
292 case I40E_ERR_NVM_BLANK_MODE:
293 return "I40E_ERR_NVM_BLANK_MODE";
294 case I40E_ERR_NOT_IMPLEMENTED:
295 return "I40E_ERR_NOT_IMPLEMENTED";
296 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
297 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
298 case I40E_ERR_DIAG_TEST_FAILED:
299 return "I40E_ERR_DIAG_TEST_FAILED";
300 case I40E_ERR_NOT_READY:
301 return "I40E_ERR_NOT_READY";
302 case I40E_NOT_SUPPORTED:
303 return "I40E_NOT_SUPPORTED";
304 case I40E_ERR_FIRMWARE_API_VERSION:
305 return "I40E_ERR_FIRMWARE_API_VERSION";
306 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
307 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
308 }
309
310 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
311 return hw->err_str;
312 }
313
314 /**
315 * i40e_debug_aq
316 * @hw: debug mask related to admin queue
317 * @mask: debug mask
318 * @desc: pointer to admin queue descriptor
319 * @buffer: pointer to command buffer
320 * @buf_len: max length of buffer
321 *
322 * Dumps debug log about adminq command with descriptor contents.
323 **/
i40e_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)324 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
325 void *buffer, u16 buf_len)
326 {
327 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
328 u32 effective_mask = hw->debug_mask & mask;
329 u8 *buf = (u8 *)buffer;
330 u16 len;
331 u16 i;
332
333 if (!effective_mask || !desc)
334 return;
335
336 len = LE16_TO_CPU(aq_desc->datalen);
337
338 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
339 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
340 LE16_TO_CPU(aq_desc->opcode),
341 LE16_TO_CPU(aq_desc->flags),
342 LE16_TO_CPU(aq_desc->datalen),
343 LE16_TO_CPU(aq_desc->retval));
344 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
345 "\tcookie (h,l) 0x%08X 0x%08X\n",
346 LE32_TO_CPU(aq_desc->cookie_high),
347 LE32_TO_CPU(aq_desc->cookie_low));
348 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
349 "\tparam (0,1) 0x%08X 0x%08X\n",
350 LE32_TO_CPU(aq_desc->params.internal.param0),
351 LE32_TO_CPU(aq_desc->params.internal.param1));
352 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
353 "\taddr (h,l) 0x%08X 0x%08X\n",
354 LE32_TO_CPU(aq_desc->params.external.addr_high),
355 LE32_TO_CPU(aq_desc->params.external.addr_low));
356
357 if (buffer && (buf_len != 0) && (len != 0) &&
358 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
359 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
360 if (buf_len < len)
361 len = buf_len;
362 /* write the full 16-byte chunks */
363 for (i = 0; i < (len - 16); i += 16)
364 i40e_debug(hw, mask,
365 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
366 i, buf[i], buf[i+1], buf[i+2], buf[i+3],
367 buf[i+4], buf[i+5], buf[i+6], buf[i+7],
368 buf[i+8], buf[i+9], buf[i+10], buf[i+11],
369 buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
370 /* the most we could have left is 16 bytes, pad with zeros */
371 if (i < len) {
372 char d_buf[16];
373 int j, i_sav;
374
375 i_sav = i;
376 memset(d_buf, 0, sizeof(d_buf));
377 for (j = 0; i < len; j++, i++)
378 d_buf[j] = buf[i];
379 i40e_debug(hw, mask,
380 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
381 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
382 d_buf[4], d_buf[5], d_buf[6], d_buf[7],
383 d_buf[8], d_buf[9], d_buf[10], d_buf[11],
384 d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
385 }
386 }
387 }
388
389 /**
390 * i40e_check_asq_alive
391 * @hw: pointer to the hw struct
392 *
393 * Returns TRUE if Queue is enabled else FALSE.
394 **/
i40e_check_asq_alive(struct i40e_hw * hw)395 bool i40e_check_asq_alive(struct i40e_hw *hw)
396 {
397 if (hw->aq.asq.len) {
398 if (!i40e_is_vf(hw))
399 return !!(rd32(hw, hw->aq.asq.len) &
400 I40E_PF_ATQLEN_ATQENABLE_MASK);
401 else
402 return !!(rd32(hw, hw->aq.asq.len) &
403 I40E_VF_ATQLEN1_ATQENABLE_MASK);
404 }
405 return FALSE;
406 }
407
408 /**
409 * i40e_aq_queue_shutdown
410 * @hw: pointer to the hw struct
411 * @unloading: is the driver unloading itself
412 *
413 * Tell the Firmware that we're shutting down the AdminQ and whether
414 * or not the driver is unloading as well.
415 **/
i40e_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)416 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
417 bool unloading)
418 {
419 struct i40e_aq_desc desc;
420 struct i40e_aqc_queue_shutdown *cmd =
421 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
422 enum i40e_status_code status;
423
424 i40e_fill_default_direct_cmd_desc(&desc,
425 i40e_aqc_opc_queue_shutdown);
426
427 if (unloading)
428 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
429 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
430
431 return status;
432 }
433
434 /**
435 * i40e_aq_get_set_rss_lut
436 * @hw: pointer to the hardware structure
437 * @vsi_id: vsi fw index
438 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
439 * @lut: pointer to the lut buffer provided by the caller
440 * @lut_size: size of the lut buffer
441 * @set: set TRUE to set the table, FALSE to get the table
442 *
443 * Internal function to get or set RSS look up table
444 **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)445 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
446 u16 vsi_id, bool pf_lut,
447 u8 *lut, u16 lut_size,
448 bool set)
449 {
450 enum i40e_status_code status;
451 struct i40e_aq_desc desc;
452 struct i40e_aqc_get_set_rss_lut *cmd_resp =
453 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
454
455 if (set)
456 i40e_fill_default_direct_cmd_desc(&desc,
457 i40e_aqc_opc_set_rss_lut);
458 else
459 i40e_fill_default_direct_cmd_desc(&desc,
460 i40e_aqc_opc_get_rss_lut);
461
462 /* Indirect command */
463 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
464 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
465
466 cmd_resp->vsi_id =
467 CPU_TO_LE16((u16)((vsi_id <<
468 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
469 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
470 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
471
472 if (pf_lut)
473 cmd_resp->flags |= CPU_TO_LE16((u16)
474 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
475 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
476 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
477 else
478 cmd_resp->flags |= CPU_TO_LE16((u16)
479 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
480 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
481 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
482
483 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
484
485 return status;
486 }
487
488 /**
489 * i40e_aq_get_rss_lut
490 * @hw: pointer to the hardware structure
491 * @vsi_id: vsi fw index
492 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
493 * @lut: pointer to the lut buffer provided by the caller
494 * @lut_size: size of the lut buffer
495 *
496 * get the RSS lookup table, PF or VSI type
497 **/
i40e_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)498 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
499 bool pf_lut, u8 *lut, u16 lut_size)
500 {
501 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
502 FALSE);
503 }
504
505 /**
506 * i40e_aq_set_rss_lut
507 * @hw: pointer to the hardware structure
508 * @vsi_id: vsi fw index
509 * @pf_lut: for PF table set TRUE, for VSI table set FALSE
510 * @lut: pointer to the lut buffer provided by the caller
511 * @lut_size: size of the lut buffer
512 *
513 * set the RSS lookup table, PF or VSI type
514 **/
i40e_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)515 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
516 bool pf_lut, u8 *lut, u16 lut_size)
517 {
518 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
519 }
520
521 /**
522 * i40e_aq_get_set_rss_key
523 * @hw: pointer to the hw struct
524 * @vsi_id: vsi fw index
525 * @key: pointer to key info struct
526 * @set: set TRUE to set the key, FALSE to get the key
527 *
528 * get the RSS key per VSI
529 **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)530 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
531 u16 vsi_id,
532 struct i40e_aqc_get_set_rss_key_data *key,
533 bool set)
534 {
535 enum i40e_status_code status;
536 struct i40e_aq_desc desc;
537 struct i40e_aqc_get_set_rss_key *cmd_resp =
538 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
539 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
540
541 if (set)
542 i40e_fill_default_direct_cmd_desc(&desc,
543 i40e_aqc_opc_set_rss_key);
544 else
545 i40e_fill_default_direct_cmd_desc(&desc,
546 i40e_aqc_opc_get_rss_key);
547
548 /* Indirect command */
549 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
550 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
551
552 cmd_resp->vsi_id =
553 CPU_TO_LE16((u16)((vsi_id <<
554 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
555 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
556 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
557
558 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
559
560 return status;
561 }
562
563 /**
564 * i40e_aq_get_rss_key
565 * @hw: pointer to the hw struct
566 * @vsi_id: vsi fw index
567 * @key: pointer to key info struct
568 *
569 **/
i40e_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)570 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
571 u16 vsi_id,
572 struct i40e_aqc_get_set_rss_key_data *key)
573 {
574 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
575 }
576
577 /**
578 * i40e_aq_set_rss_key
579 * @hw: pointer to the hw struct
580 * @vsi_id: vsi fw index
581 * @key: pointer to key info struct
582 *
583 * set the RSS key per VSI
584 **/
i40e_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)585 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
586 u16 vsi_id,
587 struct i40e_aqc_get_set_rss_key_data *key)
588 {
589 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
590 }
591
592 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
593 * hardware to a bit-field that can be used by SW to more easily determine the
594 * packet type.
595 *
596 * Macros are used to shorten the table lines and make this table human
597 * readable.
598 *
599 * We store the PTYPE in the top byte of the bit field - this is just so that
600 * we can check that the table doesn't have a row missing, as the index into
601 * the table should be the PTYPE.
602 *
603 * Typical work flow:
604 *
605 * IF NOT i40e_ptype_lookup[ptype].known
606 * THEN
607 * Packet is unknown
608 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
609 * Use the rest of the fields to look at the tunnels, inner protocols, etc
610 * ELSE
611 * Use the enum i40e_rx_l2_ptype to decode the packet type
612 * ENDIF
613 */
614
615 /* macro to make the table lines short */
616 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
617 { PTYPE, \
618 1, \
619 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
620 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
621 I40E_RX_PTYPE_##OUTER_FRAG, \
622 I40E_RX_PTYPE_TUNNEL_##T, \
623 I40E_RX_PTYPE_TUNNEL_END_##TE, \
624 I40E_RX_PTYPE_##TEF, \
625 I40E_RX_PTYPE_INNER_PROT_##I, \
626 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
627
628 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
629 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
630
631 /* shorter macros makes the table fit but are terse */
632 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
633 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
634 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
635
636 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
637 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
638 /* L2 Packet types */
639 I40E_PTT_UNUSED_ENTRY(0),
640 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
641 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
642 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
643 I40E_PTT_UNUSED_ENTRY(4),
644 I40E_PTT_UNUSED_ENTRY(5),
645 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
646 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
647 I40E_PTT_UNUSED_ENTRY(8),
648 I40E_PTT_UNUSED_ENTRY(9),
649 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
650 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
651 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
652 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
653 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
654 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
655 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
656 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
657 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
658 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
659 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
660 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
661
662 /* Non Tunneled IPv4 */
663 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
664 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
665 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
666 I40E_PTT_UNUSED_ENTRY(25),
667 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
668 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
669 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
670
671 /* IPv4 --> IPv4 */
672 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
673 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
674 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
675 I40E_PTT_UNUSED_ENTRY(32),
676 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
677 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
678 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
679
680 /* IPv4 --> IPv6 */
681 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
682 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
683 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(39),
685 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
686 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
687 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
688
689 /* IPv4 --> GRE/NAT */
690 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
691
692 /* IPv4 --> GRE/NAT --> IPv4 */
693 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
694 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
695 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
696 I40E_PTT_UNUSED_ENTRY(47),
697 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
698 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
699 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
700
701 /* IPv4 --> GRE/NAT --> IPv6 */
702 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
703 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
704 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
705 I40E_PTT_UNUSED_ENTRY(54),
706 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
707 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
708 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
709
710 /* IPv4 --> GRE/NAT --> MAC */
711 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
712
713 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
714 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
715 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
716 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
717 I40E_PTT_UNUSED_ENTRY(62),
718 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
719 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
720 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
721
722 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
723 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
724 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
725 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
726 I40E_PTT_UNUSED_ENTRY(69),
727 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
728 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
729 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
730
731 /* IPv4 --> GRE/NAT --> MAC/VLAN */
732 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
733
734 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
735 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
736 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
737 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
738 I40E_PTT_UNUSED_ENTRY(77),
739 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
740 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
741 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
742
743 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
744 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
745 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
746 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
747 I40E_PTT_UNUSED_ENTRY(84),
748 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
749 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
750 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
751
752 /* Non Tunneled IPv6 */
753 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
754 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
755 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
756 I40E_PTT_UNUSED_ENTRY(91),
757 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
758 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
759 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
760
761 /* IPv6 --> IPv4 */
762 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
763 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
764 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(98),
766 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
767 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
768 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
769
770 /* IPv6 --> IPv6 */
771 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
772 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
773 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(105),
775 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
776 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
777 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
778
779 /* IPv6 --> GRE/NAT */
780 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
781
782 /* IPv6 --> GRE/NAT -> IPv4 */
783 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
784 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
785 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
786 I40E_PTT_UNUSED_ENTRY(113),
787 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
788 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
789 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
790
791 /* IPv6 --> GRE/NAT -> IPv6 */
792 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
793 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
794 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
795 I40E_PTT_UNUSED_ENTRY(120),
796 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
797 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
798 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
799
800 /* IPv6 --> GRE/NAT -> MAC */
801 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
802
803 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
804 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
805 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
806 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
807 I40E_PTT_UNUSED_ENTRY(128),
808 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
809 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
810 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
811
812 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
813 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
814 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
815 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
816 I40E_PTT_UNUSED_ENTRY(135),
817 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
818 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
819 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
820
821 /* IPv6 --> GRE/NAT -> MAC/VLAN */
822 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
823
824 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
825 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
826 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
827 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
828 I40E_PTT_UNUSED_ENTRY(143),
829 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
830 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
831 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
832
833 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
834 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
835 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
836 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
837 I40E_PTT_UNUSED_ENTRY(150),
838 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
839 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
840 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
841
842 /* unused entries */
843 I40E_PTT_UNUSED_ENTRY(154),
844 I40E_PTT_UNUSED_ENTRY(155),
845 I40E_PTT_UNUSED_ENTRY(156),
846 I40E_PTT_UNUSED_ENTRY(157),
847 I40E_PTT_UNUSED_ENTRY(158),
848 I40E_PTT_UNUSED_ENTRY(159),
849
850 I40E_PTT_UNUSED_ENTRY(160),
851 I40E_PTT_UNUSED_ENTRY(161),
852 I40E_PTT_UNUSED_ENTRY(162),
853 I40E_PTT_UNUSED_ENTRY(163),
854 I40E_PTT_UNUSED_ENTRY(164),
855 I40E_PTT_UNUSED_ENTRY(165),
856 I40E_PTT_UNUSED_ENTRY(166),
857 I40E_PTT_UNUSED_ENTRY(167),
858 I40E_PTT_UNUSED_ENTRY(168),
859 I40E_PTT_UNUSED_ENTRY(169),
860
861 I40E_PTT_UNUSED_ENTRY(170),
862 I40E_PTT_UNUSED_ENTRY(171),
863 I40E_PTT_UNUSED_ENTRY(172),
864 I40E_PTT_UNUSED_ENTRY(173),
865 I40E_PTT_UNUSED_ENTRY(174),
866 I40E_PTT_UNUSED_ENTRY(175),
867 I40E_PTT_UNUSED_ENTRY(176),
868 I40E_PTT_UNUSED_ENTRY(177),
869 I40E_PTT_UNUSED_ENTRY(178),
870 I40E_PTT_UNUSED_ENTRY(179),
871
872 I40E_PTT_UNUSED_ENTRY(180),
873 I40E_PTT_UNUSED_ENTRY(181),
874 I40E_PTT_UNUSED_ENTRY(182),
875 I40E_PTT_UNUSED_ENTRY(183),
876 I40E_PTT_UNUSED_ENTRY(184),
877 I40E_PTT_UNUSED_ENTRY(185),
878 I40E_PTT_UNUSED_ENTRY(186),
879 I40E_PTT_UNUSED_ENTRY(187),
880 I40E_PTT_UNUSED_ENTRY(188),
881 I40E_PTT_UNUSED_ENTRY(189),
882
883 I40E_PTT_UNUSED_ENTRY(190),
884 I40E_PTT_UNUSED_ENTRY(191),
885 I40E_PTT_UNUSED_ENTRY(192),
886 I40E_PTT_UNUSED_ENTRY(193),
887 I40E_PTT_UNUSED_ENTRY(194),
888 I40E_PTT_UNUSED_ENTRY(195),
889 I40E_PTT_UNUSED_ENTRY(196),
890 I40E_PTT_UNUSED_ENTRY(197),
891 I40E_PTT_UNUSED_ENTRY(198),
892 I40E_PTT_UNUSED_ENTRY(199),
893
894 I40E_PTT_UNUSED_ENTRY(200),
895 I40E_PTT_UNUSED_ENTRY(201),
896 I40E_PTT_UNUSED_ENTRY(202),
897 I40E_PTT_UNUSED_ENTRY(203),
898 I40E_PTT_UNUSED_ENTRY(204),
899 I40E_PTT_UNUSED_ENTRY(205),
900 I40E_PTT_UNUSED_ENTRY(206),
901 I40E_PTT_UNUSED_ENTRY(207),
902 I40E_PTT_UNUSED_ENTRY(208),
903 I40E_PTT_UNUSED_ENTRY(209),
904
905 I40E_PTT_UNUSED_ENTRY(210),
906 I40E_PTT_UNUSED_ENTRY(211),
907 I40E_PTT_UNUSED_ENTRY(212),
908 I40E_PTT_UNUSED_ENTRY(213),
909 I40E_PTT_UNUSED_ENTRY(214),
910 I40E_PTT_UNUSED_ENTRY(215),
911 I40E_PTT_UNUSED_ENTRY(216),
912 I40E_PTT_UNUSED_ENTRY(217),
913 I40E_PTT_UNUSED_ENTRY(218),
914 I40E_PTT_UNUSED_ENTRY(219),
915
916 I40E_PTT_UNUSED_ENTRY(220),
917 I40E_PTT_UNUSED_ENTRY(221),
918 I40E_PTT_UNUSED_ENTRY(222),
919 I40E_PTT_UNUSED_ENTRY(223),
920 I40E_PTT_UNUSED_ENTRY(224),
921 I40E_PTT_UNUSED_ENTRY(225),
922 I40E_PTT_UNUSED_ENTRY(226),
923 I40E_PTT_UNUSED_ENTRY(227),
924 I40E_PTT_UNUSED_ENTRY(228),
925 I40E_PTT_UNUSED_ENTRY(229),
926
927 I40E_PTT_UNUSED_ENTRY(230),
928 I40E_PTT_UNUSED_ENTRY(231),
929 I40E_PTT_UNUSED_ENTRY(232),
930 I40E_PTT_UNUSED_ENTRY(233),
931 I40E_PTT_UNUSED_ENTRY(234),
932 I40E_PTT_UNUSED_ENTRY(235),
933 I40E_PTT_UNUSED_ENTRY(236),
934 I40E_PTT_UNUSED_ENTRY(237),
935 I40E_PTT_UNUSED_ENTRY(238),
936 I40E_PTT_UNUSED_ENTRY(239),
937
938 I40E_PTT_UNUSED_ENTRY(240),
939 I40E_PTT_UNUSED_ENTRY(241),
940 I40E_PTT_UNUSED_ENTRY(242),
941 I40E_PTT_UNUSED_ENTRY(243),
942 I40E_PTT_UNUSED_ENTRY(244),
943 I40E_PTT_UNUSED_ENTRY(245),
944 I40E_PTT_UNUSED_ENTRY(246),
945 I40E_PTT_UNUSED_ENTRY(247),
946 I40E_PTT_UNUSED_ENTRY(248),
947 I40E_PTT_UNUSED_ENTRY(249),
948
949 I40E_PTT_UNUSED_ENTRY(250),
950 I40E_PTT_UNUSED_ENTRY(251),
951 I40E_PTT_UNUSED_ENTRY(252),
952 I40E_PTT_UNUSED_ENTRY(253),
953 I40E_PTT_UNUSED_ENTRY(254),
954 I40E_PTT_UNUSED_ENTRY(255)
955 };
956
957
958 /**
959 * i40e_validate_mac_addr - Validate unicast MAC address
960 * @mac_addr: pointer to MAC address
961 *
962 * Tests a MAC address to ensure it is a valid Individual Address
963 **/
i40e_validate_mac_addr(u8 * mac_addr)964 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
965 {
966 enum i40e_status_code status = I40E_SUCCESS;
967
968 DEBUGFUNC("i40e_validate_mac_addr");
969
970 /* Broadcast addresses ARE multicast addresses
971 * Make sure it is not a multicast address
972 * Reject the zero address
973 */
974 if (I40E_IS_MULTICAST(mac_addr) ||
975 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
976 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
977 status = I40E_ERR_INVALID_MAC_ADDR;
978
979 return status;
980 }
981
982 /**
983 * i40e_init_shared_code - Initialize the shared code
984 * @hw: pointer to hardware structure
985 *
986 * This assigns the MAC type and PHY code and inits the NVM.
987 * Does not touch the hardware. This function must be called prior to any
988 * other function in the shared code. The i40e_hw structure should be
989 * memset to 0 prior to calling this function. The following fields in
990 * hw structure should be filled in prior to calling this function:
991 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
992 * subsystem_vendor_id, and revision_id
993 **/
i40e_init_shared_code(struct i40e_hw * hw)994 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
995 {
996 enum i40e_status_code status = I40E_SUCCESS;
997 u32 port, ari, func_rid;
998
999 DEBUGFUNC("i40e_init_shared_code");
1000
1001 i40e_set_mac_type(hw);
1002
1003 switch (hw->mac.type) {
1004 case I40E_MAC_XL710:
1005 case I40E_MAC_X722:
1006 break;
1007 default:
1008 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1009 }
1010
1011 hw->phy.get_link_info = TRUE;
1012
1013 /* Determine port number and PF number*/
1014 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1015 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
1016 hw->port = (u8)port;
1017 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1018 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
1019 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1020 if (ari)
1021 hw->pf_id = (u8)(func_rid & 0xff);
1022 else
1023 hw->pf_id = (u8)(func_rid & 0x7);
1024
1025 /* NVMUpdate features structure initialization */
1026 hw->nvmupd_features.major = I40E_NVMUPD_FEATURES_API_VER_MAJOR;
1027 hw->nvmupd_features.minor = I40E_NVMUPD_FEATURES_API_VER_MINOR;
1028 hw->nvmupd_features.size = sizeof(hw->nvmupd_features);
1029 i40e_memset(hw->nvmupd_features.features, 0x0,
1030 I40E_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *
1031 sizeof(*hw->nvmupd_features.features),
1032 I40E_NONDMA_MEM);
1033
1034 /* No features supported at the moment */
1035 hw->nvmupd_features.features[0] = 0;
1036
1037 status = i40e_init_nvm(hw);
1038 return status;
1039 }
1040
1041 /**
1042 * i40e_aq_mac_address_read - Retrieve the MAC addresses
1043 * @hw: pointer to the hw struct
1044 * @flags: a return indicator of what addresses were added to the addr store
1045 * @addrs: the requestor's mac addr store
1046 * @cmd_details: pointer to command details structure or NULL
1047 **/
i40e_aq_mac_address_read(struct i40e_hw * hw,u16 * flags,struct i40e_aqc_mac_address_read_data * addrs,struct i40e_asq_cmd_details * cmd_details)1048 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1049 u16 *flags,
1050 struct i40e_aqc_mac_address_read_data *addrs,
1051 struct i40e_asq_cmd_details *cmd_details)
1052 {
1053 struct i40e_aq_desc desc;
1054 struct i40e_aqc_mac_address_read *cmd_data =
1055 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
1056 enum i40e_status_code status;
1057
1058 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1059 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1060
1061 status = i40e_asq_send_command(hw, &desc, addrs,
1062 sizeof(*addrs), cmd_details);
1063 *flags = LE16_TO_CPU(cmd_data->command_flags);
1064
1065 return status;
1066 }
1067
1068 /**
1069 * i40e_aq_mac_address_write - Change the MAC addresses
1070 * @hw: pointer to the hw struct
1071 * @flags: indicates which MAC to be written
1072 * @mac_addr: address to write
1073 * @cmd_details: pointer to command details structure or NULL
1074 **/
i40e_aq_mac_address_write(struct i40e_hw * hw,u16 flags,u8 * mac_addr,struct i40e_asq_cmd_details * cmd_details)1075 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1076 u16 flags, u8 *mac_addr,
1077 struct i40e_asq_cmd_details *cmd_details)
1078 {
1079 struct i40e_aq_desc desc;
1080 struct i40e_aqc_mac_address_write *cmd_data =
1081 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
1082 enum i40e_status_code status;
1083
1084 i40e_fill_default_direct_cmd_desc(&desc,
1085 i40e_aqc_opc_mac_address_write);
1086 cmd_data->command_flags = CPU_TO_LE16(flags);
1087 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1088 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1089 ((u32)mac_addr[3] << 16) |
1090 ((u32)mac_addr[4] << 8) |
1091 mac_addr[5]);
1092
1093 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1094
1095 return status;
1096 }
1097
1098 /**
1099 * i40e_get_mac_addr - get MAC address
1100 * @hw: pointer to the HW structure
1101 * @mac_addr: pointer to MAC address
1102 *
1103 * Reads the adapter's MAC address from register
1104 **/
i40e_get_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1105 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1106 {
1107 struct i40e_aqc_mac_address_read_data addrs;
1108 enum i40e_status_code status;
1109 u16 flags = 0;
1110
1111 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1112
1113 if (flags & I40E_AQC_LAN_ADDR_VALID)
1114 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1115 I40E_NONDMA_TO_NONDMA);
1116
1117 return status;
1118 }
1119
1120 /**
1121 * i40e_get_port_mac_addr - get Port MAC address
1122 * @hw: pointer to the HW structure
1123 * @mac_addr: pointer to Port MAC address
1124 *
1125 * Reads the adapter's Port MAC address
1126 **/
i40e_get_port_mac_addr(struct i40e_hw * hw,u8 * mac_addr)1127 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1128 {
1129 struct i40e_aqc_mac_address_read_data addrs;
1130 enum i40e_status_code status;
1131 u16 flags = 0;
1132
1133 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1134 if (status)
1135 return status;
1136
1137 if (flags & I40E_AQC_PORT_ADDR_VALID)
1138 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1139 I40E_NONDMA_TO_NONDMA);
1140 else
1141 status = I40E_ERR_INVALID_MAC_ADDR;
1142
1143 return status;
1144 }
1145
1146 /**
1147 * i40e_pre_tx_queue_cfg - pre tx queue configure
1148 * @hw: pointer to the HW structure
1149 * @queue: target pf queue index
1150 * @enable: state change request
1151 *
1152 * Handles hw requirement to indicate intention to enable
1153 * or disable target queue.
1154 **/
i40e_pre_tx_queue_cfg(struct i40e_hw * hw,u32 queue,bool enable)1155 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1156 {
1157 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1158 u32 reg_block = 0;
1159 u32 reg_val;
1160
1161 if (abs_queue_idx >= 128) {
1162 reg_block = abs_queue_idx / 128;
1163 abs_queue_idx %= 128;
1164 }
1165
1166 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1167 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1168 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1169
1170 if (enable)
1171 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1172 else
1173 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1174
1175 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1176 }
1177
1178 /**
1179 * i40e_read_pba_string - Reads part number string from EEPROM
1180 * @hw: pointer to hardware structure
1181 * @pba_num: stores the part number string from the EEPROM
1182 * @pba_num_size: part number string buffer length
1183 *
1184 * Reads the part number string from the EEPROM.
1185 **/
i40e_read_pba_string(struct i40e_hw * hw,u8 * pba_num,u32 pba_num_size)1186 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1187 u32 pba_num_size)
1188 {
1189 enum i40e_status_code status = I40E_SUCCESS;
1190 u16 pba_word = 0;
1191 u16 pba_size = 0;
1192 u16 pba_ptr = 0;
1193 u16 i = 0;
1194
1195 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1196 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1197 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1198 return status;
1199 }
1200
1201 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1202 if (status != I40E_SUCCESS) {
1203 DEBUGOUT("Failed to read PBA Block pointer.\n");
1204 return status;
1205 }
1206
1207 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1208 if (status != I40E_SUCCESS) {
1209 DEBUGOUT("Failed to read PBA Block size.\n");
1210 return status;
1211 }
1212
1213 /* Subtract one to get PBA word count (PBA Size word is included in
1214 * total size)
1215 */
1216 pba_size--;
1217 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1218 DEBUGOUT("Buffer to small for PBA data.\n");
1219 return I40E_ERR_PARAM;
1220 }
1221
1222 for (i = 0; i < pba_size; i++) {
1223 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1224 if (status != I40E_SUCCESS) {
1225 DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1226 return status;
1227 }
1228
1229 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1230 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1231 }
1232 pba_num[(pba_size * 2)] = '\0';
1233
1234 return status;
1235 }
1236
1237 /**
1238 * i40e_get_media_type - Gets media type
1239 * @hw: pointer to the hardware structure
1240 **/
i40e_get_media_type(struct i40e_hw * hw)1241 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1242 {
1243 enum i40e_media_type media;
1244
1245 switch (hw->phy.link_info.phy_type) {
1246 case I40E_PHY_TYPE_10GBASE_SR:
1247 case I40E_PHY_TYPE_10GBASE_LR:
1248 case I40E_PHY_TYPE_1000BASE_SX:
1249 case I40E_PHY_TYPE_1000BASE_LX:
1250 case I40E_PHY_TYPE_40GBASE_SR4:
1251 case I40E_PHY_TYPE_40GBASE_LR4:
1252 case I40E_PHY_TYPE_25GBASE_LR:
1253 case I40E_PHY_TYPE_25GBASE_SR:
1254 media = I40E_MEDIA_TYPE_FIBER;
1255 break;
1256 case I40E_PHY_TYPE_100BASE_TX:
1257 case I40E_PHY_TYPE_1000BASE_T:
1258 case I40E_PHY_TYPE_2_5GBASE_T:
1259 case I40E_PHY_TYPE_5GBASE_T:
1260 case I40E_PHY_TYPE_10GBASE_T:
1261 media = I40E_MEDIA_TYPE_BASET;
1262 break;
1263 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1264 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1265 case I40E_PHY_TYPE_10GBASE_CR1:
1266 case I40E_PHY_TYPE_40GBASE_CR4:
1267 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1268 case I40E_PHY_TYPE_40GBASE_AOC:
1269 case I40E_PHY_TYPE_10GBASE_AOC:
1270 case I40E_PHY_TYPE_25GBASE_CR:
1271 case I40E_PHY_TYPE_25GBASE_AOC:
1272 case I40E_PHY_TYPE_25GBASE_ACC:
1273 media = I40E_MEDIA_TYPE_DA;
1274 break;
1275 case I40E_PHY_TYPE_1000BASE_KX:
1276 case I40E_PHY_TYPE_10GBASE_KX4:
1277 case I40E_PHY_TYPE_10GBASE_KR:
1278 case I40E_PHY_TYPE_40GBASE_KR4:
1279 case I40E_PHY_TYPE_20GBASE_KR2:
1280 case I40E_PHY_TYPE_25GBASE_KR:
1281 media = I40E_MEDIA_TYPE_BACKPLANE;
1282 break;
1283 case I40E_PHY_TYPE_SGMII:
1284 case I40E_PHY_TYPE_XAUI:
1285 case I40E_PHY_TYPE_XFI:
1286 case I40E_PHY_TYPE_XLAUI:
1287 case I40E_PHY_TYPE_XLPPI:
1288 default:
1289 media = I40E_MEDIA_TYPE_UNKNOWN;
1290 break;
1291 }
1292
1293 return media;
1294 }
1295
1296 /**
1297 * i40e_poll_globr - Poll for Global Reset completion
1298 * @hw: pointer to the hardware structure
1299 * @retry_limit: how many times to retry before failure
1300 **/
i40e_poll_globr(struct i40e_hw * hw,u32 retry_limit)1301 static enum i40e_status_code i40e_poll_globr(struct i40e_hw *hw,
1302 u32 retry_limit)
1303 {
1304 u32 cnt, reg = 0;
1305
1306 for (cnt = 0; cnt < retry_limit; cnt++) {
1307 reg = rd32(hw, I40E_GLGEN_RSTAT);
1308 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1309 return I40E_SUCCESS;
1310 i40e_msec_delay(100);
1311 }
1312
1313 DEBUGOUT("Global reset failed.\n");
1314 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg);
1315
1316 return I40E_ERR_RESET_FAILED;
1317 }
1318
1319 #define I40E_PF_RESET_WAIT_COUNT 200
1320 /**
1321 * i40e_pf_reset - Reset the PF
1322 * @hw: pointer to the hardware structure
1323 *
1324 * Assuming someone else has triggered a global reset,
1325 * assure the global reset is complete and then reset the PF
1326 **/
i40e_pf_reset(struct i40e_hw * hw)1327 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1328 {
1329 u32 cnt = 0;
1330 u32 cnt1 = 0;
1331 u32 reg = 0;
1332 u32 grst_del;
1333
1334 /* Poll for Global Reset steady state in case of recent GRST.
1335 * The grst delay value is in 100ms units, and we'll wait a
1336 * couple counts longer to be sure we don't just miss the end.
1337 */
1338 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1339 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1340 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1341
1342 grst_del = min(grst_del * 20, 160U);
1343
1344 for (cnt = 0; cnt < grst_del; cnt++) {
1345 reg = rd32(hw, I40E_GLGEN_RSTAT);
1346 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1347 break;
1348 i40e_msec_delay(100);
1349 }
1350 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1351 DEBUGOUT("Global reset polling failed to complete.\n");
1352 return I40E_ERR_RESET_FAILED;
1353 }
1354
1355 /* Now Wait for the FW to be ready */
1356 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1357 reg = rd32(hw, I40E_GLNVM_ULD);
1358 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1359 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1360 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1361 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1362 DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1363 break;
1364 }
1365 i40e_msec_delay(10);
1366 }
1367 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1368 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1369 DEBUGOUT("wait for FW Reset complete timedout\n");
1370 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1371 return I40E_ERR_RESET_FAILED;
1372 }
1373
1374 /* If there was a Global Reset in progress when we got here,
1375 * we don't need to do the PF Reset
1376 */
1377 if (!cnt) {
1378 u32 reg2 = 0;
1379
1380 reg = rd32(hw, I40E_PFGEN_CTRL);
1381 wr32(hw, I40E_PFGEN_CTRL,
1382 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1383 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1384 reg = rd32(hw, I40E_PFGEN_CTRL);
1385 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1386 break;
1387 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1388 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1389 break;
1390 i40e_msec_delay(1);
1391 }
1392 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1393 if (i40e_poll_globr(hw, grst_del) != I40E_SUCCESS)
1394 return I40E_ERR_RESET_FAILED;
1395 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1396 DEBUGOUT("PF reset polling failed to complete.\n");
1397 return I40E_ERR_RESET_FAILED;
1398 }
1399 }
1400
1401 i40e_clear_pxe_mode(hw);
1402
1403
1404 return I40E_SUCCESS;
1405 }
1406
1407 /**
1408 * i40e_clear_hw - clear out any left over hw state
1409 * @hw: pointer to the hw struct
1410 *
1411 * Clear queues and interrupts, typically called at init time,
1412 * but after the capabilities have been found so we know how many
1413 * queues and msix vectors have been allocated.
1414 **/
i40e_clear_hw(struct i40e_hw * hw)1415 void i40e_clear_hw(struct i40e_hw *hw)
1416 {
1417 u32 num_queues, base_queue;
1418 u32 num_pf_int;
1419 u32 num_vf_int;
1420 u32 num_vfs;
1421 u32 i, j;
1422 u32 val;
1423 u32 eol = 0x7ff;
1424
1425 /* get number of interrupts, queues, and vfs */
1426 val = rd32(hw, I40E_GLPCI_CNF2);
1427 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1428 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1429 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1430 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1431
1432 val = rd32(hw, I40E_PFLAN_QALLOC);
1433 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1434 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1435 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1436 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1437 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1438 num_queues = (j - base_queue) + 1;
1439 else
1440 num_queues = 0;
1441
1442 val = rd32(hw, I40E_PF_VT_PFALLOC);
1443 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1444 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1445 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1446 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1447 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1448 num_vfs = (j - i) + 1;
1449 else
1450 num_vfs = 0;
1451
1452 /* stop all the interrupts */
1453 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1454 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1455 for (i = 0; i < num_pf_int - 2; i++)
1456 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1457
1458 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1459 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1460 wr32(hw, I40E_PFINT_LNKLST0, val);
1461 for (i = 0; i < num_pf_int - 2; i++)
1462 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1463 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1464 for (i = 0; i < num_vfs; i++)
1465 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1466 for (i = 0; i < num_vf_int - 2; i++)
1467 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1468
1469 /* warn the HW of the coming Tx disables */
1470 for (i = 0; i < num_queues; i++) {
1471 u32 abs_queue_idx = base_queue + i;
1472 u32 reg_block = 0;
1473
1474 if (abs_queue_idx >= 128) {
1475 reg_block = abs_queue_idx / 128;
1476 abs_queue_idx %= 128;
1477 }
1478
1479 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1480 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1481 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1482 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1483
1484 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1485 }
1486 i40e_usec_delay(400);
1487
1488 /* stop all the queues */
1489 for (i = 0; i < num_queues; i++) {
1490 wr32(hw, I40E_QINT_TQCTL(i), 0);
1491 wr32(hw, I40E_QTX_ENA(i), 0);
1492 wr32(hw, I40E_QINT_RQCTL(i), 0);
1493 wr32(hw, I40E_QRX_ENA(i), 0);
1494 }
1495
1496 /* short wait for all queue disables to settle */
1497 i40e_usec_delay(50);
1498 }
1499
1500 /**
1501 * i40e_clear_pxe_mode - clear pxe operations mode
1502 * @hw: pointer to the hw struct
1503 *
1504 * Make sure all PXE mode settings are cleared, including things
1505 * like descriptor fetch/write-back mode.
1506 **/
i40e_clear_pxe_mode(struct i40e_hw * hw)1507 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1508 {
1509 if (i40e_check_asq_alive(hw))
1510 i40e_aq_clear_pxe_mode(hw, NULL);
1511 }
1512
1513 /**
1514 * i40e_led_is_mine - helper to find matching led
1515 * @hw: pointer to the hw struct
1516 * @idx: index into GPIO registers
1517 *
1518 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1519 */
i40e_led_is_mine(struct i40e_hw * hw,int idx)1520 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1521 {
1522 u32 gpio_val = 0;
1523 u32 port;
1524
1525 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1526 !hw->func_caps.led[idx])
1527 return 0;
1528 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1529 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1530 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1531
1532 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1533 * if it is not our port then ignore
1534 */
1535 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1536 (port != hw->port))
1537 return 0;
1538
1539 return gpio_val;
1540 }
1541
1542 #define I40E_COMBINED_ACTIVITY 0xA
1543 #define I40E_FILTER_ACTIVITY 0xE
1544 #define I40E_LINK_ACTIVITY 0xC
1545 #define I40E_MAC_ACTIVITY 0xD
1546 #define I40E_FW_LED BIT(4)
1547 #define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1549
1550 #define I40E_LED0 22
1551
1552 #define I40E_PIN_FUNC_SDP 0x0
1553 #define I40E_PIN_FUNC_LED 0x1
1554
1555 /**
1556 * i40e_led_get - return current on/off mode
1557 * @hw: pointer to the hw struct
1558 *
1559 * The value returned is the 'mode' field as defined in the
1560 * GPIO register definitions: 0x0 = off, 0xf = on, and other
1561 * values are variations of possible behaviors relating to
1562 * blink, link, and wire.
1563 **/
i40e_led_get(struct i40e_hw * hw)1564 u32 i40e_led_get(struct i40e_hw *hw)
1565 {
1566 u32 current_mode = 0;
1567 u32 mode = 0;
1568 int i;
1569
1570 /* as per the documentation GPIO 22-29 are the LED
1571 * GPIO pins named LED0..LED7
1572 */
1573 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1574 u32 gpio_val = i40e_led_is_mine(hw, i);
1575
1576 if (!gpio_val)
1577 continue;
1578
1579 /* ignore gpio LED src mode entries related to the activity
1580 * LEDs
1581 */
1582 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1583 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1584 switch (current_mode) {
1585 case I40E_COMBINED_ACTIVITY:
1586 case I40E_FILTER_ACTIVITY:
1587 case I40E_MAC_ACTIVITY:
1588 case I40E_LINK_ACTIVITY:
1589 continue;
1590 default:
1591 break;
1592 }
1593
1594 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1595 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1596 break;
1597 }
1598
1599 return mode;
1600 }
1601
1602 /**
1603 * i40e_led_set - set new on/off mode
1604 * @hw: pointer to the hw struct
1605 * @mode: 0=off, 0xf=on (else see manual for mode details)
1606 * @blink: TRUE if the LED should blink when on, FALSE if steady
1607 *
1608 * if this function is used to turn on the blink it should
1609 * be used to disable the blink when restoring the original state.
1610 **/
i40e_led_set(struct i40e_hw * hw,u32 mode,bool blink)1611 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1612 {
1613 u32 current_mode = 0;
1614 int i;
1615
1616 if (mode & ~I40E_LED_MODE_VALID) {
1617 DEBUGOUT1("invalid mode passed in %X\n", mode);
1618 return;
1619 }
1620
1621 /* as per the documentation GPIO 22-29 are the LED
1622 * GPIO pins named LED0..LED7
1623 */
1624 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1625 u32 gpio_val = i40e_led_is_mine(hw, i);
1626
1627 if (!gpio_val)
1628 continue;
1629
1630 /* ignore gpio LED src mode entries related to the activity
1631 * LEDs
1632 */
1633 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1634 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1635 switch (current_mode) {
1636 case I40E_COMBINED_ACTIVITY:
1637 case I40E_FILTER_ACTIVITY:
1638 case I40E_MAC_ACTIVITY:
1639 case I40E_LINK_ACTIVITY:
1640 continue;
1641 default:
1642 break;
1643 }
1644
1645 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1646 u32 pin_func = 0;
1647
1648 if (mode & I40E_FW_LED)
1649 pin_func = I40E_PIN_FUNC_SDP;
1650 else
1651 pin_func = I40E_PIN_FUNC_LED;
1652
1653 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1654 gpio_val |= ((pin_func <<
1655 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1656 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1657 }
1658 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1659 /* this & is a bit of paranoia, but serves as a range check */
1660 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1661 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1662
1663 if (blink)
1664 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1665 else
1666 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1667
1668 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1669 break;
1670 }
1671 }
1672
1673 /* Admin command wrappers */
1674
1675 /**
1676 * i40e_aq_get_phy_capabilities
1677 * @hw: pointer to the hw struct
1678 * @abilities: structure for PHY capabilities to be filled
1679 * @qualified_modules: report Qualified Modules
1680 * @report_init: report init capabilities (active are default)
1681 * @cmd_details: pointer to command details structure or NULL
1682 *
1683 * Returns the various PHY abilities supported on the Port.
1684 **/
i40e_aq_get_phy_capabilities(struct i40e_hw * hw,bool qualified_modules,bool report_init,struct i40e_aq_get_phy_abilities_resp * abilities,struct i40e_asq_cmd_details * cmd_details)1685 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1686 bool qualified_modules, bool report_init,
1687 struct i40e_aq_get_phy_abilities_resp *abilities,
1688 struct i40e_asq_cmd_details *cmd_details)
1689 {
1690 struct i40e_aq_desc desc;
1691 enum i40e_status_code status;
1692 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1693 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1694
1695 if (!abilities)
1696 return I40E_ERR_PARAM;
1697
1698 do {
1699 i40e_fill_default_direct_cmd_desc(&desc,
1700 i40e_aqc_opc_get_phy_abilities);
1701
1702 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1703 if (abilities_size > I40E_AQ_LARGE_BUF)
1704 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1705
1706 if (qualified_modules)
1707 desc.params.external.param0 |=
1708 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1709
1710 if (report_init)
1711 desc.params.external.param0 |=
1712 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1713
1714 status = i40e_asq_send_command(hw, &desc, abilities,
1715 abilities_size, cmd_details);
1716
1717 switch (hw->aq.asq_last_status) {
1718 case I40E_AQ_RC_EIO:
1719 status = I40E_ERR_UNKNOWN_PHY;
1720 break;
1721 case I40E_AQ_RC_EAGAIN:
1722 i40e_msec_delay(1);
1723 total_delay++;
1724 status = I40E_ERR_TIMEOUT;
1725 break;
1726 /* also covers I40E_AQ_RC_OK */
1727 default:
1728 break;
1729 }
1730
1731 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1732 (total_delay < max_delay));
1733
1734 if (status != I40E_SUCCESS)
1735 return status;
1736
1737 if (report_init) {
1738 if (hw->mac.type == I40E_MAC_XL710 &&
1739 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1740 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1741 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1742 } else {
1743 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1744 hw->phy.phy_types |=
1745 ((u64)abilities->phy_type_ext << 32);
1746 }
1747 }
1748
1749 return status;
1750 }
1751
1752 /**
1753 * i40e_aq_set_phy_config
1754 * @hw: pointer to the hw struct
1755 * @config: structure with PHY configuration to be set
1756 * @cmd_details: pointer to command details structure or NULL
1757 *
1758 * Set the various PHY configuration parameters
1759 * supported on the Port.One or more of the Set PHY config parameters may be
1760 * ignored in an MFP mode as the PF may not have the privilege to set some
1761 * of the PHY Config parameters. This status will be indicated by the
1762 * command response.
1763 **/
i40e_aq_set_phy_config(struct i40e_hw * hw,struct i40e_aq_set_phy_config * config,struct i40e_asq_cmd_details * cmd_details)1764 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1765 struct i40e_aq_set_phy_config *config,
1766 struct i40e_asq_cmd_details *cmd_details)
1767 {
1768 struct i40e_aq_desc desc;
1769 struct i40e_aq_set_phy_config *cmd =
1770 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1771 enum i40e_status_code status;
1772
1773 if (!config)
1774 return I40E_ERR_PARAM;
1775
1776 i40e_fill_default_direct_cmd_desc(&desc,
1777 i40e_aqc_opc_set_phy_config);
1778
1779 *cmd = *config;
1780
1781 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1782
1783 return status;
1784 }
1785
1786 /**
1787 * i40e_set_fc
1788 * @hw: pointer to the hw struct
1789 * @aq_failures: buffer to return AdminQ failure information
1790 * @atomic_restart: whether to enable atomic link restart
1791 *
1792 * Set the requested flow control mode using set_phy_config.
1793 **/
i40e_set_fc(struct i40e_hw * hw,u8 * aq_failures,bool atomic_restart)1794 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1795 bool atomic_restart)
1796 {
1797 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1798 struct i40e_aq_get_phy_abilities_resp abilities;
1799 struct i40e_aq_set_phy_config config;
1800 enum i40e_status_code status;
1801 u8 pause_mask = 0x0;
1802
1803 *aq_failures = 0x0;
1804
1805 switch (fc_mode) {
1806 case I40E_FC_FULL:
1807 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1808 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1809 break;
1810 case I40E_FC_RX_PAUSE:
1811 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1812 break;
1813 case I40E_FC_TX_PAUSE:
1814 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1815 break;
1816 default:
1817 break;
1818 }
1819
1820 /* Get the current phy config */
1821 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1822 NULL);
1823 if (status) {
1824 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1825 return status;
1826 }
1827
1828 memset(&config, 0, sizeof(config));
1829 /* clear the old pause settings */
1830 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1831 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1832 /* set the new abilities */
1833 config.abilities |= pause_mask;
1834 /* If the abilities have changed, then set the new config */
1835 if (config.abilities != abilities.abilities) {
1836 /* Auto restart link so settings take effect */
1837 if (atomic_restart)
1838 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1839 /* Copy over all the old settings */
1840 config.phy_type = abilities.phy_type;
1841 config.phy_type_ext = abilities.phy_type_ext;
1842 config.link_speed = abilities.link_speed;
1843 config.eee_capability = abilities.eee_capability;
1844 config.eeer = abilities.eeer_val;
1845 config.low_power_ctrl = abilities.d3_lpan;
1846 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1847 I40E_AQ_PHY_FEC_CONFIG_MASK;
1848 status = i40e_aq_set_phy_config(hw, &config, NULL);
1849
1850 if (status)
1851 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1852 }
1853 /* Update the link info */
1854 status = i40e_update_link_info(hw);
1855 if (status) {
1856 /* Wait a little bit (on 40G cards it sometimes takes a really
1857 * long time for link to come back from the atomic reset)
1858 * and try once more
1859 */
1860 i40e_msec_delay(1000);
1861 status = i40e_update_link_info(hw);
1862 }
1863 if (status)
1864 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1865
1866 return status;
1867 }
1868
1869 /**
1870 * i40e_aq_set_mac_config
1871 * @hw: pointer to the hw struct
1872 * @max_frame_size: Maximum Frame Size to be supported by the port
1873 * @crc_en: Tell HW to append a CRC to outgoing frames
1874 * @pacing: Pacing configurations
1875 * @auto_drop_blocking_packets: Tell HW to drop packets if TC queue is blocked
1876 * @cmd_details: pointer to command details structure or NULL
1877 *
1878 * Configure MAC settings for frame size, jumbo frame support and the
1879 * addition of a CRC by the hardware.
1880 **/
i40e_aq_set_mac_config(struct i40e_hw * hw,u16 max_frame_size,bool crc_en,u16 pacing,bool auto_drop_blocking_packets,struct i40e_asq_cmd_details * cmd_details)1881 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1882 u16 max_frame_size,
1883 bool crc_en, u16 pacing,
1884 bool auto_drop_blocking_packets,
1885 struct i40e_asq_cmd_details *cmd_details)
1886 {
1887 struct i40e_aq_desc desc;
1888 struct i40e_aq_set_mac_config *cmd =
1889 (struct i40e_aq_set_mac_config *)&desc.params.raw;
1890 enum i40e_status_code status;
1891
1892 if (max_frame_size == 0)
1893 return I40E_ERR_PARAM;
1894
1895 i40e_fill_default_direct_cmd_desc(&desc,
1896 i40e_aqc_opc_set_mac_config);
1897
1898 cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1899 cmd->params = ((u8)pacing & 0x0F) << 3;
1900 if (crc_en)
1901 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1902
1903 if (auto_drop_blocking_packets) {
1904 if (hw->flags & I40E_HW_FLAG_DROP_MODE)
1905 cmd->params |=
1906 I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN;
1907 else
1908 i40e_debug(hw, I40E_DEBUG_ALL,
1909 "This FW api version does not support drop mode.\n");
1910 }
1911
1912 #define I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD 0x7FFF
1913 cmd->fc_refresh_threshold =
1914 CPU_TO_LE16(I40E_AQ_SET_MAC_CONFIG_FC_DEFAULT_THRESHOLD);
1915
1916 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1917
1918 return status;
1919 }
1920
1921 /**
1922 * i40e_aq_clear_pxe_mode
1923 * @hw: pointer to the hw struct
1924 * @cmd_details: pointer to command details structure or NULL
1925 *
1926 * Tell the firmware that the driver is taking over from PXE
1927 **/
i40e_aq_clear_pxe_mode(struct i40e_hw * hw,struct i40e_asq_cmd_details * cmd_details)1928 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1929 struct i40e_asq_cmd_details *cmd_details)
1930 {
1931 enum i40e_status_code status;
1932 struct i40e_aq_desc desc;
1933 struct i40e_aqc_clear_pxe *cmd =
1934 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1935
1936 i40e_fill_default_direct_cmd_desc(&desc,
1937 i40e_aqc_opc_clear_pxe_mode);
1938
1939 cmd->rx_cnt = 0x2;
1940
1941 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1942
1943 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1944
1945 return status;
1946 }
1947
1948 /**
1949 * i40e_aq_set_link_restart_an
1950 * @hw: pointer to the hw struct
1951 * @enable_link: if TRUE: enable link, if FALSE: disable link
1952 * @cmd_details: pointer to command details structure or NULL
1953 *
1954 * Sets up the link and restarts the Auto-Negotiation over the link.
1955 **/
i40e_aq_set_link_restart_an(struct i40e_hw * hw,bool enable_link,struct i40e_asq_cmd_details * cmd_details)1956 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1957 bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1958 {
1959 struct i40e_aq_desc desc;
1960 struct i40e_aqc_set_link_restart_an *cmd =
1961 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1962 enum i40e_status_code status;
1963
1964 i40e_fill_default_direct_cmd_desc(&desc,
1965 i40e_aqc_opc_set_link_restart_an);
1966
1967 cmd->command = I40E_AQ_PHY_RESTART_AN;
1968 if (enable_link)
1969 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1970 else
1971 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1972
1973 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1974
1975 return status;
1976 }
1977
1978 /**
1979 * i40e_aq_get_link_info
1980 * @hw: pointer to the hw struct
1981 * @enable_lse: enable/disable LinkStatusEvent reporting
1982 * @link: pointer to link status structure - optional
1983 * @cmd_details: pointer to command details structure or NULL
1984 *
1985 * Returns the link status of the adapter.
1986 **/
i40e_aq_get_link_info(struct i40e_hw * hw,bool enable_lse,struct i40e_link_status * link,struct i40e_asq_cmd_details * cmd_details)1987 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1988 bool enable_lse, struct i40e_link_status *link,
1989 struct i40e_asq_cmd_details *cmd_details)
1990 {
1991 struct i40e_aq_desc desc;
1992 struct i40e_aqc_get_link_status *resp =
1993 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1994 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1995 enum i40e_status_code status;
1996 bool tx_pause, rx_pause;
1997 u16 command_flags;
1998
1999 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
2000
2001 if (enable_lse)
2002 command_flags = I40E_AQ_LSE_ENABLE;
2003 else
2004 command_flags = I40E_AQ_LSE_DISABLE;
2005 resp->command_flags = CPU_TO_LE16(command_flags);
2006
2007 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2008
2009 if (status != I40E_SUCCESS)
2010 goto aq_get_link_info_exit;
2011
2012 /* save off old link status information */
2013 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2014 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
2015
2016 /* update link status */
2017 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
2018 hw->phy.media_type = i40e_get_media_type(hw);
2019 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
2020 hw_link_info->link_info = resp->link_info;
2021 hw_link_info->an_info = resp->an_info;
2022 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
2023 I40E_AQ_CONFIG_FEC_RS_ENA);
2024 hw_link_info->ext_info = resp->ext_info;
2025 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
2026 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
2027 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
2028
2029 /* update fc info */
2030 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
2031 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
2032 if (tx_pause & rx_pause)
2033 hw->fc.current_mode = I40E_FC_FULL;
2034 else if (tx_pause)
2035 hw->fc.current_mode = I40E_FC_TX_PAUSE;
2036 else if (rx_pause)
2037 hw->fc.current_mode = I40E_FC_RX_PAUSE;
2038 else
2039 hw->fc.current_mode = I40E_FC_NONE;
2040
2041 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
2042 hw_link_info->crc_enable = TRUE;
2043 else
2044 hw_link_info->crc_enable = FALSE;
2045
2046 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
2047 hw_link_info->lse_enable = TRUE;
2048 else
2049 hw_link_info->lse_enable = FALSE;
2050
2051 if ((hw->mac.type == I40E_MAC_XL710) &&
2052 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
2053 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
2054 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
2055
2056 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
2057 hw->mac.type != I40E_MAC_X722) {
2058 __le32 tmp;
2059
2060 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
2061 I40E_NONDMA_TO_NONDMA);
2062 hw->phy.phy_types = LE32_TO_CPU(tmp);
2063 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
2064 }
2065
2066 /* save link status information */
2067 if (link)
2068 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
2069 I40E_NONDMA_TO_NONDMA);
2070
2071 /* flag cleared so helper functions don't call AQ again */
2072 hw->phy.get_link_info = FALSE;
2073
2074 aq_get_link_info_exit:
2075 return status;
2076 }
2077
2078 /**
2079 * i40e_aq_set_phy_int_mask
2080 * @hw: pointer to the hw struct
2081 * @mask: interrupt mask to be set
2082 * @cmd_details: pointer to command details structure or NULL
2083 *
2084 * Set link interrupt mask.
2085 **/
i40e_aq_set_phy_int_mask(struct i40e_hw * hw,u16 mask,struct i40e_asq_cmd_details * cmd_details)2086 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
2087 u16 mask,
2088 struct i40e_asq_cmd_details *cmd_details)
2089 {
2090 struct i40e_aq_desc desc;
2091 struct i40e_aqc_set_phy_int_mask *cmd =
2092 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
2093 enum i40e_status_code status;
2094
2095 i40e_fill_default_direct_cmd_desc(&desc,
2096 i40e_aqc_opc_set_phy_int_mask);
2097
2098 cmd->event_mask = CPU_TO_LE16(mask);
2099
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101
2102 return status;
2103 }
2104
2105 /**
2106 * i40e_aq_get_local_advt_reg
2107 * @hw: pointer to the hw struct
2108 * @advt_reg: local AN advertisement register value
2109 * @cmd_details: pointer to command details structure or NULL
2110 *
2111 * Get the Local AN advertisement register value.
2112 **/
i40e_aq_get_local_advt_reg(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)2113 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2114 u64 *advt_reg,
2115 struct i40e_asq_cmd_details *cmd_details)
2116 {
2117 struct i40e_aq_desc desc;
2118 struct i40e_aqc_an_advt_reg *resp =
2119 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2120 enum i40e_status_code status;
2121
2122 i40e_fill_default_direct_cmd_desc(&desc,
2123 i40e_aqc_opc_get_local_advt_reg);
2124
2125 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2126
2127 if (status != I40E_SUCCESS)
2128 goto aq_get_local_advt_reg_exit;
2129
2130 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2131 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2132
2133 aq_get_local_advt_reg_exit:
2134 return status;
2135 }
2136
2137 /**
2138 * i40e_aq_set_local_advt_reg
2139 * @hw: pointer to the hw struct
2140 * @advt_reg: local AN advertisement register value
2141 * @cmd_details: pointer to command details structure or NULL
2142 *
2143 * Get the Local AN advertisement register value.
2144 **/
i40e_aq_set_local_advt_reg(struct i40e_hw * hw,u64 advt_reg,struct i40e_asq_cmd_details * cmd_details)2145 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2146 u64 advt_reg,
2147 struct i40e_asq_cmd_details *cmd_details)
2148 {
2149 struct i40e_aq_desc desc;
2150 struct i40e_aqc_an_advt_reg *cmd =
2151 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2152 enum i40e_status_code status;
2153
2154 i40e_fill_default_direct_cmd_desc(&desc,
2155 i40e_aqc_opc_get_local_advt_reg);
2156
2157 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2158 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2159
2160 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2161
2162 return status;
2163 }
2164
2165 /**
2166 * i40e_aq_get_partner_advt
2167 * @hw: pointer to the hw struct
2168 * @advt_reg: AN partner advertisement register value
2169 * @cmd_details: pointer to command details structure or NULL
2170 *
2171 * Get the link partner AN advertisement register value.
2172 **/
i40e_aq_get_partner_advt(struct i40e_hw * hw,u64 * advt_reg,struct i40e_asq_cmd_details * cmd_details)2173 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2174 u64 *advt_reg,
2175 struct i40e_asq_cmd_details *cmd_details)
2176 {
2177 struct i40e_aq_desc desc;
2178 struct i40e_aqc_an_advt_reg *resp =
2179 (struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2180 enum i40e_status_code status;
2181
2182 i40e_fill_default_direct_cmd_desc(&desc,
2183 i40e_aqc_opc_get_partner_advt);
2184
2185 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2186
2187 if (status != I40E_SUCCESS)
2188 goto aq_get_partner_advt_exit;
2189
2190 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2191 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2192
2193 aq_get_partner_advt_exit:
2194 return status;
2195 }
2196
2197 /**
2198 * i40e_aq_set_lb_modes
2199 * @hw: pointer to the hw struct
2200 * @lb_modes: loopback mode to be set
2201 * @cmd_details: pointer to command details structure or NULL
2202 *
2203 * Sets loopback modes.
2204 **/
2205 enum i40e_status_code
i40e_aq_set_lb_modes(struct i40e_hw * hw,u8 lb_level,u8 lb_type,u8 speed,struct i40e_asq_cmd_details * cmd_details)2206 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed,
2207 struct i40e_asq_cmd_details *cmd_details)
2208 {
2209 struct i40e_aq_desc desc;
2210 struct i40e_aqc_set_lb_mode *cmd =
2211 (struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2212 enum i40e_status_code status;
2213
2214 i40e_fill_default_direct_cmd_desc(&desc,
2215 i40e_aqc_opc_set_lb_modes);
2216
2217 cmd->lb_level = lb_level;
2218 cmd->lb_type = lb_type;
2219 cmd->speed = speed;
2220 if (speed)
2221 cmd->force_speed = 1;
2222
2223 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2224
2225 return status;
2226 }
2227
2228 /**
2229 * i40e_aq_set_phy_debug
2230 * @hw: pointer to the hw struct
2231 * @cmd_flags: debug command flags
2232 * @cmd_details: pointer to command details structure or NULL
2233 *
2234 * Reset the external PHY.
2235 **/
i40e_aq_set_phy_debug(struct i40e_hw * hw,u8 cmd_flags,struct i40e_asq_cmd_details * cmd_details)2236 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2237 struct i40e_asq_cmd_details *cmd_details)
2238 {
2239 struct i40e_aq_desc desc;
2240 struct i40e_aqc_set_phy_debug *cmd =
2241 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2242 enum i40e_status_code status;
2243
2244 i40e_fill_default_direct_cmd_desc(&desc,
2245 i40e_aqc_opc_set_phy_debug);
2246
2247 cmd->command_flags = cmd_flags;
2248
2249 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250
2251 return status;
2252 }
2253
2254 /**
2255 * i40e_aq_add_vsi
2256 * @hw: pointer to the hw struct
2257 * @vsi_ctx: pointer to a vsi context struct
2258 * @cmd_details: pointer to command details structure or NULL
2259 *
2260 * Add a VSI context to the hardware.
2261 **/
i40e_aq_add_vsi(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2262 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2263 struct i40e_vsi_context *vsi_ctx,
2264 struct i40e_asq_cmd_details *cmd_details)
2265 {
2266 struct i40e_aq_desc desc;
2267 struct i40e_aqc_add_get_update_vsi *cmd =
2268 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2269 struct i40e_aqc_add_get_update_vsi_completion *resp =
2270 (struct i40e_aqc_add_get_update_vsi_completion *)
2271 &desc.params.raw;
2272 enum i40e_status_code status;
2273
2274 i40e_fill_default_direct_cmd_desc(&desc,
2275 i40e_aqc_opc_add_vsi);
2276
2277 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2278 cmd->connection_type = vsi_ctx->connection_type;
2279 cmd->vf_id = vsi_ctx->vf_num;
2280 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2281
2282 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2283
2284 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2285 sizeof(vsi_ctx->info), cmd_details);
2286
2287 if (status != I40E_SUCCESS)
2288 goto aq_add_vsi_exit;
2289
2290 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2291 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2292 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2293 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2294
2295 aq_add_vsi_exit:
2296 return status;
2297 }
2298
2299 /**
2300 * i40e_aq_set_default_vsi
2301 * @hw: pointer to the hw struct
2302 * @seid: vsi number
2303 * @cmd_details: pointer to command details structure or NULL
2304 **/
i40e_aq_set_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)2305 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2306 u16 seid,
2307 struct i40e_asq_cmd_details *cmd_details)
2308 {
2309 struct i40e_aq_desc desc;
2310 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2311 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2312 &desc.params.raw;
2313 enum i40e_status_code status;
2314
2315 i40e_fill_default_direct_cmd_desc(&desc,
2316 i40e_aqc_opc_set_vsi_promiscuous_modes);
2317
2318 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2319 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2320 cmd->seid = CPU_TO_LE16(seid);
2321
2322 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2323
2324 return status;
2325 }
2326
2327 /**
2328 * i40e_aq_clear_default_vsi
2329 * @hw: pointer to the hw struct
2330 * @seid: vsi number
2331 * @cmd_details: pointer to command details structure or NULL
2332 **/
i40e_aq_clear_default_vsi(struct i40e_hw * hw,u16 seid,struct i40e_asq_cmd_details * cmd_details)2333 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2334 u16 seid,
2335 struct i40e_asq_cmd_details *cmd_details)
2336 {
2337 struct i40e_aq_desc desc;
2338 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2339 (struct i40e_aqc_set_vsi_promiscuous_modes *)
2340 &desc.params.raw;
2341 enum i40e_status_code status;
2342
2343 i40e_fill_default_direct_cmd_desc(&desc,
2344 i40e_aqc_opc_set_vsi_promiscuous_modes);
2345
2346 cmd->promiscuous_flags = CPU_TO_LE16(0);
2347 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2348 cmd->seid = CPU_TO_LE16(seid);
2349
2350 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2351
2352 return status;
2353 }
2354
2355 /**
2356 * i40e_aq_set_vsi_unicast_promiscuous
2357 * @hw: pointer to the hw struct
2358 * @seid: vsi number
2359 * @set: set unicast promiscuous enable/disable
2360 * @cmd_details: pointer to command details structure or NULL
2361 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2362 **/
i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details,bool rx_only_promisc)2363 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2364 u16 seid, bool set,
2365 struct i40e_asq_cmd_details *cmd_details,
2366 bool rx_only_promisc)
2367 {
2368 struct i40e_aq_desc desc;
2369 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2370 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2371 enum i40e_status_code status;
2372 u16 flags = 0;
2373
2374 i40e_fill_default_direct_cmd_desc(&desc,
2375 i40e_aqc_opc_set_vsi_promiscuous_modes);
2376
2377 if (set) {
2378 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2379 if (rx_only_promisc &&
2380 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2381 (hw->aq.api_maj_ver > 1)))
2382 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2383 }
2384
2385 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2386
2387 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2388 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2389 (hw->aq.api_maj_ver > 1))
2390 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2391
2392 cmd->seid = CPU_TO_LE16(seid);
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394
2395 return status;
2396 }
2397
2398 /**
2399 * i40e_aq_set_vsi_multicast_promiscuous
2400 * @hw: pointer to the hw struct
2401 * @seid: vsi number
2402 * @set: set multicast promiscuous enable/disable
2403 * @cmd_details: pointer to command details structure or NULL
2404 **/
i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)2405 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2406 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2407 {
2408 struct i40e_aq_desc desc;
2409 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2410 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2411 enum i40e_status_code status;
2412 u16 flags = 0;
2413
2414 i40e_fill_default_direct_cmd_desc(&desc,
2415 i40e_aqc_opc_set_vsi_promiscuous_modes);
2416
2417 if (set)
2418 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2419
2420 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2421
2422 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2423
2424 cmd->seid = CPU_TO_LE16(seid);
2425 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2426
2427 return status;
2428 }
2429
2430 /**
2431 * i40e_aq_set_vsi_full_promiscuous
2432 * @hw: pointer to the hw struct
2433 * @seid: VSI number
2434 * @set: set promiscuous enable/disable
2435 * @cmd_details: pointer to command details structure or NULL
2436 **/
i40e_aq_set_vsi_full_promiscuous(struct i40e_hw * hw,u16 seid,bool set,struct i40e_asq_cmd_details * cmd_details)2437 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
2438 u16 seid, bool set,
2439 struct i40e_asq_cmd_details *cmd_details)
2440 {
2441 struct i40e_aq_desc desc;
2442 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2443 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2444 enum i40e_status_code status;
2445 u16 flags = 0;
2446
2447 i40e_fill_default_direct_cmd_desc(&desc,
2448 i40e_aqc_opc_set_vsi_promiscuous_modes);
2449
2450 if (set)
2451 flags = I40E_AQC_SET_VSI_PROMISC_UNICAST |
2452 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2453 I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2454
2455 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2456
2457 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST |
2458 I40E_AQC_SET_VSI_PROMISC_MULTICAST |
2459 I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2460
2461 cmd->seid = CPU_TO_LE16(seid);
2462 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2463
2464 return status;
2465 }
2466
2467 /**
2468 * i40e_aq_set_vsi_mc_promisc_on_vlan
2469 * @hw: pointer to the hw struct
2470 * @seid: vsi number
2471 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2472 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2473 * @cmd_details: pointer to command details structure or NULL
2474 **/
i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2475 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2476 u16 seid, bool enable, u16 vid,
2477 struct i40e_asq_cmd_details *cmd_details)
2478 {
2479 struct i40e_aq_desc desc;
2480 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2481 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2482 enum i40e_status_code status;
2483 u16 flags = 0;
2484
2485 i40e_fill_default_direct_cmd_desc(&desc,
2486 i40e_aqc_opc_set_vsi_promiscuous_modes);
2487
2488 if (enable)
2489 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2490
2491 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2492 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2493 cmd->seid = CPU_TO_LE16(seid);
2494 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2495
2496 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2497
2498 return status;
2499 }
2500
2501 /**
2502 * i40e_aq_set_vsi_uc_promisc_on_vlan
2503 * @hw: pointer to the hw struct
2504 * @seid: vsi number
2505 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2506 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2507 * @cmd_details: pointer to command details structure or NULL
2508 **/
i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2509 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2510 u16 seid, bool enable, u16 vid,
2511 struct i40e_asq_cmd_details *cmd_details)
2512 {
2513 struct i40e_aq_desc desc;
2514 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2515 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2516 enum i40e_status_code status;
2517 u16 flags = 0;
2518
2519 i40e_fill_default_direct_cmd_desc(&desc,
2520 i40e_aqc_opc_set_vsi_promiscuous_modes);
2521
2522 if (enable)
2523 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2524
2525 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2526 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2527 cmd->seid = CPU_TO_LE16(seid);
2528 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2529
2530 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2531
2532 return status;
2533 }
2534
2535 /**
2536 * i40e_aq_set_vsi_bc_promisc_on_vlan
2537 * @hw: pointer to the hw struct
2538 * @seid: vsi number
2539 * @enable: set broadcast promiscuous enable/disable for a given VLAN
2540 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2541 * @cmd_details: pointer to command details structure or NULL
2542 **/
i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw * hw,u16 seid,bool enable,u16 vid,struct i40e_asq_cmd_details * cmd_details)2543 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2544 u16 seid, bool enable, u16 vid,
2545 struct i40e_asq_cmd_details *cmd_details)
2546 {
2547 struct i40e_aq_desc desc;
2548 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2549 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2550 enum i40e_status_code status;
2551 u16 flags = 0;
2552
2553 i40e_fill_default_direct_cmd_desc(&desc,
2554 i40e_aqc_opc_set_vsi_promiscuous_modes);
2555
2556 if (enable)
2557 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2558
2559 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2560 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2561 cmd->seid = CPU_TO_LE16(seid);
2562 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2563
2564 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2565
2566 return status;
2567 }
2568
2569 /**
2570 * i40e_aq_set_vsi_broadcast
2571 * @hw: pointer to the hw struct
2572 * @seid: vsi number
2573 * @set_filter: TRUE to set filter, FALSE to clear filter
2574 * @cmd_details: pointer to command details structure or NULL
2575 *
2576 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2577 **/
i40e_aq_set_vsi_broadcast(struct i40e_hw * hw,u16 seid,bool set_filter,struct i40e_asq_cmd_details * cmd_details)2578 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2579 u16 seid, bool set_filter,
2580 struct i40e_asq_cmd_details *cmd_details)
2581 {
2582 struct i40e_aq_desc desc;
2583 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2584 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2585 enum i40e_status_code status;
2586
2587 i40e_fill_default_direct_cmd_desc(&desc,
2588 i40e_aqc_opc_set_vsi_promiscuous_modes);
2589
2590 if (set_filter)
2591 cmd->promiscuous_flags
2592 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2593 else
2594 cmd->promiscuous_flags
2595 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2596
2597 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2598 cmd->seid = CPU_TO_LE16(seid);
2599 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2600
2601 return status;
2602 }
2603
2604 /**
2605 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2606 * @hw: pointer to the hw struct
2607 * @seid: vsi number
2608 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2609 * @cmd_details: pointer to command details structure or NULL
2610 **/
i40e_aq_set_vsi_vlan_promisc(struct i40e_hw * hw,u16 seid,bool enable,struct i40e_asq_cmd_details * cmd_details)2611 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2612 u16 seid, bool enable,
2613 struct i40e_asq_cmd_details *cmd_details)
2614 {
2615 struct i40e_aq_desc desc;
2616 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2617 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2618 enum i40e_status_code status;
2619 u16 flags = 0;
2620
2621 i40e_fill_default_direct_cmd_desc(&desc,
2622 i40e_aqc_opc_set_vsi_promiscuous_modes);
2623 if (enable)
2624 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2625
2626 cmd->promiscuous_flags = CPU_TO_LE16(flags);
2627 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2628 cmd->seid = CPU_TO_LE16(seid);
2629
2630 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2631
2632 return status;
2633 }
2634
2635 /**
2636 * i40e_get_vsi_params - get VSI configuration info
2637 * @hw: pointer to the hw struct
2638 * @vsi_ctx: pointer to a vsi context struct
2639 * @cmd_details: pointer to command details structure or NULL
2640 **/
i40e_aq_get_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2641 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2642 struct i40e_vsi_context *vsi_ctx,
2643 struct i40e_asq_cmd_details *cmd_details)
2644 {
2645 struct i40e_aq_desc desc;
2646 struct i40e_aqc_add_get_update_vsi *cmd =
2647 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2648 struct i40e_aqc_add_get_update_vsi_completion *resp =
2649 (struct i40e_aqc_add_get_update_vsi_completion *)
2650 &desc.params.raw;
2651 enum i40e_status_code status;
2652
2653 i40e_fill_default_direct_cmd_desc(&desc,
2654 i40e_aqc_opc_get_vsi_parameters);
2655
2656 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2657
2658 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2659
2660 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2661 sizeof(vsi_ctx->info), NULL);
2662
2663 if (status != I40E_SUCCESS)
2664 goto aq_get_vsi_params_exit;
2665
2666 vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2667 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2668 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2669 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2670
2671 aq_get_vsi_params_exit:
2672 return status;
2673 }
2674
2675 /**
2676 * i40e_aq_update_vsi_params
2677 * @hw: pointer to the hw struct
2678 * @vsi_ctx: pointer to a vsi context struct
2679 * @cmd_details: pointer to command details structure or NULL
2680 *
2681 * Update a VSI context.
2682 **/
i40e_aq_update_vsi_params(struct i40e_hw * hw,struct i40e_vsi_context * vsi_ctx,struct i40e_asq_cmd_details * cmd_details)2683 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2684 struct i40e_vsi_context *vsi_ctx,
2685 struct i40e_asq_cmd_details *cmd_details)
2686 {
2687 struct i40e_aq_desc desc;
2688 struct i40e_aqc_add_get_update_vsi *cmd =
2689 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2690 struct i40e_aqc_add_get_update_vsi_completion *resp =
2691 (struct i40e_aqc_add_get_update_vsi_completion *)
2692 &desc.params.raw;
2693 enum i40e_status_code status;
2694
2695 i40e_fill_default_direct_cmd_desc(&desc,
2696 i40e_aqc_opc_update_vsi_parameters);
2697 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2698
2699 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2700
2701 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2702 sizeof(vsi_ctx->info), cmd_details);
2703
2704 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2705 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2706
2707 return status;
2708 }
2709
2710 /**
2711 * i40e_aq_get_switch_config
2712 * @hw: pointer to the hardware structure
2713 * @buf: pointer to the result buffer
2714 * @buf_size: length of input buffer
2715 * @start_seid: seid to start for the report, 0 == beginning
2716 * @cmd_details: pointer to command details structure or NULL
2717 *
2718 * Fill the buf with switch configuration returned from AdminQ command
2719 **/
i40e_aq_get_switch_config(struct i40e_hw * hw,struct i40e_aqc_get_switch_config_resp * buf,u16 buf_size,u16 * start_seid,struct i40e_asq_cmd_details * cmd_details)2720 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2721 struct i40e_aqc_get_switch_config_resp *buf,
2722 u16 buf_size, u16 *start_seid,
2723 struct i40e_asq_cmd_details *cmd_details)
2724 {
2725 struct i40e_aq_desc desc;
2726 struct i40e_aqc_switch_seid *scfg =
2727 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2728 enum i40e_status_code status;
2729
2730 i40e_fill_default_direct_cmd_desc(&desc,
2731 i40e_aqc_opc_get_switch_config);
2732 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2733 if (buf_size > I40E_AQ_LARGE_BUF)
2734 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2735 scfg->seid = CPU_TO_LE16(*start_seid);
2736
2737 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2738 *start_seid = LE16_TO_CPU(scfg->seid);
2739
2740 return status;
2741 }
2742
2743 /**
2744 * i40e_aq_set_switch_config
2745 * @hw: pointer to the hardware structure
2746 * @flags: bit flag values to set
2747 * @mode: cloud filter mode
2748 * @valid_flags: which bit flags to set
2749 * @cmd_details: pointer to command details structure or NULL
2750 *
2751 * Set switch configuration bits
2752 **/
i40e_aq_set_switch_config(struct i40e_hw * hw,u16 flags,u16 valid_flags,u8 mode,struct i40e_asq_cmd_details * cmd_details)2753 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2754 u16 flags, u16 valid_flags, u8 mode,
2755 struct i40e_asq_cmd_details *cmd_details)
2756 {
2757 struct i40e_aq_desc desc;
2758 struct i40e_aqc_set_switch_config *scfg =
2759 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2760 enum i40e_status_code status;
2761
2762 i40e_fill_default_direct_cmd_desc(&desc,
2763 i40e_aqc_opc_set_switch_config);
2764 scfg->flags = CPU_TO_LE16(flags);
2765 scfg->valid_flags = CPU_TO_LE16(valid_flags);
2766 scfg->mode = mode;
2767 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2768 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2769 scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2770 scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2771 }
2772 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2773
2774 return status;
2775 }
2776
2777 /**
2778 * i40e_aq_get_firmware_version
2779 * @hw: pointer to the hw struct
2780 * @fw_major_version: firmware major version
2781 * @fw_minor_version: firmware minor version
2782 * @fw_build: firmware build number
2783 * @api_major_version: major queue version
2784 * @api_minor_version: minor queue version
2785 * @cmd_details: pointer to command details structure or NULL
2786 *
2787 * Get the firmware version from the admin queue commands
2788 **/
i40e_aq_get_firmware_version(struct i40e_hw * hw,u16 * fw_major_version,u16 * fw_minor_version,u32 * fw_build,u16 * api_major_version,u16 * api_minor_version,struct i40e_asq_cmd_details * cmd_details)2789 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2790 u16 *fw_major_version, u16 *fw_minor_version,
2791 u32 *fw_build,
2792 u16 *api_major_version, u16 *api_minor_version,
2793 struct i40e_asq_cmd_details *cmd_details)
2794 {
2795 struct i40e_aq_desc desc;
2796 struct i40e_aqc_get_version *resp =
2797 (struct i40e_aqc_get_version *)&desc.params.raw;
2798 enum i40e_status_code status;
2799
2800 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2801
2802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2803
2804 if (status == I40E_SUCCESS) {
2805 if (fw_major_version != NULL)
2806 *fw_major_version = LE16_TO_CPU(resp->fw_major);
2807 if (fw_minor_version != NULL)
2808 *fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2809 if (fw_build != NULL)
2810 *fw_build = LE32_TO_CPU(resp->fw_build);
2811 if (api_major_version != NULL)
2812 *api_major_version = LE16_TO_CPU(resp->api_major);
2813 if (api_minor_version != NULL)
2814 *api_minor_version = LE16_TO_CPU(resp->api_minor);
2815
2816 /* A workaround to fix the API version in SW */
2817 if (api_major_version && api_minor_version &&
2818 fw_major_version && fw_minor_version &&
2819 ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2820 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2821 (*fw_major_version > 4)))
2822 *api_minor_version = 2;
2823 }
2824
2825 return status;
2826 }
2827
2828 /**
2829 * i40e_aq_send_driver_version
2830 * @hw: pointer to the hw struct
2831 * @dv: driver's major, minor version
2832 * @cmd_details: pointer to command details structure or NULL
2833 *
2834 * Send the driver version to the firmware
2835 **/
i40e_aq_send_driver_version(struct i40e_hw * hw,struct i40e_driver_version * dv,struct i40e_asq_cmd_details * cmd_details)2836 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2837 struct i40e_driver_version *dv,
2838 struct i40e_asq_cmd_details *cmd_details)
2839 {
2840 struct i40e_aq_desc desc;
2841 struct i40e_aqc_driver_version *cmd =
2842 (struct i40e_aqc_driver_version *)&desc.params.raw;
2843 enum i40e_status_code status;
2844 u16 len;
2845
2846 if (dv == NULL)
2847 return I40E_ERR_PARAM;
2848
2849 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2850
2851 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2852 cmd->driver_major_ver = dv->major_version;
2853 cmd->driver_minor_ver = dv->minor_version;
2854 cmd->driver_build_ver = dv->build_version;
2855 cmd->driver_subbuild_ver = dv->subbuild_version;
2856
2857 len = 0;
2858 while (len < sizeof(dv->driver_string) &&
2859 (dv->driver_string[len] < 0x80) &&
2860 dv->driver_string[len])
2861 len++;
2862 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2863 len, cmd_details);
2864
2865 return status;
2866 }
2867
2868 /**
2869 * i40e_get_link_status - get status of the HW network link
2870 * @hw: pointer to the hw struct
2871 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2872 *
2873 * Variable link_up TRUE if link is up, FALSE if link is down.
2874 * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2875 *
2876 * Side effect: LinkStatusEvent reporting becomes enabled
2877 **/
i40e_get_link_status(struct i40e_hw * hw,bool * link_up)2878 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2879 {
2880 enum i40e_status_code status = I40E_SUCCESS;
2881
2882 if (hw->phy.get_link_info) {
2883 status = i40e_update_link_info(hw);
2884
2885 if (status != I40E_SUCCESS)
2886 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2887 status);
2888 }
2889
2890 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2891
2892 return status;
2893 }
2894
2895 /**
2896 * i40e_updatelink_status - update status of the HW network link
2897 * @hw: pointer to the hw struct
2898 **/
i40e_update_link_info(struct i40e_hw * hw)2899 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2900 {
2901 struct i40e_aq_get_phy_abilities_resp abilities;
2902 enum i40e_status_code status = I40E_SUCCESS;
2903
2904 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2905 if (status)
2906 return status;
2907
2908 /* extra checking needed to ensure link info to user is timely */
2909 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2910 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2911 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2912 status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
2913 &abilities, NULL);
2914 if (status)
2915 return status;
2916
2917 if (abilities.fec_cfg_curr_mod_ext_info &
2918 I40E_AQ_ENABLE_FEC_AUTO)
2919 hw->phy.link_info.req_fec_info =
2920 (I40E_AQ_REQUEST_FEC_KR |
2921 I40E_AQ_REQUEST_FEC_RS);
2922 else
2923 hw->phy.link_info.req_fec_info =
2924 abilities.fec_cfg_curr_mod_ext_info &
2925 (I40E_AQ_REQUEST_FEC_KR |
2926 I40E_AQ_REQUEST_FEC_RS);
2927
2928 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2929 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2930 }
2931 return status;
2932 }
2933
2934
2935 /**
2936 * i40e_get_link_speed
2937 * @hw: pointer to the hw struct
2938 *
2939 * Returns the link speed of the adapter.
2940 **/
i40e_get_link_speed(struct i40e_hw * hw)2941 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2942 {
2943 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2944 enum i40e_status_code status = I40E_SUCCESS;
2945
2946 if (hw->phy.get_link_info) {
2947 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2948
2949 if (status != I40E_SUCCESS)
2950 goto i40e_link_speed_exit;
2951 }
2952
2953 speed = hw->phy.link_info.link_speed;
2954
2955 i40e_link_speed_exit:
2956 return speed;
2957 }
2958
2959 /**
2960 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2961 * @hw: pointer to the hw struct
2962 * @uplink_seid: the MAC or other gizmo SEID
2963 * @downlink_seid: the VSI SEID
2964 * @enabled_tc: bitmap of TCs to be enabled
2965 * @default_port: TRUE for default port VSI, FALSE for control port
2966 * @veb_seid: pointer to where to put the resulting VEB SEID
2967 * @enable_stats: TRUE to turn on VEB stats
2968 * @cmd_details: pointer to command details structure or NULL
2969 *
2970 * This asks the FW to add a VEB between the uplink and downlink
2971 * elements. If the uplink SEID is 0, this will be a floating VEB.
2972 **/
i40e_aq_add_veb(struct i40e_hw * hw,u16 uplink_seid,u16 downlink_seid,u8 enabled_tc,bool default_port,u16 * veb_seid,bool enable_stats,struct i40e_asq_cmd_details * cmd_details)2973 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2974 u16 downlink_seid, u8 enabled_tc,
2975 bool default_port, u16 *veb_seid,
2976 bool enable_stats,
2977 struct i40e_asq_cmd_details *cmd_details)
2978 {
2979 struct i40e_aq_desc desc;
2980 struct i40e_aqc_add_veb *cmd =
2981 (struct i40e_aqc_add_veb *)&desc.params.raw;
2982 struct i40e_aqc_add_veb_completion *resp =
2983 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2984 enum i40e_status_code status;
2985 u16 veb_flags = 0;
2986
2987 /* SEIDs need to either both be set or both be 0 for floating VEB */
2988 if (!!uplink_seid != !!downlink_seid)
2989 return I40E_ERR_PARAM;
2990
2991 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2992
2993 cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2994 cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2995 cmd->enable_tcs = enabled_tc;
2996 if (!uplink_seid)
2997 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2998 if (default_port)
2999 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
3000 else
3001 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
3002
3003 /* reverse logic here: set the bitflag t