1 /****************************************************************************** 2 3 Copyright (c) 2013-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_KX_X722: 72 case I40E_DEV_ID_QSFP_X722: 73 case I40E_DEV_ID_SFP_X722: 74 case I40E_DEV_ID_1G_BASE_T_X722: 75 case I40E_DEV_ID_10G_BASE_T_X722: 76 case I40E_DEV_ID_SFP_I_X722: 77 hw->mac.type = I40E_MAC_X722; 78 break; 79 default: 80 hw->mac.type = I40E_MAC_GENERIC; 81 break; 82 } 83 } else { 84 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 85 } 86 87 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 88 hw->mac.type, status); 89 return status; 90 } 91 92 /** 93 * i40e_aq_str - convert AQ err code to a string 94 * @hw: pointer to the HW structure 95 * @aq_err: the AQ error code to convert 96 **/ 97 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 98 { 99 switch (aq_err) { 100 case I40E_AQ_RC_OK: 101 return "OK"; 102 case I40E_AQ_RC_EPERM: 103 return "I40E_AQ_RC_EPERM"; 104 case I40E_AQ_RC_ENOENT: 105 return "I40E_AQ_RC_ENOENT"; 106 case I40E_AQ_RC_ESRCH: 107 return "I40E_AQ_RC_ESRCH"; 108 case I40E_AQ_RC_EINTR: 109 return "I40E_AQ_RC_EINTR"; 110 case I40E_AQ_RC_EIO: 111 return "I40E_AQ_RC_EIO"; 112 case I40E_AQ_RC_ENXIO: 113 return "I40E_AQ_RC_ENXIO"; 114 case I40E_AQ_RC_E2BIG: 115 return "I40E_AQ_RC_E2BIG"; 116 case I40E_AQ_RC_EAGAIN: 117 return "I40E_AQ_RC_EAGAIN"; 118 case I40E_AQ_RC_ENOMEM: 119 return "I40E_AQ_RC_ENOMEM"; 120 case I40E_AQ_RC_EACCES: 121 return "I40E_AQ_RC_EACCES"; 122 case I40E_AQ_RC_EFAULT: 123 return "I40E_AQ_RC_EFAULT"; 124 case I40E_AQ_RC_EBUSY: 125 return "I40E_AQ_RC_EBUSY"; 126 case I40E_AQ_RC_EEXIST: 127 return "I40E_AQ_RC_EEXIST"; 128 case I40E_AQ_RC_EINVAL: 129 return "I40E_AQ_RC_EINVAL"; 130 case I40E_AQ_RC_ENOTTY: 131 return "I40E_AQ_RC_ENOTTY"; 132 case I40E_AQ_RC_ENOSPC: 133 return "I40E_AQ_RC_ENOSPC"; 134 case I40E_AQ_RC_ENOSYS: 135 return "I40E_AQ_RC_ENOSYS"; 136 case I40E_AQ_RC_ERANGE: 137 return "I40E_AQ_RC_ERANGE"; 138 case I40E_AQ_RC_EFLUSHED: 139 return "I40E_AQ_RC_EFLUSHED"; 140 case I40E_AQ_RC_BAD_ADDR: 141 return "I40E_AQ_RC_BAD_ADDR"; 142 case I40E_AQ_RC_EMODE: 143 return "I40E_AQ_RC_EMODE"; 144 case I40E_AQ_RC_EFBIG: 145 return "I40E_AQ_RC_EFBIG"; 146 } 147 148 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 149 return hw->err_str; 150 } 151 152 /** 153 * i40e_stat_str - convert status err code to a string 154 * @hw: pointer to the HW structure 155 * @stat_err: the status error code to convert 156 **/ 157 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 158 { 159 switch (stat_err) { 160 case I40E_SUCCESS: 161 return "OK"; 162 case I40E_ERR_NVM: 163 return "I40E_ERR_NVM"; 164 case I40E_ERR_NVM_CHECKSUM: 165 return "I40E_ERR_NVM_CHECKSUM"; 166 case I40E_ERR_PHY: 167 return "I40E_ERR_PHY"; 168 case I40E_ERR_CONFIG: 169 return "I40E_ERR_CONFIG"; 170 case I40E_ERR_PARAM: 171 return "I40E_ERR_PARAM"; 172 case I40E_ERR_MAC_TYPE: 173 return "I40E_ERR_MAC_TYPE"; 174 case I40E_ERR_UNKNOWN_PHY: 175 return "I40E_ERR_UNKNOWN_PHY"; 176 case I40E_ERR_LINK_SETUP: 177 return "I40E_ERR_LINK_SETUP"; 178 case I40E_ERR_ADAPTER_STOPPED: 179 return "I40E_ERR_ADAPTER_STOPPED"; 180 case I40E_ERR_INVALID_MAC_ADDR: 181 return "I40E_ERR_INVALID_MAC_ADDR"; 182 case I40E_ERR_DEVICE_NOT_SUPPORTED: 183 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 184 case I40E_ERR_MASTER_REQUESTS_PENDING: 185 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 186 case I40E_ERR_INVALID_LINK_SETTINGS: 187 return "I40E_ERR_INVALID_LINK_SETTINGS"; 188 case I40E_ERR_AUTONEG_NOT_COMPLETE: 189 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 190 case I40E_ERR_RESET_FAILED: 191 return "I40E_ERR_RESET_FAILED"; 192 case I40E_ERR_SWFW_SYNC: 193 return "I40E_ERR_SWFW_SYNC"; 194 case I40E_ERR_NO_AVAILABLE_VSI: 195 return "I40E_ERR_NO_AVAILABLE_VSI"; 196 case I40E_ERR_NO_MEMORY: 197 return "I40E_ERR_NO_MEMORY"; 198 case I40E_ERR_BAD_PTR: 199 return "I40E_ERR_BAD_PTR"; 200 case I40E_ERR_RING_FULL: 201 return "I40E_ERR_RING_FULL"; 202 case I40E_ERR_INVALID_PD_ID: 203 return "I40E_ERR_INVALID_PD_ID"; 204 case I40E_ERR_INVALID_QP_ID: 205 return "I40E_ERR_INVALID_QP_ID"; 206 case I40E_ERR_INVALID_CQ_ID: 207 return "I40E_ERR_INVALID_CQ_ID"; 208 case I40E_ERR_INVALID_CEQ_ID: 209 return "I40E_ERR_INVALID_CEQ_ID"; 210 case I40E_ERR_INVALID_AEQ_ID: 211 return "I40E_ERR_INVALID_AEQ_ID"; 212 case I40E_ERR_INVALID_SIZE: 213 return "I40E_ERR_INVALID_SIZE"; 214 case I40E_ERR_INVALID_ARP_INDEX: 215 return "I40E_ERR_INVALID_ARP_INDEX"; 216 case I40E_ERR_INVALID_FPM_FUNC_ID: 217 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 218 case I40E_ERR_QP_INVALID_MSG_SIZE: 219 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 220 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 221 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 222 case I40E_ERR_INVALID_FRAG_COUNT: 223 return "I40E_ERR_INVALID_FRAG_COUNT"; 224 case I40E_ERR_QUEUE_EMPTY: 225 return "I40E_ERR_QUEUE_EMPTY"; 226 case I40E_ERR_INVALID_ALIGNMENT: 227 return "I40E_ERR_INVALID_ALIGNMENT"; 228 case I40E_ERR_FLUSHED_QUEUE: 229 return "I40E_ERR_FLUSHED_QUEUE"; 230 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 231 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 232 case I40E_ERR_INVALID_IMM_DATA_SIZE: 233 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 234 case I40E_ERR_TIMEOUT: 235 return "I40E_ERR_TIMEOUT"; 236 case I40E_ERR_OPCODE_MISMATCH: 237 return "I40E_ERR_OPCODE_MISMATCH"; 238 case I40E_ERR_CQP_COMPL_ERROR: 239 return "I40E_ERR_CQP_COMPL_ERROR"; 240 case I40E_ERR_INVALID_VF_ID: 241 return "I40E_ERR_INVALID_VF_ID"; 242 case I40E_ERR_INVALID_HMCFN_ID: 243 return "I40E_ERR_INVALID_HMCFN_ID"; 244 case I40E_ERR_BACKING_PAGE_ERROR: 245 return "I40E_ERR_BACKING_PAGE_ERROR"; 246 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 247 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 248 case I40E_ERR_INVALID_PBLE_INDEX: 249 return "I40E_ERR_INVALID_PBLE_INDEX"; 250 case I40E_ERR_INVALID_SD_INDEX: 251 return "I40E_ERR_INVALID_SD_INDEX"; 252 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 253 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 254 case I40E_ERR_INVALID_SD_TYPE: 255 return "I40E_ERR_INVALID_SD_TYPE"; 256 case I40E_ERR_MEMCPY_FAILED: 257 return "I40E_ERR_MEMCPY_FAILED"; 258 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 259 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 260 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 261 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 262 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 263 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 264 case I40E_ERR_SRQ_ENABLED: 265 return "I40E_ERR_SRQ_ENABLED"; 266 case I40E_ERR_ADMIN_QUEUE_ERROR: 267 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 268 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 269 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 270 case I40E_ERR_BUF_TOO_SHORT: 271 return "I40E_ERR_BUF_TOO_SHORT"; 272 case I40E_ERR_ADMIN_QUEUE_FULL: 273 return "I40E_ERR_ADMIN_QUEUE_FULL"; 274 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 275 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 276 case I40E_ERR_BAD_IWARP_CQE: 277 return "I40E_ERR_BAD_IWARP_CQE"; 278 case I40E_ERR_NVM_BLANK_MODE: 279 return "I40E_ERR_NVM_BLANK_MODE"; 280 case I40E_ERR_NOT_IMPLEMENTED: 281 return "I40E_ERR_NOT_IMPLEMENTED"; 282 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 283 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 284 case I40E_ERR_DIAG_TEST_FAILED: 285 return "I40E_ERR_DIAG_TEST_FAILED"; 286 case I40E_ERR_NOT_READY: 287 return "I40E_ERR_NOT_READY"; 288 case I40E_NOT_SUPPORTED: 289 return "I40E_NOT_SUPPORTED"; 290 case I40E_ERR_FIRMWARE_API_VERSION: 291 return "I40E_ERR_FIRMWARE_API_VERSION"; 292 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR: 293 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR"; 294 } 295 296 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 297 return hw->err_str; 298 } 299 300 /** 301 * i40e_debug_aq 302 * @hw: debug mask related to admin queue 303 * @mask: debug mask 304 * @desc: pointer to admin queue descriptor 305 * @buffer: pointer to command buffer 306 * @buf_len: max length of buffer 307 * 308 * Dumps debug log about adminq command with descriptor contents. 309 **/ 310 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 311 void *buffer, u16 buf_len) 312 { 313 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 314 u8 *buf = (u8 *)buffer; 315 u16 len; 316 u16 i = 0; 317 318 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 319 return; 320 321 len = LE16_TO_CPU(aq_desc->datalen); 322 323 i40e_debug(hw, mask, 324 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 325 LE16_TO_CPU(aq_desc->opcode), 326 LE16_TO_CPU(aq_desc->flags), 327 LE16_TO_CPU(aq_desc->datalen), 328 LE16_TO_CPU(aq_desc->retval)); 329 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->cookie_high), 331 LE32_TO_CPU(aq_desc->cookie_low)); 332 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.internal.param0), 334 LE32_TO_CPU(aq_desc->params.internal.param1)); 335 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 336 LE32_TO_CPU(aq_desc->params.external.addr_high), 337 LE32_TO_CPU(aq_desc->params.external.addr_low)); 338 339 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 340 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 341 if (buf_len < len) 342 len = buf_len; 343 /* write the full 16-byte chunks */ 344 for (i = 0; i < (len - 16); i += 16) 345 i40e_debug(hw, mask, 346 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 347 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 348 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 349 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 350 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 351 /* the most we could have left is 16 bytes, pad with zeros */ 352 if (i < len) { 353 char d_buf[16]; 354 int j, i_sav; 355 356 i_sav = i; 357 memset(d_buf, 0, sizeof(d_buf)); 358 for (j = 0; i < len; j++, i++) 359 d_buf[j] = buf[i]; 360 i40e_debug(hw, mask, 361 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 362 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 363 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 364 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 365 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 366 } 367 } 368 } 369 370 /** 371 * i40e_check_asq_alive 372 * @hw: pointer to the hw struct 373 * 374 * Returns TRUE if Queue is enabled else FALSE. 375 **/ 376 bool i40e_check_asq_alive(struct i40e_hw *hw) 377 { 378 if (hw->aq.asq.len) 379 return !!(rd32(hw, hw->aq.asq.len) & 380 I40E_PF_ATQLEN_ATQENABLE_MASK); 381 return FALSE; 382 } 383 384 /** 385 * i40e_aq_queue_shutdown 386 * @hw: pointer to the hw struct 387 * @unloading: is the driver unloading itself 388 * 389 * Tell the Firmware that we're shutting down the AdminQ and whether 390 * or not the driver is unloading as well. 391 **/ 392 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 393 bool unloading) 394 { 395 struct i40e_aq_desc desc; 396 struct i40e_aqc_queue_shutdown *cmd = 397 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 398 enum i40e_status_code status; 399 400 i40e_fill_default_direct_cmd_desc(&desc, 401 i40e_aqc_opc_queue_shutdown); 402 403 if (unloading) 404 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 405 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 406 407 return status; 408 } 409 410 /** 411 * i40e_aq_get_set_rss_lut 412 * @hw: pointer to the hardware structure 413 * @vsi_id: vsi fw index 414 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 415 * @lut: pointer to the lut buffer provided by the caller 416 * @lut_size: size of the lut buffer 417 * @set: set TRUE to set the table, FALSE to get the table 418 * 419 * Internal function to get or set RSS look up table 420 **/ 421 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 422 u16 vsi_id, bool pf_lut, 423 u8 *lut, u16 lut_size, 424 bool set) 425 { 426 enum i40e_status_code status; 427 struct i40e_aq_desc desc; 428 struct i40e_aqc_get_set_rss_lut *cmd_resp = 429 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 430 431 if (set) 432 i40e_fill_default_direct_cmd_desc(&desc, 433 i40e_aqc_opc_set_rss_lut); 434 else 435 i40e_fill_default_direct_cmd_desc(&desc, 436 i40e_aqc_opc_get_rss_lut); 437 438 /* Indirect command */ 439 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 440 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 441 442 cmd_resp->vsi_id = 443 CPU_TO_LE16((u16)((vsi_id << 444 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 445 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 446 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 447 448 if (pf_lut) 449 cmd_resp->flags |= CPU_TO_LE16((u16) 450 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 451 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 452 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 453 else 454 cmd_resp->flags |= CPU_TO_LE16((u16) 455 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 456 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 457 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 458 459 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 460 461 return status; 462 } 463 464 /** 465 * i40e_aq_get_rss_lut 466 * @hw: pointer to the hardware structure 467 * @vsi_id: vsi fw index 468 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 469 * @lut: pointer to the lut buffer provided by the caller 470 * @lut_size: size of the lut buffer 471 * 472 * get the RSS lookup table, PF or VSI type 473 **/ 474 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 475 bool pf_lut, u8 *lut, u16 lut_size) 476 { 477 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 478 FALSE); 479 } 480 481 /** 482 * i40e_aq_set_rss_lut 483 * @hw: pointer to the hardware structure 484 * @vsi_id: vsi fw index 485 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 486 * @lut: pointer to the lut buffer provided by the caller 487 * @lut_size: size of the lut buffer 488 * 489 * set the RSS lookup table, PF or VSI type 490 **/ 491 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 492 bool pf_lut, u8 *lut, u16 lut_size) 493 { 494 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 495 } 496 497 /** 498 * i40e_aq_get_set_rss_key 499 * @hw: pointer to the hw struct 500 * @vsi_id: vsi fw index 501 * @key: pointer to key info struct 502 * @set: set TRUE to set the key, FALSE to get the key 503 * 504 * get the RSS key per VSI 505 **/ 506 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 507 u16 vsi_id, 508 struct i40e_aqc_get_set_rss_key_data *key, 509 bool set) 510 { 511 enum i40e_status_code status; 512 struct i40e_aq_desc desc; 513 struct i40e_aqc_get_set_rss_key *cmd_resp = 514 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 515 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 516 517 if (set) 518 i40e_fill_default_direct_cmd_desc(&desc, 519 i40e_aqc_opc_set_rss_key); 520 else 521 i40e_fill_default_direct_cmd_desc(&desc, 522 i40e_aqc_opc_get_rss_key); 523 524 /* Indirect command */ 525 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 526 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 527 528 cmd_resp->vsi_id = 529 CPU_TO_LE16((u16)((vsi_id << 530 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 531 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 532 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 533 534 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 535 536 return status; 537 } 538 539 /** 540 * i40e_aq_get_rss_key 541 * @hw: pointer to the hw struct 542 * @vsi_id: vsi fw index 543 * @key: pointer to key info struct 544 * 545 **/ 546 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 547 u16 vsi_id, 548 struct i40e_aqc_get_set_rss_key_data *key) 549 { 550 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 551 } 552 553 /** 554 * i40e_aq_set_rss_key 555 * @hw: pointer to the hw struct 556 * @vsi_id: vsi fw index 557 * @key: pointer to key info struct 558 * 559 * set the RSS key per VSI 560 **/ 561 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 562 u16 vsi_id, 563 struct i40e_aqc_get_set_rss_key_data *key) 564 { 565 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 566 } 567 568 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 569 * hardware to a bit-field that can be used by SW to more easily determine the 570 * packet type. 571 * 572 * Macros are used to shorten the table lines and make this table human 573 * readable. 574 * 575 * We store the PTYPE in the top byte of the bit field - this is just so that 576 * we can check that the table doesn't have a row missing, as the index into 577 * the table should be the PTYPE. 578 * 579 * Typical work flow: 580 * 581 * IF NOT i40e_ptype_lookup[ptype].known 582 * THEN 583 * Packet is unknown 584 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 585 * Use the rest of the fields to look at the tunnels, inner protocols, etc 586 * ELSE 587 * Use the enum i40e_rx_l2_ptype to decode the packet type 588 * ENDIF 589 */ 590 591 /* macro to make the table lines short */ 592 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 593 { PTYPE, \ 594 1, \ 595 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 596 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 597 I40E_RX_PTYPE_##OUTER_FRAG, \ 598 I40E_RX_PTYPE_TUNNEL_##T, \ 599 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 600 I40E_RX_PTYPE_##TEF, \ 601 I40E_RX_PTYPE_INNER_PROT_##I, \ 602 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 603 604 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 605 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 606 607 /* shorter macros makes the table fit but are terse */ 608 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 609 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 610 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 611 612 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 613 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 614 /* L2 Packet types */ 615 I40E_PTT_UNUSED_ENTRY(0), 616 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 617 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 618 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 619 I40E_PTT_UNUSED_ENTRY(4), 620 I40E_PTT_UNUSED_ENTRY(5), 621 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 622 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 623 I40E_PTT_UNUSED_ENTRY(8), 624 I40E_PTT_UNUSED_ENTRY(9), 625 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 626 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 627 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 628 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 629 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 632 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 633 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 634 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 635 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 636 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 637 638 /* Non Tunneled IPv4 */ 639 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 640 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 641 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 642 I40E_PTT_UNUSED_ENTRY(25), 643 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 644 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 645 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 646 647 /* IPv4 --> IPv4 */ 648 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 649 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 650 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 651 I40E_PTT_UNUSED_ENTRY(32), 652 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 653 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 654 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 655 656 /* IPv4 --> IPv6 */ 657 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 658 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 659 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 660 I40E_PTT_UNUSED_ENTRY(39), 661 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 662 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 663 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 664 665 /* IPv4 --> GRE/NAT */ 666 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 667 668 /* IPv4 --> GRE/NAT --> IPv4 */ 669 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 670 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 671 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 672 I40E_PTT_UNUSED_ENTRY(47), 673 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 674 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 675 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 676 677 /* IPv4 --> GRE/NAT --> IPv6 */ 678 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 679 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 680 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 681 I40E_PTT_UNUSED_ENTRY(54), 682 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 683 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 684 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 685 686 /* IPv4 --> GRE/NAT --> MAC */ 687 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 688 689 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 690 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 691 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 692 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 693 I40E_PTT_UNUSED_ENTRY(62), 694 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 695 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 696 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 697 698 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 699 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 700 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 701 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 702 I40E_PTT_UNUSED_ENTRY(69), 703 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 704 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 705 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 706 707 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 708 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 709 710 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 711 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 712 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 713 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 714 I40E_PTT_UNUSED_ENTRY(77), 715 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 716 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 717 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 718 719 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 720 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 721 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 722 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 723 I40E_PTT_UNUSED_ENTRY(84), 724 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 725 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 726 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 727 728 /* Non Tunneled IPv6 */ 729 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 730 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 731 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 732 I40E_PTT_UNUSED_ENTRY(91), 733 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 734 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 735 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 736 737 /* IPv6 --> IPv4 */ 738 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 739 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 740 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 741 I40E_PTT_UNUSED_ENTRY(98), 742 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 743 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 744 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 745 746 /* IPv6 --> IPv6 */ 747 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 748 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 749 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 750 I40E_PTT_UNUSED_ENTRY(105), 751 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 752 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 753 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 754 755 /* IPv6 --> GRE/NAT */ 756 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 757 758 /* IPv6 --> GRE/NAT -> IPv4 */ 759 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 760 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 761 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 762 I40E_PTT_UNUSED_ENTRY(113), 763 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 764 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 765 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 766 767 /* IPv6 --> GRE/NAT -> IPv6 */ 768 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 769 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 770 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 771 I40E_PTT_UNUSED_ENTRY(120), 772 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 773 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 774 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 775 776 /* IPv6 --> GRE/NAT -> MAC */ 777 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 778 779 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 780 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 781 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 782 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 783 I40E_PTT_UNUSED_ENTRY(128), 784 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 785 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 786 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 787 788 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 789 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 790 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 791 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 792 I40E_PTT_UNUSED_ENTRY(135), 793 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 794 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 795 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 796 797 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 798 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 799 800 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 801 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 802 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 803 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 804 I40E_PTT_UNUSED_ENTRY(143), 805 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 806 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 807 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 808 809 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 810 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 811 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 812 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 813 I40E_PTT_UNUSED_ENTRY(150), 814 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 815 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 816 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 817 818 /* unused entries */ 819 I40E_PTT_UNUSED_ENTRY(154), 820 I40E_PTT_UNUSED_ENTRY(155), 821 I40E_PTT_UNUSED_ENTRY(156), 822 I40E_PTT_UNUSED_ENTRY(157), 823 I40E_PTT_UNUSED_ENTRY(158), 824 I40E_PTT_UNUSED_ENTRY(159), 825 826 I40E_PTT_UNUSED_ENTRY(160), 827 I40E_PTT_UNUSED_ENTRY(161), 828 I40E_PTT_UNUSED_ENTRY(162), 829 I40E_PTT_UNUSED_ENTRY(163), 830 I40E_PTT_UNUSED_ENTRY(164), 831 I40E_PTT_UNUSED_ENTRY(165), 832 I40E_PTT_UNUSED_ENTRY(166), 833 I40E_PTT_UNUSED_ENTRY(167), 834 I40E_PTT_UNUSED_ENTRY(168), 835 I40E_PTT_UNUSED_ENTRY(169), 836 837 I40E_PTT_UNUSED_ENTRY(170), 838 I40E_PTT_UNUSED_ENTRY(171), 839 I40E_PTT_UNUSED_ENTRY(172), 840 I40E_PTT_UNUSED_ENTRY(173), 841 I40E_PTT_UNUSED_ENTRY(174), 842 I40E_PTT_UNUSED_ENTRY(175), 843 I40E_PTT_UNUSED_ENTRY(176), 844 I40E_PTT_UNUSED_ENTRY(177), 845 I40E_PTT_UNUSED_ENTRY(178), 846 I40E_PTT_UNUSED_ENTRY(179), 847 848 I40E_PTT_UNUSED_ENTRY(180), 849 I40E_PTT_UNUSED_ENTRY(181), 850 I40E_PTT_UNUSED_ENTRY(182), 851 I40E_PTT_UNUSED_ENTRY(183), 852 I40E_PTT_UNUSED_ENTRY(184), 853 I40E_PTT_UNUSED_ENTRY(185), 854 I40E_PTT_UNUSED_ENTRY(186), 855 I40E_PTT_UNUSED_ENTRY(187), 856 I40E_PTT_UNUSED_ENTRY(188), 857 I40E_PTT_UNUSED_ENTRY(189), 858 859 I40E_PTT_UNUSED_ENTRY(190), 860 I40E_PTT_UNUSED_ENTRY(191), 861 I40E_PTT_UNUSED_ENTRY(192), 862 I40E_PTT_UNUSED_ENTRY(193), 863 I40E_PTT_UNUSED_ENTRY(194), 864 I40E_PTT_UNUSED_ENTRY(195), 865 I40E_PTT_UNUSED_ENTRY(196), 866 I40E_PTT_UNUSED_ENTRY(197), 867 I40E_PTT_UNUSED_ENTRY(198), 868 I40E_PTT_UNUSED_ENTRY(199), 869 870 I40E_PTT_UNUSED_ENTRY(200), 871 I40E_PTT_UNUSED_ENTRY(201), 872 I40E_PTT_UNUSED_ENTRY(202), 873 I40E_PTT_UNUSED_ENTRY(203), 874 I40E_PTT_UNUSED_ENTRY(204), 875 I40E_PTT_UNUSED_ENTRY(205), 876 I40E_PTT_UNUSED_ENTRY(206), 877 I40E_PTT_UNUSED_ENTRY(207), 878 I40E_PTT_UNUSED_ENTRY(208), 879 I40E_PTT_UNUSED_ENTRY(209), 880 881 I40E_PTT_UNUSED_ENTRY(210), 882 I40E_PTT_UNUSED_ENTRY(211), 883 I40E_PTT_UNUSED_ENTRY(212), 884 I40E_PTT_UNUSED_ENTRY(213), 885 I40E_PTT_UNUSED_ENTRY(214), 886 I40E_PTT_UNUSED_ENTRY(215), 887 I40E_PTT_UNUSED_ENTRY(216), 888 I40E_PTT_UNUSED_ENTRY(217), 889 I40E_PTT_UNUSED_ENTRY(218), 890 I40E_PTT_UNUSED_ENTRY(219), 891 892 I40E_PTT_UNUSED_ENTRY(220), 893 I40E_PTT_UNUSED_ENTRY(221), 894 I40E_PTT_UNUSED_ENTRY(222), 895 I40E_PTT_UNUSED_ENTRY(223), 896 I40E_PTT_UNUSED_ENTRY(224), 897 I40E_PTT_UNUSED_ENTRY(225), 898 I40E_PTT_UNUSED_ENTRY(226), 899 I40E_PTT_UNUSED_ENTRY(227), 900 I40E_PTT_UNUSED_ENTRY(228), 901 I40E_PTT_UNUSED_ENTRY(229), 902 903 I40E_PTT_UNUSED_ENTRY(230), 904 I40E_PTT_UNUSED_ENTRY(231), 905 I40E_PTT_UNUSED_ENTRY(232), 906 I40E_PTT_UNUSED_ENTRY(233), 907 I40E_PTT_UNUSED_ENTRY(234), 908 I40E_PTT_UNUSED_ENTRY(235), 909 I40E_PTT_UNUSED_ENTRY(236), 910 I40E_PTT_UNUSED_ENTRY(237), 911 I40E_PTT_UNUSED_ENTRY(238), 912 I40E_PTT_UNUSED_ENTRY(239), 913 914 I40E_PTT_UNUSED_ENTRY(240), 915 I40E_PTT_UNUSED_ENTRY(241), 916 I40E_PTT_UNUSED_ENTRY(242), 917 I40E_PTT_UNUSED_ENTRY(243), 918 I40E_PTT_UNUSED_ENTRY(244), 919 I40E_PTT_UNUSED_ENTRY(245), 920 I40E_PTT_UNUSED_ENTRY(246), 921 I40E_PTT_UNUSED_ENTRY(247), 922 I40E_PTT_UNUSED_ENTRY(248), 923 I40E_PTT_UNUSED_ENTRY(249), 924 925 I40E_PTT_UNUSED_ENTRY(250), 926 I40E_PTT_UNUSED_ENTRY(251), 927 I40E_PTT_UNUSED_ENTRY(252), 928 I40E_PTT_UNUSED_ENTRY(253), 929 I40E_PTT_UNUSED_ENTRY(254), 930 I40E_PTT_UNUSED_ENTRY(255) 931 }; 932 933 934 /** 935 * i40e_validate_mac_addr - Validate unicast MAC address 936 * @mac_addr: pointer to MAC address 937 * 938 * Tests a MAC address to ensure it is a valid Individual Address 939 **/ 940 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 941 { 942 enum i40e_status_code status = I40E_SUCCESS; 943 944 DEBUGFUNC("i40e_validate_mac_addr"); 945 946 /* Broadcast addresses ARE multicast addresses 947 * Make sure it is not a multicast address 948 * Reject the zero address 949 */ 950 if (I40E_IS_MULTICAST(mac_addr) || 951 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 952 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 953 status = I40E_ERR_INVALID_MAC_ADDR; 954 955 return status; 956 } 957 958 /** 959 * i40e_init_shared_code - Initialize the shared code 960 * @hw: pointer to hardware structure 961 * 962 * This assigns the MAC type and PHY code and inits the NVM. 963 * Does not touch the hardware. This function must be called prior to any 964 * other function in the shared code. The i40e_hw structure should be 965 * memset to 0 prior to calling this function. The following fields in 966 * hw structure should be filled in prior to calling this function: 967 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 968 * subsystem_vendor_id, and revision_id 969 **/ 970 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 971 { 972 enum i40e_status_code status = I40E_SUCCESS; 973 u32 port, ari, func_rid; 974 975 DEBUGFUNC("i40e_init_shared_code"); 976 977 i40e_set_mac_type(hw); 978 979 switch (hw->mac.type) { 980 case I40E_MAC_XL710: 981 case I40E_MAC_X722: 982 break; 983 default: 984 return I40E_ERR_DEVICE_NOT_SUPPORTED; 985 } 986 987 hw->phy.get_link_info = TRUE; 988 989 /* Determine port number and PF number*/ 990 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 991 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 992 hw->port = (u8)port; 993 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 994 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 995 func_rid = rd32(hw, I40E_PF_FUNC_RID); 996 if (ari) 997 hw->pf_id = (u8)(func_rid & 0xff); 998 else 999 hw->pf_id = (u8)(func_rid & 0x7); 1000 1001 if (hw->mac.type == I40E_MAC_X722) 1002 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | 1003 I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; 1004 1005 status = i40e_init_nvm(hw); 1006 return status; 1007 } 1008 1009 /** 1010 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1011 * @hw: pointer to the hw struct 1012 * @flags: a return indicator of what addresses were added to the addr store 1013 * @addrs: the requestor's mac addr store 1014 * @cmd_details: pointer to command details structure or NULL 1015 **/ 1016 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1017 u16 *flags, 1018 struct i40e_aqc_mac_address_read_data *addrs, 1019 struct i40e_asq_cmd_details *cmd_details) 1020 { 1021 struct i40e_aq_desc desc; 1022 struct i40e_aqc_mac_address_read *cmd_data = 1023 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1024 enum i40e_status_code status; 1025 1026 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1027 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1028 1029 status = i40e_asq_send_command(hw, &desc, addrs, 1030 sizeof(*addrs), cmd_details); 1031 *flags = LE16_TO_CPU(cmd_data->command_flags); 1032 1033 return status; 1034 } 1035 1036 /** 1037 * i40e_aq_mac_address_write - Change the MAC addresses 1038 * @hw: pointer to the hw struct 1039 * @flags: indicates which MAC to be written 1040 * @mac_addr: address to write 1041 * @cmd_details: pointer to command details structure or NULL 1042 **/ 1043 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1044 u16 flags, u8 *mac_addr, 1045 struct i40e_asq_cmd_details *cmd_details) 1046 { 1047 struct i40e_aq_desc desc; 1048 struct i40e_aqc_mac_address_write *cmd_data = 1049 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1050 enum i40e_status_code status; 1051 1052 i40e_fill_default_direct_cmd_desc(&desc, 1053 i40e_aqc_opc_mac_address_write); 1054 cmd_data->command_flags = CPU_TO_LE16(flags); 1055 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1056 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1057 ((u32)mac_addr[3] << 16) | 1058 ((u32)mac_addr[4] << 8) | 1059 mac_addr[5]); 1060 1061 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1062 1063 return status; 1064 } 1065 1066 /** 1067 * i40e_get_mac_addr - get MAC address 1068 * @hw: pointer to the HW structure 1069 * @mac_addr: pointer to MAC address 1070 * 1071 * Reads the adapter's MAC address from register 1072 **/ 1073 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1074 { 1075 struct i40e_aqc_mac_address_read_data addrs; 1076 enum i40e_status_code status; 1077 u16 flags = 0; 1078 1079 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1080 1081 if (flags & I40E_AQC_LAN_ADDR_VALID) 1082 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1083 I40E_NONDMA_TO_NONDMA); 1084 1085 return status; 1086 } 1087 1088 /** 1089 * i40e_get_port_mac_addr - get Port MAC address 1090 * @hw: pointer to the HW structure 1091 * @mac_addr: pointer to Port MAC address 1092 * 1093 * Reads the adapter's Port MAC address 1094 **/ 1095 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1096 { 1097 struct i40e_aqc_mac_address_read_data addrs; 1098 enum i40e_status_code status; 1099 u16 flags = 0; 1100 1101 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1102 if (status) 1103 return status; 1104 1105 if (flags & I40E_AQC_PORT_ADDR_VALID) 1106 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1107 I40E_NONDMA_TO_NONDMA); 1108 else 1109 status = I40E_ERR_INVALID_MAC_ADDR; 1110 1111 return status; 1112 } 1113 1114 /** 1115 * i40e_pre_tx_queue_cfg - pre tx queue configure 1116 * @hw: pointer to the HW structure 1117 * @queue: target pf queue index 1118 * @enable: state change request 1119 * 1120 * Handles hw requirement to indicate intention to enable 1121 * or disable target queue. 1122 **/ 1123 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1124 { 1125 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1126 u32 reg_block = 0; 1127 u32 reg_val; 1128 1129 if (abs_queue_idx >= 128) { 1130 reg_block = abs_queue_idx / 128; 1131 abs_queue_idx %= 128; 1132 } 1133 1134 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1135 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1136 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1137 1138 if (enable) 1139 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1140 else 1141 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1142 1143 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1144 } 1145 1146 /** 1147 * i40e_read_pba_string - Reads part number string from EEPROM 1148 * @hw: pointer to hardware structure 1149 * @pba_num: stores the part number string from the EEPROM 1150 * @pba_num_size: part number string buffer length 1151 * 1152 * Reads the part number string from the EEPROM. 1153 **/ 1154 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1155 u32 pba_num_size) 1156 { 1157 enum i40e_status_code status = I40E_SUCCESS; 1158 u16 pba_word = 0; 1159 u16 pba_size = 0; 1160 u16 pba_ptr = 0; 1161 u16 i = 0; 1162 1163 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1164 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1165 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1166 return status; 1167 } 1168 1169 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1170 if (status != I40E_SUCCESS) { 1171 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1172 return status; 1173 } 1174 1175 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1176 if (status != I40E_SUCCESS) { 1177 DEBUGOUT("Failed to read PBA Block size.\n"); 1178 return status; 1179 } 1180 1181 /* Subtract one to get PBA word count (PBA Size word is included in 1182 * total size) 1183 */ 1184 pba_size--; 1185 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1186 DEBUGOUT("Buffer to small for PBA data.\n"); 1187 return I40E_ERR_PARAM; 1188 } 1189 1190 for (i = 0; i < pba_size; i++) { 1191 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1192 if (status != I40E_SUCCESS) { 1193 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1194 return status; 1195 } 1196 1197 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1198 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1199 } 1200 pba_num[(pba_size * 2)] = '\0'; 1201 1202 return status; 1203 } 1204 1205 /** 1206 * i40e_get_media_type - Gets media type 1207 * @hw: pointer to the hardware structure 1208 **/ 1209 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1210 { 1211 enum i40e_media_type media; 1212 1213 switch (hw->phy.link_info.phy_type) { 1214 case I40E_PHY_TYPE_10GBASE_SR: 1215 case I40E_PHY_TYPE_10GBASE_LR: 1216 case I40E_PHY_TYPE_1000BASE_SX: 1217 case I40E_PHY_TYPE_1000BASE_LX: 1218 case I40E_PHY_TYPE_40GBASE_SR4: 1219 case I40E_PHY_TYPE_40GBASE_LR4: 1220 case I40E_PHY_TYPE_25GBASE_LR: 1221 case I40E_PHY_TYPE_25GBASE_SR: 1222 media = I40E_MEDIA_TYPE_FIBER; 1223 break; 1224 case I40E_PHY_TYPE_100BASE_TX: 1225 case I40E_PHY_TYPE_1000BASE_T: 1226 case I40E_PHY_TYPE_10GBASE_T: 1227 media = I40E_MEDIA_TYPE_BASET; 1228 break; 1229 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1230 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1231 case I40E_PHY_TYPE_10GBASE_CR1: 1232 case I40E_PHY_TYPE_40GBASE_CR4: 1233 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1234 case I40E_PHY_TYPE_40GBASE_AOC: 1235 case I40E_PHY_TYPE_10GBASE_AOC: 1236 case I40E_PHY_TYPE_25GBASE_CR: 1237 case I40E_PHY_TYPE_25GBASE_AOC: 1238 case I40E_PHY_TYPE_25GBASE_ACC: 1239 media = I40E_MEDIA_TYPE_DA; 1240 break; 1241 case I40E_PHY_TYPE_1000BASE_KX: 1242 case I40E_PHY_TYPE_10GBASE_KX4: 1243 case I40E_PHY_TYPE_10GBASE_KR: 1244 case I40E_PHY_TYPE_40GBASE_KR4: 1245 case I40E_PHY_TYPE_20GBASE_KR2: 1246 case I40E_PHY_TYPE_25GBASE_KR: 1247 media = I40E_MEDIA_TYPE_BACKPLANE; 1248 break; 1249 case I40E_PHY_TYPE_SGMII: 1250 case I40E_PHY_TYPE_XAUI: 1251 case I40E_PHY_TYPE_XFI: 1252 case I40E_PHY_TYPE_XLAUI: 1253 case I40E_PHY_TYPE_XLPPI: 1254 default: 1255 media = I40E_MEDIA_TYPE_UNKNOWN; 1256 break; 1257 } 1258 1259 return media; 1260 } 1261 1262 #define I40E_PF_RESET_WAIT_COUNT 200 1263 /** 1264 * i40e_pf_reset - Reset the PF 1265 * @hw: pointer to the hardware structure 1266 * 1267 * Assuming someone else has triggered a global reset, 1268 * assure the global reset is complete and then reset the PF 1269 **/ 1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1271 { 1272 u32 cnt = 0; 1273 u32 cnt1 = 0; 1274 u32 reg = 0; 1275 u32 grst_del; 1276 1277 /* Poll for Global Reset steady state in case of recent GRST. 1278 * The grst delay value is in 100ms units, and we'll wait a 1279 * couple counts longer to be sure we don't just miss the end. 1280 */ 1281 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1282 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1283 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1284 1285 grst_del = grst_del * 20; 1286 1287 for (cnt = 0; cnt < grst_del; cnt++) { 1288 reg = rd32(hw, I40E_GLGEN_RSTAT); 1289 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1290 break; 1291 i40e_msec_delay(100); 1292 } 1293 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1294 DEBUGOUT("Global reset polling failed to complete.\n"); 1295 return I40E_ERR_RESET_FAILED; 1296 } 1297 1298 /* Now Wait for the FW to be ready */ 1299 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1300 reg = rd32(hw, I40E_GLNVM_ULD); 1301 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1302 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1303 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1304 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1305 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1306 break; 1307 } 1308 i40e_msec_delay(10); 1309 } 1310 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1311 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1312 DEBUGOUT("wait for FW Reset complete timedout\n"); 1313 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1314 return I40E_ERR_RESET_FAILED; 1315 } 1316 1317 /* If there was a Global Reset in progress when we got here, 1318 * we don't need to do the PF Reset 1319 */ 1320 if (!cnt) { 1321 u32 reg2 = 0; 1322 1323 reg = rd32(hw, I40E_PFGEN_CTRL); 1324 wr32(hw, I40E_PFGEN_CTRL, 1325 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1326 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1327 reg = rd32(hw, I40E_PFGEN_CTRL); 1328 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1329 break; 1330 reg2 = rd32(hw, I40E_GLGEN_RSTAT); 1331 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1332 DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n"); 1333 DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2); 1334 return I40E_ERR_NOT_READY; 1335 } 1336 i40e_msec_delay(1); 1337 } 1338 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1339 DEBUGOUT("PF reset polling failed to complete.\n"); 1340 return I40E_ERR_RESET_FAILED; 1341 } 1342 } 1343 1344 i40e_clear_pxe_mode(hw); 1345 1346 1347 return I40E_SUCCESS; 1348 } 1349 1350 /** 1351 * i40e_clear_hw - clear out any left over hw state 1352 * @hw: pointer to the hw struct 1353 * 1354 * Clear queues and interrupts, typically called at init time, 1355 * but after the capabilities have been found so we know how many 1356 * queues and msix vectors have been allocated. 1357 **/ 1358 void i40e_clear_hw(struct i40e_hw *hw) 1359 { 1360 u32 num_queues, base_queue; 1361 u32 num_pf_int; 1362 u32 num_vf_int; 1363 u32 num_vfs; 1364 u32 i, j; 1365 u32 val; 1366 u32 eol = 0x7ff; 1367 1368 /* get number of interrupts, queues, and vfs */ 1369 val = rd32(hw, I40E_GLPCI_CNF2); 1370 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1371 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1372 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1373 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1374 1375 val = rd32(hw, I40E_PFLAN_QALLOC); 1376 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1377 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1378 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1379 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1380 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1381 num_queues = (j - base_queue) + 1; 1382 else 1383 num_queues = 0; 1384 1385 val = rd32(hw, I40E_PF_VT_PFALLOC); 1386 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1387 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1388 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1389 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1390 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1391 num_vfs = (j - i) + 1; 1392 else 1393 num_vfs = 0; 1394 1395 /* stop all the interrupts */ 1396 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1397 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1398 for (i = 0; i < num_pf_int - 2; i++) 1399 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1400 1401 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1402 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1403 wr32(hw, I40E_PFINT_LNKLST0, val); 1404 for (i = 0; i < num_pf_int - 2; i++) 1405 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1406 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1407 for (i = 0; i < num_vfs; i++) 1408 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1409 for (i = 0; i < num_vf_int - 2; i++) 1410 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1411 1412 /* warn the HW of the coming Tx disables */ 1413 for (i = 0; i < num_queues; i++) { 1414 u32 abs_queue_idx = base_queue + i; 1415 u32 reg_block = 0; 1416 1417 if (abs_queue_idx >= 128) { 1418 reg_block = abs_queue_idx / 128; 1419 abs_queue_idx %= 128; 1420 } 1421 1422 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1423 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1424 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1425 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1426 1427 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1428 } 1429 i40e_usec_delay(400); 1430 1431 /* stop all the queues */ 1432 for (i = 0; i < num_queues; i++) { 1433 wr32(hw, I40E_QINT_TQCTL(i), 0); 1434 wr32(hw, I40E_QTX_ENA(i), 0); 1435 wr32(hw, I40E_QINT_RQCTL(i), 0); 1436 wr32(hw, I40E_QRX_ENA(i), 0); 1437 } 1438 1439 /* short wait for all queue disables to settle */ 1440 i40e_usec_delay(50); 1441 } 1442 1443 /** 1444 * i40e_clear_pxe_mode - clear pxe operations mode 1445 * @hw: pointer to the hw struct 1446 * 1447 * Make sure all PXE mode settings are cleared, including things 1448 * like descriptor fetch/write-back mode. 1449 **/ 1450 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1451 { 1452 if (i40e_check_asq_alive(hw)) 1453 i40e_aq_clear_pxe_mode(hw, NULL); 1454 } 1455 1456 /** 1457 * i40e_led_is_mine - helper to find matching led 1458 * @hw: pointer to the hw struct 1459 * @idx: index into GPIO registers 1460 * 1461 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1462 */ 1463 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1464 { 1465 u32 gpio_val = 0; 1466 u32 port; 1467 1468 if (!hw->func_caps.led[idx]) 1469 return 0; 1470 1471 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1472 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1473 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1474 1475 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1476 * if it is not our port then ignore 1477 */ 1478 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1479 (port != hw->port)) 1480 return 0; 1481 1482 return gpio_val; 1483 } 1484 1485 #define I40E_COMBINED_ACTIVITY 0xA 1486 #define I40E_FILTER_ACTIVITY 0xE 1487 #define I40E_LINK_ACTIVITY 0xC 1488 #define I40E_MAC_ACTIVITY 0xD 1489 #define I40E_LED0 22 1490 1491 /** 1492 * i40e_led_get - return current on/off mode 1493 * @hw: pointer to the hw struct 1494 * 1495 * The value returned is the 'mode' field as defined in the 1496 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1497 * values are variations of possible behaviors relating to 1498 * blink, link, and wire. 1499 **/ 1500 u32 i40e_led_get(struct i40e_hw *hw) 1501 { 1502 u32 current_mode = 0; 1503 u32 mode = 0; 1504 int i; 1505 1506 /* as per the documentation GPIO 22-29 are the LED 1507 * GPIO pins named LED0..LED7 1508 */ 1509 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1510 u32 gpio_val = i40e_led_is_mine(hw, i); 1511 1512 if (!gpio_val) 1513 continue; 1514 1515 /* ignore gpio LED src mode entries related to the activity 1516 * LEDs 1517 */ 1518 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1519 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1520 switch (current_mode) { 1521 case I40E_COMBINED_ACTIVITY: 1522 case I40E_FILTER_ACTIVITY: 1523 case I40E_MAC_ACTIVITY: 1524 case I40E_LINK_ACTIVITY: 1525 continue; 1526 default: 1527 break; 1528 } 1529 1530 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1531 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1532 break; 1533 } 1534 1535 return mode; 1536 } 1537 1538 /** 1539 * i40e_led_set - set new on/off mode 1540 * @hw: pointer to the hw struct 1541 * @mode: 0=off, 0xf=on (else see manual for mode details) 1542 * @blink: TRUE if the LED should blink when on, FALSE if steady 1543 * 1544 * if this function is used to turn on the blink it should 1545 * be used to disable the blink when restoring the original state. 1546 **/ 1547 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1548 { 1549 u32 current_mode = 0; 1550 int i; 1551 1552 if (mode & 0xfffffff0) 1553 DEBUGOUT1("invalid mode passed in %X\n", mode); 1554 1555 /* as per the documentation GPIO 22-29 are the LED 1556 * GPIO pins named LED0..LED7 1557 */ 1558 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1559 u32 gpio_val = i40e_led_is_mine(hw, i); 1560 1561 if (!gpio_val) 1562 continue; 1563 1564 /* ignore gpio LED src mode entries related to the activity 1565 * LEDs 1566 */ 1567 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1568 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1569 switch (current_mode) { 1570 case I40E_COMBINED_ACTIVITY: 1571 case I40E_FILTER_ACTIVITY: 1572 case I40E_MAC_ACTIVITY: 1573 case I40E_LINK_ACTIVITY: 1574 continue; 1575 default: 1576 break; 1577 } 1578 1579 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1580 /* this & is a bit of paranoia, but serves as a range check */ 1581 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1582 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1583 1584 if (blink) 1585 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1586 else 1587 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1588 1589 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1590 break; 1591 } 1592 } 1593 1594 /* Admin command wrappers */ 1595 1596 /** 1597 * i40e_aq_get_phy_capabilities 1598 * @hw: pointer to the hw struct 1599 * @abilities: structure for PHY capabilities to be filled 1600 * @qualified_modules: report Qualified Modules 1601 * @report_init: report init capabilities (active are default) 1602 * @cmd_details: pointer to command details structure or NULL 1603 * 1604 * Returns the various PHY abilities supported on the Port. 1605 **/ 1606 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1607 bool qualified_modules, bool report_init, 1608 struct i40e_aq_get_phy_abilities_resp *abilities, 1609 struct i40e_asq_cmd_details *cmd_details) 1610 { 1611 struct i40e_aq_desc desc; 1612 enum i40e_status_code status; 1613 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0; 1614 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1615 1616 if (!abilities) 1617 return I40E_ERR_PARAM; 1618 1619 do { 1620 i40e_fill_default_direct_cmd_desc(&desc, 1621 i40e_aqc_opc_get_phy_abilities); 1622 1623 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1624 if (abilities_size > I40E_AQ_LARGE_BUF) 1625 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1626 1627 if (qualified_modules) 1628 desc.params.external.param0 |= 1629 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1630 1631 if (report_init) 1632 desc.params.external.param0 |= 1633 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1634 1635 status = i40e_asq_send_command(hw, &desc, abilities, 1636 abilities_size, cmd_details); 1637 1638 if (status != I40E_SUCCESS) 1639 break; 1640 1641 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) { 1642 status = I40E_ERR_UNKNOWN_PHY; 1643 break; 1644 } else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) { 1645 i40e_msec_delay(1); 1646 total_delay++; 1647 status = I40E_ERR_TIMEOUT; 1648 } 1649 } while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) && 1650 (total_delay < max_delay)); 1651 1652 if (status != I40E_SUCCESS) 1653 return status; 1654 1655 if (report_init) { 1656 if (hw->mac.type == I40E_MAC_XL710 && 1657 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1658 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) { 1659 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 1660 } else { 1661 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1662 hw->phy.phy_types |= 1663 ((u64)abilities->phy_type_ext << 32); 1664 } 1665 } 1666 1667 return status; 1668 } 1669 1670 /** 1671 * i40e_aq_set_phy_config 1672 * @hw: pointer to the hw struct 1673 * @config: structure with PHY configuration to be set 1674 * @cmd_details: pointer to command details structure or NULL 1675 * 1676 * Set the various PHY configuration parameters 1677 * supported on the Port.One or more of the Set PHY config parameters may be 1678 * ignored in an MFP mode as the PF may not have the privilege to set some 1679 * of the PHY Config parameters. This status will be indicated by the 1680 * command response. 1681 **/ 1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1683 struct i40e_aq_set_phy_config *config, 1684 struct i40e_asq_cmd_details *cmd_details) 1685 { 1686 struct i40e_aq_desc desc; 1687 struct i40e_aq_set_phy_config *cmd = 1688 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1689 enum i40e_status_code status; 1690 1691 if (!config) 1692 return I40E_ERR_PARAM; 1693 1694 i40e_fill_default_direct_cmd_desc(&desc, 1695 i40e_aqc_opc_set_phy_config); 1696 1697 *cmd = *config; 1698 1699 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1700 1701 return status; 1702 } 1703 1704 /** 1705 * i40e_set_fc 1706 * @hw: pointer to the hw struct 1707 * @aq_failures: buffer to return AdminQ failure information 1708 * @atomic_restart: whether to enable atomic link restart 1709 * 1710 * Set the requested flow control mode using set_phy_config. 1711 **/ 1712 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1713 bool atomic_restart) 1714 { 1715 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1716 struct i40e_aq_get_phy_abilities_resp abilities; 1717 struct i40e_aq_set_phy_config config; 1718 enum i40e_status_code status; 1719 u8 pause_mask = 0x0; 1720 1721 *aq_failures = 0x0; 1722 1723 switch (fc_mode) { 1724 case I40E_FC_FULL: 1725 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1726 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1727 break; 1728 case I40E_FC_RX_PAUSE: 1729 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1730 break; 1731 case I40E_FC_TX_PAUSE: 1732 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1733 break; 1734 default: 1735 break; 1736 } 1737 1738 /* Get the current phy config */ 1739 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1740 NULL); 1741 if (status) { 1742 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1743 return status; 1744 } 1745 1746 memset(&config, 0, sizeof(config)); 1747 /* clear the old pause settings */ 1748 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1749 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1750 /* set the new abilities */ 1751 config.abilities |= pause_mask; 1752 /* If the abilities have changed, then set the new config */ 1753 if (config.abilities != abilities.abilities) { 1754 /* Auto restart link so settings take effect */ 1755 if (atomic_restart) 1756 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1757 /* Copy over all the old settings */ 1758 config.phy_type = abilities.phy_type; 1759 config.phy_type_ext = abilities.phy_type_ext; 1760 config.link_speed = abilities.link_speed; 1761 config.eee_capability = abilities.eee_capability; 1762 config.eeer = abilities.eeer_val; 1763 config.low_power_ctrl = abilities.d3_lpan; 1764 status = i40e_aq_set_phy_config(hw, &config, NULL); 1765 1766 if (status) 1767 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1768 } 1769 /* Update the link info */ 1770 status = i40e_update_link_info(hw); 1771 if (status) { 1772 /* Wait a little bit (on 40G cards it sometimes takes a really 1773 * long time for link to come back from the atomic reset) 1774 * and try once more 1775 */ 1776 i40e_msec_delay(1000); 1777 status = i40e_update_link_info(hw); 1778 } 1779 if (status) 1780 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1781 1782 return status; 1783 } 1784 1785 /** 1786 * i40e_aq_set_mac_config 1787 * @hw: pointer to the hw struct 1788 * @max_frame_size: Maximum Frame Size to be supported by the port 1789 * @crc_en: Tell HW to append a CRC to outgoing frames 1790 * @pacing: Pacing configurations 1791 * @cmd_details: pointer to command details structure or NULL 1792 * 1793 * Configure MAC settings for frame size, jumbo frame support and the 1794 * addition of a CRC by the hardware. 1795 **/ 1796 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1797 u16 max_frame_size, 1798 bool crc_en, u16 pacing, 1799 struct i40e_asq_cmd_details *cmd_details) 1800 { 1801 struct i40e_aq_desc desc; 1802 struct i40e_aq_set_mac_config *cmd = 1803 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1804 enum i40e_status_code status; 1805 1806 if (max_frame_size == 0) 1807 return I40E_ERR_PARAM; 1808 1809 i40e_fill_default_direct_cmd_desc(&desc, 1810 i40e_aqc_opc_set_mac_config); 1811 1812 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1813 cmd->params = ((u8)pacing & 0x0F) << 3; 1814 if (crc_en) 1815 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1816 1817 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1818 1819 return status; 1820 } 1821 1822 /** 1823 * i40e_aq_clear_pxe_mode 1824 * @hw: pointer to the hw struct 1825 * @cmd_details: pointer to command details structure or NULL 1826 * 1827 * Tell the firmware that the driver is taking over from PXE 1828 **/ 1829 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1830 struct i40e_asq_cmd_details *cmd_details) 1831 { 1832 enum i40e_status_code status; 1833 struct i40e_aq_desc desc; 1834 struct i40e_aqc_clear_pxe *cmd = 1835 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1836 1837 i40e_fill_default_direct_cmd_desc(&desc, 1838 i40e_aqc_opc_clear_pxe_mode); 1839 1840 cmd->rx_cnt = 0x2; 1841 1842 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1843 1844 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1845 1846 return status; 1847 } 1848 1849 /** 1850 * i40e_aq_set_link_restart_an 1851 * @hw: pointer to the hw struct 1852 * @enable_link: if TRUE: enable link, if FALSE: disable link 1853 * @cmd_details: pointer to command details structure or NULL 1854 * 1855 * Sets up the link and restarts the Auto-Negotiation over the link. 1856 **/ 1857 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1858 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1859 { 1860 struct i40e_aq_desc desc; 1861 struct i40e_aqc_set_link_restart_an *cmd = 1862 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1863 enum i40e_status_code status; 1864 1865 i40e_fill_default_direct_cmd_desc(&desc, 1866 i40e_aqc_opc_set_link_restart_an); 1867 1868 cmd->command = I40E_AQ_PHY_RESTART_AN; 1869 if (enable_link) 1870 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1871 else 1872 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1873 1874 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1875 1876 return status; 1877 } 1878 1879 /** 1880 * i40e_aq_get_link_info 1881 * @hw: pointer to the hw struct 1882 * @enable_lse: enable/disable LinkStatusEvent reporting 1883 * @link: pointer to link status structure - optional 1884 * @cmd_details: pointer to command details structure or NULL 1885 * 1886 * Returns the link status of the adapter. 1887 **/ 1888 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1889 bool enable_lse, struct i40e_link_status *link, 1890 struct i40e_asq_cmd_details *cmd_details) 1891 { 1892 struct i40e_aq_desc desc; 1893 struct i40e_aqc_get_link_status *resp = 1894 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1895 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1896 enum i40e_status_code status; 1897 bool tx_pause, rx_pause; 1898 u16 command_flags; 1899 1900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1901 1902 if (enable_lse) 1903 command_flags = I40E_AQ_LSE_ENABLE; 1904 else 1905 command_flags = I40E_AQ_LSE_DISABLE; 1906 resp->command_flags = CPU_TO_LE16(command_flags); 1907 1908 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1909 1910 if (status != I40E_SUCCESS) 1911 goto aq_get_link_info_exit; 1912 1913 /* save off old link status information */ 1914 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1915 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1916 1917 /* update link status */ 1918 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1919 hw->phy.media_type = i40e_get_media_type(hw); 1920 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1921 hw_link_info->link_info = resp->link_info; 1922 hw_link_info->an_info = resp->an_info; 1923 hw_link_info->ext_info = resp->ext_info; 1924 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK; 1925 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1926 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1927 1928 /* update fc info */ 1929 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1930 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1931 if (tx_pause & rx_pause) 1932 hw->fc.current_mode = I40E_FC_FULL; 1933 else if (tx_pause) 1934 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1935 else if (rx_pause) 1936 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1937 else 1938 hw->fc.current_mode = I40E_FC_NONE; 1939 1940 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1941 hw_link_info->crc_enable = TRUE; 1942 else 1943 hw_link_info->crc_enable = FALSE; 1944 1945 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1946 hw_link_info->lse_enable = TRUE; 1947 else 1948 hw_link_info->lse_enable = FALSE; 1949 1950 if ((hw->mac.type == I40E_MAC_XL710) && 1951 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1952 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1953 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1954 1955 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && 1956 hw->aq.api_min_ver >= 7) { 1957 __le32 tmp; 1958 1959 i40e_memcpy(&tmp, resp->link_type, sizeof(tmp), 1960 I40E_NONDMA_TO_NONDMA); 1961 hw->phy.phy_types = LE32_TO_CPU(tmp); 1962 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32); 1963 } 1964 1965 /* save link status information */ 1966 if (link) 1967 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1968 I40E_NONDMA_TO_NONDMA); 1969 1970 /* flag cleared so helper functions don't call AQ again */ 1971 hw->phy.get_link_info = FALSE; 1972 1973 aq_get_link_info_exit: 1974 return status; 1975 } 1976 1977 /** 1978 * i40e_aq_set_phy_int_mask 1979 * @hw: pointer to the hw struct 1980 * @mask: interrupt mask to be set 1981 * @cmd_details: pointer to command details structure or NULL 1982 * 1983 * Set link interrupt mask. 1984 **/ 1985 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1986 u16 mask, 1987 struct i40e_asq_cmd_details *cmd_details) 1988 { 1989 struct i40e_aq_desc desc; 1990 struct i40e_aqc_set_phy_int_mask *cmd = 1991 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1992 enum i40e_status_code status; 1993 1994 i40e_fill_default_direct_cmd_desc(&desc, 1995 i40e_aqc_opc_set_phy_int_mask); 1996 1997 cmd->event_mask = CPU_TO_LE16(mask); 1998 1999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2000 2001 return status; 2002 } 2003 2004 /** 2005 * i40e_aq_get_local_advt_reg 2006 * @hw: pointer to the hw struct 2007 * @advt_reg: local AN advertisement register value 2008 * @cmd_details: pointer to command details structure or NULL 2009 * 2010 * Get the Local AN advertisement register value. 2011 **/ 2012 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 2013 u64 *advt_reg, 2014 struct i40e_asq_cmd_details *cmd_details) 2015 { 2016 struct i40e_aq_desc desc; 2017 struct i40e_aqc_an_advt_reg *resp = 2018 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2019 enum i40e_status_code status; 2020 2021 i40e_fill_default_direct_cmd_desc(&desc, 2022 i40e_aqc_opc_get_local_advt_reg); 2023 2024 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2025 2026 if (status != I40E_SUCCESS) 2027 goto aq_get_local_advt_reg_exit; 2028 2029 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2030 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2031 2032 aq_get_local_advt_reg_exit: 2033 return status; 2034 } 2035 2036 /** 2037 * i40e_aq_set_local_advt_reg 2038 * @hw: pointer to the hw struct 2039 * @advt_reg: local AN advertisement register value 2040 * @cmd_details: pointer to command details structure or NULL 2041 * 2042 * Get the Local AN advertisement register value. 2043 **/ 2044 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 2045 u64 advt_reg, 2046 struct i40e_asq_cmd_details *cmd_details) 2047 { 2048 struct i40e_aq_desc desc; 2049 struct i40e_aqc_an_advt_reg *cmd = 2050 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2051 enum i40e_status_code status; 2052 2053 i40e_fill_default_direct_cmd_desc(&desc, 2054 i40e_aqc_opc_get_local_advt_reg); 2055 2056 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2057 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2058 2059 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2060 2061 return status; 2062 } 2063 2064 /** 2065 * i40e_aq_get_partner_advt 2066 * @hw: pointer to the hw struct 2067 * @advt_reg: AN partner advertisement register value 2068 * @cmd_details: pointer to command details structure or NULL 2069 * 2070 * Get the link partner AN advertisement register value. 2071 **/ 2072 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2073 u64 *advt_reg, 2074 struct i40e_asq_cmd_details *cmd_details) 2075 { 2076 struct i40e_aq_desc desc; 2077 struct i40e_aqc_an_advt_reg *resp = 2078 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2079 enum i40e_status_code status; 2080 2081 i40e_fill_default_direct_cmd_desc(&desc, 2082 i40e_aqc_opc_get_partner_advt); 2083 2084 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2085 2086 if (status != I40E_SUCCESS) 2087 goto aq_get_partner_advt_exit; 2088 2089 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2090 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2091 2092 aq_get_partner_advt_exit: 2093 return status; 2094 } 2095 2096 /** 2097 * i40e_aq_set_lb_modes 2098 * @hw: pointer to the hw struct 2099 * @lb_modes: loopback mode to be set 2100 * @cmd_details: pointer to command details structure or NULL 2101 * 2102 * Sets loopback modes. 2103 **/ 2104 enum i40e_status_code 2105 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed, 2106 struct i40e_asq_cmd_details *cmd_details) 2107 { 2108 struct i40e_aq_desc desc; 2109 struct i40e_aqc_set_lb_mode *cmd = 2110 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2111 enum i40e_status_code status; 2112 2113 i40e_fill_default_direct_cmd_desc(&desc, 2114 i40e_aqc_opc_set_lb_modes); 2115 2116 cmd->lb_level = lb_level; 2117 cmd->lb_type = lb_type; 2118 cmd->speed = speed; 2119 if (speed) 2120 cmd->force_speed = 1; 2121 2122 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2123 2124 return status; 2125 } 2126 2127 /** 2128 * i40e_aq_set_phy_debug 2129 * @hw: pointer to the hw struct 2130 * @cmd_flags: debug command flags 2131 * @cmd_details: pointer to command details structure or NULL 2132 * 2133 * Reset the external PHY. 2134 **/ 2135 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2136 struct i40e_asq_cmd_details *cmd_details) 2137 { 2138 struct i40e_aq_desc desc; 2139 struct i40e_aqc_set_phy_debug *cmd = 2140 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2141 enum i40e_status_code status; 2142 2143 i40e_fill_default_direct_cmd_desc(&desc, 2144 i40e_aqc_opc_set_phy_debug); 2145 2146 cmd->command_flags = cmd_flags; 2147 2148 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2149 2150 return status; 2151 } 2152 2153 /** 2154 * i40e_aq_add_vsi 2155 * @hw: pointer to the hw struct 2156 * @vsi_ctx: pointer to a vsi context struct 2157 * @cmd_details: pointer to command details structure or NULL 2158 * 2159 * Add a VSI context to the hardware. 2160 **/ 2161 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2162 struct i40e_vsi_context *vsi_ctx, 2163 struct i40e_asq_cmd_details *cmd_details) 2164 { 2165 struct i40e_aq_desc desc; 2166 struct i40e_aqc_add_get_update_vsi *cmd = 2167 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2168 struct i40e_aqc_add_get_update_vsi_completion *resp = 2169 (struct i40e_aqc_add_get_update_vsi_completion *) 2170 &desc.params.raw; 2171 enum i40e_status_code status; 2172 2173 i40e_fill_default_direct_cmd_desc(&desc, 2174 i40e_aqc_opc_add_vsi); 2175 2176 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2177 cmd->connection_type = vsi_ctx->connection_type; 2178 cmd->vf_id = vsi_ctx->vf_num; 2179 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2180 2181 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2182 2183 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2184 sizeof(vsi_ctx->info), cmd_details); 2185 2186 if (status != I40E_SUCCESS) 2187 goto aq_add_vsi_exit; 2188 2189 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2190 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2191 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2192 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2193 2194 aq_add_vsi_exit: 2195 return status; 2196 } 2197 2198 /** 2199 * i40e_aq_set_default_vsi 2200 * @hw: pointer to the hw struct 2201 * @seid: vsi number 2202 * @cmd_details: pointer to command details structure or NULL 2203 **/ 2204 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2205 u16 seid, 2206 struct i40e_asq_cmd_details *cmd_details) 2207 { 2208 struct i40e_aq_desc desc; 2209 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2210 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2211 &desc.params.raw; 2212 enum i40e_status_code status; 2213 2214 i40e_fill_default_direct_cmd_desc(&desc, 2215 i40e_aqc_opc_set_vsi_promiscuous_modes); 2216 2217 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2218 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2219 cmd->seid = CPU_TO_LE16(seid); 2220 2221 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2222 2223 return status; 2224 } 2225 2226 /** 2227 * i40e_aq_clear_default_vsi 2228 * @hw: pointer to the hw struct 2229 * @seid: vsi number 2230 * @cmd_details: pointer to command details structure or NULL 2231 **/ 2232 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2233 u16 seid, 2234 struct i40e_asq_cmd_details *cmd_details) 2235 { 2236 struct i40e_aq_desc desc; 2237 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2238 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2239 &desc.params.raw; 2240 enum i40e_status_code status; 2241 2242 i40e_fill_default_direct_cmd_desc(&desc, 2243 i40e_aqc_opc_set_vsi_promiscuous_modes); 2244 2245 cmd->promiscuous_flags = CPU_TO_LE16(0); 2246 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2247 cmd->seid = CPU_TO_LE16(seid); 2248 2249 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2250 2251 return status; 2252 } 2253 2254 /** 2255 * i40e_aq_set_vsi_unicast_promiscuous 2256 * @hw: pointer to the hw struct 2257 * @seid: vsi number 2258 * @set: set unicast promiscuous enable/disable 2259 * @cmd_details: pointer to command details structure or NULL 2260 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2261 **/ 2262 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2263 u16 seid, bool set, 2264 struct i40e_asq_cmd_details *cmd_details, 2265 bool rx_only_promisc) 2266 { 2267 struct i40e_aq_desc desc; 2268 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2269 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2270 enum i40e_status_code status; 2271 u16 flags = 0; 2272 2273 i40e_fill_default_direct_cmd_desc(&desc, 2274 i40e_aqc_opc_set_vsi_promiscuous_modes); 2275 2276 if (set) { 2277 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2278 if (rx_only_promisc && 2279 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2280 (hw->aq.api_maj_ver > 1))) 2281 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2282 } 2283 2284 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2285 2286 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2287 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2288 (hw->aq.api_maj_ver > 1)) 2289 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2290 2291 cmd->seid = CPU_TO_LE16(seid); 2292 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2293 2294 return status; 2295 } 2296 2297 /** 2298 * i40e_aq_set_vsi_multicast_promiscuous 2299 * @hw: pointer to the hw struct 2300 * @seid: vsi number 2301 * @set: set multicast promiscuous enable/disable 2302 * @cmd_details: pointer to command details structure or NULL 2303 **/ 2304 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2305 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2306 { 2307 struct i40e_aq_desc desc; 2308 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2309 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2310 enum i40e_status_code status; 2311 u16 flags = 0; 2312 2313 i40e_fill_default_direct_cmd_desc(&desc, 2314 i40e_aqc_opc_set_vsi_promiscuous_modes); 2315 2316 if (set) 2317 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2318 2319 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2320 2321 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2322 2323 cmd->seid = CPU_TO_LE16(seid); 2324 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2325 2326 return status; 2327 } 2328 2329 /** 2330 * i40e_aq_set_vsi_mc_promisc_on_vlan 2331 * @hw: pointer to the hw struct 2332 * @seid: vsi number 2333 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2334 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2335 * @cmd_details: pointer to command details structure or NULL 2336 **/ 2337 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2338 u16 seid, bool enable, u16 vid, 2339 struct i40e_asq_cmd_details *cmd_details) 2340 { 2341 struct i40e_aq_desc desc; 2342 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2343 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2344 enum i40e_status_code status; 2345 u16 flags = 0; 2346 2347 i40e_fill_default_direct_cmd_desc(&desc, 2348 i40e_aqc_opc_set_vsi_promiscuous_modes); 2349 2350 if (enable) 2351 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2352 2353 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2354 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2355 cmd->seid = CPU_TO_LE16(seid); 2356 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2357 2358 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2359 2360 return status; 2361 } 2362 2363 /** 2364 * i40e_aq_set_vsi_uc_promisc_on_vlan 2365 * @hw: pointer to the hw struct 2366 * @seid: vsi number 2367 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2368 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2369 * @cmd_details: pointer to command details structure or NULL 2370 **/ 2371 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2372 u16 seid, bool enable, u16 vid, 2373 struct i40e_asq_cmd_details *cmd_details) 2374 { 2375 struct i40e_aq_desc desc; 2376 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2377 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2378 enum i40e_status_code status; 2379 u16 flags = 0; 2380 2381 i40e_fill_default_direct_cmd_desc(&desc, 2382 i40e_aqc_opc_set_vsi_promiscuous_modes); 2383 2384 if (enable) 2385 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2386 2387 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2388 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2389 cmd->seid = CPU_TO_LE16(seid); 2390 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2391 2392 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2393 2394 return status; 2395 } 2396 2397 /** 2398 * i40e_aq_set_vsi_bc_promisc_on_vlan 2399 * @hw: pointer to the hw struct 2400 * @seid: vsi number 2401 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2402 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2403 * @cmd_details: pointer to command details structure or NULL 2404 **/ 2405 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2406 u16 seid, bool enable, u16 vid, 2407 struct i40e_asq_cmd_details *cmd_details) 2408 { 2409 struct i40e_aq_desc desc; 2410 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2411 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2412 enum i40e_status_code status; 2413 u16 flags = 0; 2414 2415 i40e_fill_default_direct_cmd_desc(&desc, 2416 i40e_aqc_opc_set_vsi_promiscuous_modes); 2417 2418 if (enable) 2419 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2420 2421 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2422 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2423 cmd->seid = CPU_TO_LE16(seid); 2424 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2425 2426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2427 2428 return status; 2429 } 2430 2431 /** 2432 * i40e_aq_set_vsi_broadcast 2433 * @hw: pointer to the hw struct 2434 * @seid: vsi number 2435 * @set_filter: TRUE to set filter, FALSE to clear filter 2436 * @cmd_details: pointer to command details structure or NULL 2437 * 2438 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2439 **/ 2440 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2441 u16 seid, bool set_filter, 2442 struct i40e_asq_cmd_details *cmd_details) 2443 { 2444 struct i40e_aq_desc desc; 2445 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2446 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2447 enum i40e_status_code status; 2448 2449 i40e_fill_default_direct_cmd_desc(&desc, 2450 i40e_aqc_opc_set_vsi_promiscuous_modes); 2451 2452 if (set_filter) 2453 cmd->promiscuous_flags 2454 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2455 else 2456 cmd->promiscuous_flags 2457 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2458 2459 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2460 cmd->seid = CPU_TO_LE16(seid); 2461 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2462 2463 return status; 2464 } 2465 2466 /** 2467 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2468 * @hw: pointer to the hw struct 2469 * @seid: vsi number 2470 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2471 * @cmd_details: pointer to command details structure or NULL 2472 **/ 2473 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2474 u16 seid, bool enable, 2475 struct i40e_asq_cmd_details *cmd_details) 2476 { 2477 struct i40e_aq_desc desc; 2478 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2479 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2480 enum i40e_status_code status; 2481 u16 flags = 0; 2482 2483 i40e_fill_default_direct_cmd_desc(&desc, 2484 i40e_aqc_opc_set_vsi_promiscuous_modes); 2485 if (enable) 2486 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2487 2488 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2489 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2490 cmd->seid = CPU_TO_LE16(seid); 2491 2492 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2493 2494 return status; 2495 } 2496 2497 /** 2498 * i40e_get_vsi_params - get VSI configuration info 2499 * @hw: pointer to the hw struct 2500 * @vsi_ctx: pointer to a vsi context struct 2501 * @cmd_details: pointer to command details structure or NULL 2502 **/ 2503 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2504 struct i40e_vsi_context *vsi_ctx, 2505 struct i40e_asq_cmd_details *cmd_details) 2506 { 2507 struct i40e_aq_desc desc; 2508 struct i40e_aqc_add_get_update_vsi *cmd = 2509 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2510 struct i40e_aqc_add_get_update_vsi_completion *resp = 2511 (struct i40e_aqc_add_get_update_vsi_completion *) 2512 &desc.params.raw; 2513 enum i40e_status_code status; 2514 2515 i40e_fill_default_direct_cmd_desc(&desc, 2516 i40e_aqc_opc_get_vsi_parameters); 2517 2518 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2519 2520 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2521 2522 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2523 sizeof(vsi_ctx->info), NULL); 2524 2525 if (status != I40E_SUCCESS) 2526 goto aq_get_vsi_params_exit; 2527 2528 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2529 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2530 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2531 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2532 2533 aq_get_vsi_params_exit: 2534 return status; 2535 } 2536 2537 /** 2538 * i40e_aq_update_vsi_params 2539 * @hw: pointer to the hw struct 2540 * @vsi_ctx: pointer to a vsi context struct 2541 * @cmd_details: pointer to command details structure or NULL 2542 * 2543 * Update a VSI context. 2544 **/ 2545 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2546 struct i40e_vsi_context *vsi_ctx, 2547 struct i40e_asq_cmd_details *cmd_details) 2548 { 2549 struct i40e_aq_desc desc; 2550 struct i40e_aqc_add_get_update_vsi *cmd = 2551 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2552 struct i40e_aqc_add_get_update_vsi_completion *resp = 2553 (struct i40e_aqc_add_get_update_vsi_completion *) 2554 &desc.params.raw; 2555 enum i40e_status_code status; 2556 2557 i40e_fill_default_direct_cmd_desc(&desc, 2558 i40e_aqc_opc_update_vsi_parameters); 2559 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2560 2561 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2562 2563 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2564 sizeof(vsi_ctx->info), cmd_details); 2565 2566 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2567 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2568 2569 return status; 2570 } 2571 2572 /** 2573 * i40e_aq_get_switch_config 2574 * @hw: pointer to the hardware structure 2575 * @buf: pointer to the result buffer 2576 * @buf_size: length of input buffer 2577 * @start_seid: seid to start for the report, 0 == beginning 2578 * @cmd_details: pointer to command details structure or NULL 2579 * 2580 * Fill the buf with switch configuration returned from AdminQ command 2581 **/ 2582 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2583 struct i40e_aqc_get_switch_config_resp *buf, 2584 u16 buf_size, u16 *start_seid, 2585 struct i40e_asq_cmd_details *cmd_details) 2586 { 2587 struct i40e_aq_desc desc; 2588 struct i40e_aqc_switch_seid *scfg = 2589 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2590 enum i40e_status_code status; 2591 2592 i40e_fill_default_direct_cmd_desc(&desc, 2593 i40e_aqc_opc_get_switch_config); 2594 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2595 if (buf_size > I40E_AQ_LARGE_BUF) 2596 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2597 scfg->seid = CPU_TO_LE16(*start_seid); 2598 2599 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2600 *start_seid = LE16_TO_CPU(scfg->seid); 2601 2602 return status; 2603 } 2604 2605 /** 2606 * i40e_aq_set_switch_config 2607 * @hw: pointer to the hardware structure 2608 * @flags: bit flag values to set 2609 * @mode: cloud filter mode 2610 * @valid_flags: which bit flags to set 2611 * @cmd_details: pointer to command details structure or NULL 2612 * 2613 * Set switch configuration bits 2614 **/ 2615 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2616 u16 flags, u16 valid_flags, u8 mode, 2617 struct i40e_asq_cmd_details *cmd_details) 2618 { 2619 struct i40e_aq_desc desc; 2620 struct i40e_aqc_set_switch_config *scfg = 2621 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2622 enum i40e_status_code status; 2623 2624 i40e_fill_default_direct_cmd_desc(&desc, 2625 i40e_aqc_opc_set_switch_config); 2626 scfg->flags = CPU_TO_LE16(flags); 2627 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2628 scfg->mode = mode; 2629 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) { 2630 scfg->switch_tag = CPU_TO_LE16(hw->switch_tag); 2631 scfg->first_tag = CPU_TO_LE16(hw->first_tag); 2632 scfg->second_tag = CPU_TO_LE16(hw->second_tag); 2633 } 2634 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2635 2636 return status; 2637 } 2638 2639 /** 2640 * i40e_aq_get_firmware_version 2641 * @hw: pointer to the hw struct 2642 * @fw_major_version: firmware major version 2643 * @fw_minor_version: firmware minor version 2644 * @fw_build: firmware build number 2645 * @api_major_version: major queue version 2646 * @api_minor_version: minor queue version 2647 * @cmd_details: pointer to command details structure or NULL 2648 * 2649 * Get the firmware version from the admin queue commands 2650 **/ 2651 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2652 u16 *fw_major_version, u16 *fw_minor_version, 2653 u32 *fw_build, 2654 u16 *api_major_version, u16 *api_minor_version, 2655 struct i40e_asq_cmd_details *cmd_details) 2656 { 2657 struct i40e_aq_desc desc; 2658 struct i40e_aqc_get_version *resp = 2659 (struct i40e_aqc_get_version *)&desc.params.raw; 2660 enum i40e_status_code status; 2661 2662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2663 2664 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2665 2666 if (status == I40E_SUCCESS) { 2667 if (fw_major_version != NULL) 2668 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2669 if (fw_minor_version != NULL) 2670 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2671 if (fw_build != NULL) 2672 *fw_build = LE32_TO_CPU(resp->fw_build); 2673 if (api_major_version != NULL) 2674 *api_major_version = LE16_TO_CPU(resp->api_major); 2675 if (api_minor_version != NULL) 2676 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2677 2678 /* A workaround to fix the API version in SW */ 2679 if (api_major_version && api_minor_version && 2680 fw_major_version && fw_minor_version && 2681 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2682 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2683 (*fw_major_version > 4))) 2684 *api_minor_version = 2; 2685 } 2686 2687 return status; 2688 } 2689 2690 /** 2691 * i40e_aq_send_driver_version 2692 * @hw: pointer to the hw struct 2693 * @dv: driver's major, minor version 2694 * @cmd_details: pointer to command details structure or NULL 2695 * 2696 * Send the driver version to the firmware 2697 **/ 2698 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2699 struct i40e_driver_version *dv, 2700 struct i40e_asq_cmd_details *cmd_details) 2701 { 2702 struct i40e_aq_desc desc; 2703 struct i40e_aqc_driver_version *cmd = 2704 (struct i40e_aqc_driver_version *)&desc.params.raw; 2705 enum i40e_status_code status; 2706 u16 len; 2707 2708 if (dv == NULL) 2709 return I40E_ERR_PARAM; 2710 2711 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2712 2713 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2714 cmd->driver_major_ver = dv->major_version; 2715 cmd->driver_minor_ver = dv->minor_version; 2716 cmd->driver_build_ver = dv->build_version; 2717 cmd->driver_subbuild_ver = dv->subbuild_version; 2718 2719 len = 0; 2720 while (len < sizeof(dv->driver_string) && 2721 (dv->driver_string[len] < 0x80) && 2722 dv->driver_string[len]) 2723 len++; 2724 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2725 len, cmd_details); 2726 2727 return status; 2728 } 2729 2730 /** 2731 * i40e_get_link_status - get status of the HW network link 2732 * @hw: pointer to the hw struct 2733 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2734 * 2735 * Variable link_up TRUE if link is up, FALSE if link is down. 2736 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2737 * 2738 * Side effect: LinkStatusEvent reporting becomes enabled 2739 **/ 2740 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2741 { 2742 enum i40e_status_code status = I40E_SUCCESS; 2743 2744 if (hw->phy.get_link_info) { 2745 status = i40e_update_link_info(hw); 2746 2747 if (status != I40E_SUCCESS) 2748 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2749 status); 2750 } 2751 2752 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2753 2754 return status; 2755 } 2756 2757 /** 2758 * i40e_updatelink_status - update status of the HW network link 2759 * @hw: pointer to the hw struct 2760 **/ 2761 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2762 { 2763 struct i40e_aq_get_phy_abilities_resp abilities; 2764 enum i40e_status_code status = I40E_SUCCESS; 2765 2766 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2767 if (status) 2768 return status; 2769 2770 /* extra checking needed to ensure link info to user is timely */ 2771 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2772 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2773 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2774 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2775 &abilities, NULL); 2776 if (status) 2777 return status; 2778 2779 hw->phy.link_info.req_fec_info = 2780 abilities.fec_cfg_curr_mod_ext_info & 2781 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS); 2782 2783 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2784 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2785 } 2786 return status; 2787 } 2788 2789 2790 /** 2791 * i40e_get_link_speed 2792 * @hw: pointer to the hw struct 2793 * 2794 * Returns the link speed of the adapter. 2795 **/ 2796 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2797 { 2798 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2799 enum i40e_status_code status = I40E_SUCCESS; 2800 2801 if (hw->phy.get_link_info) { 2802 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2803 2804 if (status != I40E_SUCCESS) 2805 goto i40e_link_speed_exit; 2806 } 2807 2808 speed = hw->phy.link_info.link_speed; 2809 2810 i40e_link_speed_exit: 2811 return speed; 2812 } 2813 2814 /** 2815 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2816 * @hw: pointer to the hw struct 2817 * @uplink_seid: the MAC or other gizmo SEID 2818 * @downlink_seid: the VSI SEID 2819 * @enabled_tc: bitmap of TCs to be enabled 2820 * @default_port: TRUE for default port VSI, FALSE for control port 2821 * @veb_seid: pointer to where to put the resulting VEB SEID 2822 * @enable_stats: TRUE to turn on VEB stats 2823 * @cmd_details: pointer to command details structure or NULL 2824 * 2825 * This asks the FW to add a VEB between the uplink and downlink 2826 * elements. If the uplink SEID is 0, this will be a floating VEB. 2827 **/ 2828 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2829 u16 downlink_seid, u8 enabled_tc, 2830 bool default_port, u16 *veb_seid, 2831 bool enable_stats, 2832 struct i40e_asq_cmd_details *cmd_details) 2833 { 2834 struct i40e_aq_desc desc; 2835 struct i40e_aqc_add_veb *cmd = 2836 (struct i40e_aqc_add_veb *)&desc.params.raw; 2837 struct i40e_aqc_add_veb_completion *resp = 2838 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2839 enum i40e_status_code status; 2840 u16 veb_flags = 0; 2841 2842 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2843 if (!!uplink_seid != !!downlink_seid) 2844 return I40E_ERR_PARAM; 2845 2846 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2847 2848 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2849 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2850 cmd->enable_tcs = enabled_tc; 2851 if (!uplink_seid) 2852 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2853 if (default_port) 2854 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2855 else 2856 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2857 2858 /* reverse logic here: set the bitflag to disable the stats */ 2859 if (!enable_stats) 2860 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2861 2862 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2863 2864 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2865 2866 if (!status && veb_seid) 2867 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2868 2869 return status; 2870 } 2871 2872 /** 2873 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2874 * @hw: pointer to the hw struct 2875 * @veb_seid: the SEID of the VEB to query 2876 * @switch_id: the uplink switch id 2877 * @floating: set to TRUE if the VEB is floating 2878 * @statistic_index: index of the stats counter block for this VEB 2879 * @vebs_used: number of VEB's used by function 2880 * @vebs_free: total VEB's not reserved by any function 2881 * @cmd_details: pointer to command details structure or NULL 2882 * 2883 * This retrieves the parameters for a particular VEB, specified by 2884 * uplink_seid, and returns them to the caller. 2885 **/ 2886 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2887 u16 veb_seid, u16 *switch_id, 2888 bool *floating, u16 *statistic_index, 2889 u16 *vebs_used, u16 *vebs_free, 2890 struct i40e_asq_cmd_details *cmd_details) 2891 { 2892 struct i40e_aq_desc desc; 2893 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2894 (struct i40e_aqc_get_veb_parameters_completion *) 2895 &desc.params.raw; 2896 enum i40e_status_code status; 2897 2898 if (veb_seid == 0) 2899 return I40E_ERR_PARAM; 2900 2901 i40e_fill_default_direct_cmd_desc(&desc, 2902 i40e_aqc_opc_get_veb_parameters); 2903 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2904 2905 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2906 if (status) 2907 goto get_veb_exit; 2908 2909 if (switch_id) 2910 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2911 if (statistic_index) 2912 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2913 if (vebs_used) 2914 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2915 if (vebs_free) 2916 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2917 if (floating) { 2918 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2919 2920 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2921 *floating = TRUE; 2922 else 2923 *floating = FALSE; 2924 } 2925 2926 get_veb_exit: 2927 return status; 2928 } 2929 2930 /** 2931 * i40e_aq_add_macvlan 2932 * @hw: pointer to the hw struct 2933 * @seid: VSI for the mac address 2934 * @mv_list: list of macvlans to be added 2935 * @count: length of the list 2936 * @cmd_details: pointer to command details structure or NULL 2937 * 2938 * Add MAC/VLAN addresses to the HW filtering 2939 **/ 2940 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2941 struct i40e_aqc_add_macvlan_element_data *mv_list, 2942 u16 count, struct i40e_asq_cmd_details *cmd_details) 2943 { 2944 struct i40e_aq_desc desc; 2945 struct i40e_aqc_macvlan *cmd = 2946 (struct i40e_aqc_macvlan *)&desc.params.raw; 2947 enum i40e_status_code status; 2948 u16 buf_size; 2949 int i; 2950 2951 if (count == 0 || !mv_list || !hw) 2952 return I40E_ERR_PARAM; 2953 2954 buf_size = count * sizeof(*mv_list); 2955 2956 /* prep the rest of the request */ 2957 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2958 cmd->num_addresses = CPU_TO_LE16(count); 2959 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2960 cmd->seid[1] = 0; 2961 cmd->seid[2] = 0; 2962 2963 for (i = 0; i < count; i++) 2964 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2965 mv_list[i].flags |= 2966 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2967 2968 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2969 if (buf_size > I40E_AQ_LARGE_BUF) 2970 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2971 2972 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2973 cmd_details); 2974 2975 return status; 2976 } 2977 2978 /** 2979 * i40e_aq_remove_macvlan 2980 * @hw: pointer to the hw struct 2981 * @seid: VSI for the mac address 2982 * @mv_list: list of macvlans to be removed 2983 * @count: length of the list 2984 * @cmd_details: pointer to command details structure or NULL 2985 * 2986 * Remove MAC/VLAN addresses from the HW filtering 2987 **/ 2988 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2989 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2990 u16 count, struct i40e_asq_cmd_details *cmd_details) 2991 { 2992 struct i40e_aq_desc desc; 2993 struct i40e_aqc_macvlan *cmd = 2994 (struct i40e_aqc_macvlan *)&desc.params.raw; 2995 enum i40e_status_code status; 2996 u16 buf_size; 2997 2998 if (count == 0 || !mv_list || !hw) 2999 return I40E_ERR_PARAM; 3000 3001 buf_size = count * sizeof(*mv_list); 3002 3003 /* prep the rest of the request */ 3004 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 3005 cmd->num_addresses = CPU_TO_LE16(count); 3006 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 3007 cmd->seid[1] = 0; 3008 cmd->seid[2] = 0; 3009 3010 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3011 if (buf_size > I40E_AQ_LARGE_BUF) 3012 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3013 3014 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 3015 cmd_details); 3016 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 3022 * @hw: pointer to the hw struct 3023 * @opcode: AQ opcode for add or delete mirror rule 3024 * @sw_seid: Switch SEID (to which rule refers) 3025 * @rule_type: Rule Type (ingress/egress/VLAN) 3026 * @id: Destination VSI SEID or Rule ID 3027 * @count: length of the list 3028 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3029 * @cmd_details: pointer to command details structure or NULL 3030 * @rule_id: Rule ID returned from FW 3031 * @rules_used: Number of rules used in internal switch 3032 * @rules_free: Number of rules free in internal switch 3033 * 3034 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 3035 * VEBs/VEPA elements only 3036 **/ 3037 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 3038 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 3039 u16 count, __le16 *mr_list, 3040 struct i40e_asq_cmd_details *cmd_details, 3041 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3042 { 3043 struct i40e_aq_desc desc; 3044 struct i40e_aqc_add_delete_mirror_rule *cmd = 3045 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 3046 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 3047 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 3048 enum i40e_status_code status; 3049 u16 buf_size; 3050 3051 buf_size = count * sizeof(*mr_list); 3052 3053 /* prep the rest of the request */ 3054 i40e_fill_default_direct_cmd_desc(&desc, opcode); 3055 cmd->seid = CPU_TO_LE16(sw_seid); 3056 cmd->rule_type = CPU_TO_LE16(rule_type & 3057 I40E_AQC_MIRROR_RULE_TYPE_MASK); 3058 cmd->num_entries = CPU_TO_LE16(count); 3059 /* Dest VSI for add, rule_id for delete */ 3060 cmd->destination = CPU_TO_LE16(id); 3061 if (mr_list) { 3062 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3063 I40E_AQ_FLAG_RD)); 3064 if (buf_size > I40E_AQ_LARGE_BUF) 3065 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3066 } 3067 3068 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3069 cmd_details); 3070 if (status == I40E_SUCCESS || 3071 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3072 if (rule_id) 3073 *rule_id = LE16_TO_CPU(resp->rule_id); 3074 if (rules_used) 3075 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3076 if (rules_free) 3077 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3078 } 3079 return status; 3080 } 3081 3082 /** 3083 * i40e_aq_add_mirrorrule - add a mirror rule 3084 * @hw: pointer to the hw struct 3085 * @sw_seid: Switch SEID (to which rule refers) 3086 * @rule_type: Rule Type (ingress/egress/VLAN) 3087 * @dest_vsi: SEID of VSI to which packets will be mirrored 3088 * @count: length of the list 3089 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3090 * @cmd_details: pointer to command details structure or NULL 3091 * @rule_id: Rule ID returned from FW 3092 * @rules_used: Number of rules used in internal switch 3093 * @rules_free: Number of rules free in internal switch 3094 * 3095 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3096 **/ 3097 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3098 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3099 struct i40e_asq_cmd_details *cmd_details, 3100 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3101 { 3102 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3103 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3104 if (count == 0 || !mr_list) 3105 return I40E_ERR_PARAM; 3106 } 3107 3108 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3109 rule_type, dest_vsi, count, mr_list, 3110 cmd_details, rule_id, rules_used, rules_free); 3111 } 3112 3113 /** 3114 * i40e_aq_delete_mirrorrule - delete a mirror rule 3115 * @hw: pointer to the hw struct 3116 * @sw_seid: Switch SEID (to which rule refers) 3117 * @rule_type: Rule Type (ingress/egress/VLAN) 3118 * @count: length of the list 3119 * @rule_id: Rule ID that is returned in the receive desc as part of 3120 * add_mirrorrule. 3121 * @mr_list: list of mirrored VLAN IDs to be removed 3122 * @cmd_details: pointer to command details structure or NULL 3123 * @rules_used: Number of rules used in internal switch 3124 * @rules_free: Number of rules free in internal switch 3125 * 3126 * Delete a mirror rule. Mirror rules are supported for VEBs/VEPA elements only 3127 **/ 3128 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3129 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list, 3130 struct i40e_asq_cmd_details *cmd_details, 3131 u16 *rules_used, u16 *rules_free) 3132 { 3133 /* Rule ID has to be valid except rule_type: INGRESS VLAN mirroring */ 3134 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) { 3135 /* count and mr_list shall be valid for rule_type INGRESS VLAN 3136 * mirroring. For other rule_type, count and rule_type should 3137 * not matter. 3138 */ 3139 if (count == 0 || !mr_list) 3140 return I40E_ERR_PARAM; 3141 } 3142 3143 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid, 3144 rule_type, rule_id, count, mr_list, 3145 cmd_details, NULL, rules_used, rules_free); 3146 } 3147 3148 /** 3149 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering 3150 * @hw: pointer to the hw struct 3151 * @seid: VSI for the vlan filters 3152 * @v_list: list of vlan filters to be added 3153 * @count: length of the list 3154 * @cmd_details: pointer to command details structure or NULL 3155 **/ 3156 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid, 3157 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3158 u8 count, struct i40e_asq_cmd_details *cmd_details) 3159 { 3160 struct i40e_aq_desc desc; 3161 struct i40e_aqc_macvlan *cmd = 3162 (struct i40e_aqc_macvlan *)&desc.params.raw; 3163 enum i40e_status_code status; 3164 u16 buf_size; 3165 3166 if (count == 0 || !v_list || !hw) 3167 return I40E_ERR_PARAM; 3168 3169 buf_size = count * sizeof(*v_list); 3170 3171 /* prep the rest of the request */ 3172 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan); 3173 cmd->num_addresses = CPU_TO_LE16(count); 3174 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3175 cmd->seid[1] = 0; 3176 cmd->seid[2] = 0; 3177 3178 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3179 if (buf_size > I40E_AQ_LARGE_BUF) 3180 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3181 3182 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3183 cmd_details); 3184 3185 return status; 3186 } 3187 3188 /** 3189 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering 3190 * @hw: pointer to the hw struct 3191 * @seid: VSI for the vlan filters 3192 * @v_list: list of macvlans to be removed 3193 * @count: length of the list 3194 * @cmd_details: pointer to command details structure or NULL 3195 **/ 3196 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid, 3197 struct i40e_aqc_add_remove_vlan_element_data *v_list, 3198 u8 count, struct i40e_asq_cmd_details *cmd_details) 3199 { 3200 struct i40e_aq_desc desc; 3201 struct i40e_aqc_macvlan *cmd = 3202 (struct i40e_aqc_macvlan *)&desc.params.raw; 3203 enum i40e_status_code status; 3204 u16 buf_size; 3205 3206 if (count == 0 || !v_list || !hw) 3207 return I40E_ERR_PARAM; 3208 3209 buf_size = count * sizeof(*v_list); 3210 3211 /* prep the rest of the request */ 3212 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan); 3213 cmd->num_addresses = CPU_TO_LE16(count); 3214 cmd->seid[0] = CPU_TO_LE16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID); 3215 cmd->seid[1] = 0; 3216 cmd->seid[2] = 0; 3217 3218 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3219 if (buf_size > I40E_AQ_LARGE_BUF) 3220 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3221 3222 status = i40e_asq_send_command(hw, &desc, v_list, buf_size, 3223 cmd_details); 3224 3225 return status; 3226 } 3227 3228 /** 3229 * i40e_aq_send_msg_to_vf 3230 * @hw: pointer to the hardware structure 3231 * @vfid: vf id to send msg 3232 * @v_opcode: opcodes for VF-PF communication 3233 * @v_retval: return error code 3234 * @msg: pointer to the msg buffer 3235 * @msglen: msg length 3236 * @cmd_details: pointer to command details 3237 * 3238 * send msg to vf 3239 **/ 3240 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid, 3241 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen, 3242 struct i40e_asq_cmd_details *cmd_details) 3243 { 3244 struct i40e_aq_desc desc; 3245 struct i40e_aqc_pf_vf_message *cmd = 3246 (struct i40e_aqc_pf_vf_message *)&desc.params.raw; 3247 enum i40e_status_code status; 3248 3249 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf); 3250 cmd->id = CPU_TO_LE32(vfid); 3251 desc.cookie_high = CPU_TO_LE32(v_opcode); 3252 desc.cookie_low = CPU_TO_LE32(v_retval); 3253 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_SI); 3254 if (msglen) { 3255 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3256 I40E_AQ_FLAG_RD)); 3257 if (msglen > I40E_AQ_LARGE_BUF) 3258 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3259 desc.datalen = CPU_TO_LE16(msglen); 3260 } 3261 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details); 3262 3263 return status; 3264 } 3265 3266 /** 3267 * i40e_aq_debug_read_register 3268 * @hw: pointer to the hw struct 3269 * @reg_addr: register address 3270 * @reg_val: register value 3271 * @cmd_details: pointer to command details structure or NULL 3272 * 3273 * Read the register using the admin queue commands 3274 **/ 3275 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw, 3276 u32 reg_addr, u64 *reg_val, 3277 struct i40e_asq_cmd_details *cmd_details) 3278 { 3279 struct i40e_aq_desc desc; 3280 struct i40e_aqc_debug_reg_read_write *cmd_resp = 3281 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3282 enum i40e_status_code status; 3283 3284 if (reg_val == NULL) 3285 return I40E_ERR_PARAM; 3286 3287 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg); 3288 3289 cmd_resp->address = CPU_TO_LE32(reg_addr); 3290 3291 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3292 3293 if (status == I40E_SUCCESS) { 3294 *reg_val = ((u64)LE32_TO_CPU(cmd_resp->value_high) << 32) | 3295 (u64)LE32_TO_CPU(cmd_resp->value_low); 3296 } 3297 3298 return status; 3299 } 3300 3301 /** 3302 * i40e_aq_debug_write_register 3303 * @hw: pointer to the hw struct 3304 * @reg_addr: register address 3305 * @reg_val: register value 3306 * @cmd_details: pointer to command details structure or NULL 3307 * 3308 * Write to a register using the admin queue commands 3309 **/ 3310 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw, 3311 u32 reg_addr, u64 reg_val, 3312 struct i40e_asq_cmd_details *cmd_details) 3313 { 3314 struct i40e_aq_desc desc; 3315 struct i40e_aqc_debug_reg_read_write *cmd = 3316 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw; 3317 enum i40e_status_code status; 3318 3319 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg); 3320 3321 cmd->address = CPU_TO_LE32(reg_addr); 3322 cmd->value_high = CPU_TO_LE32((u32)(reg_val >> 32)); 3323 cmd->value_low = CPU_TO_LE32((u32)(reg_val & 0xFFFFFFFF)); 3324 3325 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3326 3327 return status; 3328 } 3329 3330 /** 3331 * i40e_aq_request_resource 3332 * @hw: pointer to the hw struct 3333 * @resource: resource id 3334 * @access: access type 3335 * @sdp_number: resource number 3336 * @timeout: the maximum time in ms that the driver may hold the resource 3337 * @cmd_details: pointer to command details structure or NULL 3338 * 3339 * requests common resource using the admin queue commands 3340 **/ 3341 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw, 3342 enum i40e_aq_resources_ids resource, 3343 enum i40e_aq_resource_access_type access, 3344 u8 sdp_number, u64 *timeout, 3345 struct i40e_asq_cmd_details *cmd_details) 3346 { 3347 struct i40e_aq_desc desc; 3348 struct i40e_aqc_request_resource *cmd_resp = 3349 (struct i40e_aqc_request_resource *)&desc.params.raw; 3350 enum i40e_status_code status; 3351 3352 DEBUGFUNC("i40e_aq_request_resource"); 3353 3354 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource); 3355 3356 cmd_resp->resource_id = CPU_TO_LE16(resource); 3357 cmd_resp->access_type = CPU_TO_LE16(access); 3358 cmd_resp->resource_number = CPU_TO_LE32(sdp_number); 3359 3360 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3361 /* The completion specifies the maximum time in ms that the driver 3362 * may hold the resource in the Timeout field. 3363 * If the resource is held by someone else, the command completes with 3364 * busy return value and the timeout field indicates the maximum time 3365 * the current owner of the resource has to free it. 3366 */ 3367 if (status == I40E_SUCCESS || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) 3368 *timeout = LE32_TO_CPU(cmd_resp->timeout); 3369 3370 return status; 3371 } 3372 3373 /** 3374 * i40e_aq_release_resource 3375 * @hw: pointer to the hw struct 3376 * @resource: resource id 3377 * @sdp_number: resource number 3378 * @cmd_details: pointer to command details structure or NULL 3379 * 3380 * release common resource using the admin queue commands 3381 **/ 3382 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw, 3383 enum i40e_aq_resources_ids resource, 3384 u8 sdp_number, 3385 struct i40e_asq_cmd_details *cmd_details) 3386 { 3387 struct i40e_aq_desc desc; 3388 struct i40e_aqc_request_resource *cmd = 3389 (struct i40e_aqc_request_resource *)&desc.params.raw; 3390 enum i40e_status_code status; 3391 3392 DEBUGFUNC("i40e_aq_release_resource"); 3393 3394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource); 3395 3396 cmd->resource_id = CPU_TO_LE16(resource); 3397 cmd->resource_number = CPU_TO_LE32(sdp_number); 3398 3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3400 3401 return status; 3402 } 3403 3404 /** 3405 * i40e_aq_read_nvm 3406 * @hw: pointer to the hw struct 3407 * @module_pointer: module pointer location in words from the NVM beginning 3408 * @offset: byte offset from the module beginning 3409 * @length: length of the section to be read (in bytes from the offset) 3410 * @data: command buffer (size [bytes] = length) 3411 * @last_command: tells if this is the last command in a series 3412 * @cmd_details: pointer to command details structure or NULL 3413 * 3414 * Read the NVM using the admin queue commands 3415 **/ 3416 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer, 3417 u32 offset, u16 length, void *data, 3418 bool last_command, 3419 struct i40e_asq_cmd_details *cmd_details) 3420 { 3421 struct i40e_aq_desc desc; 3422 struct i40e_aqc_nvm_update *cmd = 3423 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3424 enum i40e_status_code status; 3425 3426 DEBUGFUNC("i40e_aq_read_nvm"); 3427 3428 /* In offset the highest byte must be zeroed. */ 3429 if (offset & 0xFF000000) { 3430 status = I40E_ERR_PARAM; 3431 goto i40e_aq_read_nvm_exit; 3432 } 3433 3434 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read); 3435 3436 /* If this is the last command in a series, set the proper flag. */ 3437 if (last_command) 3438 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3439 cmd->module_pointer = module_pointer; 3440 cmd->offset = CPU_TO_LE32(offset); 3441 cmd->length = CPU_TO_LE16(length); 3442 3443 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3444 if (length > I40E_AQ_LARGE_BUF) 3445 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3446 3447 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 3448 3449 i40e_aq_read_nvm_exit: 3450 return status; 3451 } 3452 3453 /** 3454 * i40e_aq_read_nvm_config - read an nvm config block 3455 * @hw: pointer to the hw struct 3456 * @cmd_flags: NVM access admin command bits 3457 * @field_id: field or feature id 3458 * @data: buffer for result 3459 * @buf_size: buffer size 3460 * @element_count: pointer to count of elements read by FW 3461 * @cmd_details: pointer to command details structure or NULL 3462 **/ 3463 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw, 3464 u8 cmd_flags, u32 field_id, void *data, 3465 u16 buf_size, u16 *element_count, 3466 struct i40e_asq_cmd_details *cmd_details) 3467 { 3468 struct i40e_aq_desc desc; 3469 struct i40e_aqc_nvm_config_read *cmd = 3470 (struct i40e_aqc_nvm_config_read *)&desc.params.raw; 3471 enum i40e_status_code status; 3472 3473 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_read); 3474 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF)); 3475 if (buf_size > I40E_AQ_LARGE_BUF) 3476 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3477 3478 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3479 cmd->element_id = CPU_TO_LE16((u16)(0xffff & field_id)); 3480 if (cmd_flags & I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK) 3481 cmd->element_id_msw = CPU_TO_LE16((u16)(field_id >> 16)); 3482 else 3483 cmd->element_id_msw = 0; 3484 3485 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3486 3487 if (!status && element_count) 3488 *element_count = LE16_TO_CPU(cmd->element_count); 3489 3490 return status; 3491 } 3492 3493 /** 3494 * i40e_aq_write_nvm_config - write an nvm config block 3495 * @hw: pointer to the hw struct 3496 * @cmd_flags: NVM access admin command bits 3497 * @data: buffer for result 3498 * @buf_size: buffer size 3499 * @element_count: count of elements to be written 3500 * @cmd_details: pointer to command details structure or NULL 3501 **/ 3502 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw, 3503 u8 cmd_flags, void *data, u16 buf_size, 3504 u16 element_count, 3505 struct i40e_asq_cmd_details *cmd_details) 3506 { 3507 struct i40e_aq_desc desc; 3508 struct i40e_aqc_nvm_config_write *cmd = 3509 (struct i40e_aqc_nvm_config_write *)&desc.params.raw; 3510 enum i40e_status_code status; 3511 3512 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_config_write); 3513 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 3514 if (buf_size > I40E_AQ_LARGE_BUF) 3515 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3516 3517 cmd->element_count = CPU_TO_LE16(element_count); 3518 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 3519 status = i40e_asq_send_command(hw, &desc, data, buf_size, cmd_details); 3520 3521 return status; 3522 } 3523 3524 /** 3525 * i40e_aq_oem_post_update - triggers an OEM specific flow after update 3526 * @hw: pointer to the hw struct 3527 * @buff: buffer for result 3528 * @buff_size: buffer size 3529 * @cmd_details: pointer to command details structure or NULL 3530 **/ 3531 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw, 3532 void *buff, u16 buff_size, 3533 struct i40e_asq_cmd_details *cmd_details) 3534 { 3535 struct i40e_aq_desc desc; 3536 enum i40e_status_code status; 3537 3538 3539 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_oem_post_update); 3540 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3541 if (status && LE16_TO_CPU(desc.retval) == I40E_AQ_RC_ESRCH) 3542 status = I40E_ERR_NOT_IMPLEMENTED; 3543 3544 return status; 3545 } 3546 3547 /** 3548 * i40e_aq_erase_nvm 3549 * @hw: pointer to the hw struct 3550 * @module_pointer: module pointer location in words from the NVM beginning 3551 * @offset: offset in the module (expressed in 4 KB from module's beginning) 3552 * @length: length of the section to be erased (expressed in 4 KB) 3553 * @last_command: tells if this is the last command in a series 3554 * @cmd_details: pointer to command details structure or NULL 3555 * 3556 * Erase the NVM sector using the admin queue commands 3557 **/ 3558 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer, 3559 u32 offset, u16 length, bool last_command, 3560 struct i40e_asq_cmd_details *cmd_details) 3561 { 3562 struct i40e_aq_desc desc; 3563 struct i40e_aqc_nvm_update *cmd = 3564 (struct i40e_aqc_nvm_update *)&desc.params.raw; 3565 enum i40e_status_code status; 3566 3567 DEBUGFUNC("i40e_aq_erase_nvm"); 3568 3569 /* In offset the highest byte must be zeroed. */ 3570 if (offset & 0xFF000000) { 3571 status = I40E_ERR_PARAM; 3572 goto i40e_aq_erase_nvm_exit; 3573 } 3574 3575 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase); 3576 3577 /* If this is the last command in a series, set the proper flag. */ 3578 if (last_command) 3579 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 3580 cmd->module_pointer = module_pointer; 3581 cmd->offset = CPU_TO_LE32(offset); 3582 cmd->length = CPU_TO_LE16(length); 3583 3584 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 3585 3586 i40e_aq_erase_nvm_exit: 3587 return status; 3588 } 3589 3590 /** 3591 * i40e_parse_discover_capabilities 3592 * @hw: pointer to the hw struct 3593 * @buff: pointer to a buffer containing device/function capability records 3594 * @cap_count: number of capability records in the list 3595 * @list_type_opc: type of capabilities list to parse 3596 * 3597 * Parse the device/function capabilities list. 3598 **/ 3599 static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, 3600 u32 cap_count, 3601 enum i40e_admin_queue_opc list_type_opc) 3602 { 3603 struct i40e_aqc_list_capabilities_element_resp *cap; 3604 u32 valid_functions, num_functions; 3605 u32 number, logical_id, phys_id; 3606 struct i40e_hw_capabilities *p; 3607 enum i40e_status_code status; 3608 u16 id, ocp_cfg_word0; 3609 u8 major_rev; 3610 u32 i = 0; 3611 3612 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff; 3613 3614 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities) 3615 p = (struct i40e_hw_capabilities *)&hw->dev_caps; 3616 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities) 3617 p = (struct i40e_hw_capabilities *)&hw->func_caps; 3618 else 3619 return; 3620 3621 for (i = 0; i < cap_count; i++, cap++) { 3622 id = LE16_TO_CPU(cap->id); 3623 number = LE32_TO_CPU(cap->number); 3624 logical_id = LE32_TO_CPU(cap->logical_id); 3625 phys_id = LE32_TO_CPU(cap->phys_id); 3626 major_rev = cap->major_rev; 3627 3628 switch (id) { 3629 case I40E_AQ_CAP_ID_SWITCH_MODE: 3630 p->switch_mode = number; 3631 i40e_debug(hw, I40E_DEBUG_INIT, 3632 "HW Capability: Switch mode = %d\n", 3633 p->switch_mode); 3634 break; 3635 case I40E_AQ_CAP_ID_MNG_MODE: 3636 p->management_mode = number; 3637 if (major_rev > 1) { 3638 p->mng_protocols_over_mctp = logical_id; 3639 i40e_debug(hw, I40E_DEBUG_INIT, 3640 "HW Capability: Protocols over MCTP = %d\n", 3641 p->mng_protocols_over_mctp); 3642 } else { 3643 p->mng_protocols_over_mctp = 0; 3644 } 3645 i40e_debug(hw, I40E_DEBUG_INIT, 3646 "HW Capability: Management Mode = %d\n", 3647 p->management_mode); 3648 break; 3649 case I40E_AQ_CAP_ID_NPAR_ACTIVE: 3650 p->npar_enable = number; 3651 i40e_debug(hw, I40E_DEBUG_INIT, 3652 "HW Capability: NPAR enable = %d\n", 3653 p->npar_enable); 3654 break; 3655 case I40E_AQ_CAP_ID_OS2BMC_CAP: 3656 p->os2bmc = number; 3657 i40e_debug(hw, I40E_DEBUG_INIT, 3658 "HW Capability: OS2BMC = %d\n", p->os2bmc); 3659 break; 3660 case I40E_AQ_CAP_ID_FUNCTIONS_VALID: 3661 p->valid_functions = number; 3662 i40e_debug(hw, I40E_DEBUG_INIT, 3663 "HW Capability: Valid Functions = %d\n", 3664 p->valid_functions); 3665 break; 3666 case I40E_AQ_CAP_ID_SRIOV: 3667 if (number == 1) 3668 p->sr_iov_1_1 = TRUE; 3669 i40e_debug(hw, I40E_DEBUG_INIT, 3670 "HW Capability: SR-IOV = %d\n", 3671 p->sr_iov_1_1); 3672 break; 3673 case I40E_AQ_CAP_ID_VF: 3674 p->num_vfs = number; 3675 p->vf_base_id = logical_id; 3676 i40e_debug(hw, I40E_DEBUG_INIT, 3677 "HW Capability: VF count = %d\n", 3678 p->num_vfs); 3679 i40e_debug(hw, I40E_DEBUG_INIT, 3680 "HW Capability: VF base_id = %d\n", 3681 p->vf_base_id); 3682 break; 3683 case I40E_AQ_CAP_ID_VMDQ: 3684 if (number == 1) 3685 p->vmdq = TRUE; 3686 i40e_debug(hw, I40E_DEBUG_INIT, 3687 "HW Capability: VMDQ = %d\n", p->vmdq); 3688 break; 3689 case I40E_AQ_CAP_ID_8021QBG: 3690 if (number == 1) 3691 p->evb_802_1_qbg = TRUE; 3692 i40e_debug(hw, I40E_DEBUG_INIT, 3693 "HW Capability: 802.1Qbg = %d\n", number); 3694 break; 3695 case I40E_AQ_CAP_ID_8021QBR: 3696 if (number == 1) 3697 p->evb_802_1_qbh = TRUE; 3698 i40e_debug(hw, I40E_DEBUG_INIT, 3699 "HW Capability: 802.1Qbh = %d\n", number); 3700 break; 3701 case I40E_AQ_CAP_ID_VSI: 3702 p->num_vsis = number; 3703 i40e_debug(hw, I40E_DEBUG_INIT, 3704 "HW Capability: VSI count = %d\n", 3705 p->num_vsis); 3706 break; 3707 case I40E_AQ_CAP_ID_DCB: 3708 if (number == 1) { 3709 p->dcb = TRUE; 3710 p->enabled_tcmap = logical_id; 3711 p->maxtc = phys_id; 3712 } 3713 i40e_debug(hw, I40E_DEBUG_INIT, 3714 "HW Capability: DCB = %d\n", p->dcb); 3715 i40e_debug(hw, I40E_DEBUG_INIT, 3716 "HW Capability: TC Mapping = %d\n", 3717 logical_id); 3718 i40e_debug(hw, I40E_DEBUG_INIT, 3719 "HW Capability: TC Max = %d\n", p->maxtc); 3720 break; 3721 case I40E_AQ_CAP_ID_FCOE: 3722 if (number == 1) 3723 p->fcoe = TRUE; 3724 i40e_debug(hw, I40E_DEBUG_INIT, 3725 "HW Capability: FCOE = %d\n", p->fcoe); 3726 break; 3727 case I40E_AQ_CAP_ID_ISCSI: 3728 if (number == 1) 3729 p->iscsi = TRUE; 3730 i40e_debug(hw, I40E_DEBUG_INIT, 3731 "HW Capability: iSCSI = %d\n", p->iscsi); 3732 break; 3733 case I40E_AQ_CAP_ID_RSS: 3734 p->rss = TRUE; 3735 p->rss_table_size = number; 3736 p->rss_table_entry_width = logical_id; 3737 i40e_debug(hw, I40E_DEBUG_INIT, 3738 "HW Capability: RSS = %d\n", p->rss); 3739 i40e_debug(hw, I40E_DEBUG_INIT, 3740 "HW Capability: RSS table size = %d\n", 3741 p->rss_table_size); 3742 i40e_debug(hw, I40E_DEBUG_INIT, 3743 "HW Capability: RSS table width = %d\n", 3744 p->rss_table_entry_width); 3745 break; 3746 case I40E_AQ_CAP_ID_RXQ: 3747 p->num_rx_qp = number; 3748 p->base_queue = phys_id; 3749 i40e_debug(hw, I40E_DEBUG_INIT, 3750 "HW Capability: Rx QP = %d\n", number); 3751 i40e_debug(hw, I40E_DEBUG_INIT, 3752 "HW Capability: base_queue = %d\n", 3753 p->base_queue); 3754 break; 3755 case I40E_AQ_CAP_ID_TXQ: 3756 p->num_tx_qp = number; 3757 p->base_queue = phys_id; 3758 i40e_debug(hw, I40E_DEBUG_INIT, 3759 "HW Capability: Tx QP = %d\n", number); 3760 i40e_debug(hw, I40E_DEBUG_INIT, 3761 "HW Capability: base_queue = %d\n", 3762 p->base_queue); 3763 break; 3764 case I40E_AQ_CAP_ID_MSIX: 3765 p->num_msix_vectors = number; 3766 i40e_debug(hw, I40E_DEBUG_INIT, 3767 "HW Capability: MSIX vector count = %d\n", 3768 p->num_msix_vectors); 3769 break; 3770 case I40E_AQ_CAP_ID_VF_MSIX: 3771 p->num_msix_vectors_vf = number; 3772 i40e_debug(hw, I40E_DEBUG_INIT, 3773 "HW Capability: MSIX VF vector count = %d\n", 3774 p->num_msix_vectors_vf); 3775 break; 3776 case I40E_AQ_CAP_ID_FLEX10: 3777 if (major_rev == 1) { 3778 if (number == 1) { 3779 p->flex10_enable = TRUE; 3780 p->flex10_capable = TRUE; 3781 } 3782 } else { 3783 /* Capability revision >= 2 */ 3784 if (number & 1) 3785 p->flex10_enable = TRUE; 3786 if (number & 2) 3787 p->flex10_capable = TRUE; 3788 } 3789 p->flex10_mode = logical_id; 3790 p->flex10_status = phys_id; 3791 i40e_debug(hw, I40E_DEBUG_INIT, 3792 "HW Capability: Flex10 mode = %d\n", 3793 p->flex10_mode); 3794 i40e_debug(hw, I40E_DEBUG_INIT, 3795 "HW Capability: Flex10 status = %d\n", 3796 p->flex10_status); 3797 break; 3798 case I40E_AQ_CAP_ID_CEM: 3799 if (number == 1) 3800 p->mgmt_cem = TRUE; 3801 i40e_debug(hw, I40E_DEBUG_INIT, 3802 "HW Capability: CEM = %d\n", p->mgmt_cem); 3803 break; 3804 case I40E_AQ_CAP_ID_IWARP: 3805 if (number == 1) 3806 p->iwarp = TRUE; 3807 i40e_debug(hw, I40E_DEBUG_INIT, 3808 "HW Capability: iWARP = %d\n", p->iwarp); 3809 break; 3810 case I40E_AQ_CAP_ID_LED: 3811 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3812 p->led[phys_id] = TRUE; 3813 i40e_debug(hw, I40E_DEBUG_INIT, 3814 "HW Capability: LED - PIN %d\n", phys_id); 3815 break; 3816 case I40E_AQ_CAP_ID_SDP: 3817 if (phys_id < I40E_HW_CAP_MAX_GPIO) 3818 p->sdp[phys_id] = TRUE; 3819 i40e_debug(hw, I40E_DEBUG_INIT, 3820 "HW Capability: SDP - PIN %d\n", phys_id); 3821 break; 3822 case I40E_AQ_CAP_ID_MDIO: 3823 if (number == 1) { 3824 p->mdio_port_num = phys_id; 3825 p->mdio_port_mode = logical_id; 3826 } 3827 i40e_debug(hw, I40E_DEBUG_INIT, 3828 "HW Capability: MDIO port number = %d\n", 3829 p->mdio_port_num); 3830 i40e_debug(hw, I40E_DEBUG_INIT, 3831 "HW Capability: MDIO port mode = %d\n", 3832 p->mdio_port_mode); 3833 break; 3834 case I40E_AQ_CAP_ID_1588: 3835 if (number == 1) 3836 p->ieee_1588 = TRUE; 3837 i40e_debug(hw, I40E_DEBUG_INIT, 3838 "HW Capability: IEEE 1588 = %d\n", 3839 p->ieee_1588); 3840 break; 3841 case I40E_AQ_CAP_ID_FLOW_DIRECTOR: 3842 p->fd = TRUE; 3843 p->fd_filters_guaranteed = number; 3844 p->fd_filters_best_effort = logical_id; 3845 i40e_debug(hw, I40E_DEBUG_INIT, 3846 "HW Capability: Flow Director = 1\n"); 3847 i40e_debug(hw, I40E_DEBUG_INIT, 3848 "HW Capability: Guaranteed FD filters = %d\n", 3849 p->fd_filters_guaranteed); 3850 break; 3851 case I40E_AQ_CAP_ID_WSR_PROT: 3852 p->wr_csr_prot = (u64)number; 3853 p->wr_csr_prot |= (u64)logical_id << 32; 3854 i40e_debug(hw, I40E_DEBUG_INIT, 3855 "HW Capability: wr_csr_prot = 0x%llX\n\n", 3856 (p->wr_csr_prot & 0xffff)); 3857 break; 3858 case I40E_AQ_CAP_ID_NVM_MGMT: 3859 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED) 3860 p->sec_rev_disabled = TRUE; 3861 if (number & I40E_NVM_MGMT_UPDATE_DISABLED) 3862 p->update_disabled = TRUE; 3863 break; 3864 case I40E_AQ_CAP_ID_WOL_AND_PROXY: 3865 hw->num_wol_proxy_filters = (u16)number; 3866 hw->wol_proxy_vsi_seid = (u16)logical_id; 3867 p->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK; 3868 if (phys_id & I40E_ACPI_PROGRAMMING_METHOD_MASK) 3869 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_AQC_FPK; 3870 else 3871 p->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL; 3872 p->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0; 3873 i40e_debug(hw, I40E_DEBUG_INIT, 3874 "HW Capability: WOL proxy filters = %d\n", 3875 hw->num_wol_proxy_filters); 3876 break; 3877 default: 3878 break; 3879 } 3880 } 3881 3882 if (p->fcoe) 3883 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n"); 3884 3885 /* Always disable FCoE if compiled without the I40E_FCOE_ENA flag */ 3886 p->fcoe = FALSE; 3887 3888 /* count the enabled ports (aka the "not disabled" ports) */ 3889 hw->num_ports = 0; 3890 for (i = 0; i < 4; i++) { 3891 enum i40e_status_code status; 3892 u32 port_cfg_reg = I40E_PRTGEN_STATUS + (4 * i); 3893 u64 port_cfg = 0; 3894 3895 /* use AQ read to get the physical register offset instead 3896 * of the port relative offset 3897 */ 3898 status = i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL); 3899 if ((status == I40E_SUCCESS) && 3900 (port_cfg & I40E_PRTGEN_STATUS_PORT_VALID_MASK)) 3901 hw->num_ports++; 3902 } 3903 3904 /* OCP cards case: if a mezz is removed the ethernet port is at 3905 * disabled state in PRTGEN_CNF register. Additional NVM read is 3906 * needed in order to check if we are dealing with OCP card. 3907 * Those cards have 4 PFs at minimum, so using PRTGEN_CNF for counting 3908 * physical ports results in wrong partition id calculation and thus 3909 * not supporting WoL. 3910 */ 3911 if (hw->mac.type == I40E_MAC_X722) { 3912 if (i40e_acquire_nvm(hw, I40E_RESOURCE_READ) == I40E_SUCCESS) { 3913 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR, 3914 2 * I40E_SR_OCP_CFG_WORD0, 3915 sizeof(ocp_cfg_word0), 3916 &ocp_cfg_word0, TRUE, NULL); 3917 if (status == I40E_SUCCESS && 3918 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED)) 3919 hw->num_ports = 4; 3920 i40e_release_nvm(hw); 3921 } 3922 } 3923 3924 valid_functions = p->valid_functions; 3925 num_functions = 0; 3926 while (valid_functions) { 3927 if (valid_functions & 1) 3928 num_functions++; 3929 valid_functions >>= 1; 3930 } 3931 3932 /* partition id is 1-based, and functions are evenly spread 3933 * across the ports as partitions 3934 */ 3935 if (hw->num_ports != 0) { 3936 hw->partition_id = (hw->pf_id / hw->num_ports) + 1; 3937 hw->num_partitions = num_functions / hw->num_ports; 3938 } 3939 3940 /* additional HW specific goodies that might 3941 * someday be HW version specific 3942 */ 3943 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS; 3944 } 3945 3946 /** 3947 * i40e_aq_discover_capabilities 3948 * @hw: pointer to the hw struct 3949 * @buff: a virtual buffer to hold the capabilities 3950 * @buff_size: Size of the virtual buffer 3951 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM 3952 * @list_type_opc: capabilities type to discover - pass in the command opcode 3953 * @cmd_details: pointer to command details structure or NULL 3954 * 3955 * Get the device capabilities descriptions from the firmware 3956 **/ 3957 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw, 3958 void *buff, u16 buff_size, u16 *data_size, 3959 enum i40e_admin_queue_opc list_type_opc, 3960 struct i40e_asq_cmd_details *cmd_details) 3961 { 3962 struct i40e_aqc_list_capabilites *cmd; 3963 struct i40e_aq_desc desc; 3964 enum i40e_status_code status = I40E_SUCCESS; 3965 3966 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw; 3967 3968 if (list_type_opc != i40e_aqc_opc_list_func_capabilities && 3969 list_type_opc != i40e_aqc_opc_list_dev_capabilities) { 3970 status = I40E_ERR_PARAM; 3971 goto exit; 3972 } 3973 3974 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc); 3975 3976 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 3977 if (buff_size > I40E_AQ_LARGE_BUF) 3978 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3979 3980 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 3981 *data_size = LE16_TO_CPU(desc.datalen); 3982 3983 if (status) 3984 goto exit; 3985 3986 i40e_parse_discover_capabilities(hw, buff, LE32_TO_CPU(cmd->count), 3987 list_type_opc); 3988 3989 exit: 3990 return status; 3991 } 3992 3993 /** 3994 * i40e_aq_update_nvm 3995 * @hw: pointer to the hw struct 3996 * @module_pointer: module pointer location in words from the NVM beginning 3997 * @offset: byte offset from the module beginning 3998 * @length: length of the section to be written (in bytes from the offset) 3999 * @data: command buffer (size [bytes] = length) 4000 * @last_command: tells if this is the last command in a series 4001 * @preservation_flags: Preservation mode flags 4002 * @cmd_details: pointer to command details structure or NULL 4003 * 4004 * Update the NVM using the admin queue commands 4005 **/ 4006 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer, 4007 u32 offset, u16 length, void *data, 4008 bool last_command, u8 preservation_flags, 4009 struct i40e_asq_cmd_details *cmd_details) 4010 { 4011 struct i40e_aq_desc desc; 4012 struct i40e_aqc_nvm_update *cmd = 4013 (struct i40e_aqc_nvm_update *)&desc.params.raw; 4014 enum i40e_status_code status; 4015 4016 DEBUGFUNC("i40e_aq_update_nvm"); 4017 4018 /* In offset the highest byte must be zeroed. */ 4019 if (offset & 0xFF000000) { 4020 status = I40E_ERR_PARAM; 4021 goto i40e_aq_update_nvm_exit; 4022 } 4023 4024 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update); 4025 4026 /* If this is the last command in a series, set the proper flag. */ 4027 if (last_command) 4028 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD; 4029 if (hw->mac.type == I40E_MAC_X722) { 4030 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED) 4031 cmd->command_flags |= 4032 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED << 4033 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4034 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL) 4035 cmd->command_flags |= 4036 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL << 4037 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT); 4038 } 4039 cmd->module_pointer = module_pointer; 4040 cmd->offset = CPU_TO_LE32(offset); 4041 cmd->length = CPU_TO_LE16(length); 4042 4043 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4044 if (length > I40E_AQ_LARGE_BUF) 4045 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4046 4047 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details); 4048 4049 i40e_aq_update_nvm_exit: 4050 return status; 4051 } 4052 4053 /** 4054 * i40e_aq_nvm_progress 4055 * @hw: pointer to the hw struct 4056 * @progress: pointer to progress returned from AQ 4057 * @cmd_details: pointer to command details structure or NULL 4058 * 4059 * Gets progress of flash rearrangement process 4060 **/ 4061 enum i40e_status_code i40e_aq_nvm_progress(struct i40e_hw *hw, u8 *progress, 4062 struct i40e_asq_cmd_details *cmd_details) 4063 { 4064 enum i40e_status_code status; 4065 struct i40e_aq_desc desc; 4066 4067 DEBUGFUNC("i40e_aq_nvm_progress"); 4068 4069 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_progress); 4070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4071 *progress = desc.params.raw[0]; 4072 return status; 4073 } 4074 4075 /** 4076 * i40e_aq_get_lldp_mib 4077 * @hw: pointer to the hw struct 4078 * @bridge_type: type of bridge requested 4079 * @mib_type: Local, Remote or both Local and Remote MIBs 4080 * @buff: pointer to a user supplied buffer to store the MIB block 4081 * @buff_size: size of the buffer (in bytes) 4082 * @local_len : length of the returned Local LLDP MIB 4083 * @remote_len: length of the returned Remote LLDP MIB 4084 * @cmd_details: pointer to command details structure or NULL 4085 * 4086 * Requests the complete LLDP MIB (entire packet). 4087 **/ 4088 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type, 4089 u8 mib_type, void *buff, u16 buff_size, 4090 u16 *local_len, u16 *remote_len, 4091 struct i40e_asq_cmd_details *cmd_details) 4092 { 4093 struct i40e_aq_desc desc; 4094 struct i40e_aqc_lldp_get_mib *cmd = 4095 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4096 struct i40e_aqc_lldp_get_mib *resp = 4097 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw; 4098 enum i40e_status_code status; 4099 4100 if (buff_size == 0 || !buff) 4101 return I40E_ERR_PARAM; 4102 4103 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib); 4104 /* Indirect Command */ 4105 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4106 4107 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK; 4108 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4109 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4110 4111 desc.datalen = CPU_TO_LE16(buff_size); 4112 4113 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4114 if (buff_size > I40E_AQ_LARGE_BUF) 4115 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4116 4117 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4118 if (!status) { 4119 if (local_len != NULL) 4120 *local_len = LE16_TO_CPU(resp->local_len); 4121 if (remote_len != NULL) 4122 *remote_len = LE16_TO_CPU(resp->remote_len); 4123 } 4124 4125 return status; 4126 } 4127 4128 /** 4129 * i40e_aq_set_lldp_mib - Set the LLDP MIB 4130 * @hw: pointer to the hw struct 4131 * @mib_type: Local, Remote or both Local and Remote MIBs 4132 * @buff: pointer to a user supplied buffer to store the MIB block 4133 * @buff_size: size of the buffer (in bytes) 4134 * @cmd_details: pointer to command details structure or NULL 4135 * 4136 * Set the LLDP MIB. 4137 **/ 4138 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw, 4139 u8 mib_type, void *buff, u16 buff_size, 4140 struct i40e_asq_cmd_details *cmd_details) 4141 { 4142 struct i40e_aq_desc desc; 4143 struct i40e_aqc_lldp_set_local_mib *cmd = 4144 (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; 4145 enum i40e_status_code status; 4146 4147 if (buff_size == 0 || !buff) 4148 return I40E_ERR_PARAM; 4149 4150 i40e_fill_default_direct_cmd_desc(&desc, 4151 i40e_aqc_opc_lldp_set_local_mib); 4152 /* Indirect Command */ 4153 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4154 if (buff_size > I40E_AQ_LARGE_BUF) 4155 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4156 desc.datalen = CPU_TO_LE16(buff_size); 4157 4158 cmd->type = mib_type; 4159 cmd->length = CPU_TO_LE16(buff_size); 4160 cmd->address_high = CPU_TO_LE32(I40E_HI_WORD((uintptr_t)buff)); 4161 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)buff)); 4162 4163 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4164 return status; 4165 } 4166 4167 /** 4168 * i40e_aq_cfg_lldp_mib_change_event 4169 * @hw: pointer to the hw struct 4170 * @enable_update: Enable or Disable event posting 4171 * @cmd_details: pointer to command details structure or NULL 4172 * 4173 * Enable or Disable posting of an event on ARQ when LLDP MIB 4174 * associated with the interface changes 4175 **/ 4176 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw, 4177 bool enable_update, 4178 struct i40e_asq_cmd_details *cmd_details) 4179 { 4180 struct i40e_aq_desc desc; 4181 struct i40e_aqc_lldp_update_mib *cmd = 4182 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw; 4183 enum i40e_status_code status; 4184 4185 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib); 4186 4187 if (!enable_update) 4188 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE; 4189 4190 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4191 4192 return status; 4193 } 4194 4195 /** 4196 * i40e_aq_add_lldp_tlv 4197 * @hw: pointer to the hw struct 4198 * @bridge_type: type of bridge 4199 * @buff: buffer with TLV to add 4200 * @buff_size: length of the buffer 4201 * @tlv_len: length of the TLV to be added 4202 * @mib_len: length of the LLDP MIB returned in response 4203 * @cmd_details: pointer to command details structure or NULL 4204 * 4205 * Add the specified TLV to LLDP Local MIB for the given bridge type, 4206 * it is responsibility of the caller to make sure that the TLV is not 4207 * already present in the LLDPDU. 4208 * In return firmware will write the complete LLDP MIB with the newly 4209 * added TLV in the response buffer. 4210 **/ 4211 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type, 4212 void *buff, u16 buff_size, u16 tlv_len, 4213 u16 *mib_len, 4214 struct i40e_asq_cmd_details *cmd_details) 4215 { 4216 struct i40e_aq_desc desc; 4217 struct i40e_aqc_lldp_add_tlv *cmd = 4218 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4219 enum i40e_status_code status; 4220 4221 if (buff_size == 0 || !buff || tlv_len == 0) 4222 return I40E_ERR_PARAM; 4223 4224 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_add_tlv); 4225 4226 /* Indirect Command */ 4227 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4228 if (buff_size > I40E_AQ_LARGE_BUF) 4229 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4230 desc.datalen = CPU_TO_LE16(buff_size); 4231 4232 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4233 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4234 cmd->len = CPU_TO_LE16(tlv_len); 4235 4236 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4237 if (!status) { 4238 if (mib_len != NULL) 4239 *mib_len = LE16_TO_CPU(desc.datalen); 4240 } 4241 4242 return status; 4243 } 4244 4245 /** 4246 * i40e_aq_update_lldp_tlv 4247 * @hw: pointer to the hw struct 4248 * @bridge_type: type of bridge 4249 * @buff: buffer with TLV to update 4250 * @buff_size: size of the buffer holding original and updated TLVs 4251 * @old_len: Length of the Original TLV 4252 * @new_len: Length of the Updated TLV 4253 * @offset: offset of the updated TLV in the buff 4254 * @mib_len: length of the returned LLDP MIB 4255 * @cmd_details: pointer to command details structure or NULL 4256 * 4257 * Update the specified TLV to the LLDP Local MIB for the given bridge type. 4258 * Firmware will place the complete LLDP MIB in response buffer with the 4259 * updated TLV. 4260 **/ 4261 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw, 4262 u8 bridge_type, void *buff, u16 buff_size, 4263 u16 old_len, u16 new_len, u16 offset, 4264 u16 *mib_len, 4265 struct i40e_asq_cmd_details *cmd_details) 4266 { 4267 struct i40e_aq_desc desc; 4268 struct i40e_aqc_lldp_update_tlv *cmd = 4269 (struct i40e_aqc_lldp_update_tlv *)&desc.params.raw; 4270 enum i40e_status_code status; 4271 4272 if (buff_size == 0 || !buff || offset == 0 || 4273 old_len == 0 || new_len == 0) 4274 return I40E_ERR_PARAM; 4275 4276 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_tlv); 4277 4278 /* Indirect Command */ 4279 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4280 if (buff_size > I40E_AQ_LARGE_BUF) 4281 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4282 desc.datalen = CPU_TO_LE16(buff_size); 4283 4284 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4285 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4286 cmd->old_len = CPU_TO_LE16(old_len); 4287 cmd->new_offset = CPU_TO_LE16(offset); 4288 cmd->new_len = CPU_TO_LE16(new_len); 4289 4290 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4291 if (!status) { 4292 if (mib_len != NULL) 4293 *mib_len = LE16_TO_CPU(desc.datalen); 4294 } 4295 4296 return status; 4297 } 4298 4299 /** 4300 * i40e_aq_delete_lldp_tlv 4301 * @hw: pointer to the hw struct 4302 * @bridge_type: type of bridge 4303 * @buff: pointer to a user supplied buffer that has the TLV 4304 * @buff_size: length of the buffer 4305 * @tlv_len: length of the TLV to be deleted 4306 * @mib_len: length of the returned LLDP MIB 4307 * @cmd_details: pointer to command details structure or NULL 4308 * 4309 * Delete the specified TLV from LLDP Local MIB for the given bridge type. 4310 * The firmware places the entire LLDP MIB in the response buffer. 4311 **/ 4312 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw, 4313 u8 bridge_type, void *buff, u16 buff_size, 4314 u16 tlv_len, u16 *mib_len, 4315 struct i40e_asq_cmd_details *cmd_details) 4316 { 4317 struct i40e_aq_desc desc; 4318 struct i40e_aqc_lldp_add_tlv *cmd = 4319 (struct i40e_aqc_lldp_add_tlv *)&desc.params.raw; 4320 enum i40e_status_code status; 4321 4322 if (buff_size == 0 || !buff) 4323 return I40E_ERR_PARAM; 4324 4325 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_delete_tlv); 4326 4327 /* Indirect Command */ 4328 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4329 if (buff_size > I40E_AQ_LARGE_BUF) 4330 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4331 desc.datalen = CPU_TO_LE16(buff_size); 4332 cmd->len = CPU_TO_LE16(tlv_len); 4333 cmd->type = ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) & 4334 I40E_AQ_LLDP_BRIDGE_TYPE_MASK); 4335 4336 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 4337 if (!status) { 4338 if (mib_len != NULL) 4339 *mib_len = LE16_TO_CPU(desc.datalen); 4340 } 4341 4342 return status; 4343 } 4344 4345 /** 4346 * i40e_aq_stop_lldp 4347 * @hw: pointer to the hw struct 4348 * @shutdown_agent: True if LLDP Agent needs to be Shutdown 4349 * @cmd_details: pointer to command details structure or NULL 4350 * 4351 * Stop or Shutdown the embedded LLDP Agent 4352 **/ 4353 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent, 4354 struct i40e_asq_cmd_details *cmd_details) 4355 { 4356 struct i40e_aq_desc desc; 4357 struct i40e_aqc_lldp_stop *cmd = 4358 (struct i40e_aqc_lldp_stop *)&desc.params.raw; 4359 enum i40e_status_code status; 4360 4361 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop); 4362 4363 if (shutdown_agent) 4364 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN; 4365 4366 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4367 4368 return status; 4369 } 4370 4371 /** 4372 * i40e_aq_start_lldp 4373 * @hw: pointer to the hw struct 4374 * @cmd_details: pointer to command details structure or NULL 4375 * 4376 * Start the embedded LLDP Agent on all ports. 4377 **/ 4378 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw, 4379 struct i40e_asq_cmd_details *cmd_details) 4380 { 4381 struct i40e_aq_desc desc; 4382 struct i40e_aqc_lldp_start *cmd = 4383 (struct i40e_aqc_lldp_start *)&desc.params.raw; 4384 enum i40e_status_code status; 4385 4386 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start); 4387 4388 cmd->command = I40E_AQ_LLDP_AGENT_START; 4389 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4390 4391 return status; 4392 } 4393 4394 /** 4395 * i40e_aq_set_dcb_parameters 4396 * @hw: pointer to the hw struct 4397 * @cmd_details: pointer to command details structure or NULL 4398 * @dcb_enable: True if DCB configuration needs to be applied 4399 * 4400 **/ 4401 enum i40e_status_code 4402 i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable, 4403 struct i40e_asq_cmd_details *cmd_details) 4404 { 4405 struct i40e_aq_desc desc; 4406 struct i40e_aqc_set_dcb_parameters *cmd = 4407 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw; 4408 enum i40e_status_code status; 4409 4410 if ((hw->mac.type != I40E_MAC_XL710) || 4411 ((hw->aq.api_maj_ver < 1) || 4412 ((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 6)))) 4413 return I40E_ERR_DEVICE_NOT_SUPPORTED; 4414 4415 i40e_fill_default_direct_cmd_desc(&desc, 4416 i40e_aqc_opc_set_dcb_parameters); 4417 4418 if (dcb_enable) { 4419 cmd->valid_flags = I40E_DCB_VALID; 4420 cmd->command = I40E_AQ_DCB_SET_AGENT; 4421 } 4422 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4423 4424 return status; 4425 } 4426 4427 /** 4428 * i40e_aq_get_cee_dcb_config 4429 * @hw: pointer to the hw struct 4430 * @buff: response buffer that stores CEE operational configuration 4431 * @buff_size: size of the buffer passed 4432 * @cmd_details: pointer to command details structure or NULL 4433 * 4434 * Get CEE DCBX mode operational configuration from firmware 4435 **/ 4436 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw, 4437 void *buff, u16 buff_size, 4438 struct i40e_asq_cmd_details *cmd_details) 4439 { 4440 struct i40e_aq_desc desc; 4441 enum i40e_status_code status; 4442 4443 if (buff_size == 0 || !buff) 4444 return I40E_ERR_PARAM; 4445 4446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg); 4447 4448 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4449 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size, 4450 cmd_details); 4451 4452 return status; 4453 } 4454 4455 /** 4456 * i40e_aq_start_stop_dcbx - Start/Stop DCBx service in FW 4457 * @hw: pointer to the hw struct 4458 * @start_agent: True if DCBx Agent needs to be Started 4459 * False if DCBx Agent needs to be Stopped 4460 * @cmd_details: pointer to command details structure or NULL 4461 * 4462 * Start/Stop the embedded dcbx Agent 4463 **/ 4464 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw, 4465 bool start_agent, 4466 struct i40e_asq_cmd_details *cmd_details) 4467 { 4468 struct i40e_aq_desc desc; 4469 struct i40e_aqc_lldp_stop_start_specific_agent *cmd = 4470 (struct i40e_aqc_lldp_stop_start_specific_agent *) 4471 &desc.params.raw; 4472 enum i40e_status_code status; 4473 4474 i40e_fill_default_direct_cmd_desc(&desc, 4475 i40e_aqc_opc_lldp_stop_start_spec_agent); 4476 4477 if (start_agent) 4478 cmd->command = I40E_AQC_START_SPECIFIC_AGENT_MASK; 4479 4480 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4481 4482 return status; 4483 } 4484 4485 /** 4486 * i40e_aq_add_udp_tunnel 4487 * @hw: pointer to the hw struct 4488 * @udp_port: the UDP port to add 4489 * @header_len: length of the tunneling header length in DWords 4490 * @protocol_index: protocol index type 4491 * @filter_index: pointer to filter index 4492 * @cmd_details: pointer to command details structure or NULL 4493 **/ 4494 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw, 4495 u16 udp_port, u8 protocol_index, 4496 u8 *filter_index, 4497 struct i40e_asq_cmd_details *cmd_details) 4498 { 4499 struct i40e_aq_desc desc; 4500 struct i40e_aqc_add_udp_tunnel *cmd = 4501 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw; 4502 struct i40e_aqc_del_udp_tunnel_completion *resp = 4503 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw; 4504 enum i40e_status_code status; 4505 4506 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel); 4507 4508 cmd->udp_port = CPU_TO_LE16(udp_port); 4509 cmd->protocol_type = protocol_index; 4510 4511 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4512 4513 if (!status && filter_index) 4514 *filter_index = resp->index; 4515 4516 return status; 4517 } 4518 4519 /** 4520 * i40e_aq_del_udp_tunnel 4521 * @hw: pointer to the hw struct 4522 * @index: filter index 4523 * @cmd_details: pointer to command details structure or NULL 4524 **/ 4525 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index, 4526 struct i40e_asq_cmd_details *cmd_details) 4527 { 4528 struct i40e_aq_desc desc; 4529 struct i40e_aqc_remove_udp_tunnel *cmd = 4530 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw; 4531 enum i40e_status_code status; 4532 4533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel); 4534 4535 cmd->index = index; 4536 4537 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4538 4539 return status; 4540 } 4541 4542 /** 4543 * i40e_aq_get_switch_resource_alloc (0x0204) 4544 * @hw: pointer to the hw struct 4545 * @num_entries: pointer to u8 to store the number of resource entries returned 4546 * @buf: pointer to a user supplied buffer. This buffer must be large enough 4547 * to store the resource information for all resource types. Each 4548 * resource type is a i40e_aqc_switch_resource_alloc_data structure. 4549 * @count: size, in bytes, of the buffer provided 4550 * @cmd_details: pointer to command details structure or NULL 4551 * 4552 * Query the resources allocated to a function. 4553 **/ 4554 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw, 4555 u8 *num_entries, 4556 struct i40e_aqc_switch_resource_alloc_element_resp *buf, 4557 u16 count, 4558 struct i40e_asq_cmd_details *cmd_details) 4559 { 4560 struct i40e_aq_desc desc; 4561 struct i40e_aqc_get_switch_resource_alloc *cmd_resp = 4562 (struct i40e_aqc_get_switch_resource_alloc *)&desc.params.raw; 4563 enum i40e_status_code status; 4564 u16 length = count * sizeof(*buf); 4565 4566 i40e_fill_default_direct_cmd_desc(&desc, 4567 i40e_aqc_opc_get_switch_resource_alloc); 4568 4569 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 4570 if (length > I40E_AQ_LARGE_BUF) 4571 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4572 4573 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4574 4575 if (!status && num_entries) 4576 *num_entries = cmd_resp->num_entries; 4577 4578 return status; 4579 } 4580 4581 /** 4582 * i40e_aq_delete_element - Delete switch element 4583 * @hw: pointer to the hw struct 4584 * @seid: the SEID to delete from the switch 4585 * @cmd_details: pointer to command details structure or NULL 4586 * 4587 * This deletes a switch element from the switch. 4588 **/ 4589 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid, 4590 struct i40e_asq_cmd_details *cmd_details) 4591 { 4592 struct i40e_aq_desc desc; 4593 struct i40e_aqc_switch_seid *cmd = 4594 (struct i40e_aqc_switch_seid *)&desc.params.raw; 4595 enum i40e_status_code status; 4596 4597 if (seid == 0) 4598 return I40E_ERR_PARAM; 4599 4600 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element); 4601 4602 cmd->seid = CPU_TO_LE16(seid); 4603 4604 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4605 4606 return status; 4607 } 4608 4609 /** 4610 * i40e_aq_add_pvirt - Instantiate a Port Virtualizer on a port 4611 * @hw: pointer to the hw struct 4612 * @flags: component flags 4613 * @mac_seid: uplink seid (MAC SEID) 4614 * @vsi_seid: connected vsi seid 4615 * @ret_seid: seid of create pv component 4616 * 4617 * This instantiates an i40e port virtualizer with specified flags. 4618 * Depending on specified flags the port virtualizer can act as a 4619 * 802.1Qbr port virtualizer or a 802.1Qbg S-component. 4620 */ 4621 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags, 4622 u16 mac_seid, u16 vsi_seid, 4623 u16 *ret_seid) 4624 { 4625 struct i40e_aq_desc desc; 4626 struct i40e_aqc_add_update_pv *cmd = 4627 (struct i40e_aqc_add_update_pv *)&desc.params.raw; 4628 struct i40e_aqc_add_update_pv_completion *resp = 4629 (struct i40e_aqc_add_update_pv_completion *)&desc.params.raw; 4630 enum i40e_status_code status; 4631 4632 if (vsi_seid == 0) 4633 return I40E_ERR_PARAM; 4634 4635 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_pv); 4636 cmd->command_flags = CPU_TO_LE16(flags); 4637 cmd->uplink_seid = CPU_TO_LE16(mac_seid); 4638 cmd->connected_seid = CPU_TO_LE16(vsi_seid); 4639 4640 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 4641 if (!status && ret_seid) 4642 *ret_seid = LE16_TO_CPU(resp->pv_seid); 4643 4644 return status; 4645 } 4646 4647 /** 4648 * i40e_aq_add_tag - Add an S/E-tag 4649 * @hw: pointer to the hw struct 4650 * @direct_to_queue: should s-tag direct flow to a specific queue 4651 * @vsi_seid: VSI SEID to use this tag 4652 * @tag: value of the tag 4653 * @queue_num: queue number, only valid is direct_to_queue is TRUE 4654 * @tags_used: return value, number of tags in use by this PF 4655 * @tags_free: return value, number of unallocated tags 4656 * @cmd_details: pointer to command details structure or NULL 4657 * 4658 * This associates an S- or E-tag to a VSI in the switch complex. It returns 4659 * the number of tags allocated by the PF, and the number of unallocated 4660 * tags available. 4661 **/ 4662 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue, 4663 u16 vsi_seid, u16 tag, u16 queue_num, 4664 u16 *tags_used, u16 *tags_free, 4665 struct i40e_asq_cmd_details *cmd_details) 4666 { 4667 struct i40e_aq_desc desc; 4668 struct i40e_aqc_add_tag *cmd = 4669 (struct i40e_aqc_add_tag *)&desc.params.raw; 4670 struct i40e_aqc_add_remove_tag_completion *resp = 4671 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4672 enum i40e_status_code status; 4673 4674 if (vsi_seid == 0) 4675 return I40E_ERR_PARAM; 4676 4677 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_tag); 4678 4679 cmd->seid = CPU_TO_LE16(vsi_seid); 4680 cmd->tag = CPU_TO_LE16(tag); 4681 if (direct_to_queue) { 4682 cmd->flags = CPU_TO_LE16(I40E_AQC_ADD_TAG_FLAG_TO_QUEUE); 4683 cmd->queue_number = CPU_TO_LE16(queue_num); 4684 } 4685 4686 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4687 4688 if (!status) { 4689 if (tags_used != NULL) 4690 *tags_used = LE16_TO_CPU(resp->tags_used); 4691 if (tags_free != NULL) 4692 *tags_free = LE16_TO_CPU(resp->tags_free); 4693 } 4694 4695 return status; 4696 } 4697 4698 /** 4699 * i40e_aq_remove_tag - Remove an S- or E-tag 4700 * @hw: pointer to the hw struct 4701 * @vsi_seid: VSI SEID this tag is associated with 4702 * @tag: value of the S-tag to delete 4703 * @tags_used: return value, number of tags in use by this PF 4704 * @tags_free: return value, number of unallocated tags 4705 * @cmd_details: pointer to command details structure or NULL 4706 * 4707 * This deletes an S- or E-tag from a VSI in the switch complex. It returns 4708 * the number of tags allocated by the PF, and the number of unallocated 4709 * tags available. 4710 **/ 4711 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid, 4712 u16 tag, u16 *tags_used, u16 *tags_free, 4713 struct i40e_asq_cmd_details *cmd_details) 4714 { 4715 struct i40e_aq_desc desc; 4716 struct i40e_aqc_remove_tag *cmd = 4717 (struct i40e_aqc_remove_tag *)&desc.params.raw; 4718 struct i40e_aqc_add_remove_tag_completion *resp = 4719 (struct i40e_aqc_add_remove_tag_completion *)&desc.params.raw; 4720 enum i40e_status_code status; 4721 4722 if (vsi_seid == 0) 4723 return I40E_ERR_PARAM; 4724 4725 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_tag); 4726 4727 cmd->seid = CPU_TO_LE16(vsi_seid); 4728 cmd->tag = CPU_TO_LE16(tag); 4729 4730 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4731 4732 if (!status) { 4733 if (tags_used != NULL) 4734 *tags_used = LE16_TO_CPU(resp->tags_used); 4735 if (tags_free != NULL) 4736 *tags_free = LE16_TO_CPU(resp->tags_free); 4737 } 4738 4739 return status; 4740 } 4741 4742 /** 4743 * i40e_aq_add_mcast_etag - Add a multicast E-tag 4744 * @hw: pointer to the hw struct 4745 * @pv_seid: Port Virtualizer of this SEID to associate E-tag with 4746 * @etag: value of E-tag to add 4747 * @num_tags_in_buf: number of unicast E-tags in indirect buffer 4748 * @buf: address of indirect buffer 4749 * @tags_used: return value, number of E-tags in use by this port 4750 * @tags_free: return value, number of unallocated M-tags 4751 * @cmd_details: pointer to command details structure or NULL 4752 * 4753 * This associates a multicast E-tag to a port virtualizer. It will return 4754 * the number of tags allocated by the PF, and the number of unallocated 4755 * tags available. 4756 * 4757 * The indirect buffer pointed to by buf is a list of 2-byte E-tags, 4758 * num_tags_in_buf long. 4759 **/ 4760 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4761 u16 etag, u8 num_tags_in_buf, void *buf, 4762 u16 *tags_used, u16 *tags_free, 4763 struct i40e_asq_cmd_details *cmd_details) 4764 { 4765 struct i40e_aq_desc desc; 4766 struct i40e_aqc_add_remove_mcast_etag *cmd = 4767 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4768 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4769 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4770 enum i40e_status_code status; 4771 u16 length = sizeof(u16) * num_tags_in_buf; 4772 4773 if ((pv_seid == 0) || (buf == NULL) || (num_tags_in_buf == 0)) 4774 return I40E_ERR_PARAM; 4775 4776 i40e_fill_default_direct_cmd_desc(&desc, 4777 i40e_aqc_opc_add_multicast_etag); 4778 4779 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4780 cmd->etag = CPU_TO_LE16(etag); 4781 cmd->num_unicast_etags = num_tags_in_buf; 4782 4783 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 4784 if (length > I40E_AQ_LARGE_BUF) 4785 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 4786 4787 status = i40e_asq_send_command(hw, &desc, buf, length, cmd_details); 4788 4789 if (!status) { 4790 if (tags_used != NULL) 4791 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4792 if (tags_free != NULL) 4793 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4794 } 4795 4796 return status; 4797 } 4798 4799 /** 4800 * i40e_aq_remove_mcast_etag - Remove a multicast E-tag 4801 * @hw: pointer to the hw struct 4802 * @pv_seid: Port Virtualizer SEID this M-tag is associated with 4803 * @etag: value of the E-tag to remove 4804 * @tags_used: return value, number of tags in use by this port 4805 * @tags_free: return value, number of unallocated tags 4806 * @cmd_details: pointer to command details structure or NULL 4807 * 4808 * This deletes an E-tag from the port virtualizer. It will return 4809 * the number of tags allocated by the port, and the number of unallocated 4810 * tags available. 4811 **/ 4812 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pv_seid, 4813 u16 etag, u16 *tags_used, u16 *tags_free, 4814 struct i40e_asq_cmd_details *cmd_details) 4815 { 4816 struct i40e_aq_desc desc; 4817 struct i40e_aqc_add_remove_mcast_etag *cmd = 4818 (struct i40e_aqc_add_remove_mcast_etag *)&desc.params.raw; 4819 struct i40e_aqc_add_remove_mcast_etag_completion *resp = 4820 (struct i40e_aqc_add_remove_mcast_etag_completion *)&desc.params.raw; 4821 enum i40e_status_code status; 4822 4823 4824 if (pv_seid == 0) 4825 return I40E_ERR_PARAM; 4826 4827 i40e_fill_default_direct_cmd_desc(&desc, 4828 i40e_aqc_opc_remove_multicast_etag); 4829 4830 cmd->pv_seid = CPU_TO_LE16(pv_seid); 4831 cmd->etag = CPU_TO_LE16(etag); 4832 4833 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4834 4835 if (!status) { 4836 if (tags_used != NULL) 4837 *tags_used = LE16_TO_CPU(resp->mcast_etags_used); 4838 if (tags_free != NULL) 4839 *tags_free = LE16_TO_CPU(resp->mcast_etags_free); 4840 } 4841 4842 return status; 4843 } 4844 4845 /** 4846 * i40e_aq_update_tag - Update an S/E-tag 4847 * @hw: pointer to the hw struct 4848 * @vsi_seid: VSI SEID using this S-tag 4849 * @old_tag: old tag value 4850 * @new_tag: new tag value 4851 * @tags_used: return value, number of tags in use by this PF 4852 * @tags_free: return value, number of unallocated tags 4853 * @cmd_details: pointer to command details structure or NULL 4854 * 4855 * This updates the value of the tag currently attached to this VSI 4856 * in the switch complex. It will return the number of tags allocated 4857 * by the PF, and the number of unallocated tags available. 4858 **/ 4859 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid, 4860 u16 old_tag, u16 new_tag, u16 *tags_used, 4861 u16 *tags_free, 4862 struct i40e_asq_cmd_details *cmd_details) 4863 { 4864 struct i40e_aq_desc desc; 4865 struct i40e_aqc_update_tag *cmd = 4866 (struct i40e_aqc_update_tag *)&desc.params.raw; 4867 struct i40e_aqc_update_tag_completion *resp = 4868 (struct i40e_aqc_update_tag_completion *)&desc.params.raw; 4869 enum i40e_status_code status; 4870 4871 if (vsi_seid == 0) 4872 return I40E_ERR_PARAM; 4873 4874 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_update_tag); 4875 4876 cmd->seid = CPU_TO_LE16(vsi_seid); 4877 cmd->old_tag = CPU_TO_LE16(old_tag); 4878 cmd->new_tag = CPU_TO_LE16(new_tag); 4879 4880 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4881 4882 if (!status) { 4883 if (tags_used != NULL) 4884 *tags_used = LE16_TO_CPU(resp->tags_used); 4885 if (tags_free != NULL) 4886 *tags_free = LE16_TO_CPU(resp->tags_free); 4887 } 4888 4889 return status; 4890 } 4891 4892 /** 4893 * i40e_aq_dcb_ignore_pfc - Ignore PFC for given TCs 4894 * @hw: pointer to the hw struct 4895 * @tcmap: TC map for request/release any ignore PFC condition 4896 * @request: request or release ignore PFC condition 4897 * @tcmap_ret: return TCs for which PFC is currently ignored 4898 * @cmd_details: pointer to command details structure or NULL 4899 * 4900 * This sends out request/release to ignore PFC condition for a TC. 4901 * It will return the TCs for which PFC is currently ignored. 4902 **/ 4903 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw, u8 tcmap, 4904 bool request, u8 *tcmap_ret, 4905 struct i40e_asq_cmd_details *cmd_details) 4906 { 4907 struct i40e_aq_desc desc; 4908 struct i40e_aqc_pfc_ignore *cmd_resp = 4909 (struct i40e_aqc_pfc_ignore *)&desc.params.raw; 4910 enum i40e_status_code status; 4911 4912 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_ignore_pfc); 4913 4914 if (request) 4915 cmd_resp->command_flags = I40E_AQC_PFC_IGNORE_SET; 4916 4917 cmd_resp->tc_bitmap = tcmap; 4918 4919 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4920 4921 if (!status) { 4922 if (tcmap_ret != NULL) 4923 *tcmap_ret = cmd_resp->tc_bitmap; 4924 } 4925 4926 return status; 4927 } 4928 4929 /** 4930 * i40e_aq_dcb_updated - DCB Updated Command 4931 * @hw: pointer to the hw struct 4932 * @cmd_details: pointer to command details structure or NULL 4933 * 4934 * When LLDP is handled in PF this command is used by the PF 4935 * to notify EMP that a DCB setting is modified. 4936 * When LLDP is handled in EMP this command is used by the PF 4937 * to notify EMP whenever one of the following parameters get 4938 * modified: 4939 * - PFCLinkDelayAllowance in PRTDCB_GENC.PFCLDA 4940 * - PCIRTT in PRTDCB_GENC.PCIRTT 4941 * - Maximum Frame Size for non-FCoE TCs set by PRTDCB_TDPUC.MAX_TXFRAME. 4942 * EMP will return when the shared RPB settings have been 4943 * recomputed and modified. The retval field in the descriptor 4944 * will be set to 0 when RPB is modified. 4945 **/ 4946 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw, 4947 struct i40e_asq_cmd_details *cmd_details) 4948 { 4949 struct i40e_aq_desc desc; 4950 enum i40e_status_code status; 4951 4952 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated); 4953 4954 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4955 4956 return status; 4957 } 4958 4959 /** 4960 * i40e_aq_add_statistics - Add a statistics block to a VLAN in a switch. 4961 * @hw: pointer to the hw struct 4962 * @seid: defines the SEID of the switch for which the stats are requested 4963 * @vlan_id: the VLAN ID for which the statistics are requested 4964 * @stat_index: index of the statistics counters block assigned to this VLAN 4965 * @cmd_details: pointer to command details structure or NULL 4966 * 4967 * XL710 supports 128 smonVlanStats counters.This command is used to 4968 * allocate a set of smonVlanStats counters to a specific VLAN in a specific 4969 * switch. 4970 **/ 4971 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid, 4972 u16 vlan_id, u16 *stat_index, 4973 struct i40e_asq_cmd_details *cmd_details) 4974 { 4975 struct i40e_aq_desc desc; 4976 struct i40e_aqc_add_remove_statistics *cmd_resp = 4977 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 4978 enum i40e_status_code status; 4979 4980 if ((seid == 0) || (stat_index == NULL)) 4981 return I40E_ERR_PARAM; 4982 4983 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_statistics); 4984 4985 cmd_resp->seid = CPU_TO_LE16(seid); 4986 cmd_resp->vlan = CPU_TO_LE16(vlan_id); 4987 4988 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 4989 4990 if (!status && stat_index) 4991 *stat_index = LE16_TO_CPU(cmd_resp->stat_index); 4992 4993 return status; 4994 } 4995 4996 /** 4997 * i40e_aq_remove_statistics - Remove a statistics block to a VLAN in a switch. 4998 * @hw: pointer to the hw struct 4999 * @seid: defines the SEID of the switch for which the stats are requested 5000 * @vlan_id: the VLAN ID for which the statistics are requested 5001 * @stat_index: index of the statistics counters block assigned to this VLAN 5002 * @cmd_details: pointer to command details structure or NULL 5003 * 5004 * XL710 supports 128 smonVlanStats counters.This command is used to 5005 * deallocate a set of smonVlanStats counters to a specific VLAN in a specific 5006 * switch. 5007 **/ 5008 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid, 5009 u16 vlan_id, u16 stat_index, 5010 struct i40e_asq_cmd_details *cmd_details) 5011 { 5012 struct i40e_aq_desc desc; 5013 struct i40e_aqc_add_remove_statistics *cmd = 5014 (struct i40e_aqc_add_remove_statistics *)&desc.params.raw; 5015 enum i40e_status_code status; 5016 5017 if (seid == 0) 5018 return I40E_ERR_PARAM; 5019 5020 i40e_fill_default_direct_cmd_desc(&desc, 5021 i40e_aqc_opc_remove_statistics); 5022 5023 cmd->seid = CPU_TO_LE16(seid); 5024 cmd->vlan = CPU_TO_LE16(vlan_id); 5025 cmd->stat_index = CPU_TO_LE16(stat_index); 5026 5027 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5028 5029 return status; 5030 } 5031 5032 /** 5033 * i40e_aq_set_port_parameters - set physical port parameters. 5034 * @hw: pointer to the hw struct 5035 * @bad_frame_vsi: defines the VSI to which bad frames are forwarded 5036 * @save_bad_pac: if set packets with errors are forwarded to the bad frames VSI 5037 * @pad_short_pac: if set transmit packets smaller than 60 bytes are padded 5038 * @double_vlan: if set double VLAN is enabled 5039 * @cmd_details: pointer to command details structure or NULL 5040 **/ 5041 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw, 5042 u16 bad_frame_vsi, bool save_bad_pac, 5043 bool pad_short_pac, bool double_vlan, 5044 struct i40e_asq_cmd_details *cmd_details) 5045 { 5046 struct i40e_aqc_set_port_parameters *cmd; 5047 enum i40e_status_code status; 5048 struct i40e_aq_desc desc; 5049 u16 command_flags = 0; 5050 5051 cmd = (struct i40e_aqc_set_port_parameters *)&desc.params.raw; 5052 5053 i40e_fill_default_direct_cmd_desc(&desc, 5054 i40e_aqc_opc_set_port_parameters); 5055 5056 cmd->bad_frame_vsi = CPU_TO_LE16(bad_frame_vsi); 5057 if (save_bad_pac) 5058 command_flags |= I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS; 5059 if (pad_short_pac) 5060 command_flags |= I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS; 5061 if (double_vlan) 5062 command_flags |= I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA; 5063 cmd->command_flags = CPU_TO_LE16(command_flags); 5064 5065 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5066 5067 return status; 5068 } 5069 5070 /** 5071 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler 5072 * @hw: pointer to the hw struct 5073 * @seid: seid for the physical port/switching component/vsi 5074 * @buff: Indirect buffer to hold data parameters and response 5075 * @buff_size: Indirect buffer size 5076 * @opcode: Tx scheduler AQ command opcode 5077 * @cmd_details: pointer to command details structure or NULL 5078 * 5079 * Generic command handler for Tx scheduler AQ commands 5080 **/ 5081 static enum i40e_status_code i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid, 5082 void *buff, u16 buff_size, 5083 enum i40e_admin_queue_opc opcode, 5084 struct i40e_asq_cmd_details *cmd_details) 5085 { 5086 struct i40e_aq_desc desc; 5087 struct i40e_aqc_tx_sched_ind *cmd = 5088 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; 5089 enum i40e_status_code status; 5090 bool cmd_param_flag = FALSE; 5091 5092 switch (opcode) { 5093 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit: 5094 case i40e_aqc_opc_configure_vsi_tc_bw: 5095 case i40e_aqc_opc_enable_switching_comp_ets: 5096 case i40e_aqc_opc_modify_switching_comp_ets: 5097 case i40e_aqc_opc_disable_switching_comp_ets: 5098 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit: 5099 case i40e_aqc_opc_configure_switching_comp_bw_config: 5100 cmd_param_flag = TRUE; 5101 break; 5102 case i40e_aqc_opc_query_vsi_bw_config: 5103 case i40e_aqc_opc_query_vsi_ets_sla_config: 5104 case i40e_aqc_opc_query_switching_comp_ets_config: 5105 case i40e_aqc_opc_query_port_ets_config: 5106 case i40e_aqc_opc_query_switching_comp_bw_config: 5107 cmd_param_flag = FALSE; 5108 break; 5109 default: 5110 return I40E_ERR_PARAM; 5111 } 5112 5113 i40e_fill_default_direct_cmd_desc(&desc, opcode); 5114 5115 /* Indirect command */ 5116 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 5117 if (cmd_param_flag) 5118 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 5119 if (buff_size > I40E_AQ_LARGE_BUF) 5120 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5121 5122 desc.datalen = CPU_TO_LE16(buff_size); 5123 5124 cmd->vsi_seid = CPU_TO_LE16(seid); 5125 5126 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 5127 5128 return status; 5129 } 5130 5131 /** 5132 * i40e_aq_config_vsi_bw_limit - Configure VSI BW Limit 5133 * @hw: pointer to the hw struct 5134 * @seid: VSI seid 5135 * @credit: BW limit credits (0 = disabled) 5136 * @max_credit: Max BW limit credits 5137 * @cmd_details: pointer to command details structure or NULL 5138 **/ 5139 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw, 5140 u16 seid, u16 credit, u8 max_credit, 5141 struct i40e_asq_cmd_details *cmd_details) 5142 { 5143 struct i40e_aq_desc desc; 5144 struct i40e_aqc_configure_vsi_bw_limit *cmd = 5145 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw; 5146 enum i40e_status_code status; 5147 5148 i40e_fill_default_direct_cmd_desc(&desc, 5149 i40e_aqc_opc_configure_vsi_bw_limit); 5150 5151 cmd->vsi_seid = CPU_TO_LE16(seid); 5152 cmd->credit = CPU_TO_LE16(credit); 5153 cmd->max_credit = max_credit; 5154 5155 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5156 5157 return status; 5158 } 5159 5160 /** 5161 * i40e_aq_config_switch_comp_bw_limit - Configure Switching component BW Limit 5162 * @hw: pointer to the hw struct 5163 * @seid: switching component seid 5164 * @credit: BW limit credits (0 = disabled) 5165 * @max_bw: Max BW limit credits 5166 * @cmd_details: pointer to command details structure or NULL 5167 **/ 5168 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw, 5169 u16 seid, u16 credit, u8 max_bw, 5170 struct i40e_asq_cmd_details *cmd_details) 5171 { 5172 struct i40e_aq_desc desc; 5173 struct i40e_aqc_configure_switching_comp_bw_limit *cmd = 5174 (struct i40e_aqc_configure_switching_comp_bw_limit *)&desc.params.raw; 5175 enum i40e_status_code status; 5176 5177 i40e_fill_default_direct_cmd_desc(&desc, 5178 i40e_aqc_opc_configure_switching_comp_bw_limit); 5179 5180 cmd->seid = CPU_TO_LE16(seid); 5181 cmd->credit = CPU_TO_LE16(credit); 5182 cmd->max_bw = max_bw; 5183 5184 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5185 5186 return status; 5187 } 5188 5189 /** 5190 * i40e_aq_config_vsi_ets_sla_bw_limit - Config VSI BW Limit per TC 5191 * @hw: pointer to the hw struct 5192 * @seid: VSI seid 5193 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5194 * @cmd_details: pointer to command details structure or NULL 5195 **/ 5196 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw, 5197 u16 seid, 5198 struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data, 5199 struct i40e_asq_cmd_details *cmd_details) 5200 { 5201 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5202 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit, 5203 cmd_details); 5204 } 5205 5206 /** 5207 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC 5208 * @hw: pointer to the hw struct 5209 * @seid: VSI seid 5210 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits 5211 * @cmd_details: pointer to command details structure or NULL 5212 **/ 5213 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, 5214 u16 seid, 5215 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data, 5216 struct i40e_asq_cmd_details *cmd_details) 5217 { 5218 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5219 i40e_aqc_opc_configure_vsi_tc_bw, 5220 cmd_details); 5221 } 5222 5223 /** 5224 * i40e_aq_config_switch_comp_ets_bw_limit - Config Switch comp BW Limit per TC 5225 * @hw: pointer to the hw struct 5226 * @seid: seid of the switching component 5227 * @bw_data: Buffer holding enabled TCs, per TC BW limit/credits 5228 * @cmd_details: pointer to command details structure or NULL 5229 **/ 5230 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit( 5231 struct i40e_hw *hw, u16 seid, 5232 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data, 5233 struct i40e_asq_cmd_details *cmd_details) 5234 { 5235 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5236 i40e_aqc_opc_configure_switching_comp_ets_bw_limit, 5237 cmd_details); 5238 } 5239 5240 /** 5241 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration 5242 * @hw: pointer to the hw struct 5243 * @seid: seid of the VSI 5244 * @bw_data: Buffer to hold VSI BW configuration 5245 * @cmd_details: pointer to command details structure or NULL 5246 **/ 5247 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw, 5248 u16 seid, 5249 struct i40e_aqc_query_vsi_bw_config_resp *bw_data, 5250 struct i40e_asq_cmd_details *cmd_details) 5251 { 5252 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5253 i40e_aqc_opc_query_vsi_bw_config, 5254 cmd_details); 5255 } 5256 5257 /** 5258 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC 5259 * @hw: pointer to the hw struct 5260 * @seid: seid of the VSI 5261 * @bw_data: Buffer to hold VSI BW configuration per TC 5262 * @cmd_details: pointer to command details structure or NULL 5263 **/ 5264 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw, 5265 u16 seid, 5266 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data, 5267 struct i40e_asq_cmd_details *cmd_details) 5268 { 5269 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5270 i40e_aqc_opc_query_vsi_ets_sla_config, 5271 cmd_details); 5272 } 5273 5274 /** 5275 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC 5276 * @hw: pointer to the hw struct 5277 * @seid: seid of the switching component 5278 * @bw_data: Buffer to hold switching component's per TC BW config 5279 * @cmd_details: pointer to command details structure or NULL 5280 **/ 5281 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw, 5282 u16 seid, 5283 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data, 5284 struct i40e_asq_cmd_details *cmd_details) 5285 { 5286 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5287 i40e_aqc_opc_query_switching_comp_ets_config, 5288 cmd_details); 5289 } 5290 5291 /** 5292 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration 5293 * @hw: pointer to the hw struct 5294 * @seid: seid of the VSI or switching component connected to Physical Port 5295 * @bw_data: Buffer to hold current ETS configuration for the Physical Port 5296 * @cmd_details: pointer to command details structure or NULL 5297 **/ 5298 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw, 5299 u16 seid, 5300 struct i40e_aqc_query_port_ets_config_resp *bw_data, 5301 struct i40e_asq_cmd_details *cmd_details) 5302 { 5303 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5304 i40e_aqc_opc_query_port_ets_config, 5305 cmd_details); 5306 } 5307 5308 /** 5309 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration 5310 * @hw: pointer to the hw struct 5311 * @seid: seid of the switching component 5312 * @bw_data: Buffer to hold switching component's BW configuration 5313 * @cmd_details: pointer to command details structure or NULL 5314 **/ 5315 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw, 5316 u16 seid, 5317 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data, 5318 struct i40e_asq_cmd_details *cmd_details) 5319 { 5320 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data), 5321 i40e_aqc_opc_query_switching_comp_bw_config, 5322 cmd_details); 5323 } 5324 5325 /** 5326 * i40e_validate_filter_settings 5327 * @hw: pointer to the hardware structure 5328 * @settings: Filter control settings 5329 * 5330 * Check and validate the filter control settings passed. 5331 * The function checks for the valid filter/context sizes being 5332 * passed for FCoE and PE. 5333 * 5334 * Returns I40E_SUCCESS if the values passed are valid and within 5335 * range else returns an error. 5336 **/ 5337 static enum i40e_status_code i40e_validate_filter_settings(struct i40e_hw *hw, 5338 struct i40e_filter_control_settings *settings) 5339 { 5340 u32 fcoe_cntx_size, fcoe_filt_size; 5341 u32 pe_cntx_size, pe_filt_size; 5342 u32 fcoe_fmax; 5343 5344 u32 val; 5345 5346 /* Validate FCoE settings passed */ 5347 switch (settings->fcoe_filt_num) { 5348 case I40E_HASH_FILTER_SIZE_1K: 5349 case I40E_HASH_FILTER_SIZE_2K: 5350 case I40E_HASH_FILTER_SIZE_4K: 5351 case I40E_HASH_FILTER_SIZE_8K: 5352 case I40E_HASH_FILTER_SIZE_16K: 5353 case I40E_HASH_FILTER_SIZE_32K: 5354 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5355 fcoe_filt_size <<= (u32)settings->fcoe_filt_num; 5356 break; 5357 default: 5358 return I40E_ERR_PARAM; 5359 } 5360 5361 switch (settings->fcoe_cntx_num) { 5362 case I40E_DMA_CNTX_SIZE_512: 5363 case I40E_DMA_CNTX_SIZE_1K: 5364 case I40E_DMA_CNTX_SIZE_2K: 5365 case I40E_DMA_CNTX_SIZE_4K: 5366 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5367 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num; 5368 break; 5369 default: 5370 return I40E_ERR_PARAM; 5371 } 5372 5373 /* Validate PE settings passed */ 5374 switch (settings->pe_filt_num) { 5375 case I40E_HASH_FILTER_SIZE_1K: 5376 case I40E_HASH_FILTER_SIZE_2K: 5377 case I40E_HASH_FILTER_SIZE_4K: 5378 case I40E_HASH_FILTER_SIZE_8K: 5379 case I40E_HASH_FILTER_SIZE_16K: 5380 case I40E_HASH_FILTER_SIZE_32K: 5381 case I40E_HASH_FILTER_SIZE_64K: 5382 case I40E_HASH_FILTER_SIZE_128K: 5383 case I40E_HASH_FILTER_SIZE_256K: 5384 case I40E_HASH_FILTER_SIZE_512K: 5385 case I40E_HASH_FILTER_SIZE_1M: 5386 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE; 5387 pe_filt_size <<= (u32)settings->pe_filt_num; 5388 break; 5389 default: 5390 return I40E_ERR_PARAM; 5391 } 5392 5393 switch (settings->pe_cntx_num) { 5394 case I40E_DMA_CNTX_SIZE_512: 5395 case I40E_DMA_CNTX_SIZE_1K: 5396 case I40E_DMA_CNTX_SIZE_2K: 5397 case I40E_DMA_CNTX_SIZE_4K: 5398 case I40E_DMA_CNTX_SIZE_8K: 5399 case I40E_DMA_CNTX_SIZE_16K: 5400 case I40E_DMA_CNTX_SIZE_32K: 5401 case I40E_DMA_CNTX_SIZE_64K: 5402 case I40E_DMA_CNTX_SIZE_128K: 5403 case I40E_DMA_CNTX_SIZE_256K: 5404 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE; 5405 pe_cntx_size <<= (u32)settings->pe_cntx_num; 5406 break; 5407 default: 5408 return I40E_ERR_PARAM; 5409 } 5410 5411 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */ 5412 val = rd32(hw, I40E_GLHMC_FCOEFMAX); 5413 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK) 5414 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT; 5415 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax) 5416 return I40E_ERR_INVALID_SIZE; 5417 5418 return I40E_SUCCESS; 5419 } 5420 5421 /** 5422 * i40e_set_filter_control 5423 * @hw: pointer to the hardware structure 5424 * @settings: Filter control settings 5425 * 5426 * Set the Queue Filters for PE/FCoE and enable filters required 5427 * for a single PF. It is expected that these settings are programmed 5428 * at the driver initialization time. 5429 **/ 5430 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw, 5431 struct i40e_filter_control_settings *settings) 5432 { 5433 enum i40e_status_code ret = I40E_SUCCESS; 5434 u32 hash_lut_size = 0; 5435 u32 val; 5436 5437 if (!settings) 5438 return I40E_ERR_PARAM; 5439 5440 /* Validate the input settings */ 5441 ret = i40e_validate_filter_settings(hw, settings); 5442 if (ret) 5443 return ret; 5444 5445 /* Read the PF Queue Filter control register */ 5446 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); 5447 5448 /* Program required PE hash buckets for the PF */ 5449 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK; 5450 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) & 5451 I40E_PFQF_CTL_0_PEHSIZE_MASK; 5452 /* Program required PE contexts for the PF */ 5453 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK; 5454 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) & 5455 I40E_PFQF_CTL_0_PEDSIZE_MASK; 5456 5457 /* Program required FCoE hash buckets for the PF */ 5458 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5459 val |= ((u32)settings->fcoe_filt_num << 5460 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) & 5461 I40E_PFQF_CTL_0_PFFCHSIZE_MASK; 5462 /* Program required FCoE DDP contexts for the PF */ 5463 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5464 val |= ((u32)settings->fcoe_cntx_num << 5465 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) & 5466 I40E_PFQF_CTL_0_PFFCDSIZE_MASK; 5467 5468 /* Program Hash LUT size for the PF */ 5469 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5470 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512) 5471 hash_lut_size = 1; 5472 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) & 5473 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK; 5474 5475 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */ 5476 if (settings->enable_fdir) 5477 val |= I40E_PFQF_CTL_0_FD_ENA_MASK; 5478 if (settings->enable_ethtype) 5479 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK; 5480 if (settings->enable_macvlan) 5481 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK; 5482 5483 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val); 5484 5485 return I40E_SUCCESS; 5486 } 5487 5488 /** 5489 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter 5490 * @hw: pointer to the hw struct 5491 * @mac_addr: MAC address to use in the filter 5492 * @ethtype: Ethertype to use in the filter 5493 * @flags: Flags that needs to be applied to the filter 5494 * @vsi_seid: seid of the control VSI 5495 * @queue: VSI queue number to send the packet to 5496 * @is_add: Add control packet filter if True else remove 5497 * @stats: Structure to hold information on control filter counts 5498 * @cmd_details: pointer to command details structure or NULL 5499 * 5500 * This command will Add or Remove control packet filter for a control VSI. 5501 * In return it will update the total number of perfect filter count in 5502 * the stats member. 5503 **/ 5504 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, 5505 u8 *mac_addr, u16 ethtype, u16 flags, 5506 u16 vsi_seid, u16 queue, bool is_add, 5507 struct i40e_control_filter_stats *stats, 5508 struct i40e_asq_cmd_details *cmd_details) 5509 { 5510 struct i40e_aq_desc desc; 5511 struct i40e_aqc_add_remove_control_packet_filter *cmd = 5512 (struct i40e_aqc_add_remove_control_packet_filter *) 5513 &desc.params.raw; 5514 struct i40e_aqc_add_remove_control_packet_filter_completion *resp = 5515 (struct i40e_aqc_add_remove_control_packet_filter_completion *) 5516 &desc.params.raw; 5517 enum i40e_status_code status; 5518 5519 if (vsi_seid == 0) 5520 return I40E_ERR_PARAM; 5521 5522 if (is_add) { 5523 i40e_fill_default_direct_cmd_desc(&desc, 5524 i40e_aqc_opc_add_control_packet_filter); 5525 cmd->queue = CPU_TO_LE16(queue); 5526 } else { 5527 i40e_fill_default_direct_cmd_desc(&desc, 5528 i40e_aqc_opc_remove_control_packet_filter); 5529 } 5530 5531 if (mac_addr) 5532 i40e_memcpy(cmd->mac, mac_addr, ETH_ALEN, 5533 I40E_NONDMA_TO_NONDMA); 5534 5535 cmd->etype = CPU_TO_LE16(ethtype); 5536 cmd->flags = CPU_TO_LE16(flags); 5537 cmd->seid = CPU_TO_LE16(vsi_seid); 5538 5539 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5540 5541 if (!status && stats) { 5542 stats->mac_etype_used = LE16_TO_CPU(resp->mac_etype_used); 5543 stats->etype_used = LE16_TO_CPU(resp->etype_used); 5544 stats->mac_etype_free = LE16_TO_CPU(resp->mac_etype_free); 5545 stats->etype_free = LE16_TO_CPU(resp->etype_free); 5546 } 5547 5548 return status; 5549 } 5550 5551 /** 5552 * i40e_add_filter_to_drop_tx_flow_control_frames- filter to drop flow control 5553 * @hw: pointer to the hw struct 5554 * @seid: VSI seid to add ethertype filter from 5555 **/ 5556 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, 5557 u16 seid) 5558 { 5559 #define I40E_FLOW_CONTROL_ETHTYPE 0x8808 5560 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC | 5561 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP | 5562 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX; 5563 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE; 5564 enum i40e_status_code status; 5565 5566 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag, 5567 seid, 0, TRUE, NULL, 5568 NULL); 5569 if (status) 5570 DEBUGOUT("Ethtype Filter Add failed: Error pruning Tx flow control frames\n"); 5571 } 5572 5573 /** 5574 * i40e_fix_up_geneve_vni - adjust Geneve VNI for HW issue 5575 * @filters: list of cloud filters 5576 * @filter_count: length of list 5577 * 5578 * There's an issue in the device where the Geneve VNI layout needs 5579 * to be shifted 1 byte over from the VxLAN VNI 5580 **/ 5581 static void i40e_fix_up_geneve_vni( 5582 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5583 u8 filter_count) 5584 { 5585 struct i40e_aqc_add_remove_cloud_filters_element_data *f = filters; 5586 int i; 5587 5588 for (i = 0; i < filter_count; i++) { 5589 u16 tnl_type; 5590 u32 ti; 5591 5592 tnl_type = (LE16_TO_CPU(f[i].flags) & 5593 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >> 5594 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT; 5595 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) { 5596 ti = LE32_TO_CPU(f[i].tenant_id); 5597 f[i].tenant_id = CPU_TO_LE32(ti << 8); 5598 } 5599 } 5600 } 5601 5602 /** 5603 * i40e_aq_add_cloud_filters 5604 * @hw: pointer to the hardware structure 5605 * @seid: VSI seid to add cloud filters from 5606 * @filters: Buffer which contains the filters to be added 5607 * @filter_count: number of filters contained in the buffer 5608 * 5609 * Set the cloud filters for a given VSI. The contents of the 5610 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5611 * in by the caller of the function. 5612 * 5613 **/ 5614 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw, 5615 u16 seid, 5616 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5617 u8 filter_count) 5618 { 5619 struct i40e_aq_desc desc; 5620 struct i40e_aqc_add_remove_cloud_filters *cmd = 5621 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5622 enum i40e_status_code status; 5623 u16 buff_len; 5624 5625 i40e_fill_default_direct_cmd_desc(&desc, 5626 i40e_aqc_opc_add_cloud_filters); 5627 5628 buff_len = filter_count * sizeof(*filters); 5629 desc.datalen = CPU_TO_LE16(buff_len); 5630 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5631 cmd->num_filters = filter_count; 5632 cmd->seid = CPU_TO_LE16(seid); 5633 5634 i40e_fix_up_geneve_vni(filters, filter_count); 5635 5636 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5637 5638 return status; 5639 } 5640 5641 /** 5642 * i40e_aq_remove_cloud_filters 5643 * @hw: pointer to the hardware structure 5644 * @seid: VSI seid to remove cloud filters from 5645 * @filters: Buffer which contains the filters to be removed 5646 * @filter_count: number of filters contained in the buffer 5647 * 5648 * Remove the cloud filters for a given VSI. The contents of the 5649 * i40e_aqc_add_remove_cloud_filters_element_data are filled 5650 * in by the caller of the function. 5651 * 5652 **/ 5653 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw, 5654 u16 seid, 5655 struct i40e_aqc_add_remove_cloud_filters_element_data *filters, 5656 u8 filter_count) 5657 { 5658 struct i40e_aq_desc desc; 5659 struct i40e_aqc_add_remove_cloud_filters *cmd = 5660 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw; 5661 enum i40e_status_code status; 5662 u16 buff_len; 5663 5664 i40e_fill_default_direct_cmd_desc(&desc, 5665 i40e_aqc_opc_remove_cloud_filters); 5666 5667 buff_len = filter_count * sizeof(*filters); 5668 desc.datalen = CPU_TO_LE16(buff_len); 5669 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 5670 cmd->num_filters = filter_count; 5671 cmd->seid = CPU_TO_LE16(seid); 5672 5673 i40e_fix_up_geneve_vni(filters, filter_count); 5674 5675 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL); 5676 5677 return status; 5678 } 5679 5680 /** 5681 * i40e_aq_alternate_write 5682 * @hw: pointer to the hardware structure 5683 * @reg_addr0: address of first dword to be read 5684 * @reg_val0: value to be written under 'reg_addr0' 5685 * @reg_addr1: address of second dword to be read 5686 * @reg_val1: value to be written under 'reg_addr1' 5687 * 5688 * Write one or two dwords to alternate structure. Fields are indicated 5689 * by 'reg_addr0' and 'reg_addr1' register numbers. 5690 * 5691 **/ 5692 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw, 5693 u32 reg_addr0, u32 reg_val0, 5694 u32 reg_addr1, u32 reg_val1) 5695 { 5696 struct i40e_aq_desc desc; 5697 struct i40e_aqc_alternate_write *cmd_resp = 5698 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5699 enum i40e_status_code status; 5700 5701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_write); 5702 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5703 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5704 cmd_resp->data0 = CPU_TO_LE32(reg_val0); 5705 cmd_resp->data1 = CPU_TO_LE32(reg_val1); 5706 5707 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5708 5709 return status; 5710 } 5711 5712 /** 5713 * i40e_aq_alternate_write_indirect 5714 * @hw: pointer to the hardware structure 5715 * @addr: address of a first register to be modified 5716 * @dw_count: number of alternate structure fields to write 5717 * @buffer: pointer to the command buffer 5718 * 5719 * Write 'dw_count' dwords from 'buffer' to alternate structure 5720 * starting at 'addr'. 5721 * 5722 **/ 5723 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw, 5724 u32 addr, u32 dw_count, void *buffer) 5725 { 5726 struct i40e_aq_desc desc; 5727 struct i40e_aqc_alternate_ind_write *cmd_resp = 5728 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5729 enum i40e_status_code status; 5730 5731 if (buffer == NULL) 5732 return I40E_ERR_PARAM; 5733 5734 /* Indirect command */ 5735 i40e_fill_default_direct_cmd_desc(&desc, 5736 i40e_aqc_opc_alternate_write_indirect); 5737 5738 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5739 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5740 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5741 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5742 5743 cmd_resp->address = CPU_TO_LE32(addr); 5744 cmd_resp->length = CPU_TO_LE32(dw_count); 5745 5746 status = i40e_asq_send_command(hw, &desc, buffer, 5747 I40E_LO_DWORD(4*dw_count), NULL); 5748 5749 return status; 5750 } 5751 5752 /** 5753 * i40e_aq_alternate_read 5754 * @hw: pointer to the hardware structure 5755 * @reg_addr0: address of first dword to be read 5756 * @reg_val0: pointer for data read from 'reg_addr0' 5757 * @reg_addr1: address of second dword to be read 5758 * @reg_val1: pointer for data read from 'reg_addr1' 5759 * 5760 * Read one or two dwords from alternate structure. Fields are indicated 5761 * by 'reg_addr0' and 'reg_addr1' register numbers. If 'reg_val1' pointer 5762 * is not passed then only register at 'reg_addr0' is read. 5763 * 5764 **/ 5765 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw, 5766 u32 reg_addr0, u32 *reg_val0, 5767 u32 reg_addr1, u32 *reg_val1) 5768 { 5769 struct i40e_aq_desc desc; 5770 struct i40e_aqc_alternate_write *cmd_resp = 5771 (struct i40e_aqc_alternate_write *)&desc.params.raw; 5772 enum i40e_status_code status; 5773 5774 if (reg_val0 == NULL) 5775 return I40E_ERR_PARAM; 5776 5777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read); 5778 cmd_resp->address0 = CPU_TO_LE32(reg_addr0); 5779 cmd_resp->address1 = CPU_TO_LE32(reg_addr1); 5780 5781 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5782 5783 if (status == I40E_SUCCESS) { 5784 *reg_val0 = LE32_TO_CPU(cmd_resp->data0); 5785 5786 if (reg_val1 != NULL) 5787 *reg_val1 = LE32_TO_CPU(cmd_resp->data1); 5788 } 5789 5790 return status; 5791 } 5792 5793 /** 5794 * i40e_aq_alternate_read_indirect 5795 * @hw: pointer to the hardware structure 5796 * @addr: address of the alternate structure field 5797 * @dw_count: number of alternate structure fields to read 5798 * @buffer: pointer to the command buffer 5799 * 5800 * Read 'dw_count' dwords from alternate structure starting at 'addr' and 5801 * place them in 'buffer'. The buffer should be allocated by caller. 5802 * 5803 **/ 5804 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw, 5805 u32 addr, u32 dw_count, void *buffer) 5806 { 5807 struct i40e_aq_desc desc; 5808 struct i40e_aqc_alternate_ind_write *cmd_resp = 5809 (struct i40e_aqc_alternate_ind_write *)&desc.params.raw; 5810 enum i40e_status_code status; 5811 5812 if (buffer == NULL) 5813 return I40E_ERR_PARAM; 5814 5815 /* Indirect command */ 5816 i40e_fill_default_direct_cmd_desc(&desc, 5817 i40e_aqc_opc_alternate_read_indirect); 5818 5819 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_RD); 5820 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 5821 if (dw_count > (I40E_AQ_LARGE_BUF/4)) 5822 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 5823 5824 cmd_resp->address = CPU_TO_LE32(addr); 5825 cmd_resp->length = CPU_TO_LE32(dw_count); 5826 5827 status = i40e_asq_send_command(hw, &desc, buffer, 5828 I40E_LO_DWORD(4*dw_count), NULL); 5829 5830 return status; 5831 } 5832 5833 /** 5834 * i40e_aq_alternate_clear 5835 * @hw: pointer to the HW structure. 5836 * 5837 * Clear the alternate structures of the port from which the function 5838 * is called. 5839 * 5840 **/ 5841 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw) 5842 { 5843 struct i40e_aq_desc desc; 5844 enum i40e_status_code status; 5845 5846 i40e_fill_default_direct_cmd_desc(&desc, 5847 i40e_aqc_opc_alternate_clear_port); 5848 5849 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5850 5851 return status; 5852 } 5853 5854 /** 5855 * i40e_aq_alternate_write_done 5856 * @hw: pointer to the HW structure. 5857 * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS 5858 * @reset_needed: indicates the SW should trigger GLOBAL reset 5859 * 5860 * Indicates to the FW that alternate structures have been changed. 5861 * 5862 **/ 5863 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw, 5864 u8 bios_mode, bool *reset_needed) 5865 { 5866 struct i40e_aq_desc desc; 5867 struct i40e_aqc_alternate_write_done *cmd = 5868 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5869 enum i40e_status_code status; 5870 5871 if (reset_needed == NULL) 5872 return I40E_ERR_PARAM; 5873 5874 i40e_fill_default_direct_cmd_desc(&desc, 5875 i40e_aqc_opc_alternate_write_done); 5876 5877 cmd->cmd_flags = CPU_TO_LE16(bios_mode); 5878 5879 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5880 if (!status && reset_needed) 5881 *reset_needed = ((LE16_TO_CPU(cmd->cmd_flags) & 5882 I40E_AQ_ALTERNATE_RESET_NEEDED) != 0); 5883 5884 return status; 5885 } 5886 5887 /** 5888 * i40e_aq_set_oem_mode 5889 * @hw: pointer to the HW structure. 5890 * @oem_mode: the OEM mode to be used 5891 * 5892 * Sets the device to a specific operating mode. Currently the only supported 5893 * mode is no_clp, which causes FW to refrain from using Alternate RAM. 5894 * 5895 **/ 5896 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw, 5897 u8 oem_mode) 5898 { 5899 struct i40e_aq_desc desc; 5900 struct i40e_aqc_alternate_write_done *cmd = 5901 (struct i40e_aqc_alternate_write_done *)&desc.params.raw; 5902 enum i40e_status_code status; 5903 5904 i40e_fill_default_direct_cmd_desc(&desc, 5905 i40e_aqc_opc_alternate_set_mode); 5906 5907 cmd->cmd_flags = CPU_TO_LE16(oem_mode); 5908 5909 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 5910 5911 return status; 5912 } 5913 5914 /** 5915 * i40e_aq_resume_port_tx 5916 * @hw: pointer to the hardware structure 5917 * @cmd_details: pointer to command details structure or NULL 5918 * 5919 * Resume port's Tx traffic 5920 **/ 5921 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw, 5922 struct i40e_asq_cmd_details *cmd_details) 5923 { 5924 struct i40e_aq_desc desc; 5925 enum i40e_status_code status; 5926 5927 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx); 5928 5929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 5930 5931 return status; 5932 } 5933 5934 /** 5935 * i40e_set_pci_config_data - store PCI bus info 5936 * @hw: pointer to hardware structure 5937 * @link_status: the link status word from PCI config space 5938 * 5939 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure 5940 **/ 5941 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status) 5942 { 5943 hw->bus.type = i40e_bus_type_pci_express; 5944 5945 switch (link_status & I40E_PCI_LINK_WIDTH) { 5946 case I40E_PCI_LINK_WIDTH_1: 5947 hw->bus.width = i40e_bus_width_pcie_x1; 5948 break; 5949 case I40E_PCI_LINK_WIDTH_2: 5950 hw->bus.width = i40e_bus_width_pcie_x2; 5951 break; 5952 case I40E_PCI_LINK_WIDTH_4: 5953 hw->bus.width = i40e_bus_width_pcie_x4; 5954 break; 5955 case I40E_PCI_LINK_WIDTH_8: 5956 hw->bus.width = i40e_bus_width_pcie_x8; 5957 break; 5958 default: 5959 hw->bus.width = i40e_bus_width_unknown; 5960 break; 5961 } 5962 5963 switch (link_status & I40E_PCI_LINK_SPEED) { 5964 case I40E_PCI_LINK_SPEED_2500: 5965 hw->bus.speed = i40e_bus_speed_2500; 5966 break; 5967 case I40E_PCI_LINK_SPEED_5000: 5968 hw->bus.speed = i40e_bus_speed_5000; 5969 break; 5970 case I40E_PCI_LINK_SPEED_8000: 5971 hw->bus.speed = i40e_bus_speed_8000; 5972 break; 5973 default: 5974 hw->bus.speed = i40e_bus_speed_unknown; 5975 break; 5976 } 5977 } 5978 5979 /** 5980 * i40e_aq_debug_dump 5981 * @hw: pointer to the hardware structure 5982 * @cluster_id: specific cluster to dump 5983 * @table_id: table id within cluster 5984 * @start_index: index of line in the block to read 5985 * @buff_size: dump buffer size 5986 * @buff: dump buffer 5987 * @ret_buff_size: actual buffer size returned 5988 * @ret_next_table: next block to read 5989 * @ret_next_index: next index to read 5990 * @cmd_details: pointer to command details structure or NULL 5991 * 5992 * Dump internal FW/HW data for debug purposes. 5993 * 5994 **/ 5995 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id, 5996 u8 table_id, u32 start_index, u16 buff_size, 5997 void *buff, u16 *ret_buff_size, 5998 u8 *ret_next_table, u32 *ret_next_index, 5999 struct i40e_asq_cmd_details *cmd_details) 6000 { 6001 struct i40e_aq_desc desc; 6002 struct i40e_aqc_debug_dump_internals *cmd = 6003 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6004 struct i40e_aqc_debug_dump_internals *resp = 6005 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw; 6006 enum i40e_status_code status; 6007 6008 if (buff_size == 0 || !buff) 6009 return I40E_ERR_PARAM; 6010 6011 i40e_fill_default_direct_cmd_desc(&desc, 6012 i40e_aqc_opc_debug_dump_internals); 6013 /* Indirect Command */ 6014 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6015 if (buff_size > I40E_AQ_LARGE_BUF) 6016 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 6017 6018 cmd->cluster_id = cluster_id; 6019 cmd->table_id = table_id; 6020 cmd->idx = CPU_TO_LE32(start_index); 6021 6022 desc.datalen = CPU_TO_LE16(buff_size); 6023 6024 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); 6025 if (!status) { 6026 if (ret_buff_size != NULL) 6027 *ret_buff_size = LE16_TO_CPU(desc.datalen); 6028 if (ret_next_table != NULL) 6029 *ret_next_table = resp->table_id; 6030 if (ret_next_index != NULL) 6031 *ret_next_index = LE32_TO_CPU(resp->idx); 6032 } 6033 6034 return status; 6035 } 6036 6037 /** 6038 * i40e_read_bw_from_alt_ram 6039 * @hw: pointer to the hardware structure 6040 * @max_bw: pointer for max_bw read 6041 * @min_bw: pointer for min_bw read 6042 * @min_valid: pointer for bool that is TRUE if min_bw is a valid value 6043 * @max_valid: pointer for bool that is TRUE if max_bw is a valid value 6044 * 6045 * Read bw from the alternate ram for the given pf 6046 **/ 6047 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw, 6048 u32 *max_bw, u32 *min_bw, 6049 bool *min_valid, bool *max_valid) 6050 { 6051 enum i40e_status_code status; 6052 u32 max_bw_addr, min_bw_addr; 6053 6054 /* Calculate the address of the min/max bw registers */ 6055 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6056 I40E_ALT_STRUCT_MAX_BW_OFFSET + 6057 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6058 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET + 6059 I40E_ALT_STRUCT_MIN_BW_OFFSET + 6060 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id); 6061 6062 /* Read the bandwidths from alt ram */ 6063 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw, 6064 min_bw_addr, min_bw); 6065 6066 if (*min_bw & I40E_ALT_BW_VALID_MASK) 6067 *min_valid = TRUE; 6068 else 6069 *min_valid = FALSE; 6070 6071 if (*max_bw & I40E_ALT_BW_VALID_MASK) 6072 *max_valid = TRUE; 6073 else 6074 *max_valid = FALSE; 6075 6076 return status; 6077 } 6078 6079 /** 6080 * i40e_aq_configure_partition_bw 6081 * @hw: pointer to the hardware structure 6082 * @bw_data: Buffer holding valid pfs and bw limits 6083 * @cmd_details: pointer to command details 6084 * 6085 * Configure partitions guaranteed/max bw 6086 **/ 6087 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw, 6088 struct i40e_aqc_configure_partition_bw_data *bw_data, 6089 struct i40e_asq_cmd_details *cmd_details) 6090 { 6091 enum i40e_status_code status; 6092 struct i40e_aq_desc desc; 6093 u16 bwd_size = sizeof(*bw_data); 6094 6095 i40e_fill_default_direct_cmd_desc(&desc, 6096 i40e_aqc_opc_configure_partition_bw); 6097 6098 /* Indirect command */ 6099 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 6100 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 6101 6102 desc.datalen = CPU_TO_LE16(bwd_size); 6103 6104 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size, cmd_details); 6105 6106 return status; 6107 } 6108 6109 /** 6110 * i40e_read_phy_register_clause22 6111 * @hw: pointer to the HW structure 6112 * @reg: register address in the page 6113 * @phy_addr: PHY address on MDIO interface 6114 * @value: PHY register value 6115 * 6116 * Reads specified PHY register value 6117 **/ 6118 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw, 6119 u16 reg, u8 phy_addr, u16 *value) 6120 { 6121 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6122 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6123 u32 command = 0; 6124 u16 retry = 1000; 6125 6126 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6127 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6128 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) | 6129 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6130 (I40E_GLGEN_MSCA_MDICMD_MASK); 6131 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6132 do { 6133 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6134 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6135 status = I40E_SUCCESS; 6136 break; 6137 } 6138 i40e_usec_delay(10); 6139 retry--; 6140 } while (retry); 6141 6142 if (status) { 6143 i40e_debug(hw, I40E_DEBUG_PHY, 6144 "PHY: Can't write command to external PHY.\n"); 6145 } else { 6146 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6147 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6148 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6149 } 6150 6151 return status; 6152 } 6153 6154 /** 6155 * i40e_write_phy_register_clause22 6156 * @hw: pointer to the HW structure 6157 * @reg: register address in the page 6158 * @phy_addr: PHY address on MDIO interface 6159 * @value: PHY register value 6160 * 6161 * Writes specified PHY register value 6162 **/ 6163 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw, 6164 u16 reg, u8 phy_addr, u16 value) 6165 { 6166 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6167 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6168 u32 command = 0; 6169 u16 retry = 1000; 6170 6171 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6172 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6173 6174 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6175 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6176 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) | 6177 (I40E_MDIO_CLAUSE22_STCODE_MASK) | 6178 (I40E_GLGEN_MSCA_MDICMD_MASK); 6179 6180 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6181 do { 6182 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6183 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6184 status = I40E_SUCCESS; 6185 break; 6186 } 6187 i40e_usec_delay(10); 6188 retry--; 6189 } while (retry); 6190 6191 return status; 6192 } 6193 6194 /** 6195 * i40e_read_phy_register_clause45 6196 * @hw: pointer to the HW structure 6197 * @page: registers page number 6198 * @reg: register address in the page 6199 * @phy_addr: PHY address on MDIO interface 6200 * @value: PHY register value 6201 * 6202 * Reads specified PHY register value 6203 **/ 6204 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw, 6205 u8 page, u16 reg, u8 phy_addr, u16 *value) 6206 { 6207 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6208 u32 command = 0; 6209 u16 retry = 1000; 6210 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6211 6212 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6213 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6214 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6215 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6216 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6217 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6218 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6219 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6220 do { 6221 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6222 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6223 status = I40E_SUCCESS; 6224 break; 6225 } 6226 i40e_usec_delay(10); 6227 retry--; 6228 } while (retry); 6229 6230 if (status) { 6231 i40e_debug(hw, I40E_DEBUG_PHY, 6232 "PHY: Can't write command to external PHY.\n"); 6233 goto phy_read_end; 6234 } 6235 6236 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6237 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6238 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) | 6239 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6240 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6241 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6242 status = I40E_ERR_TIMEOUT; 6243 retry = 1000; 6244 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6245 do { 6246 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6247 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6248 status = I40E_SUCCESS; 6249 break; 6250 } 6251 i40e_usec_delay(10); 6252 retry--; 6253 } while (retry); 6254 6255 if (!status) { 6256 command = rd32(hw, I40E_GLGEN_MSRWD(port_num)); 6257 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >> 6258 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT; 6259 } else { 6260 i40e_debug(hw, I40E_DEBUG_PHY, 6261 "PHY: Can't read register value from external PHY.\n"); 6262 } 6263 6264 phy_read_end: 6265 return status; 6266 } 6267 6268 /** 6269 * i40e_write_phy_register_clause45 6270 * @hw: pointer to the HW structure 6271 * @page: registers page number 6272 * @reg: register address in the page 6273 * @phy_addr: PHY address on MDIO interface 6274 * @value: PHY register value 6275 * 6276 * Writes value to specified PHY register 6277 **/ 6278 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw, 6279 u8 page, u16 reg, u8 phy_addr, u16 value) 6280 { 6281 enum i40e_status_code status = I40E_ERR_TIMEOUT; 6282 u32 command = 0; 6283 u16 retry = 1000; 6284 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6285 6286 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) | 6287 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6288 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6289 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) | 6290 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6291 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6292 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6293 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6294 do { 6295 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6296 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6297 status = I40E_SUCCESS; 6298 break; 6299 } 6300 i40e_usec_delay(10); 6301 retry--; 6302 } while (retry); 6303 if (status) { 6304 i40e_debug(hw, I40E_DEBUG_PHY, 6305 "PHY: Can't write command to external PHY.\n"); 6306 goto phy_write_end; 6307 } 6308 6309 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT; 6310 wr32(hw, I40E_GLGEN_MSRWD(port_num), command); 6311 6312 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) | 6313 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) | 6314 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) | 6315 (I40E_MDIO_CLAUSE45_STCODE_MASK) | 6316 (I40E_GLGEN_MSCA_MDICMD_MASK) | 6317 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK); 6318 status = I40E_ERR_TIMEOUT; 6319 retry = 1000; 6320 wr32(hw, I40E_GLGEN_MSCA(port_num), command); 6321 do { 6322 command = rd32(hw, I40E_GLGEN_MSCA(port_num)); 6323 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) { 6324 status = I40E_SUCCESS; 6325 break; 6326 } 6327 i40e_usec_delay(10); 6328 retry--; 6329 } while (retry); 6330 6331 phy_write_end: 6332 return status; 6333 } 6334 6335 /** 6336 * i40e_write_phy_register 6337 * @hw: pointer to the HW structure 6338 * @page: registers page number 6339 * @reg: register address in the page 6340 * @phy_addr: PHY address on MDIO interface 6341 * @value: PHY register value 6342 * 6343 * Writes value to specified PHY register 6344 **/ 6345 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw, 6346 u8 page, u16 reg, u8 phy_addr, u16 value) 6347 { 6348 enum i40e_status_code status; 6349 6350 switch (hw->device_id) { 6351 case I40E_DEV_ID_1G_BASE_T_X722: 6352 status = i40e_write_phy_register_clause22(hw, 6353 reg, phy_addr, value); 6354 break; 6355 case I40E_DEV_ID_10G_BASE_T: 6356 case I40E_DEV_ID_10G_BASE_T4: 6357 case I40E_DEV_ID_10G_BASE_T_X722: 6358 case I40E_DEV_ID_25G_B: 6359 case I40E_DEV_ID_25G_SFP28: 6360 status = i40e_write_phy_register_clause45(hw, 6361 page, reg, phy_addr, value); 6362 break; 6363 default: 6364 status = I40E_ERR_UNKNOWN_PHY; 6365 break; 6366 } 6367 6368 return status; 6369 } 6370 6371 /** 6372 * i40e_read_phy_register 6373 * @hw: pointer to the HW structure 6374 * @page: registers page number 6375 * @reg: register address in the page 6376 * @phy_addr: PHY address on MDIO interface 6377 * @value: PHY register value 6378 * 6379 * Reads specified PHY register value 6380 **/ 6381 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw, 6382 u8 page, u16 reg, u8 phy_addr, u16 *value) 6383 { 6384 enum i40e_status_code status; 6385 6386 switch (hw->device_id) { 6387 case I40E_DEV_ID_1G_BASE_T_X722: 6388 status = i40e_read_phy_register_clause22(hw, reg, phy_addr, 6389 value); 6390 break; 6391 case I40E_DEV_ID_10G_BASE_T: 6392 case I40E_DEV_ID_10G_BASE_T4: 6393 case I40E_DEV_ID_10G_BASE_T_X722: 6394 case I40E_DEV_ID_25G_B: 6395 case I40E_DEV_ID_25G_SFP28: 6396 status = i40e_read_phy_register_clause45(hw, page, reg, 6397 phy_addr, value); 6398 break; 6399 default: 6400 status = I40E_ERR_UNKNOWN_PHY; 6401 break; 6402 } 6403 6404 return status; 6405 } 6406 6407 /** 6408 * i40e_get_phy_address 6409 * @hw: pointer to the HW structure 6410 * @dev_num: PHY port num that address we want 6411 * 6412 * Gets PHY address for current port 6413 **/ 6414 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num) 6415 { 6416 u8 port_num = (u8)hw->func_caps.mdio_port_num; 6417 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num)); 6418 6419 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f; 6420 } 6421 6422 /** 6423 * i40e_blink_phy_led 6424 * @hw: pointer to the HW structure 6425 * @time: time how long led will blinks in secs 6426 * @interval: gap between LED on and off in msecs 6427 * 6428 * Blinks PHY link LED 6429 **/ 6430 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw, 6431 u32 time, u32 interval) 6432 { 6433 enum i40e_status_code status = I40E_SUCCESS; 6434 u32 i; 6435 u16 led_ctl = 0; 6436 u16 gpio_led_port; 6437 u16 led_reg; 6438 u16 led_addr = I40E_PHY_LED_PROV_REG_1; 6439 u8 phy_addr = 0; 6440 u8 port_num; 6441 6442 i = rd32(hw, I40E_PFGEN_PORTNUM); 6443 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK); 6444 phy_addr = i40e_get_phy_address(hw, port_num); 6445 6446 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6447 led_addr++) { 6448 status = i40e_read_phy_register_clause45(hw, 6449 I40E_PHY_COM_REG_PAGE, 6450 led_addr, phy_addr, 6451 &led_reg); 6452 if (status) 6453 goto phy_blinking_end; 6454 led_ctl = led_reg; 6455 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6456 led_reg = 0; 6457 status = i40e_write_phy_register_clause45(hw, 6458 I40E_PHY_COM_REG_PAGE, 6459 led_addr, phy_addr, 6460 led_reg); 6461 if (status) 6462 goto phy_blinking_end; 6463 break; 6464 } 6465 } 6466 6467 if (time > 0 && interval > 0) { 6468 for (i = 0; i < time * 1000; i += interval) { 6469 status = i40e_read_phy_register_clause45(hw, 6470 I40E_PHY_COM_REG_PAGE, 6471 led_addr, phy_addr, &led_reg); 6472 if (status) 6473 goto restore_config; 6474 if (led_reg & I40E_PHY_LED_MANUAL_ON) 6475 led_reg = 0; 6476 else 6477 led_reg = I40E_PHY_LED_MANUAL_ON; 6478 status = i40e_write_phy_register_clause45(hw, 6479 I40E_PHY_COM_REG_PAGE, 6480 led_addr, phy_addr, led_reg); 6481 if (status) 6482 goto restore_config; 6483 i40e_msec_delay(interval); 6484 } 6485 } 6486 6487 restore_config: 6488 status = i40e_write_phy_register_clause45(hw, 6489 I40E_PHY_COM_REG_PAGE, 6490 led_addr, phy_addr, led_ctl); 6491 6492 phy_blinking_end: 6493 return status; 6494 } 6495 6496 /** 6497 * i40e_led_get_reg - read LED register 6498 * @hw: pointer to the HW structure 6499 * @led_addr: LED register address 6500 * @reg_val: read register value 6501 **/ 6502 static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr, 6503 u32 *reg_val) 6504 { 6505 enum i40e_status_code status; 6506 u8 phy_addr = 0; 6507 6508 *reg_val = 0; 6509 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6510 status = i40e_aq_get_phy_register(hw, 6511 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6512 I40E_PHY_COM_REG_PAGE, 6513 I40E_PHY_LED_PROV_REG_1, 6514 reg_val, NULL); 6515 } else { 6516 phy_addr = i40e_get_phy_address(hw, hw->port); 6517 status = i40e_read_phy_register_clause45(hw, 6518 I40E_PHY_COM_REG_PAGE, 6519 led_addr, phy_addr, 6520 (u16 *)reg_val); 6521 } 6522 return status; 6523 } 6524 6525 /** 6526 * i40e_led_set_reg - write LED register 6527 * @hw: pointer to the HW structure 6528 * @led_addr: LED register address 6529 * @reg_val: register value to write 6530 **/ 6531 static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr, 6532 u32 reg_val) 6533 { 6534 enum i40e_status_code status; 6535 u8 phy_addr = 0; 6536 6537 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6538 status = i40e_aq_set_phy_register(hw, 6539 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6540 I40E_PHY_COM_REG_PAGE, 6541 I40E_PHY_LED_PROV_REG_1, 6542 reg_val, NULL); 6543 } else { 6544 phy_addr = i40e_get_phy_address(hw, hw->port); 6545 status = i40e_write_phy_register_clause45(hw, 6546 I40E_PHY_COM_REG_PAGE, 6547 led_addr, phy_addr, 6548 (u16)reg_val); 6549 } 6550 6551 return status; 6552 } 6553 6554 /** 6555 * i40e_led_get_phy - return current on/off mode 6556 * @hw: pointer to the hw struct 6557 * @led_addr: address of led register to use 6558 * @val: original value of register to use 6559 * 6560 **/ 6561 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr, 6562 u16 *val) 6563 { 6564 enum i40e_status_code status = I40E_SUCCESS; 6565 u16 gpio_led_port; 6566 u32 reg_val_aq; 6567 u16 temp_addr; 6568 u8 phy_addr = 0; 6569 u16 reg_val; 6570 6571 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) { 6572 status = i40e_aq_get_phy_register(hw, 6573 I40E_AQ_PHY_REG_ACCESS_EXTERNAL, 6574 I40E_PHY_COM_REG_PAGE, 6575 I40E_PHY_LED_PROV_REG_1, 6576 ®_val_aq, NULL); 6577 if (status == I40E_SUCCESS) 6578 *val = (u16)reg_val_aq; 6579 return status; 6580 } 6581 temp_addr = I40E_PHY_LED_PROV_REG_1; 6582 phy_addr = i40e_get_phy_address(hw, hw->port); 6583 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++, 6584 temp_addr++) { 6585 status = i40e_read_phy_register_clause45(hw, 6586 I40E_PHY_COM_REG_PAGE, 6587 temp_addr, phy_addr, 6588 ®_val); 6589 if (status) 6590 return status; 6591 *val = reg_val; 6592 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) { 6593 *led_addr = temp_addr; 6594 break; 6595 } 6596 } 6597 return status; 6598 } 6599 6600 /** 6601 * i40e_led_set_phy 6602 * @hw: pointer to the HW structure 6603 * @on: TRUE or FALSE 6604 * @led_addr: address of led register to use 6605 * @mode: original val plus bit for set or ignore 6606 * 6607 * Set led's on or off when controlled by the PHY 6608 * 6609 **/ 6610 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on, 6611 u16 led_addr, u32 mode) 6612 { 6613 enum i40e_status_code status = I40E_SUCCESS; 6614 u32 led_ctl = 0; 6615 u32 led_reg = 0; 6616 6617 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6618 if (status) 6619 return status; 6620 led_ctl = led_reg; 6621 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) { 6622 led_reg = 0; 6623 status = i40e_led_set_reg(hw, led_addr, led_reg); 6624 if (status) 6625 return status; 6626 } 6627 status = i40e_led_get_reg(hw, led_addr, &led_reg); 6628 if (status) 6629 goto restore_config; 6630 if (on) 6631 led_reg = I40E_PHY_LED_MANUAL_ON; 6632 else 6633 led_reg = 0; 6634 status = i40e_led_set_reg(hw, led_addr, led_reg); 6635 if (status) 6636 goto restore_config; 6637 if (mode & I40E_PHY_LED_MODE_ORIG) { 6638 led_ctl = (mode & I40E_PHY_LED_MODE_MASK); 6639 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6640 } 6641 return status; 6642 6643 restore_config: 6644 status = i40e_led_set_reg(hw, led_addr, led_ctl); 6645 return status; 6646 } 6647 6648 /** 6649 * i40e_aq_rx_ctl_read_register - use FW to read from an Rx control register 6650 * @hw: pointer to the hw struct 6651 * @reg_addr: register address 6652 * @reg_val: ptr to register value 6653 * @cmd_details: pointer to command details structure or NULL 6654 * 6655 * Use the firmware to read the Rx control register, 6656 * especially useful if the Rx unit is under heavy pressure 6657 **/ 6658 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw, 6659 u32 reg_addr, u32 *reg_val, 6660 struct i40e_asq_cmd_details *cmd_details) 6661 { 6662 struct i40e_aq_desc desc; 6663 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = 6664 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6665 enum i40e_status_code status; 6666 6667 if (reg_val == NULL) 6668 return I40E_ERR_PARAM; 6669 6670 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read); 6671 6672 cmd_resp->address = CPU_TO_LE32(reg_addr); 6673 6674 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6675 6676 if (status == I40E_SUCCESS) 6677 *reg_val = LE32_TO_CPU(cmd_resp->value); 6678 6679 return status; 6680 } 6681 6682 /** 6683 * i40e_read_rx_ctl - read from an Rx control register 6684 * @hw: pointer to the hw struct 6685 * @reg_addr: register address 6686 **/ 6687 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) 6688 { 6689 enum i40e_status_code status = I40E_SUCCESS; 6690 bool use_register; 6691 int retry = 5; 6692 u32 val = 0; 6693 6694 use_register = (((hw->aq.api_maj_ver == 1) && 6695 (hw->aq.api_min_ver < 5)) || 6696 (hw->mac.type == I40E_MAC_X722)); 6697 if (!use_register) { 6698 do_retry: 6699 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL); 6700 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6701 i40e_msec_delay(1); 6702 retry--; 6703 goto do_retry; 6704 } 6705 } 6706 6707 /* if the AQ access failed, try the old-fashioned way */ 6708 if (status || use_register) 6709 val = rd32(hw, reg_addr); 6710 6711 return val; 6712 } 6713 6714 /** 6715 * i40e_aq_rx_ctl_write_register 6716 * @hw: pointer to the hw struct 6717 * @reg_addr: register address 6718 * @reg_val: register value 6719 * @cmd_details: pointer to command details structure or NULL 6720 * 6721 * Use the firmware to write to an Rx control register, 6722 * especially useful if the Rx unit is under heavy pressure 6723 **/ 6724 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw, 6725 u32 reg_addr, u32 reg_val, 6726 struct i40e_asq_cmd_details *cmd_details) 6727 { 6728 struct i40e_aq_desc desc; 6729 struct i40e_aqc_rx_ctl_reg_read_write *cmd = 6730 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; 6731 enum i40e_status_code status; 6732 6733 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write); 6734 6735 cmd->address = CPU_TO_LE32(reg_addr); 6736 cmd->value = CPU_TO_LE32(reg_val); 6737 6738 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6739 6740 return status; 6741 } 6742 6743 /** 6744 * i40e_write_rx_ctl - write to an Rx control register 6745 * @hw: pointer to the hw struct 6746 * @reg_addr: register address 6747 * @reg_val: register value 6748 **/ 6749 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) 6750 { 6751 enum i40e_status_code status = I40E_SUCCESS; 6752 bool use_register; 6753 int retry = 5; 6754 6755 use_register = (((hw->aq.api_maj_ver == 1) && 6756 (hw->aq.api_min_ver < 5)) || 6757 (hw->mac.type == I40E_MAC_X722)); 6758 if (!use_register) { 6759 do_retry: 6760 status = i40e_aq_rx_ctl_write_register(hw, reg_addr, 6761 reg_val, NULL); 6762 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { 6763 i40e_msec_delay(1); 6764 retry--; 6765 goto do_retry; 6766 } 6767 } 6768 6769 /* if the AQ access failed, try the old-fashioned way */ 6770 if (status || use_register) 6771 wr32(hw, reg_addr, reg_val); 6772 } 6773 6774 6775 /** 6776 * i40e_aq_set_phy_register 6777 * @hw: pointer to the hw struct 6778 * @phy_select: select which phy should be accessed 6779 * @dev_addr: PHY device address 6780 * @reg_addr: PHY register address 6781 * @reg_val: new register value 6782 * @cmd_details: pointer to command details structure or NULL 6783 * 6784 * Write the external PHY register. 6785 **/ 6786 enum i40e_status_code i40e_aq_set_phy_register(struct i40e_hw *hw, 6787 u8 phy_select, u8 dev_addr, 6788 u32 reg_addr, u32 reg_val, 6789 struct i40e_asq_cmd_details *cmd_details) 6790 { 6791 struct i40e_aq_desc desc; 6792 struct i40e_aqc_phy_register_access *cmd = 6793 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6794 enum i40e_status_code status; 6795 6796 i40e_fill_default_direct_cmd_desc(&desc, 6797 i40e_aqc_opc_set_phy_register); 6798 6799 cmd->phy_interface = phy_select; 6800 cmd->dev_addres = dev_addr; 6801 cmd->reg_address = reg_addr; 6802 cmd->reg_value = reg_val; 6803 6804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6805 6806 return status; 6807 } 6808 6809 /** 6810 * i40e_aq_get_phy_register 6811 * @hw: pointer to the hw struct 6812 * @phy_select: select which phy should be accessed 6813 * @dev_addr: PHY device address 6814 * @reg_addr: PHY register address 6815 * @reg_val: read register value 6816 * @cmd_details: pointer to command details structure or NULL 6817 * 6818 * Read the external PHY register. 6819 **/ 6820 enum i40e_status_code i40e_aq_get_phy_register(struct i40e_hw *hw, 6821 u8 phy_select, u8 dev_addr, 6822 u32 reg_addr, u32 *reg_val, 6823 struct i40e_asq_cmd_details *cmd_details) 6824 { 6825 struct i40e_aq_desc desc; 6826 struct i40e_aqc_phy_register_access *cmd = 6827 (struct i40e_aqc_phy_register_access *)&desc.params.raw; 6828 enum i40e_status_code status; 6829 6830 i40e_fill_default_direct_cmd_desc(&desc, 6831 i40e_aqc_opc_get_phy_register); 6832 6833 cmd->phy_interface = phy_select; 6834 cmd->dev_addres = dev_addr; 6835 cmd->reg_address = reg_addr; 6836 6837 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6838 if (!status) 6839 *reg_val = cmd->reg_value; 6840 6841 return status; 6842 } 6843 6844 /** 6845 * i40e_aq_set_arp_proxy_config 6846 * @hw: pointer to the HW structure 6847 * @proxy_config: pointer to proxy config command table struct 6848 * @cmd_details: pointer to command details 6849 * 6850 * Set ARP offload parameters from pre-populated 6851 * i40e_aqc_arp_proxy_data struct 6852 **/ 6853 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw, 6854 struct i40e_aqc_arp_proxy_data *proxy_config, 6855 struct i40e_asq_cmd_details *cmd_details) 6856 { 6857 struct i40e_aq_desc desc; 6858 enum i40e_status_code status; 6859 6860 if (!proxy_config) 6861 return I40E_ERR_PARAM; 6862 6863 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_proxy_config); 6864 6865 desc.params.external.addr_high = 6866 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)proxy_config)); 6867 desc.params.external.addr_low = 6868 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)proxy_config)); 6869 6870 status = i40e_asq_send_command(hw, &desc, proxy_config, 6871 sizeof(struct i40e_aqc_arp_proxy_data), 6872 cmd_details); 6873 6874 return status; 6875 } 6876 6877 /** 6878 * i40e_aq_opc_set_ns_proxy_table_entry 6879 * @hw: pointer to the HW structure 6880 * @ns_proxy_table_entry: pointer to NS table entry command struct 6881 * @cmd_details: pointer to command details 6882 * 6883 * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters 6884 * from pre-populated i40e_aqc_ns_proxy_data struct 6885 **/ 6886 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw, 6887 struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry, 6888 struct i40e_asq_cmd_details *cmd_details) 6889 { 6890 struct i40e_aq_desc desc; 6891 enum i40e_status_code status; 6892 6893 if (!ns_proxy_table_entry) 6894 return I40E_ERR_PARAM; 6895 6896 i40e_fill_default_direct_cmd_desc(&desc, 6897 i40e_aqc_opc_set_ns_proxy_table_entry); 6898 6899 desc.params.external.addr_high = 6900 CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)ns_proxy_table_entry)); 6901 desc.params.external.addr_low = 6902 CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)ns_proxy_table_entry)); 6903 6904 status = i40e_asq_send_command(hw, &desc, ns_proxy_table_entry, 6905 sizeof(struct i40e_aqc_ns_proxy_data), 6906 cmd_details); 6907 6908 return status; 6909 } 6910 6911 /** 6912 * i40e_aq_set_clear_wol_filter 6913 * @hw: pointer to the hw struct 6914 * @filter_index: index of filter to modify (0-7) 6915 * @filter: buffer containing filter to be set 6916 * @set_filter: TRUE to set filter, FALSE to clear filter 6917 * @no_wol_tco: if TRUE, pass through packets cannot cause wake-up 6918 * if FALSE, pass through packets may cause wake-up 6919 * @filter_valid: TRUE if filter action is valid 6920 * @no_wol_tco_valid: TRUE if no WoL in TCO traffic action valid 6921 * @cmd_details: pointer to command details structure or NULL 6922 * 6923 * Set or clear WoL filter for port attached to the PF 6924 **/ 6925 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw, 6926 u8 filter_index, 6927 struct i40e_aqc_set_wol_filter_data *filter, 6928 bool set_filter, bool no_wol_tco, 6929 bool filter_valid, bool no_wol_tco_valid, 6930 struct i40e_asq_cmd_details *cmd_details) 6931 { 6932 struct i40e_aq_desc desc; 6933 struct i40e_aqc_set_wol_filter *cmd = 6934 (struct i40e_aqc_set_wol_filter *)&desc.params.raw; 6935 enum i40e_status_code status; 6936 u16 cmd_flags = 0; 6937 u16 valid_flags = 0; 6938 u16 buff_len = 0; 6939 6940 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_set_wol_filter); 6941 6942 if (filter_index >= I40E_AQC_MAX_NUM_WOL_FILTERS) 6943 return I40E_ERR_PARAM; 6944 cmd->filter_index = CPU_TO_LE16(filter_index); 6945 6946 if (set_filter) { 6947 if (!filter) 6948 return I40E_ERR_PARAM; 6949 cmd_flags |= I40E_AQC_SET_WOL_FILTER; 6950 buff_len = sizeof(*filter); 6951 } 6952 if (no_wol_tco) 6953 cmd_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL; 6954 cmd->cmd_flags = CPU_TO_LE16(cmd_flags); 6955 6956 if (filter_valid) 6957 valid_flags |= I40E_AQC_SET_WOL_FILTER_ACTION_VALID; 6958 if (no_wol_tco_valid) 6959 valid_flags |= I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID; 6960 cmd->valid_flags = CPU_TO_LE16(valid_flags); 6961 6962 cmd->address_high = CPU_TO_LE32(I40E_HI_DWORD((uintptr_t)filter)); 6963 cmd->address_low = CPU_TO_LE32(I40E_LO_DWORD((uintptr_t)filter)); 6964 6965 status = i40e_asq_send_command(hw, &desc, filter, 6966 buff_len, cmd_details); 6967 6968 return status; 6969 } 6970 6971 /** 6972 * i40e_aq_get_wake_event_reason 6973 * @hw: pointer to the hw struct 6974 * @wake_reason: return value, index of matching filter 6975 * @cmd_details: pointer to command details structure or NULL 6976 * 6977 * Get information for the reason of a Wake Up event 6978 **/ 6979 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw, 6980 u16 *wake_reason, 6981 struct i40e_asq_cmd_details *cmd_details) 6982 { 6983 struct i40e_aq_desc desc; 6984 struct i40e_aqc_get_wake_reason_completion *resp = 6985 (struct i40e_aqc_get_wake_reason_completion *)&desc.params.raw; 6986 enum i40e_status_code status; 6987 6988 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_wake_reason); 6989 6990 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 6991 6992 if (status == I40E_SUCCESS) 6993 *wake_reason = LE16_TO_CPU(resp->wake_reason); 6994 6995 return status; 6996 } 6997 6998