1 /******************************************************************************
2 
3   Copyright (c) 2013-2017, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
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16    3. Neither the name of the Intel Corporation nor the names of its
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18       this software without specific prior written permission.
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20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "virtchnl.h"
39 
40 
41 /**
42  * i40e_set_mac_type - Sets MAC type
43  * @hw: pointer to the HW structure
44  *
45  * This function sets the mac type of the adapter based on the
46  * vendor ID and device ID stored in the hw structure.
47  **/
48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 {
50 	enum i40e_status_code status = I40E_SUCCESS;
51 
52 	DEBUGFUNC("i40e_set_mac_type\n");
53 
54 	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 		switch (hw->device_id) {
56 		case I40E_DEV_ID_SFP_XL710:
57 		case I40E_DEV_ID_QEMU:
58 		case I40E_DEV_ID_KX_B:
59 		case I40E_DEV_ID_KX_C:
60 		case I40E_DEV_ID_QSFP_A:
61 		case I40E_DEV_ID_QSFP_B:
62 		case I40E_DEV_ID_QSFP_C:
63 		case I40E_DEV_ID_10G_BASE_T:
64 		case I40E_DEV_ID_10G_BASE_T4:
65 		case I40E_DEV_ID_20G_KR2:
66 		case I40E_DEV_ID_20G_KR2_A:
67 		case I40E_DEV_ID_25G_B:
68 		case I40E_DEV_ID_25G_SFP28:
69 			hw->mac.type = I40E_MAC_XL710;
70 			break;
71 		case I40E_DEV_ID_KX_X722:
72 		case I40E_DEV_ID_QSFP_X722:
73 		case I40E_DEV_ID_SFP_X722:
74 		case I40E_DEV_ID_1G_BASE_T_X722:
75 		case I40E_DEV_ID_10G_BASE_T_X722:
76 		case I40E_DEV_ID_SFP_I_X722:
77 			hw->mac.type = I40E_MAC_X722;
78 			break;
79 		default:
80 			hw->mac.type = I40E_MAC_GENERIC;
81 			break;
82 		}
83 	} else {
84 		status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 	}
86 
87 	DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
88 		  hw->mac.type, status);
89 	return status;
90 }
91 
92 /**
93  * i40e_aq_str - convert AQ err code to a string
94  * @hw: pointer to the HW structure
95  * @aq_err: the AQ error code to convert
96  **/
97 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
98 {
99 	switch (aq_err) {
100 	case I40E_AQ_RC_OK:
101 		return "OK";
102 	case I40E_AQ_RC_EPERM:
103 		return "I40E_AQ_RC_EPERM";
104 	case I40E_AQ_RC_ENOENT:
105 		return "I40E_AQ_RC_ENOENT";
106 	case I40E_AQ_RC_ESRCH:
107 		return "I40E_AQ_RC_ESRCH";
108 	case I40E_AQ_RC_EINTR:
109 		return "I40E_AQ_RC_EINTR";
110 	case I40E_AQ_RC_EIO:
111 		return "I40E_AQ_RC_EIO";
112 	case I40E_AQ_RC_ENXIO:
113 		return "I40E_AQ_RC_ENXIO";
114 	case I40E_AQ_RC_E2BIG:
115 		return "I40E_AQ_RC_E2BIG";
116 	case I40E_AQ_RC_EAGAIN:
117 		return "I40E_AQ_RC_EAGAIN";
118 	case I40E_AQ_RC_ENOMEM:
119 		return "I40E_AQ_RC_ENOMEM";
120 	case I40E_AQ_RC_EACCES:
121 		return "I40E_AQ_RC_EACCES";
122 	case I40E_AQ_RC_EFAULT:
123 		return "I40E_AQ_RC_EFAULT";
124 	case I40E_AQ_RC_EBUSY:
125 		return "I40E_AQ_RC_EBUSY";
126 	case I40E_AQ_RC_EEXIST:
127 		return "I40E_AQ_RC_EEXIST";
128 	case I40E_AQ_RC_EINVAL:
129 		return "I40E_AQ_RC_EINVAL";
130 	case I40E_AQ_RC_ENOTTY:
131 		return "I40E_AQ_RC_ENOTTY";
132 	case I40E_AQ_RC_ENOSPC:
133 		return "I40E_AQ_RC_ENOSPC";
134 	case I40E_AQ_RC_ENOSYS:
135 		return "I40E_AQ_RC_ENOSYS";
136 	case I40E_AQ_RC_ERANGE:
137 		return "I40E_AQ_RC_ERANGE";
138 	case I40E_AQ_RC_EFLUSHED:
139 		return "I40E_AQ_RC_EFLUSHED";
140 	case I40E_AQ_RC_BAD_ADDR:
141 		return "I40E_AQ_RC_BAD_ADDR";
142 	case I40E_AQ_RC_EMODE:
143 		return "I40E_AQ_RC_EMODE";
144 	case I40E_AQ_RC_EFBIG:
145 		return "I40E_AQ_RC_EFBIG";
146 	}
147 
148 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
149 	return hw->err_str;
150 }
151 
152 /**
153  * i40e_stat_str - convert status err code to a string
154  * @hw: pointer to the HW structure
155  * @stat_err: the status error code to convert
156  **/
157 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
158 {
159 	switch (stat_err) {
160 	case I40E_SUCCESS:
161 		return "OK";
162 	case I40E_ERR_NVM:
163 		return "I40E_ERR_NVM";
164 	case I40E_ERR_NVM_CHECKSUM:
165 		return "I40E_ERR_NVM_CHECKSUM";
166 	case I40E_ERR_PHY:
167 		return "I40E_ERR_PHY";
168 	case I40E_ERR_CONFIG:
169 		return "I40E_ERR_CONFIG";
170 	case I40E_ERR_PARAM:
171 		return "I40E_ERR_PARAM";
172 	case I40E_ERR_MAC_TYPE:
173 		return "I40E_ERR_MAC_TYPE";
174 	case I40E_ERR_UNKNOWN_PHY:
175 		return "I40E_ERR_UNKNOWN_PHY";
176 	case I40E_ERR_LINK_SETUP:
177 		return "I40E_ERR_LINK_SETUP";
178 	case I40E_ERR_ADAPTER_STOPPED:
179 		return "I40E_ERR_ADAPTER_STOPPED";
180 	case I40E_ERR_INVALID_MAC_ADDR:
181 		return "I40E_ERR_INVALID_MAC_ADDR";
182 	case I40E_ERR_DEVICE_NOT_SUPPORTED:
183 		return "I40E_ERR_DEVICE_NOT_SUPPORTED";
184 	case I40E_ERR_MASTER_REQUESTS_PENDING:
185 		return "I40E_ERR_MASTER_REQUESTS_PENDING";
186 	case I40E_ERR_INVALID_LINK_SETTINGS:
187 		return "I40E_ERR_INVALID_LINK_SETTINGS";
188 	case I40E_ERR_AUTONEG_NOT_COMPLETE:
189 		return "I40E_ERR_AUTONEG_NOT_COMPLETE";
190 	case I40E_ERR_RESET_FAILED:
191 		return "I40E_ERR_RESET_FAILED";
192 	case I40E_ERR_SWFW_SYNC:
193 		return "I40E_ERR_SWFW_SYNC";
194 	case I40E_ERR_NO_AVAILABLE_VSI:
195 		return "I40E_ERR_NO_AVAILABLE_VSI";
196 	case I40E_ERR_NO_MEMORY:
197 		return "I40E_ERR_NO_MEMORY";
198 	case I40E_ERR_BAD_PTR:
199 		return "I40E_ERR_BAD_PTR";
200 	case I40E_ERR_RING_FULL:
201 		return "I40E_ERR_RING_FULL";
202 	case I40E_ERR_INVALID_PD_ID:
203 		return "I40E_ERR_INVALID_PD_ID";
204 	case I40E_ERR_INVALID_QP_ID:
205 		return "I40E_ERR_INVALID_QP_ID";
206 	case I40E_ERR_INVALID_CQ_ID:
207 		return "I40E_ERR_INVALID_CQ_ID";
208 	case I40E_ERR_INVALID_CEQ_ID:
209 		return "I40E_ERR_INVALID_CEQ_ID";
210 	case I40E_ERR_INVALID_AEQ_ID:
211 		return "I40E_ERR_INVALID_AEQ_ID";
212 	case I40E_ERR_INVALID_SIZE:
213 		return "I40E_ERR_INVALID_SIZE";
214 	case I40E_ERR_INVALID_ARP_INDEX:
215 		return "I40E_ERR_INVALID_ARP_INDEX";
216 	case I40E_ERR_INVALID_FPM_FUNC_ID:
217 		return "I40E_ERR_INVALID_FPM_FUNC_ID";
218 	case I40E_ERR_QP_INVALID_MSG_SIZE:
219 		return "I40E_ERR_QP_INVALID_MSG_SIZE";
220 	case I40E_ERR_QP_TOOMANY_WRS_POSTED:
221 		return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
222 	case I40E_ERR_INVALID_FRAG_COUNT:
223 		return "I40E_ERR_INVALID_FRAG_COUNT";
224 	case I40E_ERR_QUEUE_EMPTY:
225 		return "I40E_ERR_QUEUE_EMPTY";
226 	case I40E_ERR_INVALID_ALIGNMENT:
227 		return "I40E_ERR_INVALID_ALIGNMENT";
228 	case I40E_ERR_FLUSHED_QUEUE:
229 		return "I40E_ERR_FLUSHED_QUEUE";
230 	case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
231 		return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
232 	case I40E_ERR_INVALID_IMM_DATA_SIZE:
233 		return "I40E_ERR_INVALID_IMM_DATA_SIZE";
234 	case I40E_ERR_TIMEOUT:
235 		return "I40E_ERR_TIMEOUT";
236 	case I40E_ERR_OPCODE_MISMATCH:
237 		return "I40E_ERR_OPCODE_MISMATCH";
238 	case I40E_ERR_CQP_COMPL_ERROR:
239 		return "I40E_ERR_CQP_COMPL_ERROR";
240 	case I40E_ERR_INVALID_VF_ID:
241 		return "I40E_ERR_INVALID_VF_ID";
242 	case I40E_ERR_INVALID_HMCFN_ID:
243 		return "I40E_ERR_INVALID_HMCFN_ID";
244 	case I40E_ERR_BACKING_PAGE_ERROR:
245 		return "I40E_ERR_BACKING_PAGE_ERROR";
246 	case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
247 		return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
248 	case I40E_ERR_INVALID_PBLE_INDEX:
249 		return "I40E_ERR_INVALID_PBLE_INDEX";
250 	case I40E_ERR_INVALID_SD_INDEX:
251 		return "I40E_ERR_INVALID_SD_INDEX";
252 	case I40E_ERR_INVALID_PAGE_DESC_INDEX:
253 		return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
254 	case I40E_ERR_INVALID_SD_TYPE:
255 		return "I40E_ERR_INVALID_SD_TYPE";
256 	case I40E_ERR_MEMCPY_FAILED:
257 		return "I40E_ERR_MEMCPY_FAILED";
258 	case I40E_ERR_INVALID_HMC_OBJ_INDEX:
259 		return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
260 	case I40E_ERR_INVALID_HMC_OBJ_COUNT:
261 		return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
262 	case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
263 		return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
264 	case I40E_ERR_SRQ_ENABLED:
265 		return "I40E_ERR_SRQ_ENABLED";
266 	case I40E_ERR_ADMIN_QUEUE_ERROR:
267 		return "I40E_ERR_ADMIN_QUEUE_ERROR";
268 	case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
269 		return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
270 	case I40E_ERR_BUF_TOO_SHORT:
271 		return "I40E_ERR_BUF_TOO_SHORT";
272 	case I40E_ERR_ADMIN_QUEUE_FULL:
273 		return "I40E_ERR_ADMIN_QUEUE_FULL";
274 	case I40E_ERR_ADMIN_QUEUE_NO_WORK:
275 		return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
276 	case I40E_ERR_BAD_IWARP_CQE:
277 		return "I40E_ERR_BAD_IWARP_CQE";
278 	case I40E_ERR_NVM_BLANK_MODE:
279 		return "I40E_ERR_NVM_BLANK_MODE";
280 	case I40E_ERR_NOT_IMPLEMENTED:
281 		return "I40E_ERR_NOT_IMPLEMENTED";
282 	case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
283 		return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
284 	case I40E_ERR_DIAG_TEST_FAILED:
285 		return "I40E_ERR_DIAG_TEST_FAILED";
286 	case I40E_ERR_NOT_READY:
287 		return "I40E_ERR_NOT_READY";
288 	case I40E_NOT_SUPPORTED:
289 		return "I40E_NOT_SUPPORTED";
290 	case I40E_ERR_FIRMWARE_API_VERSION:
291 		return "I40E_ERR_FIRMWARE_API_VERSION";
292 	case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
293 		return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
294 	}
295 
296 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 	return hw->err_str;
298 }
299 
300 /**
301  * i40e_debug_aq
302  * @hw: debug mask related to admin queue
303  * @mask: debug mask
304  * @desc: pointer to admin queue descriptor
305  * @buffer: pointer to command buffer
306  * @buf_len: max length of buffer
307  *
308  * Dumps debug log about adminq command with descriptor contents.
309  **/
310 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
311 		   void *buffer, u16 buf_len)
312 {
313 	struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
314 	u8 *buf = (u8 *)buffer;
315 	u16 len;
316 	u16 i = 0;
317 
318 	if ((!(mask & hw->debug_mask)) || (desc == NULL))
319 		return;
320 
321 	len = LE16_TO_CPU(aq_desc->datalen);
322 
323 	i40e_debug(hw, mask,
324 		   "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
325 		   LE16_TO_CPU(aq_desc->opcode),
326 		   LE16_TO_CPU(aq_desc->flags),
327 		   LE16_TO_CPU(aq_desc->datalen),
328 		   LE16_TO_CPU(aq_desc->retval));
329 	i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
330 		   LE32_TO_CPU(aq_desc->cookie_high),
331 		   LE32_TO_CPU(aq_desc->cookie_low));
332 	i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
333 		   LE32_TO_CPU(aq_desc->params.internal.param0),
334 		   LE32_TO_CPU(aq_desc->params.internal.param1));
335 	i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
336 		   LE32_TO_CPU(aq_desc->params.external.addr_high),
337 		   LE32_TO_CPU(aq_desc->params.external.addr_low));
338 
339 	if ((buffer != NULL) && (aq_desc->datalen != 0)) {
340 		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
341 		if (buf_len < len)
342 			len = buf_len;
343 		/* write the full 16-byte chunks */
344 		for (i = 0; i < (len - 16); i += 16)
345 			i40e_debug(hw, mask,
346 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
347 				   i, buf[i], buf[i+1], buf[i+2], buf[i+3],
348 				   buf[i+4], buf[i+5], buf[i+6], buf[i+7],
349 				   buf[i+8], buf[i+9], buf[i+10], buf[i+11],
350 				   buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
351 		/* the most we could have left is 16 bytes, pad with zeros */
352 		if (i < len) {
353 			char d_buf[16];
354 			int j, i_sav;
355 
356 			i_sav = i;
357 			memset(d_buf, 0, sizeof(d_buf));
358 			for (j = 0; i < len; j++, i++)
359 				d_buf[j] = buf[i];
360 			i40e_debug(hw, mask,
361 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
362 				   i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
363 				   d_buf[4], d_buf[5], d_buf[6], d_buf[7],
364 				   d_buf[8], d_buf[9], d_buf[10], d_buf[11],
365 				   d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 		}
367 	}
368 }
369 
370 /**
371  * i40e_check_asq_alive
372  * @hw: pointer to the hw struct
373  *
374  * Returns TRUE if Queue is enabled else FALSE.
375  **/
376 bool i40e_check_asq_alive(struct i40e_hw *hw)
377 {
378 	if (hw->aq.asq.len)
379 		return !!(rd32(hw, hw->aq.asq.len) &
380 			I40E_PF_ATQLEN_ATQENABLE_MASK);
381 	return FALSE;
382 }
383 
384 /**
385  * i40e_aq_queue_shutdown
386  * @hw: pointer to the hw struct
387  * @unloading: is the driver unloading itself
388  *
389  * Tell the Firmware that we're shutting down the AdminQ and whether
390  * or not the driver is unloading as well.
391  **/
392 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
393 					     bool unloading)
394 {
395 	struct i40e_aq_desc desc;
396 	struct i40e_aqc_queue_shutdown *cmd =
397 		(struct i40e_aqc_queue_shutdown *)&desc.params.raw;
398 	enum i40e_status_code status;
399 
400 	i40e_fill_default_direct_cmd_desc(&desc,
401 					  i40e_aqc_opc_queue_shutdown);
402 
403 	if (unloading)
404 		cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
405 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
406 
407 	return status;
408 }
409 
410 /**
411  * i40e_aq_get_set_rss_lut
412  * @hw: pointer to the hardware structure
413  * @vsi_id: vsi fw index
414  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
415  * @lut: pointer to the lut buffer provided by the caller
416  * @lut_size: size of the lut buffer
417  * @set: set TRUE to set the table, FALSE to get the table
418  *
419  * Internal function to get or set RSS look up table
420  **/
421 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
422 						     u16 vsi_id, bool pf_lut,
423 						     u8 *lut, u16 lut_size,
424 						     bool set)
425 {
426 	enum i40e_status_code status;
427 	struct i40e_aq_desc desc;
428 	struct i40e_aqc_get_set_rss_lut *cmd_resp =
429 		   (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
430 
431 	if (set)
432 		i40e_fill_default_direct_cmd_desc(&desc,
433 						  i40e_aqc_opc_set_rss_lut);
434 	else
435 		i40e_fill_default_direct_cmd_desc(&desc,
436 						  i40e_aqc_opc_get_rss_lut);
437 
438 	/* Indirect command */
439 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
440 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
441 
442 	cmd_resp->vsi_id =
443 			CPU_TO_LE16((u16)((vsi_id <<
444 					  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
445 					  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
446 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
447 
448 	if (pf_lut)
449 		cmd_resp->flags |= CPU_TO_LE16((u16)
450 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
451 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
452 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
453 	else
454 		cmd_resp->flags |= CPU_TO_LE16((u16)
455 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
456 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
457 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
458 
459 	status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
460 
461 	return status;
462 }
463 
464 /**
465  * i40e_aq_get_rss_lut
466  * @hw: pointer to the hardware structure
467  * @vsi_id: vsi fw index
468  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
469  * @lut: pointer to the lut buffer provided by the caller
470  * @lut_size: size of the lut buffer
471  *
472  * get the RSS lookup table, PF or VSI type
473  **/
474 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
475 					  bool pf_lut, u8 *lut, u16 lut_size)
476 {
477 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
478 				       FALSE);
479 }
480 
481 /**
482  * i40e_aq_set_rss_lut
483  * @hw: pointer to the hardware structure
484  * @vsi_id: vsi fw index
485  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
486  * @lut: pointer to the lut buffer provided by the caller
487  * @lut_size: size of the lut buffer
488  *
489  * set the RSS lookup table, PF or VSI type
490  **/
491 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
492 					  bool pf_lut, u8 *lut, u16 lut_size)
493 {
494 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
495 }
496 
497 /**
498  * i40e_aq_get_set_rss_key
499  * @hw: pointer to the hw struct
500  * @vsi_id: vsi fw index
501  * @key: pointer to key info struct
502  * @set: set TRUE to set the key, FALSE to get the key
503  *
504  * get the RSS key per VSI
505  **/
506 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
507 				      u16 vsi_id,
508 				      struct i40e_aqc_get_set_rss_key_data *key,
509 				      bool set)
510 {
511 	enum i40e_status_code status;
512 	struct i40e_aq_desc desc;
513 	struct i40e_aqc_get_set_rss_key *cmd_resp =
514 			(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
515 	u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
516 
517 	if (set)
518 		i40e_fill_default_direct_cmd_desc(&desc,
519 						  i40e_aqc_opc_set_rss_key);
520 	else
521 		i40e_fill_default_direct_cmd_desc(&desc,
522 						  i40e_aqc_opc_get_rss_key);
523 
524 	/* Indirect command */
525 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
526 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
527 
528 	cmd_resp->vsi_id =
529 			CPU_TO_LE16((u16)((vsi_id <<
530 					  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
531 					  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
532 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
533 
534 	status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
535 
536 	return status;
537 }
538 
539 /**
540  * i40e_aq_get_rss_key
541  * @hw: pointer to the hw struct
542  * @vsi_id: vsi fw index
543  * @key: pointer to key info struct
544  *
545  **/
546 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
547 				      u16 vsi_id,
548 				      struct i40e_aqc_get_set_rss_key_data *key)
549 {
550 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
551 }
552 
553 /**
554  * i40e_aq_set_rss_key
555  * @hw: pointer to the hw struct
556  * @vsi_id: vsi fw index
557  * @key: pointer to key info struct
558  *
559  * set the RSS key per VSI
560  **/
561 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
562 				      u16 vsi_id,
563 				      struct i40e_aqc_get_set_rss_key_data *key)
564 {
565 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
566 }
567 
568 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
569  * hardware to a bit-field that can be used by SW to more easily determine the
570  * packet type.
571  *
572  * Macros are used to shorten the table lines and make this table human
573  * readable.
574  *
575  * We store the PTYPE in the top byte of the bit field - this is just so that
576  * we can check that the table doesn't have a row missing, as the index into
577  * the table should be the PTYPE.
578  *
579  * Typical work flow:
580  *
581  * IF NOT i40e_ptype_lookup[ptype].known
582  * THEN
583  *      Packet is unknown
584  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
585  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
586  * ELSE
587  *      Use the enum i40e_rx_l2_ptype to decode the packet type
588  * ENDIF
589  */
590 
591 /* macro to make the table lines short */
592 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
593 	{	PTYPE, \
594 		1, \
595 		I40E_RX_PTYPE_OUTER_##OUTER_IP, \
596 		I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
597 		I40E_RX_PTYPE_##OUTER_FRAG, \
598 		I40E_RX_PTYPE_TUNNEL_##T, \
599 		I40E_RX_PTYPE_TUNNEL_END_##TE, \
600 		I40E_RX_PTYPE_##TEF, \
601 		I40E_RX_PTYPE_INNER_PROT_##I, \
602 		I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
603 
604 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
605 		{ PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
606 
607 /* shorter macros makes the table fit but are terse */
608 #define I40E_RX_PTYPE_NOF		I40E_RX_PTYPE_NOT_FRAG
609 #define I40E_RX_PTYPE_FRG		I40E_RX_PTYPE_FRAG
610 #define I40E_RX_PTYPE_INNER_PROT_TS	I40E_RX_PTYPE_INNER_PROT_TIMESYNC
611 
612 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
613 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
614 	/* L2 Packet types */
615 	I40E_PTT_UNUSED_ENTRY(0),
616 	I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
617 	I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
618 	I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
619 	I40E_PTT_UNUSED_ENTRY(4),
620 	I40E_PTT_UNUSED_ENTRY(5),
621 	I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
622 	I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
623 	I40E_PTT_UNUSED_ENTRY(8),
624 	I40E_PTT_UNUSED_ENTRY(9),
625 	I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
626 	I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
627 	I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
628 	I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
629 	I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
630 	I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
631 	I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
632 	I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
633 	I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
634 	I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
635 	I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
636 	I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
637 
638 	/* Non Tunneled IPv4 */
639 	I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
640 	I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
641 	I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
642 	I40E_PTT_UNUSED_ENTRY(25),
643 	I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
644 	I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
645 	I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
646 
647 	/* IPv4 --> IPv4 */
648 	I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
649 	I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
650 	I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
651 	I40E_PTT_UNUSED_ENTRY(32),
652 	I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
653 	I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
654 	I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
655 
656 	/* IPv4 --> IPv6 */
657 	I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
658 	I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
659 	I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
660 	I40E_PTT_UNUSED_ENTRY(39),
661 	I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
662 	I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
663 	I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
664 
665 	/* IPv4 --> GRE/NAT */
666 	I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
667 
668 	/* IPv4 --> GRE/NAT --> IPv4 */
669 	I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
670 	I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
671 	I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
672 	I40E_PTT_UNUSED_ENTRY(47),
673 	I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
674 	I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
675 	I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
676 
677 	/* IPv4 --> GRE/NAT --> IPv6 */
678 	I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
679 	I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
680 	I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
681 	I40E_PTT_UNUSED_ENTRY(54),
682 	I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
683 	I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
684 	I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
685 
686 	/* IPv4 --> GRE/NAT --> MAC */
687 	I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
688 
689 	/* IPv4 --> GRE/NAT --> MAC --> IPv4 */
690 	I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
691 	I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
692 	I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
693 	I40E_PTT_UNUSED_ENTRY(62),
694 	I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
695 	I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
696 	I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
697 
698 	/* IPv4 --> GRE/NAT -> MAC --> IPv6 */
699 	I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
700 	I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
701 	I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
702 	I40E_PTT_UNUSED_ENTRY(69),
703 	I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
704 	I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
705 	I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
706 
707 	/* IPv4 --> GRE/NAT --> MAC/VLAN */
708 	I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
709 
710 	/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
711 	I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
712 	I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
713 	I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
714 	I40E_PTT_UNUSED_ENTRY(77),
715 	I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
716 	I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
717 	I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
718 
719 	/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
720 	I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
721 	I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
722 	I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
723 	I40E_PTT_UNUSED_ENTRY(84),
724 	I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
725 	I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
726 	I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
727 
728 	/* Non Tunneled IPv6 */
729 	I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
730 	I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
731 	I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
732 	I40E_PTT_UNUSED_ENTRY(91),
733 	I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
734 	I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
735 	I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
736 
737 	/* IPv6 --> IPv4 */
738 	I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
739 	I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
740 	I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
741 	I40E_PTT_UNUSED_ENTRY(98),
742 	I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
743 	I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
744 	I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
745 
746 	/* IPv6 --> IPv6 */
747 	I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
748 	I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
749 	I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
750 	I40E_PTT_UNUSED_ENTRY(105),
751 	I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
752 	I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
753 	I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
754 
755 	/* IPv6 --> GRE/NAT */
756 	I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
757 
758 	/* IPv6 --> GRE/NAT -> IPv4 */
759 	I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
760 	I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
761 	I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
762 	I40E_PTT_UNUSED_ENTRY(113),
763 	I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
764 	I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
765 	I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
766 
767 	/* IPv6 --> GRE/NAT -> IPv6 */
768 	I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
769 	I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
770 	I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
771 	I40E_PTT_UNUSED_ENTRY(120),
772 	I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
773 	I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
774 	I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
775 
776 	/* IPv6 --> GRE/NAT -> MAC */
777 	I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
778 
779 	/* IPv6 --> GRE/NAT -> MAC -> IPv4 */
780 	I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
781 	I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
782 	I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
783 	I40E_PTT_UNUSED_ENTRY(128),
784 	I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
785 	I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
786 	I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
787 
788 	/* IPv6 --> GRE/NAT -> MAC -> IPv6 */
789 	I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
790 	I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
791 	I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
792 	I40E_PTT_UNUSED_ENTRY(135),
793 	I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
794 	I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
795 	I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
796 
797 	/* IPv6 --> GRE/NAT -> MAC/VLAN */
798 	I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
799 
800 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
801 	I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
802 	I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
803 	I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
804 	I40E_PTT_UNUSED_ENTRY(143),
805 	I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
806 	I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
807 	I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
808 
809 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
810 	I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
811 	I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
812 	I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
813 	I40E_PTT_UNUSED_ENTRY(150),
814 	I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
815 	I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
816 	I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
817 
818 	/* unused entries */
819 	I40E_PTT_UNUSED_ENTRY(154),
820 	I40E_PTT_UNUSED_ENTRY(155),
821 	I40E_PTT_UNUSED_ENTRY(156),
822 	I40E_PTT_UNUSED_ENTRY(157),
823 	I40E_PTT_UNUSED_ENTRY(158),
824 	I40E_PTT_UNUSED_ENTRY(159),
825 
826 	I40E_PTT_UNUSED_ENTRY(160),
827 	I40E_PTT_UNUSED_ENTRY(161),
828 	I40E_PTT_UNUSED_ENTRY(162),
829 	I40E_PTT_UNUSED_ENTRY(163),
830 	I40E_PTT_UNUSED_ENTRY(164),
831 	I40E_PTT_UNUSED_ENTRY(165),
832 	I40E_PTT_UNUSED_ENTRY(166),
833 	I40E_PTT_UNUSED_ENTRY(167),
834 	I40E_PTT_UNUSED_ENTRY(168),
835 	I40E_PTT_UNUSED_ENTRY(169),
836 
837 	I40E_PTT_UNUSED_ENTRY(170),
838 	I40E_PTT_UNUSED_ENTRY(171),
839 	I40E_PTT_UNUSED_ENTRY(172),
840 	I40E_PTT_UNUSED_ENTRY(173),
841 	I40E_PTT_UNUSED_ENTRY(174),
842 	I40E_PTT_UNUSED_ENTRY(175),
843 	I40E_PTT_UNUSED_ENTRY(176),
844 	I40E_PTT_UNUSED_ENTRY(177),
845 	I40E_PTT_UNUSED_ENTRY(178),
846 	I40E_PTT_UNUSED_ENTRY(179),
847 
848 	I40E_PTT_UNUSED_ENTRY(180),
849 	I40E_PTT_UNUSED_ENTRY(181),
850 	I40E_PTT_UNUSED_ENTRY(182),
851 	I40E_PTT_UNUSED_ENTRY(183),
852 	I40E_PTT_UNUSED_ENTRY(184),
853 	I40E_PTT_UNUSED_ENTRY(185),
854 	I40E_PTT_UNUSED_ENTRY(186),
855 	I40E_PTT_UNUSED_ENTRY(187),
856 	I40E_PTT_UNUSED_ENTRY(188),
857 	I40E_PTT_UNUSED_ENTRY(189),
858 
859 	I40E_PTT_UNUSED_ENTRY(190),
860 	I40E_PTT_UNUSED_ENTRY(191),
861 	I40E_PTT_UNUSED_ENTRY(192),
862 	I40E_PTT_UNUSED_ENTRY(193),
863 	I40E_PTT_UNUSED_ENTRY(194),
864 	I40E_PTT_UNUSED_ENTRY(195),
865 	I40E_PTT_UNUSED_ENTRY(196),
866 	I40E_PTT_UNUSED_ENTRY(197),
867 	I40E_PTT_UNUSED_ENTRY(198),
868 	I40E_PTT_UNUSED_ENTRY(199),
869 
870 	I40E_PTT_UNUSED_ENTRY(200),
871 	I40E_PTT_UNUSED_ENTRY(201),
872 	I40E_PTT_UNUSED_ENTRY(202),
873 	I40E_PTT_UNUSED_ENTRY(203),
874 	I40E_PTT_UNUSED_ENTRY(204),
875 	I40E_PTT_UNUSED_ENTRY(205),
876 	I40E_PTT_UNUSED_ENTRY(206),
877 	I40E_PTT_UNUSED_ENTRY(207),
878 	I40E_PTT_UNUSED_ENTRY(208),
879 	I40E_PTT_UNUSED_ENTRY(209),
880 
881 	I40E_PTT_UNUSED_ENTRY(210),
882 	I40E_PTT_UNUSED_ENTRY(211),
883 	I40E_PTT_UNUSED_ENTRY(212),
884 	I40E_PTT_UNUSED_ENTRY(213),
885 	I40E_PTT_UNUSED_ENTRY(214),
886 	I40E_PTT_UNUSED_ENTRY(215),
887 	I40E_PTT_UNUSED_ENTRY(216),
888 	I40E_PTT_UNUSED_ENTRY(217),
889 	I40E_PTT_UNUSED_ENTRY(218),
890 	I40E_PTT_UNUSED_ENTRY(219),
891 
892 	I40E_PTT_UNUSED_ENTRY(220),
893 	I40E_PTT_UNUSED_ENTRY(221),
894 	I40E_PTT_UNUSED_ENTRY(222),
895 	I40E_PTT_UNUSED_ENTRY(223),
896 	I40E_PTT_UNUSED_ENTRY(224),
897 	I40E_PTT_UNUSED_ENTRY(225),
898 	I40E_PTT_UNUSED_ENTRY(226),
899 	I40E_PTT_UNUSED_ENTRY(227),
900 	I40E_PTT_UNUSED_ENTRY(228),
901 	I40E_PTT_UNUSED_ENTRY(229),
902 
903 	I40E_PTT_UNUSED_ENTRY(230),
904 	I40E_PTT_UNUSED_ENTRY(231),
905 	I40E_PTT_UNUSED_ENTRY(232),
906 	I40E_PTT_UNUSED_ENTRY(233),
907 	I40E_PTT_UNUSED_ENTRY(234),
908 	I40E_PTT_UNUSED_ENTRY(235),
909 	I40E_PTT_UNUSED_ENTRY(236),
910 	I40E_PTT_UNUSED_ENTRY(237),
911 	I40E_PTT_UNUSED_ENTRY(238),
912 	I40E_PTT_UNUSED_ENTRY(239),
913 
914 	I40E_PTT_UNUSED_ENTRY(240),
915 	I40E_PTT_UNUSED_ENTRY(241),
916 	I40E_PTT_UNUSED_ENTRY(242),
917 	I40E_PTT_UNUSED_ENTRY(243),
918 	I40E_PTT_UNUSED_ENTRY(244),
919 	I40E_PTT_UNUSED_ENTRY(245),
920 	I40E_PTT_UNUSED_ENTRY(246),
921 	I40E_PTT_UNUSED_ENTRY(247),
922 	I40E_PTT_UNUSED_ENTRY(248),
923 	I40E_PTT_UNUSED_ENTRY(249),
924 
925 	I40E_PTT_UNUSED_ENTRY(250),
926 	I40E_PTT_UNUSED_ENTRY(251),
927 	I40E_PTT_UNUSED_ENTRY(252),
928 	I40E_PTT_UNUSED_ENTRY(253),
929 	I40E_PTT_UNUSED_ENTRY(254),
930 	I40E_PTT_UNUSED_ENTRY(255)
931 };
932 
933 
934 /**
935  * i40e_validate_mac_addr - Validate unicast MAC address
936  * @mac_addr: pointer to MAC address
937  *
938  * Tests a MAC address to ensure it is a valid Individual Address
939  **/
940 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
941 {
942 	enum i40e_status_code status = I40E_SUCCESS;
943 
944 	DEBUGFUNC("i40e_validate_mac_addr");
945 
946 	/* Broadcast addresses ARE multicast addresses
947 	 * Make sure it is not a multicast address
948 	 * Reject the zero address
949 	 */
950 	if (I40E_IS_MULTICAST(mac_addr) ||
951 	    (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
952 	      mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
953 		status = I40E_ERR_INVALID_MAC_ADDR;
954 
955 	return status;
956 }
957 
958 /**
959  * i40e_init_shared_code - Initialize the shared code
960  * @hw: pointer to hardware structure
961  *
962  * This assigns the MAC type and PHY code and inits the NVM.
963  * Does not touch the hardware. This function must be called prior to any
964  * other function in the shared code. The i40e_hw structure should be
965  * memset to 0 prior to calling this function.  The following fields in
966  * hw structure should be filled in prior to calling this function:
967  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
968  * subsystem_vendor_id, and revision_id
969  **/
970 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
971 {
972 	enum i40e_status_code status = I40E_SUCCESS;
973 	u32 port, ari, func_rid;
974 
975 	DEBUGFUNC("i40e_init_shared_code");
976 
977 	i40e_set_mac_type(hw);
978 
979 	switch (hw->mac.type) {
980 	case I40E_MAC_XL710:
981 	case I40E_MAC_X722:
982 		break;
983 	default:
984 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
985 	}
986 
987 	hw->phy.get_link_info = TRUE;
988 
989 	/* Determine port number and PF number*/
990 	port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
991 					   >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
992 	hw->port = (u8)port;
993 	ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
994 						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
995 	func_rid = rd32(hw, I40E_PF_FUNC_RID);
996 	if (ari)
997 		hw->pf_id = (u8)(func_rid & 0xff);
998 	else
999 		hw->pf_id = (u8)(func_rid & 0x7);
1000 
1001 	if (hw->mac.type == I40E_MAC_X722)
1002 		hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1003 			     I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1004 
1005 	status = i40e_init_nvm(hw);
1006 	return status;
1007 }
1008 
1009 /**
1010  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1011  * @hw: pointer to the hw struct
1012  * @flags: a return indicator of what addresses were added to the addr store
1013  * @addrs: the requestor's mac addr store
1014  * @cmd_details: pointer to command details structure or NULL
1015  **/
1016 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1017 				   u16 *flags,
1018 				   struct i40e_aqc_mac_address_read_data *addrs,
1019 				   struct i40e_asq_cmd_details *cmd_details)
1020 {
1021 	struct i40e_aq_desc desc;
1022 	struct i40e_aqc_mac_address_read *cmd_data =
1023 		(struct i40e_aqc_mac_address_read *)&desc.params.raw;
1024 	enum i40e_status_code status;
1025 
1026 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1027 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1028 
1029 	status = i40e_asq_send_command(hw, &desc, addrs,
1030 				       sizeof(*addrs), cmd_details);
1031 	*flags = LE16_TO_CPU(cmd_data->command_flags);
1032 
1033 	return status;
1034 }
1035 
1036 /**
1037  * i40e_aq_mac_address_write - Change the MAC addresses
1038  * @hw: pointer to the hw struct
1039  * @flags: indicates which MAC to be written
1040  * @mac_addr: address to write
1041  * @cmd_details: pointer to command details structure or NULL
1042  **/
1043 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1044 				    u16 flags, u8 *mac_addr,
1045 				    struct i40e_asq_cmd_details *cmd_details)
1046 {
1047 	struct i40e_aq_desc desc;
1048 	struct i40e_aqc_mac_address_write *cmd_data =
1049 		(struct i40e_aqc_mac_address_write *)&desc.params.raw;
1050 	enum i40e_status_code status;
1051 
1052 	i40e_fill_default_direct_cmd_desc(&desc,
1053 					  i40e_aqc_opc_mac_address_write);
1054 	cmd_data->command_flags = CPU_TO_LE16(flags);
1055 	cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1056 	cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1057 					((u32)mac_addr[3] << 16) |
1058 					((u32)mac_addr[4] << 8) |
1059 					mac_addr[5]);
1060 
1061 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1062 
1063 	return status;
1064 }
1065 
1066 /**
1067  * i40e_get_mac_addr - get MAC address
1068  * @hw: pointer to the HW structure
1069  * @mac_addr: pointer to MAC address
1070  *
1071  * Reads the adapter's MAC address from register
1072  **/
1073 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1074 {
1075 	struct i40e_aqc_mac_address_read_data addrs;
1076 	enum i40e_status_code status;
1077 	u16 flags = 0;
1078 
1079 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1080 
1081 	if (flags & I40E_AQC_LAN_ADDR_VALID)
1082 		i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1083 			I40E_NONDMA_TO_NONDMA);
1084 
1085 	return status;
1086 }
1087 
1088 /**
1089  * i40e_get_port_mac_addr - get Port MAC address
1090  * @hw: pointer to the HW structure
1091  * @mac_addr: pointer to Port MAC address
1092  *
1093  * Reads the adapter's Port MAC address
1094  **/
1095 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1096 {
1097 	struct i40e_aqc_mac_address_read_data addrs;
1098 	enum i40e_status_code status;
1099 	u16 flags = 0;
1100 
1101 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1102 	if (status)
1103 		return status;
1104 
1105 	if (flags & I40E_AQC_PORT_ADDR_VALID)
1106 		i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1107 			I40E_NONDMA_TO_NONDMA);
1108 	else
1109 		status = I40E_ERR_INVALID_MAC_ADDR;
1110 
1111 	return status;
1112 }
1113 
1114 /**
1115  * i40e_pre_tx_queue_cfg - pre tx queue configure
1116  * @hw: pointer to the HW structure
1117  * @queue: target pf queue index
1118  * @enable: state change request
1119  *
1120  * Handles hw requirement to indicate intention to enable
1121  * or disable target queue.
1122  **/
1123 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1124 {
1125 	u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1126 	u32 reg_block = 0;
1127 	u32 reg_val;
1128 
1129 	if (abs_queue_idx >= 128) {
1130 		reg_block = abs_queue_idx / 128;
1131 		abs_queue_idx %= 128;
1132 	}
1133 
1134 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1135 	reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1136 	reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1137 
1138 	if (enable)
1139 		reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1140 	else
1141 		reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1142 
1143 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1144 }
1145 
1146 /**
1147  *  i40e_read_pba_string - Reads part number string from EEPROM
1148  *  @hw: pointer to hardware structure
1149  *  @pba_num: stores the part number string from the EEPROM
1150  *  @pba_num_size: part number string buffer length
1151  *
1152  *  Reads the part number string from the EEPROM.
1153  **/
1154 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1155 					    u32 pba_num_size)
1156 {
1157 	enum i40e_status_code status = I40E_SUCCESS;
1158 	u16 pba_word = 0;
1159 	u16 pba_size = 0;
1160 	u16 pba_ptr = 0;
1161 	u16 i = 0;
1162 
1163 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1164 	if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1165 		DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1166 		return status;
1167 	}
1168 
1169 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1170 	if (status != I40E_SUCCESS) {
1171 		DEBUGOUT("Failed to read PBA Block pointer.\n");
1172 		return status;
1173 	}
1174 
1175 	status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1176 	if (status != I40E_SUCCESS) {
1177 		DEBUGOUT("Failed to read PBA Block size.\n");
1178 		return status;
1179 	}
1180 
1181 	/* Subtract one to get PBA word count (PBA Size word is included in
1182 	 * total size)
1183 	 */
1184 	pba_size--;
1185 	if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1186 		DEBUGOUT("Buffer to small for PBA data.\n");
1187 		return I40E_ERR_PARAM;
1188 	}
1189 
1190 	for (i = 0; i < pba_size; i++) {
1191 		status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1192 		if (status != I40E_SUCCESS) {
1193 			DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1194 			return status;
1195 		}
1196 
1197 		pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1198 		pba_num[(i * 2) + 1] = pba_word & 0xFF;
1199 	}
1200 	pba_num[(pba_size * 2)] = '\0';
1201 
1202 	return status;
1203 }
1204 
1205 /**
1206  * i40e_get_media_type - Gets media type
1207  * @hw: pointer to the hardware structure
1208  **/
1209 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1210 {
1211 	enum i40e_media_type media;
1212 
1213 	switch (hw->phy.link_info.phy_type) {
1214 	case I40E_PHY_TYPE_10GBASE_SR:
1215 	case I40E_PHY_TYPE_10GBASE_LR:
1216 	case I40E_PHY_TYPE_1000BASE_SX:
1217 	case I40E_PHY_TYPE_1000BASE_LX:
1218 	case I40E_PHY_TYPE_40GBASE_SR4:
1219 	case I40E_PHY_TYPE_40GBASE_LR4:
1220 	case I40E_PHY_TYPE_25GBASE_LR:
1221 	case I40E_PHY_TYPE_25GBASE_SR:
1222 		media = I40E_MEDIA_TYPE_FIBER;
1223 		break;
1224 	case I40E_PHY_TYPE_100BASE_TX:
1225 	case I40E_PHY_TYPE_1000BASE_T:
1226 	case I40E_PHY_TYPE_10GBASE_T:
1227 		media = I40E_MEDIA_TYPE_BASET;
1228 		break;
1229 	case I40E_PHY_TYPE_10GBASE_CR1_CU:
1230 	case I40E_PHY_TYPE_40GBASE_CR4_CU:
1231 	case I40E_PHY_TYPE_10GBASE_CR1:
1232 	case I40E_PHY_TYPE_40GBASE_CR4:
1233 	case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1234 	case I40E_PHY_TYPE_40GBASE_AOC:
1235 	case I40E_PHY_TYPE_10GBASE_AOC:
1236 	case I40E_PHY_TYPE_25GBASE_CR:
1237 	case I40E_PHY_TYPE_25GBASE_AOC:
1238 	case I40E_PHY_TYPE_25GBASE_ACC:
1239 		media = I40E_MEDIA_TYPE_DA;
1240 		break;
1241 	case I40E_PHY_TYPE_1000BASE_KX:
1242 	case I40E_PHY_TYPE_10GBASE_KX4:
1243 	case I40E_PHY_TYPE_10GBASE_KR:
1244 	case I40E_PHY_TYPE_40GBASE_KR4:
1245 	case I40E_PHY_TYPE_20GBASE_KR2:
1246 	case I40E_PHY_TYPE_25GBASE_KR:
1247 		media = I40E_MEDIA_TYPE_BACKPLANE;
1248 		break;
1249 	case I40E_PHY_TYPE_SGMII:
1250 	case I40E_PHY_TYPE_XAUI:
1251 	case I40E_PHY_TYPE_XFI:
1252 	case I40E_PHY_TYPE_XLAUI:
1253 	case I40E_PHY_TYPE_XLPPI:
1254 	default:
1255 		media = I40E_MEDIA_TYPE_UNKNOWN;
1256 		break;
1257 	}
1258 
1259 	return media;
1260 }
1261 
1262 #define I40E_PF_RESET_WAIT_COUNT	200
1263 /**
1264  * i40e_pf_reset - Reset the PF
1265  * @hw: pointer to the hardware structure
1266  *
1267  * Assuming someone else has triggered a global reset,
1268  * assure the global reset is complete and then reset the PF
1269  **/
1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1271 {
1272 	u32 cnt = 0;
1273 	u32 cnt1 = 0;
1274 	u32 reg = 0;
1275 	u32 grst_del;
1276 
1277 	/* Poll for Global Reset steady state in case of recent GRST.
1278 	 * The grst delay value is in 100ms units, and we'll wait a
1279 	 * couple counts longer to be sure we don't just miss the end.
1280 	 */
1281 	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1282 			I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1283 			I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1284 
1285 	grst_del = grst_del * 20;
1286 
1287 	for (cnt = 0; cnt < grst_del; cnt++) {
1288 		reg = rd32(hw, I40E_GLGEN_RSTAT);
1289 		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1290 			break;
1291 		i40e_msec_delay(100);
1292 	}
1293 	if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1294 		DEBUGOUT("Global reset polling failed to complete.\n");
1295 		return I40E_ERR_RESET_FAILED;
1296 	}
1297 
1298 	/* Now Wait for the FW to be ready */
1299 	for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1300 		reg = rd32(hw, I40E_GLNVM_ULD);
1301 		reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1302 			I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1303 		if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1304 			    I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1305 			DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1306 			break;
1307 		}
1308 		i40e_msec_delay(10);
1309 	}
1310 	if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1311 		     I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1312 		DEBUGOUT("wait for FW Reset complete timedout\n");
1313 		DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1314 		return I40E_ERR_RESET_FAILED;
1315 	}
1316 
1317 	/* If there was a Global Reset in progress when we got here,
1318 	 * we don't need to do the PF Reset
1319 	 */
1320 	if (!cnt) {
1321 		u32 reg2 = 0;
1322 
1323 		reg = rd32(hw, I40E_PFGEN_CTRL);
1324 		wr32(hw, I40E_PFGEN_CTRL,
1325 		     (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1326 		for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1327 			reg = rd32(hw, I40E_PFGEN_CTRL);
1328 			if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1329 				break;
1330 			reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1331 			if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1332 				DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1333 				DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1334 				return I40E_ERR_NOT_READY;
1335 			}
1336 			i40e_msec_delay(1);
1337 		}
1338 		if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1339 			DEBUGOUT("PF reset polling failed to complete.\n");
1340 			return I40E_ERR_RESET_FAILED;
1341 		}
1342 	}
1343 
1344 	i40e_clear_pxe_mode(hw);
1345 
1346 
1347 	return I40E_SUCCESS;
1348 }
1349 
1350 /**
1351  * i40e_clear_hw - clear out any left over hw state
1352  * @hw: pointer to the hw struct
1353  *
1354  * Clear queues and interrupts, typically called at init time,
1355  * but after the capabilities have been found so we know how many
1356  * queues and msix vectors have been allocated.
1357  **/
1358 void i40e_clear_hw(struct i40e_hw *hw)
1359 {
1360 	u32 num_queues, base_queue;
1361 	u32 num_pf_int;
1362 	u32 num_vf_int;
1363 	u32 num_vfs;
1364 	u32 i, j;
1365 	u32 val;
1366 	u32 eol = 0x7ff;
1367 
1368 	/* get number of interrupts, queues, and vfs */
1369 	val = rd32(hw, I40E_GLPCI_CNF2);
1370 	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1371 			I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1372 	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1373 			I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1374 
1375 	val = rd32(hw, I40E_PFLAN_QALLOC);
1376 	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1377 			I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1378 	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1379 			I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1380 	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1381 		num_queues = (j - base_queue) + 1;
1382 	else
1383 		num_queues = 0;
1384 
1385 	val = rd32(hw, I40E_PF_VT_PFALLOC);
1386 	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1387 			I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1388 	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1389 			I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1390 	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1391 		num_vfs = (j - i) + 1;
1392 	else
1393 		num_vfs = 0;
1394 
1395 	/* stop all the interrupts */
1396 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1397 	val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1398 	for (i = 0; i < num_pf_int - 2; i++)
1399 		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1400 
1401 	/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1402 	val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1403 	wr32(hw, I40E_PFINT_LNKLST0, val);
1404 	for (i = 0; i < num_pf_int - 2; i++)
1405 		wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1406 	val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1407 	for (i = 0; i < num_vfs; i++)
1408 		wr32(hw, I40E_VPINT_LNKLST0(i), val);
1409 	for (i = 0; i < num_vf_int - 2; i++)
1410 		wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1411 
1412 	/* warn the HW of the coming Tx disables */
1413 	for (i = 0; i < num_queues; i++) {
1414 		u32 abs_queue_idx = base_queue + i;
1415 		u32 reg_block = 0;
1416 
1417 		if (abs_queue_idx >= 128) {
1418 			reg_block = abs_queue_idx / 128;
1419 			abs_queue_idx %= 128;
1420 		}
1421 
1422 		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1423 		val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1424 		val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1425 		val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1426 
1427 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1428 	}
1429 	i40e_usec_delay(400);
1430 
1431 	/* stop all the queues */
1432 	for (i = 0; i < num_queues; i++) {
1433 		wr32(hw, I40E_QINT_TQCTL(i), 0);
1434 		wr32(hw, I40E_QTX_ENA(i), 0);
1435 		wr32(hw, I40E_QINT_RQCTL(i), 0);
1436 		wr32(hw, I40E_QRX_ENA(i), 0);
1437 	}
1438 
1439 	/* short wait for all queue disables to settle */
1440 	i40e_usec_delay(50);
1441 }
1442 
1443 /**
1444  * i40e_clear_pxe_mode - clear pxe operations mode
1445  * @hw: pointer to the hw struct
1446  *
1447  * Make sure all PXE mode settings are cleared, including things
1448  * like descriptor fetch/write-back mode.
1449  **/
1450 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1451 {
1452 	if (i40e_check_asq_alive(hw))
1453 		i40e_aq_clear_pxe_mode(hw, NULL);
1454 }
1455 
1456 /**
1457  * i40e_led_is_mine - helper to find matching led
1458  * @hw: pointer to the hw struct
1459  * @idx: index into GPIO registers
1460  *
1461  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1462  */
1463 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1464 {
1465 	u32 gpio_val = 0;
1466 	u32 port;
1467 
1468 	if (!hw->func_caps.led[idx])
1469 		return 0;
1470 
1471 	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1472 	port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1473 		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1474 
1475 	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1476 	 * if it is not our port then ignore
1477 	 */
1478 	if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1479 	    (port != hw->port))
1480 		return 0;
1481 
1482 	return gpio_val;
1483 }
1484 
1485 #define I40E_COMBINED_ACTIVITY 0xA
1486 #define I40E_FILTER_ACTIVITY 0xE
1487 #define I40E_LINK_ACTIVITY 0xC
1488 #define I40E_MAC_ACTIVITY 0xD
1489 #define I40E_LED0 22
1490 
1491 /**
1492  * i40e_led_get - return current on/off mode
1493  * @hw: pointer to the hw struct
1494  *
1495  * The value returned is the 'mode' field as defined in the
1496  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1497  * values are variations of possible behaviors relating to
1498  * blink, link, and wire.
1499  **/
1500 u32 i40e_led_get(struct i40e_hw *hw)
1501 {
1502 	u32 current_mode = 0;
1503 	u32 mode = 0;
1504 	int i;
1505 
1506 	/* as per the documentation GPIO 22-29 are the LED
1507 	 * GPIO pins named LED0..LED7
1508 	 */
1509 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1510 		u32 gpio_val = i40e_led_is_mine(hw, i);
1511 
1512 		if (!gpio_val)
1513 			continue;
1514 
1515 		/* ignore gpio LED src mode entries related to the activity
1516 		 *  LEDs
1517 		 */
1518 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1519 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1520 		switch (current_mode) {
1521 		case I40E_COMBINED_ACTIVITY:
1522 		case I40E_FILTER_ACTIVITY:
1523 		case I40E_MAC_ACTIVITY:
1524 		case I40E_LINK_ACTIVITY:
1525 			continue;
1526 		default:
1527 			break;
1528 		}
1529 
1530 		mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1531 			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1532 		break;
1533 	}
1534 
1535 	return mode;
1536 }
1537 
1538 /**
1539  * i40e_led_set - set new on/off mode
1540  * @hw: pointer to the hw struct
1541  * @mode: 0=off, 0xf=on (else see manual for mode details)
1542  * @blink: TRUE if the LED should blink when on, FALSE if steady
1543  *
1544  * if this function is used to turn on the blink it should
1545  * be used to disable the blink when restoring the original state.
1546  **/
1547 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1548 {
1549 	u32 current_mode = 0;
1550 	int i;
1551 
1552 	if (mode & 0xfffffff0)
1553 		DEBUGOUT1("invalid mode passed in %X\n", mode);
1554 
1555 	/* as per the documentation GPIO 22-29 are the LED
1556 	 * GPIO pins named LED0..LED7
1557 	 */
1558 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1559 		u32 gpio_val = i40e_led_is_mine(hw, i);
1560 
1561 		if (!gpio_val)
1562 			continue;
1563 
1564 		/* ignore gpio LED src mode entries related to the activity
1565 		 * LEDs
1566 		 */
1567 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1568 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1569 		switch (current_mode) {
1570 		case I40E_COMBINED_ACTIVITY:
1571 		case I40E_FILTER_ACTIVITY:
1572 		case I40E_MAC_ACTIVITY:
1573 		case I40E_LINK_ACTIVITY:
1574 			continue;
1575 		default:
1576 			break;
1577 		}
1578 
1579 		gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1580 		/* this & is a bit of paranoia, but serves as a range check */
1581 		gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1582 			     I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1583 
1584 		if (blink)
1585 			gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1586 		else
1587 			gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1588 
1589 		wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1590 		break;
1591 	}
1592 }
1593 
1594 /* Admin command wrappers */
1595 
1596 /**
1597  * i40e_aq_get_phy_capabilities
1598  * @hw: pointer to the hw struct
1599  * @abilities: structure for PHY capabilities to be filled
1600  * @qualified_modules: report Qualified Modules
1601  * @report_init: report init capabilities (active are default)
1602  * @cmd_details: pointer to command details structure or NULL
1603  *
1604  * Returns the various PHY abilities supported on the Port.
1605  **/
1606 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1607 			bool qualified_modules, bool report_init,
1608 			struct i40e_aq_get_phy_abilities_resp *abilities,
1609 			struct i40e_asq_cmd_details *cmd_details)
1610 {
1611 	struct i40e_aq_desc desc;
1612 	enum i40e_status_code status;
1613 	u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1614 	u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1615 
1616 	if (!abilities)
1617 		return I40E_ERR_PARAM;
1618 
1619 	do {
1620 		i40e_fill_default_direct_cmd_desc(&desc,
1621 					       i40e_aqc_opc_get_phy_abilities);
1622 
1623 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1624 		if (abilities_size > I40E_AQ_LARGE_BUF)
1625 			desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1626 
1627 		if (qualified_modules)
1628 			desc.params.external.param0 |=
1629 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1630 
1631 		if (report_init)
1632 			desc.params.external.param0 |=
1633 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1634 
1635 		status = i40e_asq_send_command(hw, &desc, abilities,
1636 					       abilities_size, cmd_details);
1637 
1638 		if (status != I40E_SUCCESS)
1639 			break;
1640 
1641 		if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1642 			status = I40E_ERR_UNKNOWN_PHY;
1643 			break;
1644 		} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1645 			i40e_msec_delay(1);
1646 			total_delay++;
1647 			status = I40E_ERR_TIMEOUT;
1648 		}
1649 	} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1650 		 (total_delay < max_delay));
1651 
1652 	if (status != I40E_SUCCESS)
1653 		return status;
1654 
1655 	if (report_init) {
1656 		if (hw->mac.type ==  I40E_MAC_XL710 &&
1657 		    hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1658 		    hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1659 			status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1660 		} else {
1661 			hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1662 			hw->phy.phy_types |=
1663 					((u64)abilities->phy_type_ext << 32);
1664 		}
1665 	}
1666 
1667 	return status;
1668 }
1669 
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683 				struct i40e_aq_set_phy_config *config,
1684 				struct i40e_asq_cmd_details *cmd_details)
1685 {
1686 	struct i40e_aq_desc desc;
1687 	struct i40e_aq_set_phy_config *cmd =
1688 		(struct i40e_aq_set_phy_config *)&desc.params.raw;
1689 	enum i40e_status_code status;
1690 
1691 	if (!config)
1692 		return I40E_ERR_PARAM;
1693 
1694 	i40e_fill_default_direct_cmd_desc(&desc,
1695 					  i40e_aqc_opc_set_phy_config);
1696 
1697 	*cmd = *config;
1698 
1699 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700 
1701 	return status;
1702 }
1703 
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  * @aq_failures: buffer to return AdminQ failure information
1708  * @atomic_restart: whether to enable atomic link restart
1709  *
1710  * Set the requested flow control mode using set_phy_config.
1711  **/
1712 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1713 				  bool atomic_restart)
1714 {
1715 	enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1716 	struct i40e_aq_get_phy_abilities_resp abilities;
1717 	struct i40e_aq_set_phy_config config;
1718 	enum i40e_status_code status;
1719 	u8 pause_mask = 0x0;
1720 
1721 	*aq_failures = 0x0;
1722 
1723 	switch (fc_mode) {
1724 	case I40E_FC_FULL:
1725 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1726 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1727 		break;
1728 	case I40E_FC_RX_PAUSE:
1729 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1730 		break;
1731 	case I40E_FC_TX_PAUSE:
1732 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733 		break;
1734 	default:
1735 		break;
1736 	}
1737 
1738 	/* Get the current phy config */
1739 	status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1740 					      NULL);
1741 	if (status) {
1742 		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1743 		return status;
1744 	}
1745 
1746 	memset(&config, 0, sizeof(config));
1747 	/* clear the old pause settings */
1748 	config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1749 			   ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1750 	/* set the new abilities */
1751 	config.abilities |= pause_mask;
1752 	/* If the abilities have changed, then set the new config */
1753 	if (config.abilities != abilities.abilities) {
1754 		/* Auto restart link so settings take effect */
1755 		if (atomic_restart)
1756 			config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1757 		/* Copy over all the old settings */
1758 		config.phy_type = abilities.phy_type;
1759 		config.phy_type_ext = abilities.phy_type_ext;
1760 		config.link_speed = abilities.link_speed;
1761 		config.eee_capability = abilities.eee_capability;
1762 		config.eeer = abilities.eeer_val;
1763 		config.low_power_ctrl = abilities.d3_lpan;
1764 		status = i40e_aq_set_phy_config(hw, &config, NULL);
1765 
1766 		if (status)
1767 			*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1768 	}
1769 	/* Update the link info */
1770 	status = i40e_update_link_info(hw);
1771 	if (status) {
1772 		/* Wait a little bit (on 40G cards it sometimes takes a really
1773 		 * long time for link to come back from the atomic reset)
1774 		 * and try once more
1775 		 */
1776 		i40e_msec_delay(1000);
1777 		status = i40e_update_link_info(hw);
1778 	}
1779 	if (status)
1780 		*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1781 
1782 	return status;
1783 }
1784 
1785 /**
1786  * i40e_aq_set_mac_config
1787  * @hw: pointer to the hw struct
1788  * @max_frame_size: Maximum Frame Size to be supported by the port
1789  * @crc_en: Tell HW to append a CRC to outgoing frames
1790  * @pacing: Pacing configurations
1791  * @cmd_details: pointer to command details structure or NULL
1792  *
1793  * Configure MAC settings for frame size, jumbo frame support and the
1794  * addition of a CRC by the hardware.
1795  **/
1796 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1797 				u16 max_frame_size,
1798 				bool crc_en, u16 pacing,
1799 				struct i40e_asq_cmd_details *cmd_details)
1800 {
1801 	struct i40e_aq_desc desc;
1802 	struct i40e_aq_set_mac_config *cmd =
1803 		(struct i40e_aq_set_mac_config *)&desc.params.raw;
1804 	enum i40e_status_code status;
1805 
1806 	if (max_frame_size == 0)
1807 		return I40E_ERR_PARAM;
1808 
1809 	i40e_fill_default_direct_cmd_desc(&desc,
1810 					  i40e_aqc_opc_set_mac_config);
1811 
1812 	cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1813 	cmd->params = ((u8)pacing & 0x0F) << 3;
1814 	if (crc_en)
1815 		cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1816 
1817 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1818 
1819 	return status;
1820 }
1821 
1822 /**
1823  * i40e_aq_clear_pxe_mode
1824  * @hw: pointer to the hw struct
1825  * @cmd_details: pointer to command details structure or NULL
1826  *
1827  * Tell the firmware that the driver is taking over from PXE
1828  **/
1829 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1830 			struct i40e_asq_cmd_details *cmd_details)
1831 {
1832 	enum i40e_status_code status;
1833 	struct i40e_aq_desc desc;
1834 	struct i40e_aqc_clear_pxe *cmd =
1835 		(struct i40e_aqc_clear_pxe *)&desc.params.raw;
1836 
1837 	i40e_fill_default_direct_cmd_desc(&desc,
1838 					  i40e_aqc_opc_clear_pxe_mode);
1839 
1840 	cmd->rx_cnt = 0x2;
1841 
1842 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1843 
1844 	wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1845 
1846 	return status;
1847 }
1848 
1849 /**
1850  * i40e_aq_set_link_restart_an
1851  * @hw: pointer to the hw struct
1852  * @enable_link: if TRUE: enable link, if FALSE: disable link
1853  * @cmd_details: pointer to command details structure or NULL
1854  *
1855  * Sets up the link and restarts the Auto-Negotiation over the link.
1856  **/
1857 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1858 		bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1859 {
1860 	struct i40e_aq_desc desc;
1861 	struct i40e_aqc_set_link_restart_an *cmd =
1862 		(struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1863 	enum i40e_status_code status;
1864 
1865 	i40e_fill_default_direct_cmd_desc(&desc,
1866 					  i40e_aqc_opc_set_link_restart_an);
1867 
1868 	cmd->command = I40E_AQ_PHY_RESTART_AN;
1869 	if (enable_link)
1870 		cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1871 	else
1872 		cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1873 
1874 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1875 
1876 	return status;
1877 }
1878 
1879 /**
1880  * i40e_aq_get_link_info
1881  * @hw: pointer to the hw struct
1882  * @enable_lse: enable/disable LinkStatusEvent reporting
1883  * @link: pointer to link status structure - optional
1884  * @cmd_details: pointer to command details structure or NULL
1885  *
1886  * Returns the link status of the adapter.
1887  **/
1888 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1889 				bool enable_lse, struct i40e_link_status *link,
1890 				struct i40e_asq_cmd_details *cmd_details)
1891 {
1892 	struct i40e_aq_desc desc;
1893 	struct i40e_aqc_get_link_status *resp =
1894 		(struct i40e_aqc_get_link_status *)&desc.params.raw;
1895 	struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1896 	enum i40e_status_code status;
1897 	bool tx_pause, rx_pause;
1898 	u16 command_flags;
1899 
1900 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1901 
1902 	if (enable_lse)
1903 		command_flags = I40E_AQ_LSE_ENABLE;
1904 	else
1905 		command_flags = I40E_AQ_LSE_DISABLE;
1906 	resp->command_flags = CPU_TO_LE16(command_flags);
1907 
1908 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1909 
1910 	if (status != I40E_SUCCESS)
1911 		goto aq_get_link_info_exit;
1912 
1913 	/* save off old link status information */
1914 	i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1915 		    sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1916 
1917 	/* update link status */
1918 	hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1919 	hw->phy.media_type = i40e_get_media_type(hw);
1920 	hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1921 	hw_link_info->link_info = resp->link_info;
1922 	hw_link_info->an_info = resp->an_info;
1923 	hw_link_info->ext_info = resp->ext_info;
1924 	hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1925 	hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1926 	hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1927 
1928 	/* update fc info */
1929 	tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1930 	rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1931 	if (tx_pause & rx_pause)
1932 		hw->fc.current_mode = I40E_FC_FULL;
1933 	else if (tx_pause)
1934 		hw->fc.current_mode = I40E_FC_TX_PAUSE;
1935 	else if (rx_pause)
1936 		hw->fc.current_mode = I40E_FC_RX_PAUSE;
1937 	else
1938 		hw->fc.current_mode = I40E_FC_NONE;
1939 
1940 	if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1941 		hw_link_info->crc_enable = TRUE;
1942 	else
1943 		hw_link_info->crc_enable = FALSE;
1944 
1945 	if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1946 		hw_link_info->lse_enable = TRUE;
1947 	else
1948 		hw_link_info->lse_enable = FALSE;
1949 
1950 	if ((hw->mac.type == I40E_MAC_XL710) &&
1951 	    (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1952 	     hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1953 		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1954 
1955 	if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1956 	    hw->aq.api_min_ver >= 7) {
1957 		__le32 tmp;
1958 
1959 		i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
1960 			    I40E_NONDMA_TO_NONDMA);
1961 		hw->phy.phy_types = LE32_TO_CPU(tmp);
1962 		hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1963 	}
1964 
1965 	/* save link status information */
1966 	if (link)
1967 		i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1968 			    I40E_NONDMA_TO_NONDMA);
1969 
1970 	/* flag cleared so helper functions don't call AQ again */
1971 	hw->phy.get_link_info = FALSE;
1972 
1973 aq_get_link_info_exit:
1974 	return status;
1975 }
1976 
1977 /**
1978  * i40e_aq_set_phy_int_mask
1979  * @hw: pointer to the hw struct
1980  * @mask: interrupt mask to be set
1981  * @cmd_details: pointer to command details structure or NULL
1982  *
1983  * Set link interrupt mask.
1984  **/
1985 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1986 				u16 mask,
1987 				struct i40e_asq_cmd_details *cmd_details)
1988 {
1989 	struct i40e_aq_desc desc;
1990 	struct i40e_aqc_set_phy_int_mask *cmd =
1991 		(struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1992 	enum i40e_status_code status;
1993 
1994 	i40e_fill_default_direct_cmd_desc(&desc,
1995 					  i40e_aqc_opc_set_phy_int_mask);
1996 
1997 	cmd->event_mask = CPU_TO_LE16(mask);
1998 
1999 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2000 
2001 	return status;
2002 }
2003 
2004 /**
2005  * i40e_aq_get_local_advt_reg
2006  * @hw: pointer to the hw struct
2007  * @advt_reg: local AN advertisement register value
2008  * @cmd_details: pointer to command details structure or NULL
2009  *
2010  * Get the Local AN advertisement register value.
2011  **/
2012 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2013 				u64 *advt_reg,
2014 				struct i40e_asq_cmd_details *cmd_details)
2015 {
2016 	struct i40e_aq_desc desc;
2017 	struct i40e_aqc_an_advt_reg *resp =
2018 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2019 	enum i40e_status_code status;
2020 
2021 	i40e_fill_default_direct_cmd_desc(&desc,
2022 					  i40e_aqc_opc_get_local_advt_reg);
2023 
2024 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2025 
2026 	if (status != I40E_SUCCESS)
2027 		goto aq_get_local_advt_reg_exit;
2028 
2029 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2030 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2031 
2032 aq_get_local_advt_reg_exit:
2033 	return status;
2034 }
2035 
2036 /**
2037  * i40e_aq_set_local_advt_reg
2038  * @hw: pointer to the hw struct
2039  * @advt_reg: local AN advertisement register value
2040  * @cmd_details: pointer to command details structure or NULL
2041  *
2042  * Get the Local AN advertisement register value.
2043  **/
2044 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2045 				u64 advt_reg,
2046 				struct i40e_asq_cmd_details *cmd_details)
2047 {
2048 	struct i40e_aq_desc desc;
2049 	struct i40e_aqc_an_advt_reg *cmd =
2050 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2051 	enum i40e_status_code status;
2052 
2053 	i40e_fill_default_direct_cmd_desc(&desc,
2054 					  i40e_aqc_opc_get_local_advt_reg);
2055 
2056 	cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2057 	cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2058 
2059 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2060 
2061 	return status;
2062 }
2063 
2064 /**
2065  * i40e_aq_get_partner_advt
2066  * @hw: pointer to the hw struct
2067  * @advt_reg: AN partner advertisement register value
2068  * @cmd_details: pointer to command details structure or NULL
2069  *
2070  * Get the link partner AN advertisement register value.
2071  **/
2072 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2073 				u64 *advt_reg,
2074 				struct i40e_asq_cmd_details *cmd_details)
2075 {
2076 	struct i40e_aq_desc desc;
2077 	struct i40e_aqc_an_advt_reg *resp =
2078 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2079 	enum i40e_status_code status;
2080 
2081 	i40e_fill_default_direct_cmd_desc(&desc,
2082 					  i40e_aqc_opc_get_partner_advt);
2083 
2084 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2085 
2086 	if (status != I40E_SUCCESS)
2087 		goto aq_get_partner_advt_exit;
2088 
2089 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2090 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2091 
2092 aq_get_partner_advt_exit:
2093 	return status;
2094 }
2095 
2096 /**
2097  * i40e_aq_set_lb_modes
2098  * @hw: pointer to the hw struct
2099  * @lb_modes: loopback mode to be set
2100  * @cmd_details: pointer to command details structure or NULL
2101  *
2102  * Sets loopback modes.
2103  **/
2104 enum i40e_status_code
2105 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed,
2106 		     struct i40e_asq_cmd_details *cmd_details)
2107 {
2108 	struct i40e_aq_desc desc;
2109 	struct i40e_aqc_set_lb_mode *cmd =
2110 		(struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2111 	enum i40e_status_code status;
2112 
2113 	i40e_fill_default_direct_cmd_desc(&desc,
2114 					  i40e_aqc_opc_set_lb_modes);
2115 
2116 	cmd->lb_level = lb_level;
2117 	cmd->lb_type = lb_type;
2118 	cmd->speed = speed;
2119 	if (speed)
2120 		cmd->force_speed = 1;
2121 
2122 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2123 
2124 	return status;
2125 }
2126 
2127 /**
2128  * i40e_aq_set_phy_debug
2129  * @hw: pointer to the hw struct
2130  * @cmd_flags: debug command flags
2131  * @cmd_details: pointer to command details structure or NULL
2132  *
2133  * Reset the external PHY.
2134  **/
2135 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2136 				struct i40e_asq_cmd_details *cmd_details)
2137 {
2138 	struct i40e_aq_desc desc;
2139 	struct i40e_aqc_set_phy_debug *cmd =
2140 		(struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2141 	enum i40e_status_code status;
2142 
2143 	i40e_fill_default_direct_cmd_desc(&desc,
2144 					  i40e_aqc_opc_set_phy_debug);
2145 
2146 	cmd->command_flags = cmd_flags;
2147 
2148 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2149 
2150 	return status;
2151 }
2152 
2153 /**
2154  * i40e_aq_add_vsi
2155  * @hw: pointer to the hw struct
2156  * @vsi_ctx: pointer to a vsi context struct
2157  * @cmd_details: pointer to command details structure or NULL
2158  *
2159  * Add a VSI context to the hardware.
2160 **/
2161 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2162 				struct i40e_vsi_context *vsi_ctx,
2163 				struct i40e_asq_cmd_details *cmd_details)
2164 {
2165 	struct i40e_aq_desc desc;
2166 	struct i40e_aqc_add_get_update_vsi *cmd =
2167 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2168 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2169 		(struct i40e_aqc_add_get_update_vsi_completion *)
2170 		&desc.params.raw;
2171 	enum i40e_status_code status;
2172 
2173 	i40e_fill_default_direct_cmd_desc(&desc,
2174 					  i40e_aqc_opc_add_vsi);
2175 
2176 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2177 	cmd->connection_type = vsi_ctx->connection_type;
2178 	cmd->vf_id = vsi_ctx->vf_num;
2179 	cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2180 
2181 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2182 
2183 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2184 				    sizeof(vsi_ctx->info), cmd_details);
2185 
2186 	if (status != I40E_SUCCESS)
2187 		goto aq_add_vsi_exit;
2188 
2189 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2190 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2191 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2192 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2193 
2194 aq_add_vsi_exit:
2195 	return status;
2196 }
2197 
2198 /**
2199  * i40e_aq_set_default_vsi
2200  * @hw: pointer to the hw struct
2201  * @seid: vsi number
2202  * @cmd_details: pointer to command details structure or NULL
2203  **/
2204 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2205 				u16 seid,
2206 				struct i40e_asq_cmd_details *cmd_details)
2207 {
2208 	struct i40e_aq_desc desc;
2209 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2210 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2211 		&desc.params.raw;
2212 	enum i40e_status_code status;
2213 
2214 	i40e_fill_default_direct_cmd_desc(&desc,
2215 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2216 
2217 	cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2218 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2219 	cmd->seid = CPU_TO_LE16(seid);
2220 
2221 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2222 
2223 	return status;
2224 }
2225 
2226 /**
2227  * i40e_aq_clear_default_vsi
2228  * @hw: pointer to the hw struct
2229  * @seid: vsi number
2230  * @cmd_details: pointer to command details structure or NULL
2231  **/
2232 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2233 				u16 seid,
2234 				struct i40e_asq_cmd_details *cmd_details)
2235 {
2236 	struct i40e_aq_desc desc;
2237 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2238 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2239 		&desc.params.raw;
2240 	enum i40e_status_code status;
2241 
2242 	i40e_fill_default_direct_cmd_desc(&desc,
2243 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2244 
2245 	cmd->promiscuous_flags = CPU_TO_LE16(0);
2246 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2247 	cmd->seid = CPU_TO_LE16(seid);
2248 
2249 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2250 
2251 	return status;
2252 }
2253 
2254 /**
2255  * i40e_aq_set_vsi_unicast_promiscuous
2256  * @hw: pointer to the hw struct
2257  * @seid: vsi number
2258  * @set: set unicast promiscuous enable/disable
2259  * @cmd_details: pointer to command details structure or NULL
2260  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2261  **/
2262 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2263 				u16 seid, bool set,
2264 				struct i40e_asq_cmd_details *cmd_details,
2265 				bool rx_only_promisc)
2266 {
2267 	struct i40e_aq_desc desc;
2268 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2269 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2270 	enum i40e_status_code status;
2271 	u16 flags = 0;
2272 
2273 	i40e_fill_default_direct_cmd_desc(&desc,
2274 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2275 
2276 	if (set) {
2277 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2278 		if (rx_only_promisc &&
2279 		    (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2280 		     (hw->aq.api_maj_ver > 1)))
2281 			flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2282 	}
2283 
2284 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2285 
2286 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2287 	if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2288 	     (hw->aq.api_maj_ver > 1))
2289 		cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2290 
2291 	cmd->seid = CPU_TO_LE16(seid);
2292 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2293 
2294 	return status;
2295 }
2296 
2297 /**
2298  * i40e_aq_set_vsi_multicast_promiscuous
2299  * @hw: pointer to the hw struct
2300  * @seid: vsi number
2301  * @set: set multicast promiscuous enable/disable
2302  * @cmd_details: pointer to command details structure or NULL
2303  **/
2304 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2305 				u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2306 {
2307 	struct i40e_aq_desc desc;
2308 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2309 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2310 	enum i40e_status_code status;
2311 	u16 flags = 0;
2312 
2313 	i40e_fill_default_direct_cmd_desc(&desc,
2314 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2315 
2316 	if (set)
2317 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2318 
2319 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2320 
2321 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2322 
2323 	cmd->seid = CPU_TO_LE16(seid);
2324 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2325 
2326 	return status;
2327 }
2328 
2329 /**
2330  * i40e_aq_set_vsi_mc_promisc_on_vlan
2331  * @hw: pointer to the hw struct
2332  * @seid: vsi number
2333  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2334  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2335  * @cmd_details: pointer to command details structure or NULL
2336  **/
2337 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2338 				u16 seid, bool enable, u16 vid,
2339 				struct i40e_asq_cmd_details *cmd_details)
2340 {
2341 	struct i40e_aq_desc desc;
2342 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2343 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2344 	enum i40e_status_code status;
2345 	u16 flags = 0;
2346 
2347 	i40e_fill_default_direct_cmd_desc(&desc,
2348 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2349 
2350 	if (enable)
2351 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2352 
2353 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2354 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2355 	cmd->seid = CPU_TO_LE16(seid);
2356 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2357 
2358 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2359 
2360 	return status;
2361 }
2362 
2363 /**
2364  * i40e_aq_set_vsi_uc_promisc_on_vlan
2365  * @hw: pointer to the hw struct
2366  * @seid: vsi number
2367  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2368  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2369  * @cmd_details: pointer to command details structure or NULL
2370  **/
2371 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2372 				u16 seid, bool enable, u16 vid,
2373 				struct i40e_asq_cmd_details *cmd_details)
2374 {
2375 	struct i40e_aq_desc desc;
2376 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2377 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2378 	enum i40e_status_code status;
2379 	u16 flags = 0;
2380 
2381 	i40e_fill_default_direct_cmd_desc(&desc,
2382 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2383 
2384 	if (enable)
2385 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2386 
2387 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2388 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2389 	cmd->seid = CPU_TO_LE16(seid);
2390 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2391 
2392 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2393 
2394 	return status;
2395 }
2396 
2397 /**
2398  * i40e_aq_set_vsi_bc_promisc_on_vlan
2399  * @hw: pointer to the hw struct
2400  * @seid: vsi number
2401  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2402  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2403  * @cmd_details: pointer to command details structure or NULL
2404  **/
2405 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2406 				u16 seid, bool enable, u16 vid,
2407 				struct i40e_asq_cmd_details *cmd_details)
2408 {
2409 	struct i40e_aq_desc desc;
2410 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2411 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2412 	enum i40e_status_code status;
2413 	u16 flags = 0;
2414 
2415 	i40e_fill_default_direct_cmd_desc(&desc,
2416 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2417 
2418 	if (enable)
2419 		flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2420 
2421 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2422 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2423 	cmd->seid = CPU_TO_LE16(seid);
2424 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2425 
2426 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2427 
2428 	return status;
2429 }
2430 
2431 /**
2432  * i40e_aq_set_vsi_broadcast
2433  * @hw: pointer to the hw struct
2434  * @seid: vsi number
2435  * @set_filter: TRUE to set filter, FALSE to clear filter
2436  * @cmd_details: pointer to command details structure or NULL
2437  *
2438  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2439  **/
2440 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2441 				u16 seid, bool set_filter,
2442 				struct i40e_asq_cmd_details *cmd_details)
2443 {
2444 	struct i40e_aq_desc desc;
2445 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2446 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2447 	enum i40e_status_code status;
2448 
2449 	i40e_fill_default_direct_cmd_desc(&desc,
2450 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2451 
2452 	if (set_filter)
2453 		cmd->promiscuous_flags
2454 			    |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2455 	else
2456 		cmd->promiscuous_flags
2457 			    &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2458 
2459 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2460 	cmd->seid = CPU_TO_LE16(seid);
2461 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2462 
2463 	return status;
2464 }
2465 
2466 /**
2467  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2468  * @hw: pointer to the hw struct
2469  * @seid: vsi number
2470  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2471  * @cmd_details: pointer to command details structure or NULL
2472  **/
2473 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2474 				u16 seid, bool enable,
2475 				struct i40e_asq_cmd_details *cmd_details)
2476 {
2477 	struct i40e_aq_desc desc;
2478 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2479 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2480 	enum i40e_status_code status;
2481 	u16 flags = 0;
2482 
2483 	i40e_fill_default_direct_cmd_desc(&desc,
2484 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2485 	if (enable)
2486 		flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2487 
2488 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2489 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2490 	cmd->seid = CPU_TO_LE16(seid);
2491 
2492 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2493 
2494 	return status;
2495 }
2496 
2497 /**
2498  * i40e_get_vsi_params - get VSI configuration info
2499  * @hw: pointer to the hw struct
2500  * @vsi_ctx: pointer to a vsi context struct
2501  * @cmd_details: pointer to command details structure or NULL
2502  **/
2503 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2504 				struct i40e_vsi_context *vsi_ctx,
2505 				struct i40e_asq_cmd_details *cmd_details)
2506 {
2507 	struct i40e_aq_desc desc;
2508 	struct i40e_aqc_add_get_update_vsi *cmd =
2509 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2510 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2511 		(struct i40e_aqc_add_get_update_vsi_completion *)
2512 		&desc.params.raw;
2513 	enum i40e_status_code status;
2514 
2515 	i40e_fill_default_direct_cmd_desc(&desc,
2516 					  i40e_aqc_opc_get_vsi_parameters);
2517 
2518 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2519 
2520 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2521 
2522 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2523 				    sizeof(vsi_ctx->info), NULL);
2524 
2525 	if (status != I40E_SUCCESS)
2526 		goto aq_get_vsi_params_exit;
2527 
2528 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2529 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2530 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2531 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2532 
2533 aq_get_vsi_params_exit:
2534 	return status;
2535 }
2536 
2537 /**
2538  * i40e_aq_update_vsi_params
2539  * @hw: pointer to the hw struct
2540  * @vsi_ctx: pointer to a vsi context struct
2541  * @cmd_details: pointer to command details structure or NULL
2542  *
2543  * Update a VSI context.
2544  **/
2545 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2546 				struct i40e_vsi_context *vsi_ctx,
2547 				struct i40e_asq_cmd_details *cmd_details)
2548 {
2549 	struct i40e_aq_desc desc;
2550 	struct i40e_aqc_add_get_update_vsi *cmd =
2551 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2552 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2553 		(struct i40e_aqc_add_get_update_vsi_completion *)
2554 		&desc.params.raw;
2555 	enum i40e_status_code status;
2556 
2557 	i40e_fill_default_direct_cmd_desc(&desc,
2558 					  i40e_aqc_opc_update_vsi_parameters);
2559 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2560 
2561 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2562 
2563 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2564 				    sizeof(vsi_ctx->info), cmd_details);
2565 
2566 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2567 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2568 
2569 	return status;
2570 }
2571 
2572 /**
2573  * i40e_aq_get_switch_config
2574  * @hw: pointer to the hardware structure
2575  * @buf: pointer to the result buffer
2576  * @buf_size: length of input buffer
2577  * @start_seid: seid to start for the report, 0 == beginning
2578  * @cmd_details: pointer to command details structure or NULL
2579  *
2580  * Fill the buf with switch configuration returned from AdminQ command
2581  **/
2582 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2583 				struct i40e_aqc_get_switch_config_resp *buf,
2584 				u16 buf_size, u16 *start_seid,
2585 				struct i40e_asq_cmd_details *cmd_details)
2586 {
2587 	struct i40e_aq_desc desc;
2588 	struct i40e_aqc_switch_seid *scfg =
2589 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
2590 	enum i40e_status_code status;
2591 
2592 	i40e_fill_default_direct_cmd_desc(&desc,
2593 					  i40e_aqc_opc_get_switch_config);
2594 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2595 	if (buf_size > I40E_AQ_LARGE_BUF)
2596 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2597 	scfg->seid = CPU_TO_LE16(*start_seid);
2598 
2599 	status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2600 	*start_seid = LE16_TO_CPU(scfg->seid);
2601 
2602 	return status;
2603 }
2604 
2605 /**
2606  * i40e_aq_set_switch_config
2607  * @hw: pointer to the hardware structure
2608  * @flags: bit flag values to set
2609  * @mode: cloud filter mode
2610  * @valid_flags: which bit flags to set
2611  * @cmd_details: pointer to command details structure or NULL
2612  *
2613  * Set switch configuration bits
2614  **/
2615 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2616 				u16 flags, u16 valid_flags, u8 mode,
2617 				struct i40e_asq_cmd_details *cmd_details)
2618 {
2619 	struct i40e_aq_desc desc;
2620 	struct i40e_aqc_set_switch_config *scfg =
2621 		(struct i40e_aqc_set_switch_config *)&desc.params.raw;
2622 	enum i40e_status_code status;
2623 
2624 	i40e_fill_default_direct_cmd_desc(&desc,
2625 					  i40e_aqc_opc_set_switch_config);
2626 	scfg->flags = CPU_TO_LE16(flags);
2627 	scfg->valid_flags = CPU_TO_LE16(valid_flags);
2628 	scfg->mode = mode;
2629 	if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2630 		scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2631 		scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2632 		scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2633 	}
2634 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2635 
2636 	return status;
2637 }
2638 
2639 /**
2640  * i40e_aq_get_firmware_version
2641  * @hw: pointer to the hw struct
2642  * @fw_major_version: firmware major version
2643  * @fw_minor_version: firmware minor version
2644  * @fw_build: firmware build number
2645  * @api_major_version: major queue version
2646  * @api_minor_version: minor queue version
2647  * @cmd_details: pointer to command details structure or NULL
2648  *
2649  * Get the firmware version from the admin queue commands
2650  **/
2651 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2652 				u16 *fw_major_version, u16 *fw_minor_version,
2653 				u32 *fw_build,
2654 				u16 *api_major_version, u16 *api_minor_version,
2655 				struct i40e_asq_cmd_details *cmd_details)
2656 {
2657 	struct i40e_aq_desc desc;
2658 	struct i40e_aqc_get_version *resp =
2659 		(struct i40e_aqc_get_version *)&desc.params.raw;
2660 	enum i40e_status_code status;
2661 
2662 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2663 
2664 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2665 
2666 	if (status == I40E_SUCCESS) {
2667 		if (fw_major_version != NULL)
2668 			*fw_major_version = LE16_TO_CPU(resp->fw_major);
2669 		if (fw_minor_version != NULL)
2670 			*fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2671 		if (fw_build != NULL)
2672 			*fw_build = LE32_TO_CPU(resp->fw_build);
2673 		if (api_major_version != NULL)
2674 			*api_major_version = LE16_TO_CPU(resp->api_major);
2675 		if (api_minor_version != NULL)
2676 			*api_minor_version = LE16_TO_CPU(resp->api_minor);
2677 
2678 		/* A workaround to fix the API version in SW */
2679 		if (api_major_version && api_minor_version &&
2680 		    fw_major_version && fw_minor_version &&
2681 		    ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2682 		    (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2683 		     (*fw_major_version > 4)))
2684 			*api_minor_version = 2;
2685 	}
2686 
2687 	return status;
2688 }
2689 
2690 /**
2691  * i40e_aq_send_driver_version
2692  * @hw: pointer to the hw struct
2693  * @dv: driver's major, minor version
2694  * @cmd_details: pointer to command details structure or NULL
2695  *
2696  * Send the driver version to the firmware
2697  **/
2698 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2699 				struct i40e_driver_version *dv,
2700 				struct i40e_asq_cmd_details *cmd_details)
2701 {
2702 	struct i40e_aq_desc desc;
2703 	struct i40e_aqc_driver_version *cmd =
2704 		(struct i40e_aqc_driver_version *)&desc.params.raw;
2705 	enum i40e_status_code status;
2706 	u16 len;
2707 
2708 	if (dv == NULL)
2709 		return I40E_ERR_PARAM;
2710 
2711 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2712 
2713 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2714 	cmd->driver_major_ver = dv->major_version;
2715 	cmd->driver_minor_ver = dv->minor_version;
2716 	cmd->driver_build_ver = dv->build_version;
2717 	cmd->driver_subbuild_ver = dv->subbuild_version;
2718 
2719 	len = 0;
2720 	while (len < sizeof(dv->driver_string) &&
2721 	       (dv->driver_string[len] < 0x80) &&
2722 	       dv->driver_string[len])
2723 		len++;
2724 	status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2725 				       len, cmd_details);
2726 
2727 	return status;
2728 }
2729 
2730 /**
2731  * i40e_get_link_status - get status of the HW network link
2732  * @hw: pointer to the hw struct
2733  * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2734  *
2735  * Variable link_up TRUE if link is up, FALSE if link is down.
2736  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2737  *
2738  * Side effect: LinkStatusEvent reporting becomes enabled
2739  **/
2740 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2741 {
2742 	enum i40e_status_code status = I40E_SUCCESS;
2743 
2744 	if (hw->phy.get_link_info) {
2745 		status = i40e_update_link_info(hw);
2746 
2747 		if (status != I40E_SUCCESS)
2748 			i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2749 				   status);
2750 	}
2751 
2752 	*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2753 
2754 	return status;
2755 }
2756 
2757 /**
2758  * i40e_updatelink_status - update status of the HW network link
2759  * @hw: pointer to the hw struct
2760  **/
2761 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2762 {
2763 	struct i40e_aq_get_phy_abilities_resp abilities;
2764 	enum i40e_status_code status = I40E_SUCCESS;
2765 
2766 	status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2767 	if (status)
2768 		return status;
2769 
2770 	/* extra checking needed to ensure link info to user is timely */
2771 	if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2772 	    ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2773 	     !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2774 		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
2775 						      &abilities, NULL);
2776 		if (status)
2777 			return status;
2778 
2779 		hw->phy.link_info.req_fec_info =
2780 			abilities.fec_cfg_curr_mod_ext_info &
2781 			(I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2782 
2783 		i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2784 			sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2785 	}
2786 	return status;
2787 }
2788 
2789 
2790 /**
2791  * i40e_get_link_speed
2792  * @hw: pointer to the hw struct
2793  *
2794  * Returns the link speed of the adapter.
2795  **/
2796 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2797 {
2798 	enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2799 	enum i40e_status_code status = I40E_SUCCESS;
2800 
2801 	if (hw->phy.get_link_info) {
2802 		status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2803 
2804 		if (status != I40E_SUCCESS)
2805 			goto i40e_link_speed_exit;
2806 	}
2807 
2808 	speed = hw->phy.link_info.link_speed;
2809 
2810 i40e_link_speed_exit:
2811 	return speed;
2812 }
2813 
2814 /**
2815  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2816  * @hw: pointer to the hw struct
2817  * @uplink_seid: the MAC or other gizmo SEID
2818  * @downlink_seid: the VSI SEID
2819  * @enabled_tc: bitmap of TCs to be enabled
2820  * @default_port: TRUE for default port VSI, FALSE for control port
2821  * @veb_seid: pointer to where to put the resulting VEB SEID
2822  * @enable_stats: TRUE to turn on VEB stats
2823  * @cmd_details: pointer to command details structure or NULL
2824  *
2825  * This asks the FW to add a VEB between the uplink and downlink
2826  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2827  **/
2828 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2829 				u16 downlink_seid, u8 enabled_tc,
2830 				bool default_port, u16 *veb_seid,
2831 				bool enable_stats,
2832 				struct i40e_asq_cmd_details *cmd_details)
2833 {
2834 	struct i40e_aq_desc desc;
2835 	struct i40e_aqc_add_veb *cmd =
2836 		(struct i40e_aqc_add_veb *)&desc.params.raw;
2837 	struct i40e_aqc_add_veb_completion *resp =
2838 		(struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2839 	enum i40e_status_code status;
2840 	u16 veb_flags = 0;
2841 
2842 	/* SEIDs need to either both be set or both be 0 for floating VEB */
2843 	if (!!uplink_seid != !!downlink_seid)
2844 		return I40E_ERR_PARAM;
2845 
2846 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2847 
2848 	cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2849 	cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2850 	cmd->enable_tcs = enabled_tc;
2851 	if (!uplink_seid)
2852 		veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2853 	if (default_port)
2854 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2855 	else
2856 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2857 
2858 	/* reverse logic here: set the bitflag to disable the stats */
2859 	if (!enable_stats)
2860 		veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2861 
2862 	cmd->veb_flags = CPU_TO_LE16(veb_flags);
2863 
2864 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2865 
2866 	if (!status && veb_seid)
2867 		*veb_seid = LE16_TO_CPU(resp->veb_seid);
2868 
2869 	return status;
2870 }
2871 
2872 /**
2873  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2874  * @hw: pointer to the hw struct
2875  * @veb_seid: the SEID of the VEB to query
2876  * @switch_id: the uplink switch id
2877  * @floating: set to TRUE if the VEB is floating
2878  * @statistic_index: index of the stats counter block for this VEB
2879  * @vebs_used: number of VEB's used by function
2880  * @vebs_free: total VEB's not reserved by any function
2881  * @cmd_details: pointer to command details structure or NULL
2882  *
2883  * This retrieves the parameters for a particular VEB, specified by
2884  * uplink_seid, and returns them to the caller.
2885  **/
2886 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2887 				u16 veb_seid, u16 *switch_id,
2888 				bool *floating, u16 *statistic_index,
2889 				u16 *vebs_used, u16 *vebs_free,
2890 				struct i40e_asq_cmd_details *cmd_details)
2891 {
2892 	struct i40e_aq_desc desc;
2893 	struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2894 		(struct i40e_aqc_get_veb_parameters_completion *)
2895 		&desc.params.raw;
2896 	enum i40e_status_code status;
2897 
2898 	if (veb_seid == 0)
2899 		return I40E_ERR_PARAM;
2900 
2901 	i40e_fill_default_direct_cmd_desc(&desc,
2902 					  i40e_aqc_opc_get_veb_parameters);
2903 	cmd_resp->seid = CPU_TO_LE16(veb_seid);
2904 
2905 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2906 	if (status)
2907 		goto get_veb_exit;
2908 
2909 	if (switch_id)
2910 		*switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2911 	if (statistic_index)
2912 		*statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2913 	if (vebs_used)
2914 		*vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2915 	if (vebs_free)
2916 		*vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2917 	if (floating) {
2918 		u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2919 
2920 		if (flags & I40E_AQC_ADD_VEB_FLOATING)
2921 			*floating = TRUE;
2922 		else
2923 			*floating = FALSE;
2924 	}
2925 
2926 get_veb_exit:
2927 	return status;
2928 }
2929 
2930 /**
2931  * i40e_aq_add_macvlan
2932  * @hw: pointer to the hw struct
2933  * @seid: VSI for the mac address
2934  * @mv_list: list of macvlans to be added
2935  * @count: length of the list
2936  * @cmd_details: pointer to command details structure or NULL
2937  *
2938  * Add MAC/VLAN addresses to the HW filtering
2939  **/
2940 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2941 			struct i40e_aqc_add_macvlan_element_data *mv_list,
2942 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2943 {
2944 	struct i40e_aq_desc desc;
2945 	struct i40e_aqc_macvlan *cmd =
2946 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2947 	enum i40e_status_code status;
2948 	u16 buf_size;
2949 	int i;
2950 
2951 	if (count == 0 || !mv_list || !hw)
2952 		return I40E_ERR_PARAM;
2953 
2954 	buf_size = count * sizeof(*mv_list);
2955 
2956 	/* prep the rest of the request */
2957 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2958 	cmd->num_addresses = CPU_TO_LE16(count);
2959 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2960 	cmd->seid[1] = 0;
2961 	cmd->seid[2] = 0;
2962 
2963 	for (i = 0; i < count; i++)
2964 		if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2965 			mv_list[i].flags |=
2966 			    CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2967 
2968 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2969 	if (buf_size > I40E_AQ_LARGE_BUF)
2970 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2971 
2972 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2973 				       cmd_details);
2974 
2975 	return status;
2976 }
2977 
2978 /**
2979  * i40e_aq_remove_macvlan
2980  * @hw: pointer to the hw struct
2981  * @seid: VSI for the mac address
2982  * @mv_list: list of macvlans to be removed
2983  * @count: length of the list
2984  * @cmd_details: pointer to command details structure or NULL
2985  *
2986  * Remove MAC/VLAN addresses from the HW filtering
2987  **/
2988 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2989 			struct i40e_aqc_remove_macvlan_element_data *mv_list,
2990 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2991 {
2992 	struct i40e_aq_desc desc;
2993 	struct i40e_aqc_macvlan *cmd =
2994 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2995 	enum i40e_status_code status;
2996 	u16 buf_size;
2997 
2998 	if (count == 0 || !mv_list || !hw)
2999 		return I40E_ERR_PARAM;
3000 
3001 	buf_size = count * sizeof(*mv_list);
3002 
3003 	/* prep the rest of the request */
3004 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3005 	cmd->num_addresses = CPU_TO_LE16(count);
3006 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3007 	cmd->seid[1] = 0;
3008 	cmd->seid[2] = 0;
3009 
3010 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3011 	if (buf_size > I40E_AQ_LARGE_BUF)
3012 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3013 
3014 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3015 				       cmd_details);
3016 
3017 	return status;
3018 }
3019 
3020 /**
3021  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3022  * @hw: pointer to the hw struct
3023  * @opcode: AQ opcode for add or delete mirror rule
3024  * @sw_seid: Switch SEID (to which rule refers)
3025  * @rule_type: Rule Type (ingress/egress/VLAN)
3026  * @id: Destination VSI SEID or Rule ID
3027  * @count: length of the list
3028  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3029  * @cmd_details: pointer to command details structure or NULL
3030  * @rule_id: Rule ID returned from FW
3031  * @rules_used: Number of rules used in internal switch
3032  * @rules_free: Number of rules free in internal switch
3033  *
3034  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3035  * VEBs/VEPA elements only
3036  **/
3037 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3038 			u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3039 			u16 count, __le16 *mr_list,
3040 			struct i40e_asq_cmd_details *cmd_details,
3041 			u16 *rule_id, u16 *rules_used, u16 *rules_free)
3042 {
3043 	struct i40e_aq_desc desc;
3044 	struct i40e_aqc_add_delete_mirror_rule *cmd =
3045 		(struct i40e_aqc_add_delete_mirror_rule *)&desc.