1 /****************************************************************************** 2 3 Copyright (c) 2013-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #include "i40e_type.h" 36 #include "i40e_adminq.h" 37 #include "i40e_prototype.h" 38 #include "i40e_virtchnl.h" 39 40 41 /** 42 * i40e_set_mac_type - Sets MAC type 43 * @hw: pointer to the HW structure 44 * 45 * This function sets the mac type of the adapter based on the 46 * vendor ID and device ID stored in the hw structure. 47 **/ 48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw) 49 { 50 enum i40e_status_code status = I40E_SUCCESS; 51 52 DEBUGFUNC("i40e_set_mac_type\n"); 53 54 if (hw->vendor_id == I40E_INTEL_VENDOR_ID) { 55 switch (hw->device_id) { 56 case I40E_DEV_ID_SFP_XL710: 57 case I40E_DEV_ID_QEMU: 58 case I40E_DEV_ID_KX_B: 59 case I40E_DEV_ID_KX_C: 60 case I40E_DEV_ID_QSFP_A: 61 case I40E_DEV_ID_QSFP_B: 62 case I40E_DEV_ID_QSFP_C: 63 case I40E_DEV_ID_10G_BASE_T: 64 case I40E_DEV_ID_10G_BASE_T4: 65 case I40E_DEV_ID_20G_KR2: 66 case I40E_DEV_ID_20G_KR2_A: 67 case I40E_DEV_ID_25G_B: 68 case I40E_DEV_ID_25G_SFP28: 69 hw->mac.type = I40E_MAC_XL710; 70 break; 71 case I40E_DEV_ID_X722_A0: 72 case I40E_DEV_ID_KX_X722: 73 case I40E_DEV_ID_QSFP_X722: 74 case I40E_DEV_ID_SFP_X722: 75 case I40E_DEV_ID_1G_BASE_T_X722: 76 case I40E_DEV_ID_10G_BASE_T_X722: 77 case I40E_DEV_ID_SFP_I_X722: 78 hw->mac.type = I40E_MAC_X722; 79 break; 80 default: 81 hw->mac.type = I40E_MAC_GENERIC; 82 break; 83 } 84 } else { 85 status = I40E_ERR_DEVICE_NOT_SUPPORTED; 86 } 87 88 DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n", 89 hw->mac.type, status); 90 return status; 91 } 92 93 /** 94 * i40e_aq_str - convert AQ err code to a string 95 * @hw: pointer to the HW structure 96 * @aq_err: the AQ error code to convert 97 **/ 98 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err) 99 { 100 switch (aq_err) { 101 case I40E_AQ_RC_OK: 102 return "OK"; 103 case I40E_AQ_RC_EPERM: 104 return "I40E_AQ_RC_EPERM"; 105 case I40E_AQ_RC_ENOENT: 106 return "I40E_AQ_RC_ENOENT"; 107 case I40E_AQ_RC_ESRCH: 108 return "I40E_AQ_RC_ESRCH"; 109 case I40E_AQ_RC_EINTR: 110 return "I40E_AQ_RC_EINTR"; 111 case I40E_AQ_RC_EIO: 112 return "I40E_AQ_RC_EIO"; 113 case I40E_AQ_RC_ENXIO: 114 return "I40E_AQ_RC_ENXIO"; 115 case I40E_AQ_RC_E2BIG: 116 return "I40E_AQ_RC_E2BIG"; 117 case I40E_AQ_RC_EAGAIN: 118 return "I40E_AQ_RC_EAGAIN"; 119 case I40E_AQ_RC_ENOMEM: 120 return "I40E_AQ_RC_ENOMEM"; 121 case I40E_AQ_RC_EACCES: 122 return "I40E_AQ_RC_EACCES"; 123 case I40E_AQ_RC_EFAULT: 124 return "I40E_AQ_RC_EFAULT"; 125 case I40E_AQ_RC_EBUSY: 126 return "I40E_AQ_RC_EBUSY"; 127 case I40E_AQ_RC_EEXIST: 128 return "I40E_AQ_RC_EEXIST"; 129 case I40E_AQ_RC_EINVAL: 130 return "I40E_AQ_RC_EINVAL"; 131 case I40E_AQ_RC_ENOTTY: 132 return "I40E_AQ_RC_ENOTTY"; 133 case I40E_AQ_RC_ENOSPC: 134 return "I40E_AQ_RC_ENOSPC"; 135 case I40E_AQ_RC_ENOSYS: 136 return "I40E_AQ_RC_ENOSYS"; 137 case I40E_AQ_RC_ERANGE: 138 return "I40E_AQ_RC_ERANGE"; 139 case I40E_AQ_RC_EFLUSHED: 140 return "I40E_AQ_RC_EFLUSHED"; 141 case I40E_AQ_RC_BAD_ADDR: 142 return "I40E_AQ_RC_BAD_ADDR"; 143 case I40E_AQ_RC_EMODE: 144 return "I40E_AQ_RC_EMODE"; 145 case I40E_AQ_RC_EFBIG: 146 return "I40E_AQ_RC_EFBIG"; 147 } 148 149 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err); 150 return hw->err_str; 151 } 152 153 /** 154 * i40e_stat_str - convert status err code to a string 155 * @hw: pointer to the HW structure 156 * @stat_err: the status error code to convert 157 **/ 158 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err) 159 { 160 switch (stat_err) { 161 case I40E_SUCCESS: 162 return "OK"; 163 case I40E_ERR_NVM: 164 return "I40E_ERR_NVM"; 165 case I40E_ERR_NVM_CHECKSUM: 166 return "I40E_ERR_NVM_CHECKSUM"; 167 case I40E_ERR_PHY: 168 return "I40E_ERR_PHY"; 169 case I40E_ERR_CONFIG: 170 return "I40E_ERR_CONFIG"; 171 case I40E_ERR_PARAM: 172 return "I40E_ERR_PARAM"; 173 case I40E_ERR_MAC_TYPE: 174 return "I40E_ERR_MAC_TYPE"; 175 case I40E_ERR_UNKNOWN_PHY: 176 return "I40E_ERR_UNKNOWN_PHY"; 177 case I40E_ERR_LINK_SETUP: 178 return "I40E_ERR_LINK_SETUP"; 179 case I40E_ERR_ADAPTER_STOPPED: 180 return "I40E_ERR_ADAPTER_STOPPED"; 181 case I40E_ERR_INVALID_MAC_ADDR: 182 return "I40E_ERR_INVALID_MAC_ADDR"; 183 case I40E_ERR_DEVICE_NOT_SUPPORTED: 184 return "I40E_ERR_DEVICE_NOT_SUPPORTED"; 185 case I40E_ERR_MASTER_REQUESTS_PENDING: 186 return "I40E_ERR_MASTER_REQUESTS_PENDING"; 187 case I40E_ERR_INVALID_LINK_SETTINGS: 188 return "I40E_ERR_INVALID_LINK_SETTINGS"; 189 case I40E_ERR_AUTONEG_NOT_COMPLETE: 190 return "I40E_ERR_AUTONEG_NOT_COMPLETE"; 191 case I40E_ERR_RESET_FAILED: 192 return "I40E_ERR_RESET_FAILED"; 193 case I40E_ERR_SWFW_SYNC: 194 return "I40E_ERR_SWFW_SYNC"; 195 case I40E_ERR_NO_AVAILABLE_VSI: 196 return "I40E_ERR_NO_AVAILABLE_VSI"; 197 case I40E_ERR_NO_MEMORY: 198 return "I40E_ERR_NO_MEMORY"; 199 case I40E_ERR_BAD_PTR: 200 return "I40E_ERR_BAD_PTR"; 201 case I40E_ERR_RING_FULL: 202 return "I40E_ERR_RING_FULL"; 203 case I40E_ERR_INVALID_PD_ID: 204 return "I40E_ERR_INVALID_PD_ID"; 205 case I40E_ERR_INVALID_QP_ID: 206 return "I40E_ERR_INVALID_QP_ID"; 207 case I40E_ERR_INVALID_CQ_ID: 208 return "I40E_ERR_INVALID_CQ_ID"; 209 case I40E_ERR_INVALID_CEQ_ID: 210 return "I40E_ERR_INVALID_CEQ_ID"; 211 case I40E_ERR_INVALID_AEQ_ID: 212 return "I40E_ERR_INVALID_AEQ_ID"; 213 case I40E_ERR_INVALID_SIZE: 214 return "I40E_ERR_INVALID_SIZE"; 215 case I40E_ERR_INVALID_ARP_INDEX: 216 return "I40E_ERR_INVALID_ARP_INDEX"; 217 case I40E_ERR_INVALID_FPM_FUNC_ID: 218 return "I40E_ERR_INVALID_FPM_FUNC_ID"; 219 case I40E_ERR_QP_INVALID_MSG_SIZE: 220 return "I40E_ERR_QP_INVALID_MSG_SIZE"; 221 case I40E_ERR_QP_TOOMANY_WRS_POSTED: 222 return "I40E_ERR_QP_TOOMANY_WRS_POSTED"; 223 case I40E_ERR_INVALID_FRAG_COUNT: 224 return "I40E_ERR_INVALID_FRAG_COUNT"; 225 case I40E_ERR_QUEUE_EMPTY: 226 return "I40E_ERR_QUEUE_EMPTY"; 227 case I40E_ERR_INVALID_ALIGNMENT: 228 return "I40E_ERR_INVALID_ALIGNMENT"; 229 case I40E_ERR_FLUSHED_QUEUE: 230 return "I40E_ERR_FLUSHED_QUEUE"; 231 case I40E_ERR_INVALID_PUSH_PAGE_INDEX: 232 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX"; 233 case I40E_ERR_INVALID_IMM_DATA_SIZE: 234 return "I40E_ERR_INVALID_IMM_DATA_SIZE"; 235 case I40E_ERR_TIMEOUT: 236 return "I40E_ERR_TIMEOUT"; 237 case I40E_ERR_OPCODE_MISMATCH: 238 return "I40E_ERR_OPCODE_MISMATCH"; 239 case I40E_ERR_CQP_COMPL_ERROR: 240 return "I40E_ERR_CQP_COMPL_ERROR"; 241 case I40E_ERR_INVALID_VF_ID: 242 return "I40E_ERR_INVALID_VF_ID"; 243 case I40E_ERR_INVALID_HMCFN_ID: 244 return "I40E_ERR_INVALID_HMCFN_ID"; 245 case I40E_ERR_BACKING_PAGE_ERROR: 246 return "I40E_ERR_BACKING_PAGE_ERROR"; 247 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE: 248 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE"; 249 case I40E_ERR_INVALID_PBLE_INDEX: 250 return "I40E_ERR_INVALID_PBLE_INDEX"; 251 case I40E_ERR_INVALID_SD_INDEX: 252 return "I40E_ERR_INVALID_SD_INDEX"; 253 case I40E_ERR_INVALID_PAGE_DESC_INDEX: 254 return "I40E_ERR_INVALID_PAGE_DESC_INDEX"; 255 case I40E_ERR_INVALID_SD_TYPE: 256 return "I40E_ERR_INVALID_SD_TYPE"; 257 case I40E_ERR_MEMCPY_FAILED: 258 return "I40E_ERR_MEMCPY_FAILED"; 259 case I40E_ERR_INVALID_HMC_OBJ_INDEX: 260 return "I40E_ERR_INVALID_HMC_OBJ_INDEX"; 261 case I40E_ERR_INVALID_HMC_OBJ_COUNT: 262 return "I40E_ERR_INVALID_HMC_OBJ_COUNT"; 263 case I40E_ERR_INVALID_SRQ_ARM_LIMIT: 264 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT"; 265 case I40E_ERR_SRQ_ENABLED: 266 return "I40E_ERR_SRQ_ENABLED"; 267 case I40E_ERR_ADMIN_QUEUE_ERROR: 268 return "I40E_ERR_ADMIN_QUEUE_ERROR"; 269 case I40E_ERR_ADMIN_QUEUE_TIMEOUT: 270 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT"; 271 case I40E_ERR_BUF_TOO_SHORT: 272 return "I40E_ERR_BUF_TOO_SHORT"; 273 case I40E_ERR_ADMIN_QUEUE_FULL: 274 return "I40E_ERR_ADMIN_QUEUE_FULL"; 275 case I40E_ERR_ADMIN_QUEUE_NO_WORK: 276 return "I40E_ERR_ADMIN_QUEUE_NO_WORK"; 277 case I40E_ERR_BAD_IWARP_CQE: 278 return "I40E_ERR_BAD_IWARP_CQE"; 279 case I40E_ERR_NVM_BLANK_MODE: 280 return "I40E_ERR_NVM_BLANK_MODE"; 281 case I40E_ERR_NOT_IMPLEMENTED: 282 return "I40E_ERR_NOT_IMPLEMENTED"; 283 case I40E_ERR_PE_DOORBELL_NOT_ENABLED: 284 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED"; 285 case I40E_ERR_DIAG_TEST_FAILED: 286 return "I40E_ERR_DIAG_TEST_FAILED"; 287 case I40E_ERR_NOT_READY: 288 return "I40E_ERR_NOT_READY"; 289 case I40E_NOT_SUPPORTED: 290 return "I40E_NOT_SUPPORTED"; 291 case I40E_ERR_FIRMWARE_API_VERSION: 292 return "I40E_ERR_FIRMWARE_API_VERSION"; 293 } 294 295 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err); 296 return hw->err_str; 297 } 298 299 /** 300 * i40e_debug_aq 301 * @hw: debug mask related to admin queue 302 * @mask: debug mask 303 * @desc: pointer to admin queue descriptor 304 * @buffer: pointer to command buffer 305 * @buf_len: max length of buffer 306 * 307 * Dumps debug log about adminq command with descriptor contents. 308 **/ 309 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc, 310 void *buffer, u16 buf_len) 311 { 312 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc; 313 u16 len = LE16_TO_CPU(aq_desc->datalen); 314 u8 *buf = (u8 *)buffer; 315 u16 i = 0; 316 317 if ((!(mask & hw->debug_mask)) || (desc == NULL)) 318 return; 319 320 i40e_debug(hw, mask, 321 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n", 322 LE16_TO_CPU(aq_desc->opcode), 323 LE16_TO_CPU(aq_desc->flags), 324 LE16_TO_CPU(aq_desc->datalen), 325 LE16_TO_CPU(aq_desc->retval)); 326 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n", 327 LE32_TO_CPU(aq_desc->cookie_high), 328 LE32_TO_CPU(aq_desc->cookie_low)); 329 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n", 330 LE32_TO_CPU(aq_desc->params.internal.param0), 331 LE32_TO_CPU(aq_desc->params.internal.param1)); 332 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n", 333 LE32_TO_CPU(aq_desc->params.external.addr_high), 334 LE32_TO_CPU(aq_desc->params.external.addr_low)); 335 336 if ((buffer != NULL) && (aq_desc->datalen != 0)) { 337 i40e_debug(hw, mask, "AQ CMD Buffer:\n"); 338 if (buf_len < len) 339 len = buf_len; 340 /* write the full 16-byte chunks */ 341 for (i = 0; i < (len - 16); i += 16) 342 i40e_debug(hw, mask, 343 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 344 i, buf[i], buf[i+1], buf[i+2], buf[i+3], 345 buf[i+4], buf[i+5], buf[i+6], buf[i+7], 346 buf[i+8], buf[i+9], buf[i+10], buf[i+11], 347 buf[i+12], buf[i+13], buf[i+14], buf[i+15]); 348 /* the most we could have left is 16 bytes, pad with zeros */ 349 if (i < len) { 350 char d_buf[16]; 351 int j, i_sav; 352 353 i_sav = i; 354 memset(d_buf, 0, sizeof(d_buf)); 355 for (j = 0; i < len; j++, i++) 356 d_buf[j] = buf[i]; 357 i40e_debug(hw, mask, 358 "\t0x%04X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", 359 i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3], 360 d_buf[4], d_buf[5], d_buf[6], d_buf[7], 361 d_buf[8], d_buf[9], d_buf[10], d_buf[11], 362 d_buf[12], d_buf[13], d_buf[14], d_buf[15]); 363 } 364 } 365 } 366 367 /** 368 * i40e_check_asq_alive 369 * @hw: pointer to the hw struct 370 * 371 * Returns TRUE if Queue is enabled else FALSE. 372 **/ 373 bool i40e_check_asq_alive(struct i40e_hw *hw) 374 { 375 if (hw->aq.asq.len) 376 return !!(rd32(hw, hw->aq.asq.len) & 377 I40E_PF_ATQLEN_ATQENABLE_MASK); 378 return FALSE; 379 } 380 381 /** 382 * i40e_aq_queue_shutdown 383 * @hw: pointer to the hw struct 384 * @unloading: is the driver unloading itself 385 * 386 * Tell the Firmware that we're shutting down the AdminQ and whether 387 * or not the driver is unloading as well. 388 **/ 389 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, 390 bool unloading) 391 { 392 struct i40e_aq_desc desc; 393 struct i40e_aqc_queue_shutdown *cmd = 394 (struct i40e_aqc_queue_shutdown *)&desc.params.raw; 395 enum i40e_status_code status; 396 397 i40e_fill_default_direct_cmd_desc(&desc, 398 i40e_aqc_opc_queue_shutdown); 399 400 if (unloading) 401 cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING); 402 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL); 403 404 return status; 405 } 406 407 /** 408 * i40e_aq_get_set_rss_lut 409 * @hw: pointer to the hardware structure 410 * @vsi_id: vsi fw index 411 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 412 * @lut: pointer to the lut buffer provided by the caller 413 * @lut_size: size of the lut buffer 414 * @set: set TRUE to set the table, FALSE to get the table 415 * 416 * Internal function to get or set RSS look up table 417 **/ 418 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw, 419 u16 vsi_id, bool pf_lut, 420 u8 *lut, u16 lut_size, 421 bool set) 422 { 423 enum i40e_status_code status; 424 struct i40e_aq_desc desc; 425 struct i40e_aqc_get_set_rss_lut *cmd_resp = 426 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw; 427 428 if (set) 429 i40e_fill_default_direct_cmd_desc(&desc, 430 i40e_aqc_opc_set_rss_lut); 431 else 432 i40e_fill_default_direct_cmd_desc(&desc, 433 i40e_aqc_opc_get_rss_lut); 434 435 /* Indirect command */ 436 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 437 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 438 439 cmd_resp->vsi_id = 440 CPU_TO_LE16((u16)((vsi_id << 441 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) & 442 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK)); 443 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID); 444 445 if (pf_lut) 446 cmd_resp->flags |= CPU_TO_LE16((u16) 447 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF << 448 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 449 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 450 else 451 cmd_resp->flags |= CPU_TO_LE16((u16) 452 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI << 453 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) & 454 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK)); 455 456 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL); 457 458 return status; 459 } 460 461 /** 462 * i40e_aq_get_rss_lut 463 * @hw: pointer to the hardware structure 464 * @vsi_id: vsi fw index 465 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 466 * @lut: pointer to the lut buffer provided by the caller 467 * @lut_size: size of the lut buffer 468 * 469 * get the RSS lookup table, PF or VSI type 470 **/ 471 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id, 472 bool pf_lut, u8 *lut, u16 lut_size) 473 { 474 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, 475 FALSE); 476 } 477 478 /** 479 * i40e_aq_set_rss_lut 480 * @hw: pointer to the hardware structure 481 * @vsi_id: vsi fw index 482 * @pf_lut: for PF table set TRUE, for VSI table set FALSE 483 * @lut: pointer to the lut buffer provided by the caller 484 * @lut_size: size of the lut buffer 485 * 486 * set the RSS lookup table, PF or VSI type 487 **/ 488 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id, 489 bool pf_lut, u8 *lut, u16 lut_size) 490 { 491 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE); 492 } 493 494 /** 495 * i40e_aq_get_set_rss_key 496 * @hw: pointer to the hw struct 497 * @vsi_id: vsi fw index 498 * @key: pointer to key info struct 499 * @set: set TRUE to set the key, FALSE to get the key 500 * 501 * get the RSS key per VSI 502 **/ 503 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw, 504 u16 vsi_id, 505 struct i40e_aqc_get_set_rss_key_data *key, 506 bool set) 507 { 508 enum i40e_status_code status; 509 struct i40e_aq_desc desc; 510 struct i40e_aqc_get_set_rss_key *cmd_resp = 511 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw; 512 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data); 513 514 if (set) 515 i40e_fill_default_direct_cmd_desc(&desc, 516 i40e_aqc_opc_set_rss_key); 517 else 518 i40e_fill_default_direct_cmd_desc(&desc, 519 i40e_aqc_opc_get_rss_key); 520 521 /* Indirect command */ 522 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 523 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD); 524 525 cmd_resp->vsi_id = 526 CPU_TO_LE16((u16)((vsi_id << 527 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) & 528 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK)); 529 cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID); 530 531 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL); 532 533 return status; 534 } 535 536 /** 537 * i40e_aq_get_rss_key 538 * @hw: pointer to the hw struct 539 * @vsi_id: vsi fw index 540 * @key: pointer to key info struct 541 * 542 **/ 543 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw, 544 u16 vsi_id, 545 struct i40e_aqc_get_set_rss_key_data *key) 546 { 547 return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE); 548 } 549 550 /** 551 * i40e_aq_set_rss_key 552 * @hw: pointer to the hw struct 553 * @vsi_id: vsi fw index 554 * @key: pointer to key info struct 555 * 556 * set the RSS key per VSI 557 **/ 558 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw, 559 u16 vsi_id, 560 struct i40e_aqc_get_set_rss_key_data *key) 561 { 562 return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE); 563 } 564 565 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the 566 * hardware to a bit-field that can be used by SW to more easily determine the 567 * packet type. 568 * 569 * Macros are used to shorten the table lines and make this table human 570 * readable. 571 * 572 * We store the PTYPE in the top byte of the bit field - this is just so that 573 * we can check that the table doesn't have a row missing, as the index into 574 * the table should be the PTYPE. 575 * 576 * Typical work flow: 577 * 578 * IF NOT i40e_ptype_lookup[ptype].known 579 * THEN 580 * Packet is unknown 581 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP 582 * Use the rest of the fields to look at the tunnels, inner protocols, etc 583 * ELSE 584 * Use the enum i40e_rx_l2_ptype to decode the packet type 585 * ENDIF 586 */ 587 588 /* macro to make the table lines short */ 589 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 590 { PTYPE, \ 591 1, \ 592 I40E_RX_PTYPE_OUTER_##OUTER_IP, \ 593 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 594 I40E_RX_PTYPE_##OUTER_FRAG, \ 595 I40E_RX_PTYPE_TUNNEL_##T, \ 596 I40E_RX_PTYPE_TUNNEL_END_##TE, \ 597 I40E_RX_PTYPE_##TEF, \ 598 I40E_RX_PTYPE_INNER_PROT_##I, \ 599 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL } 600 601 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \ 602 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 603 604 /* shorter macros makes the table fit but are terse */ 605 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG 606 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG 607 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC 608 609 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 610 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = { 611 /* L2 Packet types */ 612 I40E_PTT_UNUSED_ENTRY(0), 613 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 614 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2), 615 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 616 I40E_PTT_UNUSED_ENTRY(4), 617 I40E_PTT_UNUSED_ENTRY(5), 618 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 619 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 620 I40E_PTT_UNUSED_ENTRY(8), 621 I40E_PTT_UNUSED_ENTRY(9), 622 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 623 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 624 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 625 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 626 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 627 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 628 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 629 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 630 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 631 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 632 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 633 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3), 634 635 /* Non Tunneled IPv4 */ 636 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 637 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 638 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 639 I40E_PTT_UNUSED_ENTRY(25), 640 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 641 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 642 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 643 644 /* IPv4 --> IPv4 */ 645 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 646 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 647 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 648 I40E_PTT_UNUSED_ENTRY(32), 649 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 650 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 651 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 652 653 /* IPv4 --> IPv6 */ 654 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 655 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 656 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 657 I40E_PTT_UNUSED_ENTRY(39), 658 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 659 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 660 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 661 662 /* IPv4 --> GRE/NAT */ 663 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 664 665 /* IPv4 --> GRE/NAT --> IPv4 */ 666 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 667 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 668 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 669 I40E_PTT_UNUSED_ENTRY(47), 670 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 671 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 672 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 673 674 /* IPv4 --> GRE/NAT --> IPv6 */ 675 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 676 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 677 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 678 I40E_PTT_UNUSED_ENTRY(54), 679 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 680 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 681 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 682 683 /* IPv4 --> GRE/NAT --> MAC */ 684 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 685 686 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 687 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 688 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 689 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 690 I40E_PTT_UNUSED_ENTRY(62), 691 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 692 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 693 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 694 695 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 696 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 697 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 698 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 699 I40E_PTT_UNUSED_ENTRY(69), 700 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 701 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 702 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 703 704 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 705 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 706 707 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 708 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 709 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 710 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 711 I40E_PTT_UNUSED_ENTRY(77), 712 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 713 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 714 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 715 716 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 717 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 718 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 719 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 720 I40E_PTT_UNUSED_ENTRY(84), 721 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 722 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 723 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 724 725 /* Non Tunneled IPv6 */ 726 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 727 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 728 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4), 729 I40E_PTT_UNUSED_ENTRY(91), 730 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 731 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 732 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 733 734 /* IPv6 --> IPv4 */ 735 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 736 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 737 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 738 I40E_PTT_UNUSED_ENTRY(98), 739 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 740 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 741 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 742 743 /* IPv6 --> IPv6 */ 744 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 745 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 746 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 747 I40E_PTT_UNUSED_ENTRY(105), 748 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 749 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 750 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 751 752 /* IPv6 --> GRE/NAT */ 753 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 754 755 /* IPv6 --> GRE/NAT -> IPv4 */ 756 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 757 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 758 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 759 I40E_PTT_UNUSED_ENTRY(113), 760 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 761 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 762 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 763 764 /* IPv6 --> GRE/NAT -> IPv6 */ 765 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 766 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 767 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 768 I40E_PTT_UNUSED_ENTRY(120), 769 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 770 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 771 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 772 773 /* IPv6 --> GRE/NAT -> MAC */ 774 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 775 776 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 777 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 778 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 779 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 780 I40E_PTT_UNUSED_ENTRY(128), 781 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 782 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 783 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 784 785 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 786 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 787 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 788 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 789 I40E_PTT_UNUSED_ENTRY(135), 790 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 791 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 792 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 793 794 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 795 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 796 797 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 798 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 799 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 800 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 801 I40E_PTT_UNUSED_ENTRY(143), 802 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 803 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 804 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 805 806 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 807 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 808 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 809 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 810 I40E_PTT_UNUSED_ENTRY(150), 811 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 812 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 813 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 814 815 /* unused entries */ 816 I40E_PTT_UNUSED_ENTRY(154), 817 I40E_PTT_UNUSED_ENTRY(155), 818 I40E_PTT_UNUSED_ENTRY(156), 819 I40E_PTT_UNUSED_ENTRY(157), 820 I40E_PTT_UNUSED_ENTRY(158), 821 I40E_PTT_UNUSED_ENTRY(159), 822 823 I40E_PTT_UNUSED_ENTRY(160), 824 I40E_PTT_UNUSED_ENTRY(161), 825 I40E_PTT_UNUSED_ENTRY(162), 826 I40E_PTT_UNUSED_ENTRY(163), 827 I40E_PTT_UNUSED_ENTRY(164), 828 I40E_PTT_UNUSED_ENTRY(165), 829 I40E_PTT_UNUSED_ENTRY(166), 830 I40E_PTT_UNUSED_ENTRY(167), 831 I40E_PTT_UNUSED_ENTRY(168), 832 I40E_PTT_UNUSED_ENTRY(169), 833 834 I40E_PTT_UNUSED_ENTRY(170), 835 I40E_PTT_UNUSED_ENTRY(171), 836 I40E_PTT_UNUSED_ENTRY(172), 837 I40E_PTT_UNUSED_ENTRY(173), 838 I40E_PTT_UNUSED_ENTRY(174), 839 I40E_PTT_UNUSED_ENTRY(175), 840 I40E_PTT_UNUSED_ENTRY(176), 841 I40E_PTT_UNUSED_ENTRY(177), 842 I40E_PTT_UNUSED_ENTRY(178), 843 I40E_PTT_UNUSED_ENTRY(179), 844 845 I40E_PTT_UNUSED_ENTRY(180), 846 I40E_PTT_UNUSED_ENTRY(181), 847 I40E_PTT_UNUSED_ENTRY(182), 848 I40E_PTT_UNUSED_ENTRY(183), 849 I40E_PTT_UNUSED_ENTRY(184), 850 I40E_PTT_UNUSED_ENTRY(185), 851 I40E_PTT_UNUSED_ENTRY(186), 852 I40E_PTT_UNUSED_ENTRY(187), 853 I40E_PTT_UNUSED_ENTRY(188), 854 I40E_PTT_UNUSED_ENTRY(189), 855 856 I40E_PTT_UNUSED_ENTRY(190), 857 I40E_PTT_UNUSED_ENTRY(191), 858 I40E_PTT_UNUSED_ENTRY(192), 859 I40E_PTT_UNUSED_ENTRY(193), 860 I40E_PTT_UNUSED_ENTRY(194), 861 I40E_PTT_UNUSED_ENTRY(195), 862 I40E_PTT_UNUSED_ENTRY(196), 863 I40E_PTT_UNUSED_ENTRY(197), 864 I40E_PTT_UNUSED_ENTRY(198), 865 I40E_PTT_UNUSED_ENTRY(199), 866 867 I40E_PTT_UNUSED_ENTRY(200), 868 I40E_PTT_UNUSED_ENTRY(201), 869 I40E_PTT_UNUSED_ENTRY(202), 870 I40E_PTT_UNUSED_ENTRY(203), 871 I40E_PTT_UNUSED_ENTRY(204), 872 I40E_PTT_UNUSED_ENTRY(205), 873 I40E_PTT_UNUSED_ENTRY(206), 874 I40E_PTT_UNUSED_ENTRY(207), 875 I40E_PTT_UNUSED_ENTRY(208), 876 I40E_PTT_UNUSED_ENTRY(209), 877 878 I40E_PTT_UNUSED_ENTRY(210), 879 I40E_PTT_UNUSED_ENTRY(211), 880 I40E_PTT_UNUSED_ENTRY(212), 881 I40E_PTT_UNUSED_ENTRY(213), 882 I40E_PTT_UNUSED_ENTRY(214), 883 I40E_PTT_UNUSED_ENTRY(215), 884 I40E_PTT_UNUSED_ENTRY(216), 885 I40E_PTT_UNUSED_ENTRY(217), 886 I40E_PTT_UNUSED_ENTRY(218), 887 I40E_PTT_UNUSED_ENTRY(219), 888 889 I40E_PTT_UNUSED_ENTRY(220), 890 I40E_PTT_UNUSED_ENTRY(221), 891 I40E_PTT_UNUSED_ENTRY(222), 892 I40E_PTT_UNUSED_ENTRY(223), 893 I40E_PTT_UNUSED_ENTRY(224), 894 I40E_PTT_UNUSED_ENTRY(225), 895 I40E_PTT_UNUSED_ENTRY(226), 896 I40E_PTT_UNUSED_ENTRY(227), 897 I40E_PTT_UNUSED_ENTRY(228), 898 I40E_PTT_UNUSED_ENTRY(229), 899 900 I40E_PTT_UNUSED_ENTRY(230), 901 I40E_PTT_UNUSED_ENTRY(231), 902 I40E_PTT_UNUSED_ENTRY(232), 903 I40E_PTT_UNUSED_ENTRY(233), 904 I40E_PTT_UNUSED_ENTRY(234), 905 I40E_PTT_UNUSED_ENTRY(235), 906 I40E_PTT_UNUSED_ENTRY(236), 907 I40E_PTT_UNUSED_ENTRY(237), 908 I40E_PTT_UNUSED_ENTRY(238), 909 I40E_PTT_UNUSED_ENTRY(239), 910 911 I40E_PTT_UNUSED_ENTRY(240), 912 I40E_PTT_UNUSED_ENTRY(241), 913 I40E_PTT_UNUSED_ENTRY(242), 914 I40E_PTT_UNUSED_ENTRY(243), 915 I40E_PTT_UNUSED_ENTRY(244), 916 I40E_PTT_UNUSED_ENTRY(245), 917 I40E_PTT_UNUSED_ENTRY(246), 918 I40E_PTT_UNUSED_ENTRY(247), 919 I40E_PTT_UNUSED_ENTRY(248), 920 I40E_PTT_UNUSED_ENTRY(249), 921 922 I40E_PTT_UNUSED_ENTRY(250), 923 I40E_PTT_UNUSED_ENTRY(251), 924 I40E_PTT_UNUSED_ENTRY(252), 925 I40E_PTT_UNUSED_ENTRY(253), 926 I40E_PTT_UNUSED_ENTRY(254), 927 I40E_PTT_UNUSED_ENTRY(255) 928 }; 929 930 931 /** 932 * i40e_validate_mac_addr - Validate unicast MAC address 933 * @mac_addr: pointer to MAC address 934 * 935 * Tests a MAC address to ensure it is a valid Individual Address 936 **/ 937 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr) 938 { 939 enum i40e_status_code status = I40E_SUCCESS; 940 941 DEBUGFUNC("i40e_validate_mac_addr"); 942 943 /* Broadcast addresses ARE multicast addresses 944 * Make sure it is not a multicast address 945 * Reject the zero address 946 */ 947 if (I40E_IS_MULTICAST(mac_addr) || 948 (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 949 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)) 950 status = I40E_ERR_INVALID_MAC_ADDR; 951 952 return status; 953 } 954 955 /** 956 * i40e_init_shared_code - Initialize the shared code 957 * @hw: pointer to hardware structure 958 * 959 * This assigns the MAC type and PHY code and inits the NVM. 960 * Does not touch the hardware. This function must be called prior to any 961 * other function in the shared code. The i40e_hw structure should be 962 * memset to 0 prior to calling this function. The following fields in 963 * hw structure should be filled in prior to calling this function: 964 * hw_addr, back, device_id, vendor_id, subsystem_device_id, 965 * subsystem_vendor_id, and revision_id 966 **/ 967 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw) 968 { 969 enum i40e_status_code status = I40E_SUCCESS; 970 u32 port, ari, func_rid; 971 972 DEBUGFUNC("i40e_init_shared_code"); 973 974 i40e_set_mac_type(hw); 975 976 switch (hw->mac.type) { 977 case I40E_MAC_XL710: 978 case I40E_MAC_X722: 979 break; 980 default: 981 return I40E_ERR_DEVICE_NOT_SUPPORTED; 982 } 983 984 hw->phy.get_link_info = TRUE; 985 986 /* Determine port number and PF number*/ 987 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) 988 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT; 989 hw->port = (u8)port; 990 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> 991 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT; 992 func_rid = rd32(hw, I40E_PF_FUNC_RID); 993 if (ari) 994 hw->pf_id = (u8)(func_rid & 0xff); 995 else 996 hw->pf_id = (u8)(func_rid & 0x7); 997 998 if (hw->mac.type == I40E_MAC_X722) 999 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE; 1000 1001 status = i40e_init_nvm(hw); 1002 return status; 1003 } 1004 1005 /** 1006 * i40e_aq_mac_address_read - Retrieve the MAC addresses 1007 * @hw: pointer to the hw struct 1008 * @flags: a return indicator of what addresses were added to the addr store 1009 * @addrs: the requestor's mac addr store 1010 * @cmd_details: pointer to command details structure or NULL 1011 **/ 1012 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw, 1013 u16 *flags, 1014 struct i40e_aqc_mac_address_read_data *addrs, 1015 struct i40e_asq_cmd_details *cmd_details) 1016 { 1017 struct i40e_aq_desc desc; 1018 struct i40e_aqc_mac_address_read *cmd_data = 1019 (struct i40e_aqc_mac_address_read *)&desc.params.raw; 1020 enum i40e_status_code status; 1021 1022 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read); 1023 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF); 1024 1025 status = i40e_asq_send_command(hw, &desc, addrs, 1026 sizeof(*addrs), cmd_details); 1027 *flags = LE16_TO_CPU(cmd_data->command_flags); 1028 1029 return status; 1030 } 1031 1032 /** 1033 * i40e_aq_mac_address_write - Change the MAC addresses 1034 * @hw: pointer to the hw struct 1035 * @flags: indicates which MAC to be written 1036 * @mac_addr: address to write 1037 * @cmd_details: pointer to command details structure or NULL 1038 **/ 1039 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw, 1040 u16 flags, u8 *mac_addr, 1041 struct i40e_asq_cmd_details *cmd_details) 1042 { 1043 struct i40e_aq_desc desc; 1044 struct i40e_aqc_mac_address_write *cmd_data = 1045 (struct i40e_aqc_mac_address_write *)&desc.params.raw; 1046 enum i40e_status_code status; 1047 1048 i40e_fill_default_direct_cmd_desc(&desc, 1049 i40e_aqc_opc_mac_address_write); 1050 cmd_data->command_flags = CPU_TO_LE16(flags); 1051 cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]); 1052 cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) | 1053 ((u32)mac_addr[3] << 16) | 1054 ((u32)mac_addr[4] << 8) | 1055 mac_addr[5]); 1056 1057 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1058 1059 return status; 1060 } 1061 1062 /** 1063 * i40e_get_mac_addr - get MAC address 1064 * @hw: pointer to the HW structure 1065 * @mac_addr: pointer to MAC address 1066 * 1067 * Reads the adapter's MAC address from register 1068 **/ 1069 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1070 { 1071 struct i40e_aqc_mac_address_read_data addrs; 1072 enum i40e_status_code status; 1073 u16 flags = 0; 1074 1075 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1076 1077 if (flags & I40E_AQC_LAN_ADDR_VALID) 1078 i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac), 1079 I40E_NONDMA_TO_NONDMA); 1080 1081 return status; 1082 } 1083 1084 /** 1085 * i40e_get_port_mac_addr - get Port MAC address 1086 * @hw: pointer to the HW structure 1087 * @mac_addr: pointer to Port MAC address 1088 * 1089 * Reads the adapter's Port MAC address 1090 **/ 1091 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr) 1092 { 1093 struct i40e_aqc_mac_address_read_data addrs; 1094 enum i40e_status_code status; 1095 u16 flags = 0; 1096 1097 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL); 1098 if (status) 1099 return status; 1100 1101 if (flags & I40E_AQC_PORT_ADDR_VALID) 1102 i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac), 1103 I40E_NONDMA_TO_NONDMA); 1104 else 1105 status = I40E_ERR_INVALID_MAC_ADDR; 1106 1107 return status; 1108 } 1109 1110 /** 1111 * i40e_pre_tx_queue_cfg - pre tx queue configure 1112 * @hw: pointer to the HW structure 1113 * @queue: target pf queue index 1114 * @enable: state change request 1115 * 1116 * Handles hw requirement to indicate intention to enable 1117 * or disable target queue. 1118 **/ 1119 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable) 1120 { 1121 u32 abs_queue_idx = hw->func_caps.base_queue + queue; 1122 u32 reg_block = 0; 1123 u32 reg_val; 1124 1125 if (abs_queue_idx >= 128) { 1126 reg_block = abs_queue_idx / 128; 1127 abs_queue_idx %= 128; 1128 } 1129 1130 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1131 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1132 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1133 1134 if (enable) 1135 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK; 1136 else 1137 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1138 1139 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val); 1140 } 1141 1142 /** 1143 * i40e_read_pba_string - Reads part number string from EEPROM 1144 * @hw: pointer to hardware structure 1145 * @pba_num: stores the part number string from the EEPROM 1146 * @pba_num_size: part number string buffer length 1147 * 1148 * Reads the part number string from the EEPROM. 1149 **/ 1150 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num, 1151 u32 pba_num_size) 1152 { 1153 enum i40e_status_code status = I40E_SUCCESS; 1154 u16 pba_word = 0; 1155 u16 pba_size = 0; 1156 u16 pba_ptr = 0; 1157 u16 i = 0; 1158 1159 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word); 1160 if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) { 1161 DEBUGOUT("Failed to read PBA flags or flag is invalid.\n"); 1162 return status; 1163 } 1164 1165 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr); 1166 if (status != I40E_SUCCESS) { 1167 DEBUGOUT("Failed to read PBA Block pointer.\n"); 1168 return status; 1169 } 1170 1171 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size); 1172 if (status != I40E_SUCCESS) { 1173 DEBUGOUT("Failed to read PBA Block size.\n"); 1174 return status; 1175 } 1176 1177 /* Subtract one to get PBA word count (PBA Size word is included in 1178 * total size) 1179 */ 1180 pba_size--; 1181 if (pba_num_size < (((u32)pba_size * 2) + 1)) { 1182 DEBUGOUT("Buffer to small for PBA data.\n"); 1183 return I40E_ERR_PARAM; 1184 } 1185 1186 for (i = 0; i < pba_size; i++) { 1187 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word); 1188 if (status != I40E_SUCCESS) { 1189 DEBUGOUT1("Failed to read PBA Block word %d.\n", i); 1190 return status; 1191 } 1192 1193 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF; 1194 pba_num[(i * 2) + 1] = pba_word & 0xFF; 1195 } 1196 pba_num[(pba_size * 2)] = '\0'; 1197 1198 return status; 1199 } 1200 1201 /** 1202 * i40e_get_media_type - Gets media type 1203 * @hw: pointer to the hardware structure 1204 **/ 1205 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) 1206 { 1207 enum i40e_media_type media; 1208 1209 switch (hw->phy.link_info.phy_type) { 1210 case I40E_PHY_TYPE_10GBASE_SR: 1211 case I40E_PHY_TYPE_10GBASE_LR: 1212 case I40E_PHY_TYPE_1000BASE_SX: 1213 case I40E_PHY_TYPE_1000BASE_LX: 1214 case I40E_PHY_TYPE_40GBASE_SR4: 1215 case I40E_PHY_TYPE_40GBASE_LR4: 1216 case I40E_PHY_TYPE_25GBASE_LR: 1217 case I40E_PHY_TYPE_25GBASE_SR: 1218 media = I40E_MEDIA_TYPE_FIBER; 1219 break; 1220 case I40E_PHY_TYPE_100BASE_TX: 1221 case I40E_PHY_TYPE_1000BASE_T: 1222 case I40E_PHY_TYPE_10GBASE_T: 1223 media = I40E_MEDIA_TYPE_BASET; 1224 break; 1225 case I40E_PHY_TYPE_10GBASE_CR1_CU: 1226 case I40E_PHY_TYPE_40GBASE_CR4_CU: 1227 case I40E_PHY_TYPE_10GBASE_CR1: 1228 case I40E_PHY_TYPE_40GBASE_CR4: 1229 case I40E_PHY_TYPE_10GBASE_SFPP_CU: 1230 case I40E_PHY_TYPE_40GBASE_AOC: 1231 case I40E_PHY_TYPE_10GBASE_AOC: 1232 case I40E_PHY_TYPE_25GBASE_CR: 1233 media = I40E_MEDIA_TYPE_DA; 1234 break; 1235 case I40E_PHY_TYPE_1000BASE_KX: 1236 case I40E_PHY_TYPE_10GBASE_KX4: 1237 case I40E_PHY_TYPE_10GBASE_KR: 1238 case I40E_PHY_TYPE_40GBASE_KR4: 1239 case I40E_PHY_TYPE_20GBASE_KR2: 1240 case I40E_PHY_TYPE_25GBASE_KR: 1241 media = I40E_MEDIA_TYPE_BACKPLANE; 1242 break; 1243 case I40E_PHY_TYPE_SGMII: 1244 case I40E_PHY_TYPE_XAUI: 1245 case I40E_PHY_TYPE_XFI: 1246 case I40E_PHY_TYPE_XLAUI: 1247 case I40E_PHY_TYPE_XLPPI: 1248 default: 1249 media = I40E_MEDIA_TYPE_UNKNOWN; 1250 break; 1251 } 1252 1253 return media; 1254 } 1255 1256 #define I40E_PF_RESET_WAIT_COUNT 200 1257 /** 1258 * i40e_pf_reset - Reset the PF 1259 * @hw: pointer to the hardware structure 1260 * 1261 * Assuming someone else has triggered a global reset, 1262 * assure the global reset is complete and then reset the PF 1263 **/ 1264 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw) 1265 { 1266 u32 cnt = 0; 1267 u32 cnt1 = 0; 1268 u32 reg = 0; 1269 u32 grst_del; 1270 1271 /* Poll for Global Reset steady state in case of recent GRST. 1272 * The grst delay value is in 100ms units, and we'll wait a 1273 * couple counts longer to be sure we don't just miss the end. 1274 */ 1275 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & 1276 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >> 1277 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT; 1278 1279 grst_del = grst_del * 20; 1280 1281 for (cnt = 0; cnt < grst_del; cnt++) { 1282 reg = rd32(hw, I40E_GLGEN_RSTAT); 1283 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK)) 1284 break; 1285 i40e_msec_delay(100); 1286 } 1287 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { 1288 DEBUGOUT("Global reset polling failed to complete.\n"); 1289 return I40E_ERR_RESET_FAILED; 1290 } 1291 1292 /* Now Wait for the FW to be ready */ 1293 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) { 1294 reg = rd32(hw, I40E_GLNVM_ULD); 1295 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1296 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK); 1297 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1298 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) { 1299 DEBUGOUT1("Core and Global modules ready %d\n", cnt1); 1300 break; 1301 } 1302 i40e_msec_delay(10); 1303 } 1304 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK | 1305 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) { 1306 DEBUGOUT("wait for FW Reset complete timedout\n"); 1307 DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg); 1308 return I40E_ERR_RESET_FAILED; 1309 } 1310 1311 /* If there was a Global Reset in progress when we got here, 1312 * we don't need to do the PF Reset 1313 */ 1314 if (!cnt) { 1315 reg = rd32(hw, I40E_PFGEN_CTRL); 1316 wr32(hw, I40E_PFGEN_CTRL, 1317 (reg | I40E_PFGEN_CTRL_PFSWR_MASK)); 1318 for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) { 1319 reg = rd32(hw, I40E_PFGEN_CTRL); 1320 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) 1321 break; 1322 i40e_msec_delay(1); 1323 } 1324 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { 1325 DEBUGOUT("PF reset polling failed to complete.\n"); 1326 return I40E_ERR_RESET_FAILED; 1327 } 1328 } 1329 1330 i40e_clear_pxe_mode(hw); 1331 1332 1333 return I40E_SUCCESS; 1334 } 1335 1336 /** 1337 * i40e_clear_hw - clear out any left over hw state 1338 * @hw: pointer to the hw struct 1339 * 1340 * Clear queues and interrupts, typically called at init time, 1341 * but after the capabilities have been found so we know how many 1342 * queues and msix vectors have been allocated. 1343 **/ 1344 void i40e_clear_hw(struct i40e_hw *hw) 1345 { 1346 u32 num_queues, base_queue; 1347 u32 num_pf_int; 1348 u32 num_vf_int; 1349 u32 num_vfs; 1350 u32 i, j; 1351 u32 val; 1352 u32 eol = 0x7ff; 1353 1354 /* get number of interrupts, queues, and vfs */ 1355 val = rd32(hw, I40E_GLPCI_CNF2); 1356 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >> 1357 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT; 1358 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >> 1359 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT; 1360 1361 val = rd32(hw, I40E_PFLAN_QALLOC); 1362 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >> 1363 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; 1364 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> 1365 I40E_PFLAN_QALLOC_LASTQ_SHIFT; 1366 if (val & I40E_PFLAN_QALLOC_VALID_MASK) 1367 num_queues = (j - base_queue) + 1; 1368 else 1369 num_queues = 0; 1370 1371 val = rd32(hw, I40E_PF_VT_PFALLOC); 1372 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >> 1373 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; 1374 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> 1375 I40E_PF_VT_PFALLOC_LASTVF_SHIFT; 1376 if (val & I40E_PF_VT_PFALLOC_VALID_MASK) 1377 num_vfs = (j - i) + 1; 1378 else 1379 num_vfs = 0; 1380 1381 /* stop all the interrupts */ 1382 wr32(hw, I40E_PFINT_ICR0_ENA, 0); 1383 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT; 1384 for (i = 0; i < num_pf_int - 2; i++) 1385 wr32(hw, I40E_PFINT_DYN_CTLN(i), val); 1386 1387 /* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */ 1388 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1389 wr32(hw, I40E_PFINT_LNKLST0, val); 1390 for (i = 0; i < num_pf_int - 2; i++) 1391 wr32(hw, I40E_PFINT_LNKLSTN(i), val); 1392 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT; 1393 for (i = 0; i < num_vfs; i++) 1394 wr32(hw, I40E_VPINT_LNKLST0(i), val); 1395 for (i = 0; i < num_vf_int - 2; i++) 1396 wr32(hw, I40E_VPINT_LNKLSTN(i), val); 1397 1398 /* warn the HW of the coming Tx disables */ 1399 for (i = 0; i < num_queues; i++) { 1400 u32 abs_queue_idx = base_queue + i; 1401 u32 reg_block = 0; 1402 1403 if (abs_queue_idx >= 128) { 1404 reg_block = abs_queue_idx / 128; 1405 abs_queue_idx %= 128; 1406 } 1407 1408 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); 1409 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK; 1410 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT); 1411 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK; 1412 1413 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val); 1414 } 1415 i40e_usec_delay(400); 1416 1417 /* stop all the queues */ 1418 for (i = 0; i < num_queues; i++) { 1419 wr32(hw, I40E_QINT_TQCTL(i), 0); 1420 wr32(hw, I40E_QTX_ENA(i), 0); 1421 wr32(hw, I40E_QINT_RQCTL(i), 0); 1422 wr32(hw, I40E_QRX_ENA(i), 0); 1423 } 1424 1425 /* short wait for all queue disables to settle */ 1426 i40e_usec_delay(50); 1427 } 1428 1429 /** 1430 * i40e_clear_pxe_mode - clear pxe operations mode 1431 * @hw: pointer to the hw struct 1432 * 1433 * Make sure all PXE mode settings are cleared, including things 1434 * like descriptor fetch/write-back mode. 1435 **/ 1436 void i40e_clear_pxe_mode(struct i40e_hw *hw) 1437 { 1438 if (i40e_check_asq_alive(hw)) 1439 i40e_aq_clear_pxe_mode(hw, NULL); 1440 } 1441 1442 /** 1443 * i40e_led_is_mine - helper to find matching led 1444 * @hw: pointer to the hw struct 1445 * @idx: index into GPIO registers 1446 * 1447 * returns: 0 if no match, otherwise the value of the GPIO_CTL register 1448 */ 1449 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx) 1450 { 1451 u32 gpio_val = 0; 1452 u32 port; 1453 1454 if (!hw->func_caps.led[idx]) 1455 return 0; 1456 1457 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx)); 1458 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >> 1459 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT; 1460 1461 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR 1462 * if it is not our port then ignore 1463 */ 1464 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) || 1465 (port != hw->port)) 1466 return 0; 1467 1468 return gpio_val; 1469 } 1470 1471 #define I40E_COMBINED_ACTIVITY 0xA 1472 #define I40E_FILTER_ACTIVITY 0xE 1473 #define I40E_LINK_ACTIVITY 0xC 1474 #define I40E_MAC_ACTIVITY 0xD 1475 #define I40E_LED0 22 1476 1477 /** 1478 * i40e_led_get - return current on/off mode 1479 * @hw: pointer to the hw struct 1480 * 1481 * The value returned is the 'mode' field as defined in the 1482 * GPIO register definitions: 0x0 = off, 0xf = on, and other 1483 * values are variations of possible behaviors relating to 1484 * blink, link, and wire. 1485 **/ 1486 u32 i40e_led_get(struct i40e_hw *hw) 1487 { 1488 u32 current_mode = 0; 1489 u32 mode = 0; 1490 int i; 1491 1492 /* as per the documentation GPIO 22-29 are the LED 1493 * GPIO pins named LED0..LED7 1494 */ 1495 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1496 u32 gpio_val = i40e_led_is_mine(hw, i); 1497 1498 if (!gpio_val) 1499 continue; 1500 1501 /* ignore gpio LED src mode entries related to the activity 1502 * LEDs 1503 */ 1504 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1505 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1506 switch (current_mode) { 1507 case I40E_COMBINED_ACTIVITY: 1508 case I40E_FILTER_ACTIVITY: 1509 case I40E_MAC_ACTIVITY: 1510 continue; 1511 default: 1512 break; 1513 } 1514 1515 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >> 1516 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT; 1517 break; 1518 } 1519 1520 return mode; 1521 } 1522 1523 /** 1524 * i40e_led_set - set new on/off mode 1525 * @hw: pointer to the hw struct 1526 * @mode: 0=off, 0xf=on (else see manual for mode details) 1527 * @blink: TRUE if the LED should blink when on, FALSE if steady 1528 * 1529 * if this function is used to turn on the blink it should 1530 * be used to disable the blink when restoring the original state. 1531 **/ 1532 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink) 1533 { 1534 u32 current_mode = 0; 1535 int i; 1536 1537 if (mode & 0xfffffff0) 1538 DEBUGOUT1("invalid mode passed in %X\n", mode); 1539 1540 /* as per the documentation GPIO 22-29 are the LED 1541 * GPIO pins named LED0..LED7 1542 */ 1543 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) { 1544 u32 gpio_val = i40e_led_is_mine(hw, i); 1545 1546 if (!gpio_val) 1547 continue; 1548 1549 /* ignore gpio LED src mode entries related to the activity 1550 * LEDs 1551 */ 1552 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) 1553 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT); 1554 switch (current_mode) { 1555 case I40E_COMBINED_ACTIVITY: 1556 case I40E_FILTER_ACTIVITY: 1557 case I40E_MAC_ACTIVITY: 1558 continue; 1559 default: 1560 break; 1561 } 1562 1563 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK; 1564 /* this & is a bit of paranoia, but serves as a range check */ 1565 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) & 1566 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK); 1567 1568 if (mode == I40E_LINK_ACTIVITY) 1569 blink = FALSE; 1570 1571 if (blink) 1572 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1573 else 1574 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT); 1575 1576 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val); 1577 break; 1578 } 1579 } 1580 1581 /* Admin command wrappers */ 1582 1583 /** 1584 * i40e_aq_get_phy_capabilities 1585 * @hw: pointer to the hw struct 1586 * @abilities: structure for PHY capabilities to be filled 1587 * @qualified_modules: report Qualified Modules 1588 * @report_init: report init capabilities (active are default) 1589 * @cmd_details: pointer to command details structure or NULL 1590 * 1591 * Returns the various PHY abilities supported on the Port. 1592 **/ 1593 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw, 1594 bool qualified_modules, bool report_init, 1595 struct i40e_aq_get_phy_abilities_resp *abilities, 1596 struct i40e_asq_cmd_details *cmd_details) 1597 { 1598 struct i40e_aq_desc desc; 1599 enum i40e_status_code status; 1600 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp); 1601 1602 if (!abilities) 1603 return I40E_ERR_PARAM; 1604 1605 i40e_fill_default_direct_cmd_desc(&desc, 1606 i40e_aqc_opc_get_phy_abilities); 1607 1608 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 1609 if (abilities_size > I40E_AQ_LARGE_BUF) 1610 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 1611 1612 if (qualified_modules) 1613 desc.params.external.param0 |= 1614 CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES); 1615 1616 if (report_init) 1617 desc.params.external.param0 |= 1618 CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES); 1619 1620 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size, 1621 cmd_details); 1622 1623 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) 1624 status = I40E_ERR_UNKNOWN_PHY; 1625 1626 if (report_init) { 1627 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type); 1628 hw->phy.phy_types |= ((u64)abilities->phy_type_ext << 32); 1629 } 1630 1631 return status; 1632 } 1633 1634 /** 1635 * i40e_aq_set_phy_config 1636 * @hw: pointer to the hw struct 1637 * @config: structure with PHY configuration to be set 1638 * @cmd_details: pointer to command details structure or NULL 1639 * 1640 * Set the various PHY configuration parameters 1641 * supported on the Port.One or more of the Set PHY config parameters may be 1642 * ignored in an MFP mode as the PF may not have the privilege to set some 1643 * of the PHY Config parameters. This status will be indicated by the 1644 * command response. 1645 **/ 1646 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw, 1647 struct i40e_aq_set_phy_config *config, 1648 struct i40e_asq_cmd_details *cmd_details) 1649 { 1650 struct i40e_aq_desc desc; 1651 struct i40e_aq_set_phy_config *cmd = 1652 (struct i40e_aq_set_phy_config *)&desc.params.raw; 1653 enum i40e_status_code status; 1654 1655 if (!config) 1656 return I40E_ERR_PARAM; 1657 1658 i40e_fill_default_direct_cmd_desc(&desc, 1659 i40e_aqc_opc_set_phy_config); 1660 1661 *cmd = *config; 1662 1663 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1664 1665 return status; 1666 } 1667 1668 /** 1669 * i40e_set_fc 1670 * @hw: pointer to the hw struct 1671 * 1672 * Set the requested flow control mode using set_phy_config. 1673 **/ 1674 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures, 1675 bool atomic_restart) 1676 { 1677 enum i40e_fc_mode fc_mode = hw->fc.requested_mode; 1678 struct i40e_aq_get_phy_abilities_resp abilities; 1679 struct i40e_aq_set_phy_config config; 1680 enum i40e_status_code status; 1681 u8 pause_mask = 0x0; 1682 1683 *aq_failures = 0x0; 1684 1685 switch (fc_mode) { 1686 case I40E_FC_FULL: 1687 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1688 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1689 break; 1690 case I40E_FC_RX_PAUSE: 1691 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX; 1692 break; 1693 case I40E_FC_TX_PAUSE: 1694 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX; 1695 break; 1696 default: 1697 break; 1698 } 1699 1700 /* Get the current phy config */ 1701 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities, 1702 NULL); 1703 if (status) { 1704 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET; 1705 return status; 1706 } 1707 1708 memset(&config, 0, sizeof(config)); 1709 /* clear the old pause settings */ 1710 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) & 1711 ~(I40E_AQ_PHY_FLAG_PAUSE_RX); 1712 /* set the new abilities */ 1713 config.abilities |= pause_mask; 1714 /* If the abilities have changed, then set the new config */ 1715 if (config.abilities != abilities.abilities) { 1716 /* Auto restart link so settings take effect */ 1717 if (atomic_restart) 1718 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK; 1719 /* Copy over all the old settings */ 1720 config.phy_type = abilities.phy_type; 1721 config.phy_type_ext = abilities.phy_type_ext; 1722 config.link_speed = abilities.link_speed; 1723 config.eee_capability = abilities.eee_capability; 1724 config.eeer = abilities.eeer_val; 1725 config.low_power_ctrl = abilities.d3_lpan; 1726 status = i40e_aq_set_phy_config(hw, &config, NULL); 1727 1728 if (status) 1729 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET; 1730 } 1731 /* Update the link info */ 1732 status = i40e_update_link_info(hw); 1733 if (status) { 1734 /* Wait a little bit (on 40G cards it sometimes takes a really 1735 * long time for link to come back from the atomic reset) 1736 * and try once more 1737 */ 1738 i40e_msec_delay(1000); 1739 status = i40e_update_link_info(hw); 1740 } 1741 if (status) 1742 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE; 1743 1744 return status; 1745 } 1746 1747 /** 1748 * i40e_aq_set_mac_config 1749 * @hw: pointer to the hw struct 1750 * @max_frame_size: Maximum Frame Size to be supported by the port 1751 * @crc_en: Tell HW to append a CRC to outgoing frames 1752 * @pacing: Pacing configurations 1753 * @cmd_details: pointer to command details structure or NULL 1754 * 1755 * Configure MAC settings for frame size, jumbo frame support and the 1756 * addition of a CRC by the hardware. 1757 **/ 1758 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw, 1759 u16 max_frame_size, 1760 bool crc_en, u16 pacing, 1761 struct i40e_asq_cmd_details *cmd_details) 1762 { 1763 struct i40e_aq_desc desc; 1764 struct i40e_aq_set_mac_config *cmd = 1765 (struct i40e_aq_set_mac_config *)&desc.params.raw; 1766 enum i40e_status_code status; 1767 1768 if (max_frame_size == 0) 1769 return I40E_ERR_PARAM; 1770 1771 i40e_fill_default_direct_cmd_desc(&desc, 1772 i40e_aqc_opc_set_mac_config); 1773 1774 cmd->max_frame_size = CPU_TO_LE16(max_frame_size); 1775 cmd->params = ((u8)pacing & 0x0F) << 3; 1776 if (crc_en) 1777 cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN; 1778 1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1780 1781 return status; 1782 } 1783 1784 /** 1785 * i40e_aq_clear_pxe_mode 1786 * @hw: pointer to the hw struct 1787 * @cmd_details: pointer to command details structure or NULL 1788 * 1789 * Tell the firmware that the driver is taking over from PXE 1790 **/ 1791 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw, 1792 struct i40e_asq_cmd_details *cmd_details) 1793 { 1794 enum i40e_status_code status; 1795 struct i40e_aq_desc desc; 1796 struct i40e_aqc_clear_pxe *cmd = 1797 (struct i40e_aqc_clear_pxe *)&desc.params.raw; 1798 1799 i40e_fill_default_direct_cmd_desc(&desc, 1800 i40e_aqc_opc_clear_pxe_mode); 1801 1802 cmd->rx_cnt = 0x2; 1803 1804 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1805 1806 wr32(hw, I40E_GLLAN_RCTL_0, 0x1); 1807 1808 return status; 1809 } 1810 1811 /** 1812 * i40e_aq_set_link_restart_an 1813 * @hw: pointer to the hw struct 1814 * @enable_link: if TRUE: enable link, if FALSE: disable link 1815 * @cmd_details: pointer to command details structure or NULL 1816 * 1817 * Sets up the link and restarts the Auto-Negotiation over the link. 1818 **/ 1819 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw, 1820 bool enable_link, struct i40e_asq_cmd_details *cmd_details) 1821 { 1822 struct i40e_aq_desc desc; 1823 struct i40e_aqc_set_link_restart_an *cmd = 1824 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw; 1825 enum i40e_status_code status; 1826 1827 i40e_fill_default_direct_cmd_desc(&desc, 1828 i40e_aqc_opc_set_link_restart_an); 1829 1830 cmd->command = I40E_AQ_PHY_RESTART_AN; 1831 if (enable_link) 1832 cmd->command |= I40E_AQ_PHY_LINK_ENABLE; 1833 else 1834 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE; 1835 1836 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1837 1838 return status; 1839 } 1840 1841 /** 1842 * i40e_aq_get_link_info 1843 * @hw: pointer to the hw struct 1844 * @enable_lse: enable/disable LinkStatusEvent reporting 1845 * @link: pointer to link status structure - optional 1846 * @cmd_details: pointer to command details structure or NULL 1847 * 1848 * Returns the link status of the adapter. 1849 **/ 1850 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw, 1851 bool enable_lse, struct i40e_link_status *link, 1852 struct i40e_asq_cmd_details *cmd_details) 1853 { 1854 struct i40e_aq_desc desc; 1855 struct i40e_aqc_get_link_status *resp = 1856 (struct i40e_aqc_get_link_status *)&desc.params.raw; 1857 struct i40e_link_status *hw_link_info = &hw->phy.link_info; 1858 enum i40e_status_code status; 1859 bool tx_pause, rx_pause; 1860 u16 command_flags; 1861 1862 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status); 1863 1864 if (enable_lse) 1865 command_flags = I40E_AQ_LSE_ENABLE; 1866 else 1867 command_flags = I40E_AQ_LSE_DISABLE; 1868 resp->command_flags = CPU_TO_LE16(command_flags); 1869 1870 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1871 1872 if (status != I40E_SUCCESS) 1873 goto aq_get_link_info_exit; 1874 1875 /* save off old link status information */ 1876 i40e_memcpy(&hw->phy.link_info_old, hw_link_info, 1877 sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA); 1878 1879 /* update link status */ 1880 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type; 1881 hw->phy.media_type = i40e_get_media_type(hw); 1882 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed; 1883 hw_link_info->link_info = resp->link_info; 1884 hw_link_info->an_info = resp->an_info; 1885 hw_link_info->ext_info = resp->ext_info; 1886 hw_link_info->loopback = resp->loopback; 1887 hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size); 1888 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK; 1889 1890 /* update fc info */ 1891 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX); 1892 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX); 1893 if (tx_pause & rx_pause) 1894 hw->fc.current_mode = I40E_FC_FULL; 1895 else if (tx_pause) 1896 hw->fc.current_mode = I40E_FC_TX_PAUSE; 1897 else if (rx_pause) 1898 hw->fc.current_mode = I40E_FC_RX_PAUSE; 1899 else 1900 hw->fc.current_mode = I40E_FC_NONE; 1901 1902 if (resp->config & I40E_AQ_CONFIG_CRC_ENA) 1903 hw_link_info->crc_enable = TRUE; 1904 else 1905 hw_link_info->crc_enable = FALSE; 1906 1907 if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED)) 1908 hw_link_info->lse_enable = TRUE; 1909 else 1910 hw_link_info->lse_enable = FALSE; 1911 1912 if ((hw->mac.type == I40E_MAC_XL710) && 1913 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 && 1914 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE) 1915 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU; 1916 1917 /* save link status information */ 1918 if (link) 1919 i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info), 1920 I40E_NONDMA_TO_NONDMA); 1921 1922 /* flag cleared so helper functions don't call AQ again */ 1923 hw->phy.get_link_info = FALSE; 1924 1925 aq_get_link_info_exit: 1926 return status; 1927 } 1928 1929 /** 1930 * i40e_aq_set_phy_int_mask 1931 * @hw: pointer to the hw struct 1932 * @mask: interrupt mask to be set 1933 * @cmd_details: pointer to command details structure or NULL 1934 * 1935 * Set link interrupt mask. 1936 **/ 1937 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, 1938 u16 mask, 1939 struct i40e_asq_cmd_details *cmd_details) 1940 { 1941 struct i40e_aq_desc desc; 1942 struct i40e_aqc_set_phy_int_mask *cmd = 1943 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw; 1944 enum i40e_status_code status; 1945 1946 i40e_fill_default_direct_cmd_desc(&desc, 1947 i40e_aqc_opc_set_phy_int_mask); 1948 1949 cmd->event_mask = CPU_TO_LE16(mask); 1950 1951 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1952 1953 return status; 1954 } 1955 1956 /** 1957 * i40e_aq_get_local_advt_reg 1958 * @hw: pointer to the hw struct 1959 * @advt_reg: local AN advertisement register value 1960 * @cmd_details: pointer to command details structure or NULL 1961 * 1962 * Get the Local AN advertisement register value. 1963 **/ 1964 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw, 1965 u64 *advt_reg, 1966 struct i40e_asq_cmd_details *cmd_details) 1967 { 1968 struct i40e_aq_desc desc; 1969 struct i40e_aqc_an_advt_reg *resp = 1970 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 1971 enum i40e_status_code status; 1972 1973 i40e_fill_default_direct_cmd_desc(&desc, 1974 i40e_aqc_opc_get_local_advt_reg); 1975 1976 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 1977 1978 if (status != I40E_SUCCESS) 1979 goto aq_get_local_advt_reg_exit; 1980 1981 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 1982 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 1983 1984 aq_get_local_advt_reg_exit: 1985 return status; 1986 } 1987 1988 /** 1989 * i40e_aq_set_local_advt_reg 1990 * @hw: pointer to the hw struct 1991 * @advt_reg: local AN advertisement register value 1992 * @cmd_details: pointer to command details structure or NULL 1993 * 1994 * Get the Local AN advertisement register value. 1995 **/ 1996 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw, 1997 u64 advt_reg, 1998 struct i40e_asq_cmd_details *cmd_details) 1999 { 2000 struct i40e_aq_desc desc; 2001 struct i40e_aqc_an_advt_reg *cmd = 2002 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2003 enum i40e_status_code status; 2004 2005 i40e_fill_default_direct_cmd_desc(&desc, 2006 i40e_aqc_opc_get_local_advt_reg); 2007 2008 cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg)); 2009 cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg)); 2010 2011 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2012 2013 return status; 2014 } 2015 2016 /** 2017 * i40e_aq_get_partner_advt 2018 * @hw: pointer to the hw struct 2019 * @advt_reg: AN partner advertisement register value 2020 * @cmd_details: pointer to command details structure or NULL 2021 * 2022 * Get the link partner AN advertisement register value. 2023 **/ 2024 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw, 2025 u64 *advt_reg, 2026 struct i40e_asq_cmd_details *cmd_details) 2027 { 2028 struct i40e_aq_desc desc; 2029 struct i40e_aqc_an_advt_reg *resp = 2030 (struct i40e_aqc_an_advt_reg *)&desc.params.raw; 2031 enum i40e_status_code status; 2032 2033 i40e_fill_default_direct_cmd_desc(&desc, 2034 i40e_aqc_opc_get_partner_advt); 2035 2036 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2037 2038 if (status != I40E_SUCCESS) 2039 goto aq_get_partner_advt_exit; 2040 2041 *advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32; 2042 *advt_reg |= LE32_TO_CPU(resp->local_an_reg0); 2043 2044 aq_get_partner_advt_exit: 2045 return status; 2046 } 2047 2048 /** 2049 * i40e_aq_set_lb_modes 2050 * @hw: pointer to the hw struct 2051 * @lb_modes: loopback mode to be set 2052 * @cmd_details: pointer to command details structure or NULL 2053 * 2054 * Sets loopback modes. 2055 **/ 2056 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, 2057 u16 lb_modes, 2058 struct i40e_asq_cmd_details *cmd_details) 2059 { 2060 struct i40e_aq_desc desc; 2061 struct i40e_aqc_set_lb_mode *cmd = 2062 (struct i40e_aqc_set_lb_mode *)&desc.params.raw; 2063 enum i40e_status_code status; 2064 2065 i40e_fill_default_direct_cmd_desc(&desc, 2066 i40e_aqc_opc_set_lb_modes); 2067 2068 cmd->lb_mode = CPU_TO_LE16(lb_modes); 2069 2070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2071 2072 return status; 2073 } 2074 2075 /** 2076 * i40e_aq_set_phy_debug 2077 * @hw: pointer to the hw struct 2078 * @cmd_flags: debug command flags 2079 * @cmd_details: pointer to command details structure or NULL 2080 * 2081 * Reset the external PHY. 2082 **/ 2083 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags, 2084 struct i40e_asq_cmd_details *cmd_details) 2085 { 2086 struct i40e_aq_desc desc; 2087 struct i40e_aqc_set_phy_debug *cmd = 2088 (struct i40e_aqc_set_phy_debug *)&desc.params.raw; 2089 enum i40e_status_code status; 2090 2091 i40e_fill_default_direct_cmd_desc(&desc, 2092 i40e_aqc_opc_set_phy_debug); 2093 2094 cmd->command_flags = cmd_flags; 2095 2096 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2097 2098 return status; 2099 } 2100 2101 /** 2102 * i40e_aq_add_vsi 2103 * @hw: pointer to the hw struct 2104 * @vsi_ctx: pointer to a vsi context struct 2105 * @cmd_details: pointer to command details structure or NULL 2106 * 2107 * Add a VSI context to the hardware. 2108 **/ 2109 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw, 2110 struct i40e_vsi_context *vsi_ctx, 2111 struct i40e_asq_cmd_details *cmd_details) 2112 { 2113 struct i40e_aq_desc desc; 2114 struct i40e_aqc_add_get_update_vsi *cmd = 2115 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2116 struct i40e_aqc_add_get_update_vsi_completion *resp = 2117 (struct i40e_aqc_add_get_update_vsi_completion *) 2118 &desc.params.raw; 2119 enum i40e_status_code status; 2120 2121 i40e_fill_default_direct_cmd_desc(&desc, 2122 i40e_aqc_opc_add_vsi); 2123 2124 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid); 2125 cmd->connection_type = vsi_ctx->connection_type; 2126 cmd->vf_id = vsi_ctx->vf_num; 2127 cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags); 2128 2129 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2130 2131 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2132 sizeof(vsi_ctx->info), cmd_details); 2133 2134 if (status != I40E_SUCCESS) 2135 goto aq_add_vsi_exit; 2136 2137 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2138 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2139 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2140 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2141 2142 aq_add_vsi_exit: 2143 return status; 2144 } 2145 2146 /** 2147 * i40e_aq_set_default_vsi 2148 * @hw: pointer to the hw struct 2149 * @seid: vsi number 2150 * @cmd_details: pointer to command details structure or NULL 2151 **/ 2152 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, 2153 u16 seid, 2154 struct i40e_asq_cmd_details *cmd_details) 2155 { 2156 struct i40e_aq_desc desc; 2157 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2158 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2159 &desc.params.raw; 2160 enum i40e_status_code status; 2161 2162 i40e_fill_default_direct_cmd_desc(&desc, 2163 i40e_aqc_opc_set_vsi_promiscuous_modes); 2164 2165 cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2166 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2167 cmd->seid = CPU_TO_LE16(seid); 2168 2169 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2170 2171 return status; 2172 } 2173 2174 /** 2175 * i40e_aq_clear_default_vsi 2176 * @hw: pointer to the hw struct 2177 * @seid: vsi number 2178 * @cmd_details: pointer to command details structure or NULL 2179 **/ 2180 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, 2181 u16 seid, 2182 struct i40e_asq_cmd_details *cmd_details) 2183 { 2184 struct i40e_aq_desc desc; 2185 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2186 (struct i40e_aqc_set_vsi_promiscuous_modes *) 2187 &desc.params.raw; 2188 enum i40e_status_code status; 2189 2190 i40e_fill_default_direct_cmd_desc(&desc, 2191 i40e_aqc_opc_set_vsi_promiscuous_modes); 2192 2193 cmd->promiscuous_flags = CPU_TO_LE16(0); 2194 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT); 2195 cmd->seid = CPU_TO_LE16(seid); 2196 2197 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2198 2199 return status; 2200 } 2201 2202 /** 2203 * i40e_aq_set_vsi_unicast_promiscuous 2204 * @hw: pointer to the hw struct 2205 * @seid: vsi number 2206 * @set: set unicast promiscuous enable/disable 2207 * @cmd_details: pointer to command details structure or NULL 2208 * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc 2209 **/ 2210 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw, 2211 u16 seid, bool set, 2212 struct i40e_asq_cmd_details *cmd_details, 2213 bool rx_only_promisc) 2214 { 2215 struct i40e_aq_desc desc; 2216 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2217 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2218 enum i40e_status_code status; 2219 u16 flags = 0; 2220 2221 i40e_fill_default_direct_cmd_desc(&desc, 2222 i40e_aqc_opc_set_vsi_promiscuous_modes); 2223 2224 if (set) { 2225 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2226 if (rx_only_promisc && 2227 (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) || 2228 (hw->aq.api_maj_ver > 1))) 2229 flags |= I40E_AQC_SET_VSI_PROMISC_TX; 2230 } 2231 2232 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2233 2234 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2235 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) || 2236 (hw->aq.api_maj_ver > 1)) 2237 cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX); 2238 2239 cmd->seid = CPU_TO_LE16(seid); 2240 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2241 2242 return status; 2243 } 2244 2245 /** 2246 * i40e_aq_set_vsi_multicast_promiscuous 2247 * @hw: pointer to the hw struct 2248 * @seid: vsi number 2249 * @set: set multicast promiscuous enable/disable 2250 * @cmd_details: pointer to command details structure or NULL 2251 **/ 2252 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw, 2253 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details) 2254 { 2255 struct i40e_aq_desc desc; 2256 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2257 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2258 enum i40e_status_code status; 2259 u16 flags = 0; 2260 2261 i40e_fill_default_direct_cmd_desc(&desc, 2262 i40e_aqc_opc_set_vsi_promiscuous_modes); 2263 2264 if (set) 2265 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2266 2267 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2268 2269 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2270 2271 cmd->seid = CPU_TO_LE16(seid); 2272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2273 2274 return status; 2275 } 2276 2277 /** 2278 * i40e_aq_set_vsi_mc_promisc_on_vlan 2279 * @hw: pointer to the hw struct 2280 * @seid: vsi number 2281 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2282 * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag 2283 * @cmd_details: pointer to command details structure or NULL 2284 **/ 2285 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw, 2286 u16 seid, bool enable, u16 vid, 2287 struct i40e_asq_cmd_details *cmd_details) 2288 { 2289 struct i40e_aq_desc desc; 2290 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2291 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2292 enum i40e_status_code status; 2293 u16 flags = 0; 2294 2295 i40e_fill_default_direct_cmd_desc(&desc, 2296 i40e_aqc_opc_set_vsi_promiscuous_modes); 2297 2298 if (enable) 2299 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST; 2300 2301 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2302 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST); 2303 cmd->seid = CPU_TO_LE16(seid); 2304 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2305 2306 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2307 2308 return status; 2309 } 2310 2311 /** 2312 * i40e_aq_set_vsi_uc_promisc_on_vlan 2313 * @hw: pointer to the hw struct 2314 * @seid: vsi number 2315 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2316 * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag 2317 * @cmd_details: pointer to command details structure or NULL 2318 **/ 2319 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw, 2320 u16 seid, bool enable, u16 vid, 2321 struct i40e_asq_cmd_details *cmd_details) 2322 { 2323 struct i40e_aq_desc desc; 2324 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2325 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2326 enum i40e_status_code status; 2327 u16 flags = 0; 2328 2329 i40e_fill_default_direct_cmd_desc(&desc, 2330 i40e_aqc_opc_set_vsi_promiscuous_modes); 2331 2332 if (enable) 2333 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST; 2334 2335 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2336 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST); 2337 cmd->seid = CPU_TO_LE16(seid); 2338 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2339 2340 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2341 2342 return status; 2343 } 2344 2345 /** 2346 * i40e_aq_set_vsi_bc_promisc_on_vlan 2347 * @hw: pointer to the hw struct 2348 * @seid: vsi number 2349 * @enable: set broadcast promiscuous enable/disable for a given VLAN 2350 * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag 2351 * @cmd_details: pointer to command details structure or NULL 2352 **/ 2353 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw, 2354 u16 seid, bool enable, u16 vid, 2355 struct i40e_asq_cmd_details *cmd_details) 2356 { 2357 struct i40e_aq_desc desc; 2358 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2359 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2360 enum i40e_status_code status; 2361 u16 flags = 0; 2362 2363 i40e_fill_default_direct_cmd_desc(&desc, 2364 i40e_aqc_opc_set_vsi_promiscuous_modes); 2365 2366 if (enable) 2367 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST; 2368 2369 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2370 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2371 cmd->seid = CPU_TO_LE16(seid); 2372 cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID); 2373 2374 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2375 2376 return status; 2377 } 2378 2379 /** 2380 * i40e_aq_set_vsi_broadcast 2381 * @hw: pointer to the hw struct 2382 * @seid: vsi number 2383 * @set_filter: TRUE to set filter, FALSE to clear filter 2384 * @cmd_details: pointer to command details structure or NULL 2385 * 2386 * Set or clear the broadcast promiscuous flag (filter) for a given VSI. 2387 **/ 2388 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw, 2389 u16 seid, bool set_filter, 2390 struct i40e_asq_cmd_details *cmd_details) 2391 { 2392 struct i40e_aq_desc desc; 2393 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2394 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2395 enum i40e_status_code status; 2396 2397 i40e_fill_default_direct_cmd_desc(&desc, 2398 i40e_aqc_opc_set_vsi_promiscuous_modes); 2399 2400 if (set_filter) 2401 cmd->promiscuous_flags 2402 |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2403 else 2404 cmd->promiscuous_flags 2405 &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2406 2407 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST); 2408 cmd->seid = CPU_TO_LE16(seid); 2409 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2410 2411 return status; 2412 } 2413 2414 /** 2415 * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting 2416 * @hw: pointer to the hw struct 2417 * @seid: vsi number 2418 * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN 2419 * @cmd_details: pointer to command details structure or NULL 2420 **/ 2421 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw, 2422 u16 seid, bool enable, 2423 struct i40e_asq_cmd_details *cmd_details) 2424 { 2425 struct i40e_aq_desc desc; 2426 struct i40e_aqc_set_vsi_promiscuous_modes *cmd = 2427 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw; 2428 enum i40e_status_code status; 2429 u16 flags = 0; 2430 2431 i40e_fill_default_direct_cmd_desc(&desc, 2432 i40e_aqc_opc_set_vsi_promiscuous_modes); 2433 if (enable) 2434 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN; 2435 2436 cmd->promiscuous_flags = CPU_TO_LE16(flags); 2437 cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN); 2438 cmd->seid = CPU_TO_LE16(seid); 2439 2440 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2441 2442 return status; 2443 } 2444 2445 /** 2446 * i40e_get_vsi_params - get VSI configuration info 2447 * @hw: pointer to the hw struct 2448 * @vsi_ctx: pointer to a vsi context struct 2449 * @cmd_details: pointer to command details structure or NULL 2450 **/ 2451 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw, 2452 struct i40e_vsi_context *vsi_ctx, 2453 struct i40e_asq_cmd_details *cmd_details) 2454 { 2455 struct i40e_aq_desc desc; 2456 struct i40e_aqc_add_get_update_vsi *cmd = 2457 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2458 struct i40e_aqc_add_get_update_vsi_completion *resp = 2459 (struct i40e_aqc_add_get_update_vsi_completion *) 2460 &desc.params.raw; 2461 enum i40e_status_code status; 2462 2463 i40e_fill_default_direct_cmd_desc(&desc, 2464 i40e_aqc_opc_get_vsi_parameters); 2465 2466 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2467 2468 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2469 2470 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2471 sizeof(vsi_ctx->info), NULL); 2472 2473 if (status != I40E_SUCCESS) 2474 goto aq_get_vsi_params_exit; 2475 2476 vsi_ctx->seid = LE16_TO_CPU(resp->seid); 2477 vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number); 2478 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2479 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2480 2481 aq_get_vsi_params_exit: 2482 return status; 2483 } 2484 2485 /** 2486 * i40e_aq_update_vsi_params 2487 * @hw: pointer to the hw struct 2488 * @vsi_ctx: pointer to a vsi context struct 2489 * @cmd_details: pointer to command details structure or NULL 2490 * 2491 * Update a VSI context. 2492 **/ 2493 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw, 2494 struct i40e_vsi_context *vsi_ctx, 2495 struct i40e_asq_cmd_details *cmd_details) 2496 { 2497 struct i40e_aq_desc desc; 2498 struct i40e_aqc_add_get_update_vsi *cmd = 2499 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw; 2500 struct i40e_aqc_add_get_update_vsi_completion *resp = 2501 (struct i40e_aqc_add_get_update_vsi_completion *) 2502 &desc.params.raw; 2503 enum i40e_status_code status; 2504 2505 i40e_fill_default_direct_cmd_desc(&desc, 2506 i40e_aqc_opc_update_vsi_parameters); 2507 cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid); 2508 2509 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2510 2511 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info, 2512 sizeof(vsi_ctx->info), cmd_details); 2513 2514 vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used); 2515 vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free); 2516 2517 return status; 2518 } 2519 2520 /** 2521 * i40e_aq_get_switch_config 2522 * @hw: pointer to the hardware structure 2523 * @buf: pointer to the result buffer 2524 * @buf_size: length of input buffer 2525 * @start_seid: seid to start for the report, 0 == beginning 2526 * @cmd_details: pointer to command details structure or NULL 2527 * 2528 * Fill the buf with switch configuration returned from AdminQ command 2529 **/ 2530 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw, 2531 struct i40e_aqc_get_switch_config_resp *buf, 2532 u16 buf_size, u16 *start_seid, 2533 struct i40e_asq_cmd_details *cmd_details) 2534 { 2535 struct i40e_aq_desc desc; 2536 struct i40e_aqc_switch_seid *scfg = 2537 (struct i40e_aqc_switch_seid *)&desc.params.raw; 2538 enum i40e_status_code status; 2539 2540 i40e_fill_default_direct_cmd_desc(&desc, 2541 i40e_aqc_opc_get_switch_config); 2542 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF); 2543 if (buf_size > I40E_AQ_LARGE_BUF) 2544 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2545 scfg->seid = CPU_TO_LE16(*start_seid); 2546 2547 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details); 2548 *start_seid = LE16_TO_CPU(scfg->seid); 2549 2550 return status; 2551 } 2552 2553 /** 2554 * i40e_aq_set_switch_config 2555 * @hw: pointer to the hardware structure 2556 * @flags: bit flag values to set 2557 * @valid_flags: which bit flags to set 2558 * @cmd_details: pointer to command details structure or NULL 2559 * 2560 * Set switch configuration bits 2561 **/ 2562 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw, 2563 u16 flags, u16 valid_flags, 2564 struct i40e_asq_cmd_details *cmd_details) 2565 { 2566 struct i40e_aq_desc desc; 2567 struct i40e_aqc_set_switch_config *scfg = 2568 (struct i40e_aqc_set_switch_config *)&desc.params.raw; 2569 enum i40e_status_code status; 2570 2571 i40e_fill_default_direct_cmd_desc(&desc, 2572 i40e_aqc_opc_set_switch_config); 2573 scfg->flags = CPU_TO_LE16(flags); 2574 scfg->valid_flags = CPU_TO_LE16(valid_flags); 2575 2576 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2577 2578 return status; 2579 } 2580 2581 /** 2582 * i40e_aq_get_firmware_version 2583 * @hw: pointer to the hw struct 2584 * @fw_major_version: firmware major version 2585 * @fw_minor_version: firmware minor version 2586 * @fw_build: firmware build number 2587 * @api_major_version: major queue version 2588 * @api_minor_version: minor queue version 2589 * @cmd_details: pointer to command details structure or NULL 2590 * 2591 * Get the firmware version from the admin queue commands 2592 **/ 2593 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw, 2594 u16 *fw_major_version, u16 *fw_minor_version, 2595 u32 *fw_build, 2596 u16 *api_major_version, u16 *api_minor_version, 2597 struct i40e_asq_cmd_details *cmd_details) 2598 { 2599 struct i40e_aq_desc desc; 2600 struct i40e_aqc_get_version *resp = 2601 (struct i40e_aqc_get_version *)&desc.params.raw; 2602 enum i40e_status_code status; 2603 2604 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version); 2605 2606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2607 2608 if (status == I40E_SUCCESS) { 2609 if (fw_major_version != NULL) 2610 *fw_major_version = LE16_TO_CPU(resp->fw_major); 2611 if (fw_minor_version != NULL) 2612 *fw_minor_version = LE16_TO_CPU(resp->fw_minor); 2613 if (fw_build != NULL) 2614 *fw_build = LE32_TO_CPU(resp->fw_build); 2615 if (api_major_version != NULL) 2616 *api_major_version = LE16_TO_CPU(resp->api_major); 2617 if (api_minor_version != NULL) 2618 *api_minor_version = LE16_TO_CPU(resp->api_minor); 2619 2620 /* A workaround to fix the API version in SW */ 2621 if (api_major_version && api_minor_version && 2622 fw_major_version && fw_minor_version && 2623 ((*api_major_version == 1) && (*api_minor_version == 1)) && 2624 (((*fw_major_version == 4) && (*fw_minor_version >= 2)) || 2625 (*fw_major_version > 4))) 2626 *api_minor_version = 2; 2627 } 2628 2629 return status; 2630 } 2631 2632 /** 2633 * i40e_aq_send_driver_version 2634 * @hw: pointer to the hw struct 2635 * @dv: driver's major, minor version 2636 * @cmd_details: pointer to command details structure or NULL 2637 * 2638 * Send the driver version to the firmware 2639 **/ 2640 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw, 2641 struct i40e_driver_version *dv, 2642 struct i40e_asq_cmd_details *cmd_details) 2643 { 2644 struct i40e_aq_desc desc; 2645 struct i40e_aqc_driver_version *cmd = 2646 (struct i40e_aqc_driver_version *)&desc.params.raw; 2647 enum i40e_status_code status; 2648 u16 len; 2649 2650 if (dv == NULL) 2651 return I40E_ERR_PARAM; 2652 2653 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version); 2654 2655 desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); 2656 cmd->driver_major_ver = dv->major_version; 2657 cmd->driver_minor_ver = dv->minor_version; 2658 cmd->driver_build_ver = dv->build_version; 2659 cmd->driver_subbuild_ver = dv->subbuild_version; 2660 2661 len = 0; 2662 while (len < sizeof(dv->driver_string) && 2663 (dv->driver_string[len] < 0x80) && 2664 dv->driver_string[len]) 2665 len++; 2666 status = i40e_asq_send_command(hw, &desc, dv->driver_string, 2667 len, cmd_details); 2668 2669 return status; 2670 } 2671 2672 /** 2673 * i40e_get_link_status - get status of the HW network link 2674 * @hw: pointer to the hw struct 2675 * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown) 2676 * 2677 * Variable link_up TRUE if link is up, FALSE if link is down. 2678 * The variable link_up is invalid if returned value of status != I40E_SUCCESS 2679 * 2680 * Side effect: LinkStatusEvent reporting becomes enabled 2681 **/ 2682 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up) 2683 { 2684 enum i40e_status_code status = I40E_SUCCESS; 2685 2686 if (hw->phy.get_link_info) { 2687 status = i40e_update_link_info(hw); 2688 2689 if (status != I40E_SUCCESS) 2690 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n", 2691 status); 2692 } 2693 2694 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP; 2695 2696 return status; 2697 } 2698 2699 /** 2700 * i40e_updatelink_status - update status of the HW network link 2701 * @hw: pointer to the hw struct 2702 **/ 2703 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw) 2704 { 2705 struct i40e_aq_get_phy_abilities_resp abilities; 2706 enum i40e_status_code status = I40E_SUCCESS; 2707 2708 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2709 if (status) 2710 return status; 2711 2712 /* extra checking needed to ensure link info to user is timely */ 2713 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) && 2714 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) || 2715 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) { 2716 status = i40e_aq_get_phy_capabilities(hw, FALSE, false, 2717 &abilities, NULL); 2718 if (status) 2719 return status; 2720 2721 i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type, 2722 sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA); 2723 } 2724 return status; 2725 } 2726 2727 2728 /** 2729 * i40e_get_link_speed 2730 * @hw: pointer to the hw struct 2731 * 2732 * Returns the link speed of the adapter. 2733 **/ 2734 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw) 2735 { 2736 enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN; 2737 enum i40e_status_code status = I40E_SUCCESS; 2738 2739 if (hw->phy.get_link_info) { 2740 status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL); 2741 2742 if (status != I40E_SUCCESS) 2743 goto i40e_link_speed_exit; 2744 } 2745 2746 speed = hw->phy.link_info.link_speed; 2747 2748 i40e_link_speed_exit: 2749 return speed; 2750 } 2751 2752 /** 2753 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC 2754 * @hw: pointer to the hw struct 2755 * @uplink_seid: the MAC or other gizmo SEID 2756 * @downlink_seid: the VSI SEID 2757 * @enabled_tc: bitmap of TCs to be enabled 2758 * @default_port: TRUE for default port VSI, FALSE for control port 2759 * @veb_seid: pointer to where to put the resulting VEB SEID 2760 * @enable_stats: TRUE to turn on VEB stats 2761 * @cmd_details: pointer to command details structure or NULL 2762 * 2763 * This asks the FW to add a VEB between the uplink and downlink 2764 * elements. If the uplink SEID is 0, this will be a floating VEB. 2765 **/ 2766 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid, 2767 u16 downlink_seid, u8 enabled_tc, 2768 bool default_port, u16 *veb_seid, 2769 bool enable_stats, 2770 struct i40e_asq_cmd_details *cmd_details) 2771 { 2772 struct i40e_aq_desc desc; 2773 struct i40e_aqc_add_veb *cmd = 2774 (struct i40e_aqc_add_veb *)&desc.params.raw; 2775 struct i40e_aqc_add_veb_completion *resp = 2776 (struct i40e_aqc_add_veb_completion *)&desc.params.raw; 2777 enum i40e_status_code status; 2778 u16 veb_flags = 0; 2779 2780 /* SEIDs need to either both be set or both be 0 for floating VEB */ 2781 if (!!uplink_seid != !!downlink_seid) 2782 return I40E_ERR_PARAM; 2783 2784 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb); 2785 2786 cmd->uplink_seid = CPU_TO_LE16(uplink_seid); 2787 cmd->downlink_seid = CPU_TO_LE16(downlink_seid); 2788 cmd->enable_tcs = enabled_tc; 2789 if (!uplink_seid) 2790 veb_flags |= I40E_AQC_ADD_VEB_FLOATING; 2791 if (default_port) 2792 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT; 2793 else 2794 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA; 2795 2796 /* reverse logic here: set the bitflag to disable the stats */ 2797 if (!enable_stats) 2798 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS; 2799 2800 cmd->veb_flags = CPU_TO_LE16(veb_flags); 2801 2802 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2803 2804 if (!status && veb_seid) 2805 *veb_seid = LE16_TO_CPU(resp->veb_seid); 2806 2807 return status; 2808 } 2809 2810 /** 2811 * i40e_aq_get_veb_parameters - Retrieve VEB parameters 2812 * @hw: pointer to the hw struct 2813 * @veb_seid: the SEID of the VEB to query 2814 * @switch_id: the uplink switch id 2815 * @floating: set to TRUE if the VEB is floating 2816 * @statistic_index: index of the stats counter block for this VEB 2817 * @vebs_used: number of VEB's used by function 2818 * @vebs_free: total VEB's not reserved by any function 2819 * @cmd_details: pointer to command details structure or NULL 2820 * 2821 * This retrieves the parameters for a particular VEB, specified by 2822 * uplink_seid, and returns them to the caller. 2823 **/ 2824 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw, 2825 u16 veb_seid, u16 *switch_id, 2826 bool *floating, u16 *statistic_index, 2827 u16 *vebs_used, u16 *vebs_free, 2828 struct i40e_asq_cmd_details *cmd_details) 2829 { 2830 struct i40e_aq_desc desc; 2831 struct i40e_aqc_get_veb_parameters_completion *cmd_resp = 2832 (struct i40e_aqc_get_veb_parameters_completion *) 2833 &desc.params.raw; 2834 enum i40e_status_code status; 2835 2836 if (veb_seid == 0) 2837 return I40E_ERR_PARAM; 2838 2839 i40e_fill_default_direct_cmd_desc(&desc, 2840 i40e_aqc_opc_get_veb_parameters); 2841 cmd_resp->seid = CPU_TO_LE16(veb_seid); 2842 2843 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details); 2844 if (status) 2845 goto get_veb_exit; 2846 2847 if (switch_id) 2848 *switch_id = LE16_TO_CPU(cmd_resp->switch_id); 2849 if (statistic_index) 2850 *statistic_index = LE16_TO_CPU(cmd_resp->statistic_index); 2851 if (vebs_used) 2852 *vebs_used = LE16_TO_CPU(cmd_resp->vebs_used); 2853 if (vebs_free) 2854 *vebs_free = LE16_TO_CPU(cmd_resp->vebs_free); 2855 if (floating) { 2856 u16 flags = LE16_TO_CPU(cmd_resp->veb_flags); 2857 2858 if (flags & I40E_AQC_ADD_VEB_FLOATING) 2859 *floating = TRUE; 2860 else 2861 *floating = FALSE; 2862 } 2863 2864 get_veb_exit: 2865 return status; 2866 } 2867 2868 /** 2869 * i40e_aq_add_macvlan 2870 * @hw: pointer to the hw struct 2871 * @seid: VSI for the mac address 2872 * @mv_list: list of macvlans to be added 2873 * @count: length of the list 2874 * @cmd_details: pointer to command details structure or NULL 2875 * 2876 * Add MAC/VLAN addresses to the HW filtering 2877 **/ 2878 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid, 2879 struct i40e_aqc_add_macvlan_element_data *mv_list, 2880 u16 count, struct i40e_asq_cmd_details *cmd_details) 2881 { 2882 struct i40e_aq_desc desc; 2883 struct i40e_aqc_macvlan *cmd = 2884 (struct i40e_aqc_macvlan *)&desc.params.raw; 2885 enum i40e_status_code status; 2886 u16 buf_size; 2887 int i; 2888 2889 if (count == 0 || !mv_list || !hw) 2890 return I40E_ERR_PARAM; 2891 2892 buf_size = count * sizeof(*mv_list); 2893 2894 /* prep the rest of the request */ 2895 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan); 2896 cmd->num_addresses = CPU_TO_LE16(count); 2897 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2898 cmd->seid[1] = 0; 2899 cmd->seid[2] = 0; 2900 2901 for (i = 0; i < count; i++) 2902 if (I40E_IS_MULTICAST(mv_list[i].mac_addr)) 2903 mv_list[i].flags |= 2904 CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC); 2905 2906 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2907 if (buf_size > I40E_AQ_LARGE_BUF) 2908 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2909 2910 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2911 cmd_details); 2912 2913 return status; 2914 } 2915 2916 /** 2917 * i40e_aq_remove_macvlan 2918 * @hw: pointer to the hw struct 2919 * @seid: VSI for the mac address 2920 * @mv_list: list of macvlans to be removed 2921 * @count: length of the list 2922 * @cmd_details: pointer to command details structure or NULL 2923 * 2924 * Remove MAC/VLAN addresses from the HW filtering 2925 **/ 2926 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid, 2927 struct i40e_aqc_remove_macvlan_element_data *mv_list, 2928 u16 count, struct i40e_asq_cmd_details *cmd_details) 2929 { 2930 struct i40e_aq_desc desc; 2931 struct i40e_aqc_macvlan *cmd = 2932 (struct i40e_aqc_macvlan *)&desc.params.raw; 2933 enum i40e_status_code status; 2934 u16 buf_size; 2935 2936 if (count == 0 || !mv_list || !hw) 2937 return I40E_ERR_PARAM; 2938 2939 buf_size = count * sizeof(*mv_list); 2940 2941 /* prep the rest of the request */ 2942 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan); 2943 cmd->num_addresses = CPU_TO_LE16(count); 2944 cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid); 2945 cmd->seid[1] = 0; 2946 cmd->seid[2] = 0; 2947 2948 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD)); 2949 if (buf_size > I40E_AQ_LARGE_BUF) 2950 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 2951 2952 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size, 2953 cmd_details); 2954 2955 return status; 2956 } 2957 2958 /** 2959 * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule 2960 * @hw: pointer to the hw struct 2961 * @opcode: AQ opcode for add or delete mirror rule 2962 * @sw_seid: Switch SEID (to which rule refers) 2963 * @rule_type: Rule Type (ingress/egress/VLAN) 2964 * @id: Destination VSI SEID or Rule ID 2965 * @count: length of the list 2966 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 2967 * @cmd_details: pointer to command details structure or NULL 2968 * @rule_id: Rule ID returned from FW 2969 * @rule_used: Number of rules used in internal switch 2970 * @rule_free: Number of rules free in internal switch 2971 * 2972 * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for 2973 * VEBs/VEPA elements only 2974 **/ 2975 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw, 2976 u16 opcode, u16 sw_seid, u16 rule_type, u16 id, 2977 u16 count, __le16 *mr_list, 2978 struct i40e_asq_cmd_details *cmd_details, 2979 u16 *rule_id, u16 *rules_used, u16 *rules_free) 2980 { 2981 struct i40e_aq_desc desc; 2982 struct i40e_aqc_add_delete_mirror_rule *cmd = 2983 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw; 2984 struct i40e_aqc_add_delete_mirror_rule_completion *resp = 2985 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw; 2986 enum i40e_status_code status; 2987 u16 buf_size; 2988 2989 buf_size = count * sizeof(*mr_list); 2990 2991 /* prep the rest of the request */ 2992 i40e_fill_default_direct_cmd_desc(&desc, opcode); 2993 cmd->seid = CPU_TO_LE16(sw_seid); 2994 cmd->rule_type = CPU_TO_LE16(rule_type & 2995 I40E_AQC_MIRROR_RULE_TYPE_MASK); 2996 cmd->num_entries = CPU_TO_LE16(count); 2997 /* Dest VSI for add, rule_id for delete */ 2998 cmd->destination = CPU_TO_LE16(id); 2999 if (mr_list) { 3000 desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | 3001 I40E_AQ_FLAG_RD)); 3002 if (buf_size > I40E_AQ_LARGE_BUF) 3003 desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB); 3004 } 3005 3006 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size, 3007 cmd_details); 3008 if (status == I40E_SUCCESS || 3009 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) { 3010 if (rule_id) 3011 *rule_id = LE16_TO_CPU(resp->rule_id); 3012 if (rules_used) 3013 *rules_used = LE16_TO_CPU(resp->mirror_rules_used); 3014 if (rules_free) 3015 *rules_free = LE16_TO_CPU(resp->mirror_rules_free); 3016 } 3017 return status; 3018 } 3019 3020 /** 3021 * i40e_aq_add_mirrorrule - add a mirror rule 3022 * @hw: pointer to the hw struct 3023 * @sw_seid: Switch SEID (to which rule refers) 3024 * @rule_type: Rule Type (ingress/egress/VLAN) 3025 * @dest_vsi: SEID of VSI to which packets will be mirrored 3026 * @count: length of the list 3027 * @mr_list: list of mirrored VSI SEIDs or VLAN IDs 3028 * @cmd_details: pointer to command details structure or NULL 3029 * @rule_id: Rule ID returned from FW 3030 * @rule_used: Number of rules used in internal switch 3031 * @rule_free: Number of rules free in internal switch 3032 * 3033 * Add mirror rule. Mirror rules are supported for VEBs or VEPA elements only 3034 **/ 3035 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid, 3036 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list, 3037 struct i40e_asq_cmd_details *cmd_details, 3038 u16 *rule_id, u16 *rules_used, u16 *rules_free) 3039 { 3040 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS || 3041 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) { 3042 if (count == 0 || !mr_list) 3043 return I40E_ERR_PARAM; 3044 } 3045 3046 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid, 3047 rule_type, dest_vsi, count, mr_list, 3048 cmd_details, rule_id, rules_used, rules_free); 3049 } 3050 3051