1 /******************************************************************************
2 
3   Copyright (c) 2013-2017, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8 
9    1. Redistributions of source code must retain the above copyright notice,
10       this list of conditions and the following disclaimer.
11 
12    2. Redistributions in binary form must reproduce the above copyright
13       notice, this list of conditions and the following disclaimer in the
14       documentation and/or other materials provided with the distribution.
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16    3. Neither the name of the Intel Corporation nor the names of its
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18       this software without specific prior written permission.
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20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #include "i40e_type.h"
36 #include "i40e_adminq.h"
37 #include "i40e_prototype.h"
38 #include "virtchnl.h"
39 
40 
41 /**
42  * i40e_set_mac_type - Sets MAC type
43  * @hw: pointer to the HW structure
44  *
45  * This function sets the mac type of the adapter based on the
46  * vendor ID and device ID stored in the hw structure.
47  **/
48 static enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)
49 {
50 	enum i40e_status_code status = I40E_SUCCESS;
51 
52 	DEBUGFUNC("i40e_set_mac_type\n");
53 
54 	if (hw->vendor_id == I40E_INTEL_VENDOR_ID) {
55 		switch (hw->device_id) {
56 		case I40E_DEV_ID_SFP_XL710:
57 		case I40E_DEV_ID_QEMU:
58 		case I40E_DEV_ID_KX_B:
59 		case I40E_DEV_ID_KX_C:
60 		case I40E_DEV_ID_QSFP_A:
61 		case I40E_DEV_ID_QSFP_B:
62 		case I40E_DEV_ID_QSFP_C:
63 		case I40E_DEV_ID_10G_BASE_T:
64 		case I40E_DEV_ID_10G_BASE_T4:
65 		case I40E_DEV_ID_20G_KR2:
66 		case I40E_DEV_ID_20G_KR2_A:
67 		case I40E_DEV_ID_25G_B:
68 		case I40E_DEV_ID_25G_SFP28:
69 			hw->mac.type = I40E_MAC_XL710;
70 			break;
71 		case I40E_DEV_ID_KX_X722:
72 		case I40E_DEV_ID_QSFP_X722:
73 		case I40E_DEV_ID_SFP_X722:
74 		case I40E_DEV_ID_1G_BASE_T_X722:
75 		case I40E_DEV_ID_10G_BASE_T_X722:
76 		case I40E_DEV_ID_SFP_I_X722:
77 			hw->mac.type = I40E_MAC_X722;
78 			break;
79 		default:
80 			hw->mac.type = I40E_MAC_GENERIC;
81 			break;
82 		}
83 	} else {
84 		status = I40E_ERR_DEVICE_NOT_SUPPORTED;
85 	}
86 
87 	DEBUGOUT2("i40e_set_mac_type found mac: %d, returns: %d\n",
88 		  hw->mac.type, status);
89 	return status;
90 }
91 
92 /**
93  * i40e_aq_str - convert AQ err code to a string
94  * @hw: pointer to the HW structure
95  * @aq_err: the AQ error code to convert
96  **/
97 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
98 {
99 	switch (aq_err) {
100 	case I40E_AQ_RC_OK:
101 		return "OK";
102 	case I40E_AQ_RC_EPERM:
103 		return "I40E_AQ_RC_EPERM";
104 	case I40E_AQ_RC_ENOENT:
105 		return "I40E_AQ_RC_ENOENT";
106 	case I40E_AQ_RC_ESRCH:
107 		return "I40E_AQ_RC_ESRCH";
108 	case I40E_AQ_RC_EINTR:
109 		return "I40E_AQ_RC_EINTR";
110 	case I40E_AQ_RC_EIO:
111 		return "I40E_AQ_RC_EIO";
112 	case I40E_AQ_RC_ENXIO:
113 		return "I40E_AQ_RC_ENXIO";
114 	case I40E_AQ_RC_E2BIG:
115 		return "I40E_AQ_RC_E2BIG";
116 	case I40E_AQ_RC_EAGAIN:
117 		return "I40E_AQ_RC_EAGAIN";
118 	case I40E_AQ_RC_ENOMEM:
119 		return "I40E_AQ_RC_ENOMEM";
120 	case I40E_AQ_RC_EACCES:
121 		return "I40E_AQ_RC_EACCES";
122 	case I40E_AQ_RC_EFAULT:
123 		return "I40E_AQ_RC_EFAULT";
124 	case I40E_AQ_RC_EBUSY:
125 		return "I40E_AQ_RC_EBUSY";
126 	case I40E_AQ_RC_EEXIST:
127 		return "I40E_AQ_RC_EEXIST";
128 	case I40E_AQ_RC_EINVAL:
129 		return "I40E_AQ_RC_EINVAL";
130 	case I40E_AQ_RC_ENOTTY:
131 		return "I40E_AQ_RC_ENOTTY";
132 	case I40E_AQ_RC_ENOSPC:
133 		return "I40E_AQ_RC_ENOSPC";
134 	case I40E_AQ_RC_ENOSYS:
135 		return "I40E_AQ_RC_ENOSYS";
136 	case I40E_AQ_RC_ERANGE:
137 		return "I40E_AQ_RC_ERANGE";
138 	case I40E_AQ_RC_EFLUSHED:
139 		return "I40E_AQ_RC_EFLUSHED";
140 	case I40E_AQ_RC_BAD_ADDR:
141 		return "I40E_AQ_RC_BAD_ADDR";
142 	case I40E_AQ_RC_EMODE:
143 		return "I40E_AQ_RC_EMODE";
144 	case I40E_AQ_RC_EFBIG:
145 		return "I40E_AQ_RC_EFBIG";
146 	}
147 
148 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
149 	return hw->err_str;
150 }
151 
152 /**
153  * i40e_stat_str - convert status err code to a string
154  * @hw: pointer to the HW structure
155  * @stat_err: the status error code to convert
156  **/
157 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err)
158 {
159 	switch (stat_err) {
160 	case I40E_SUCCESS:
161 		return "OK";
162 	case I40E_ERR_NVM:
163 		return "I40E_ERR_NVM";
164 	case I40E_ERR_NVM_CHECKSUM:
165 		return "I40E_ERR_NVM_CHECKSUM";
166 	case I40E_ERR_PHY:
167 		return "I40E_ERR_PHY";
168 	case I40E_ERR_CONFIG:
169 		return "I40E_ERR_CONFIG";
170 	case I40E_ERR_PARAM:
171 		return "I40E_ERR_PARAM";
172 	case I40E_ERR_MAC_TYPE:
173 		return "I40E_ERR_MAC_TYPE";
174 	case I40E_ERR_UNKNOWN_PHY:
175 		return "I40E_ERR_UNKNOWN_PHY";
176 	case I40E_ERR_LINK_SETUP:
177 		return "I40E_ERR_LINK_SETUP";
178 	case I40E_ERR_ADAPTER_STOPPED:
179 		return "I40E_ERR_ADAPTER_STOPPED";
180 	case I40E_ERR_INVALID_MAC_ADDR:
181 		return "I40E_ERR_INVALID_MAC_ADDR";
182 	case I40E_ERR_DEVICE_NOT_SUPPORTED:
183 		return "I40E_ERR_DEVICE_NOT_SUPPORTED";
184 	case I40E_ERR_MASTER_REQUESTS_PENDING:
185 		return "I40E_ERR_MASTER_REQUESTS_PENDING";
186 	case I40E_ERR_INVALID_LINK_SETTINGS:
187 		return "I40E_ERR_INVALID_LINK_SETTINGS";
188 	case I40E_ERR_AUTONEG_NOT_COMPLETE:
189 		return "I40E_ERR_AUTONEG_NOT_COMPLETE";
190 	case I40E_ERR_RESET_FAILED:
191 		return "I40E_ERR_RESET_FAILED";
192 	case I40E_ERR_SWFW_SYNC:
193 		return "I40E_ERR_SWFW_SYNC";
194 	case I40E_ERR_NO_AVAILABLE_VSI:
195 		return "I40E_ERR_NO_AVAILABLE_VSI";
196 	case I40E_ERR_NO_MEMORY:
197 		return "I40E_ERR_NO_MEMORY";
198 	case I40E_ERR_BAD_PTR:
199 		return "I40E_ERR_BAD_PTR";
200 	case I40E_ERR_RING_FULL:
201 		return "I40E_ERR_RING_FULL";
202 	case I40E_ERR_INVALID_PD_ID:
203 		return "I40E_ERR_INVALID_PD_ID";
204 	case I40E_ERR_INVALID_QP_ID:
205 		return "I40E_ERR_INVALID_QP_ID";
206 	case I40E_ERR_INVALID_CQ_ID:
207 		return "I40E_ERR_INVALID_CQ_ID";
208 	case I40E_ERR_INVALID_CEQ_ID:
209 		return "I40E_ERR_INVALID_CEQ_ID";
210 	case I40E_ERR_INVALID_AEQ_ID:
211 		return "I40E_ERR_INVALID_AEQ_ID";
212 	case I40E_ERR_INVALID_SIZE:
213 		return "I40E_ERR_INVALID_SIZE";
214 	case I40E_ERR_INVALID_ARP_INDEX:
215 		return "I40E_ERR_INVALID_ARP_INDEX";
216 	case I40E_ERR_INVALID_FPM_FUNC_ID:
217 		return "I40E_ERR_INVALID_FPM_FUNC_ID";
218 	case I40E_ERR_QP_INVALID_MSG_SIZE:
219 		return "I40E_ERR_QP_INVALID_MSG_SIZE";
220 	case I40E_ERR_QP_TOOMANY_WRS_POSTED:
221 		return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
222 	case I40E_ERR_INVALID_FRAG_COUNT:
223 		return "I40E_ERR_INVALID_FRAG_COUNT";
224 	case I40E_ERR_QUEUE_EMPTY:
225 		return "I40E_ERR_QUEUE_EMPTY";
226 	case I40E_ERR_INVALID_ALIGNMENT:
227 		return "I40E_ERR_INVALID_ALIGNMENT";
228 	case I40E_ERR_FLUSHED_QUEUE:
229 		return "I40E_ERR_FLUSHED_QUEUE";
230 	case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
231 		return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
232 	case I40E_ERR_INVALID_IMM_DATA_SIZE:
233 		return "I40E_ERR_INVALID_IMM_DATA_SIZE";
234 	case I40E_ERR_TIMEOUT:
235 		return "I40E_ERR_TIMEOUT";
236 	case I40E_ERR_OPCODE_MISMATCH:
237 		return "I40E_ERR_OPCODE_MISMATCH";
238 	case I40E_ERR_CQP_COMPL_ERROR:
239 		return "I40E_ERR_CQP_COMPL_ERROR";
240 	case I40E_ERR_INVALID_VF_ID:
241 		return "I40E_ERR_INVALID_VF_ID";
242 	case I40E_ERR_INVALID_HMCFN_ID:
243 		return "I40E_ERR_INVALID_HMCFN_ID";
244 	case I40E_ERR_BACKING_PAGE_ERROR:
245 		return "I40E_ERR_BACKING_PAGE_ERROR";
246 	case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
247 		return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
248 	case I40E_ERR_INVALID_PBLE_INDEX:
249 		return "I40E_ERR_INVALID_PBLE_INDEX";
250 	case I40E_ERR_INVALID_SD_INDEX:
251 		return "I40E_ERR_INVALID_SD_INDEX";
252 	case I40E_ERR_INVALID_PAGE_DESC_INDEX:
253 		return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
254 	case I40E_ERR_INVALID_SD_TYPE:
255 		return "I40E_ERR_INVALID_SD_TYPE";
256 	case I40E_ERR_MEMCPY_FAILED:
257 		return "I40E_ERR_MEMCPY_FAILED";
258 	case I40E_ERR_INVALID_HMC_OBJ_INDEX:
259 		return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
260 	case I40E_ERR_INVALID_HMC_OBJ_COUNT:
261 		return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
262 	case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
263 		return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
264 	case I40E_ERR_SRQ_ENABLED:
265 		return "I40E_ERR_SRQ_ENABLED";
266 	case I40E_ERR_ADMIN_QUEUE_ERROR:
267 		return "I40E_ERR_ADMIN_QUEUE_ERROR";
268 	case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
269 		return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
270 	case I40E_ERR_BUF_TOO_SHORT:
271 		return "I40E_ERR_BUF_TOO_SHORT";
272 	case I40E_ERR_ADMIN_QUEUE_FULL:
273 		return "I40E_ERR_ADMIN_QUEUE_FULL";
274 	case I40E_ERR_ADMIN_QUEUE_NO_WORK:
275 		return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
276 	case I40E_ERR_BAD_IWARP_CQE:
277 		return "I40E_ERR_BAD_IWARP_CQE";
278 	case I40E_ERR_NVM_BLANK_MODE:
279 		return "I40E_ERR_NVM_BLANK_MODE";
280 	case I40E_ERR_NOT_IMPLEMENTED:
281 		return "I40E_ERR_NOT_IMPLEMENTED";
282 	case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
283 		return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
284 	case I40E_ERR_DIAG_TEST_FAILED:
285 		return "I40E_ERR_DIAG_TEST_FAILED";
286 	case I40E_ERR_NOT_READY:
287 		return "I40E_ERR_NOT_READY";
288 	case I40E_NOT_SUPPORTED:
289 		return "I40E_NOT_SUPPORTED";
290 	case I40E_ERR_FIRMWARE_API_VERSION:
291 		return "I40E_ERR_FIRMWARE_API_VERSION";
292 	case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
293 		return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
294 	}
295 
296 	snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
297 	return hw->err_str;
298 }
299 
300 /**
301  * i40e_debug_aq
302  * @hw: debug mask related to admin queue
303  * @mask: debug mask
304  * @desc: pointer to admin queue descriptor
305  * @buffer: pointer to command buffer
306  * @buf_len: max length of buffer
307  *
308  * Dumps debug log about adminq command with descriptor contents.
309  **/
310 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
311 		   void *buffer, u16 buf_len)
312 {
313 	struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
314 	u8 *buf = (u8 *)buffer;
315 	u16 len;
316 	u16 i = 0;
317 
318 	if ((!(mask & hw->debug_mask)) || (desc == NULL))
319 		return;
320 
321 	len = LE16_TO_CPU(aq_desc->datalen);
322 
323 	i40e_debug(hw, mask,
324 		   "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
325 		   LE16_TO_CPU(aq_desc->opcode),
326 		   LE16_TO_CPU(aq_desc->flags),
327 		   LE16_TO_CPU(aq_desc->datalen),
328 		   LE16_TO_CPU(aq_desc->retval));
329 	i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
330 		   LE32_TO_CPU(aq_desc->cookie_high),
331 		   LE32_TO_CPU(aq_desc->cookie_low));
332 	i40e_debug(hw, mask, "\tparam (0,1)  0x%08X 0x%08X\n",
333 		   LE32_TO_CPU(aq_desc->params.internal.param0),
334 		   LE32_TO_CPU(aq_desc->params.internal.param1));
335 	i40e_debug(hw, mask, "\taddr (h,l)   0x%08X 0x%08X\n",
336 		   LE32_TO_CPU(aq_desc->params.external.addr_high),
337 		   LE32_TO_CPU(aq_desc->params.external.addr_low));
338 
339 	if ((buffer != NULL) && (aq_desc->datalen != 0)) {
340 		i40e_debug(hw, mask, "AQ CMD Buffer:\n");
341 		if (buf_len < len)
342 			len = buf_len;
343 		/* write the full 16-byte chunks */
344 		for (i = 0; i < (len - 16); i += 16)
345 			i40e_debug(hw, mask,
346 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
347 				   i, buf[i], buf[i+1], buf[i+2], buf[i+3],
348 				   buf[i+4], buf[i+5], buf[i+6], buf[i+7],
349 				   buf[i+8], buf[i+9], buf[i+10], buf[i+11],
350 				   buf[i+12], buf[i+13], buf[i+14], buf[i+15]);
351 		/* the most we could have left is 16 bytes, pad with zeros */
352 		if (i < len) {
353 			char d_buf[16];
354 			int j, i_sav;
355 
356 			i_sav = i;
357 			memset(d_buf, 0, sizeof(d_buf));
358 			for (j = 0; i < len; j++, i++)
359 				d_buf[j] = buf[i];
360 			i40e_debug(hw, mask,
361 				   "\t0x%04X  %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
362 				   i_sav, d_buf[0], d_buf[1], d_buf[2], d_buf[3],
363 				   d_buf[4], d_buf[5], d_buf[6], d_buf[7],
364 				   d_buf[8], d_buf[9], d_buf[10], d_buf[11],
365 				   d_buf[12], d_buf[13], d_buf[14], d_buf[15]);
366 		}
367 	}
368 }
369 
370 /**
371  * i40e_check_asq_alive
372  * @hw: pointer to the hw struct
373  *
374  * Returns TRUE if Queue is enabled else FALSE.
375  **/
376 bool i40e_check_asq_alive(struct i40e_hw *hw)
377 {
378 	if (hw->aq.asq.len)
379 		return !!(rd32(hw, hw->aq.asq.len) &
380 			I40E_PF_ATQLEN_ATQENABLE_MASK);
381 	return FALSE;
382 }
383 
384 /**
385  * i40e_aq_queue_shutdown
386  * @hw: pointer to the hw struct
387  * @unloading: is the driver unloading itself
388  *
389  * Tell the Firmware that we're shutting down the AdminQ and whether
390  * or not the driver is unloading as well.
391  **/
392 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw,
393 					     bool unloading)
394 {
395 	struct i40e_aq_desc desc;
396 	struct i40e_aqc_queue_shutdown *cmd =
397 		(struct i40e_aqc_queue_shutdown *)&desc.params.raw;
398 	enum i40e_status_code status;
399 
400 	i40e_fill_default_direct_cmd_desc(&desc,
401 					  i40e_aqc_opc_queue_shutdown);
402 
403 	if (unloading)
404 		cmd->driver_unloading = CPU_TO_LE32(I40E_AQ_DRIVER_UNLOADING);
405 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
406 
407 	return status;
408 }
409 
410 /**
411  * i40e_aq_get_set_rss_lut
412  * @hw: pointer to the hardware structure
413  * @vsi_id: vsi fw index
414  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
415  * @lut: pointer to the lut buffer provided by the caller
416  * @lut_size: size of the lut buffer
417  * @set: set TRUE to set the table, FALSE to get the table
418  *
419  * Internal function to get or set RSS look up table
420  **/
421 static enum i40e_status_code i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
422 						     u16 vsi_id, bool pf_lut,
423 						     u8 *lut, u16 lut_size,
424 						     bool set)
425 {
426 	enum i40e_status_code status;
427 	struct i40e_aq_desc desc;
428 	struct i40e_aqc_get_set_rss_lut *cmd_resp =
429 		   (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
430 
431 	if (set)
432 		i40e_fill_default_direct_cmd_desc(&desc,
433 						  i40e_aqc_opc_set_rss_lut);
434 	else
435 		i40e_fill_default_direct_cmd_desc(&desc,
436 						  i40e_aqc_opc_get_rss_lut);
437 
438 	/* Indirect command */
439 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
440 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
441 
442 	cmd_resp->vsi_id =
443 			CPU_TO_LE16((u16)((vsi_id <<
444 					  I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
445 					  I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
446 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
447 
448 	if (pf_lut)
449 		cmd_resp->flags |= CPU_TO_LE16((u16)
450 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
451 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
452 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
453 	else
454 		cmd_resp->flags |= CPU_TO_LE16((u16)
455 					((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
456 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
457 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
458 
459 	status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
460 
461 	return status;
462 }
463 
464 /**
465  * i40e_aq_get_rss_lut
466  * @hw: pointer to the hardware structure
467  * @vsi_id: vsi fw index
468  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
469  * @lut: pointer to the lut buffer provided by the caller
470  * @lut_size: size of the lut buffer
471  *
472  * get the RSS lookup table, PF or VSI type
473  **/
474 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
475 					  bool pf_lut, u8 *lut, u16 lut_size)
476 {
477 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
478 				       FALSE);
479 }
480 
481 /**
482  * i40e_aq_set_rss_lut
483  * @hw: pointer to the hardware structure
484  * @vsi_id: vsi fw index
485  * @pf_lut: for PF table set TRUE, for VSI table set FALSE
486  * @lut: pointer to the lut buffer provided by the caller
487  * @lut_size: size of the lut buffer
488  *
489  * set the RSS lookup table, PF or VSI type
490  **/
491 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
492 					  bool pf_lut, u8 *lut, u16 lut_size)
493 {
494 	return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, TRUE);
495 }
496 
497 /**
498  * i40e_aq_get_set_rss_key
499  * @hw: pointer to the hw struct
500  * @vsi_id: vsi fw index
501  * @key: pointer to key info struct
502  * @set: set TRUE to set the key, FALSE to get the key
503  *
504  * get the RSS key per VSI
505  **/
506 static enum i40e_status_code i40e_aq_get_set_rss_key(struct i40e_hw *hw,
507 				      u16 vsi_id,
508 				      struct i40e_aqc_get_set_rss_key_data *key,
509 				      bool set)
510 {
511 	enum i40e_status_code status;
512 	struct i40e_aq_desc desc;
513 	struct i40e_aqc_get_set_rss_key *cmd_resp =
514 			(struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
515 	u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
516 
517 	if (set)
518 		i40e_fill_default_direct_cmd_desc(&desc,
519 						  i40e_aqc_opc_set_rss_key);
520 	else
521 		i40e_fill_default_direct_cmd_desc(&desc,
522 						  i40e_aqc_opc_get_rss_key);
523 
524 	/* Indirect command */
525 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
526 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_RD);
527 
528 	cmd_resp->vsi_id =
529 			CPU_TO_LE16((u16)((vsi_id <<
530 					  I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
531 					  I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
532 	cmd_resp->vsi_id |= CPU_TO_LE16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
533 
534 	status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
535 
536 	return status;
537 }
538 
539 /**
540  * i40e_aq_get_rss_key
541  * @hw: pointer to the hw struct
542  * @vsi_id: vsi fw index
543  * @key: pointer to key info struct
544  *
545  **/
546 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
547 				      u16 vsi_id,
548 				      struct i40e_aqc_get_set_rss_key_data *key)
549 {
550 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, FALSE);
551 }
552 
553 /**
554  * i40e_aq_set_rss_key
555  * @hw: pointer to the hw struct
556  * @vsi_id: vsi fw index
557  * @key: pointer to key info struct
558  *
559  * set the RSS key per VSI
560  **/
561 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
562 				      u16 vsi_id,
563 				      struct i40e_aqc_get_set_rss_key_data *key)
564 {
565 	return i40e_aq_get_set_rss_key(hw, vsi_id, key, TRUE);
566 }
567 
568 /* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
569  * hardware to a bit-field that can be used by SW to more easily determine the
570  * packet type.
571  *
572  * Macros are used to shorten the table lines and make this table human
573  * readable.
574  *
575  * We store the PTYPE in the top byte of the bit field - this is just so that
576  * we can check that the table doesn't have a row missing, as the index into
577  * the table should be the PTYPE.
578  *
579  * Typical work flow:
580  *
581  * IF NOT i40e_ptype_lookup[ptype].known
582  * THEN
583  *      Packet is unknown
584  * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
585  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
586  * ELSE
587  *      Use the enum i40e_rx_l2_ptype to decode the packet type
588  * ENDIF
589  */
590 
591 /* macro to make the table lines short */
592 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
593 	{	PTYPE, \
594 		1, \
595 		I40E_RX_PTYPE_OUTER_##OUTER_IP, \
596 		I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
597 		I40E_RX_PTYPE_##OUTER_FRAG, \
598 		I40E_RX_PTYPE_TUNNEL_##T, \
599 		I40E_RX_PTYPE_TUNNEL_END_##TE, \
600 		I40E_RX_PTYPE_##TEF, \
601 		I40E_RX_PTYPE_INNER_PROT_##I, \
602 		I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
603 
604 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
605 		{ PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
606 
607 /* shorter macros makes the table fit but are terse */
608 #define I40E_RX_PTYPE_NOF		I40E_RX_PTYPE_NOT_FRAG
609 #define I40E_RX_PTYPE_FRG		I40E_RX_PTYPE_FRAG
610 #define I40E_RX_PTYPE_INNER_PROT_TS	I40E_RX_PTYPE_INNER_PROT_TIMESYNC
611 
612 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
613 struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
614 	/* L2 Packet types */
615 	I40E_PTT_UNUSED_ENTRY(0),
616 	I40E_PTT(1,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
617 	I40E_PTT(2,  L2, NONE, NOF, NONE, NONE, NOF, TS,   PAY2),
618 	I40E_PTT(3,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
619 	I40E_PTT_UNUSED_ENTRY(4),
620 	I40E_PTT_UNUSED_ENTRY(5),
621 	I40E_PTT(6,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
622 	I40E_PTT(7,  L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
623 	I40E_PTT_UNUSED_ENTRY(8),
624 	I40E_PTT_UNUSED_ENTRY(9),
625 	I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
626 	I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
627 	I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
628 	I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
629 	I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
630 	I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
631 	I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
632 	I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
633 	I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
634 	I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
635 	I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
636 	I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
637 
638 	/* Non Tunneled IPv4 */
639 	I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
640 	I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
641 	I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
642 	I40E_PTT_UNUSED_ENTRY(25),
643 	I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
644 	I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
645 	I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
646 
647 	/* IPv4 --> IPv4 */
648 	I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
649 	I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
650 	I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
651 	I40E_PTT_UNUSED_ENTRY(32),
652 	I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
653 	I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
654 	I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
655 
656 	/* IPv4 --> IPv6 */
657 	I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
658 	I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
659 	I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
660 	I40E_PTT_UNUSED_ENTRY(39),
661 	I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
662 	I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
663 	I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
664 
665 	/* IPv4 --> GRE/NAT */
666 	I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
667 
668 	/* IPv4 --> GRE/NAT --> IPv4 */
669 	I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
670 	I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
671 	I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
672 	I40E_PTT_UNUSED_ENTRY(47),
673 	I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
674 	I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
675 	I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
676 
677 	/* IPv4 --> GRE/NAT --> IPv6 */
678 	I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
679 	I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
680 	I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
681 	I40E_PTT_UNUSED_ENTRY(54),
682 	I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
683 	I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
684 	I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
685 
686 	/* IPv4 --> GRE/NAT --> MAC */
687 	I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
688 
689 	/* IPv4 --> GRE/NAT --> MAC --> IPv4 */
690 	I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
691 	I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
692 	I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
693 	I40E_PTT_UNUSED_ENTRY(62),
694 	I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
695 	I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
696 	I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
697 
698 	/* IPv4 --> GRE/NAT -> MAC --> IPv6 */
699 	I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
700 	I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
701 	I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
702 	I40E_PTT_UNUSED_ENTRY(69),
703 	I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
704 	I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
705 	I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
706 
707 	/* IPv4 --> GRE/NAT --> MAC/VLAN */
708 	I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
709 
710 	/* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
711 	I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
712 	I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
713 	I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
714 	I40E_PTT_UNUSED_ENTRY(77),
715 	I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
716 	I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
717 	I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
718 
719 	/* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
720 	I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
721 	I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
722 	I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
723 	I40E_PTT_UNUSED_ENTRY(84),
724 	I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
725 	I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
726 	I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
727 
728 	/* Non Tunneled IPv6 */
729 	I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
730 	I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
731 	I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
732 	I40E_PTT_UNUSED_ENTRY(91),
733 	I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
734 	I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
735 	I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
736 
737 	/* IPv6 --> IPv4 */
738 	I40E_PTT(95,  IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
739 	I40E_PTT(96,  IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
740 	I40E_PTT(97,  IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
741 	I40E_PTT_UNUSED_ENTRY(98),
742 	I40E_PTT(99,  IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
743 	I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
744 	I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
745 
746 	/* IPv6 --> IPv6 */
747 	I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
748 	I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
749 	I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
750 	I40E_PTT_UNUSED_ENTRY(105),
751 	I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
752 	I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
753 	I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
754 
755 	/* IPv6 --> GRE/NAT */
756 	I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
757 
758 	/* IPv6 --> GRE/NAT -> IPv4 */
759 	I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
760 	I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
761 	I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
762 	I40E_PTT_UNUSED_ENTRY(113),
763 	I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
764 	I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
765 	I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
766 
767 	/* IPv6 --> GRE/NAT -> IPv6 */
768 	I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
769 	I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
770 	I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
771 	I40E_PTT_UNUSED_ENTRY(120),
772 	I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
773 	I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
774 	I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
775 
776 	/* IPv6 --> GRE/NAT -> MAC */
777 	I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
778 
779 	/* IPv6 --> GRE/NAT -> MAC -> IPv4 */
780 	I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
781 	I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
782 	I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
783 	I40E_PTT_UNUSED_ENTRY(128),
784 	I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
785 	I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
786 	I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
787 
788 	/* IPv6 --> GRE/NAT -> MAC -> IPv6 */
789 	I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
790 	I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
791 	I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
792 	I40E_PTT_UNUSED_ENTRY(135),
793 	I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
794 	I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
795 	I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
796 
797 	/* IPv6 --> GRE/NAT -> MAC/VLAN */
798 	I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
799 
800 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
801 	I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
802 	I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
803 	I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
804 	I40E_PTT_UNUSED_ENTRY(143),
805 	I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
806 	I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
807 	I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
808 
809 	/* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
810 	I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
811 	I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
812 	I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
813 	I40E_PTT_UNUSED_ENTRY(150),
814 	I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
815 	I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
816 	I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
817 
818 	/* unused entries */
819 	I40E_PTT_UNUSED_ENTRY(154),
820 	I40E_PTT_UNUSED_ENTRY(155),
821 	I40E_PTT_UNUSED_ENTRY(156),
822 	I40E_PTT_UNUSED_ENTRY(157),
823 	I40E_PTT_UNUSED_ENTRY(158),
824 	I40E_PTT_UNUSED_ENTRY(159),
825 
826 	I40E_PTT_UNUSED_ENTRY(160),
827 	I40E_PTT_UNUSED_ENTRY(161),
828 	I40E_PTT_UNUSED_ENTRY(162),
829 	I40E_PTT_UNUSED_ENTRY(163),
830 	I40E_PTT_UNUSED_ENTRY(164),
831 	I40E_PTT_UNUSED_ENTRY(165),
832 	I40E_PTT_UNUSED_ENTRY(166),
833 	I40E_PTT_UNUSED_ENTRY(167),
834 	I40E_PTT_UNUSED_ENTRY(168),
835 	I40E_PTT_UNUSED_ENTRY(169),
836 
837 	I40E_PTT_UNUSED_ENTRY(170),
838 	I40E_PTT_UNUSED_ENTRY(171),
839 	I40E_PTT_UNUSED_ENTRY(172),
840 	I40E_PTT_UNUSED_ENTRY(173),
841 	I40E_PTT_UNUSED_ENTRY(174),
842 	I40E_PTT_UNUSED_ENTRY(175),
843 	I40E_PTT_UNUSED_ENTRY(176),
844 	I40E_PTT_UNUSED_ENTRY(177),
845 	I40E_PTT_UNUSED_ENTRY(178),
846 	I40E_PTT_UNUSED_ENTRY(179),
847 
848 	I40E_PTT_UNUSED_ENTRY(180),
849 	I40E_PTT_UNUSED_ENTRY(181),
850 	I40E_PTT_UNUSED_ENTRY(182),
851 	I40E_PTT_UNUSED_ENTRY(183),
852 	I40E_PTT_UNUSED_ENTRY(184),
853 	I40E_PTT_UNUSED_ENTRY(185),
854 	I40E_PTT_UNUSED_ENTRY(186),
855 	I40E_PTT_UNUSED_ENTRY(187),
856 	I40E_PTT_UNUSED_ENTRY(188),
857 	I40E_PTT_UNUSED_ENTRY(189),
858 
859 	I40E_PTT_UNUSED_ENTRY(190),
860 	I40E_PTT_UNUSED_ENTRY(191),
861 	I40E_PTT_UNUSED_ENTRY(192),
862 	I40E_PTT_UNUSED_ENTRY(193),
863 	I40E_PTT_UNUSED_ENTRY(194),
864 	I40E_PTT_UNUSED_ENTRY(195),
865 	I40E_PTT_UNUSED_ENTRY(196),
866 	I40E_PTT_UNUSED_ENTRY(197),
867 	I40E_PTT_UNUSED_ENTRY(198),
868 	I40E_PTT_UNUSED_ENTRY(199),
869 
870 	I40E_PTT_UNUSED_ENTRY(200),
871 	I40E_PTT_UNUSED_ENTRY(201),
872 	I40E_PTT_UNUSED_ENTRY(202),
873 	I40E_PTT_UNUSED_ENTRY(203),
874 	I40E_PTT_UNUSED_ENTRY(204),
875 	I40E_PTT_UNUSED_ENTRY(205),
876 	I40E_PTT_UNUSED_ENTRY(206),
877 	I40E_PTT_UNUSED_ENTRY(207),
878 	I40E_PTT_UNUSED_ENTRY(208),
879 	I40E_PTT_UNUSED_ENTRY(209),
880 
881 	I40E_PTT_UNUSED_ENTRY(210),
882 	I40E_PTT_UNUSED_ENTRY(211),
883 	I40E_PTT_UNUSED_ENTRY(212),
884 	I40E_PTT_UNUSED_ENTRY(213),
885 	I40E_PTT_UNUSED_ENTRY(214),
886 	I40E_PTT_UNUSED_ENTRY(215),
887 	I40E_PTT_UNUSED_ENTRY(216),
888 	I40E_PTT_UNUSED_ENTRY(217),
889 	I40E_PTT_UNUSED_ENTRY(218),
890 	I40E_PTT_UNUSED_ENTRY(219),
891 
892 	I40E_PTT_UNUSED_ENTRY(220),
893 	I40E_PTT_UNUSED_ENTRY(221),
894 	I40E_PTT_UNUSED_ENTRY(222),
895 	I40E_PTT_UNUSED_ENTRY(223),
896 	I40E_PTT_UNUSED_ENTRY(224),
897 	I40E_PTT_UNUSED_ENTRY(225),
898 	I40E_PTT_UNUSED_ENTRY(226),
899 	I40E_PTT_UNUSED_ENTRY(227),
900 	I40E_PTT_UNUSED_ENTRY(228),
901 	I40E_PTT_UNUSED_ENTRY(229),
902 
903 	I40E_PTT_UNUSED_ENTRY(230),
904 	I40E_PTT_UNUSED_ENTRY(231),
905 	I40E_PTT_UNUSED_ENTRY(232),
906 	I40E_PTT_UNUSED_ENTRY(233),
907 	I40E_PTT_UNUSED_ENTRY(234),
908 	I40E_PTT_UNUSED_ENTRY(235),
909 	I40E_PTT_UNUSED_ENTRY(236),
910 	I40E_PTT_UNUSED_ENTRY(237),
911 	I40E_PTT_UNUSED_ENTRY(238),
912 	I40E_PTT_UNUSED_ENTRY(239),
913 
914 	I40E_PTT_UNUSED_ENTRY(240),
915 	I40E_PTT_UNUSED_ENTRY(241),
916 	I40E_PTT_UNUSED_ENTRY(242),
917 	I40E_PTT_UNUSED_ENTRY(243),
918 	I40E_PTT_UNUSED_ENTRY(244),
919 	I40E_PTT_UNUSED_ENTRY(245),
920 	I40E_PTT_UNUSED_ENTRY(246),
921 	I40E_PTT_UNUSED_ENTRY(247),
922 	I40E_PTT_UNUSED_ENTRY(248),
923 	I40E_PTT_UNUSED_ENTRY(249),
924 
925 	I40E_PTT_UNUSED_ENTRY(250),
926 	I40E_PTT_UNUSED_ENTRY(251),
927 	I40E_PTT_UNUSED_ENTRY(252),
928 	I40E_PTT_UNUSED_ENTRY(253),
929 	I40E_PTT_UNUSED_ENTRY(254),
930 	I40E_PTT_UNUSED_ENTRY(255)
931 };
932 
933 
934 /**
935  * i40e_validate_mac_addr - Validate unicast MAC address
936  * @mac_addr: pointer to MAC address
937  *
938  * Tests a MAC address to ensure it is a valid Individual Address
939  **/
940 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr)
941 {
942 	enum i40e_status_code status = I40E_SUCCESS;
943 
944 	DEBUGFUNC("i40e_validate_mac_addr");
945 
946 	/* Broadcast addresses ARE multicast addresses
947 	 * Make sure it is not a multicast address
948 	 * Reject the zero address
949 	 */
950 	if (I40E_IS_MULTICAST(mac_addr) ||
951 	    (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
952 	      mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0))
953 		status = I40E_ERR_INVALID_MAC_ADDR;
954 
955 	return status;
956 }
957 
958 /**
959  * i40e_init_shared_code - Initialize the shared code
960  * @hw: pointer to hardware structure
961  *
962  * This assigns the MAC type and PHY code and inits the NVM.
963  * Does not touch the hardware. This function must be called prior to any
964  * other function in the shared code. The i40e_hw structure should be
965  * memset to 0 prior to calling this function.  The following fields in
966  * hw structure should be filled in prior to calling this function:
967  * hw_addr, back, device_id, vendor_id, subsystem_device_id,
968  * subsystem_vendor_id, and revision_id
969  **/
970 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw)
971 {
972 	enum i40e_status_code status = I40E_SUCCESS;
973 	u32 port, ari, func_rid;
974 
975 	DEBUGFUNC("i40e_init_shared_code");
976 
977 	i40e_set_mac_type(hw);
978 
979 	switch (hw->mac.type) {
980 	case I40E_MAC_XL710:
981 	case I40E_MAC_X722:
982 		break;
983 	default:
984 		return I40E_ERR_DEVICE_NOT_SUPPORTED;
985 	}
986 
987 	hw->phy.get_link_info = TRUE;
988 
989 	/* Determine port number and PF number*/
990 	port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
991 					   >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
992 	hw->port = (u8)port;
993 	ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
994 						 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
995 	func_rid = rd32(hw, I40E_PF_FUNC_RID);
996 	if (ari)
997 		hw->pf_id = (u8)(func_rid & 0xff);
998 	else
999 		hw->pf_id = (u8)(func_rid & 0x7);
1000 
1001 	if (hw->mac.type == I40E_MAC_X722)
1002 		hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE |
1003 			     I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK;
1004 
1005 	status = i40e_init_nvm(hw);
1006 	return status;
1007 }
1008 
1009 /**
1010  * i40e_aq_mac_address_read - Retrieve the MAC addresses
1011  * @hw: pointer to the hw struct
1012  * @flags: a return indicator of what addresses were added to the addr store
1013  * @addrs: the requestor's mac addr store
1014  * @cmd_details: pointer to command details structure or NULL
1015  **/
1016 static enum i40e_status_code i40e_aq_mac_address_read(struct i40e_hw *hw,
1017 				   u16 *flags,
1018 				   struct i40e_aqc_mac_address_read_data *addrs,
1019 				   struct i40e_asq_cmd_details *cmd_details)
1020 {
1021 	struct i40e_aq_desc desc;
1022 	struct i40e_aqc_mac_address_read *cmd_data =
1023 		(struct i40e_aqc_mac_address_read *)&desc.params.raw;
1024 	enum i40e_status_code status;
1025 
1026 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
1027 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF);
1028 
1029 	status = i40e_asq_send_command(hw, &desc, addrs,
1030 				       sizeof(*addrs), cmd_details);
1031 	*flags = LE16_TO_CPU(cmd_data->command_flags);
1032 
1033 	return status;
1034 }
1035 
1036 /**
1037  * i40e_aq_mac_address_write - Change the MAC addresses
1038  * @hw: pointer to the hw struct
1039  * @flags: indicates which MAC to be written
1040  * @mac_addr: address to write
1041  * @cmd_details: pointer to command details structure or NULL
1042  **/
1043 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
1044 				    u16 flags, u8 *mac_addr,
1045 				    struct i40e_asq_cmd_details *cmd_details)
1046 {
1047 	struct i40e_aq_desc desc;
1048 	struct i40e_aqc_mac_address_write *cmd_data =
1049 		(struct i40e_aqc_mac_address_write *)&desc.params.raw;
1050 	enum i40e_status_code status;
1051 
1052 	i40e_fill_default_direct_cmd_desc(&desc,
1053 					  i40e_aqc_opc_mac_address_write);
1054 	cmd_data->command_flags = CPU_TO_LE16(flags);
1055 	cmd_data->mac_sah = CPU_TO_LE16((u16)mac_addr[0] << 8 | mac_addr[1]);
1056 	cmd_data->mac_sal = CPU_TO_LE32(((u32)mac_addr[2] << 24) |
1057 					((u32)mac_addr[3] << 16) |
1058 					((u32)mac_addr[4] << 8) |
1059 					mac_addr[5]);
1060 
1061 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1062 
1063 	return status;
1064 }
1065 
1066 /**
1067  * i40e_get_mac_addr - get MAC address
1068  * @hw: pointer to the HW structure
1069  * @mac_addr: pointer to MAC address
1070  *
1071  * Reads the adapter's MAC address from register
1072  **/
1073 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1074 {
1075 	struct i40e_aqc_mac_address_read_data addrs;
1076 	enum i40e_status_code status;
1077 	u16 flags = 0;
1078 
1079 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1080 
1081 	if (flags & I40E_AQC_LAN_ADDR_VALID)
1082 		i40e_memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac),
1083 			I40E_NONDMA_TO_NONDMA);
1084 
1085 	return status;
1086 }
1087 
1088 /**
1089  * i40e_get_port_mac_addr - get Port MAC address
1090  * @hw: pointer to the HW structure
1091  * @mac_addr: pointer to Port MAC address
1092  *
1093  * Reads the adapter's Port MAC address
1094  **/
1095 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1096 {
1097 	struct i40e_aqc_mac_address_read_data addrs;
1098 	enum i40e_status_code status;
1099 	u16 flags = 0;
1100 
1101 	status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1102 	if (status)
1103 		return status;
1104 
1105 	if (flags & I40E_AQC_PORT_ADDR_VALID)
1106 		i40e_memcpy(mac_addr, &addrs.port_mac, sizeof(addrs.port_mac),
1107 			I40E_NONDMA_TO_NONDMA);
1108 	else
1109 		status = I40E_ERR_INVALID_MAC_ADDR;
1110 
1111 	return status;
1112 }
1113 
1114 /**
1115  * i40e_pre_tx_queue_cfg - pre tx queue configure
1116  * @hw: pointer to the HW structure
1117  * @queue: target pf queue index
1118  * @enable: state change request
1119  *
1120  * Handles hw requirement to indicate intention to enable
1121  * or disable target queue.
1122  **/
1123 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1124 {
1125 	u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1126 	u32 reg_block = 0;
1127 	u32 reg_val;
1128 
1129 	if (abs_queue_idx >= 128) {
1130 		reg_block = abs_queue_idx / 128;
1131 		abs_queue_idx %= 128;
1132 	}
1133 
1134 	reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1135 	reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1136 	reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1137 
1138 	if (enable)
1139 		reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1140 	else
1141 		reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1142 
1143 	wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1144 }
1145 
1146 /**
1147  *  i40e_read_pba_string - Reads part number string from EEPROM
1148  *  @hw: pointer to hardware structure
1149  *  @pba_num: stores the part number string from the EEPROM
1150  *  @pba_num_size: part number string buffer length
1151  *
1152  *  Reads the part number string from the EEPROM.
1153  **/
1154 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1155 					    u32 pba_num_size)
1156 {
1157 	enum i40e_status_code status = I40E_SUCCESS;
1158 	u16 pba_word = 0;
1159 	u16 pba_size = 0;
1160 	u16 pba_ptr = 0;
1161 	u16 i = 0;
1162 
1163 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1164 	if ((status != I40E_SUCCESS) || (pba_word != 0xFAFA)) {
1165 		DEBUGOUT("Failed to read PBA flags or flag is invalid.\n");
1166 		return status;
1167 	}
1168 
1169 	status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1170 	if (status != I40E_SUCCESS) {
1171 		DEBUGOUT("Failed to read PBA Block pointer.\n");
1172 		return status;
1173 	}
1174 
1175 	status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1176 	if (status != I40E_SUCCESS) {
1177 		DEBUGOUT("Failed to read PBA Block size.\n");
1178 		return status;
1179 	}
1180 
1181 	/* Subtract one to get PBA word count (PBA Size word is included in
1182 	 * total size)
1183 	 */
1184 	pba_size--;
1185 	if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1186 		DEBUGOUT("Buffer to small for PBA data.\n");
1187 		return I40E_ERR_PARAM;
1188 	}
1189 
1190 	for (i = 0; i < pba_size; i++) {
1191 		status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1192 		if (status != I40E_SUCCESS) {
1193 			DEBUGOUT1("Failed to read PBA Block word %d.\n", i);
1194 			return status;
1195 		}
1196 
1197 		pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1198 		pba_num[(i * 2) + 1] = pba_word & 0xFF;
1199 	}
1200 	pba_num[(pba_size * 2)] = '\0';
1201 
1202 	return status;
1203 }
1204 
1205 /**
1206  * i40e_get_media_type - Gets media type
1207  * @hw: pointer to the hardware structure
1208  **/
1209 static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1210 {
1211 	enum i40e_media_type media;
1212 
1213 	switch (hw->phy.link_info.phy_type) {
1214 	case I40E_PHY_TYPE_10GBASE_SR:
1215 	case I40E_PHY_TYPE_10GBASE_LR:
1216 	case I40E_PHY_TYPE_1000BASE_SX:
1217 	case I40E_PHY_TYPE_1000BASE_LX:
1218 	case I40E_PHY_TYPE_40GBASE_SR4:
1219 	case I40E_PHY_TYPE_40GBASE_LR4:
1220 	case I40E_PHY_TYPE_25GBASE_LR:
1221 	case I40E_PHY_TYPE_25GBASE_SR:
1222 		media = I40E_MEDIA_TYPE_FIBER;
1223 		break;
1224 	case I40E_PHY_TYPE_100BASE_TX:
1225 	case I40E_PHY_TYPE_1000BASE_T:
1226 	case I40E_PHY_TYPE_10GBASE_T:
1227 		media = I40E_MEDIA_TYPE_BASET;
1228 		break;
1229 	case I40E_PHY_TYPE_10GBASE_CR1_CU:
1230 	case I40E_PHY_TYPE_40GBASE_CR4_CU:
1231 	case I40E_PHY_TYPE_10GBASE_CR1:
1232 	case I40E_PHY_TYPE_40GBASE_CR4:
1233 	case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1234 	case I40E_PHY_TYPE_40GBASE_AOC:
1235 	case I40E_PHY_TYPE_10GBASE_AOC:
1236 	case I40E_PHY_TYPE_25GBASE_CR:
1237 	case I40E_PHY_TYPE_25GBASE_AOC:
1238 	case I40E_PHY_TYPE_25GBASE_ACC:
1239 		media = I40E_MEDIA_TYPE_DA;
1240 		break;
1241 	case I40E_PHY_TYPE_1000BASE_KX:
1242 	case I40E_PHY_TYPE_10GBASE_KX4:
1243 	case I40E_PHY_TYPE_10GBASE_KR:
1244 	case I40E_PHY_TYPE_40GBASE_KR4:
1245 	case I40E_PHY_TYPE_20GBASE_KR2:
1246 	case I40E_PHY_TYPE_25GBASE_KR:
1247 		media = I40E_MEDIA_TYPE_BACKPLANE;
1248 		break;
1249 	case I40E_PHY_TYPE_SGMII:
1250 	case I40E_PHY_TYPE_XAUI:
1251 	case I40E_PHY_TYPE_XFI:
1252 	case I40E_PHY_TYPE_XLAUI:
1253 	case I40E_PHY_TYPE_XLPPI:
1254 	default:
1255 		media = I40E_MEDIA_TYPE_UNKNOWN;
1256 		break;
1257 	}
1258 
1259 	return media;
1260 }
1261 
1262 #define I40E_PF_RESET_WAIT_COUNT	200
1263 /**
1264  * i40e_pf_reset - Reset the PF
1265  * @hw: pointer to the hardware structure
1266  *
1267  * Assuming someone else has triggered a global reset,
1268  * assure the global reset is complete and then reset the PF
1269  **/
1270 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw)
1271 {
1272 	u32 cnt = 0;
1273 	u32 cnt1 = 0;
1274 	u32 reg = 0;
1275 	u32 grst_del;
1276 
1277 	/* Poll for Global Reset steady state in case of recent GRST.
1278 	 * The grst delay value is in 100ms units, and we'll wait a
1279 	 * couple counts longer to be sure we don't just miss the end.
1280 	 */
1281 	grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1282 			I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1283 			I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1284 
1285 	grst_del = grst_del * 20;
1286 
1287 	for (cnt = 0; cnt < grst_del; cnt++) {
1288 		reg = rd32(hw, I40E_GLGEN_RSTAT);
1289 		if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1290 			break;
1291 		i40e_msec_delay(100);
1292 	}
1293 	if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1294 		DEBUGOUT("Global reset polling failed to complete.\n");
1295 		return I40E_ERR_RESET_FAILED;
1296 	}
1297 
1298 	/* Now Wait for the FW to be ready */
1299 	for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1300 		reg = rd32(hw, I40E_GLNVM_ULD);
1301 		reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1302 			I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1303 		if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1304 			    I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1305 			DEBUGOUT1("Core and Global modules ready %d\n", cnt1);
1306 			break;
1307 		}
1308 		i40e_msec_delay(10);
1309 	}
1310 	if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1311 		     I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1312 		DEBUGOUT("wait for FW Reset complete timedout\n");
1313 		DEBUGOUT1("I40E_GLNVM_ULD = 0x%x\n", reg);
1314 		return I40E_ERR_RESET_FAILED;
1315 	}
1316 
1317 	/* If there was a Global Reset in progress when we got here,
1318 	 * we don't need to do the PF Reset
1319 	 */
1320 	if (!cnt) {
1321 		u32 reg2 = 0;
1322 
1323 		reg = rd32(hw, I40E_PFGEN_CTRL);
1324 		wr32(hw, I40E_PFGEN_CTRL,
1325 		     (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1326 		for (cnt = 0; cnt < I40E_PF_RESET_WAIT_COUNT; cnt++) {
1327 			reg = rd32(hw, I40E_PFGEN_CTRL);
1328 			if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1329 				break;
1330 			reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1331 			if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1332 				DEBUGOUT("Core reset upcoming. Skipping PF reset request.\n");
1333 				DEBUGOUT1("I40E_GLGEN_RSTAT = 0x%x\n", reg2);
1334 				return I40E_ERR_NOT_READY;
1335 			}
1336 			i40e_msec_delay(1);
1337 		}
1338 		if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1339 			DEBUGOUT("PF reset polling failed to complete.\n");
1340 			return I40E_ERR_RESET_FAILED;
1341 		}
1342 	}
1343 
1344 	i40e_clear_pxe_mode(hw);
1345 
1346 
1347 	return I40E_SUCCESS;
1348 }
1349 
1350 /**
1351  * i40e_clear_hw - clear out any left over hw state
1352  * @hw: pointer to the hw struct
1353  *
1354  * Clear queues and interrupts, typically called at init time,
1355  * but after the capabilities have been found so we know how many
1356  * queues and msix vectors have been allocated.
1357  **/
1358 void i40e_clear_hw(struct i40e_hw *hw)
1359 {
1360 	u32 num_queues, base_queue;
1361 	u32 num_pf_int;
1362 	u32 num_vf_int;
1363 	u32 num_vfs;
1364 	u32 i, j;
1365 	u32 val;
1366 	u32 eol = 0x7ff;
1367 
1368 	/* get number of interrupts, queues, and vfs */
1369 	val = rd32(hw, I40E_GLPCI_CNF2);
1370 	num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1371 			I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1372 	num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1373 			I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1374 
1375 	val = rd32(hw, I40E_PFLAN_QALLOC);
1376 	base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1377 			I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1378 	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1379 			I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1380 	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1381 		num_queues = (j - base_queue) + 1;
1382 	else
1383 		num_queues = 0;
1384 
1385 	val = rd32(hw, I40E_PF_VT_PFALLOC);
1386 	i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1387 			I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1388 	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1389 			I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1390 	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1391 		num_vfs = (j - i) + 1;
1392 	else
1393 		num_vfs = 0;
1394 
1395 	/* stop all the interrupts */
1396 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1397 	val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1398 	for (i = 0; i < num_pf_int - 2; i++)
1399 		wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1400 
1401 	/* Set the FIRSTQ_INDX field to 0x7FF in PFINT_LNKLSTx */
1402 	val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1403 	wr32(hw, I40E_PFINT_LNKLST0, val);
1404 	for (i = 0; i < num_pf_int - 2; i++)
1405 		wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1406 	val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1407 	for (i = 0; i < num_vfs; i++)
1408 		wr32(hw, I40E_VPINT_LNKLST0(i), val);
1409 	for (i = 0; i < num_vf_int - 2; i++)
1410 		wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1411 
1412 	/* warn the HW of the coming Tx disables */
1413 	for (i = 0; i < num_queues; i++) {
1414 		u32 abs_queue_idx = base_queue + i;
1415 		u32 reg_block = 0;
1416 
1417 		if (abs_queue_idx >= 128) {
1418 			reg_block = abs_queue_idx / 128;
1419 			abs_queue_idx %= 128;
1420 		}
1421 
1422 		val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1423 		val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1424 		val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1425 		val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1426 
1427 		wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1428 	}
1429 	i40e_usec_delay(400);
1430 
1431 	/* stop all the queues */
1432 	for (i = 0; i < num_queues; i++) {
1433 		wr32(hw, I40E_QINT_TQCTL(i), 0);
1434 		wr32(hw, I40E_QTX_ENA(i), 0);
1435 		wr32(hw, I40E_QINT_RQCTL(i), 0);
1436 		wr32(hw, I40E_QRX_ENA(i), 0);
1437 	}
1438 
1439 	/* short wait for all queue disables to settle */
1440 	i40e_usec_delay(50);
1441 }
1442 
1443 /**
1444  * i40e_clear_pxe_mode - clear pxe operations mode
1445  * @hw: pointer to the hw struct
1446  *
1447  * Make sure all PXE mode settings are cleared, including things
1448  * like descriptor fetch/write-back mode.
1449  **/
1450 void i40e_clear_pxe_mode(struct i40e_hw *hw)
1451 {
1452 	if (i40e_check_asq_alive(hw))
1453 		i40e_aq_clear_pxe_mode(hw, NULL);
1454 }
1455 
1456 /**
1457  * i40e_led_is_mine - helper to find matching led
1458  * @hw: pointer to the hw struct
1459  * @idx: index into GPIO registers
1460  *
1461  * returns: 0 if no match, otherwise the value of the GPIO_CTL register
1462  */
1463 static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1464 {
1465 	u32 gpio_val = 0;
1466 	u32 port;
1467 
1468 	if (!hw->func_caps.led[idx])
1469 		return 0;
1470 
1471 	gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1472 	port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1473 		I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1474 
1475 	/* if PRT_NUM_NA is 1 then this LED is not port specific, OR
1476 	 * if it is not our port then ignore
1477 	 */
1478 	if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1479 	    (port != hw->port))
1480 		return 0;
1481 
1482 	return gpio_val;
1483 }
1484 
1485 #define I40E_COMBINED_ACTIVITY 0xA
1486 #define I40E_FILTER_ACTIVITY 0xE
1487 #define I40E_LINK_ACTIVITY 0xC
1488 #define I40E_MAC_ACTIVITY 0xD
1489 #define I40E_LED0 22
1490 
1491 /**
1492  * i40e_led_get - return current on/off mode
1493  * @hw: pointer to the hw struct
1494  *
1495  * The value returned is the 'mode' field as defined in the
1496  * GPIO register definitions: 0x0 = off, 0xf = on, and other
1497  * values are variations of possible behaviors relating to
1498  * blink, link, and wire.
1499  **/
1500 u32 i40e_led_get(struct i40e_hw *hw)
1501 {
1502 	u32 current_mode = 0;
1503 	u32 mode = 0;
1504 	int i;
1505 
1506 	/* as per the documentation GPIO 22-29 are the LED
1507 	 * GPIO pins named LED0..LED7
1508 	 */
1509 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1510 		u32 gpio_val = i40e_led_is_mine(hw, i);
1511 
1512 		if (!gpio_val)
1513 			continue;
1514 
1515 		/* ignore gpio LED src mode entries related to the activity
1516 		 *  LEDs
1517 		 */
1518 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1519 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1520 		switch (current_mode) {
1521 		case I40E_COMBINED_ACTIVITY:
1522 		case I40E_FILTER_ACTIVITY:
1523 		case I40E_MAC_ACTIVITY:
1524 		case I40E_LINK_ACTIVITY:
1525 			continue;
1526 		default:
1527 			break;
1528 		}
1529 
1530 		mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1531 			I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1532 		break;
1533 	}
1534 
1535 	return mode;
1536 }
1537 
1538 /**
1539  * i40e_led_set - set new on/off mode
1540  * @hw: pointer to the hw struct
1541  * @mode: 0=off, 0xf=on (else see manual for mode details)
1542  * @blink: TRUE if the LED should blink when on, FALSE if steady
1543  *
1544  * if this function is used to turn on the blink it should
1545  * be used to disable the blink when restoring the original state.
1546  **/
1547 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1548 {
1549 	u32 current_mode = 0;
1550 	int i;
1551 
1552 	if (mode & 0xfffffff0)
1553 		DEBUGOUT1("invalid mode passed in %X\n", mode);
1554 
1555 	/* as per the documentation GPIO 22-29 are the LED
1556 	 * GPIO pins named LED0..LED7
1557 	 */
1558 	for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1559 		u32 gpio_val = i40e_led_is_mine(hw, i);
1560 
1561 		if (!gpio_val)
1562 			continue;
1563 
1564 		/* ignore gpio LED src mode entries related to the activity
1565 		 * LEDs
1566 		 */
1567 		current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1568 				>> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1569 		switch (current_mode) {
1570 		case I40E_COMBINED_ACTIVITY:
1571 		case I40E_FILTER_ACTIVITY:
1572 		case I40E_MAC_ACTIVITY:
1573 		case I40E_LINK_ACTIVITY:
1574 			continue;
1575 		default:
1576 			break;
1577 		}
1578 
1579 		gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1580 		/* this & is a bit of paranoia, but serves as a range check */
1581 		gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1582 			     I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1583 
1584 		if (blink)
1585 			gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1586 		else
1587 			gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1588 
1589 		wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1590 		break;
1591 	}
1592 }
1593 
1594 /* Admin command wrappers */
1595 
1596 /**
1597  * i40e_aq_get_phy_capabilities
1598  * @hw: pointer to the hw struct
1599  * @abilities: structure for PHY capabilities to be filled
1600  * @qualified_modules: report Qualified Modules
1601  * @report_init: report init capabilities (active are default)
1602  * @cmd_details: pointer to command details structure or NULL
1603  *
1604  * Returns the various PHY abilities supported on the Port.
1605  **/
1606 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1607 			bool qualified_modules, bool report_init,
1608 			struct i40e_aq_get_phy_abilities_resp *abilities,
1609 			struct i40e_asq_cmd_details *cmd_details)
1610 {
1611 	struct i40e_aq_desc desc;
1612 	enum i40e_status_code status;
1613 	u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1614 	u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1615 
1616 	if (!abilities)
1617 		return I40E_ERR_PARAM;
1618 
1619 	do {
1620 		i40e_fill_default_direct_cmd_desc(&desc,
1621 					       i40e_aqc_opc_get_phy_abilities);
1622 
1623 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
1624 		if (abilities_size > I40E_AQ_LARGE_BUF)
1625 			desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
1626 
1627 		if (qualified_modules)
1628 			desc.params.external.param0 |=
1629 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1630 
1631 		if (report_init)
1632 			desc.params.external.param0 |=
1633 			CPU_TO_LE32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1634 
1635 		status = i40e_asq_send_command(hw, &desc, abilities,
1636 					       abilities_size, cmd_details);
1637 
1638 		if (status != I40E_SUCCESS)
1639 			break;
1640 
1641 		if (hw->aq.asq_last_status == I40E_AQ_RC_EIO) {
1642 			status = I40E_ERR_UNKNOWN_PHY;
1643 			break;
1644 		} else if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) {
1645 			i40e_msec_delay(1);
1646 			total_delay++;
1647 			status = I40E_ERR_TIMEOUT;
1648 		}
1649 	} while ((hw->aq.asq_last_status != I40E_AQ_RC_OK) &&
1650 		 (total_delay < max_delay));
1651 
1652 	if (status != I40E_SUCCESS)
1653 		return status;
1654 
1655 	if (report_init) {
1656 		if (hw->mac.type ==  I40E_MAC_XL710 &&
1657 		    hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1658 		    hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1659 			status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
1660 		} else {
1661 			hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1662 			hw->phy.phy_types |=
1663 					((u64)abilities->phy_type_ext << 32);
1664 		}
1665 	}
1666 
1667 	return status;
1668 }
1669 
1670 /**
1671  * i40e_aq_set_phy_config
1672  * @hw: pointer to the hw struct
1673  * @config: structure with PHY configuration to be set
1674  * @cmd_details: pointer to command details structure or NULL
1675  *
1676  * Set the various PHY configuration parameters
1677  * supported on the Port.One or more of the Set PHY config parameters may be
1678  * ignored in an MFP mode as the PF may not have the privilege to set some
1679  * of the PHY Config parameters. This status will be indicated by the
1680  * command response.
1681  **/
1682 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1683 				struct i40e_aq_set_phy_config *config,
1684 				struct i40e_asq_cmd_details *cmd_details)
1685 {
1686 	struct i40e_aq_desc desc;
1687 	struct i40e_aq_set_phy_config *cmd =
1688 		(struct i40e_aq_set_phy_config *)&desc.params.raw;
1689 	enum i40e_status_code status;
1690 
1691 	if (!config)
1692 		return I40E_ERR_PARAM;
1693 
1694 	i40e_fill_default_direct_cmd_desc(&desc,
1695 					  i40e_aqc_opc_set_phy_config);
1696 
1697 	*cmd = *config;
1698 
1699 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1700 
1701 	return status;
1702 }
1703 
1704 /**
1705  * i40e_set_fc
1706  * @hw: pointer to the hw struct
1707  * @aq_failures: buffer to return AdminQ failure information
1708  * @atomic_restart: whether to enable atomic link restart
1709  *
1710  * Set the requested flow control mode using set_phy_config.
1711  **/
1712 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1713 				  bool atomic_restart)
1714 {
1715 	enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1716 	struct i40e_aq_get_phy_abilities_resp abilities;
1717 	struct i40e_aq_set_phy_config config;
1718 	enum i40e_status_code status;
1719 	u8 pause_mask = 0x0;
1720 
1721 	*aq_failures = 0x0;
1722 
1723 	switch (fc_mode) {
1724 	case I40E_FC_FULL:
1725 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1726 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1727 		break;
1728 	case I40E_FC_RX_PAUSE:
1729 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1730 		break;
1731 	case I40E_FC_TX_PAUSE:
1732 		pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1733 		break;
1734 	default:
1735 		break;
1736 	}
1737 
1738 	/* Get the current phy config */
1739 	status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
1740 					      NULL);
1741 	if (status) {
1742 		*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1743 		return status;
1744 	}
1745 
1746 	memset(&config, 0, sizeof(config));
1747 	/* clear the old pause settings */
1748 	config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1749 			   ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1750 	/* set the new abilities */
1751 	config.abilities |= pause_mask;
1752 	/* If the abilities have changed, then set the new config */
1753 	if (config.abilities != abilities.abilities) {
1754 		/* Auto restart link so settings take effect */
1755 		if (atomic_restart)
1756 			config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1757 		/* Copy over all the old settings */
1758 		config.phy_type = abilities.phy_type;
1759 		config.phy_type_ext = abilities.phy_type_ext;
1760 		config.link_speed = abilities.link_speed;
1761 		config.eee_capability = abilities.eee_capability;
1762 		config.eeer = abilities.eeer_val;
1763 		config.low_power_ctrl = abilities.d3_lpan;
1764 		config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1765 				    I40E_AQ_PHY_FEC_CONFIG_MASK;
1766 		status = i40e_aq_set_phy_config(hw, &config, NULL);
1767 
1768 		if (status)
1769 			*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1770 	}
1771 	/* Update the link info */
1772 	status = i40e_update_link_info(hw);
1773 	if (status) {
1774 		/* Wait a little bit (on 40G cards it sometimes takes a really
1775 		 * long time for link to come back from the atomic reset)
1776 		 * and try once more
1777 		 */
1778 		i40e_msec_delay(1000);
1779 		status = i40e_update_link_info(hw);
1780 	}
1781 	if (status)
1782 		*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1783 
1784 	return status;
1785 }
1786 
1787 /**
1788  * i40e_aq_set_mac_config
1789  * @hw: pointer to the hw struct
1790  * @max_frame_size: Maximum Frame Size to be supported by the port
1791  * @crc_en: Tell HW to append a CRC to outgoing frames
1792  * @pacing: Pacing configurations
1793  * @cmd_details: pointer to command details structure or NULL
1794  *
1795  * Configure MAC settings for frame size, jumbo frame support and the
1796  * addition of a CRC by the hardware.
1797  **/
1798 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
1799 				u16 max_frame_size,
1800 				bool crc_en, u16 pacing,
1801 				struct i40e_asq_cmd_details *cmd_details)
1802 {
1803 	struct i40e_aq_desc desc;
1804 	struct i40e_aq_set_mac_config *cmd =
1805 		(struct i40e_aq_set_mac_config *)&desc.params.raw;
1806 	enum i40e_status_code status;
1807 
1808 	if (max_frame_size == 0)
1809 		return I40E_ERR_PARAM;
1810 
1811 	i40e_fill_default_direct_cmd_desc(&desc,
1812 					  i40e_aqc_opc_set_mac_config);
1813 
1814 	cmd->max_frame_size = CPU_TO_LE16(max_frame_size);
1815 	cmd->params = ((u8)pacing & 0x0F) << 3;
1816 	if (crc_en)
1817 		cmd->params |= I40E_AQ_SET_MAC_CONFIG_CRC_EN;
1818 
1819 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1820 
1821 	return status;
1822 }
1823 
1824 /**
1825  * i40e_aq_clear_pxe_mode
1826  * @hw: pointer to the hw struct
1827  * @cmd_details: pointer to command details structure or NULL
1828  *
1829  * Tell the firmware that the driver is taking over from PXE
1830  **/
1831 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1832 			struct i40e_asq_cmd_details *cmd_details)
1833 {
1834 	enum i40e_status_code status;
1835 	struct i40e_aq_desc desc;
1836 	struct i40e_aqc_clear_pxe *cmd =
1837 		(struct i40e_aqc_clear_pxe *)&desc.params.raw;
1838 
1839 	i40e_fill_default_direct_cmd_desc(&desc,
1840 					  i40e_aqc_opc_clear_pxe_mode);
1841 
1842 	cmd->rx_cnt = 0x2;
1843 
1844 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1845 
1846 	wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1847 
1848 	return status;
1849 }
1850 
1851 /**
1852  * i40e_aq_set_link_restart_an
1853  * @hw: pointer to the hw struct
1854  * @enable_link: if TRUE: enable link, if FALSE: disable link
1855  * @cmd_details: pointer to command details structure or NULL
1856  *
1857  * Sets up the link and restarts the Auto-Negotiation over the link.
1858  **/
1859 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1860 		bool enable_link, struct i40e_asq_cmd_details *cmd_details)
1861 {
1862 	struct i40e_aq_desc desc;
1863 	struct i40e_aqc_set_link_restart_an *cmd =
1864 		(struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1865 	enum i40e_status_code status;
1866 
1867 	i40e_fill_default_direct_cmd_desc(&desc,
1868 					  i40e_aqc_opc_set_link_restart_an);
1869 
1870 	cmd->command = I40E_AQ_PHY_RESTART_AN;
1871 	if (enable_link)
1872 		cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1873 	else
1874 		cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1875 
1876 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1877 
1878 	return status;
1879 }
1880 
1881 /**
1882  * i40e_aq_get_link_info
1883  * @hw: pointer to the hw struct
1884  * @enable_lse: enable/disable LinkStatusEvent reporting
1885  * @link: pointer to link status structure - optional
1886  * @cmd_details: pointer to command details structure or NULL
1887  *
1888  * Returns the link status of the adapter.
1889  **/
1890 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
1891 				bool enable_lse, struct i40e_link_status *link,
1892 				struct i40e_asq_cmd_details *cmd_details)
1893 {
1894 	struct i40e_aq_desc desc;
1895 	struct i40e_aqc_get_link_status *resp =
1896 		(struct i40e_aqc_get_link_status *)&desc.params.raw;
1897 	struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1898 	enum i40e_status_code status;
1899 	bool tx_pause, rx_pause;
1900 	u16 command_flags;
1901 
1902 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1903 
1904 	if (enable_lse)
1905 		command_flags = I40E_AQ_LSE_ENABLE;
1906 	else
1907 		command_flags = I40E_AQ_LSE_DISABLE;
1908 	resp->command_flags = CPU_TO_LE16(command_flags);
1909 
1910 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1911 
1912 	if (status != I40E_SUCCESS)
1913 		goto aq_get_link_info_exit;
1914 
1915 	/* save off old link status information */
1916 	i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
1917 		    sizeof(*hw_link_info), I40E_NONDMA_TO_NONDMA);
1918 
1919 	/* update link status */
1920 	hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1921 	hw->phy.media_type = i40e_get_media_type(hw);
1922 	hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1923 	hw_link_info->link_info = resp->link_info;
1924 	hw_link_info->an_info = resp->an_info;
1925 	hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1926 						 I40E_AQ_CONFIG_FEC_RS_ENA);
1927 	hw_link_info->ext_info = resp->ext_info;
1928 	hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1929 	hw_link_info->max_frame_size = LE16_TO_CPU(resp->max_frame_size);
1930 	hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1931 
1932 	/* update fc info */
1933 	tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1934 	rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1935 	if (tx_pause & rx_pause)
1936 		hw->fc.current_mode = I40E_FC_FULL;
1937 	else if (tx_pause)
1938 		hw->fc.current_mode = I40E_FC_TX_PAUSE;
1939 	else if (rx_pause)
1940 		hw->fc.current_mode = I40E_FC_RX_PAUSE;
1941 	else
1942 		hw->fc.current_mode = I40E_FC_NONE;
1943 
1944 	if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1945 		hw_link_info->crc_enable = TRUE;
1946 	else
1947 		hw_link_info->crc_enable = FALSE;
1948 
1949 	if (resp->command_flags & CPU_TO_LE16(I40E_AQ_LSE_IS_ENABLED))
1950 		hw_link_info->lse_enable = TRUE;
1951 	else
1952 		hw_link_info->lse_enable = FALSE;
1953 
1954 	if ((hw->mac.type == I40E_MAC_XL710) &&
1955 	    (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1956 	     hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1957 		hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1958 
1959 	if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1960 	    hw->aq.api_min_ver >= 7) {
1961 		__le32 tmp;
1962 
1963 		i40e_memcpy(&tmp, resp->link_type, sizeof(tmp),
1964 			    I40E_NONDMA_TO_NONDMA);
1965 		hw->phy.phy_types = LE32_TO_CPU(tmp);
1966 		hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1967 	}
1968 
1969 	/* save link status information */
1970 	if (link)
1971 		i40e_memcpy(link, hw_link_info, sizeof(*hw_link_info),
1972 			    I40E_NONDMA_TO_NONDMA);
1973 
1974 	/* flag cleared so helper functions don't call AQ again */
1975 	hw->phy.get_link_info = FALSE;
1976 
1977 aq_get_link_info_exit:
1978 	return status;
1979 }
1980 
1981 /**
1982  * i40e_aq_set_phy_int_mask
1983  * @hw: pointer to the hw struct
1984  * @mask: interrupt mask to be set
1985  * @cmd_details: pointer to command details structure or NULL
1986  *
1987  * Set link interrupt mask.
1988  **/
1989 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1990 				u16 mask,
1991 				struct i40e_asq_cmd_details *cmd_details)
1992 {
1993 	struct i40e_aq_desc desc;
1994 	struct i40e_aqc_set_phy_int_mask *cmd =
1995 		(struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1996 	enum i40e_status_code status;
1997 
1998 	i40e_fill_default_direct_cmd_desc(&desc,
1999 					  i40e_aqc_opc_set_phy_int_mask);
2000 
2001 	cmd->event_mask = CPU_TO_LE16(mask);
2002 
2003 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2004 
2005 	return status;
2006 }
2007 
2008 /**
2009  * i40e_aq_get_local_advt_reg
2010  * @hw: pointer to the hw struct
2011  * @advt_reg: local AN advertisement register value
2012  * @cmd_details: pointer to command details structure or NULL
2013  *
2014  * Get the Local AN advertisement register value.
2015  **/
2016 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
2017 				u64 *advt_reg,
2018 				struct i40e_asq_cmd_details *cmd_details)
2019 {
2020 	struct i40e_aq_desc desc;
2021 	struct i40e_aqc_an_advt_reg *resp =
2022 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2023 	enum i40e_status_code status;
2024 
2025 	i40e_fill_default_direct_cmd_desc(&desc,
2026 					  i40e_aqc_opc_get_local_advt_reg);
2027 
2028 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2029 
2030 	if (status != I40E_SUCCESS)
2031 		goto aq_get_local_advt_reg_exit;
2032 
2033 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2034 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2035 
2036 aq_get_local_advt_reg_exit:
2037 	return status;
2038 }
2039 
2040 /**
2041  * i40e_aq_set_local_advt_reg
2042  * @hw: pointer to the hw struct
2043  * @advt_reg: local AN advertisement register value
2044  * @cmd_details: pointer to command details structure or NULL
2045  *
2046  * Get the Local AN advertisement register value.
2047  **/
2048 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
2049 				u64 advt_reg,
2050 				struct i40e_asq_cmd_details *cmd_details)
2051 {
2052 	struct i40e_aq_desc desc;
2053 	struct i40e_aqc_an_advt_reg *cmd =
2054 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2055 	enum i40e_status_code status;
2056 
2057 	i40e_fill_default_direct_cmd_desc(&desc,
2058 					  i40e_aqc_opc_get_local_advt_reg);
2059 
2060 	cmd->local_an_reg0 = CPU_TO_LE32(I40E_LO_DWORD(advt_reg));
2061 	cmd->local_an_reg1 = CPU_TO_LE16(I40E_HI_DWORD(advt_reg));
2062 
2063 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2064 
2065 	return status;
2066 }
2067 
2068 /**
2069  * i40e_aq_get_partner_advt
2070  * @hw: pointer to the hw struct
2071  * @advt_reg: AN partner advertisement register value
2072  * @cmd_details: pointer to command details structure or NULL
2073  *
2074  * Get the link partner AN advertisement register value.
2075  **/
2076 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
2077 				u64 *advt_reg,
2078 				struct i40e_asq_cmd_details *cmd_details)
2079 {
2080 	struct i40e_aq_desc desc;
2081 	struct i40e_aqc_an_advt_reg *resp =
2082 		(struct i40e_aqc_an_advt_reg *)&desc.params.raw;
2083 	enum i40e_status_code status;
2084 
2085 	i40e_fill_default_direct_cmd_desc(&desc,
2086 					  i40e_aqc_opc_get_partner_advt);
2087 
2088 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2089 
2090 	if (status != I40E_SUCCESS)
2091 		goto aq_get_partner_advt_exit;
2092 
2093 	*advt_reg = (u64)(LE16_TO_CPU(resp->local_an_reg1)) << 32;
2094 	*advt_reg |= LE32_TO_CPU(resp->local_an_reg0);
2095 
2096 aq_get_partner_advt_exit:
2097 	return status;
2098 }
2099 
2100 /**
2101  * i40e_aq_set_lb_modes
2102  * @hw: pointer to the hw struct
2103  * @lb_modes: loopback mode to be set
2104  * @cmd_details: pointer to command details structure or NULL
2105  *
2106  * Sets loopback modes.
2107  **/
2108 enum i40e_status_code
2109 i40e_aq_set_lb_modes(struct i40e_hw *hw, u8 lb_level, u8 lb_type, u8 speed,
2110 		     struct i40e_asq_cmd_details *cmd_details)
2111 {
2112 	struct i40e_aq_desc desc;
2113 	struct i40e_aqc_set_lb_mode *cmd =
2114 		(struct i40e_aqc_set_lb_mode *)&desc.params.raw;
2115 	enum i40e_status_code status;
2116 
2117 	i40e_fill_default_direct_cmd_desc(&desc,
2118 					  i40e_aqc_opc_set_lb_modes);
2119 
2120 	cmd->lb_level = lb_level;
2121 	cmd->lb_type = lb_type;
2122 	cmd->speed = speed;
2123 	if (speed)
2124 		cmd->force_speed = 1;
2125 
2126 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2127 
2128 	return status;
2129 }
2130 
2131 /**
2132  * i40e_aq_set_phy_debug
2133  * @hw: pointer to the hw struct
2134  * @cmd_flags: debug command flags
2135  * @cmd_details: pointer to command details structure or NULL
2136  *
2137  * Reset the external PHY.
2138  **/
2139 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
2140 				struct i40e_asq_cmd_details *cmd_details)
2141 {
2142 	struct i40e_aq_desc desc;
2143 	struct i40e_aqc_set_phy_debug *cmd =
2144 		(struct i40e_aqc_set_phy_debug *)&desc.params.raw;
2145 	enum i40e_status_code status;
2146 
2147 	i40e_fill_default_direct_cmd_desc(&desc,
2148 					  i40e_aqc_opc_set_phy_debug);
2149 
2150 	cmd->command_flags = cmd_flags;
2151 
2152 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2153 
2154 	return status;
2155 }
2156 
2157 /**
2158  * i40e_aq_add_vsi
2159  * @hw: pointer to the hw struct
2160  * @vsi_ctx: pointer to a vsi context struct
2161  * @cmd_details: pointer to command details structure or NULL
2162  *
2163  * Add a VSI context to the hardware.
2164 **/
2165 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
2166 				struct i40e_vsi_context *vsi_ctx,
2167 				struct i40e_asq_cmd_details *cmd_details)
2168 {
2169 	struct i40e_aq_desc desc;
2170 	struct i40e_aqc_add_get_update_vsi *cmd =
2171 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2172 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2173 		(struct i40e_aqc_add_get_update_vsi_completion *)
2174 		&desc.params.raw;
2175 	enum i40e_status_code status;
2176 
2177 	i40e_fill_default_direct_cmd_desc(&desc,
2178 					  i40e_aqc_opc_add_vsi);
2179 
2180 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->uplink_seid);
2181 	cmd->connection_type = vsi_ctx->connection_type;
2182 	cmd->vf_id = vsi_ctx->vf_num;
2183 	cmd->vsi_flags = CPU_TO_LE16(vsi_ctx->flags);
2184 
2185 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2186 
2187 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2188 				    sizeof(vsi_ctx->info), cmd_details);
2189 
2190 	if (status != I40E_SUCCESS)
2191 		goto aq_add_vsi_exit;
2192 
2193 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2194 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2195 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2196 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2197 
2198 aq_add_vsi_exit:
2199 	return status;
2200 }
2201 
2202 /**
2203  * i40e_aq_set_default_vsi
2204  * @hw: pointer to the hw struct
2205  * @seid: vsi number
2206  * @cmd_details: pointer to command details structure or NULL
2207  **/
2208 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw,
2209 				u16 seid,
2210 				struct i40e_asq_cmd_details *cmd_details)
2211 {
2212 	struct i40e_aq_desc desc;
2213 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2214 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2215 		&desc.params.raw;
2216 	enum i40e_status_code status;
2217 
2218 	i40e_fill_default_direct_cmd_desc(&desc,
2219 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2220 
2221 	cmd->promiscuous_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2222 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2223 	cmd->seid = CPU_TO_LE16(seid);
2224 
2225 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2226 
2227 	return status;
2228 }
2229 
2230 /**
2231  * i40e_aq_clear_default_vsi
2232  * @hw: pointer to the hw struct
2233  * @seid: vsi number
2234  * @cmd_details: pointer to command details structure or NULL
2235  **/
2236 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw,
2237 				u16 seid,
2238 				struct i40e_asq_cmd_details *cmd_details)
2239 {
2240 	struct i40e_aq_desc desc;
2241 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2242 		(struct i40e_aqc_set_vsi_promiscuous_modes *)
2243 		&desc.params.raw;
2244 	enum i40e_status_code status;
2245 
2246 	i40e_fill_default_direct_cmd_desc(&desc,
2247 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2248 
2249 	cmd->promiscuous_flags = CPU_TO_LE16(0);
2250 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_DEFAULT);
2251 	cmd->seid = CPU_TO_LE16(seid);
2252 
2253 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2254 
2255 	return status;
2256 }
2257 
2258 /**
2259  * i40e_aq_set_vsi_unicast_promiscuous
2260  * @hw: pointer to the hw struct
2261  * @seid: vsi number
2262  * @set: set unicast promiscuous enable/disable
2263  * @cmd_details: pointer to command details structure or NULL
2264  * @rx_only_promisc: flag to decide if egress traffic gets mirrored in promisc
2265  **/
2266 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
2267 				u16 seid, bool set,
2268 				struct i40e_asq_cmd_details *cmd_details,
2269 				bool rx_only_promisc)
2270 {
2271 	struct i40e_aq_desc desc;
2272 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2273 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2274 	enum i40e_status_code status;
2275 	u16 flags = 0;
2276 
2277 	i40e_fill_default_direct_cmd_desc(&desc,
2278 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2279 
2280 	if (set) {
2281 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2282 		if (rx_only_promisc &&
2283 		    (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
2284 		     (hw->aq.api_maj_ver > 1)))
2285 			flags |= I40E_AQC_SET_VSI_PROMISC_TX;
2286 	}
2287 
2288 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2289 
2290 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2291 	if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
2292 	     (hw->aq.api_maj_ver > 1))
2293 		cmd->valid_flags |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_TX);
2294 
2295 	cmd->seid = CPU_TO_LE16(seid);
2296 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2297 
2298 	return status;
2299 }
2300 
2301 /**
2302  * i40e_aq_set_vsi_multicast_promiscuous
2303  * @hw: pointer to the hw struct
2304  * @seid: vsi number
2305  * @set: set multicast promiscuous enable/disable
2306  * @cmd_details: pointer to command details structure or NULL
2307  **/
2308 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2309 				u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2310 {
2311 	struct i40e_aq_desc desc;
2312 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2313 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2314 	enum i40e_status_code status;
2315 	u16 flags = 0;
2316 
2317 	i40e_fill_default_direct_cmd_desc(&desc,
2318 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2319 
2320 	if (set)
2321 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2322 
2323 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2324 
2325 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2326 
2327 	cmd->seid = CPU_TO_LE16(seid);
2328 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2329 
2330 	return status;
2331 }
2332 
2333 /**
2334  * i40e_aq_set_vsi_mc_promisc_on_vlan
2335  * @hw: pointer to the hw struct
2336  * @seid: vsi number
2337  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2338  * @vid: The VLAN tag filter - capture any multicast packet with this VLAN tag
2339  * @cmd_details: pointer to command details structure or NULL
2340  **/
2341 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2342 				u16 seid, bool enable, u16 vid,
2343 				struct i40e_asq_cmd_details *cmd_details)
2344 {
2345 	struct i40e_aq_desc desc;
2346 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2347 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2348 	enum i40e_status_code status;
2349 	u16 flags = 0;
2350 
2351 	i40e_fill_default_direct_cmd_desc(&desc,
2352 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2353 
2354 	if (enable)
2355 		flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2356 
2357 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2358 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2359 	cmd->seid = CPU_TO_LE16(seid);
2360 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2361 
2362 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2363 
2364 	return status;
2365 }
2366 
2367 /**
2368  * i40e_aq_set_vsi_uc_promisc_on_vlan
2369  * @hw: pointer to the hw struct
2370  * @seid: vsi number
2371  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2372  * @vid: The VLAN tag filter - capture any unicast packet with this VLAN tag
2373  * @cmd_details: pointer to command details structure or NULL
2374  **/
2375 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2376 				u16 seid, bool enable, u16 vid,
2377 				struct i40e_asq_cmd_details *cmd_details)
2378 {
2379 	struct i40e_aq_desc desc;
2380 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2381 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2382 	enum i40e_status_code status;
2383 	u16 flags = 0;
2384 
2385 	i40e_fill_default_direct_cmd_desc(&desc,
2386 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2387 
2388 	if (enable)
2389 		flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2390 
2391 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2392 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2393 	cmd->seid = CPU_TO_LE16(seid);
2394 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2395 
2396 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2397 
2398 	return status;
2399 }
2400 
2401 /**
2402  * i40e_aq_set_vsi_bc_promisc_on_vlan
2403  * @hw: pointer to the hw struct
2404  * @seid: vsi number
2405  * @enable: set broadcast promiscuous enable/disable for a given VLAN
2406  * @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2407  * @cmd_details: pointer to command details structure or NULL
2408  **/
2409 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2410 				u16 seid, bool enable, u16 vid,
2411 				struct i40e_asq_cmd_details *cmd_details)
2412 {
2413 	struct i40e_aq_desc desc;
2414 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2415 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2416 	enum i40e_status_code status;
2417 	u16 flags = 0;
2418 
2419 	i40e_fill_default_direct_cmd_desc(&desc,
2420 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2421 
2422 	if (enable)
2423 		flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2424 
2425 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2426 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2427 	cmd->seid = CPU_TO_LE16(seid);
2428 	cmd->vlan_tag = CPU_TO_LE16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2429 
2430 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2431 
2432 	return status;
2433 }
2434 
2435 /**
2436  * i40e_aq_set_vsi_broadcast
2437  * @hw: pointer to the hw struct
2438  * @seid: vsi number
2439  * @set_filter: TRUE to set filter, FALSE to clear filter
2440  * @cmd_details: pointer to command details structure or NULL
2441  *
2442  * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
2443  **/
2444 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2445 				u16 seid, bool set_filter,
2446 				struct i40e_asq_cmd_details *cmd_details)
2447 {
2448 	struct i40e_aq_desc desc;
2449 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2450 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2451 	enum i40e_status_code status;
2452 
2453 	i40e_fill_default_direct_cmd_desc(&desc,
2454 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2455 
2456 	if (set_filter)
2457 		cmd->promiscuous_flags
2458 			    |= CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2459 	else
2460 		cmd->promiscuous_flags
2461 			    &= CPU_TO_LE16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2462 
2463 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2464 	cmd->seid = CPU_TO_LE16(seid);
2465 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2466 
2467 	return status;
2468 }
2469 
2470 /**
2471  * i40e_aq_set_vsi_vlan_promisc - control the VLAN promiscuous setting
2472  * @hw: pointer to the hw struct
2473  * @seid: vsi number
2474  * @enable: set MAC L2 layer unicast promiscuous enable/disable for a given VLAN
2475  * @cmd_details: pointer to command details structure or NULL
2476  **/
2477 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2478 				u16 seid, bool enable,
2479 				struct i40e_asq_cmd_details *cmd_details)
2480 {
2481 	struct i40e_aq_desc desc;
2482 	struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2483 		(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2484 	enum i40e_status_code status;
2485 	u16 flags = 0;
2486 
2487 	i40e_fill_default_direct_cmd_desc(&desc,
2488 					i40e_aqc_opc_set_vsi_promiscuous_modes);
2489 	if (enable)
2490 		flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2491 
2492 	cmd->promiscuous_flags = CPU_TO_LE16(flags);
2493 	cmd->valid_flags = CPU_TO_LE16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2494 	cmd->seid = CPU_TO_LE16(seid);
2495 
2496 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2497 
2498 	return status;
2499 }
2500 
2501 /**
2502  * i40e_get_vsi_params - get VSI configuration info
2503  * @hw: pointer to the hw struct
2504  * @vsi_ctx: pointer to a vsi context struct
2505  * @cmd_details: pointer to command details structure or NULL
2506  **/
2507 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
2508 				struct i40e_vsi_context *vsi_ctx,
2509 				struct i40e_asq_cmd_details *cmd_details)
2510 {
2511 	struct i40e_aq_desc desc;
2512 	struct i40e_aqc_add_get_update_vsi *cmd =
2513 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2514 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2515 		(struct i40e_aqc_add_get_update_vsi_completion *)
2516 		&desc.params.raw;
2517 	enum i40e_status_code status;
2518 
2519 	i40e_fill_default_direct_cmd_desc(&desc,
2520 					  i40e_aqc_opc_get_vsi_parameters);
2521 
2522 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2523 
2524 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2525 
2526 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2527 				    sizeof(vsi_ctx->info), NULL);
2528 
2529 	if (status != I40E_SUCCESS)
2530 		goto aq_get_vsi_params_exit;
2531 
2532 	vsi_ctx->seid = LE16_TO_CPU(resp->seid);
2533 	vsi_ctx->vsi_number = LE16_TO_CPU(resp->vsi_number);
2534 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2535 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2536 
2537 aq_get_vsi_params_exit:
2538 	return status;
2539 }
2540 
2541 /**
2542  * i40e_aq_update_vsi_params
2543  * @hw: pointer to the hw struct
2544  * @vsi_ctx: pointer to a vsi context struct
2545  * @cmd_details: pointer to command details structure or NULL
2546  *
2547  * Update a VSI context.
2548  **/
2549 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
2550 				struct i40e_vsi_context *vsi_ctx,
2551 				struct i40e_asq_cmd_details *cmd_details)
2552 {
2553 	struct i40e_aq_desc desc;
2554 	struct i40e_aqc_add_get_update_vsi *cmd =
2555 		(struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2556 	struct i40e_aqc_add_get_update_vsi_completion *resp =
2557 		(struct i40e_aqc_add_get_update_vsi_completion *)
2558 		&desc.params.raw;
2559 	enum i40e_status_code status;
2560 
2561 	i40e_fill_default_direct_cmd_desc(&desc,
2562 					  i40e_aqc_opc_update_vsi_parameters);
2563 	cmd->uplink_seid = CPU_TO_LE16(vsi_ctx->seid);
2564 
2565 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2566 
2567 	status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2568 				    sizeof(vsi_ctx->info), cmd_details);
2569 
2570 	vsi_ctx->vsis_allocated = LE16_TO_CPU(resp->vsi_used);
2571 	vsi_ctx->vsis_unallocated = LE16_TO_CPU(resp->vsi_free);
2572 
2573 	return status;
2574 }
2575 
2576 /**
2577  * i40e_aq_get_switch_config
2578  * @hw: pointer to the hardware structure
2579  * @buf: pointer to the result buffer
2580  * @buf_size: length of input buffer
2581  * @start_seid: seid to start for the report, 0 == beginning
2582  * @cmd_details: pointer to command details structure or NULL
2583  *
2584  * Fill the buf with switch configuration returned from AdminQ command
2585  **/
2586 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
2587 				struct i40e_aqc_get_switch_config_resp *buf,
2588 				u16 buf_size, u16 *start_seid,
2589 				struct i40e_asq_cmd_details *cmd_details)
2590 {
2591 	struct i40e_aq_desc desc;
2592 	struct i40e_aqc_switch_seid *scfg =
2593 		(struct i40e_aqc_switch_seid *)&desc.params.raw;
2594 	enum i40e_status_code status;
2595 
2596 	i40e_fill_default_direct_cmd_desc(&desc,
2597 					  i40e_aqc_opc_get_switch_config);
2598 	desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_BUF);
2599 	if (buf_size > I40E_AQ_LARGE_BUF)
2600 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2601 	scfg->seid = CPU_TO_LE16(*start_seid);
2602 
2603 	status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2604 	*start_seid = LE16_TO_CPU(scfg->seid);
2605 
2606 	return status;
2607 }
2608 
2609 /**
2610  * i40e_aq_set_switch_config
2611  * @hw: pointer to the hardware structure
2612  * @flags: bit flag values to set
2613  * @mode: cloud filter mode
2614  * @valid_flags: which bit flags to set
2615  * @cmd_details: pointer to command details structure or NULL
2616  *
2617  * Set switch configuration bits
2618  **/
2619 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2620 				u16 flags, u16 valid_flags, u8 mode,
2621 				struct i40e_asq_cmd_details *cmd_details)
2622 {
2623 	struct i40e_aq_desc desc;
2624 	struct i40e_aqc_set_switch_config *scfg =
2625 		(struct i40e_aqc_set_switch_config *)&desc.params.raw;
2626 	enum i40e_status_code status;
2627 
2628 	i40e_fill_default_direct_cmd_desc(&desc,
2629 					  i40e_aqc_opc_set_switch_config);
2630 	scfg->flags = CPU_TO_LE16(flags);
2631 	scfg->valid_flags = CPU_TO_LE16(valid_flags);
2632 	scfg->mode = mode;
2633 	if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2634 		scfg->switch_tag = CPU_TO_LE16(hw->switch_tag);
2635 		scfg->first_tag = CPU_TO_LE16(hw->first_tag);
2636 		scfg->second_tag = CPU_TO_LE16(hw->second_tag);
2637 	}
2638 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2639 
2640 	return status;
2641 }
2642 
2643 /**
2644  * i40e_aq_get_firmware_version
2645  * @hw: pointer to the hw struct
2646  * @fw_major_version: firmware major version
2647  * @fw_minor_version: firmware minor version
2648  * @fw_build: firmware build number
2649  * @api_major_version: major queue version
2650  * @api_minor_version: minor queue version
2651  * @cmd_details: pointer to command details structure or NULL
2652  *
2653  * Get the firmware version from the admin queue commands
2654  **/
2655 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
2656 				u16 *fw_major_version, u16 *fw_minor_version,
2657 				u32 *fw_build,
2658 				u16 *api_major_version, u16 *api_minor_version,
2659 				struct i40e_asq_cmd_details *cmd_details)
2660 {
2661 	struct i40e_aq_desc desc;
2662 	struct i40e_aqc_get_version *resp =
2663 		(struct i40e_aqc_get_version *)&desc.params.raw;
2664 	enum i40e_status_code status;
2665 
2666 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2667 
2668 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2669 
2670 	if (status == I40E_SUCCESS) {
2671 		if (fw_major_version != NULL)
2672 			*fw_major_version = LE16_TO_CPU(resp->fw_major);
2673 		if (fw_minor_version != NULL)
2674 			*fw_minor_version = LE16_TO_CPU(resp->fw_minor);
2675 		if (fw_build != NULL)
2676 			*fw_build = LE32_TO_CPU(resp->fw_build);
2677 		if (api_major_version != NULL)
2678 			*api_major_version = LE16_TO_CPU(resp->api_major);
2679 		if (api_minor_version != NULL)
2680 			*api_minor_version = LE16_TO_CPU(resp->api_minor);
2681 
2682 		/* A workaround to fix the API version in SW */
2683 		if (api_major_version && api_minor_version &&
2684 		    fw_major_version && fw_minor_version &&
2685 		    ((*api_major_version == 1) && (*api_minor_version == 1)) &&
2686 		    (((*fw_major_version == 4) && (*fw_minor_version >= 2)) ||
2687 		     (*fw_major_version > 4)))
2688 			*api_minor_version = 2;
2689 	}
2690 
2691 	return status;
2692 }
2693 
2694 /**
2695  * i40e_aq_send_driver_version
2696  * @hw: pointer to the hw struct
2697  * @dv: driver's major, minor version
2698  * @cmd_details: pointer to command details structure or NULL
2699  *
2700  * Send the driver version to the firmware
2701  **/
2702 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
2703 				struct i40e_driver_version *dv,
2704 				struct i40e_asq_cmd_details *cmd_details)
2705 {
2706 	struct i40e_aq_desc desc;
2707 	struct i40e_aqc_driver_version *cmd =
2708 		(struct i40e_aqc_driver_version *)&desc.params.raw;
2709 	enum i40e_status_code status;
2710 	u16 len;
2711 
2712 	if (dv == NULL)
2713 		return I40E_ERR_PARAM;
2714 
2715 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2716 
2717 	desc.flags |= CPU_TO_LE16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2718 	cmd->driver_major_ver = dv->major_version;
2719 	cmd->driver_minor_ver = dv->minor_version;
2720 	cmd->driver_build_ver = dv->build_version;
2721 	cmd->driver_subbuild_ver = dv->subbuild_version;
2722 
2723 	len = 0;
2724 	while (len < sizeof(dv->driver_string) &&
2725 	       (dv->driver_string[len] < 0x80) &&
2726 	       dv->driver_string[len])
2727 		len++;
2728 	status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2729 				       len, cmd_details);
2730 
2731 	return status;
2732 }
2733 
2734 /**
2735  * i40e_get_link_status - get status of the HW network link
2736  * @hw: pointer to the hw struct
2737  * @link_up: pointer to bool (TRUE/FALSE = linkup/linkdown)
2738  *
2739  * Variable link_up TRUE if link is up, FALSE if link is down.
2740  * The variable link_up is invalid if returned value of status != I40E_SUCCESS
2741  *
2742  * Side effect: LinkStatusEvent reporting becomes enabled
2743  **/
2744 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2745 {
2746 	enum i40e_status_code status = I40E_SUCCESS;
2747 
2748 	if (hw->phy.get_link_info) {
2749 		status = i40e_update_link_info(hw);
2750 
2751 		if (status != I40E_SUCCESS)
2752 			i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2753 				   status);
2754 	}
2755 
2756 	*link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2757 
2758 	return status;
2759 }
2760 
2761 /**
2762  * i40e_updatelink_status - update status of the HW network link
2763  * @hw: pointer to the hw struct
2764  **/
2765 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw)
2766 {
2767 	struct i40e_aq_get_phy_abilities_resp abilities;
2768 	enum i40e_status_code status = I40E_SUCCESS;
2769 
2770 	status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2771 	if (status)
2772 		return status;
2773 
2774 	/* extra checking needed to ensure link info to user is timely */
2775 	if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2776 	    ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2777 	     !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2778 		status = i40e_aq_get_phy_capabilities(hw, FALSE, false,
2779 						      &abilities, NULL);
2780 		if (status)
2781 			return status;
2782 
2783 		hw->phy.link_info.req_fec_info =
2784 			abilities.fec_cfg_curr_mod_ext_info &
2785 			(I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS);
2786 
2787 		i40e_memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2788 			sizeof(hw->phy.link_info.module_type), I40E_NONDMA_TO_NONDMA);
2789 	}
2790 	return status;
2791 }
2792 
2793 
2794 /**
2795  * i40e_get_link_speed
2796  * @hw: pointer to the hw struct
2797  *
2798  * Returns the link speed of the adapter.
2799  **/
2800 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw)
2801 {
2802 	enum i40e_aq_link_speed speed = I40E_LINK_SPEED_UNKNOWN;
2803 	enum i40e_status_code status = I40E_SUCCESS;
2804 
2805 	if (hw->phy.get_link_info) {
2806 		status = i40e_aq_get_link_info(hw, TRUE, NULL, NULL);
2807 
2808 		if (status != I40E_SUCCESS)
2809 			goto i40e_link_speed_exit;
2810 	}
2811 
2812 	speed = hw->phy.link_info.link_speed;
2813 
2814 i40e_link_speed_exit:
2815 	return speed;
2816 }
2817 
2818 /**
2819  * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
2820  * @hw: pointer to the hw struct
2821  * @uplink_seid: the MAC or other gizmo SEID
2822  * @downlink_seid: the VSI SEID
2823  * @enabled_tc: bitmap of TCs to be enabled
2824  * @default_port: TRUE for default port VSI, FALSE for control port
2825  * @veb_seid: pointer to where to put the resulting VEB SEID
2826  * @enable_stats: TRUE to turn on VEB stats
2827  * @cmd_details: pointer to command details structure or NULL
2828  *
2829  * This asks the FW to add a VEB between the uplink and downlink
2830  * elements.  If the uplink SEID is 0, this will be a floating VEB.
2831  **/
2832 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2833 				u16 downlink_seid, u8 enabled_tc,
2834 				bool default_port, u16 *veb_seid,
2835 				bool enable_stats,
2836 				struct i40e_asq_cmd_details *cmd_details)
2837 {
2838 	struct i40e_aq_desc desc;
2839 	struct i40e_aqc_add_veb *cmd =
2840 		(struct i40e_aqc_add_veb *)&desc.params.raw;
2841 	struct i40e_aqc_add_veb_completion *resp =
2842 		(struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2843 	enum i40e_status_code status;
2844 	u16 veb_flags = 0;
2845 
2846 	/* SEIDs need to either both be set or both be 0 for floating VEB */
2847 	if (!!uplink_seid != !!downlink_seid)
2848 		return I40E_ERR_PARAM;
2849 
2850 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2851 
2852 	cmd->uplink_seid = CPU_TO_LE16(uplink_seid);
2853 	cmd->downlink_seid = CPU_TO_LE16(downlink_seid);
2854 	cmd->enable_tcs = enabled_tc;
2855 	if (!uplink_seid)
2856 		veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2857 	if (default_port)
2858 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2859 	else
2860 		veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2861 
2862 	/* reverse logic here: set the bitflag to disable the stats */
2863 	if (!enable_stats)
2864 		veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2865 
2866 	cmd->veb_flags = CPU_TO_LE16(veb_flags);
2867 
2868 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2869 
2870 	if (!status && veb_seid)
2871 		*veb_seid = LE16_TO_CPU(resp->veb_seid);
2872 
2873 	return status;
2874 }
2875 
2876 /**
2877  * i40e_aq_get_veb_parameters - Retrieve VEB parameters
2878  * @hw: pointer to the hw struct
2879  * @veb_seid: the SEID of the VEB to query
2880  * @switch_id: the uplink switch id
2881  * @floating: set to TRUE if the VEB is floating
2882  * @statistic_index: index of the stats counter block for this VEB
2883  * @vebs_used: number of VEB's used by function
2884  * @vebs_free: total VEB's not reserved by any function
2885  * @cmd_details: pointer to command details structure or NULL
2886  *
2887  * This retrieves the parameters for a particular VEB, specified by
2888  * uplink_seid, and returns them to the caller.
2889  **/
2890 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2891 				u16 veb_seid, u16 *switch_id,
2892 				bool *floating, u16 *statistic_index,
2893 				u16 *vebs_used, u16 *vebs_free,
2894 				struct i40e_asq_cmd_details *cmd_details)
2895 {
2896 	struct i40e_aq_desc desc;
2897 	struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2898 		(struct i40e_aqc_get_veb_parameters_completion *)
2899 		&desc.params.raw;
2900 	enum i40e_status_code status;
2901 
2902 	if (veb_seid == 0)
2903 		return I40E_ERR_PARAM;
2904 
2905 	i40e_fill_default_direct_cmd_desc(&desc,
2906 					  i40e_aqc_opc_get_veb_parameters);
2907 	cmd_resp->seid = CPU_TO_LE16(veb_seid);
2908 
2909 	status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2910 	if (status)
2911 		goto get_veb_exit;
2912 
2913 	if (switch_id)
2914 		*switch_id = LE16_TO_CPU(cmd_resp->switch_id);
2915 	if (statistic_index)
2916 		*statistic_index = LE16_TO_CPU(cmd_resp->statistic_index);
2917 	if (vebs_used)
2918 		*vebs_used = LE16_TO_CPU(cmd_resp->vebs_used);
2919 	if (vebs_free)
2920 		*vebs_free = LE16_TO_CPU(cmd_resp->vebs_free);
2921 	if (floating) {
2922 		u16 flags = LE16_TO_CPU(cmd_resp->veb_flags);
2923 
2924 		if (flags & I40E_AQC_ADD_VEB_FLOATING)
2925 			*floating = TRUE;
2926 		else
2927 			*floating = FALSE;
2928 	}
2929 
2930 get_veb_exit:
2931 	return status;
2932 }
2933 
2934 /**
2935  * i40e_aq_add_macvlan
2936  * @hw: pointer to the hw struct
2937  * @seid: VSI for the mac address
2938  * @mv_list: list of macvlans to be added
2939  * @count: length of the list
2940  * @cmd_details: pointer to command details structure or NULL
2941  *
2942  * Add MAC/VLAN addresses to the HW filtering
2943  **/
2944 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2945 			struct i40e_aqc_add_macvlan_element_data *mv_list,
2946 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2947 {
2948 	struct i40e_aq_desc desc;
2949 	struct i40e_aqc_macvlan *cmd =
2950 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2951 	enum i40e_status_code status;
2952 	u16 buf_size;
2953 	int i;
2954 
2955 	if (count == 0 || !mv_list || !hw)
2956 		return I40E_ERR_PARAM;
2957 
2958 	buf_size = count * sizeof(*mv_list);
2959 
2960 	/* prep the rest of the request */
2961 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2962 	cmd->num_addresses = CPU_TO_LE16(count);
2963 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2964 	cmd->seid[1] = 0;
2965 	cmd->seid[2] = 0;
2966 
2967 	for (i = 0; i < count; i++)
2968 		if (I40E_IS_MULTICAST(mv_list[i].mac_addr))
2969 			mv_list[i].flags |=
2970 			    CPU_TO_LE16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2971 
2972 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2973 	if (buf_size > I40E_AQ_LARGE_BUF)
2974 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
2975 
2976 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2977 				       cmd_details);
2978 
2979 	return status;
2980 }
2981 
2982 /**
2983  * i40e_aq_remove_macvlan
2984  * @hw: pointer to the hw struct
2985  * @seid: VSI for the mac address
2986  * @mv_list: list of macvlans to be removed
2987  * @count: length of the list
2988  * @cmd_details: pointer to command details structure or NULL
2989  *
2990  * Remove MAC/VLAN addresses from the HW filtering
2991  **/
2992 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2993 			struct i40e_aqc_remove_macvlan_element_data *mv_list,
2994 			u16 count, struct i40e_asq_cmd_details *cmd_details)
2995 {
2996 	struct i40e_aq_desc desc;
2997 	struct i40e_aqc_macvlan *cmd =
2998 		(struct i40e_aqc_macvlan *)&desc.params.raw;
2999 	enum i40e_status_code status;
3000 	u16 buf_size;
3001 
3002 	if (count == 0 || !mv_list || !hw)
3003 		return I40E_ERR_PARAM;
3004 
3005 	buf_size = count * sizeof(*mv_list);
3006 
3007 	/* prep the rest of the request */
3008 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
3009 	cmd->num_addresses = CPU_TO_LE16(count);
3010 	cmd->seid[0] = CPU_TO_LE16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
3011 	cmd->seid[1] = 0;
3012 	cmd->seid[2] = 0;
3013 
3014 	desc.flags |= CPU_TO_LE16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3015 	if (buf_size > I40E_AQ_LARGE_BUF)
3016 		desc.flags |= CPU_TO_LE16((u16)I40E_AQ_FLAG_LB);
3017 
3018 	status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
3019 				       cmd_details);
3020 
3021 	return status;
3022 }
3023 
3024 /**
3025  * i40e_mirrorrule_op - Internal helper function to add/delete mirror rule
3026  * @hw: pointer to the hw struct
3027  * @opcode: AQ opcode for add or delete mirror rule
3028  * @sw_seid: Switch SEID (to which rule refers)
3029  * @rule_type: Rule Type (ingress/egress/VLAN)
3030  * @id: Destination VSI SEID or Rule ID
3031  * @count: length of the list
3032  * @mr_list: list of mirrored VSI SEIDs or VLAN IDs
3033  * @cmd_details: pointer to command details structure or NULL
3034  * @rule_id: Rule ID returned from FW
3035  * @rules_used: Number of rules used in internal switch
3036  * @rules_free: Number of rules free in internal switch
3037  *
3038  * Add/Delete a mirror rule to a specific switch. Mirror rules are supported for
3039  * VEBs/VEPA elements only
3040  **/
3041 static enum i40e_status_code i40e_mirrorrule_op(struct i40e_hw *hw,
3042 			u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
3043 			u16 count, __le16 *mr_list,
3044 			struct i40e_asq_cmd_details *cmd_details,
3045