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33 /*$FreeBSD: head/sys/dev/ixl/i40e_adminq_cmd.h 284049 2015-06-05 22:52:42Z jfv $*/
34 
35 #ifndef _I40E_ADMINQ_CMD_H_
36 #define _I40E_ADMINQ_CMD_H_
37 
38 /* This header file defines the i40e Admin Queue commands and is shared between
39  * i40e Firmware and Software.
40  *
41  * This file needs to comply with the Linux Kernel coding style.
42  */
43 
44 #define I40E_FW_API_VERSION_MAJOR	0x0001
45 #ifdef X722_SUPPORT
46 #define I40E_FW_API_VERSION_MINOR	0x0003
47 #else
48 #define I40E_FW_API_VERSION_MINOR	0x0004
49 #endif
50 
51 struct i40e_aq_desc {
52 	__le16 flags;
53 	__le16 opcode;
54 	__le16 datalen;
55 	__le16 retval;
56 	__le32 cookie_high;
57 	__le32 cookie_low;
58 	union {
59 		struct {
60 			__le32 param0;
61 			__le32 param1;
62 			__le32 param2;
63 			__le32 param3;
64 		} internal;
65 		struct {
66 			__le32 param0;
67 			__le32 param1;
68 			__le32 addr_high;
69 			__le32 addr_low;
70 		} external;
71 		u8 raw[16];
72 	} params;
73 };
74 
75 /* Flags sub-structure
76  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
77  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
78  */
79 
80 /* command flags and offsets*/
81 #define I40E_AQ_FLAG_DD_SHIFT	0
82 #define I40E_AQ_FLAG_CMP_SHIFT	1
83 #define I40E_AQ_FLAG_ERR_SHIFT	2
84 #define I40E_AQ_FLAG_VFE_SHIFT	3
85 #define I40E_AQ_FLAG_LB_SHIFT	9
86 #define I40E_AQ_FLAG_RD_SHIFT	10
87 #define I40E_AQ_FLAG_VFC_SHIFT	11
88 #define I40E_AQ_FLAG_BUF_SHIFT	12
89 #define I40E_AQ_FLAG_SI_SHIFT	13
90 #define I40E_AQ_FLAG_EI_SHIFT	14
91 #define I40E_AQ_FLAG_FE_SHIFT	15
92 
93 #define I40E_AQ_FLAG_DD		(1 << I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
94 #define I40E_AQ_FLAG_CMP	(1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
95 #define I40E_AQ_FLAG_ERR	(1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
96 #define I40E_AQ_FLAG_VFE	(1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
97 #define I40E_AQ_FLAG_LB		(1 << I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
98 #define I40E_AQ_FLAG_RD		(1 << I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
99 #define I40E_AQ_FLAG_VFC	(1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
100 #define I40E_AQ_FLAG_BUF	(1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
101 #define I40E_AQ_FLAG_SI		(1 << I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
102 #define I40E_AQ_FLAG_EI		(1 << I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
103 #define I40E_AQ_FLAG_FE		(1 << I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
104 
105 /* error codes */
106 enum i40e_admin_queue_err {
107 	I40E_AQ_RC_OK		= 0,  /* success */
108 	I40E_AQ_RC_EPERM	= 1,  /* Operation not permitted */
109 	I40E_AQ_RC_ENOENT	= 2,  /* No such element */
110 	I40E_AQ_RC_ESRCH	= 3,  /* Bad opcode */
111 	I40E_AQ_RC_EINTR	= 4,  /* operation interrupted */
112 	I40E_AQ_RC_EIO		= 5,  /* I/O error */
113 	I40E_AQ_RC_ENXIO	= 6,  /* No such resource */
114 	I40E_AQ_RC_E2BIG	= 7,  /* Arg too long */
115 	I40E_AQ_RC_EAGAIN	= 8,  /* Try again */
116 	I40E_AQ_RC_ENOMEM	= 9,  /* Out of memory */
117 	I40E_AQ_RC_EACCES	= 10, /* Permission denied */
118 	I40E_AQ_RC_EFAULT	= 11, /* Bad address */
119 	I40E_AQ_RC_EBUSY	= 12, /* Device or resource busy */
120 	I40E_AQ_RC_EEXIST	= 13, /* object already exists */
121 	I40E_AQ_RC_EINVAL	= 14, /* Invalid argument */
122 	I40E_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
123 	I40E_AQ_RC_ENOSPC	= 16, /* No space left or alloc failure */
124 	I40E_AQ_RC_ENOSYS	= 17, /* Function not implemented */
125 	I40E_AQ_RC_ERANGE	= 18, /* Parameter out of range */
126 	I40E_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
127 	I40E_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
128 	I40E_AQ_RC_EMODE	= 21, /* Op not allowed in current dev mode */
129 	I40E_AQ_RC_EFBIG	= 22, /* File too large */
130 };
131 
132 /* Admin Queue command opcodes */
133 enum i40e_admin_queue_opc {
134 	/* aq commands */
135 	i40e_aqc_opc_get_version	= 0x0001,
136 	i40e_aqc_opc_driver_version	= 0x0002,
137 	i40e_aqc_opc_queue_shutdown	= 0x0003,
138 	i40e_aqc_opc_set_pf_context	= 0x0004,
139 
140 	/* resource ownership */
141 	i40e_aqc_opc_request_resource	= 0x0008,
142 	i40e_aqc_opc_release_resource	= 0x0009,
143 
144 	i40e_aqc_opc_list_func_capabilities	= 0x000A,
145 	i40e_aqc_opc_list_dev_capabilities	= 0x000B,
146 
147 	/* LAA */
148 	i40e_aqc_opc_mac_address_read	= 0x0107,
149 	i40e_aqc_opc_mac_address_write	= 0x0108,
150 
151 	/* PXE */
152 	i40e_aqc_opc_clear_pxe_mode	= 0x0110,
153 
154 	/* internal switch commands */
155 	i40e_aqc_opc_get_switch_config		= 0x0200,
156 	i40e_aqc_opc_add_statistics		= 0x0201,
157 	i40e_aqc_opc_remove_statistics		= 0x0202,
158 	i40e_aqc_opc_set_port_parameters	= 0x0203,
159 	i40e_aqc_opc_get_switch_resource_alloc	= 0x0204,
160 
161 	i40e_aqc_opc_add_vsi			= 0x0210,
162 	i40e_aqc_opc_update_vsi_parameters	= 0x0211,
163 	i40e_aqc_opc_get_vsi_parameters		= 0x0212,
164 
165 	i40e_aqc_opc_add_pv			= 0x0220,
166 	i40e_aqc_opc_update_pv_parameters	= 0x0221,
167 	i40e_aqc_opc_get_pv_parameters		= 0x0222,
168 
169 	i40e_aqc_opc_add_veb			= 0x0230,
170 	i40e_aqc_opc_update_veb_parameters	= 0x0231,
171 	i40e_aqc_opc_get_veb_parameters		= 0x0232,
172 
173 	i40e_aqc_opc_delete_element		= 0x0243,
174 
175 	i40e_aqc_opc_add_macvlan		= 0x0250,
176 	i40e_aqc_opc_remove_macvlan		= 0x0251,
177 	i40e_aqc_opc_add_vlan			= 0x0252,
178 	i40e_aqc_opc_remove_vlan		= 0x0253,
179 	i40e_aqc_opc_set_vsi_promiscuous_modes	= 0x0254,
180 	i40e_aqc_opc_add_tag			= 0x0255,
181 	i40e_aqc_opc_remove_tag			= 0x0256,
182 	i40e_aqc_opc_add_multicast_etag		= 0x0257,
183 	i40e_aqc_opc_remove_multicast_etag	= 0x0258,
184 	i40e_aqc_opc_update_tag			= 0x0259,
185 	i40e_aqc_opc_add_control_packet_filter	= 0x025A,
186 	i40e_aqc_opc_remove_control_packet_filter	= 0x025B,
187 	i40e_aqc_opc_add_cloud_filters		= 0x025C,
188 	i40e_aqc_opc_remove_cloud_filters	= 0x025D,
189 
190 	i40e_aqc_opc_add_mirror_rule	= 0x0260,
191 	i40e_aqc_opc_delete_mirror_rule	= 0x0261,
192 
193 	/* DCB commands */
194 	i40e_aqc_opc_dcb_ignore_pfc	= 0x0301,
195 	i40e_aqc_opc_dcb_updated	= 0x0302,
196 
197 	/* TX scheduler */
198 	i40e_aqc_opc_configure_vsi_bw_limit		= 0x0400,
199 	i40e_aqc_opc_configure_vsi_ets_sla_bw_limit	= 0x0406,
200 	i40e_aqc_opc_configure_vsi_tc_bw		= 0x0407,
201 	i40e_aqc_opc_query_vsi_bw_config		= 0x0408,
202 	i40e_aqc_opc_query_vsi_ets_sla_config		= 0x040A,
203 	i40e_aqc_opc_configure_switching_comp_bw_limit	= 0x0410,
204 
205 	i40e_aqc_opc_enable_switching_comp_ets			= 0x0413,
206 	i40e_aqc_opc_modify_switching_comp_ets			= 0x0414,
207 	i40e_aqc_opc_disable_switching_comp_ets			= 0x0415,
208 	i40e_aqc_opc_configure_switching_comp_ets_bw_limit	= 0x0416,
209 	i40e_aqc_opc_configure_switching_comp_bw_config		= 0x0417,
210 	i40e_aqc_opc_query_switching_comp_ets_config		= 0x0418,
211 	i40e_aqc_opc_query_port_ets_config			= 0x0419,
212 	i40e_aqc_opc_query_switching_comp_bw_config		= 0x041A,
213 	i40e_aqc_opc_suspend_port_tx				= 0x041B,
214 	i40e_aqc_opc_resume_port_tx				= 0x041C,
215 	i40e_aqc_opc_configure_partition_bw			= 0x041D,
216 
217 	/* hmc */
218 	i40e_aqc_opc_query_hmc_resource_profile	= 0x0500,
219 	i40e_aqc_opc_set_hmc_resource_profile	= 0x0501,
220 
221 	/* phy commands*/
222 	i40e_aqc_opc_get_phy_abilities		= 0x0600,
223 	i40e_aqc_opc_set_phy_config		= 0x0601,
224 	i40e_aqc_opc_set_mac_config		= 0x0603,
225 	i40e_aqc_opc_set_link_restart_an	= 0x0605,
226 	i40e_aqc_opc_get_link_status		= 0x0607,
227 	i40e_aqc_opc_set_phy_int_mask		= 0x0613,
228 	i40e_aqc_opc_get_local_advt_reg		= 0x0614,
229 	i40e_aqc_opc_set_local_advt_reg		= 0x0615,
230 	i40e_aqc_opc_get_partner_advt		= 0x0616,
231 	i40e_aqc_opc_set_lb_modes		= 0x0618,
232 	i40e_aqc_opc_get_phy_wol_caps		= 0x0621,
233 	i40e_aqc_opc_set_phy_debug		= 0x0622,
234 	i40e_aqc_opc_upload_ext_phy_fm		= 0x0625,
235 
236 	/* NVM commands */
237 	i40e_aqc_opc_nvm_read			= 0x0701,
238 	i40e_aqc_opc_nvm_erase			= 0x0702,
239 	i40e_aqc_opc_nvm_update			= 0x0703,
240 	i40e_aqc_opc_nvm_config_read		= 0x0704,
241 	i40e_aqc_opc_nvm_config_write		= 0x0705,
242 	i40e_aqc_opc_oem_post_update		= 0x0720,
243 
244 	/* virtualization commands */
245 	i40e_aqc_opc_send_msg_to_pf		= 0x0801,
246 	i40e_aqc_opc_send_msg_to_vf		= 0x0802,
247 	i40e_aqc_opc_send_msg_to_peer		= 0x0803,
248 
249 	/* alternate structure */
250 	i40e_aqc_opc_alternate_write		= 0x0900,
251 	i40e_aqc_opc_alternate_write_indirect	= 0x0901,
252 	i40e_aqc_opc_alternate_read		= 0x0902,
253 	i40e_aqc_opc_alternate_read_indirect	= 0x0903,
254 	i40e_aqc_opc_alternate_write_done	= 0x0904,
255 	i40e_aqc_opc_alternate_set_mode		= 0x0905,
256 	i40e_aqc_opc_alternate_clear_port	= 0x0906,
257 
258 	/* LLDP commands */
259 	i40e_aqc_opc_lldp_get_mib	= 0x0A00,
260 	i40e_aqc_opc_lldp_update_mib	= 0x0A01,
261 	i40e_aqc_opc_lldp_add_tlv	= 0x0A02,
262 	i40e_aqc_opc_lldp_update_tlv	= 0x0A03,
263 	i40e_aqc_opc_lldp_delete_tlv	= 0x0A04,
264 	i40e_aqc_opc_lldp_stop		= 0x0A05,
265 	i40e_aqc_opc_lldp_start		= 0x0A06,
266 	i40e_aqc_opc_get_cee_dcb_cfg	= 0x0A07,
267 	i40e_aqc_opc_lldp_set_local_mib	= 0x0A08,
268 	i40e_aqc_opc_lldp_stop_start_spec_agent	= 0x0A09,
269 
270 	/* Tunnel commands */
271 	i40e_aqc_opc_add_udp_tunnel	= 0x0B00,
272 	i40e_aqc_opc_del_udp_tunnel	= 0x0B01,
273 #ifdef X722_SUPPORT
274 	i40e_aqc_opc_set_rss_key	= 0x0B02,
275 	i40e_aqc_opc_set_rss_lut	= 0x0B03,
276 	i40e_aqc_opc_get_rss_key	= 0x0B04,
277 	i40e_aqc_opc_get_rss_lut	= 0x0B05,
278 #endif
279 
280 	/* Async Events */
281 	i40e_aqc_opc_event_lan_overflow		= 0x1001,
282 
283 	/* OEM commands */
284 	i40e_aqc_opc_oem_parameter_change	= 0xFE00,
285 	i40e_aqc_opc_oem_device_status_change	= 0xFE01,
286 	i40e_aqc_opc_oem_ocsd_initialize	= 0xFE02,
287 	i40e_aqc_opc_oem_ocbb_initialize	= 0xFE03,
288 
289 	/* debug commands */
290 	i40e_aqc_opc_debug_read_reg		= 0xFF03,
291 	i40e_aqc_opc_debug_write_reg		= 0xFF04,
292 	i40e_aqc_opc_debug_modify_reg		= 0xFF07,
293 	i40e_aqc_opc_debug_dump_internals	= 0xFF08,
294 };
295 
296 /* command structures and indirect data structures */
297 
298 /* Structure naming conventions:
299  * - no suffix for direct command descriptor structures
300  * - _data for indirect sent data
301  * - _resp for indirect return data (data which is both will use _data)
302  * - _completion for direct return data
303  * - _element_ for repeated elements (may also be _data or _resp)
304  *
305  * Command structures are expected to overlay the params.raw member of the basic
306  * descriptor, and as such cannot exceed 16 bytes in length.
307  */
308 
309 /* This macro is used to generate a compilation error if a structure
310  * is not exactly the correct length. It gives a divide by zero error if the
311  * structure is not of the correct size, otherwise it creates an enum that is
312  * never used.
313  */
314 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
315 	{ i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
316 
317 /* This macro is used extensively to ensure that command structures are 16
318  * bytes in length as they have to map to the raw array of that size.
319  */
320 #define I40E_CHECK_CMD_LENGTH(X)	I40E_CHECK_STRUCT_LEN(16, X)
321 
322 /* internal (0x00XX) commands */
323 
324 /* Get version (direct 0x0001) */
325 struct i40e_aqc_get_version {
326 	__le32 rom_ver;
327 	__le32 fw_build;
328 	__le16 fw_major;
329 	__le16 fw_minor;
330 	__le16 api_major;
331 	__le16 api_minor;
332 };
333 
334 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
335 
336 /* Send driver version (indirect 0x0002) */
337 struct i40e_aqc_driver_version {
338 	u8	driver_major_ver;
339 	u8	driver_minor_ver;
340 	u8	driver_build_ver;
341 	u8	driver_subbuild_ver;
342 	u8	reserved[4];
343 	__le32	address_high;
344 	__le32	address_low;
345 };
346 
347 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
348 
349 /* Queue Shutdown (direct 0x0003) */
350 struct i40e_aqc_queue_shutdown {
351 	__le32	driver_unloading;
352 #define I40E_AQ_DRIVER_UNLOADING	0x1
353 	u8	reserved[12];
354 };
355 
356 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
357 
358 /* Set PF context (0x0004, direct) */
359 struct i40e_aqc_set_pf_context {
360 	u8	pf_id;
361 	u8	reserved[15];
362 };
363 
364 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
365 
366 /* Request resource ownership (direct 0x0008)
367  * Release resource ownership (direct 0x0009)
368  */
369 #define I40E_AQ_RESOURCE_NVM			1
370 #define I40E_AQ_RESOURCE_SDP			2
371 #define I40E_AQ_RESOURCE_ACCESS_READ		1
372 #define I40E_AQ_RESOURCE_ACCESS_WRITE		2
373 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT	3000
374 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT	180000
375 
376 struct i40e_aqc_request_resource {
377 	__le16	resource_id;
378 	__le16	access_type;
379 	__le32	timeout;
380 	__le32	resource_number;
381 	u8	reserved[4];
382 };
383 
384 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
385 
386 /* Get function capabilities (indirect 0x000A)
387  * Get device capabilities (indirect 0x000B)
388  */
389 struct i40e_aqc_list_capabilites {
390 	u8 command_flags;
391 #define I40E_AQ_LIST_CAP_PF_INDEX_EN	1
392 	u8 pf_index;
393 	u8 reserved[2];
394 	__le32 count;
395 	__le32 addr_high;
396 	__le32 addr_low;
397 };
398 
399 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
400 
401 struct i40e_aqc_list_capabilities_element_resp {
402 	__le16	id;
403 	u8	major_rev;
404 	u8	minor_rev;
405 	__le32	number;
406 	__le32	logical_id;
407 	__le32	phys_id;
408 	u8	reserved[16];
409 };
410 
411 /* list of caps */
412 
413 #define I40E_AQ_CAP_ID_SWITCH_MODE	0x0001
414 #define I40E_AQ_CAP_ID_MNG_MODE		0x0002
415 #define I40E_AQ_CAP_ID_NPAR_ACTIVE	0x0003
416 #define I40E_AQ_CAP_ID_OS2BMC_CAP	0x0004
417 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID	0x0005
418 #define I40E_AQ_CAP_ID_ALTERNATE_RAM	0x0006
419 #define I40E_AQ_CAP_ID_SRIOV		0x0012
420 #define I40E_AQ_CAP_ID_VF		0x0013
421 #define I40E_AQ_CAP_ID_VMDQ		0x0014
422 #define I40E_AQ_CAP_ID_8021QBG		0x0015
423 #define I40E_AQ_CAP_ID_8021QBR		0x0016
424 #define I40E_AQ_CAP_ID_VSI		0x0017
425 #define I40E_AQ_CAP_ID_DCB		0x0018
426 #define I40E_AQ_CAP_ID_FCOE		0x0021
427 #define I40E_AQ_CAP_ID_ISCSI		0x0022
428 #define I40E_AQ_CAP_ID_RSS		0x0040
429 #define I40E_AQ_CAP_ID_RXQ		0x0041
430 #define I40E_AQ_CAP_ID_TXQ		0x0042
431 #define I40E_AQ_CAP_ID_MSIX		0x0043
432 #define I40E_AQ_CAP_ID_VF_MSIX		0x0044
433 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR	0x0045
434 #define I40E_AQ_CAP_ID_1588		0x0046
435 #define I40E_AQ_CAP_ID_IWARP		0x0051
436 #define I40E_AQ_CAP_ID_LED		0x0061
437 #define I40E_AQ_CAP_ID_SDP		0x0062
438 #define I40E_AQ_CAP_ID_MDIO		0x0063
439 #define I40E_AQ_CAP_ID_FLEX10		0x00F1
440 #define I40E_AQ_CAP_ID_CEM		0x00F2
441 
442 /* Set CPPM Configuration (direct 0x0103) */
443 struct i40e_aqc_cppm_configuration {
444 	__le16	command_flags;
445 #define I40E_AQ_CPPM_EN_LTRC	0x0800
446 #define I40E_AQ_CPPM_EN_DMCTH	0x1000
447 #define I40E_AQ_CPPM_EN_DMCTLX	0x2000
448 #define I40E_AQ_CPPM_EN_HPTC	0x4000
449 #define I40E_AQ_CPPM_EN_DMARC	0x8000
450 	__le16	ttlx;
451 	__le32	dmacr;
452 	__le16	dmcth;
453 	u8	hptc;
454 	u8	reserved;
455 	__le32	pfltrc;
456 };
457 
458 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
459 
460 /* Set ARP Proxy command / response (indirect 0x0104) */
461 struct i40e_aqc_arp_proxy_data {
462 	__le16	command_flags;
463 #define I40E_AQ_ARP_INIT_IPV4	0x0008
464 #define I40E_AQ_ARP_UNSUP_CTL	0x0010
465 #define I40E_AQ_ARP_ENA		0x0020
466 #define I40E_AQ_ARP_ADD_IPV4	0x0040
467 #define I40E_AQ_ARP_DEL_IPV4	0x0080
468 	__le16	table_id;
469 	__le32	pfpm_proxyfc;
470 	__le32	ip_addr;
471 	u8	mac_addr[6];
472 	u8	reserved[2];
473 };
474 
475 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
476 
477 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
478 struct i40e_aqc_ns_proxy_data {
479 	__le16	table_idx_mac_addr_0;
480 	__le16	table_idx_mac_addr_1;
481 	__le16	table_idx_ipv6_0;
482 	__le16	table_idx_ipv6_1;
483 	__le16	control;
484 #define I40E_AQ_NS_PROXY_ADD_0		0x0100
485 #define I40E_AQ_NS_PROXY_DEL_0		0x0200
486 #define I40E_AQ_NS_PROXY_ADD_1		0x0400
487 #define I40E_AQ_NS_PROXY_DEL_1		0x0800
488 #define I40E_AQ_NS_PROXY_ADD_IPV6_0	0x1000
489 #define I40E_AQ_NS_PROXY_DEL_IPV6_0	0x2000
490 #define I40E_AQ_NS_PROXY_ADD_IPV6_1	0x4000
491 #define I40E_AQ_NS_PROXY_DEL_IPV6_1	0x8000
492 #define I40E_AQ_NS_PROXY_COMMAND_SEQ	0x0001
493 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL	0x0002
494 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL	0x0004
495 	u8	mac_addr_0[6];
496 	u8	mac_addr_1[6];
497 	u8	local_mac_addr[6];
498 	u8	ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
499 	u8	ipv6_addr_1[16];
500 };
501 
502 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
503 
504 /* Manage LAA Command (0x0106) - obsolete */
505 struct i40e_aqc_mng_laa {
506 	__le16	command_flags;
507 #define I40E_AQ_LAA_FLAG_WR	0x8000
508 	u8	reserved[2];
509 	__le32	sal;
510 	__le16	sah;
511 	u8	reserved2[6];
512 };
513 
514 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
515 
516 /* Manage MAC Address Read Command (indirect 0x0107) */
517 struct i40e_aqc_mac_address_read {
518 	__le16	command_flags;
519 #define I40E_AQC_LAN_ADDR_VALID		0x10
520 #define I40E_AQC_SAN_ADDR_VALID		0x20
521 #define I40E_AQC_PORT_ADDR_VALID	0x40
522 #define I40E_AQC_WOL_ADDR_VALID		0x80
523 #define I40E_AQC_MC_MAG_EN_VALID	0x100
524 #define I40E_AQC_ADDR_VALID_MASK	0x1F0
525 	u8	reserved[6];
526 	__le32	addr_high;
527 	__le32	addr_low;
528 };
529 
530 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
531 
532 struct i40e_aqc_mac_address_read_data {
533 	u8 pf_lan_mac[6];
534 	u8 pf_san_mac[6];
535 	u8 port_mac[6];
536 	u8 pf_wol_mac[6];
537 };
538 
539 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
540 
541 /* Manage MAC Address Write Command (0x0108) */
542 struct i40e_aqc_mac_address_write {
543 	__le16	command_flags;
544 #define I40E_AQC_WRITE_TYPE_LAA_ONLY	0x0000
545 #define I40E_AQC_WRITE_TYPE_LAA_WOL	0x4000
546 #define I40E_AQC_WRITE_TYPE_PORT	0x8000
547 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG	0xC000
548 #define I40E_AQC_WRITE_TYPE_MASK	0xC000
549 
550 	__le16	mac_sah;
551 	__le32	mac_sal;
552 	u8	reserved[8];
553 };
554 
555 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
556 
557 /* PXE commands (0x011x) */
558 
559 /* Clear PXE Command and response  (direct 0x0110) */
560 struct i40e_aqc_clear_pxe {
561 	u8	rx_cnt;
562 	u8	reserved[15];
563 };
564 
565 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
566 
567 /* Switch configuration commands (0x02xx) */
568 
569 /* Used by many indirect commands that only pass an seid and a buffer in the
570  * command
571  */
572 struct i40e_aqc_switch_seid {
573 	__le16	seid;
574 	u8	reserved[6];
575 	__le32	addr_high;
576 	__le32	addr_low;
577 };
578 
579 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
580 
581 /* Get Switch Configuration command (indirect 0x0200)
582  * uses i40e_aqc_switch_seid for the descriptor
583  */
584 struct i40e_aqc_get_switch_config_header_resp {
585 	__le16	num_reported;
586 	__le16	num_total;
587 	u8	reserved[12];
588 };
589 
590 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
591 
592 struct i40e_aqc_switch_config_element_resp {
593 	u8	element_type;
594 #define I40E_AQ_SW_ELEM_TYPE_MAC	1
595 #define I40E_AQ_SW_ELEM_TYPE_PF		2
596 #define I40E_AQ_SW_ELEM_TYPE_VF		3
597 #define I40E_AQ_SW_ELEM_TYPE_EMP	4
598 #define I40E_AQ_SW_ELEM_TYPE_BMC	5
599 #define I40E_AQ_SW_ELEM_TYPE_PV		16
600 #define I40E_AQ_SW_ELEM_TYPE_VEB	17
601 #define I40E_AQ_SW_ELEM_TYPE_PA		18
602 #define I40E_AQ_SW_ELEM_TYPE_VSI	19
603 	u8	revision;
604 #define I40E_AQ_SW_ELEM_REV_1		1
605 	__le16	seid;
606 	__le16	uplink_seid;
607 	__le16	downlink_seid;
608 	u8	reserved[3];
609 	u8	connection_type;
610 #define I40E_AQ_CONN_TYPE_REGULAR	0x1
611 #define I40E_AQ_CONN_TYPE_DEFAULT	0x2
612 #define I40E_AQ_CONN_TYPE_CASCADED	0x3
613 	__le16	scheduler_id;
614 	__le16	element_info;
615 };
616 
617 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
618 
619 /* Get Switch Configuration (indirect 0x0200)
620  *    an array of elements are returned in the response buffer
621  *    the first in the array is the header, remainder are elements
622  */
623 struct i40e_aqc_get_switch_config_resp {
624 	struct i40e_aqc_get_switch_config_header_resp	header;
625 	struct i40e_aqc_switch_config_element_resp	element[1];
626 };
627 
628 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
629 
630 /* Add Statistics (direct 0x0201)
631  * Remove Statistics (direct 0x0202)
632  */
633 struct i40e_aqc_add_remove_statistics {
634 	__le16	seid;
635 	__le16	vlan;
636 	__le16	stat_index;
637 	u8	reserved[10];
638 };
639 
640 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
641 
642 /* Set Port Parameters command (direct 0x0203) */
643 struct i40e_aqc_set_port_parameters {
644 	__le16	command_flags;
645 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS	1
646 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS	2 /* must set! */
647 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA	4
648 	__le16	bad_frame_vsi;
649 	__le16	default_seid;        /* reserved for command */
650 	u8	reserved[10];
651 };
652 
653 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
654 
655 /* Get Switch Resource Allocation (indirect 0x0204) */
656 struct i40e_aqc_get_switch_resource_alloc {
657 	u8	num_entries;         /* reserved for command */
658 	u8	reserved[7];
659 	__le32	addr_high;
660 	__le32	addr_low;
661 };
662 
663 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
664 
665 /* expect an array of these structs in the response buffer */
666 struct i40e_aqc_switch_resource_alloc_element_resp {
667 	u8	resource_type;
668 #define I40E_AQ_RESOURCE_TYPE_VEB		0x0
669 #define I40E_AQ_RESOURCE_TYPE_VSI		0x1
670 #define I40E_AQ_RESOURCE_TYPE_MACADDR		0x2
671 #define I40E_AQ_RESOURCE_TYPE_STAG		0x3
672 #define I40E_AQ_RESOURCE_TYPE_ETAG		0x4
673 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH	0x5
674 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH	0x6
675 #define I40E_AQ_RESOURCE_TYPE_VLAN		0x7
676 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY	0x8
677 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY	0x9
678 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL	0xA
679 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE	0xB
680 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS	0xC
681 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS	0xD
682 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS	0xF
683 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS	0x10
684 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS	0x11
685 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS		0x12
686 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS	0x13
687 	u8	reserved1;
688 	__le16	guaranteed;
689 	__le16	total;
690 	__le16	used;
691 	__le16	total_unalloced;
692 	u8	reserved2[6];
693 };
694 
695 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
696 
697 /* Add VSI (indirect 0x0210)
698  *    this indirect command uses struct i40e_aqc_vsi_properties_data
699  *    as the indirect buffer (128 bytes)
700  *
701  * Update VSI (indirect 0x211)
702  *     uses the same data structure as Add VSI
703  *
704  * Get VSI (indirect 0x0212)
705  *     uses the same completion and data structure as Add VSI
706  */
707 struct i40e_aqc_add_get_update_vsi {
708 	__le16	uplink_seid;
709 	u8	connection_type;
710 #define I40E_AQ_VSI_CONN_TYPE_NORMAL	0x1
711 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT	0x2
712 #define I40E_AQ_VSI_CONN_TYPE_CASCADED	0x3
713 	u8	reserved1;
714 	u8	vf_id;
715 	u8	reserved2;
716 	__le16	vsi_flags;
717 #define I40E_AQ_VSI_TYPE_SHIFT		0x0
718 #define I40E_AQ_VSI_TYPE_MASK		(0x3 << I40E_AQ_VSI_TYPE_SHIFT)
719 #define I40E_AQ_VSI_TYPE_VF		0x0
720 #define I40E_AQ_VSI_TYPE_VMDQ2		0x1
721 #define I40E_AQ_VSI_TYPE_PF		0x2
722 #define I40E_AQ_VSI_TYPE_EMP_MNG	0x3
723 #define I40E_AQ_VSI_FLAG_CASCADED_PV	0x4
724 	__le32	addr_high;
725 	__le32	addr_low;
726 };
727 
728 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
729 
730 struct i40e_aqc_add_get_update_vsi_completion {
731 	__le16 seid;
732 	__le16 vsi_number;
733 	__le16 vsi_used;
734 	__le16 vsi_free;
735 	__le32 addr_high;
736 	__le32 addr_low;
737 };
738 
739 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
740 
741 struct i40e_aqc_vsi_properties_data {
742 	/* first 96 byte are written by SW */
743 	__le16	valid_sections;
744 #define I40E_AQ_VSI_PROP_SWITCH_VALID		0x0001
745 #define I40E_AQ_VSI_PROP_SECURITY_VALID		0x0002
746 #define I40E_AQ_VSI_PROP_VLAN_VALID		0x0004
747 #define I40E_AQ_VSI_PROP_CAS_PV_VALID		0x0008
748 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID	0x0010
749 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID	0x0020
750 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID	0x0040
751 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID	0x0080
752 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID		0x0100
753 #define I40E_AQ_VSI_PROP_SCHED_VALID		0x0200
754 	/* switch section */
755 	__le16	switch_id; /* 12bit id combined with flags below */
756 #define I40E_AQ_VSI_SW_ID_SHIFT		0x0000
757 #define I40E_AQ_VSI_SW_ID_MASK		(0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
758 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG	0x1000
759 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB	0x2000
760 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB	0x4000
761 	u8	sw_reserved[2];
762 	/* security section */
763 	u8	sec_flags;
764 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	0x01
765 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK	0x02
766 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK	0x04
767 	u8	sec_reserved;
768 	/* VLAN section */
769 	__le16	pvid; /* VLANS include priority bits */
770 	__le16	fcoe_pvid;
771 	u8	port_vlan_flags;
772 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT	0x00
773 #define I40E_AQ_VSI_PVLAN_MODE_MASK	(0x03 << \
774 					 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
775 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED	0x01
776 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED	0x02
777 #define I40E_AQ_VSI_PVLAN_MODE_ALL	0x03
778 #define I40E_AQ_VSI_PVLAN_INSERT_PVID	0x04
779 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT	0x03
780 #define I40E_AQ_VSI_PVLAN_EMOD_MASK	(0x3 << \
781 					 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
782 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH	0x0
783 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP	0x08
784 #define I40E_AQ_VSI_PVLAN_EMOD_STR	0x10
785 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING	0x18
786 	u8	pvlan_reserved[3];
787 	/* ingress egress up sections */
788 	__le32	ingress_table; /* bitmap, 3 bits per up */
789 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT	0
790 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK	(0x7 << \
791 					 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
792 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT	3
793 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK	(0x7 << \
794 					 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
795 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT	6
796 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK	(0x7 << \
797 					 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
798 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT	9
799 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK	(0x7 << \
800 					 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
801 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT	12
802 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK	(0x7 << \
803 					 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
804 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT	15
805 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK	(0x7 << \
806 					 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
807 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT	18
808 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK	(0x7 << \
809 					 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
810 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT	21
811 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK	(0x7 << \
812 					 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
813 	__le32	egress_table;   /* same defines as for ingress table */
814 	/* cascaded PV section */
815 	__le16	cas_pv_tag;
816 	u8	cas_pv_flags;
817 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT		0x00
818 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK		(0x03 << \
819 						 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
820 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE		0x00
821 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE		0x01
822 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY		0x02
823 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG		0x10
824 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE		0x20
825 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG	0x40
826 	u8	cas_pv_reserved;
827 	/* queue mapping section */
828 	__le16	mapping_flags;
829 #define I40E_AQ_VSI_QUE_MAP_CONTIG	0x0
830 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG	0x1
831 	__le16	queue_mapping[16];
832 #define I40E_AQ_VSI_QUEUE_SHIFT		0x0
833 #define I40E_AQ_VSI_QUEUE_MASK		(0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
834 	__le16	tc_mapping[8];
835 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT	0
836 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK	(0x1FF << \
837 					 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
838 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT	9
839 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK	(0x7 << \
840 					 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
841 	/* queueing option section */
842 	u8	queueing_opt_flags;
843 #ifdef X722_SUPPORT
844 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA	0x04
845 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA	0x08
846 #endif
847 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA	0x10
848 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA	0x20
849 #ifdef X722_SUPPORT
850 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF	0x00
851 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI	0x40
852 #endif
853 	u8	queueing_opt_reserved[3];
854 	/* scheduler section */
855 	u8	up_enable_bits;
856 	u8	sched_reserved;
857 	/* outer up section */
858 	__le32	outer_up_table; /* same structure and defines as ingress table */
859 	u8	cmd_reserved[8];
860 	/* last 32 bytes are written by FW */
861 	__le16	qs_handle[8];
862 #define I40E_AQ_VSI_QS_HANDLE_INVALID	0xFFFF
863 	__le16	stat_counter_idx;
864 	__le16	sched_id;
865 	u8	resp_reserved[12];
866 };
867 
868 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
869 
870 /* Add Port Virtualizer (direct 0x0220)
871  * also used for update PV (direct 0x0221) but only flags are used
872  * (IS_CTRL_PORT only works on add PV)
873  */
874 struct i40e_aqc_add_update_pv {
875 	__le16	command_flags;
876 #define I40E_AQC_PV_FLAG_PV_TYPE		0x1
877 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN	0x2
878 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN	0x4
879 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT		0x8
880 	__le16	uplink_seid;
881 	__le16	connected_seid;
882 	u8	reserved[10];
883 };
884 
885 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
886 
887 struct i40e_aqc_add_update_pv_completion {
888 	/* reserved for update; for add also encodes error if rc == ENOSPC */
889 	__le16	pv_seid;
890 #define I40E_AQC_PV_ERR_FLAG_NO_PV	0x1
891 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED	0x2
892 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER	0x4
893 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY	0x8
894 	u8	reserved[14];
895 };
896 
897 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
898 
899 /* Get PV Params (direct 0x0222)
900  * uses i40e_aqc_switch_seid for the descriptor
901  */
902 
903 struct i40e_aqc_get_pv_params_completion {
904 	__le16	seid;
905 	__le16	default_stag;
906 	__le16	pv_flags; /* same flags as add_pv */
907 #define I40E_AQC_GET_PV_PV_TYPE			0x1
908 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG	0x2
909 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG	0x4
910 	u8	reserved[8];
911 	__le16	default_port_seid;
912 };
913 
914 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
915 
916 /* Add VEB (direct 0x0230) */
917 struct i40e_aqc_add_veb {
918 	__le16	uplink_seid;
919 	__le16	downlink_seid;
920 	__le16	veb_flags;
921 #define I40E_AQC_ADD_VEB_FLOATING		0x1
922 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT	1
923 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK		(0x3 << \
924 					I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
925 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT	0x2
926 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA		0x4
927 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER	0x8
928 	u8	enable_tcs;
929 	u8	reserved[9];
930 };
931 
932 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
933 
934 struct i40e_aqc_add_veb_completion {
935 	u8	reserved[6];
936 	__le16	switch_seid;
937 	/* also encodes error if rc == ENOSPC; codes are the same as add_pv */
938 	__le16	veb_seid;
939 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB		0x1
940 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED		0x2
941 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER	0x4
942 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY		0x8
943 	__le16	statistic_index;
944 	__le16	vebs_used;
945 	__le16	vebs_free;
946 };
947 
948 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
949 
950 /* Get VEB Parameters (direct 0x0232)
951  * uses i40e_aqc_switch_seid for the descriptor
952  */
953 struct i40e_aqc_get_veb_parameters_completion {
954 	__le16	seid;
955 	__le16	switch_id;
956 	__le16	veb_flags; /* only the first/last flags from 0x0230 is valid */
957 	__le16	statistic_index;
958 	__le16	vebs_used;
959 	__le16	vebs_free;
960 	u8	reserved[4];
961 };
962 
963 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
964 
965 /* Delete Element (direct 0x0243)
966  * uses the generic i40e_aqc_switch_seid
967  */
968 
969 /* Add MAC-VLAN (indirect 0x0250) */
970 
971 /* used for the command for most vlan commands */
972 struct i40e_aqc_macvlan {
973 	__le16	num_addresses;
974 	__le16	seid[3];
975 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT	0
976 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK	(0x3FF << \
977 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
978 #define I40E_AQC_MACVLAN_CMD_SEID_VALID		0x8000
979 	__le32	addr_high;
980 	__le32	addr_low;
981 };
982 
983 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
984 
985 /* indirect data for command and response */
986 struct i40e_aqc_add_macvlan_element_data {
987 	u8	mac_addr[6];
988 	__le16	vlan_tag;
989 	__le16	flags;
990 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH	0x0001
991 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH		0x0002
992 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN	0x0004
993 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE		0x0008
994 	__le16	queue_number;
995 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT	0
996 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK		(0x7FF << \
997 					I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
998 	/* response section */
999 	u8	match_method;
1000 #define I40E_AQC_MM_PERFECT_MATCH	0x01
1001 #define I40E_AQC_MM_HASH_MATCH		0x02
1002 #define I40E_AQC_MM_ERR_NO_RES		0xFF
1003 	u8	reserved1[3];
1004 };
1005 
1006 struct i40e_aqc_add_remove_macvlan_completion {
1007 	__le16 perfect_mac_used;
1008 	__le16 perfect_mac_free;
1009 	__le16 unicast_hash_free;
1010 	__le16 multicast_hash_free;
1011 	__le32 addr_high;
1012 	__le32 addr_low;
1013 };
1014 
1015 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1016 
1017 /* Remove MAC-VLAN (indirect 0x0251)
1018  * uses i40e_aqc_macvlan for the descriptor
1019  * data points to an array of num_addresses of elements
1020  */
1021 
1022 struct i40e_aqc_remove_macvlan_element_data {
1023 	u8	mac_addr[6];
1024 	__le16	vlan_tag;
1025 	u8	flags;
1026 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH	0x01
1027 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH		0x02
1028 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN	0x08
1029 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS		0x10
1030 	u8	reserved[3];
1031 	/* reply section */
1032 	u8	error_code;
1033 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS		0x0
1034 #define I40E_AQC_REMOVE_MACVLAN_FAIL		0xFF
1035 	u8	reply_reserved[3];
1036 };
1037 
1038 /* Add VLAN (indirect 0x0252)
1039  * Remove VLAN (indirect 0x0253)
1040  * use the generic i40e_aqc_macvlan for the command
1041  */
1042 struct i40e_aqc_add_remove_vlan_element_data {
1043 	__le16	vlan_tag;
1044 	u8	vlan_flags;
1045 /* flags for add VLAN */
1046 #define I40E_AQC_ADD_VLAN_LOCAL			0x1
1047 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT		1
1048 #define I40E_AQC_ADD_PVLAN_TYPE_MASK	(0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1049 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR		0x0
1050 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY		0x2
1051 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY	0x4
1052 #define I40E_AQC_VLAN_PTYPE_SHIFT		3
1053 #define I40E_AQC_VLAN_PTYPE_MASK	(0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1054 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI		0x0
1055 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI		0x8
1056 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI	0x10
1057 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI	0x18
1058 /* flags for remove VLAN */
1059 #define I40E_AQC_REMOVE_VLAN_ALL	0x1
1060 	u8	reserved;
1061 	u8	result;
1062 /* flags for add VLAN */
1063 #define I40E_AQC_ADD_VLAN_SUCCESS	0x0
1064 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST	0xFE
1065 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE	0xFF
1066 /* flags for remove VLAN */
1067 #define I40E_AQC_REMOVE_VLAN_SUCCESS	0x0
1068 #define I40E_AQC_REMOVE_VLAN_FAIL	0xFF
1069 	u8	reserved1[3];
1070 };
1071 
1072 struct i40e_aqc_add_remove_vlan_completion {
1073 	u8	reserved[4];
1074 	__le16	vlans_used;
1075 	__le16	vlans_free;
1076 	__le32	addr_high;
1077 	__le32	addr_low;
1078 };
1079 
1080 /* Set VSI Promiscuous Modes (direct 0x0254) */
1081 struct i40e_aqc_set_vsi_promiscuous_modes {
1082 	__le16	promiscuous_flags;
1083 	__le16	valid_flags;
1084 /* flags used for both fields above */
1085 #define I40E_AQC_SET_VSI_PROMISC_UNICAST	0x01
1086 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST	0x02
1087 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST	0x04
1088 #define I40E_AQC_SET_VSI_DEFAULT		0x08
1089 #define I40E_AQC_SET_VSI_PROMISC_VLAN		0x10
1090 	__le16	seid;
1091 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK		0x3FF
1092 	__le16	vlan_tag;
1093 #define I40E_AQC_SET_VSI_VLAN_MASK		0x0FFF
1094 #define I40E_AQC_SET_VSI_VLAN_VALID		0x8000
1095 	u8	reserved[8];
1096 };
1097 
1098 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1099 
1100 /* Add S/E-tag command (direct 0x0255)
1101  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1102  */
1103 struct i40e_aqc_add_tag {
1104 	__le16	flags;
1105 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE		0x0001
1106 	__le16	seid;
1107 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT	0
1108 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1109 					I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1110 	__le16	tag;
1111 	__le16	queue_number;
1112 	u8	reserved[8];
1113 };
1114 
1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1116 
1117 struct i40e_aqc_add_remove_tag_completion {
1118 	u8	reserved[12];
1119 	__le16	tags_used;
1120 	__le16	tags_free;
1121 };
1122 
1123 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1124 
1125 /* Remove S/E-tag command (direct 0x0256)
1126  * Uses generic i40e_aqc_add_remove_tag_completion for completion
1127  */
1128 struct i40e_aqc_remove_tag {
1129 	__le16	seid;
1130 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT	0
1131 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1132 					I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1133 	__le16	tag;
1134 	u8	reserved[12];
1135 };
1136 
1137 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1138 
1139 /* Add multicast E-Tag (direct 0x0257)
1140  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1141  * and no external data
1142  */
1143 struct i40e_aqc_add_remove_mcast_etag {
1144 	__le16	pv_seid;
1145 	__le16	etag;
1146 	u8	num_unicast_etags;
1147 	u8	reserved[3];
1148 	__le32	addr_high;          /* address of array of 2-byte s-tags */
1149 	__le32	addr_low;
1150 };
1151 
1152 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1153 
1154 struct i40e_aqc_add_remove_mcast_etag_completion {
1155 	u8	reserved[4];
1156 	__le16	mcast_etags_used;
1157 	__le16	mcast_etags_free;
1158 	__le32	addr_high;
1159 	__le32	addr_low;
1160 
1161 };
1162 
1163 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1164 
1165 /* Update S/E-Tag (direct 0x0259) */
1166 struct i40e_aqc_update_tag {
1167 	__le16	seid;
1168 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT	0
1169 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK	(0x3FF << \
1170 					I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1171 	__le16	old_tag;
1172 	__le16	new_tag;
1173 	u8	reserved[10];
1174 };
1175 
1176 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1177 
1178 struct i40e_aqc_update_tag_completion {
1179 	u8	reserved[12];
1180 	__le16	tags_used;
1181 	__le16	tags_free;
1182 };
1183 
1184 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1185 
1186 /* Add Control Packet filter (direct 0x025A)
1187  * Remove Control Packet filter (direct 0x025B)
1188  * uses the i40e_aqc_add_oveb_cloud,
1189  * and the generic direct completion structure
1190  */
1191 struct i40e_aqc_add_remove_control_packet_filter {
1192 	u8	mac[6];
1193 	__le16	etype;
1194 	__le16	flags;
1195 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC	0x0001
1196 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP		0x0002
1197 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE	0x0004
1198 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX		0x0008
1199 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX		0x0000
1200 	__le16	seid;
1201 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT	0
1202 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK	(0x3FF << \
1203 				I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1204 	__le16	queue;
1205 	u8	reserved[2];
1206 };
1207 
1208 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1209 
1210 struct i40e_aqc_add_remove_control_packet_filter_completion {
1211 	__le16	mac_etype_used;
1212 	__le16	etype_used;
1213 	__le16	mac_etype_free;
1214 	__le16	etype_free;
1215 	u8	reserved[8];
1216 };
1217 
1218 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1219 
1220 /* Add Cloud filters (indirect 0x025C)
1221  * Remove Cloud filters (indirect 0x025D)
1222  * uses the i40e_aqc_add_remove_cloud_filters,
1223  * and the generic indirect completion structure
1224  */
1225 struct i40e_aqc_add_remove_cloud_filters {
1226 	u8	num_filters;
1227 	u8	reserved;
1228 	__le16	seid;
1229 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT	0
1230 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK	(0x3FF << \
1231 					I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1232 	u8	reserved2[4];
1233 	__le32	addr_high;
1234 	__le32	addr_low;
1235 };
1236 
1237 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1238 
1239 struct i40e_aqc_add_remove_cloud_filters_element_data {
1240 	u8	outer_mac[6];
1241 	u8	inner_mac[6];
1242 	__le16	inner_vlan;
1243 	union {
1244 		struct {
1245 			u8 reserved[12];
1246 			u8 data[4];
1247 		} v4;
1248 		struct {
1249 			u8 data[16];
1250 		} v6;
1251 	} ipaddr;
1252 	__le16	flags;
1253 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT			0
1254 #define I40E_AQC_ADD_CLOUD_FILTER_MASK	(0x3F << \
1255 					I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1256 /* 0x0000 reserved */
1257 #define I40E_AQC_ADD_CLOUD_FILTER_OIP			0x0001
1258 /* 0x0002 reserved */
1259 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN		0x0003
1260 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID	0x0004
1261 /* 0x0005 reserved */
1262 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID		0x0006
1263 /* 0x0007 reserved */
1264 /* 0x0008 reserved */
1265 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC			0x0009
1266 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC			0x000A
1267 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC	0x000B
1268 #define I40E_AQC_ADD_CLOUD_FILTER_IIP			0x000C
1269 
1270 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE		0x0080
1271 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT			6
1272 #define I40E_AQC_ADD_CLOUD_VNK_MASK			0x00C0
1273 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4			0
1274 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6			0x0100
1275 
1276 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT		9
1277 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK		0x1E00
1278 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN		0
1279 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC		1
1280 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE			2
1281 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP			3
1282 
1283 	__le32	tenant_id;
1284 	u8	reserved[4];
1285 	__le16	queue_number;
1286 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT		0
1287 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK		(0x7FF << \
1288 						 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1289 	u8	reserved2[14];
1290 	/* response section */
1291 	u8	allocation_result;
1292 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS	0x0
1293 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL		0xFF
1294 	u8	response_reserved[7];
1295 };
1296 
1297 struct i40e_aqc_remove_cloud_filters_completion {
1298 	__le16 perfect_ovlan_used;
1299 	__le16 perfect_ovlan_free;
1300 	__le16 vlan_used;
1301 	__le16 vlan_free;
1302 	__le32 addr_high;
1303 	__le32 addr_low;
1304 };
1305 
1306 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1307 
1308 /* Add Mirror Rule (indirect or direct 0x0260)
1309  * Delete Mirror Rule (indirect or direct 0x0261)
1310  * note: some rule types (4,5) do not use an external buffer.
1311  *       take care to set the flags correctly.
1312  */
1313 struct i40e_aqc_add_delete_mirror_rule {
1314 	__le16 seid;
1315 	__le16 rule_type;
1316 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT		0
1317 #define I40E_AQC_MIRROR_RULE_TYPE_MASK		(0x7 << \
1318 						I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1319 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS	1
1320 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS	2
1321 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN		3
1322 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS	4
1323 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS	5
1324 	__le16 num_entries;
1325 	__le16 destination;  /* VSI for add, rule id for delete */
1326 	__le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1327 	__le32 addr_low;
1328 };
1329 
1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1331 
1332 struct i40e_aqc_add_delete_mirror_rule_completion {
1333 	u8	reserved[2];
1334 	__le16	rule_id;  /* only used on add */
1335 	__le16	mirror_rules_used;
1336 	__le16	mirror_rules_free;
1337 	__le32	addr_high;
1338 	__le32	addr_low;
1339 };
1340 
1341 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1342 
1343 /* DCB 0x03xx*/
1344 
1345 /* PFC Ignore (direct 0x0301)
1346  *    the command and response use the same descriptor structure
1347  */
1348 struct i40e_aqc_pfc_ignore {
1349 	u8	tc_bitmap;
1350 	u8	command_flags; /* unused on response */
1351 #define I40E_AQC_PFC_IGNORE_SET		0x80
1352 #define I40E_AQC_PFC_IGNORE_CLEAR	0x0
1353 	u8	reserved[14];
1354 };
1355 
1356 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1357 
1358 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1359  * with no parameters
1360  */
1361 
1362 /* TX scheduler 0x04xx */
1363 
1364 /* Almost all the indirect commands use
1365  * this generic struct to pass the SEID in param0
1366  */
1367 struct i40e_aqc_tx_sched_ind {
1368 	__le16	vsi_seid;
1369 	u8	reserved[6];
1370 	__le32	addr_high;
1371 	__le32	addr_low;
1372 };
1373 
1374 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1375 
1376 /* Several commands respond with a set of queue set handles */
1377 struct i40e_aqc_qs_handles_resp {
1378 	__le16 qs_handles[8];
1379 };
1380 
1381 /* Configure VSI BW limits (direct 0x0400) */
1382 struct i40e_aqc_configure_vsi_bw_limit {
1383 	__le16	vsi_seid;
1384 	u8	reserved[2];
1385 	__le16	credit;
1386 	u8	reserved1[2];
1387 	u8	max_credit; /* 0-3, limit = 2^max */
1388 	u8	reserved2[7];
1389 };
1390 
1391 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1392 
1393 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1394  *    responds with i40e_aqc_qs_handles_resp
1395  */
1396 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1397 	u8	tc_valid_bits;
1398 	u8	reserved[15];
1399 	__le16	tc_bw_credits[8]; /* FW writesback QS handles here */
1400 
1401 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1402 	__le16	tc_bw_max[2];
1403 	u8	reserved1[28];
1404 };
1405 
1406 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1407 
1408 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1409  *    responds with i40e_aqc_qs_handles_resp
1410  */
1411 struct i40e_aqc_configure_vsi_tc_bw_data {
1412 	u8	tc_valid_bits;
1413 	u8	reserved[3];
1414 	u8	tc_bw_credits[8];
1415 	u8	reserved1[4];
1416 	__le16	qs_handles[8];
1417 };
1418 
1419 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1420 
1421 /* Query vsi bw configuration (indirect 0x0408) */
1422 struct i40e_aqc_query_vsi_bw_config_resp {
1423 	u8	tc_valid_bits;
1424 	u8	tc_suspended_bits;
1425 	u8	reserved[14];
1426 	__le16	qs_handles[8];
1427 	u8	reserved1[4];
1428 	__le16	port_bw_limit;
1429 	u8	reserved2[2];
1430 	u8	max_bw; /* 0-3, limit = 2^max */
1431 	u8	reserved3[23];
1432 };
1433 
1434 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1435 
1436 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1437 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1438 	u8	tc_valid_bits;
1439 	u8	reserved[3];
1440 	u8	share_credits[8];
1441 	__le16	credits[8];
1442 
1443 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1444 	__le16	tc_bw_max[2];
1445 };
1446 
1447 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1448 
1449 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1450 struct i40e_aqc_configure_switching_comp_bw_limit {
1451 	__le16	seid;
1452 	u8	reserved[2];
1453 	__le16	credit;
1454 	u8	reserved1[2];
1455 	u8	max_bw; /* 0-3, limit = 2^max */
1456 	u8	reserved2[7];
1457 };
1458 
1459 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1460 
1461 /* Enable  Physical Port ETS (indirect 0x0413)
1462  * Modify  Physical Port ETS (indirect 0x0414)
1463  * Disable Physical Port ETS (indirect 0x0415)
1464  */
1465 struct i40e_aqc_configure_switching_comp_ets_data {
1466 	u8	reserved[4];
1467 	u8	tc_valid_bits;
1468 	u8	seepage;
1469 #define I40E_AQ_ETS_SEEPAGE_EN_MASK	0x1
1470 	u8	tc_strict_priority_flags;
1471 	u8	reserved1[17];
1472 	u8	tc_bw_share_credits[8];
1473 	u8	reserved2[96];
1474 };
1475 
1476 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1477 
1478 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1479 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1480 	u8	tc_valid_bits;
1481 	u8	reserved[15];
1482 	__le16	tc_bw_credit[8];
1483 
1484 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1485 	__le16	tc_bw_max[2];
1486 	u8	reserved1[28];
1487 };
1488 
1489 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1490 
1491 /* Configure Switching Component Bandwidth Allocation per Tc
1492  * (indirect 0x0417)
1493  */
1494 struct i40e_aqc_configure_switching_comp_bw_config_data {
1495 	u8	tc_valid_bits;
1496 	u8	reserved[2];
1497 	u8	absolute_credits; /* bool */
1498 	u8	tc_bw_share_credits[8];
1499 	u8	reserved1[20];
1500 };
1501 
1502 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1503 
1504 /* Query Switching Component Configuration (indirect 0x0418) */
1505 struct i40e_aqc_query_switching_comp_ets_config_resp {
1506 	u8	tc_valid_bits;
1507 	u8	reserved[35];
1508 	__le16	port_bw_limit;
1509 	u8	reserved1[2];
1510 	u8	tc_bw_max; /* 0-3, limit = 2^max */
1511 	u8	reserved2[23];
1512 };
1513 
1514 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1515 
1516 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1517 struct i40e_aqc_query_port_ets_config_resp {
1518 	u8	reserved[4];
1519 	u8	tc_valid_bits;
1520 	u8	reserved1;
1521 	u8	tc_strict_priority_bits;
1522 	u8	reserved2;
1523 	u8	tc_bw_share_credits[8];
1524 	__le16	tc_bw_limits[8];
1525 
1526 	/* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1527 	__le16	tc_bw_max[2];
1528 	u8	reserved3[32];
1529 };
1530 
1531 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1532 
1533 /* Query Switching Component Bandwidth Allocation per Traffic Type
1534  * (indirect 0x041A)
1535  */
1536 struct i40e_aqc_query_switching_comp_bw_config_resp {
1537 	u8	tc_valid_bits;
1538 	u8	reserved[2];
1539 	u8	absolute_credits_enable; /* bool */
1540 	u8	tc_bw_share_credits[8];
1541 	__le16	tc_bw_limits[8];
1542 
1543 	/* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1544 	__le16	tc_bw_max[2];
1545 };
1546 
1547 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1548 
1549 /* Suspend/resume port TX traffic
1550  * (direct 0x041B and 0x041C) uses the generic SEID struct
1551  */
1552 
1553 /* Configure partition BW
1554  * (indirect 0x041D)
1555  */
1556 struct i40e_aqc_configure_partition_bw_data {
1557 	__le16	pf_valid_bits;
1558 	u8	min_bw[16];      /* guaranteed bandwidth */
1559 	u8	max_bw[16];      /* bandwidth limit */
1560 };
1561 
1562 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1563 
1564 /* Get and set the active HMC resource profile and status.
1565  * (direct 0x0500) and (direct 0x0501)
1566  */
1567 struct i40e_aq_get_set_hmc_resource_profile {
1568 	u8	pm_profile;
1569 	u8	pe_vf_enabled;
1570 	u8	reserved[14];
1571 };
1572 
1573 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1574 
1575 enum i40e_aq_hmc_profile {
1576 	/* I40E_HMC_PROFILE_NO_CHANGE    = 0, reserved */
1577 	I40E_HMC_PROFILE_DEFAULT	= 1,
1578 	I40E_HMC_PROFILE_FAVOR_VF	= 2,
1579 	I40E_HMC_PROFILE_EQUAL		= 3,
1580 };
1581 
1582 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK	0xF
1583 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK	0x3F
1584 
1585 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1586 
1587 /* set in param0 for get phy abilities to report qualified modules */
1588 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES	0x0001
1589 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES	0x0002
1590 
1591 enum i40e_aq_phy_type {
1592 	I40E_PHY_TYPE_SGMII			= 0x0,
1593 	I40E_PHY_TYPE_1000BASE_KX		= 0x1,
1594 	I40E_PHY_TYPE_10GBASE_KX4		= 0x2,
1595 	I40E_PHY_TYPE_10GBASE_KR		= 0x3,
1596 	I40E_PHY_TYPE_40GBASE_KR4		= 0x4,
1597 	I40E_PHY_TYPE_XAUI			= 0x5,
1598 	I40E_PHY_TYPE_XFI			= 0x6,
1599 	I40E_PHY_TYPE_SFI			= 0x7,
1600 	I40E_PHY_TYPE_XLAUI			= 0x8,
1601 	I40E_PHY_TYPE_XLPPI			= 0x9,
1602 	I40E_PHY_TYPE_40GBASE_CR4_CU		= 0xA,
1603 	I40E_PHY_TYPE_10GBASE_CR1_CU		= 0xB,
1604 	I40E_PHY_TYPE_10GBASE_AOC		= 0xC,
1605 	I40E_PHY_TYPE_40GBASE_AOC		= 0xD,
1606 	I40E_PHY_TYPE_100BASE_TX		= 0x11,
1607 	I40E_PHY_TYPE_1000BASE_T		= 0x12,
1608 	I40E_PHY_TYPE_10GBASE_T			= 0x13,
1609 	I40E_PHY_TYPE_10GBASE_SR		= 0x14,
1610 	I40E_PHY_TYPE_10GBASE_LR		= 0x15,
1611 	I40E_PHY_TYPE_10GBASE_SFPP_CU		= 0x16,
1612 	I40E_PHY_TYPE_10GBASE_CR1		= 0x17,
1613 	I40E_PHY_TYPE_40GBASE_CR4		= 0x18,
1614 	I40E_PHY_TYPE_40GBASE_SR4		= 0x19,
1615 	I40E_PHY_TYPE_40GBASE_LR4		= 0x1A,
1616 	I40E_PHY_TYPE_1000BASE_SX		= 0x1B,
1617 	I40E_PHY_TYPE_1000BASE_LX		= 0x1C,
1618 	I40E_PHY_TYPE_1000BASE_T_OPTICAL	= 0x1D,
1619 	I40E_PHY_TYPE_20GBASE_KR2		= 0x1E,
1620 	I40E_PHY_TYPE_MAX
1621 };
1622 
1623 #define I40E_LINK_SPEED_100MB_SHIFT	0x1
1624 #define I40E_LINK_SPEED_1000MB_SHIFT	0x2
1625 #define I40E_LINK_SPEED_10GB_SHIFT	0x3
1626 #define I40E_LINK_SPEED_40GB_SHIFT	0x4
1627 #define I40E_LINK_SPEED_20GB_SHIFT	0x5
1628 
1629 enum i40e_aq_link_speed {
1630 	I40E_LINK_SPEED_UNKNOWN	= 0,
1631 	I40E_LINK_SPEED_100MB	= (1 << I40E_LINK_SPEED_100MB_SHIFT),
1632 	I40E_LINK_SPEED_1GB	= (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1633 	I40E_LINK_SPEED_10GB	= (1 << I40E_LINK_SPEED_10GB_SHIFT),
1634 	I40E_LINK_SPEED_40GB	= (1 << I40E_LINK_SPEED_40GB_SHIFT),
1635 	I40E_LINK_SPEED_20GB	= (1 << I40E_LINK_SPEED_20GB_SHIFT)
1636 };
1637 
1638 struct i40e_aqc_module_desc {
1639 	u8 oui[3];
1640 	u8 reserved1;
1641 	u8 part_number[16];
1642 	u8 revision[4];
1643 	u8 reserved2[8];
1644 };
1645 
1646 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1647 
1648 struct i40e_aq_get_phy_abilities_resp {
1649 	__le32	phy_type;       /* bitmap using the above enum for offsets */
1650 	u8	link_speed;     /* bitmap using the above enum bit patterns */
1651 	u8	abilities;
1652 #define I40E_AQ_PHY_FLAG_PAUSE_TX	0x01
1653 #define I40E_AQ_PHY_FLAG_PAUSE_RX	0x02
1654 #define I40E_AQ_PHY_FLAG_LOW_POWER	0x04
1655 #define I40E_AQ_PHY_LINK_ENABLED	0x08
1656 #define I40E_AQ_PHY_AN_ENABLED		0x10
1657 #define I40E_AQ_PHY_FLAG_MODULE_QUAL	0x20
1658 	__le16	eee_capability;
1659 #define I40E_AQ_EEE_100BASE_TX		0x0002
1660 #define I40E_AQ_EEE_1000BASE_T		0x0004
1661 #define I40E_AQ_EEE_10GBASE_T		0x0008
1662 #define I40E_AQ_EEE_1000BASE_KX		0x0010
1663 #define I40E_AQ_EEE_10GBASE_KX4		0x0020
1664 #define I40E_AQ_EEE_10GBASE_KR		0x0040
1665 	__le32	eeer_val;
1666 	u8	d3_lpan;
1667 #define I40E_AQ_SET_PHY_D3_LPAN_ENA	0x01
1668 	u8	reserved[3];
1669 	u8	phy_id[4];
1670 	u8	module_type[3];
1671 	u8	qualified_module_count;
1672 #define I40E_AQ_PHY_MAX_QMS		16
1673 	struct i40e_aqc_module_desc	qualified_module[I40E_AQ_PHY_MAX_QMS];
1674 };
1675 
1676 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1677 
1678 /* Set PHY Config (direct 0x0601) */
1679 struct i40e_aq_set_phy_config { /* same bits as above in all */
1680 	__le32	phy_type;
1681 	u8	link_speed;
1682 	u8	abilities;
1683 /* bits 0-2 use the values from get_phy_abilities_resp */
1684 #define I40E_AQ_PHY_ENABLE_LINK		0x08
1685 #define I40E_AQ_PHY_ENABLE_AN		0x10
1686 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK	0x20
1687 	__le16	eee_capability;
1688 	__le32	eeer;
1689 	u8	low_power_ctrl;
1690 	u8	reserved[3];
1691 };
1692 
1693 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1694 
1695 /* Set MAC Config command data structure (direct 0x0603) */
1696 struct i40e_aq_set_mac_config {
1697 	__le16	max_frame_size;
1698 	u8	params;
1699 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN		0x04
1700 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK	0x78
1701 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT	3
1702 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE	0x0
1703 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX	0xF
1704 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX	0x9
1705 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX	0x8
1706 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX	0x7
1707 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX	0x6
1708 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX	0x5
1709 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX	0x4
1710 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX	0x3
1711 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX	0x2
1712 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX	0x1
1713 	u8	tx_timer_priority; /* bitmap */
1714 	__le16	tx_timer_value;
1715 	__le16	fc_refresh_threshold;
1716 	u8	reserved[8];
1717 };
1718 
1719 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1720 
1721 /* Restart Auto-Negotiation (direct 0x605) */
1722 struct i40e_aqc_set_link_restart_an {
1723 	u8	command;
1724 #define I40E_AQ_PHY_RESTART_AN	0x02
1725 #define I40E_AQ_PHY_LINK_ENABLE	0x04
1726 	u8	reserved[15];
1727 };
1728 
1729 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1730 
1731 /* Get Link Status cmd & response data structure (direct 0x0607) */
1732 struct i40e_aqc_get_link_status {
1733 	__le16	command_flags; /* only field set on command */
1734 #define I40E_AQ_LSE_MASK		0x3
1735 #define I40E_AQ_LSE_NOP			0x0
1736 #define I40E_AQ_LSE_DISABLE		0x2
1737 #define I40E_AQ_LSE_ENABLE		0x3
1738 /* only response uses this flag */
1739 #define I40E_AQ_LSE_IS_ENABLED		0x1
1740 	u8	phy_type;    /* i40e_aq_phy_type   */
1741 	u8	link_speed;  /* i40e_aq_link_speed */
1742 	u8	link_info;
1743 #define I40E_AQ_LINK_UP			0x01    /* obsolete */
1744 #define I40E_AQ_LINK_UP_FUNCTION	0x01
1745 #define I40E_AQ_LINK_FAULT		0x02
1746 #define I40E_AQ_LINK_FAULT_TX		0x04
1747 #define I40E_AQ_LINK_FAULT_RX		0x08
1748 #define I40E_AQ_LINK_FAULT_REMOTE	0x10
1749 #define I40E_AQ_LINK_UP_PORT		0x20
1750 #define I40E_AQ_MEDIA_AVAILABLE		0x40
1751 #define I40E_AQ_SIGNAL_DETECT		0x80
1752 	u8	an_info;
1753 #define I40E_AQ_AN_COMPLETED		0x01
1754 #define I40E_AQ_LP_AN_ABILITY		0x02
1755 #define I40E_AQ_PD_FAULT		0x04
1756 #define I40E_AQ_FEC_EN			0x08
1757 #define I40E_AQ_PHY_LOW_POWER		0x10
1758 #define I40E_AQ_LINK_PAUSE_TX		0x20
1759 #define I40E_AQ_LINK_PAUSE_RX		0x40
1760 #define I40E_AQ_QUALIFIED_MODULE	0x80
1761 	u8	ext_info;
1762 #define I40E_AQ_LINK_PHY_TEMP_ALARM	0x01
1763 #define I40E_AQ_LINK_XCESSIVE_ERRORS	0x02
1764 #define I40E_AQ_LINK_TX_SHIFT		0x02
1765 #define I40E_AQ_LINK_TX_MASK		(0x03 << I40E_AQ_LINK_TX_SHIFT)
1766 #define I40E_AQ_LINK_TX_ACTIVE		0x00
1767 #define I40E_AQ_LINK_TX_DRAINED		0x01
1768 #define I40E_AQ_LINK_TX_FLUSHED		0x03
1769 #define I40E_AQ_LINK_FORCED_40G		0x10
1770 	u8	loopback; /* use defines from i40e_aqc_set_lb_mode */
1771 	__le16	max_frame_size;
1772 	u8	config;
1773 #define I40E_AQ_CONFIG_CRC_ENA		0x04
1774 #define I40E_AQ_CONFIG_PACING_MASK	0x78
1775 	u8	reserved[5];
1776 };
1777 
1778 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1779 
1780 /* Set event mask command (direct 0x613) */
1781 struct i40e_aqc_set_phy_int_mask {
1782 	u8	reserved[8];
1783 	__le16	event_mask;
1784 #define I40E_AQ_EVENT_LINK_UPDOWN	0x0002
1785 #define I40E_AQ_EVENT_MEDIA_NA		0x0004
1786 #define I40E_AQ_EVENT_LINK_FAULT	0x0008
1787 #define I40E_AQ_EVENT_PHY_TEMP_ALARM	0x0010
1788 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS	0x0020
1789 #define I40E_AQ_EVENT_SIGNAL_DETECT	0x0040
1790 #define I40E_AQ_EVENT_AN_COMPLETED	0x0080
1791 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL	0x0100
1792 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED	0x0200
1793 	u8	reserved1[6];
1794 };
1795 
1796 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1797 
1798 /* Get Local AN advt register (direct 0x0614)
1799  * Set Local AN advt register (direct 0x0615)
1800  * Get Link Partner AN advt register (direct 0x0616)
1801  */
1802 struct i40e_aqc_an_advt_reg {
1803 	__le32	local_an_reg0;
1804 	__le16	local_an_reg1;
1805 	u8	reserved[10];
1806 };
1807 
1808 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1809 
1810 /* Set Loopback mode (0x0618) */
1811 struct i40e_aqc_set_lb_mode {
1812 	__le16	lb_mode;
1813 #define I40E_AQ_LB_PHY_LOCAL	0x01
1814 #define I40E_AQ_LB_PHY_REMOTE	0x02
1815 #define I40E_AQ_LB_MAC_LOCAL	0x04
1816 	u8	reserved[14];
1817 };
1818 
1819 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1820 
1821 /* Set PHY Debug command (0x0622) */
1822 struct i40e_aqc_set_phy_debug {
1823 	u8	command_flags;
1824 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL	0x02
1825 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT	2
1826 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK	(0x03 << \
1827 					I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1828 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE	0x00
1829 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD	0x01
1830 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT	0x02
1831 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW	0x10
1832 	u8	reserved[15];
1833 };
1834 
1835 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1836 
1837 enum i40e_aq_phy_reg_type {
1838 	I40E_AQC_PHY_REG_INTERNAL	= 0x1,
1839 	I40E_AQC_PHY_REG_EXERNAL_BASET	= 0x2,
1840 	I40E_AQC_PHY_REG_EXERNAL_MODULE	= 0x3
1841 };
1842 
1843 /* NVM Read command (indirect 0x0701)
1844  * NVM Erase commands (direct 0x0702)
1845  * NVM Update commands (indirect 0x0703)
1846  */
1847 struct i40e_aqc_nvm_update {
1848 	u8	command_flags;
1849 #define I40E_AQ_NVM_LAST_CMD	0x01
1850 #define I40E_AQ_NVM_FLASH_ONLY	0x80
1851 	u8	module_pointer;
1852 	__le16	length;
1853 	__le32	offset;
1854 	__le32	addr_high;
1855 	__le32	addr_low;
1856 };
1857 
1858 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1859 
1860 /* NVM Config Read (indirect 0x0704) */
1861 struct i40e_aqc_nvm_config_read {
1862 	__le16	cmd_flags;
1863 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK	1
1864 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE		0
1865 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES		1
1866 	__le16	element_count;
1867 	__le16	element_id;     /* Feature/field ID */
1868 	__le16	element_id_msw;	/* MSWord of field ID */
1869 	__le32	address_high;
1870 	__le32	address_low;
1871 };
1872 
1873 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1874 
1875 /* NVM Config Write (indirect 0x0705) */
1876 struct i40e_aqc_nvm_config_write {
1877 	__le16	cmd_flags;
1878 	__le16	element_count;
1879 	u8	reserved[4];
1880 	__le32	address_high;
1881 	__le32	address_low;
1882 };
1883 
1884 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1885 
1886 /* Used for 0x0704 as well as for 0x0705 commands */
1887 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT		1
1888 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK		(1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1889 #define I40E_AQ_ANVM_FEATURE				0
1890 #define I40E_AQ_ANVM_IMMEDIATE_FIELD			(1 << FEATURE_OR_IMMEDIATE_SHIFT)
1891 struct i40e_aqc_nvm_config_data_feature {
1892 	__le16 feature_id;
1893 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY		0x01
1894 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP		0x08
1895 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR		0x10
1896 	__le16 feature_options;
1897 	__le16 feature_selection;
1898 };
1899 
1900 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1901 
1902 struct i40e_aqc_nvm_config_data_immediate_field {
1903 	__le32 field_id;
1904 	__le32 field_value;
1905 	__le16 field_options;
1906 	__le16 reserved;
1907 };
1908 
1909 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1910 
1911 /* OEM Post Update (indirect 0x0720)
1912  * no command data struct used
1913  */
1914  struct i40e_aqc_nvm_oem_post_update {
1915 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA	0x01
1916 	u8 sel_data;
1917 	u8 reserved[7];
1918 };
1919 
1920 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1921 
1922 struct i40e_aqc_nvm_oem_post_update_buffer {
1923 	u8 str_len;
1924 	u8 dev_addr;
1925 	__le16 eeprom_addr;
1926 	u8 data[36];
1927 };
1928 
1929 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1930 
1931 /* Send to PF command (indirect 0x0801) id is only used by PF
1932  * Send to VF command (indirect 0x0802) id is only used by PF
1933  * Send to Peer PF command (indirect 0x0803)
1934  */
1935 struct i40e_aqc_pf_vf_message {
1936 	__le32	id;
1937 	u8	reserved[4];
1938 	__le32	addr_high;
1939 	__le32	addr_low;
1940 };
1941 
1942 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1943 
1944 /* Alternate structure */
1945 
1946 /* Direct write (direct 0x0900)
1947  * Direct read (direct 0x0902)
1948  */
1949 struct i40e_aqc_alternate_write {
1950 	__le32 address0;
1951 	__le32 data0;
1952 	__le32 address1;
1953 	__le32 data1;
1954 };
1955 
1956 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1957 
1958 /* Indirect write (indirect 0x0901)
1959  * Indirect read (indirect 0x0903)
1960  */
1961 
1962 struct i40e_aqc_alternate_ind_write {
1963 	__le32 address;
1964 	__le32 length;
1965 	__le32 addr_high;
1966 	__le32 addr_low;
1967 };
1968 
1969 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1970 
1971 /* Done alternate write (direct 0x0904)
1972  * uses i40e_aq_desc
1973  */
1974 struct i40e_aqc_alternate_write_done {
1975 	__le16	cmd_flags;
1976 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK	1
1977 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY	0
1978 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI	1
1979 #define I40E_AQ_ALTERNATE_RESET_NEEDED		2
1980 	u8	reserved[14];
1981 };
1982 
1983 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1984 
1985 /* Set OEM mode (direct 0x0905) */
1986 struct i40e_aqc_alternate_set_mode {
1987 	__le32	mode;
1988 #define I40E_AQ_ALTERNATE_MODE_NONE	0
1989 #define I40E_AQ_ALTERNATE_MODE_OEM	1
1990 	u8	reserved[12];
1991 };
1992 
1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1994 
1995 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1996 
1997 /* async events 0x10xx */
1998 
1999 /* Lan Queue Overflow Event (direct, 0x1001) */
2000 struct i40e_aqc_lan_overflow {
2001 	__le32	prtdcb_rupto;
2002 	__le32	otx_ctl;
2003 	u8	reserved[8];
2004 };
2005 
2006 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2007 
2008 /* Get LLDP MIB (indirect 0x0A00) */
2009 struct i40e_aqc_lldp_get_mib {
2010 	u8	type;
2011 	u8	reserved1;
2012 #define I40E_AQ_LLDP_MIB_TYPE_MASK		0x3
2013 #define I40E_AQ_LLDP_MIB_LOCAL			0x0
2014 #define I40E_AQ_LLDP_MIB_REMOTE			0x1
2015 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE	0x2
2016 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK		0xC
2017 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT		0x2
2018 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE	0x0
2019 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR	0x1
2020 #define I40E_AQ_LLDP_TX_SHIFT			0x4
2021 #define I40E_AQ_LLDP_TX_MASK			(0x03 << I40E_AQ_LLDP_TX_SHIFT)
2022 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2023 	__le16	local_len;
2024 	__le16	remote_len;
2025 	u8	reserved2[2];
2026 	__le32	addr_high;
2027 	__le32	addr_low;
2028 };
2029 
2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2031 
2032 /* Configure LLDP MIB Change Event (direct 0x0A01)
2033  * also used for the event (with type in the command field)
2034  */
2035 struct i40e_aqc_lldp_update_mib {
2036 	u8	command;
2037 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE	0x0
2038 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE	0x1
2039 	u8	reserved[7];
2040 	__le32	addr_high;
2041 	__le32	addr_low;
2042 };
2043 
2044 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2045 
2046 /* Add LLDP TLV (indirect 0x0A02)
2047  * Delete LLDP TLV (indirect 0x0A04)
2048  */
2049 struct i40e_aqc_lldp_add_tlv {
2050 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2051 	u8	reserved1[1];
2052 	__le16	len;
2053 	u8	reserved2[4];
2054 	__le32	addr_high;
2055 	__le32	addr_low;
2056 };
2057 
2058 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2059 
2060 /* Update LLDP TLV (indirect 0x0A03) */
2061 struct i40e_aqc_lldp_update_tlv {
2062 	u8	type; /* only nearest bridge and non-TPMR from 0x0A00 */
2063 	u8	reserved;
2064 	__le16	old_len;
2065 	__le16	new_offset;
2066 	__le16	new_len;
2067 	__le32	addr_high;
2068 	__le32	addr_low;
2069 };
2070 
2071 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2072 
2073 /* Stop LLDP (direct 0x0A05) */
2074 struct i40e_aqc_lldp_stop {
2075 	u8	command;
2076 #define I40E_AQ_LLDP_AGENT_STOP		0x0
2077 #define I40E_AQ_LLDP_AGENT_SHUTDOWN	0x1
2078 	u8	reserved[15];
2079 };
2080 
2081 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2082 
2083 /* Start LLDP (direct 0x0A06) */
2084 
2085 struct i40e_aqc_lldp_start {
2086 	u8	command;
2087 #define I40E_AQ_LLDP_AGENT_START	0x1
2088 	u8	reserved[15];
2089 };
2090 
2091 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2092 
2093 /* Get CEE DCBX Oper Config (0x0A07)
2094  * uses the generic descriptor struct
2095  * returns below as indirect response
2096  */
2097 
2098 #define I40E_AQC_CEE_APP_FCOE_SHIFT	0x0
2099 #define I40E_AQC_CEE_APP_FCOE_MASK	(0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2100 #define I40E_AQC_CEE_APP_ISCSI_SHIFT	0x3
2101 #define I40E_AQC_CEE_APP_ISCSI_MASK	(0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2102 #define I40E_AQC_CEE_APP_FIP_SHIFT	0x8
2103 #define I40E_AQC_CEE_APP_FIP_MASK	(0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2104 
2105 #define I40E_AQC_CEE_PG_STATUS_SHIFT	0x0
2106 #define I40E_AQC_CEE_PG_STATUS_MASK	(0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2107 #define I40E_AQC_CEE_PFC_STATUS_SHIFT	0x3
2108 #define I40E_AQC_CEE_PFC_STATUS_MASK	(0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2109 #define I40E_AQC_CEE_APP_STATUS_SHIFT	0x8
2110 #define I40E_AQC_CEE_APP_STATUS_MASK	(0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2111 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT	0x8
2112 #define I40E_AQC_CEE_FCOE_STATUS_MASK	(0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2113 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT	0xB
2114 #define I40E_AQC_CEE_ISCSI_STATUS_MASK	(0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2115 #define I40E_AQC_CEE_FIP_STATUS_SHIFT	0x10
2116 #define I40E_AQC_CEE_FIP_STATUS_MASK	(0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2117 
2118 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2119  * word boundary layout issues, which the Linux compilers silently deal
2120  * with by adding padding, making the actual struct larger than designed.
2121  * However, the FW compiler for the NIC is less lenient and complains
2122  * about the struct.  Hence, the struct defined here has an extra byte in
2123  * fields reserved3 and reserved4 to directly acknowledge that padding,
2124  * and the new length is used in the length check macro.
2125  */
2126 struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2127 	u8	reserved1;
2128 	u8	oper_num_tc;
2129 	u8	oper_prio_tc[4];
2130 	u8	reserved2;
2131 	u8	oper_tc_bw[8];
2132 	u8	oper_pfc_en;
2133 	u8	reserved3[2];
2134 	__le16	oper_app_prio;
2135 	u8	reserved4[2];
2136 	__le16	tlv_status;
2137 };
2138 
2139 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2140 
2141 struct i40e_aqc_get_cee_dcb_cfg_resp {
2142 	u8	oper_num_tc;
2143 	u8	oper_prio_tc[4];
2144 	u8	oper_tc_bw[8];
2145 	u8	oper_pfc_en;
2146 	__le16	oper_app_prio;
2147 	__le32	tlv_status;
2148 	u8	reserved[12];
2149 };
2150 
2151 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2152 
2153 /*	Set Local LLDP MIB (indirect 0x0A08)
2154  *	Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2155  */
2156 struct i40e_aqc_lldp_set_local_mib {
2157 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT	0
2158 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK		(1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2159 	u8	type;
2160 	u8	reserved0;
2161 	__le16	length;
2162 	u8	reserved1[4];
2163 	__le32	address_high;
2164 	__le32	address_low;
2165 };
2166 
2167 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib);
2168 
2169 /*	Stop/Start LLDP Agent (direct 0x0A09)
2170  *	Used for stopping/starting specific LLDP agent. e.g. DCBx
2171  */
2172 struct i40e_aqc_lldp_stop_start_specific_agent {
2173 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT	0
2174 #define I40E_AQC_START_SPECIFIC_AGENT_MASK	(1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2175 	u8	command;
2176 	u8	reserved[15];
2177 };
2178 
2179 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent);
2180 
2181 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2182 struct i40e_aqc_add_udp_tunnel {
2183 	__le16	udp_port;
2184 	u8	reserved0[3];
2185 	u8	protocol_type;
2186 #define I40E_AQC_TUNNEL_TYPE_VXLAN	0x00
2187 #define I40E_AQC_TUNNEL_TYPE_NGE	0x01
2188 #define I40E_AQC_TUNNEL_TYPE_TEREDO	0x10
2189 	u8	reserved1[10];
2190 };
2191 
2192 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2193 
2194 struct i40e_aqc_add_udp_tunnel_completion {
2195 	__le16 udp_port;
2196 	u8	filter_entry_index;
2197 	u8	multiple_pfs;
2198 #define I40E_AQC_SINGLE_PF		0x0
2199 #define I40E_AQC_MULTIPLE_PFS		0x1
2200 	u8	total_filters;
2201 	u8	reserved[11];
2202 };
2203 
2204 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2205 
2206 /* remove UDP Tunnel command (0x0B01) */
2207 struct i40e_aqc_remove_udp_tunnel {
2208 	u8	reserved[2];
2209 	u8	index; /* 0 to 15 */
2210 	u8	reserved2[13];
2211 };
2212 
2213 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2214 
2215 struct i40e_aqc_del_udp_tunnel_completion {
2216 	__le16	udp_port;
2217 	u8	index; /* 0 to 15 */
2218 	u8	multiple_pfs;
2219 	u8	total_filters_used;
2220 	u8	reserved1[11];
2221 };
2222 
2223 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2224 #ifdef X722_SUPPORT
2225 
2226 struct i40e_aqc_get_set_rss_key {
2227 #define I40E_AQC_SET_RSS_KEY_VSI_VALID		(0x1 << 15)
2228 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT	0
2229 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK	(0x3FF << \
2230 					I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2231 	__le16	vsi_id;
2232 	u8	reserved[6];
2233 	__le32	addr_high;
2234 	__le32	addr_low;
2235 };
2236 
2237 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2238 
2239 struct i40e_aqc_get_set_rss_key_data {
2240 	u8 standard_rss_key[0x28];
2241 	u8 extended_hash_key[0xc];
2242 };
2243 
2244 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2245 
2246 struct  i40e_aqc_get_set_rss_lut {
2247 #define I40E_AQC_SET_RSS_LUT_VSI_VALID		(0x1 << 15)
2248 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT	0
2249 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK	(0x3FF << \
2250 					I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2251 	__le16	vsi_id;
2252 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT	0
2253 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK	(0x1 << \
2254 					I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2255 
2256 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI	0
2257 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF	1
2258 	__le16	flags;
2259 	u8	reserved[4];
2260 	__le32	addr_high;
2261 	__le32	addr_low;
2262 };
2263 
2264 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2265 #endif
2266 
2267 /* tunnel key structure 0x0B10 */
2268 
2269 struct i40e_aqc_tunnel_key_structure {
2270 	u8	key1_off;
2271 	u8	key2_off;
2272 	u8	key1_len;  /* 0 to 15 */
2273 	u8	key2_len;  /* 0 to 15 */
2274 	u8	flags;
2275 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE	0x01
2276 /* response flags */
2277 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS	0x01
2278 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED	0x02
2279 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN	0x03
2280 	u8	network_key_index;
2281 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN		0x0
2282 #define I40E_AQC_NETWORK_KEY_INDEX_NGE			0x1
2283 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP	0x2
2284 #define I40E_AQC_NETWORK_KEY_INDEX_GRE			0x3
2285 	u8	reserved[10];
2286 };
2287 
2288 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2289 
2290 /* OEM mode commands (direct 0xFE0x) */
2291 struct i40e_aqc_oem_param_change {
2292 	__le32	param_type;
2293 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL	0
2294 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL	1
2295 #define I40E_AQ_OEM_PARAM_MAC		2
2296 	__le32	param_value1;
2297 	__le16	param_value2;
2298 	u8	reserved[6];
2299 };
2300 
2301 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2302 
2303 struct i40e_aqc_oem_state_change {
2304 	__le32	state;
2305 #define I40E_AQ_OEM_STATE_LINK_DOWN	0x0
2306 #define I40E_AQ_OEM_STATE_LINK_UP	0x1
2307 	u8	reserved[12];
2308 };
2309 
2310 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2311 
2312 /* Initialize OCSD (0xFE02, direct) */
2313 struct i40e_aqc_opc_oem_ocsd_initialize {
2314 	u8 type_status;
2315 	u8 reserved1[3];
2316 	__le32 ocsd_memory_block_addr_high;
2317 	__le32 ocsd_memory_block_addr_low;
2318 	__le32 requested_update_interval;
2319 };
2320 
2321 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2322 
2323 /* Initialize OCBB  (0xFE03, direct) */
2324 struct i40e_aqc_opc_oem_ocbb_initialize {
2325 	u8 type_status;
2326 	u8 reserved1[3];
2327 	__le32 ocbb_memory_block_addr_high;
2328 	__le32 ocbb_memory_block_addr_low;
2329 	u8 reserved2[4];
2330 };
2331 
2332 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2333 
2334 /* debug commands */
2335 
2336 /* get device id (0xFF00) uses the generic structure */
2337 
2338 /* set test more (0xFF01, internal) */
2339 
2340 struct i40e_acq_set_test_mode {
2341 	u8	mode;
2342 #define I40E_AQ_TEST_PARTIAL	0
2343 #define I40E_AQ_TEST_FULL	1
2344 #define I40E_AQ_TEST_NVM	2
2345 	u8	reserved[3];
2346 	u8	command;
2347 #define I40E_AQ_TEST_OPEN	0
2348 #define I40E_AQ_TEST_CLOSE	1
2349 #define I40E_AQ_TEST_INC	2
2350 	u8	reserved2[3];
2351 	__le32	address_high;
2352 	__le32	address_low;
2353 };
2354 
2355 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2356 
2357 /* Debug Read Register command (0xFF03)
2358  * Debug Write Register command (0xFF04)
2359  */
2360 struct i40e_aqc_debug_reg_read_write {
2361 	__le32 reserved;
2362 	__le32 address;
2363 	__le32 value_high;
2364 	__le32 value_low;
2365 };
2366 
2367 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2368 
2369 /* Scatter/gather Reg Read  (indirect 0xFF05)
2370  * Scatter/gather Reg Write (indirect 0xFF06)
2371  */
2372 
2373 /* i40e_aq_desc is used for the command */
2374 struct i40e_aqc_debug_reg_sg_element_data {
2375 	__le32 address;
2376 	__le32 value;
2377 };
2378 
2379 /* Debug Modify register (direct 0xFF07) */
2380 struct i40e_aqc_debug_modify_reg {
2381 	__le32 address;
2382 	__le32 value;
2383 	__le32 clear_mask;
2384 	__le32 set_mask;
2385 };
2386 
2387 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2388 
2389 /* dump internal data (0xFF08, indirect) */
2390 
2391 #define I40E_AQ_CLUSTER_ID_AUX		0
2392 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU	1
2393 #define I40E_AQ_CLUSTER_ID_TXSCHED	2
2394 #define I40E_AQ_CLUSTER_ID_HMC		3
2395 #define I40E_AQ_CLUSTER_ID_MAC0		4
2396 #define I40E_AQ_CLUSTER_ID_MAC1		5
2397 #define I40E_AQ_CLUSTER_ID_MAC2		6
2398 #define I40E_AQ_CLUSTER_ID_MAC3		7
2399 #define I40E_AQ_CLUSTER_ID_DCB		8
2400 #define I40E_AQ_CLUSTER_ID_EMP_MEM	9
2401 #define I40E_AQ_CLUSTER_ID_PKT_BUF	10
2402 #define I40E_AQ_CLUSTER_ID_ALTRAM	11
2403 
2404 struct i40e_aqc_debug_dump_internals {
2405 	u8	cluster_id;
2406 	u8	table_id;
2407 	__le16	data_size;
2408 	__le32	idx;
2409 	__le32	address_high;
2410 	__le32	address_low;
2411 };
2412 
2413 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2414 
2415 struct i40e_aqc_debug_modify_internals {
2416 	u8	cluster_id;
2417 	u8	cluster_specific_params[7];
2418 	__le32	address_high;
2419 	__le32	address_low;
2420 };
2421 
2422 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2423 
2424 #endif
2425