1 /****************************************************************************** 2 3 Copyright (c) 2013-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _I40E_ADMINQ_CMD_H_ 36 #define _I40E_ADMINQ_CMD_H_ 37 38 /* This header file defines the i40e Admin Queue commands and is shared between 39 * i40e Firmware and Software. 40 * 41 * This file needs to comply with the Linux Kernel coding style. 42 */ 43 44 45 #define I40E_FW_API_VERSION_MAJOR 0x0001 46 #define I40E_FW_API_VERSION_MINOR_X722 0x0005 47 #define I40E_FW_API_VERSION_MINOR_X710 0x0007 48 49 #define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \ 50 I40E_FW_API_VERSION_MINOR_X710 : \ 51 I40E_FW_API_VERSION_MINOR_X722) 52 53 /* API version 1.7 implements additional link and PHY-specific APIs */ 54 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007 55 56 struct i40e_aq_desc { 57 __le16 flags; 58 __le16 opcode; 59 __le16 datalen; 60 __le16 retval; 61 __le32 cookie_high; 62 __le32 cookie_low; 63 union { 64 struct { 65 __le32 param0; 66 __le32 param1; 67 __le32 param2; 68 __le32 param3; 69 } internal; 70 struct { 71 __le32 param0; 72 __le32 param1; 73 __le32 addr_high; 74 __le32 addr_low; 75 } external; 76 u8 raw[16]; 77 } params; 78 }; 79 80 /* Flags sub-structure 81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 82 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 83 */ 84 85 /* command flags and offsets*/ 86 #define I40E_AQ_FLAG_DD_SHIFT 0 87 #define I40E_AQ_FLAG_CMP_SHIFT 1 88 #define I40E_AQ_FLAG_ERR_SHIFT 2 89 #define I40E_AQ_FLAG_VFE_SHIFT 3 90 #define I40E_AQ_FLAG_LB_SHIFT 9 91 #define I40E_AQ_FLAG_RD_SHIFT 10 92 #define I40E_AQ_FLAG_VFC_SHIFT 11 93 #define I40E_AQ_FLAG_BUF_SHIFT 12 94 #define I40E_AQ_FLAG_SI_SHIFT 13 95 #define I40E_AQ_FLAG_EI_SHIFT 14 96 #define I40E_AQ_FLAG_FE_SHIFT 15 97 98 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 99 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 100 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 101 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 102 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 103 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 104 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 105 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 106 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 107 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 108 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 109 110 /* error codes */ 111 enum i40e_admin_queue_err { 112 I40E_AQ_RC_OK = 0, /* success */ 113 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 114 I40E_AQ_RC_ENOENT = 2, /* No such element */ 115 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 116 I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 117 I40E_AQ_RC_EIO = 5, /* I/O error */ 118 I40E_AQ_RC_ENXIO = 6, /* No such resource */ 119 I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 120 I40E_AQ_RC_EAGAIN = 8, /* Try again */ 121 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 122 I40E_AQ_RC_EACCES = 10, /* Permission denied */ 123 I40E_AQ_RC_EFAULT = 11, /* Bad address */ 124 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 125 I40E_AQ_RC_EEXIST = 13, /* object already exists */ 126 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 127 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 128 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 129 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 130 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 131 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 132 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 133 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 134 I40E_AQ_RC_EFBIG = 22, /* File too large */ 135 }; 136 137 /* Admin Queue command opcodes */ 138 enum i40e_admin_queue_opc { 139 /* aq commands */ 140 i40e_aqc_opc_get_version = 0x0001, 141 i40e_aqc_opc_driver_version = 0x0002, 142 i40e_aqc_opc_queue_shutdown = 0x0003, 143 i40e_aqc_opc_set_pf_context = 0x0004, 144 145 /* resource ownership */ 146 i40e_aqc_opc_request_resource = 0x0008, 147 i40e_aqc_opc_release_resource = 0x0009, 148 149 i40e_aqc_opc_list_func_capabilities = 0x000A, 150 i40e_aqc_opc_list_dev_capabilities = 0x000B, 151 152 /* Proxy commands */ 153 i40e_aqc_opc_set_proxy_config = 0x0104, 154 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105, 155 156 /* LAA */ 157 i40e_aqc_opc_mac_address_read = 0x0107, 158 i40e_aqc_opc_mac_address_write = 0x0108, 159 160 /* PXE */ 161 i40e_aqc_opc_clear_pxe_mode = 0x0110, 162 163 /* WoL commands */ 164 i40e_aqc_opc_set_wol_filter = 0x0120, 165 i40e_aqc_opc_get_wake_reason = 0x0121, 166 167 /* internal switch commands */ 168 i40e_aqc_opc_get_switch_config = 0x0200, 169 i40e_aqc_opc_add_statistics = 0x0201, 170 i40e_aqc_opc_remove_statistics = 0x0202, 171 i40e_aqc_opc_set_port_parameters = 0x0203, 172 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 173 i40e_aqc_opc_set_switch_config = 0x0205, 174 i40e_aqc_opc_rx_ctl_reg_read = 0x0206, 175 i40e_aqc_opc_rx_ctl_reg_write = 0x0207, 176 177 i40e_aqc_opc_add_vsi = 0x0210, 178 i40e_aqc_opc_update_vsi_parameters = 0x0211, 179 i40e_aqc_opc_get_vsi_parameters = 0x0212, 180 181 i40e_aqc_opc_add_pv = 0x0220, 182 i40e_aqc_opc_update_pv_parameters = 0x0221, 183 i40e_aqc_opc_get_pv_parameters = 0x0222, 184 185 i40e_aqc_opc_add_veb = 0x0230, 186 i40e_aqc_opc_update_veb_parameters = 0x0231, 187 i40e_aqc_opc_get_veb_parameters = 0x0232, 188 189 i40e_aqc_opc_delete_element = 0x0243, 190 191 i40e_aqc_opc_add_macvlan = 0x0250, 192 i40e_aqc_opc_remove_macvlan = 0x0251, 193 i40e_aqc_opc_add_vlan = 0x0252, 194 i40e_aqc_opc_remove_vlan = 0x0253, 195 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 196 i40e_aqc_opc_add_tag = 0x0255, 197 i40e_aqc_opc_remove_tag = 0x0256, 198 i40e_aqc_opc_add_multicast_etag = 0x0257, 199 i40e_aqc_opc_remove_multicast_etag = 0x0258, 200 i40e_aqc_opc_update_tag = 0x0259, 201 i40e_aqc_opc_add_control_packet_filter = 0x025A, 202 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 203 i40e_aqc_opc_add_cloud_filters = 0x025C, 204 i40e_aqc_opc_remove_cloud_filters = 0x025D, 205 i40e_aqc_opc_clear_wol_switch_filters = 0x025E, 206 207 i40e_aqc_opc_add_mirror_rule = 0x0260, 208 i40e_aqc_opc_delete_mirror_rule = 0x0261, 209 210 /* DCB commands */ 211 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 212 i40e_aqc_opc_dcb_updated = 0x0302, 213 i40e_aqc_opc_set_dcb_parameters = 0x0303, 214 215 /* TX scheduler */ 216 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 217 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 218 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 219 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 220 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 221 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 222 223 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 224 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 225 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 226 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 227 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 228 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 229 i40e_aqc_opc_query_port_ets_config = 0x0419, 230 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 231 i40e_aqc_opc_suspend_port_tx = 0x041B, 232 i40e_aqc_opc_resume_port_tx = 0x041C, 233 i40e_aqc_opc_configure_partition_bw = 0x041D, 234 /* hmc */ 235 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 236 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 237 238 /* phy commands*/ 239 240 /* phy commands*/ 241 i40e_aqc_opc_get_phy_abilities = 0x0600, 242 i40e_aqc_opc_set_phy_config = 0x0601, 243 i40e_aqc_opc_set_mac_config = 0x0603, 244 i40e_aqc_opc_set_link_restart_an = 0x0605, 245 i40e_aqc_opc_get_link_status = 0x0607, 246 i40e_aqc_opc_set_phy_int_mask = 0x0613, 247 i40e_aqc_opc_get_local_advt_reg = 0x0614, 248 i40e_aqc_opc_set_local_advt_reg = 0x0615, 249 i40e_aqc_opc_get_partner_advt = 0x0616, 250 i40e_aqc_opc_set_lb_modes = 0x0618, 251 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 252 i40e_aqc_opc_set_phy_debug = 0x0622, 253 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 254 i40e_aqc_opc_run_phy_activity = 0x0626, 255 i40e_aqc_opc_set_phy_register = 0x0628, 256 i40e_aqc_opc_get_phy_register = 0x0629, 257 258 /* NVM commands */ 259 i40e_aqc_opc_nvm_read = 0x0701, 260 i40e_aqc_opc_nvm_erase = 0x0702, 261 i40e_aqc_opc_nvm_update = 0x0703, 262 i40e_aqc_opc_nvm_config_read = 0x0704, 263 i40e_aqc_opc_nvm_config_write = 0x0705, 264 i40e_aqc_opc_nvm_progress = 0x0706, 265 i40e_aqc_opc_oem_post_update = 0x0720, 266 i40e_aqc_opc_thermal_sensor = 0x0721, 267 268 /* virtualization commands */ 269 i40e_aqc_opc_send_msg_to_pf = 0x0801, 270 i40e_aqc_opc_send_msg_to_vf = 0x0802, 271 i40e_aqc_opc_send_msg_to_peer = 0x0803, 272 273 /* alternate structure */ 274 i40e_aqc_opc_alternate_write = 0x0900, 275 i40e_aqc_opc_alternate_write_indirect = 0x0901, 276 i40e_aqc_opc_alternate_read = 0x0902, 277 i40e_aqc_opc_alternate_read_indirect = 0x0903, 278 i40e_aqc_opc_alternate_write_done = 0x0904, 279 i40e_aqc_opc_alternate_set_mode = 0x0905, 280 i40e_aqc_opc_alternate_clear_port = 0x0906, 281 282 /* LLDP commands */ 283 i40e_aqc_opc_lldp_get_mib = 0x0A00, 284 i40e_aqc_opc_lldp_update_mib = 0x0A01, 285 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 286 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 287 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 288 i40e_aqc_opc_lldp_stop = 0x0A05, 289 i40e_aqc_opc_lldp_start = 0x0A06, 290 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 291 i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 292 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 293 294 /* Tunnel commands */ 295 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 296 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 297 i40e_aqc_opc_set_rss_key = 0x0B02, 298 i40e_aqc_opc_set_rss_lut = 0x0B03, 299 i40e_aqc_opc_get_rss_key = 0x0B04, 300 i40e_aqc_opc_get_rss_lut = 0x0B05, 301 302 /* Async Events */ 303 i40e_aqc_opc_event_lan_overflow = 0x1001, 304 305 /* OEM commands */ 306 i40e_aqc_opc_oem_parameter_change = 0xFE00, 307 i40e_aqc_opc_oem_device_status_change = 0xFE01, 308 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 309 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 310 311 /* debug commands */ 312 i40e_aqc_opc_debug_read_reg = 0xFF03, 313 i40e_aqc_opc_debug_write_reg = 0xFF04, 314 i40e_aqc_opc_debug_modify_reg = 0xFF07, 315 i40e_aqc_opc_debug_dump_internals = 0xFF08, 316 }; 317 318 /* command structures and indirect data structures */ 319 320 /* Structure naming conventions: 321 * - no suffix for direct command descriptor structures 322 * - _data for indirect sent data 323 * - _resp for indirect return data (data which is both will use _data) 324 * - _completion for direct return data 325 * - _element_ for repeated elements (may also be _data or _resp) 326 * 327 * Command structures are expected to overlay the params.raw member of the basic 328 * descriptor, and as such cannot exceed 16 bytes in length. 329 */ 330 331 /* This macro is used to generate a compilation error if a structure 332 * is not exactly the correct length. It gives a divide by zero error if the 333 * structure is not of the correct size, otherwise it creates an enum that is 334 * never used. 335 */ 336 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 337 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 338 339 /* This macro is used extensively to ensure that command structures are 16 340 * bytes in length as they have to map to the raw array of that size. 341 */ 342 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 343 344 /* internal (0x00XX) commands */ 345 346 /* Get version (direct 0x0001) */ 347 struct i40e_aqc_get_version { 348 __le32 rom_ver; 349 __le32 fw_build; 350 __le16 fw_major; 351 __le16 fw_minor; 352 __le16 api_major; 353 __le16 api_minor; 354 }; 355 356 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 357 358 /* Send driver version (indirect 0x0002) */ 359 struct i40e_aqc_driver_version { 360 u8 driver_major_ver; 361 u8 driver_minor_ver; 362 u8 driver_build_ver; 363 u8 driver_subbuild_ver; 364 u8 reserved[4]; 365 __le32 address_high; 366 __le32 address_low; 367 }; 368 369 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 370 371 /* Queue Shutdown (direct 0x0003) */ 372 struct i40e_aqc_queue_shutdown { 373 __le32 driver_unloading; 374 #define I40E_AQ_DRIVER_UNLOADING 0x1 375 u8 reserved[12]; 376 }; 377 378 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 379 380 /* Set PF context (0x0004, direct) */ 381 struct i40e_aqc_set_pf_context { 382 u8 pf_id; 383 u8 reserved[15]; 384 }; 385 386 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 387 388 /* Request resource ownership (direct 0x0008) 389 * Release resource ownership (direct 0x0009) 390 */ 391 #define I40E_AQ_RESOURCE_NVM 1 392 #define I40E_AQ_RESOURCE_SDP 2 393 #define I40E_AQ_RESOURCE_ACCESS_READ 1 394 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2 395 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 396 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 397 398 struct i40e_aqc_request_resource { 399 __le16 resource_id; 400 __le16 access_type; 401 __le32 timeout; 402 __le32 resource_number; 403 u8 reserved[4]; 404 }; 405 406 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 407 408 /* Get function capabilities (indirect 0x000A) 409 * Get device capabilities (indirect 0x000B) 410 */ 411 struct i40e_aqc_list_capabilites { 412 u8 command_flags; 413 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 414 u8 pf_index; 415 u8 reserved[2]; 416 __le32 count; 417 __le32 addr_high; 418 __le32 addr_low; 419 }; 420 421 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 422 423 struct i40e_aqc_list_capabilities_element_resp { 424 __le16 id; 425 u8 major_rev; 426 u8 minor_rev; 427 __le32 number; 428 __le32 logical_id; 429 __le32 phys_id; 430 u8 reserved[16]; 431 }; 432 433 /* list of caps */ 434 435 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 436 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002 437 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 438 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 439 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 440 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 441 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 442 #define I40E_AQ_CAP_ID_SRIOV 0x0012 443 #define I40E_AQ_CAP_ID_VF 0x0013 444 #define I40E_AQ_CAP_ID_VMDQ 0x0014 445 #define I40E_AQ_CAP_ID_8021QBG 0x0015 446 #define I40E_AQ_CAP_ID_8021QBR 0x0016 447 #define I40E_AQ_CAP_ID_VSI 0x0017 448 #define I40E_AQ_CAP_ID_DCB 0x0018 449 #define I40E_AQ_CAP_ID_FCOE 0x0021 450 #define I40E_AQ_CAP_ID_ISCSI 0x0022 451 #define I40E_AQ_CAP_ID_RSS 0x0040 452 #define I40E_AQ_CAP_ID_RXQ 0x0041 453 #define I40E_AQ_CAP_ID_TXQ 0x0042 454 #define I40E_AQ_CAP_ID_MSIX 0x0043 455 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044 456 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 457 #define I40E_AQ_CAP_ID_1588 0x0046 458 #define I40E_AQ_CAP_ID_IWARP 0x0051 459 #define I40E_AQ_CAP_ID_LED 0x0061 460 #define I40E_AQ_CAP_ID_SDP 0x0062 461 #define I40E_AQ_CAP_ID_MDIO 0x0063 462 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064 463 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 464 #define I40E_AQ_CAP_ID_FLEX10 0x00F1 465 #define I40E_AQ_CAP_ID_CEM 0x00F2 466 467 /* Set CPPM Configuration (direct 0x0103) */ 468 struct i40e_aqc_cppm_configuration { 469 __le16 command_flags; 470 #define I40E_AQ_CPPM_EN_LTRC 0x0800 471 #define I40E_AQ_CPPM_EN_DMCTH 0x1000 472 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000 473 #define I40E_AQ_CPPM_EN_HPTC 0x4000 474 #define I40E_AQ_CPPM_EN_DMARC 0x8000 475 __le16 ttlx; 476 __le32 dmacr; 477 __le16 dmcth; 478 u8 hptc; 479 u8 reserved; 480 __le32 pfltrc; 481 }; 482 483 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 484 485 /* Set ARP Proxy command / response (indirect 0x0104) */ 486 struct i40e_aqc_arp_proxy_data { 487 __le16 command_flags; 488 #define I40E_AQ_ARP_INIT_IPV4 0x0800 489 #define I40E_AQ_ARP_UNSUP_CTL 0x1000 490 #define I40E_AQ_ARP_ENA 0x2000 491 #define I40E_AQ_ARP_ADD_IPV4 0x4000 492 #define I40E_AQ_ARP_DEL_IPV4 0x8000 493 __le16 table_id; 494 __le32 enabled_offloads; 495 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 496 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 497 __le32 ip_addr; 498 u8 mac_addr[6]; 499 u8 reserved[2]; 500 }; 501 502 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 503 504 /* Set NS Proxy Table Entry Command (indirect 0x0105) */ 505 struct i40e_aqc_ns_proxy_data { 506 __le16 table_idx_mac_addr_0; 507 __le16 table_idx_mac_addr_1; 508 __le16 table_idx_ipv6_0; 509 __le16 table_idx_ipv6_1; 510 __le16 control; 511 #define I40E_AQ_NS_PROXY_ADD_0 0x0001 512 #define I40E_AQ_NS_PROXY_DEL_0 0x0002 513 #define I40E_AQ_NS_PROXY_ADD_1 0x0004 514 #define I40E_AQ_NS_PROXY_DEL_1 0x0008 515 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 516 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 517 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 518 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 519 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 520 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 521 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 522 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 523 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 524 u8 mac_addr_0[6]; 525 u8 mac_addr_1[6]; 526 u8 local_mac_addr[6]; 527 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 528 u8 ipv6_addr_1[16]; 529 }; 530 531 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 532 533 /* Manage LAA Command (0x0106) - obsolete */ 534 struct i40e_aqc_mng_laa { 535 __le16 command_flags; 536 #define I40E_AQ_LAA_FLAG_WR 0x8000 537 u8 reserved[2]; 538 __le32 sal; 539 __le16 sah; 540 u8 reserved2[6]; 541 }; 542 543 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 544 545 /* Manage MAC Address Read Command (indirect 0x0107) */ 546 struct i40e_aqc_mac_address_read { 547 __le16 command_flags; 548 #define I40E_AQC_LAN_ADDR_VALID 0x10 549 #define I40E_AQC_SAN_ADDR_VALID 0x20 550 #define I40E_AQC_PORT_ADDR_VALID 0x40 551 #define I40E_AQC_WOL_ADDR_VALID 0x80 552 #define I40E_AQC_MC_MAG_EN_VALID 0x100 553 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200 554 #define I40E_AQC_ADDR_VALID_MASK 0x3F0 555 u8 reserved[6]; 556 __le32 addr_high; 557 __le32 addr_low; 558 }; 559 560 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 561 562 struct i40e_aqc_mac_address_read_data { 563 u8 pf_lan_mac[6]; 564 u8 pf_san_mac[6]; 565 u8 port_mac[6]; 566 u8 pf_wol_mac[6]; 567 }; 568 569 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 570 571 /* Manage MAC Address Write Command (0x0108) */ 572 struct i40e_aqc_mac_address_write { 573 __le16 command_flags; 574 #define I40E_AQC_MC_MAG_EN 0x0100 575 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200 576 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 577 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 578 #define I40E_AQC_WRITE_TYPE_PORT 0x8000 579 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 580 #define I40E_AQC_WRITE_TYPE_MASK 0xC000 581 582 __le16 mac_sah; 583 __le32 mac_sal; 584 u8 reserved[8]; 585 }; 586 587 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 588 589 /* PXE commands (0x011x) */ 590 591 /* Clear PXE Command and response (direct 0x0110) */ 592 struct i40e_aqc_clear_pxe { 593 u8 rx_cnt; 594 u8 reserved[15]; 595 }; 596 597 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 598 599 /* Set WoL Filter (0x0120) */ 600 601 struct i40e_aqc_set_wol_filter { 602 __le16 filter_index; 603 #define I40E_AQC_MAX_NUM_WOL_FILTERS 8 604 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 605 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ 606 I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) 607 608 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 609 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ 610 I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) 611 __le16 cmd_flags; 612 #define I40E_AQC_SET_WOL_FILTER 0x8000 613 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 614 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 615 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 616 #define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 617 __le16 valid_flags; 618 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 619 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 620 u8 reserved[2]; 621 __le32 address_high; 622 __le32 address_low; 623 }; 624 625 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); 626 627 struct i40e_aqc_set_wol_filter_data { 628 u8 filter[128]; 629 u8 mask[16]; 630 }; 631 632 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); 633 634 /* Get Wake Reason (0x0121) */ 635 636 struct i40e_aqc_get_wake_reason_completion { 637 u8 reserved_1[2]; 638 __le16 wake_reason; 639 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 640 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ 641 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) 642 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 643 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ 644 I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) 645 u8 reserved_2[12]; 646 }; 647 648 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); 649 650 /* Switch configuration commands (0x02xx) */ 651 652 /* Used by many indirect commands that only pass an seid and a buffer in the 653 * command 654 */ 655 struct i40e_aqc_switch_seid { 656 __le16 seid; 657 u8 reserved[6]; 658 __le32 addr_high; 659 __le32 addr_low; 660 }; 661 662 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 663 664 /* Get Switch Configuration command (indirect 0x0200) 665 * uses i40e_aqc_switch_seid for the descriptor 666 */ 667 struct i40e_aqc_get_switch_config_header_resp { 668 __le16 num_reported; 669 __le16 num_total; 670 u8 reserved[12]; 671 }; 672 673 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 674 675 struct i40e_aqc_switch_config_element_resp { 676 u8 element_type; 677 #define I40E_AQ_SW_ELEM_TYPE_MAC 1 678 #define I40E_AQ_SW_ELEM_TYPE_PF 2 679 #define I40E_AQ_SW_ELEM_TYPE_VF 3 680 #define I40E_AQ_SW_ELEM_TYPE_EMP 4 681 #define I40E_AQ_SW_ELEM_TYPE_BMC 5 682 #define I40E_AQ_SW_ELEM_TYPE_PV 16 683 #define I40E_AQ_SW_ELEM_TYPE_VEB 17 684 #define I40E_AQ_SW_ELEM_TYPE_PA 18 685 #define I40E_AQ_SW_ELEM_TYPE_VSI 19 686 u8 revision; 687 #define I40E_AQ_SW_ELEM_REV_1 1 688 __le16 seid; 689 __le16 uplink_seid; 690 __le16 downlink_seid; 691 u8 reserved[3]; 692 u8 connection_type; 693 #define I40E_AQ_CONN_TYPE_REGULAR 0x1 694 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2 695 #define I40E_AQ_CONN_TYPE_CASCADED 0x3 696 __le16 scheduler_id; 697 __le16 element_info; 698 }; 699 700 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 701 702 /* Get Switch Configuration (indirect 0x0200) 703 * an array of elements are returned in the response buffer 704 * the first in the array is the header, remainder are elements 705 */ 706 struct i40e_aqc_get_switch_config_resp { 707 struct i40e_aqc_get_switch_config_header_resp header; 708 struct i40e_aqc_switch_config_element_resp element[1]; 709 }; 710 711 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 712 713 /* Add Statistics (direct 0x0201) 714 * Remove Statistics (direct 0x0202) 715 */ 716 struct i40e_aqc_add_remove_statistics { 717 __le16 seid; 718 __le16 vlan; 719 __le16 stat_index; 720 u8 reserved[10]; 721 }; 722 723 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 724 725 /* Set Port Parameters command (direct 0x0203) */ 726 struct i40e_aqc_set_port_parameters { 727 __le16 command_flags; 728 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 729 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 730 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 731 __le16 bad_frame_vsi; 732 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 733 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF 734 __le16 default_seid; /* reserved for command */ 735 u8 reserved[10]; 736 }; 737 738 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 739 740 /* Get Switch Resource Allocation (indirect 0x0204) */ 741 struct i40e_aqc_get_switch_resource_alloc { 742 u8 num_entries; /* reserved for command */ 743 u8 reserved[7]; 744 __le32 addr_high; 745 __le32 addr_low; 746 }; 747 748 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 749 750 /* expect an array of these structs in the response buffer */ 751 struct i40e_aqc_switch_resource_alloc_element_resp { 752 u8 resource_type; 753 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0 754 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1 755 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 756 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3 757 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 758 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 759 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 760 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 761 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 762 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 763 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 764 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 765 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 766 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 767 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 768 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 769 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 770 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 771 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 772 u8 reserved1; 773 __le16 guaranteed; 774 __le16 total; 775 __le16 used; 776 __le16 total_unalloced; 777 u8 reserved2[6]; 778 }; 779 780 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 781 782 /* Set Switch Configuration (direct 0x0205) */ 783 struct i40e_aqc_set_switch_config { 784 __le16 flags; 785 /* flags used for both fields below */ 786 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 787 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 788 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 789 __le16 valid_flags; 790 /* The ethertype in switch_tag is dropped on ingress and used 791 * internally by the switch. Set this to zero for the default 792 * of 0x88a8 (802.1ad). Should be zero for firmware API 793 * versions lower than 1.7. 794 */ 795 __le16 switch_tag; 796 /* The ethertypes in first_tag and second_tag are used to 797 * match the outer and inner VLAN tags (respectively) when HW 798 * double VLAN tagging is enabled via the set port parameters 799 * AQ command. Otherwise these are both ignored. Set them to 800 * zero for their defaults of 0x8100 (802.1Q). Should be zero 801 * for firmware API versions lower than 1.7. 802 */ 803 __le16 first_tag; 804 __le16 second_tag; 805 /* Next byte is split into following: 806 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0 807 * Bit 6 : 0 : Destination Port, 1: source port 808 * Bit 5..4 : L4 type 809 * 0: rsvd 810 * 1: TCP 811 * 2: UDP 812 * 3: Both TCP and UDP 813 * Bits 3:0 Mode 814 * 0: default mode 815 * 1: L4 port only mode 816 * 2: non-tunneled mode 817 * 3: tunneled mode 818 */ 819 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80 820 821 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40 822 823 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00 824 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10 825 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20 826 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30 827 828 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00 829 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01 830 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02 831 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03 832 u8 mode; 833 u8 rsvd5[5]; 834 }; 835 836 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); 837 838 /* Read Receive control registers (direct 0x0206) 839 * Write Receive control registers (direct 0x0207) 840 * used for accessing Rx control registers that can be 841 * slow and need special handling when under high Rx load 842 */ 843 struct i40e_aqc_rx_ctl_reg_read_write { 844 __le32 reserved1; 845 __le32 address; 846 __le32 reserved2; 847 __le32 value; 848 }; 849 850 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); 851 852 /* Add VSI (indirect 0x0210) 853 * this indirect command uses struct i40e_aqc_vsi_properties_data 854 * as the indirect buffer (128 bytes) 855 * 856 * Update VSI (indirect 0x211) 857 * uses the same data structure as Add VSI 858 * 859 * Get VSI (indirect 0x0212) 860 * uses the same completion and data structure as Add VSI 861 */ 862 struct i40e_aqc_add_get_update_vsi { 863 __le16 uplink_seid; 864 u8 connection_type; 865 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 866 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 867 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 868 u8 reserved1; 869 u8 vf_id; 870 u8 reserved2; 871 __le16 vsi_flags; 872 #define I40E_AQ_VSI_TYPE_SHIFT 0x0 873 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 874 #define I40E_AQ_VSI_TYPE_VF 0x0 875 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1 876 #define I40E_AQ_VSI_TYPE_PF 0x2 877 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 878 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 879 __le32 addr_high; 880 __le32 addr_low; 881 }; 882 883 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 884 885 struct i40e_aqc_add_get_update_vsi_completion { 886 __le16 seid; 887 __le16 vsi_number; 888 __le16 vsi_used; 889 __le16 vsi_free; 890 __le32 addr_high; 891 __le32 addr_low; 892 }; 893 894 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 895 896 struct i40e_aqc_vsi_properties_data { 897 /* first 96 byte are written by SW */ 898 __le16 valid_sections; 899 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 900 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 901 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 902 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 903 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 904 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 905 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 906 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 907 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 908 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 909 /* switch section */ 910 __le16 switch_id; /* 12bit id combined with flags below */ 911 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 912 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 913 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 914 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 915 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 916 u8 sw_reserved[2]; 917 /* security section */ 918 u8 sec_flags; 919 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 920 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 921 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 922 u8 sec_reserved; 923 /* VLAN section */ 924 __le16 pvid; /* VLANS include priority bits */ 925 __le16 fcoe_pvid; 926 u8 port_vlan_flags; 927 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 928 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 929 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 930 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 931 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 932 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 933 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 934 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 935 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 936 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 937 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 938 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 939 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 940 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 941 u8 pvlan_reserved[3]; 942 /* ingress egress up sections */ 943 __le32 ingress_table; /* bitmap, 3 bits per up */ 944 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 945 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 946 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 947 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 948 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 949 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 950 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 951 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 952 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 953 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 954 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 955 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 956 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 957 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 958 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 959 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 960 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 961 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 962 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 963 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 964 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 965 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 966 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 967 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 968 __le32 egress_table; /* same defines as for ingress table */ 969 /* cascaded PV section */ 970 __le16 cas_pv_tag; 971 u8 cas_pv_flags; 972 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 973 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 974 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 975 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 976 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 977 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 978 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 979 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 980 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 981 u8 cas_pv_reserved; 982 /* queue mapping section */ 983 __le16 mapping_flags; 984 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 985 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 986 __le16 queue_mapping[16]; 987 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0 988 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 989 __le16 tc_mapping[8]; 990 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 991 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 992 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 993 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 994 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 995 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 996 /* queueing option section */ 997 u8 queueing_opt_flags; 998 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 999 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 1000 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 1001 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 1002 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 1003 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 1004 u8 queueing_opt_reserved[3]; 1005 /* scheduler section */ 1006 u8 up_enable_bits; 1007 u8 sched_reserved; 1008 /* outer up section */ 1009 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 1010 u8 cmd_reserved[8]; 1011 /* last 32 bytes are written by FW */ 1012 __le16 qs_handle[8]; 1013 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 1014 __le16 stat_counter_idx; 1015 __le16 sched_id; 1016 u8 resp_reserved[12]; 1017 }; 1018 1019 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 1020 1021 /* Add Port Virtualizer (direct 0x0220) 1022 * also used for update PV (direct 0x0221) but only flags are used 1023 * (IS_CTRL_PORT only works on add PV) 1024 */ 1025 struct i40e_aqc_add_update_pv { 1026 __le16 command_flags; 1027 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1 1028 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 1029 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 1030 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 1031 __le16 uplink_seid; 1032 __le16 connected_seid; 1033 u8 reserved[10]; 1034 }; 1035 1036 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 1037 1038 struct i40e_aqc_add_update_pv_completion { 1039 /* reserved for update; for add also encodes error if rc == ENOSPC */ 1040 __le16 pv_seid; 1041 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 1042 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 1043 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 1044 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 1045 u8 reserved[14]; 1046 }; 1047 1048 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 1049 1050 /* Get PV Params (direct 0x0222) 1051 * uses i40e_aqc_switch_seid for the descriptor 1052 */ 1053 1054 struct i40e_aqc_get_pv_params_completion { 1055 __le16 seid; 1056 __le16 default_stag; 1057 __le16 pv_flags; /* same flags as add_pv */ 1058 #define I40E_AQC_GET_PV_PV_TYPE 0x1 1059 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 1060 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 1061 u8 reserved[8]; 1062 __le16 default_port_seid; 1063 }; 1064 1065 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 1066 1067 /* Add VEB (direct 0x0230) */ 1068 struct i40e_aqc_add_veb { 1069 __le16 uplink_seid; 1070 __le16 downlink_seid; 1071 __le16 veb_flags; 1072 #define I40E_AQC_ADD_VEB_FLOATING 0x1 1073 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 1074 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 1075 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 1076 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 1077 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 1078 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ 1079 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 1080 u8 enable_tcs; 1081 u8 reserved[9]; 1082 }; 1083 1084 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 1085 1086 struct i40e_aqc_add_veb_completion { 1087 u8 reserved[6]; 1088 __le16 switch_seid; 1089 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 1090 __le16 veb_seid; 1091 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 1092 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 1093 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 1094 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 1095 __le16 statistic_index; 1096 __le16 vebs_used; 1097 __le16 vebs_free; 1098 }; 1099 1100 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 1101 1102 /* Get VEB Parameters (direct 0x0232) 1103 * uses i40e_aqc_switch_seid for the descriptor 1104 */ 1105 struct i40e_aqc_get_veb_parameters_completion { 1106 __le16 seid; 1107 __le16 switch_id; 1108 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 1109 __le16 statistic_index; 1110 __le16 vebs_used; 1111 __le16 vebs_free; 1112 u8 reserved[4]; 1113 }; 1114 1115 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 1116 1117 /* Delete Element (direct 0x0243) 1118 * uses the generic i40e_aqc_switch_seid 1119 */ 1120 1121 /* Add MAC-VLAN (indirect 0x0250) */ 1122 1123 /* used for the command for most vlan commands */ 1124 struct i40e_aqc_macvlan { 1125 __le16 num_addresses; 1126 __le16 seid[3]; 1127 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 1128 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 1129 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1130 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 1131 __le32 addr_high; 1132 __le32 addr_low; 1133 }; 1134 1135 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 1136 1137 /* indirect data for command and response */ 1138 struct i40e_aqc_add_macvlan_element_data { 1139 u8 mac_addr[6]; 1140 __le16 vlan_tag; 1141 __le16 flags; 1142 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 1143 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 1144 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 1145 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 1146 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 1147 __le16 queue_number; 1148 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 1149 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 1150 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 1151 /* response section */ 1152 u8 match_method; 1153 #define I40E_AQC_MM_PERFECT_MATCH 0x01 1154 #define I40E_AQC_MM_HASH_MATCH 0x02 1155 #define I40E_AQC_MM_ERR_NO_RES 0xFF 1156 u8 reserved1[3]; 1157 }; 1158 1159 struct i40e_aqc_add_remove_macvlan_completion { 1160 __le16 perfect_mac_used; 1161 __le16 perfect_mac_free; 1162 __le16 unicast_hash_free; 1163 __le16 multicast_hash_free; 1164 __le32 addr_high; 1165 __le32 addr_low; 1166 }; 1167 1168 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1169 1170 /* Remove MAC-VLAN (indirect 0x0251) 1171 * uses i40e_aqc_macvlan for the descriptor 1172 * data points to an array of num_addresses of elements 1173 */ 1174 1175 struct i40e_aqc_remove_macvlan_element_data { 1176 u8 mac_addr[6]; 1177 __le16 vlan_tag; 1178 u8 flags; 1179 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1180 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1181 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1182 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1183 u8 reserved[3]; 1184 /* reply section */ 1185 u8 error_code; 1186 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1187 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1188 u8 reply_reserved[3]; 1189 }; 1190 1191 /* Add VLAN (indirect 0x0252) 1192 * Remove VLAN (indirect 0x0253) 1193 * use the generic i40e_aqc_macvlan for the command 1194 */ 1195 struct i40e_aqc_add_remove_vlan_element_data { 1196 __le16 vlan_tag; 1197 u8 vlan_flags; 1198 /* flags for add VLAN */ 1199 #define I40E_AQC_ADD_VLAN_LOCAL 0x1 1200 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1201 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1202 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1203 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1204 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1205 #define I40E_AQC_VLAN_PTYPE_SHIFT 3 1206 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1207 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1208 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1209 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1210 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1211 /* flags for remove VLAN */ 1212 #define I40E_AQC_REMOVE_VLAN_ALL 0x1 1213 u8 reserved; 1214 u8 result; 1215 /* flags for add VLAN */ 1216 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1217 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1218 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1219 /* flags for remove VLAN */ 1220 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1221 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1222 u8 reserved1[3]; 1223 }; 1224 1225 struct i40e_aqc_add_remove_vlan_completion { 1226 u8 reserved[4]; 1227 __le16 vlans_used; 1228 __le16 vlans_free; 1229 __le32 addr_high; 1230 __le32 addr_low; 1231 }; 1232 1233 /* Set VSI Promiscuous Modes (direct 0x0254) */ 1234 struct i40e_aqc_set_vsi_promiscuous_modes { 1235 __le16 promiscuous_flags; 1236 __le16 valid_flags; 1237 /* flags used for both fields above */ 1238 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1239 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1240 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1241 #define I40E_AQC_SET_VSI_DEFAULT 0x08 1242 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1243 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 1244 __le16 seid; 1245 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1246 __le16 vlan_tag; 1247 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1248 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1249 u8 reserved[8]; 1250 }; 1251 1252 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1253 1254 /* Add S/E-tag command (direct 0x0255) 1255 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1256 */ 1257 struct i40e_aqc_add_tag { 1258 __le16 flags; 1259 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1260 __le16 seid; 1261 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1262 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1263 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1264 __le16 tag; 1265 __le16 queue_number; 1266 u8 reserved[8]; 1267 }; 1268 1269 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1270 1271 struct i40e_aqc_add_remove_tag_completion { 1272 u8 reserved[12]; 1273 __le16 tags_used; 1274 __le16 tags_free; 1275 }; 1276 1277 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1278 1279 /* Remove S/E-tag command (direct 0x0256) 1280 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1281 */ 1282 struct i40e_aqc_remove_tag { 1283 __le16 seid; 1284 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1285 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1286 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1287 __le16 tag; 1288 u8 reserved[12]; 1289 }; 1290 1291 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1292 1293 /* Add multicast E-Tag (direct 0x0257) 1294 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1295 * and no external data 1296 */ 1297 struct i40e_aqc_add_remove_mcast_etag { 1298 __le16 pv_seid; 1299 __le16 etag; 1300 u8 num_unicast_etags; 1301 u8 reserved[3]; 1302 __le32 addr_high; /* address of array of 2-byte s-tags */ 1303 __le32 addr_low; 1304 }; 1305 1306 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1307 1308 struct i40e_aqc_add_remove_mcast_etag_completion { 1309 u8 reserved[4]; 1310 __le16 mcast_etags_used; 1311 __le16 mcast_etags_free; 1312 __le32 addr_high; 1313 __le32 addr_low; 1314 1315 }; 1316 1317 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1318 1319 /* Update S/E-Tag (direct 0x0259) */ 1320 struct i40e_aqc_update_tag { 1321 __le16 seid; 1322 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1323 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1324 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1325 __le16 old_tag; 1326 __le16 new_tag; 1327 u8 reserved[10]; 1328 }; 1329 1330 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1331 1332 struct i40e_aqc_update_tag_completion { 1333 u8 reserved[12]; 1334 __le16 tags_used; 1335 __le16 tags_free; 1336 }; 1337 1338 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1339 1340 /* Add Control Packet filter (direct 0x025A) 1341 * Remove Control Packet filter (direct 0x025B) 1342 * uses the i40e_aqc_add_oveb_cloud, 1343 * and the generic direct completion structure 1344 */ 1345 struct i40e_aqc_add_remove_control_packet_filter { 1346 u8 mac[6]; 1347 __le16 etype; 1348 __le16 flags; 1349 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1350 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1351 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1352 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1353 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1354 __le16 seid; 1355 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1356 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1357 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1358 __le16 queue; 1359 u8 reserved[2]; 1360 }; 1361 1362 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1363 1364 struct i40e_aqc_add_remove_control_packet_filter_completion { 1365 __le16 mac_etype_used; 1366 __le16 etype_used; 1367 __le16 mac_etype_free; 1368 __le16 etype_free; 1369 u8 reserved[8]; 1370 }; 1371 1372 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1373 1374 /* Add Cloud filters (indirect 0x025C) 1375 * Remove Cloud filters (indirect 0x025D) 1376 * uses the i40e_aqc_add_remove_cloud_filters, 1377 * and the generic indirect completion structure 1378 */ 1379 struct i40e_aqc_add_remove_cloud_filters { 1380 u8 num_filters; 1381 u8 reserved; 1382 __le16 seid; 1383 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1384 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1385 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1386 u8 reserved2[4]; 1387 __le32 addr_high; 1388 __le32 addr_low; 1389 }; 1390 1391 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1392 1393 struct i40e_aqc_add_remove_cloud_filters_element_data { 1394 u8 outer_mac[6]; 1395 u8 inner_mac[6]; 1396 __le16 inner_vlan; 1397 union { 1398 struct { 1399 u8 reserved[12]; 1400 u8 data[4]; 1401 } v4; 1402 struct { 1403 u8 data[16]; 1404 } v6; 1405 } ipaddr; 1406 __le16 flags; 1407 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1408 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1409 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1410 /* 0x0000 reserved */ 1411 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1412 /* 0x0002 reserved */ 1413 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1414 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1415 /* 0x0005 reserved */ 1416 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1417 /* 0x0007 reserved */ 1418 /* 0x0008 reserved */ 1419 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1420 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1421 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1422 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1423 1424 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1425 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1426 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1427 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1428 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1429 1430 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1431 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1432 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 1433 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1434 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 1435 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1436 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 1437 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 1438 1439 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 1440 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 1441 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 1442 1443 __le32 tenant_id; 1444 u8 reserved[4]; 1445 __le16 queue_number; 1446 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1447 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1448 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1449 u8 reserved2[14]; 1450 /* response section */ 1451 u8 allocation_result; 1452 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1453 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1454 u8 response_reserved[7]; 1455 }; 1456 1457 struct i40e_aqc_remove_cloud_filters_completion { 1458 __le16 perfect_ovlan_used; 1459 __le16 perfect_ovlan_free; 1460 __le16 vlan_used; 1461 __le16 vlan_free; 1462 __le32 addr_high; 1463 __le32 addr_low; 1464 }; 1465 1466 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1467 1468 /* Add Mirror Rule (indirect or direct 0x0260) 1469 * Delete Mirror Rule (indirect or direct 0x0261) 1470 * note: some rule types (4,5) do not use an external buffer. 1471 * take care to set the flags correctly. 1472 */ 1473 struct i40e_aqc_add_delete_mirror_rule { 1474 __le16 seid; 1475 __le16 rule_type; 1476 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1477 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1478 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1479 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1480 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1481 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1482 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1483 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1484 __le16 num_entries; 1485 __le16 destination; /* VSI for add, rule id for delete */ 1486 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1487 __le32 addr_low; 1488 }; 1489 1490 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1491 1492 struct i40e_aqc_add_delete_mirror_rule_completion { 1493 u8 reserved[2]; 1494 __le16 rule_id; /* only used on add */ 1495 __le16 mirror_rules_used; 1496 __le16 mirror_rules_free; 1497 __le32 addr_high; 1498 __le32 addr_low; 1499 }; 1500 1501 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1502 1503 /* DCB 0x03xx*/ 1504 1505 /* PFC Ignore (direct 0x0301) 1506 * the command and response use the same descriptor structure 1507 */ 1508 struct i40e_aqc_pfc_ignore { 1509 u8 tc_bitmap; 1510 u8 command_flags; /* unused on response */ 1511 #define I40E_AQC_PFC_IGNORE_SET 0x80 1512 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1513 u8 reserved[14]; 1514 }; 1515 1516 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1517 1518 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1519 * with no parameters 1520 */ 1521 1522 /* TX scheduler 0x04xx */ 1523 1524 /* Almost all the indirect commands use 1525 * this generic struct to pass the SEID in param0 1526 */ 1527 struct i40e_aqc_tx_sched_ind { 1528 __le16 vsi_seid; 1529 u8 reserved[6]; 1530 __le32 addr_high; 1531 __le32 addr_low; 1532 }; 1533 1534 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1535 1536 /* Several commands respond with a set of queue set handles */ 1537 struct i40e_aqc_qs_handles_resp { 1538 __le16 qs_handles[8]; 1539 }; 1540 1541 /* Configure VSI BW limits (direct 0x0400) */ 1542 struct i40e_aqc_configure_vsi_bw_limit { 1543 __le16 vsi_seid; 1544 u8 reserved[2]; 1545 __le16 credit; 1546 u8 reserved1[2]; 1547 u8 max_credit; /* 0-3, limit = 2^max */ 1548 u8 reserved2[7]; 1549 }; 1550 1551 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1552 1553 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1554 * responds with i40e_aqc_qs_handles_resp 1555 */ 1556 struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1557 u8 tc_valid_bits; 1558 u8 reserved[15]; 1559 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1560 1561 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1562 __le16 tc_bw_max[2]; 1563 u8 reserved1[28]; 1564 }; 1565 1566 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1567 1568 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1569 * responds with i40e_aqc_qs_handles_resp 1570 */ 1571 struct i40e_aqc_configure_vsi_tc_bw_data { 1572 u8 tc_valid_bits; 1573 u8 reserved[3]; 1574 u8 tc_bw_credits[8]; 1575 u8 reserved1[4]; 1576 __le16 qs_handles[8]; 1577 }; 1578 1579 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1580 1581 /* Query vsi bw configuration (indirect 0x0408) */ 1582 struct i40e_aqc_query_vsi_bw_config_resp { 1583 u8 tc_valid_bits; 1584 u8 tc_suspended_bits; 1585 u8 reserved[14]; 1586 __le16 qs_handles[8]; 1587 u8 reserved1[4]; 1588 __le16 port_bw_limit; 1589 u8 reserved2[2]; 1590 u8 max_bw; /* 0-3, limit = 2^max */ 1591 u8 reserved3[23]; 1592 }; 1593 1594 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1595 1596 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1597 struct i40e_aqc_query_vsi_ets_sla_config_resp { 1598 u8 tc_valid_bits; 1599 u8 reserved[3]; 1600 u8 share_credits[8]; 1601 __le16 credits[8]; 1602 1603 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1604 __le16 tc_bw_max[2]; 1605 }; 1606 1607 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1608 1609 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1610 struct i40e_aqc_configure_switching_comp_bw_limit { 1611 __le16 seid; 1612 u8 reserved[2]; 1613 __le16 credit; 1614 u8 reserved1[2]; 1615 u8 max_bw; /* 0-3, limit = 2^max */ 1616 u8 reserved2[7]; 1617 }; 1618 1619 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1620 1621 /* Enable Physical Port ETS (indirect 0x0413) 1622 * Modify Physical Port ETS (indirect 0x0414) 1623 * Disable Physical Port ETS (indirect 0x0415) 1624 */ 1625 struct i40e_aqc_configure_switching_comp_ets_data { 1626 u8 reserved[4]; 1627 u8 tc_valid_bits; 1628 u8 seepage; 1629 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1630 u8 tc_strict_priority_flags; 1631 u8 reserved1[17]; 1632 u8 tc_bw_share_credits[8]; 1633 u8 reserved2[96]; 1634 }; 1635 1636 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1637 1638 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1639 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1640 u8 tc_valid_bits; 1641 u8 reserved[15]; 1642 __le16 tc_bw_credit[8]; 1643 1644 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1645 __le16 tc_bw_max[2]; 1646 u8 reserved1[28]; 1647 }; 1648 1649 I40E_CHECK_STRUCT_LEN(0x40, 1650 i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1651 1652 /* Configure Switching Component Bandwidth Allocation per Tc 1653 * (indirect 0x0417) 1654 */ 1655 struct i40e_aqc_configure_switching_comp_bw_config_data { 1656 u8 tc_valid_bits; 1657 u8 reserved[2]; 1658 u8 absolute_credits; /* bool */ 1659 u8 tc_bw_share_credits[8]; 1660 u8 reserved1[20]; 1661 }; 1662 1663 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1664 1665 /* Query Switching Component Configuration (indirect 0x0418) */ 1666 struct i40e_aqc_query_switching_comp_ets_config_resp { 1667 u8 tc_valid_bits; 1668 u8 reserved[35]; 1669 __le16 port_bw_limit; 1670 u8 reserved1[2]; 1671 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1672 u8 reserved2[23]; 1673 }; 1674 1675 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1676 1677 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1678 struct i40e_aqc_query_port_ets_config_resp { 1679 u8 reserved[4]; 1680 u8 tc_valid_bits; 1681 u8 reserved1; 1682 u8 tc_strict_priority_bits; 1683 u8 reserved2; 1684 u8 tc_bw_share_credits[8]; 1685 __le16 tc_bw_limits[8]; 1686 1687 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1688 __le16 tc_bw_max[2]; 1689 u8 reserved3[32]; 1690 }; 1691 1692 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1693 1694 /* Query Switching Component Bandwidth Allocation per Traffic Type 1695 * (indirect 0x041A) 1696 */ 1697 struct i40e_aqc_query_switching_comp_bw_config_resp { 1698 u8 tc_valid_bits; 1699 u8 reserved[2]; 1700 u8 absolute_credits_enable; /* bool */ 1701 u8 tc_bw_share_credits[8]; 1702 __le16 tc_bw_limits[8]; 1703 1704 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1705 __le16 tc_bw_max[2]; 1706 }; 1707 1708 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1709 1710 /* Suspend/resume port TX traffic 1711 * (direct 0x041B and 0x041C) uses the generic SEID struct 1712 */ 1713 1714 /* Configure partition BW 1715 * (indirect 0x041D) 1716 */ 1717 struct i40e_aqc_configure_partition_bw_data { 1718 __le16 pf_valid_bits; 1719 u8 min_bw[16]; /* guaranteed bandwidth */ 1720 u8 max_bw[16]; /* bandwidth limit */ 1721 }; 1722 1723 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1724 1725 /* Get and set the active HMC resource profile and status. 1726 * (direct 0x0500) and (direct 0x0501) 1727 */ 1728 struct i40e_aq_get_set_hmc_resource_profile { 1729 u8 pm_profile; 1730 u8 pe_vf_enabled; 1731 u8 reserved[14]; 1732 }; 1733 1734 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1735 1736 enum i40e_aq_hmc_profile { 1737 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1738 I40E_HMC_PROFILE_DEFAULT = 1, 1739 I40E_HMC_PROFILE_FAVOR_VF = 2, 1740 I40E_HMC_PROFILE_EQUAL = 3, 1741 }; 1742 1743 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1744 1745 /* set in param0 for get phy abilities to report qualified modules */ 1746 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1747 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1748 1749 enum i40e_aq_phy_type { 1750 I40E_PHY_TYPE_SGMII = 0x0, 1751 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1752 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1753 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1754 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1755 I40E_PHY_TYPE_XAUI = 0x5, 1756 I40E_PHY_TYPE_XFI = 0x6, 1757 I40E_PHY_TYPE_SFI = 0x7, 1758 I40E_PHY_TYPE_XLAUI = 0x8, 1759 I40E_PHY_TYPE_XLPPI = 0x9, 1760 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1761 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1762 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1763 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1764 I40E_PHY_TYPE_UNRECOGNIZED = 0xE, 1765 I40E_PHY_TYPE_UNSUPPORTED = 0xF, 1766 I40E_PHY_TYPE_100BASE_TX = 0x11, 1767 I40E_PHY_TYPE_1000BASE_T = 0x12, 1768 I40E_PHY_TYPE_10GBASE_T = 0x13, 1769 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1770 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1771 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1772 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1773 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1774 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1775 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1776 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1777 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1778 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1779 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1780 I40E_PHY_TYPE_25GBASE_KR = 0x1F, 1781 I40E_PHY_TYPE_25GBASE_CR = 0x20, 1782 I40E_PHY_TYPE_25GBASE_SR = 0x21, 1783 I40E_PHY_TYPE_25GBASE_LR = 0x22, 1784 I40E_PHY_TYPE_25GBASE_AOC = 0x23, 1785 I40E_PHY_TYPE_25GBASE_ACC = 0x24, 1786 I40E_PHY_TYPE_MAX, 1787 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, 1788 I40E_PHY_TYPE_EMPTY = 0xFE, 1789 I40E_PHY_TYPE_DEFAULT = 0xFF, 1790 }; 1791 1792 #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \ 1793 BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \ 1794 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \ 1795 BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \ 1796 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \ 1797 BIT_ULL(I40E_PHY_TYPE_XAUI) | \ 1798 BIT_ULL(I40E_PHY_TYPE_XFI) | \ 1799 BIT_ULL(I40E_PHY_TYPE_SFI) | \ 1800 BIT_ULL(I40E_PHY_TYPE_XLAUI) | \ 1801 BIT_ULL(I40E_PHY_TYPE_XLPPI) | \ 1802 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \ 1803 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \ 1804 BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \ 1805 BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ 1806 BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ 1807 BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ 1808 BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ 1809 BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ 1810 BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ 1811 BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \ 1812 BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \ 1813 BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \ 1814 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \ 1815 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \ 1816 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \ 1817 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \ 1818 BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \ 1819 BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \ 1820 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \ 1821 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \ 1822 BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \ 1823 BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \ 1824 BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \ 1825 BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \ 1826 BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \ 1827 BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC)) 1828 1829 #define I40E_LINK_SPEED_100MB_SHIFT 0x1 1830 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1831 #define I40E_LINK_SPEED_10GB_SHIFT 0x3 1832 #define I40E_LINK_SPEED_40GB_SHIFT 0x4 1833 #define I40E_LINK_SPEED_20GB_SHIFT 0x5 1834 #define I40E_LINK_SPEED_25GB_SHIFT 0x6 1835 1836 enum i40e_aq_link_speed { 1837 I40E_LINK_SPEED_UNKNOWN = 0, 1838 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1839 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1840 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1841 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1842 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT), 1843 I40E_LINK_SPEED_25GB = (1 << I40E_LINK_SPEED_25GB_SHIFT), 1844 }; 1845 1846 struct i40e_aqc_module_desc { 1847 u8 oui[3]; 1848 u8 reserved1; 1849 u8 part_number[16]; 1850 u8 revision[4]; 1851 u8 reserved2[8]; 1852 }; 1853 1854 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1855 1856 struct i40e_aq_get_phy_abilities_resp { 1857 __le32 phy_type; /* bitmap using the above enum for offsets */ 1858 u8 link_speed; /* bitmap using the above enum bit patterns */ 1859 u8 abilities; 1860 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1861 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1862 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1863 #define I40E_AQ_PHY_LINK_ENABLED 0x08 1864 #define I40E_AQ_PHY_AN_ENABLED 0x10 1865 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1866 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 1867 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 1868 __le16 eee_capability; 1869 #define I40E_AQ_EEE_100BASE_TX 0x0002 1870 #define I40E_AQ_EEE_1000BASE_T 0x0004 1871 #define I40E_AQ_EEE_10GBASE_T 0x0008 1872 #define I40E_AQ_EEE_1000BASE_KX 0x0010 1873 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 1874 #define I40E_AQ_EEE_10GBASE_KR 0x0040 1875 __le32 eeer_val; 1876 u8 d3_lpan; 1877 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1878 u8 phy_type_ext; 1879 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01 1880 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02 1881 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 1882 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 1883 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 1884 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 1885 u8 fec_cfg_curr_mod_ext_info; 1886 #define I40E_AQ_ENABLE_FEC_KR 0x01 1887 #define I40E_AQ_ENABLE_FEC_RS 0x02 1888 #define I40E_AQ_REQUEST_FEC_KR 0x04 1889 #define I40E_AQ_REQUEST_FEC_RS 0x08 1890 #define I40E_AQ_ENABLE_FEC_AUTO 0x10 1891 #define I40E_AQ_FEC 1892 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 1893 #define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 1894 1895 u8 ext_comp_code; 1896 u8 phy_id[4]; 1897 u8 module_type[3]; 1898 u8 qualified_module_count; 1899 #define I40E_AQ_PHY_MAX_QMS 16 1900 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1901 }; 1902 1903 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1904 1905 /* Set PHY Config (direct 0x0601) */ 1906 struct i40e_aq_set_phy_config { /* same bits as above in all */ 1907 __le32 phy_type; 1908 u8 link_speed; 1909 u8 abilities; 1910 /* bits 0-2 use the values from get_phy_abilities_resp */ 1911 #define I40E_AQ_PHY_ENABLE_LINK 0x08 1912 #define I40E_AQ_PHY_ENABLE_AN 0x10 1913 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1914 __le16 eee_capability; 1915 __le32 eeer; 1916 u8 low_power_ctrl; 1917 u8 phy_type_ext; 1918 u8 fec_config; 1919 #define I40E_AQ_SET_FEC_ABILITY_KR (1 << 0) 1920 #define I40E_AQ_SET_FEC_ABILITY_RS (1 << 1) 1921 #define I40E_AQ_SET_FEC_REQUEST_KR (1 << 2) 1922 #define I40E_AQ_SET_FEC_REQUEST_RS (1 << 3) 1923 #define I40E_AQ_SET_FEC_AUTO (1 << 4) 1924 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 1925 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) 1926 u8 reserved; 1927 }; 1928 1929 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1930 1931 /* Set MAC Config command data structure (direct 0x0603) */ 1932 struct i40e_aq_set_mac_config { 1933 __le16 max_frame_size; 1934 u8 params; 1935 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1936 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1937 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1938 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1939 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1940 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1941 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1942 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1943 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1944 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1945 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1946 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1947 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1948 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1949 u8 tx_timer_priority; /* bitmap */ 1950 __le16 tx_timer_value; 1951 __le16 fc_refresh_threshold; 1952 u8 reserved[8]; 1953 }; 1954 1955 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1956 1957 /* Restart Auto-Negotiation (direct 0x605) */ 1958 struct i40e_aqc_set_link_restart_an { 1959 u8 command; 1960 #define I40E_AQ_PHY_RESTART_AN 0x02 1961 #define I40E_AQ_PHY_LINK_ENABLE 0x04 1962 u8 reserved[15]; 1963 }; 1964 1965 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1966 1967 /* Get Link Status cmd & response data structure (direct 0x0607) */ 1968 struct i40e_aqc_get_link_status { 1969 __le16 command_flags; /* only field set on command */ 1970 #define I40E_AQ_LSE_MASK 0x3 1971 #define I40E_AQ_LSE_NOP 0x0 1972 #define I40E_AQ_LSE_DISABLE 0x2 1973 #define I40E_AQ_LSE_ENABLE 0x3 1974 /* only response uses this flag */ 1975 #define I40E_AQ_LSE_IS_ENABLED 0x1 1976 u8 phy_type; /* i40e_aq_phy_type */ 1977 u8 link_speed; /* i40e_aq_link_speed */ 1978 u8 link_info; 1979 #define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1980 #define I40E_AQ_LINK_UP_FUNCTION 0x01 1981 #define I40E_AQ_LINK_FAULT 0x02 1982 #define I40E_AQ_LINK_FAULT_TX 0x04 1983 #define I40E_AQ_LINK_FAULT_RX 0x08 1984 #define I40E_AQ_LINK_FAULT_REMOTE 0x10 1985 #define I40E_AQ_LINK_UP_PORT 0x20 1986 #define I40E_AQ_MEDIA_AVAILABLE 0x40 1987 #define I40E_AQ_SIGNAL_DETECT 0x80 1988 u8 an_info; 1989 #define I40E_AQ_AN_COMPLETED 0x01 1990 #define I40E_AQ_LP_AN_ABILITY 0x02 1991 #define I40E_AQ_PD_FAULT 0x04 1992 #define I40E_AQ_FEC_EN 0x08 1993 #define I40E_AQ_PHY_LOW_POWER 0x10 1994 #define I40E_AQ_LINK_PAUSE_TX 0x20 1995 #define I40E_AQ_LINK_PAUSE_RX 0x40 1996 #define I40E_AQ_QUALIFIED_MODULE 0x80 1997 u8 ext_info; 1998 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1999 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 2000 #define I40E_AQ_LINK_TX_SHIFT 0x02 2001 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 2002 #define I40E_AQ_LINK_TX_ACTIVE 0x00 2003 #define I40E_AQ_LINK_TX_DRAINED 0x01 2004 #define I40E_AQ_LINK_TX_FLUSHED 0x03 2005 #define I40E_AQ_LINK_FORCED_40G 0x10 2006 /* 25G Error Codes */ 2007 #define I40E_AQ_25G_NO_ERR 0X00 2008 #define I40E_AQ_25G_NOT_PRESENT 0X01 2009 #define I40E_AQ_25G_NVM_CRC_ERR 0X02 2010 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 2011 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 2012 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 2013 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 2014 /* Since firmware API 1.7 loopback field keeps power class info as well */ 2015 #define I40E_AQ_LOOPBACK_MASK 0x07 2016 #define I40E_AQ_PWR_CLASS_SHIFT_LB 6 2017 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) 2018 __le16 max_frame_size; 2019 u8 config; 2020 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 2021 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 2022 #define I40E_AQ_CONFIG_CRC_ENA 0x04 2023 #define I40E_AQ_CONFIG_PACING_MASK 0x78 2024 union { 2025 struct { 2026 u8 power_desc; 2027 #define I40E_AQ_LINK_POWER_CLASS_1 0x00 2028 #define I40E_AQ_LINK_POWER_CLASS_2 0x01 2029 #define I40E_AQ_LINK_POWER_CLASS_3 0x02 2030 #define I40E_AQ_LINK_POWER_CLASS_4 0x03 2031 #define I40E_AQ_PWR_CLASS_MASK 0x03 2032 u8 reserved[4]; 2033 }; 2034 struct { 2035 u8 link_type[4]; 2036 u8 link_type_ext; 2037 }; 2038 }; 2039 }; 2040 2041 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 2042 2043 /* Set event mask command (direct 0x613) */ 2044 struct i40e_aqc_set_phy_int_mask { 2045 u8 reserved[8]; 2046 __le16 event_mask; 2047 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 2048 #define I40E_AQ_EVENT_MEDIA_NA 0x0004 2049 #define I40E_AQ_EVENT_LINK_FAULT 0x0008 2050 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 2051 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 2052 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 2053 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080 2054 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 2055 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 2056 u8 reserved1[6]; 2057 }; 2058 2059 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 2060 2061 /* Get Local AN advt register (direct 0x0614) 2062 * Set Local AN advt register (direct 0x0615) 2063 * Get Link Partner AN advt register (direct 0x0616) 2064 */ 2065 struct i40e_aqc_an_advt_reg { 2066 __le32 local_an_reg0; 2067 __le16 local_an_reg1; 2068 u8 reserved[10]; 2069 }; 2070 2071 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 2072 2073 /* Set Loopback mode (0x0618) */ 2074 struct i40e_aqc_set_lb_mode { 2075 u8 lb_level; 2076 #define I40E_AQ_LB_NONE 0 2077 #define I40E_AQ_LB_MAC 1 2078 #define I40E_AQ_LB_SERDES 2 2079 #define I40E_AQ_LB_PHY_INT 3 2080 #define I40E_AQ_LB_PHY_EXT 4 2081 #define I40E_AQ_LB_CPVL_PCS 5 2082 #define I40E_AQ_LB_CPVL_EXT 6 2083 #define I40E_AQ_LB_PHY_LOCAL 0x01 2084 #define I40E_AQ_LB_PHY_REMOTE 0x02 2085 #define I40E_AQ_LB_MAC_LOCAL 0x04 2086 u8 lb_type; 2087 #define I40E_AQ_LB_LOCAL 0 2088 #define I40E_AQ_LB_FAR 0x01 2089 u8 speed; 2090 #define I40E_AQ_LB_SPEED_NONE 0 2091 #define I40E_AQ_LB_SPEED_1G 1 2092 #define I40E_AQ_LB_SPEED_10G 2 2093 #define I40E_AQ_LB_SPEED_40G 3 2094 #define I40E_AQ_LB_SPEED_20G 4 2095 u8 force_speed; 2096 u8 reserved[12]; 2097 }; 2098 2099 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 2100 2101 /* Set PHY Debug command (0x0622) */ 2102 struct i40e_aqc_set_phy_debug { 2103 u8 command_flags; 2104 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 2105 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 2106 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 2107 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 2108 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 2109 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 2110 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 2111 /* Disable link manageability on a single port */ 2112 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 2113 /* Disable link manageability on all ports needs both bits 4 and 5 */ 2114 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20 2115 u8 reserved[15]; 2116 }; 2117 2118 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 2119 2120 enum i40e_aq_phy_reg_type { 2121 I40E_AQC_PHY_REG_INTERNAL = 0x1, 2122 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 2123 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 2124 }; 2125 2126 /* Run PHY Activity (0x0626) */ 2127 struct i40e_aqc_run_phy_activity { 2128 __le16 activity_id; 2129 u8 flags; 2130 u8 reserved1; 2131 __le32 control; 2132 __le32 data; 2133 u8 reserved2[4]; 2134 }; 2135 2136 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); 2137 2138 2139 /* Set PHY Register command (0x0628) */ 2140 /* Get PHY Register command (0x0629) */ 2141 struct i40e_aqc_phy_register_access { 2142 u8 phy_interface; 2143 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 2144 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 2145 #define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 2146 u8 dev_addres; 2147 u8 reserved1[2]; 2148 u32 reg_address; 2149 u32 reg_value; 2150 u8 reserved2[4]; 2151 }; 2152 2153 I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); 2154 2155 2156 /* NVM Read command (indirect 0x0701) 2157 * NVM Erase commands (direct 0x0702) 2158 * NVM Update commands (indirect 0x0703) 2159 */ 2160 struct i40e_aqc_nvm_update { 2161 u8 command_flags; 2162 #define I40E_AQ_NVM_LAST_CMD 0x01 2163 #define I40E_AQ_NVM_FLASH_ONLY 0x80 2164 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 2165 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 2166 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 2167 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 2168 u8 module_pointer; 2169 __le16 length; 2170 __le32 offset; 2171 __le32 addr_high; 2172 __le32 addr_low; 2173 }; 2174 2175 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 2176 2177 /* NVM Config Read (indirect 0x0704) */ 2178 struct i40e_aqc_nvm_config_read { 2179 __le16 cmd_flags; 2180 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 2181 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 2182 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 2183 __le16 element_count; 2184 __le16 element_id; /* Feature/field ID */ 2185 __le16 element_id_msw; /* MSWord of field ID */ 2186 __le32 address_high; 2187 __le32 address_low; 2188 }; 2189 2190 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 2191 2192 /* NVM Config Write (indirect 0x0705) */ 2193 struct i40e_aqc_nvm_config_write { 2194 __le16 cmd_flags; 2195 __le16 element_count; 2196 u8 reserved[4]; 2197 __le32 address_high; 2198 __le32 address_low; 2199 }; 2200 2201 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 2202 2203 /* Used for 0x0704 as well as for 0x0705 commands */ 2204 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 2205 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ 2206 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 2207 #define I40E_AQ_ANVM_FEATURE 0 2208 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 2209 struct i40e_aqc_nvm_config_data_feature { 2210 __le16 feature_id; 2211 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 2212 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 2213 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 2214 __le16 feature_options; 2215 __le16 feature_selection; 2216 }; 2217 2218 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 2219 2220 struct i40e_aqc_nvm_config_data_immediate_field { 2221 __le32 field_id; 2222 __le32 field_value; 2223 __le16 field_options; 2224 __le16 reserved; 2225 }; 2226 2227 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 2228 2229 /* OEM Post Update (indirect 0x0720) 2230 * no command data struct used 2231 */ 2232 struct i40e_aqc_nvm_oem_post_update { 2233 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 2234 u8 sel_data; 2235 u8 reserved[7]; 2236 }; 2237 2238 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 2239 2240 struct i40e_aqc_nvm_oem_post_update_buffer { 2241 u8 str_len; 2242 u8 dev_addr; 2243 __le16 eeprom_addr; 2244 u8 data[36]; 2245 }; 2246 2247 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 2248 2249 /* Thermal Sensor (indirect 0x0721) 2250 * read or set thermal sensor configs and values 2251 * takes a sensor and command specific data buffer, not detailed here 2252 */ 2253 struct i40e_aqc_thermal_sensor { 2254 u8 sensor_action; 2255 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 2256 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 2257 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 2258 u8 reserved[7]; 2259 __le32 addr_high; 2260 __le32 addr_low; 2261 }; 2262 2263 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); 2264 2265 /* Send to PF command (indirect 0x0801) id is only used by PF 2266 * Send to VF command (indirect 0x0802) id is only used by PF 2267 * Send to Peer PF command (indirect 0x0803) 2268 */ 2269 struct i40e_aqc_pf_vf_message { 2270 __le32 id; 2271 u8 reserved[4]; 2272 __le32 addr_high; 2273 __le32 addr_low; 2274 }; 2275 2276 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 2277 2278 /* Alternate structure */ 2279 2280 /* Direct write (direct 0x0900) 2281 * Direct read (direct 0x0902) 2282 */ 2283 struct i40e_aqc_alternate_write { 2284 __le32 address0; 2285 __le32 data0; 2286 __le32 address1; 2287 __le32 data1; 2288 }; 2289 2290 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 2291 2292 /* Indirect write (indirect 0x0901) 2293 * Indirect read (indirect 0x0903) 2294 */ 2295 2296 struct i40e_aqc_alternate_ind_write { 2297 __le32 address; 2298 __le32 length; 2299 __le32 addr_high; 2300 __le32 addr_low; 2301 }; 2302 2303 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 2304 2305 /* Done alternate write (direct 0x0904) 2306 * uses i40e_aq_desc 2307 */ 2308 struct i40e_aqc_alternate_write_done { 2309 __le16 cmd_flags; 2310 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 2311 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 2312 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 2313 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2 2314 u8 reserved[14]; 2315 }; 2316 2317 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 2318 2319 /* Set OEM mode (direct 0x0905) */ 2320 struct i40e_aqc_alternate_set_mode { 2321 __le32 mode; 2322 #define I40E_AQ_ALTERNATE_MODE_NONE 0 2323 #define I40E_AQ_ALTERNATE_MODE_OEM 1 2324 u8 reserved[12]; 2325 }; 2326 2327 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 2328 2329 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 2330 2331 /* async events 0x10xx */ 2332 2333 /* Lan Queue Overflow Event (direct, 0x1001) */ 2334 struct i40e_aqc_lan_overflow { 2335 __le32 prtdcb_rupto; 2336 __le32 otx_ctl; 2337 u8 reserved[8]; 2338 }; 2339 2340 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2341 2342 /* Get LLDP MIB (indirect 0x0A00) */ 2343 struct i40e_aqc_lldp_get_mib { 2344 u8 type; 2345 u8 reserved1; 2346 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2347 #define I40E_AQ_LLDP_MIB_LOCAL 0x0 2348 #define I40E_AQ_LLDP_MIB_REMOTE 0x1 2349 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2350 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2351 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2352 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2353 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2354 #define I40E_AQ_LLDP_TX_SHIFT 0x4 2355 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2356 /* TX pause flags use I40E_AQ_LINK_TX_* above */ 2357 __le16 local_len; 2358 __le16 remote_len; 2359 u8 reserved2[2]; 2360 __le32 addr_high; 2361 __le32 addr_low; 2362 }; 2363 2364 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2365 2366 /* Configure LLDP MIB Change Event (direct 0x0A01) 2367 * also used for the event (with type in the command field) 2368 */ 2369 struct i40e_aqc_lldp_update_mib { 2370 u8 command; 2371 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2372 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2373 u8 reserved[7]; 2374 __le32 addr_high; 2375 __le32 addr_low; 2376 }; 2377 2378 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2379 2380 /* Add LLDP TLV (indirect 0x0A02) 2381 * Delete LLDP TLV (indirect 0x0A04) 2382 */ 2383 struct i40e_aqc_lldp_add_tlv { 2384 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2385 u8 reserved1[1]; 2386 __le16 len; 2387 u8 reserved2[4]; 2388 __le32 addr_high; 2389 __le32 addr_low; 2390 }; 2391 2392 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2393 2394 /* Update LLDP TLV (indirect 0x0A03) */ 2395 struct i40e_aqc_lldp_update_tlv { 2396 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2397 u8 reserved; 2398 __le16 old_len; 2399 __le16 new_offset; 2400 __le16 new_len; 2401 __le32 addr_high; 2402 __le32 addr_low; 2403 }; 2404 2405 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2406 2407 /* Stop LLDP (direct 0x0A05) */ 2408 struct i40e_aqc_lldp_stop { 2409 u8 command; 2410 #define I40E_AQ_LLDP_AGENT_STOP 0x0 2411 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2412 u8 reserved[15]; 2413 }; 2414 2415 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2416 2417 /* Start LLDP (direct 0x0A06) */ 2418 2419 struct i40e_aqc_lldp_start { 2420 u8 command; 2421 #define I40E_AQ_LLDP_AGENT_START 0x1 2422 u8 reserved[15]; 2423 }; 2424 2425 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2426 2427 /* Set DCB (direct 0x0303) */ 2428 struct i40e_aqc_set_dcb_parameters { 2429 u8 command; 2430 #define I40E_AQ_DCB_SET_AGENT 0x1 2431 #define I40E_DCB_VALID 0x1 2432 u8 valid_flags; 2433 u8 reserved[14]; 2434 }; 2435 2436 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); 2437 2438 /* Get CEE DCBX Oper Config (0x0A07) 2439 * uses the generic descriptor struct 2440 * returns below as indirect response 2441 */ 2442 2443 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2444 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2445 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2446 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2447 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2448 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2449 2450 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2451 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2452 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2453 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2454 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2455 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2456 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2457 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2458 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2459 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2460 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2461 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2462 2463 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2464 * word boundary layout issues, which the Linux compilers silently deal 2465 * with by adding padding, making the actual struct larger than designed. 2466 * However, the FW compiler for the NIC is less lenient and complains 2467 * about the struct. Hence, the struct defined here has an extra byte in 2468 * fields reserved3 and reserved4 to directly acknowledge that padding, 2469 * and the new length is used in the length check macro. 2470 */ 2471 struct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2472 u8 reserved1; 2473 u8 oper_num_tc; 2474 u8 oper_prio_tc[4]; 2475 u8 reserved2; 2476 u8 oper_tc_bw[8]; 2477 u8 oper_pfc_en; 2478 u8 reserved3[2]; 2479 __le16 oper_app_prio; 2480 u8 reserved4[2]; 2481 __le16 tlv_status; 2482 }; 2483 2484 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2485 2486 struct i40e_aqc_get_cee_dcb_cfg_resp { 2487 u8 oper_num_tc; 2488 u8 oper_prio_tc[4]; 2489 u8 oper_tc_bw[8]; 2490 u8 oper_pfc_en; 2491 __le16 oper_app_prio; 2492 __le32 tlv_status; 2493 u8 reserved[12]; 2494 }; 2495 2496 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2497 2498 /* Set Local LLDP MIB (indirect 0x0A08) 2499 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2500 */ 2501 struct i40e_aqc_lldp_set_local_mib { 2502 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2503 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \ 2504 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2505 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0 2506 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1) 2507 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \ 2508 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT) 2509 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1 2510 u8 type; 2511 u8 reserved0; 2512 __le16 length; 2513 u8 reserved1[4]; 2514 __le32 address_high; 2515 __le32 address_low; 2516 }; 2517 2518 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2519 2520 struct i40e_aqc_lldp_set_local_mib_resp { 2521 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01 2522 u8 status; 2523 u8 reserved[15]; 2524 }; 2525 2526 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp); 2527 2528 /* Stop/Start LLDP Agent (direct 0x0A09) 2529 * Used for stopping/starting specific LLDP agent. e.g. DCBx 2530 */ 2531 struct i40e_aqc_lldp_stop_start_specific_agent { 2532 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2533 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \ 2534 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2535 u8 command; 2536 u8 reserved[15]; 2537 }; 2538 2539 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2540 2541 /* Add Udp Tunnel command and completion (direct 0x0B00) */ 2542 struct i40e_aqc_add_udp_tunnel { 2543 __le16 udp_port; 2544 u8 reserved0[3]; 2545 u8 protocol_type; 2546 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2547 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2548 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2549 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 2550 u8 reserved1[10]; 2551 }; 2552 2553 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2554 2555 struct i40e_aqc_add_udp_tunnel_completion { 2556 __le16 udp_port; 2557 u8 filter_entry_index; 2558 u8 multiple_pfs; 2559 #define I40E_AQC_SINGLE_PF 0x0 2560 #define I40E_AQC_MULTIPLE_PFS 0x1 2561 u8 total_filters; 2562 u8 reserved[11]; 2563 }; 2564 2565 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2566 2567 /* remove UDP Tunnel command (0x0B01) */ 2568 struct i40e_aqc_remove_udp_tunnel { 2569 u8 reserved[2]; 2570 u8 index; /* 0 to 15 */ 2571 u8 reserved2[13]; 2572 }; 2573 2574 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2575 2576 struct i40e_aqc_del_udp_tunnel_completion { 2577 __le16 udp_port; 2578 u8 index; /* 0 to 15 */ 2579 u8 multiple_pfs; 2580 u8 total_filters_used; 2581 u8 reserved1[11]; 2582 }; 2583 2584 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2585 2586 struct i40e_aqc_get_set_rss_key { 2587 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2588 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2589 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2590 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2591 __le16 vsi_id; 2592 u8 reserved[6]; 2593 __le32 addr_high; 2594 __le32 addr_low; 2595 }; 2596 2597 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2598 2599 struct i40e_aqc_get_set_rss_key_data { 2600 u8 standard_rss_key[0x28]; 2601 u8 extended_hash_key[0xc]; 2602 }; 2603 2604 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2605 2606 struct i40e_aqc_get_set_rss_lut { 2607 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2608 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2609 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2610 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2611 __le16 vsi_id; 2612 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2613 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2614 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2615 2616 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2617 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2618 __le16 flags; 2619 u8 reserved[4]; 2620 __le32 addr_high; 2621 __le32 addr_low; 2622 }; 2623 2624 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2625 2626 /* tunnel key structure 0x0B10 */ 2627 2628 struct i40e_aqc_tunnel_key_structure { 2629 u8 key1_off; 2630 u8 key2_off; 2631 u8 key1_len; /* 0 to 15 */ 2632 u8 key2_len; /* 0 to 15 */ 2633 u8 flags; 2634 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2635 /* response flags */ 2636 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2637 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2638 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2639 u8 network_key_index; 2640 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2641 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2642 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2643 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2644 u8 reserved[10]; 2645 }; 2646 2647 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2648 2649 /* OEM mode commands (direct 0xFE0x) */ 2650 struct i40e_aqc_oem_param_change { 2651 __le32 param_type; 2652 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2653 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2654 #define I40E_AQ_OEM_PARAM_MAC 2 2655 __le32 param_value1; 2656 __le16 param_value2; 2657 u8 reserved[6]; 2658 }; 2659 2660 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2661 2662 struct i40e_aqc_oem_state_change { 2663 __le32 state; 2664 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2665 #define I40E_AQ_OEM_STATE_LINK_UP 0x1 2666 u8 reserved[12]; 2667 }; 2668 2669 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2670 2671 /* Initialize OCSD (0xFE02, direct) */ 2672 struct i40e_aqc_opc_oem_ocsd_initialize { 2673 u8 type_status; 2674 u8 reserved1[3]; 2675 __le32 ocsd_memory_block_addr_high; 2676 __le32 ocsd_memory_block_addr_low; 2677 __le32 requested_update_interval; 2678 }; 2679 2680 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2681 2682 /* Initialize OCBB (0xFE03, direct) */ 2683 struct i40e_aqc_opc_oem_ocbb_initialize { 2684 u8 type_status; 2685 u8 reserved1[3]; 2686 __le32 ocbb_memory_block_addr_high; 2687 __le32 ocbb_memory_block_addr_low; 2688 u8 reserved2[4]; 2689 }; 2690 2691 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2692 2693 /* debug commands */ 2694 2695 /* get device id (0xFF00) uses the generic structure */ 2696 2697 /* set test more (0xFF01, internal) */ 2698 2699 struct i40e_acq_set_test_mode { 2700 u8 mode; 2701 #define I40E_AQ_TEST_PARTIAL 0 2702 #define I40E_AQ_TEST_FULL 1 2703 #define I40E_AQ_TEST_NVM 2 2704 u8 reserved[3]; 2705 u8 command; 2706 #define I40E_AQ_TEST_OPEN 0 2707 #define I40E_AQ_TEST_CLOSE 1 2708 #define I40E_AQ_TEST_INC 2 2709 u8 reserved2[3]; 2710 __le32 address_high; 2711 __le32 address_low; 2712 }; 2713 2714 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2715 2716 /* Debug Read Register command (0xFF03) 2717 * Debug Write Register command (0xFF04) 2718 */ 2719 struct i40e_aqc_debug_reg_read_write { 2720 __le32 reserved; 2721 __le32 address; 2722 __le32 value_high; 2723 __le32 value_low; 2724 }; 2725 2726 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2727 2728 /* Scatter/gather Reg Read (indirect 0xFF05) 2729 * Scatter/gather Reg Write (indirect 0xFF06) 2730 */ 2731 2732 /* i40e_aq_desc is used for the command */ 2733 struct i40e_aqc_debug_reg_sg_element_data { 2734 __le32 address; 2735 __le32 value; 2736 }; 2737 2738 /* Debug Modify register (direct 0xFF07) */ 2739 struct i40e_aqc_debug_modify_reg { 2740 __le32 address; 2741 __le32 value; 2742 __le32 clear_mask; 2743 __le32 set_mask; 2744 }; 2745 2746 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2747 2748 /* dump internal data (0xFF08, indirect) */ 2749 2750 #define I40E_AQ_CLUSTER_ID_AUX 0 2751 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2752 #define I40E_AQ_CLUSTER_ID_TXSCHED 2 2753 #define I40E_AQ_CLUSTER_ID_HMC 3 2754 #define I40E_AQ_CLUSTER_ID_MAC0 4 2755 #define I40E_AQ_CLUSTER_ID_MAC1 5 2756 #define I40E_AQ_CLUSTER_ID_MAC2 6 2757 #define I40E_AQ_CLUSTER_ID_MAC3 7 2758 #define I40E_AQ_CLUSTER_ID_DCB 8 2759 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2760 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2761 #define I40E_AQ_CLUSTER_ID_ALTRAM 11 2762 2763 struct i40e_aqc_debug_dump_internals { 2764 u8 cluster_id; 2765 u8 table_id; 2766 __le16 data_size; 2767 __le32 idx; 2768 __le32 address_high; 2769 __le32 address_low; 2770 }; 2771 2772 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2773 2774 struct i40e_aqc_debug_modify_internals { 2775 u8 cluster_id; 2776 u8 cluster_specific_params[7]; 2777 __le32 address_high; 2778 __le32 address_low; 2779 }; 2780 2781 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2782 2783 #endif /* _I40E_ADMINQ_CMD_H_ */ 2784