xref: /illumos-gate/usr/src/uts/common/io/hxge/hxge_main.c (revision 86ef0a63)
13dec9fcdSqs /*
23dec9fcdSqs  * CDDL HEADER START
33dec9fcdSqs  *
43dec9fcdSqs  * The contents of this file are subject to the terms of the
53dec9fcdSqs  * Common Development and Distribution License (the "License").
63dec9fcdSqs  * You may not use this file except in compliance with the License.
73dec9fcdSqs  *
83dec9fcdSqs  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
93dec9fcdSqs  * or http://www.opensolaris.org/os/licensing.
103dec9fcdSqs  * See the License for the specific language governing permissions
113dec9fcdSqs  * and limitations under the License.
123dec9fcdSqs  *
133dec9fcdSqs  * When distributing Covered Code, include this CDDL HEADER in each
143dec9fcdSqs  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
153dec9fcdSqs  * If applicable, add the following below this CDDL HEADER, with the
163dec9fcdSqs  * fields enclosed by brackets "[]" replaced with your own identifying
173dec9fcdSqs  * information: Portions Copyright [yyyy] [name of copyright owner]
183dec9fcdSqs  *
193dec9fcdSqs  * CDDL HEADER END
203dec9fcdSqs  */
213dec9fcdSqs /*
220dc2366fSVenugopal Iyer  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
233dec9fcdSqs  * Use is subject to license terms.
24b97d6ca7SMilan Jurik  * Copyright 2012 Milan Jurik. All rights reserved.
25238d8f47SDale Ghent  * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
263dec9fcdSqs  */
283dec9fcdSqs /*
293dec9fcdSqs  * SunOs MT STREAMS Hydra 10Gb Ethernet Device Driver.
303dec9fcdSqs  */
313dec9fcdSqs #include <hxge_impl.h>
323dec9fcdSqs #include <hxge_pfc.h>
343dec9fcdSqs /*
353dec9fcdSqs  * PSARC/2007/453 MSI-X interrupt limit override
363dec9fcdSqs  * (This PSARC case is limited to MSI-X vectors
373dec9fcdSqs  *  and SPARC platforms only).
383dec9fcdSqs  */
391ed83081SMichael Speer uint32_t hxge_msi_enable = 2;
413dec9fcdSqs /*
423dec9fcdSqs  * Globals: tunable parameters (/etc/system or adb)
433dec9fcdSqs  *
443dec9fcdSqs  */
453dec9fcdSqs uint32_t hxge_rbr_size = HXGE_RBR_RBB_DEFAULT;
463dec9fcdSqs uint32_t hxge_rbr_spare_size = 0;
473dec9fcdSqs uint32_t hxge_rcr_size = HXGE_RCR_DEFAULT;
483dec9fcdSqs uint32_t hxge_tx_ring_size = HXGE_TX_RING_DEFAULT;
493dec9fcdSqs uint32_t hxge_bcopy_thresh = TX_BCOPY_MAX;
503dec9fcdSqs uint32_t hxge_dvma_thresh = TX_FASTDVMA_MIN;
513dec9fcdSqs uint32_t hxge_dma_stream_thresh = TX_STREAM_MIN;
52a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint32_t hxge_jumbo_frame_size = MAX_FRAME_SIZE;
543dec9fcdSqs static hxge_os_mutex_t hxgedebuglock;
553dec9fcdSqs static int hxge_debug_init = 0;
573dec9fcdSqs /*
583dec9fcdSqs  * Debugging flags:
593dec9fcdSqs  *		hxge_no_tx_lb : transmit load balancing
603dec9fcdSqs  *		hxge_tx_lb_policy: 0 - TCP/UDP port (default)
613dec9fcdSqs  *				   1 - From the Stack
623dec9fcdSqs  *				   2 - Destination IP Address
633dec9fcdSqs  */
643dec9fcdSqs uint32_t hxge_no_tx_lb = 0;
653dec9fcdSqs uint32_t hxge_tx_lb_policy = HXGE_TX_LB_TCPUDP;
673dec9fcdSqs /*
683dec9fcdSqs  * Tunables to manage the receive buffer blocks.
693dec9fcdSqs  *
703dec9fcdSqs  * hxge_rx_threshold_hi: copy all buffers.
713dec9fcdSqs  * hxge_rx_bcopy_size_type: receive buffer block size type.
723dec9fcdSqs  * hxge_rx_threshold_lo: copy only up to tunable block size type.
733dec9fcdSqs  */
74f043ebedSMichael Speer #if defined(__sparc)
75f043ebedSMichael Speer hxge_rxbuf_threshold_t hxge_rx_threshold_hi = HXGE_RX_COPY_6;
76f043ebedSMichael Speer hxge_rxbuf_threshold_t hxge_rx_threshold_lo = HXGE_RX_COPY_4;
77f043ebedSMichael Speer #else
7857c5371aSQiyan Sun - Sun Microsystems - San Diego United States hxge_rxbuf_threshold_t hxge_rx_threshold_hi = HXGE_RX_COPY_NONE;
7957c5371aSQiyan Sun - Sun Microsystems - San Diego United States hxge_rxbuf_threshold_t hxge_rx_threshold_lo = HXGE_RX_COPY_NONE;
80f043ebedSMichael Speer #endif
81f043ebedSMichael Speer hxge_rxbuf_type_t hxge_rx_buf_size_type = RCR_PKTBUFSZ_0;
833dec9fcdSqs rtrace_t hpi_rtracebuf;
853dec9fcdSqs /*
863dec9fcdSqs  * Function Prototypes
873dec9fcdSqs  */
883dec9fcdSqs static int hxge_attach(dev_info_t *, ddi_attach_cmd_t);
893dec9fcdSqs static int hxge_detach(dev_info_t *, ddi_detach_cmd_t);
903dec9fcdSqs static void hxge_unattach(p_hxge_t);
923dec9fcdSqs static hxge_status_t hxge_setup_system_dma_pages(p_hxge_t);
943dec9fcdSqs static hxge_status_t hxge_setup_mutexes(p_hxge_t);
953dec9fcdSqs static void hxge_destroy_mutexes(p_hxge_t);
973dec9fcdSqs static hxge_status_t hxge_map_regs(p_hxge_t hxgep);
983dec9fcdSqs static void hxge_unmap_regs(p_hxge_t hxgep);
100f043ebedSMichael Speer static hxge_status_t hxge_add_intrs(p_hxge_t hxgep);
1013dec9fcdSqs static void hxge_remove_intrs(p_hxge_t hxgep);
1023dec9fcdSqs static hxge_status_t hxge_add_intrs_adv(p_hxge_t hxgep);
1033dec9fcdSqs static hxge_status_t hxge_add_intrs_adv_type(p_hxge_t, uint32_t);
1043dec9fcdSqs static hxge_status_t hxge_add_intrs_adv_type_fix(p_hxge_t, uint32_t);
105f043ebedSMichael Speer static void hxge_intrs_enable(p_hxge_t hxgep);
1063dec9fcdSqs static void hxge_intrs_disable(p_hxge_t hxgep);
1073dec9fcdSqs static void hxge_suspend(p_hxge_t);
1083dec9fcdSqs static hxge_status_t hxge_resume(p_hxge_t);
109f043ebedSMichael Speer static hxge_status_t hxge_setup_dev(p_hxge_t);
1103dec9fcdSqs static void hxge_destroy_dev(p_hxge_t);
111f043ebedSMichael Speer static hxge_status_t hxge_alloc_mem_pool(p_hxge_t);
1123dec9fcdSqs static void hxge_free_mem_pool(p_hxge_t);
1133dec9fcdSqs static hxge_status_t hxge_alloc_rx_mem_pool(p_hxge_t);
1143dec9fcdSqs static void hxge_free_rx_mem_pool(p_hxge_t);
1153dec9fcdSqs static hxge_status_t hxge_alloc_tx_mem_pool(p_hxge_t);
1163dec9fcdSqs static void hxge_free_tx_mem_pool(p_hxge_t);
1173dec9fcdSqs static hxge_status_t hxge_dma_mem_alloc(p_hxge_t, dma_method_t,
1183dec9fcdSqs     struct ddi_dma_attr *, size_t, ddi_device_acc_attr_t *, uint_t,
1193dec9fcdSqs     p_hxge_dma_common_t);
1203dec9fcdSqs static void hxge_dma_mem_free(p_hxge_dma_common_t);
1213dec9fcdSqs static hxge_status_t hxge_alloc_rx_buf_dma(p_hxge_t, uint16_t,
1223dec9fcdSqs     p_hxge_dma_common_t *, size_t, size_t, uint32_t *);
1233dec9fcdSqs static void hxge_free_rx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
1243dec9fcdSqs static hxge_status_t hxge_alloc_rx_cntl_dma(p_hxge_t, uint16_t,
1258ad8db65SMichael Speer     p_hxge_dma_common_t *, struct ddi_dma_attr *, size_t);
1263dec9fcdSqs static void hxge_free_rx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
1273dec9fcdSqs static hxge_status_t hxge_alloc_tx_buf_dma(p_hxge_t, uint16_t,
1283dec9fcdSqs     p_hxge_dma_common_t *, size_t, size_t, uint32_t *);
1293dec9fcdSqs static void hxge_free_tx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
1303dec9fcdSqs static hxge_status_t hxge_alloc_tx_cntl_dma(p_hxge_t, uint16_t,
1313dec9fcdSqs     p_hxge_dma_common_t *, size_t);
1323dec9fcdSqs static void hxge_free_tx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
1333dec9fcdSqs static int hxge_init_common_dev(p_hxge_t);
1343dec9fcdSqs static void hxge_uninit_common_dev(p_hxge_t);
1363dec9fcdSqs /*
1373dec9fcdSqs  * The next declarations are for the GLDv3 interface.
1383dec9fcdSqs  */
1393dec9fcdSqs static int hxge_m_start(void *);
1403dec9fcdSqs static void hxge_m_stop(void *);
1413dec9fcdSqs static int hxge_m_multicst(void *, boolean_t, const uint8_t *);
1423dec9fcdSqs static int hxge_m_promisc(void *, boolean_t);
1433dec9fcdSqs static void hxge_m_ioctl(void *, queue_t *, mblk_t *);
1443dec9fcdSqs static hxge_status_t hxge_mac_register(p_hxge_t hxgep);
1463dec9fcdSqs static boolean_t hxge_m_getcapab(void *, mac_capab_t, void *);
147a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static boolean_t hxge_param_locked(mac_prop_id_t pr_num);
148a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
149a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States     uint_t pr_valsize, const void *pr_val);
150a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
151a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States     uint_t pr_valsize, void *pr_val);
1520dc2366fSVenugopal Iyer static void hxge_m_propinfo(void *barg, const char *pr_name,
1530dc2366fSVenugopal Iyer     mac_prop_id_t pr_num, mac_prop_info_handle_t mph);
154a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_set_priv_prop(p_hxge_t hxgep, const char *pr_name,
155a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States     uint_t pr_valsize, const void *pr_val);
156a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_get_priv_prop(p_hxge_t hxgep, const char *pr_name,
1570dc2366fSVenugopal Iyer     uint_t pr_valsize, void *pr_val);
158a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_link_poll(void *arg);
159e5d97391SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_link_update(p_hxge_t hxge, link_state_t state);
1601c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_msix_init(p_hxge_t hxgep);
161a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 
1620dc2366fSVenugopal Iyer char *hxge_priv_props[] = {
1630dc2366fSVenugopal Iyer 	"_rxdma_intr_time",
1640dc2366fSVenugopal Iyer 	"_rxdma_intr_pkts",
1650dc2366fSVenugopal Iyer 	"_class_opt_ipv4_tcp",
1660dc2366fSVenugopal Iyer 	"_class_opt_ipv4_udp",
1670dc2366fSVenugopal Iyer 	"_class_opt_ipv4_ah",
1680dc2366fSVenugopal Iyer 	"_class_opt_ipv4_sctp",
1690dc2366fSVenugopal Iyer 	"_class_opt_ipv6_tcp",
1700dc2366fSVenugopal Iyer 	"_class_opt_ipv6_udp",
1710dc2366fSVenugopal Iyer 	"_class_opt_ipv6_ah",
1720dc2366fSVenugopal Iyer 	"_class_opt_ipv6_sctp",
1730dc2366fSVenugopal Iyer 	NULL
174a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States };
175a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 
176a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define	HXGE_MAX_PRIV_PROPS	\
177a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	(sizeof (hxge_priv_props)/sizeof (mac_priv_prop_t))
1793dec9fcdSqs #define	HXGE_MAGIC	0x4E584745UL
1803dec9fcdSqs #define	MAX_DUMP_SZ 256
182a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define	HXGE_M_CALLBACK_FLAGS	\
1853dec9fcdSqs extern hxge_status_t hxge_pfc_set_default_mac_addr(p_hxge_t hxgep);
1873dec9fcdSqs static mac_callbacks_t hxge_m_callbacks = {
1883dec9fcdSqs 	HXGE_M_CALLBACK_FLAGS,
1893dec9fcdSqs 	hxge_m_stat,
1903dec9fcdSqs 	hxge_m_start,
1913dec9fcdSqs 	hxge_m_stop,
1923dec9fcdSqs 	hxge_m_promisc,
1933dec9fcdSqs 	hxge_m_multicst,
1941ed83081SMichael Speer 	NULL,
1951ed83081SMichael Speer 	NULL,
1960dc2366fSVenugopal Iyer 	NULL,
1973dec9fcdSqs 	hxge_m_ioctl,
198a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	hxge_m_getcapab,
199a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	NULL,
200a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	NULL,
201a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	hxge_m_setprop,
2020dc2366fSVenugopal Iyer 	hxge_m_getprop,
2030dc2366fSVenugopal Iyer 	hxge_m_propinfo
2043dec9fcdSqs };
20657c5371aSQiyan Sun - Sun Microsystems - San Diego United States /* PSARC/2007/453 MSI-X interrupt limit override. */
20757c5371aSQiyan Sun - Sun Microsystems - San Diego United States #define	HXGE_MSIX_REQUEST_10G	8
20857c5371aSQiyan Sun - Sun Microsystems - San Diego United States static int hxge_create_msi_property(p_hxge_t);
20957c5371aSQiyan Sun - Sun Microsystems - San Diego United States 
2103dec9fcdSqs /* Enable debug messages as necessary. */
211a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint64_t hxge_debug_level = 0;
2133dec9fcdSqs /*
2143dec9fcdSqs  * This list contains the instance structures for the Hydra
2153dec9fcdSqs  * devices present in the system. The lock exists to guarantee
2163dec9fcdSqs  * mutually exclusive access to the list.
2173dec9fcdSqs  */
2183dec9fcdSqs void *hxge_list = NULL;
2193dec9fcdSqs void *hxge_hw_list = NULL;
2203dec9fcdSqs hxge_os_mutex_t hxge_common_lock;
2223dec9fcdSqs extern uint64_t hpi_debug_level;
224b97d6ca7SMilan Jurik extern hxge_status_t hxge_ldgv_init(p_hxge_t, int *, int *);
225b97d6ca7SMilan Jurik extern hxge_status_t hxge_ldgv_uninit(p_hxge_t);
226b97d6ca7SMilan Jurik extern hxge_status_t hxge_intr_ldgv_init(p_hxge_t);
2273dec9fcdSqs extern void hxge_fm_init(p_hxge_t hxgep, ddi_device_acc_attr_t *reg_attr,
228f043ebedSMichael Speer     ddi_device_acc_attr_t *desc_attr, ddi_dma_attr_t *dma_attr);
2293dec9fcdSqs extern void hxge_fm_fini(p_hxge_t hxgep);
2313dec9fcdSqs /*
2323dec9fcdSqs  * Count used to maintain the number of buffers being used
2333dec9fcdSqs  * by Hydra instances and loaned up to the upper layers.
2343dec9fcdSqs  */
2353dec9fcdSqs uint32_t hxge_mblks_pending = 0;
2373dec9fcdSqs /*
2383dec9fcdSqs  * Device register access attributes for PIO.
2393dec9fcdSqs  */
2403dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_reg_acc_attr = {
241f043ebedSMichael Speer 	DDI_DEVICE_ATTR_V0,
2423dec9fcdSqs 	DDI_STRUCTURE_LE_ACC,
2433dec9fcdSqs 	DDI_STRICTORDER_ACC,
2443dec9fcdSqs };
2463dec9fcdSqs /*
2473dec9fcdSqs  * Device descriptor access attributes for DMA.
2483dec9fcdSqs  */
2493dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_desc_dma_acc_attr = {
2503dec9fcdSqs 	DDI_DEVICE_ATTR_V0,
2513dec9fcdSqs 	DDI_STRUCTURE_LE_ACC,
2533dec9fcdSqs };
2553dec9fcdSqs /*
2563dec9fcdSqs  * Device buffer access attributes for DMA.
2573dec9fcdSqs  */
2583dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_buf_dma_acc_attr = {
2593dec9fcdSqs 	DDI_DEVICE_ATTR_V0,
2603dec9fcdSqs 	DDI_STRUCTURE_BE_ACC,
2623dec9fcdSqs };
2648ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_rcr_desc_dma_attr = {
2658ad8db65SMichael Speer 	DMA_ATTR_V0,		/* version number. */
2668ad8db65SMichael Speer 	0,			/* low address */
2678ad8db65SMichael Speer 	0xffffffffffffffff,	/* high address */
2688ad8db65SMichael Speer 	0xffffffffffffffff,	/* address counter max */
2698ad8db65SMichael Speer 	0x80000,		/* alignment */
2708ad8db65SMichael Speer 	0xfc00fc,		/* dlim_burstsizes */
2718ad8db65SMichael Speer 	0x1,			/* minimum transfer size */
2728ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum transfer size */
2738ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum segment size */
2748ad8db65SMichael Speer 	1,			/* scatter/gather list length */
2758ad8db65SMichael Speer 	(unsigned int)1,	/* granularity */
2768ad8db65SMichael Speer 	0			/* attribute flags */
2778ad8db65SMichael Speer };
2788ad8db65SMichael Speer 
2798ad8db65SMichael Speer ddi_dma_attr_t hxge_tx_desc_dma_attr = {
2803dec9fcdSqs 	DMA_ATTR_V0,		/* version number. */
2813dec9fcdSqs 	0,			/* low address */
2823dec9fcdSqs 	0xffffffffffffffff,	/* high address */
2833dec9fcdSqs 	0xffffffffffffffff,	/* address counter max */
2843dec9fcdSqs 	0x100000,		/* alignment */
2853dec9fcdSqs 	0xfc00fc,		/* dlim_burstsizes */
2863dec9fcdSqs 	0x1,			/* minimum transfer size */
2873dec9fcdSqs 	0xffffffffffffffff,	/* maximum transfer size */
2883dec9fcdSqs 	0xffffffffffffffff,	/* maximum segment size */
2893dec9fcdSqs 	1,			/* scatter/gather list length */
2903dec9fcdSqs 	(unsigned int)1,	/* granularity */
2913dec9fcdSqs 	0			/* attribute flags */
2923dec9fcdSqs };
2948ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_rbr_desc_dma_attr = {
2958ad8db65SMichael Speer 	DMA_ATTR_V0,		/* version number. */
2968ad8db65SMichael Speer 	0,			/* low address */
2978ad8db65SMichael Speer 	0xffffffffffffffff,	/* high address */
2988ad8db65SMichael Speer 	0xffffffffffffffff,	/* address counter max */
2998ad8db65SMichael Speer 	0x40000,		/* alignment */
3008ad8db65SMichael Speer 	0xfc00fc,		/* dlim_burstsizes */
3018ad8db65SMichael Speer 	0x1,			/* minimum transfer size */
3028ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum transfer size */
3038ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum segment size */
3048ad8db65SMichael Speer 	1,			/* scatter/gather list length */
3058ad8db65SMichael Speer 	(unsigned int)1,	/* granularity */
3068ad8db65SMichael Speer 	0			/* attribute flags */
3078ad8db65SMichael Speer };
3088ad8db65SMichael Speer 
3098ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_mbox_dma_attr = {
3108ad8db65SMichael Speer 	DMA_ATTR_V0,		/* version number. */
3118ad8db65SMichael Speer 	0,			/* low address */
3128ad8db65SMichael Speer 	0xffffffffffffffff,	/* high address */
3138ad8db65SMichael Speer 	0xffffffffffffffff,	/* address counter max */
3148ad8db65SMichael Speer #if defined(_BIG_ENDIAN)
3158ad8db65SMichael Speer 	0x2000,			/* alignment */
3168ad8db65SMichael Speer #else
3178ad8db65SMichael Speer 	0x1000,			/* alignment */
3188ad8db65SMichael Speer #endif
3198ad8db65SMichael Speer 	0xfc00fc,		/* dlim_burstsizes */
3208ad8db65SMichael Speer 	0x1,			/* minimum transfer size */
3218ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum transfer size */
3228ad8db65SMichael Speer 	0xffffffffffffffff,	/* maximum segment size */
3238ad8db65SMichael Speer 	5,			/* scatter/gather list length */
3248ad8db65SMichael Speer 	(unsigned int)1,	/* granularity */
3258ad8db65SMichael Speer 	0			/* attribute flags */
3268ad8db65SMichael Speer };
3278ad8db65SMichael Speer 
3283dec9fcdSqs ddi_dma_attr_t hxge_tx_dma_attr = {
3293dec9fcdSqs 	DMA_ATTR_V0,		/* version number. */
3303dec9fcdSqs 	0,			/* low address */
3313dec9fcdSqs 	0xffffffffffffffff,	/* high address */
3323dec9fcdSqs 	0xffffffffffffffff,	/* address counter max */
3333dec9fcdSqs #if defined(_BIG_ENDIAN)
3343dec9fcdSqs 	0x2000,			/* alignment */
3353dec9fcdSqs #else
3363dec9fcdSqs 	0x1000,			/* alignment */
3373dec9fcdSqs #endif
3383dec9fcdSqs 	0xfc00fc,		/* dlim_burstsizes */
3393dec9fcdSqs 	0x1,			/* minimum transfer size */
3403dec9fcdSqs 	0xffffffffffffffff,	/* maximum transfer size */
3413dec9fcdSqs 	0xffffffffffffffff,	/* maximum segment size */
3423dec9fcdSqs 	5,			/* scatter/gather list length */
3433dec9fcdSqs 	(unsigned int)1,	/* granularity */
3443dec9fcdSqs 	0			/* attribute flags */
3453dec9fcdSqs };
3473dec9fcdSqs ddi_dma_attr_t hxge_rx_dma_attr = {
3483dec9fcdSqs 	DMA_ATTR_V0,		/* version number. */
3493dec9fcdSqs 	0,			/* low address */
3503dec9fcdSqs 	0xffffffffffffffff,	/* high address */
3513dec9fcdSqs 	0xffffffffffffffff,	/* address counter max */
3523dec9fcdSqs 	0x10000,		/* alignment */
3533dec9fcdSqs 	0xfc00fc,		/* dlim_burstsizes */
3543dec9fcdSqs 	0x1,			/* minimum transfer size */
3553dec9fcdSqs 	0xffffffffffffffff,	/* maximum transfer size */
3563dec9fcdSqs 	0xffffffffffffffff,	/* maximum segment size */
3573dec9fcdSqs 	1,			/* scatter/gather list length */
3583dec9fcdSqs 	(unsigned int)1,	/* granularity */
3593dec9fcdSqs 	DDI_DMA_RELAXED_ORDERING /* attribute flags */
3603dec9fcdSqs };
3623dec9fcdSqs ddi_dma_lim_t hxge_dma_limits = {
3633dec9fcdSqs 	(uint_t)0,		/* dlim_addr_lo */
3643dec9fcdSqs 	(uint_t)0xffffffff,	/* dlim_addr_hi */
3653dec9fcdSqs 	(uint_t)0xffffffff,	/* dlim_cntr_max */
3663dec9fcdSqs 	(uint_t)0xfc00fc,	/* dlim_burstsizes for 32 and 64 bit xfers */
3673dec9fcdSqs 	0x1,			/* dlim_minxfer */
3683dec9fcdSqs 	1024			/* dlim_speed */
3693dec9fcdSqs };
3713dec9fcdSqs dma_method_t hxge_force_dma = DVMA;
3733dec9fcdSqs /*
3743dec9fcdSqs  * dma chunk sizes.
3753dec9fcdSqs  *
3763dec9fcdSqs  * Try to allocate the largest possible size
3773dec9fcdSqs  * so that fewer number of dma chunks would be managed
3783dec9fcdSqs  */
3793dec9fcdSqs size_t alloc_sizes[] = {
3803dec9fcdSqs     0x1000, 0x2000, 0x4000, 0x8000,
3813dec9fcdSqs     0x10000, 0x20000, 0x40000, 0x80000,
3823dec9fcdSqs     0x100000, 0x200000, 0x400000, 0x800000, 0x1000000
3833dec9fcdSqs };
3853dec9fcdSqs /*
3863dec9fcdSqs  * Translate "dev_t" to a pointer to the associated "dev_info_t".
3873dec9fcdSqs  */
3883dec9fcdSqs static int
hxge_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)3893dec9fcdSqs hxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
3903dec9fcdSqs {
3913dec9fcdSqs 	p_hxge_t	hxgep = NULL;
3923dec9fcdSqs 	int		instance;
3933dec9fcdSqs 	int		status = DDI_SUCCESS;
3941ed83081SMichael Speer 	int		i;
3963dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_attach"));
3983dec9fcdSqs 	/*
3993dec9fcdSqs 	 * Get the device instance since we'll need to setup or retrieve a soft
4003dec9fcdSqs 	 * state for this instance.
4013dec9fcdSqs 	 */
4023dec9fcdSqs 	instance = ddi_get_instance(dip);
4043dec9fcdSqs 	switch (cmd) {
4053dec9fcdSqs 	case DDI_ATTACH:
4063dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_ATTACH"));
4073dec9fcdSqs 		break;
4093dec9fcdSqs 	case DDI_RESUME:
4103dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_RESUME"));
4113dec9fcdSqs 		hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
4123dec9fcdSqs 		if (hxgep == NULL) {
4133dec9fcdSqs 			status = DDI_FAILURE;
4143dec9fcdSqs 			break;
4153dec9fcdSqs 		}
4163dec9fcdSqs 		if (hxgep->dip != dip) {
4173dec9fcdSqs 			status = DDI_FAILURE;
4183dec9fcdSqs 			break;
4193dec9fcdSqs 		}
4203dec9fcdSqs 		if (hxgep->suspended == DDI_PM_SUSPEND) {
4213dec9fcdSqs 			status = ddi_dev_is_needed(hxgep->dip, 0, 1);
4223dec9fcdSqs 		} else {
4233dec9fcdSqs 			(void) hxge_resume(hxgep);
4243dec9fcdSqs 		}
4253dec9fcdSqs 		goto hxge_attach_exit;
4273dec9fcdSqs 	case DDI_PM_RESUME:
4283dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_RESUME"));
4293dec9fcdSqs 		hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
4303dec9fcdSqs 		if (hxgep == NULL) {
4313dec9fcdSqs 			status = DDI_FAILURE;
4323dec9fcdSqs 			break;
4333dec9fcdSqs 		}
4343dec9fcdSqs 		if (hxgep->dip != dip) {
4353dec9fcdSqs 			status = DDI_FAILURE;
4363dec9fcdSqs 			break;
4373dec9fcdSqs 		}
4383dec9fcdSqs 		(void) hxge_resume(hxgep);
4393dec9fcdSqs 		goto hxge_attach_exit;
4413dec9fcdSqs 	default:
4423dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing unknown"));
4433dec9fcdSqs 		status = DDI_FAILURE;
4443dec9fcdSqs 		goto hxge_attach_exit;
4453dec9fcdSqs 	}
4473dec9fcdSqs 	if (ddi_soft_state_zalloc(hxge_list, instance) == DDI_FAILURE) {
4483dec9fcdSqs 		status = DDI_FAILURE;
4493dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, DDI_CTL,
4503dec9fcdSqs 		    "ddi_soft_state_zalloc failed"));
4513dec9fcdSqs 		goto hxge_attach_exit;
4523dec9fcdSqs 	}
4543dec9fcdSqs 	hxgep = ddi_get_soft_state(hxge_list, instance);
4553dec9fcdSqs 	if (hxgep == NULL) {
4563dec9fcdSqs 		status = HXGE_ERROR;
4573dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, DDI_CTL,
4583dec9fcdSqs 		    "ddi_get_soft_state failed"));
4593dec9fcdSqs 		goto hxge_attach_fail2;
4603dec9fcdSqs 	}
4623dec9fcdSqs 	hxgep->drv_state = 0;
4633dec9fcdSqs 	hxgep->dip = dip;
4643dec9fcdSqs 	hxgep->instance = instance;
4653dec9fcdSqs 	hxgep->p_dip = ddi_get_parent(dip);
4663dec9fcdSqs 	hxgep->hxge_debug_level = hxge_debug_level;
4673dec9fcdSqs 	hpi_debug_level = hxge_debug_level;
4691ed83081SMichael Speer 	/*
4701ed83081SMichael Speer 	 * Initialize MMAC struture.
4711ed83081SMichael Speer 	 */
4721ed83081SMichael Speer 	(void) hxge_pfc_num_macs_get(hxgep, &hxgep->mmac.total);
4731ed83081SMichael Speer 	hxgep->mmac.available = hxgep->mmac.total;
4741ed83081SMichael Speer 	for (i = 0; i < hxgep->mmac.total; i++) {
4751ed83081SMichael Speer 		hxgep->mmac.addrs[i].set = B_FALSE;
4761ed83081SMichael Speer 		hxgep->mmac.addrs[i].primary = B_FALSE;
4771ed83081SMichael Speer 	}
4781ed83081SMichael Speer 
479f043ebedSMichael Speer 	hxge_fm_init(hxgep, &hxge_dev_reg_acc_attr, &hxge_dev_desc_dma_acc_attr,
480f043ebedSMichael Speer 	    &hxge_rx_dma_attr);
4823dec9fcdSqs 	status = hxge_map_regs(hxgep);
4833dec9fcdSqs 	if (status != HXGE_OK) {
4843dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_map_regs failed"));
4853dec9fcdSqs 		goto hxge_attach_fail3;
4863dec9fcdSqs 	}
4883dec9fcdSqs 	status = hxge_init_common_dev(hxgep);
4893dec9fcdSqs 	if (status != HXGE_OK) {
4903dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4913dec9fcdSqs 		    "hxge_init_common_dev failed"));
4923dec9fcdSqs 		goto hxge_attach_fail4;
4933dec9fcdSqs 	}
4953dec9fcdSqs 	/*
4963dec9fcdSqs 	 * Setup the Ndd parameters for this instance.
4973dec9fcdSqs 	 */
4983dec9fcdSqs 	hxge_init_param(hxgep);
5003dec9fcdSqs 	/*
5013dec9fcdSqs 	 * Setup Register Tracing Buffer.
5023dec9fcdSqs 	 */
5033dec9fcdSqs 	hpi_rtrace_buf_init((rtrace_t *)&hpi_rtracebuf);
5053dec9fcdSqs 	/* init stats ptr */
5063dec9fcdSqs 	hxge_init_statsp(hxgep);
508a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	status = hxge_setup_mutexes(hxgep);
509a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	if (status != HXGE_OK) {
510a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set mutex failed"));
511a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 		goto hxge_attach_fail;
512a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	}
513a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 
51423b519b2SMichael Speer 	/* Scrub the MSI-X memory */
51523b519b2SMichael Speer 	hxge_msix_init(hxgep);
51623b519b2SMichael Speer 
5173dec9fcdSqs 	status = hxge_get_config_properties(hxgep);
5183dec9fcdSqs 	if (status != HXGE_OK) {
5193dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "get_hw create failed"));
5203dec9fcdSqs 		goto hxge_attach_fail;
5213dec9fcdSqs 	}
5233dec9fcdSqs 	/*
5243dec9fcdSqs 	 * Setup the Kstats for the driver.
5253dec9fcdSqs 	 */
5263dec9fcdSqs 	hxge_setup_kstats(hxgep);
5273dec9fcdSqs 	hxge_setup_param(hxgep);
5293dec9fcdSqs 	status = hxge_setup_system_dma_pages(hxgep);
5303dec9fcdSqs 	if (status != HXGE_OK) {
5313dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "set dma page failed"));
5323dec9fcdSqs 		goto hxge_attach_fail;
5333dec9fcdSqs 	}
5353dec9fcdSqs 	hxge_hw_id_init(hxgep);
5363dec9fcdSqs 	hxge_hw_init_niu_common(hxgep);
5383dec9fcdSqs 	status = hxge_setup_dev(hxgep);
5393dec9fcdSqs 	if (status != DDI_SUCCESS) {
5403dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set dev failed"));
5413dec9fcdSqs 		goto hxge_attach_fail;
5423dec9fcdSqs 	}
5443dec9fcdSqs 	status = hxge_add_intrs(hxgep);
5453dec9fcdSqs 	if (status != DDI_SUCCESS) {
5463dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "add_intr failed"));
5473dec9fcdSqs 		goto hxge_attach_fail;
5483dec9fcdSqs 	}
5503dec9fcdSqs 	/*
5513dec9fcdSqs 	 * Enable interrupts.
5523dec9fcdSqs 	 */
5533dec9fcdSqs 	hxge_intrs_enable(hxgep);
5553dec9fcdSqs 	if ((status = hxge_mac_register(hxgep)) != HXGE_OK) {
5563dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL,
5573dec9fcdSqs 		    "unable to register to mac layer (%d)", status));
5583dec9fcdSqs 		goto hxge_attach_fail;
5593dec9fcdSqs 	}
560a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	mac_link_update(hxgep->mach, LINK_STATE_UNKNOWN);
5623dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "registered to mac (instance %d)",
5633dec9fcdSqs 	    instance));
5653dec9fcdSqs 	goto hxge_attach_exit;
5673dec9fcdSqs hxge_attach_fail:
5683dec9fcdSqs 	hxge_unattach(hxgep);
5693dec9fcdSqs 	goto hxge_attach_fail1;
5713dec9fcdSqs hxge_attach_fail5:
5723dec9fcdSqs 	/*
5733dec9fcdSqs 	 * Tear down the ndd parameters setup.
5743dec9fcdSqs 	 */
5753dec9fcdSqs 	hxge_destroy_param(hxgep);
5773dec9fcdSqs 	/*
5783dec9fcdSqs 	 * Tear down the kstat setup.
5793dec9fcdSqs 	 */
5803dec9fcdSqs 	hxge_destroy_kstats(hxgep);
5823dec9fcdSqs hxge_attach_fail4:
5833dec9fcdSqs 	if (hxgep->hxge_hw_p) {
5843dec9fcdSqs 		hxge_uninit_common_dev(hxgep);
5853dec9fcdSqs 		hxgep->hxge_hw_p = NULL;
5863dec9fcdSqs 	}
5873dec9fcdSqs hxge_attach_fail3:
5883dec9fcdSqs 	/*
5893dec9fcdSqs 	 * Unmap the register setup.
5903dec9fcdSqs 	 */
5913dec9fcdSqs 	hxge_unmap_regs(hxgep);
5933dec9fcdSqs 	hxge_fm_fini(hxgep);
5953dec9fcdSqs hxge_attach_fail2:
5963dec9fcdSqs 	ddi_soft_state_free(hxge_list, hxgep->instance);
5983dec9fcdSqs hxge_attach_fail1:
5993dec9fcdSqs 	if (status != HXGE_OK)
6003dec9fcdSqs 		status = (HXGE_ERROR | HXGE_DDI_FAILED);
6013dec9fcdSqs 	hxgep = NULL;
6033dec9fcdSqs hxge_attach_exit:
6043dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_attach status = 0x%08x",
6053dec9fcdSqs 	    status));
6073dec9fcdSqs 	return (status);
6083dec9fcdSqs }
6103dec9fcdSqs static int
hxge_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)6113dec9fcdSqs hxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
6123dec9fcdSqs {
6133dec9fcdSqs 	int		status = DDI_SUCCESS;
6143dec9fcdSqs 	int		instance;
6153dec9fcdSqs 	p_hxge_t	hxgep = NULL;
6173dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_detach"));
6183dec9fcdSqs 	instance = ddi_get_instance(dip);
6193dec9fcdSqs 	hxgep = ddi_get_soft_state(hxge_list, instance);
6203dec9fcdSqs 	if (hxgep == NULL) {
6213dec9fcdSqs 		status = DDI_FAILURE;
6223dec9fcdSqs 		goto hxge_detach_exit;
6233dec9fcdSqs 	}
6253dec9fcdSqs 	switch (cmd) {
6263dec9fcdSqs 	case DDI_DETACH:
6273dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_DETACH"));
6283dec9fcdSqs 		break;
6303dec9fcdSqs 	case DDI_PM_SUSPEND:
6313dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
6323dec9fcdSqs 		hxgep->suspended = DDI_PM_SUSPEND;
6333dec9fcdSqs 		hxge_suspend(hxgep);
6343dec9fcdSqs 		break;
6363dec9fcdSqs 	case DDI_SUSPEND:
6373dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_SUSPEND"));
6383dec9fcdSqs 		if (hxgep->suspended != DDI_PM_SUSPEND) {
6393dec9fcdSqs 			hxgep->suspended = DDI_SUSPEND;
6403dec9fcdSqs 			hxge_suspend(hxgep);
6413dec9fcdSqs 		}
6423dec9fcdSqs 		break;
6443dec9fcdSqs 	default:
6453dec9fcdSqs 		status = DDI_FAILURE;
6463dec9fcdSqs 		break;
6473dec9fcdSqs 	}
6493dec9fcdSqs 	if (cmd != DDI_DETACH)
6503dec9fcdSqs 		goto hxge_detach_exit;
6523dec9fcdSqs 	/*
6533dec9fcdSqs 	 * Stop the xcvr polling.
6543dec9fcdSqs 	 */
6553dec9fcdSqs 	hxgep->suspended = cmd;
6573dec9fcdSqs 	if (hxgep->mach && (status = mac_unregister(hxgep->mach)) != 0) {
6583dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
6593dec9fcdSqs 		    "<== hxge_detach status = 0x%08X", status));
6603dec9fcdSqs 		return (DDI_FAILURE);
6613dec9fcdSqs 	}
6623dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
6633dec9fcdSqs 	    "<== hxge_detach (mac_unregister) status = 0x%08X", status));
6653dec9fcdSqs 	hxge_unattach(hxgep);
6663dec9fcdSqs 	hxgep = NULL;
6683dec9fcdSqs hxge_detach_exit:
6693dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_detach status = 0x%08X",
6703dec9fcdSqs 	    status));
6723dec9fcdSqs 	return (status);
6733dec9fcdSqs }
6753dec9fcdSqs static void
hxge_unattach(p_hxge_t hxgep)6763dec9fcdSqs hxge_unattach(p_hxge_t hxgep)
6773dec9fcdSqs {
6783dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unattach"));
6803dec9fcdSqs 	if (hxgep == NULL || hxgep->dev_regs == NULL) {
6813dec9fcdSqs 		return;
6823dec9fcdSqs 	}
6843dec9fcdSqs 	if (hxgep->hxge_hw_p) {
6853dec9fcdSqs 		hxge_uninit_common_dev(hxgep);
6863dec9fcdSqs 		hxgep->hxge_hw_p = NULL;
6873dec9fcdSqs 	}
6893dec9fcdSqs 	if (hxgep->hxge_timerid) {
6903dec9fcdSqs 		hxge_stop_timer(hxgep, hxgep->hxge_timerid);
6913dec9fcdSqs 		hxgep->hxge_timerid = 0;
6923dec9fcdSqs 	}
694f043ebedSMichael Speer 	/* Stop interrupts. */
695f043ebedSMichael Speer 	hxge_intrs_disable(hxgep);
696f043ebedSMichael Speer 
6973dec9fcdSqs 	/* Stop any further interrupts. */
6983dec9fcdSqs 	hxge_remove_intrs(hxgep);
7003dec9fcdSqs 	/* Stop the device and free resources. */
7013dec9fcdSqs 	hxge_destroy_dev(hxgep);
7033dec9fcdSqs 	/* Tear down the ndd parameters setup. */
7043dec9fcdSqs 	hxge_destroy_param(hxgep);
7063dec9fcdSqs 	/* Tear down the kstat setup. */
7073dec9fcdSqs 	hxge_destroy_kstats(hxgep);
7093dec9fcdSqs 	/*
7103dec9fcdSqs 	 * Remove the list of ndd parameters which were setup during attach.
7113dec9fcdSqs 	 */
7123dec9fcdSqs 	if (hxgep->dip) {
7133dec9fcdSqs 		HXGE_DEBUG_MSG((hxgep, OBP_CTL,
7143dec9fcdSqs 		    " hxge_unattach: remove all properties"));
7153dec9fcdSqs 		(void) ddi_prop_remove_all(hxgep->dip);
7163dec9fcdSqs 	}
718fe930412Sqs 	/*
719fe930412Sqs 	 * Reset RDC, TDC, PFC, and VMAC blocks from PEU to clear any
720fe930412Sqs 	 * previous state before unmapping the registers.
721fe930412Sqs 	 */
722fe930412Sqs 	HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E);
723fe930412Sqs 	HXGE_DELAY(1000);
7253dec9fcdSqs 	/*
7263dec9fcdSqs 	 * Unmap the register setup.
7273dec9fcdSqs 	 */
7283dec9fcdSqs 	hxge_unmap_regs(hxgep);
7303dec9fcdSqs 	hxge_fm_fini(hxgep);
732a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	/* Destroy all mutexes.  */
733a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	hxge_destroy_mutexes(hxgep);
734a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 
7353dec9fcdSqs 	/*
7363dec9fcdSqs 	 * Free the soft state data structures allocated with this instance.
7373dec9fcdSqs 	 */
7383dec9fcdSqs 	ddi_soft_state_free(hxge_list, hxgep->instance);
7403dec9fcdSqs 	HXGE_DEBUG_MSG((NULL, DDI_CTL, "<== hxge_unattach"));
7413dec9fcdSqs }
7433dec9fcdSqs static hxge_status_t
hxge_map_regs(p_hxge_t hxgep)7443dec9fcdSqs hxge_map_regs(p_hxge_t hxgep)
7453dec9fcdSqs {
7463dec9fcdSqs 	int		ddi_status = DDI_SUCCESS;
7473dec9fcdSqs 	p_dev_regs_t	dev_regs;
7493dec9fcdSqs #ifdef	HXGE_DEBUG
7503dec9fcdSqs 	char		*sysname;
7513dec9fcdSqs #endif
7533dec9fcdSqs 	off_t		regsize;
7543dec9fcdSqs 	hxge_status_t	status = HXGE_OK;
7553dec9fcdSqs 	int		nregs;
7573dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_map_regs"));
7593dec9fcdSqs 	if (ddi_dev_nregs(hxgep->dip, &nregs) != DDI_SUCCESS)
7603dec9fcdSqs 		return (HXGE_ERROR);
7623dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_regs: nregs: %d", nregs));
7643dec9fcdSqs 	hxgep->dev_regs = NULL;
7653dec9fcdSqs 	dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP);
7663dec9fcdSqs 	dev_regs->hxge_regh = NULL;
7673dec9fcdSqs 	dev_regs->hxge_pciregh = NULL;
7683dec9fcdSqs 	dev_regs->hxge_msix_regh = NULL;
7703dec9fcdSqs 	(void) ddi_dev_regsize(hxgep->dip, 0, &regsize);
7713dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7723dec9fcdSqs 	    "hxge_map_regs: pci config size 0x%x", regsize));
7743dec9fcdSqs 	ddi_status = ddi_regs_map_setup(hxgep->dip, 0,
7753dec9fcdSqs 	    (caddr_t *)&(dev_regs->hxge_pciregp), 0, 0,
7763dec9fcdSqs 	    &hxge_dev_reg_acc_attr, &dev_regs->hxge_pciregh);
7773dec9fcdSqs 	if (ddi_status != DDI_SUCCESS) {
7783dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
7793dec9fcdSqs 		    "ddi_map_regs, hxge bus config regs failed"));
7803dec9fcdSqs 		goto hxge_map_regs_fail0;
7813dec9fcdSqs 	}
7833dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7843dec9fcdSqs 	    "hxge_map_reg: PCI config addr 0x%0llx handle 0x%0llx",
7853dec9fcdSqs 	    dev_regs->hxge_pciregp,
7863dec9fcdSqs 	    dev_regs->hxge_pciregh));
7883dec9fcdSqs 	(void) ddi_dev_regsize(hxgep->dip, 1, &regsize);
7893dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7903dec9fcdSqs 	    "hxge_map_regs: pio size 0x%x", regsize));
7923dec9fcdSqs 	/* set up the device mapped register */
7933dec9fcdSqs 	ddi_status = ddi_regs_map_setup(hxgep->dip, 1,
7943dec9fcdSqs 	    (caddr_t *)&(dev_regs->hxge_regp), 0, 0,
7953dec9fcdSqs 	    &hxge_dev_reg_acc_attr, &dev_regs->hxge_regh);
7973dec9fcdSqs 	if (ddi_status != DDI_SUCCESS) {
7983dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
7993dec9fcdSqs 		    "ddi_map_regs for Hydra global reg failed"));
8003dec9fcdSqs 		goto hxge_map_regs_fail1;
8013dec9fcdSqs 	}
8033dec9fcdSqs 	/* set up the msi/msi-x mapped register */
8043dec9fcdSqs 	(void) ddi_dev_regsize(hxgep->dip, 2, &regsize);
8053dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8063dec9fcdSqs 	    "hxge_map_regs: msix size 0x%x", regsize));
8083dec9fcdSqs 	ddi_status = ddi_regs_map_setup(hxgep->dip, 2,
8093dec9fcdSqs 	    (caddr_t *)&(dev_regs->hxge_msix_regp), 0, 0,
8103dec9fcdSqs 	    &hxge_dev_reg_acc_attr, &dev_regs->hxge_msix_regh);
8123dec9fcdSqs 	if (ddi_status != DDI_SUCCESS) {
8133dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
8143dec9fcdSqs 		    "ddi_map_regs for msi reg failed"));
8153dec9fcdSqs 		goto hxge_map_regs_fail2;
8163dec9fcdSqs 	}
8183dec9fcdSqs 	hxgep->dev_regs = dev_regs;
8203dec9fcdSqs 	HPI_PCI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_pciregh);
8213dec9fcdSqs 	HPI_PCI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_pciregp);
8223dec9fcdSqs 	HPI_MSI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_msix_regh);
8233dec9fcdSqs 	HPI_MSI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_msix_regp);
8253dec9fcdSqs 	HPI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
8263dec9fcdSqs 	HPI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
8283dec9fcdSqs 	HPI_REG_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
8293dec9fcdSqs 	HPI_REG_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
8313dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_reg: hardware addr 0x%0llx "
8323dec9fcdSqs 	    " handle 0x%0llx", dev_regs->hxge_regp, dev_regs->hxge_regh));
8343dec9fcdSqs 	goto hxge_map_regs_exit;
8363dec9fcdSqs hxge_map_regs_fail3:
8373dec9fcdSqs 	if (dev_regs->hxge_msix_regh) {
8383dec9fcdSqs 		ddi_regs_map_free(&dev_regs->hxge_msix_regh);
8393dec9fcdSqs 	}
8413dec9fcdSqs hxge_map_regs_fail2:
8423dec9fcdSqs 	if (dev_regs->hxge_regh) {
8433dec9fcdSqs 		ddi_regs_map_free(&dev_regs->hxge_regh);
8443dec9fcdSqs 	}
8463dec9fcdSqs hxge_map_regs_fail1:
8473dec9fcdSqs 	if (dev_regs->hxge_pciregh) {
8483dec9fcdSqs 		ddi_regs_map_free(&dev_regs->hxge_pciregh);
8493dec9fcdSqs 	}
8513dec9fcdSqs hxge_map_regs_fail0:
8523dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "Freeing register set memory"));
8533dec9fcdSqs 	kmem_free(dev_regs, sizeof (dev_regs_t));
8553dec9fcdSqs hxge_map_regs_exit:
8563dec9fcdSqs 	if (ddi_status != DDI_SUCCESS)
8573dec9fcdSqs 		status |= (HXGE_ERROR | HXGE_DDI_FAILED);
8583dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_map_regs"));
8593dec9fcdSqs 	return (status);
8603dec9fcdSqs }
8623dec9fcdSqs static void
hxge_unmap_regs(p_hxge_t hxgep)8633dec9fcdSqs hxge_unmap_regs(p_hxge_t hxgep)
8643dec9fcdSqs {
8653dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unmap_regs"));
8663dec9fcdSqs 	if (hxgep->dev_regs) {
8673dec9fcdSqs 		if (hxgep->dev_regs->hxge_pciregh) {
8683dec9fcdSqs 			HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8693dec9fcdSqs 			    "==> hxge_unmap_regs: bus"));
8703dec9fcdSqs 			ddi_regs_map_free(&hxgep->dev_regs->hxge_pciregh);
8713dec9fcdSqs 			hxgep->dev_regs->hxge_pciregh = NULL;
8723dec9fcdSqs 		}
8743dec9fcdSqs 		if (hxgep->dev_regs->hxge_regh) {
8753dec9fcdSqs 			HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8763dec9fcdSqs 			    "==> hxge_unmap_regs: device registers"));
8773dec9fcdSqs 			ddi_regs_map_free(&hxgep->dev_regs->hxge_regh);
8783dec9fcdSqs 			hxgep->dev_regs->hxge_regh = NULL;
8793dec9fcdSqs 		}
8813dec9fcdSqs 		if (hxgep->dev_regs->hxge_msix_regh) {
8823dec9fcdSqs 			HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8833dec9fcdSqs 			    "==> hxge_unmap_regs: device interrupts"));
8843dec9fcdSqs 			ddi_regs_map_free(&hxgep->dev_regs->hxge_msix_regh);
8853dec9fcdSqs 			hxgep->dev_regs->hxge_msix_regh = NULL;
8863dec9fcdSqs 		}
8873dec9fcdSqs 		kmem_free(hxgep->dev_regs, sizeof (dev_regs_t));
8883dec9fcdSqs 		hxgep->dev_regs = NULL;
8893dec9fcdSqs 	}
8903dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_unmap_regs"));
8913dec9fcdSqs }
8933dec9fcdSqs static hxge_status_t
hxge_setup_mutexes(p_hxge_t hxgep)8943dec9fcdSqs hxge_setup_mutexes(p_hxge_t hxgep)
8953dec9fcdSqs {
8963dec9fcdSqs 	int		ddi_status = DDI_SUCCESS;
8973dec9fcdSqs 	hxge_status_t	status = HXGE_OK;
8993dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_mutexes"));
9013dec9fcdSqs 	/*
9023dec9fcdSqs 	 * Get the interrupt cookie so the mutexes can be Initialised.
9033dec9fcdSqs 	 */
9043dec9fcdSqs 	ddi_status = ddi_get_iblock_cookie(hxgep->dip, 0,
9053dec9fcdSqs 	    &hxgep->interrupt_cookie);
9073dec9fcdSqs 	if (ddi_status != DDI_SUCCESS) {
9083dec9fcdSqs 		HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
9093dec9fcdSqs 		    "<== hxge_setup_mutexes: failed 0x%x", ddi_status));
9103dec9fcdSqs 		goto hxge_setup_mutexes_exit;
9113dec9fcdSqs 	}
9133dec9fcdSqs 	/*
9143dec9fcdSqs 	 * Initialize mutex's for this device.
9153dec9fcdSqs 	 */
9163dec9fcdSqs 	MUTEX_INIT(hxgep->genlock, NULL,
9173dec9fcdSqs 	    MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9186ffca240SMichael Speer 	MUTEX_INIT(&hxgep->vmac_lock, NULL,
9196ffca240SMichael Speer 	    MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9203dec9fcdSqs 	MUTEX_INIT(&hxgep->ouraddr_lock, NULL,
9213dec9fcdSqs 	    MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9223dec9fcdSqs 	RW_INIT(&hxgep->filter_lock, NULL,
9233dec9fcdSqs 	    RW_DRIVER, (void *) hxgep->interrupt_cookie);
924fe930412Sqs 	MUTEX_INIT(&hxgep->pio_lock, NULL,
925fe930412Sqs 	    MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
926a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	MUTEX_INIT(&hxgep->timeout.lock, NULL,
927a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States 	    MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9293dec9fcdSqs hxge_setup_mutexes_exit:
9303dec9fcdSqs 	HXGE_DEBUG_MSG((hxgep, DDI_CTL,
9313dec9fcdSqs 	    "<== hxge_setup_mutexes status = %x", status))&#