13dec9fcdSqs /*
23dec9fcdSqs * CDDL HEADER START
33dec9fcdSqs *
43dec9fcdSqs * The contents of this file are subject to the terms of the
53dec9fcdSqs * Common Development and Distribution License (the "License").
63dec9fcdSqs * You may not use this file except in compliance with the License.
73dec9fcdSqs *
83dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
93dec9fcdSqs * or http://www.opensolaris.org/os/licensing.
103dec9fcdSqs * See the License for the specific language governing permissions
113dec9fcdSqs * and limitations under the License.
123dec9fcdSqs *
133dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each
143dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
153dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the
163dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying
173dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner]
183dec9fcdSqs *
193dec9fcdSqs * CDDL HEADER END
203dec9fcdSqs */
213dec9fcdSqs /*
220dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
233dec9fcdSqs * Use is subject to license terms.
24b97d6ca7SMilan Jurik * Copyright 2012 Milan Jurik. All rights reserved.
25238d8f47SDale Ghent * Copyright 2016 OmniTI Computer Consulting, Inc. All rights reserved.
263dec9fcdSqs */
273dec9fcdSqs
283dec9fcdSqs /*
293dec9fcdSqs * SunOs MT STREAMS Hydra 10Gb Ethernet Device Driver.
303dec9fcdSqs */
313dec9fcdSqs #include <hxge_impl.h>
323dec9fcdSqs #include <hxge_pfc.h>
333dec9fcdSqs
343dec9fcdSqs /*
353dec9fcdSqs * PSARC/2007/453 MSI-X interrupt limit override
363dec9fcdSqs * (This PSARC case is limited to MSI-X vectors
373dec9fcdSqs * and SPARC platforms only).
383dec9fcdSqs */
391ed83081SMichael Speer uint32_t hxge_msi_enable = 2;
403dec9fcdSqs
413dec9fcdSqs /*
423dec9fcdSqs * Globals: tunable parameters (/etc/system or adb)
433dec9fcdSqs *
443dec9fcdSqs */
453dec9fcdSqs uint32_t hxge_rbr_size = HXGE_RBR_RBB_DEFAULT;
463dec9fcdSqs uint32_t hxge_rbr_spare_size = 0;
473dec9fcdSqs uint32_t hxge_rcr_size = HXGE_RCR_DEFAULT;
483dec9fcdSqs uint32_t hxge_tx_ring_size = HXGE_TX_RING_DEFAULT;
493dec9fcdSqs uint32_t hxge_bcopy_thresh = TX_BCOPY_MAX;
503dec9fcdSqs uint32_t hxge_dvma_thresh = TX_FASTDVMA_MIN;
513dec9fcdSqs uint32_t hxge_dma_stream_thresh = TX_STREAM_MIN;
52a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint32_t hxge_jumbo_frame_size = MAX_FRAME_SIZE;
533dec9fcdSqs
543dec9fcdSqs static hxge_os_mutex_t hxgedebuglock;
553dec9fcdSqs static int hxge_debug_init = 0;
563dec9fcdSqs
573dec9fcdSqs /*
583dec9fcdSqs * Debugging flags:
593dec9fcdSqs * hxge_no_tx_lb : transmit load balancing
603dec9fcdSqs * hxge_tx_lb_policy: 0 - TCP/UDP port (default)
613dec9fcdSqs * 1 - From the Stack
623dec9fcdSqs * 2 - Destination IP Address
633dec9fcdSqs */
643dec9fcdSqs uint32_t hxge_no_tx_lb = 0;
653dec9fcdSqs uint32_t hxge_tx_lb_policy = HXGE_TX_LB_TCPUDP;
663dec9fcdSqs
673dec9fcdSqs /*
683dec9fcdSqs * Tunables to manage the receive buffer blocks.
693dec9fcdSqs *
703dec9fcdSqs * hxge_rx_threshold_hi: copy all buffers.
713dec9fcdSqs * hxge_rx_bcopy_size_type: receive buffer block size type.
723dec9fcdSqs * hxge_rx_threshold_lo: copy only up to tunable block size type.
733dec9fcdSqs */
74f043ebedSMichael Speer #if defined(__sparc)
75f043ebedSMichael Speer hxge_rxbuf_threshold_t hxge_rx_threshold_hi = HXGE_RX_COPY_6;
76f043ebedSMichael Speer hxge_rxbuf_threshold_t hxge_rx_threshold_lo = HXGE_RX_COPY_4;
77f043ebedSMichael Speer #else
7857c5371aSQiyan Sun - Sun Microsystems - San Diego United States hxge_rxbuf_threshold_t hxge_rx_threshold_hi = HXGE_RX_COPY_NONE;
7957c5371aSQiyan Sun - Sun Microsystems - San Diego United States hxge_rxbuf_threshold_t hxge_rx_threshold_lo = HXGE_RX_COPY_NONE;
80f043ebedSMichael Speer #endif
81f043ebedSMichael Speer hxge_rxbuf_type_t hxge_rx_buf_size_type = RCR_PKTBUFSZ_0;
823dec9fcdSqs
833dec9fcdSqs rtrace_t hpi_rtracebuf;
843dec9fcdSqs
853dec9fcdSqs /*
863dec9fcdSqs * Function Prototypes
873dec9fcdSqs */
883dec9fcdSqs static int hxge_attach(dev_info_t *, ddi_attach_cmd_t);
893dec9fcdSqs static int hxge_detach(dev_info_t *, ddi_detach_cmd_t);
903dec9fcdSqs static void hxge_unattach(p_hxge_t);
913dec9fcdSqs
923dec9fcdSqs static hxge_status_t hxge_setup_system_dma_pages(p_hxge_t);
933dec9fcdSqs
943dec9fcdSqs static hxge_status_t hxge_setup_mutexes(p_hxge_t);
953dec9fcdSqs static void hxge_destroy_mutexes(p_hxge_t);
963dec9fcdSqs
973dec9fcdSqs static hxge_status_t hxge_map_regs(p_hxge_t hxgep);
983dec9fcdSqs static void hxge_unmap_regs(p_hxge_t hxgep);
993dec9fcdSqs
100f043ebedSMichael Speer static hxge_status_t hxge_add_intrs(p_hxge_t hxgep);
1013dec9fcdSqs static void hxge_remove_intrs(p_hxge_t hxgep);
1023dec9fcdSqs static hxge_status_t hxge_add_intrs_adv(p_hxge_t hxgep);
1033dec9fcdSqs static hxge_status_t hxge_add_intrs_adv_type(p_hxge_t, uint32_t);
1043dec9fcdSqs static hxge_status_t hxge_add_intrs_adv_type_fix(p_hxge_t, uint32_t);
105f043ebedSMichael Speer static void hxge_intrs_enable(p_hxge_t hxgep);
1063dec9fcdSqs static void hxge_intrs_disable(p_hxge_t hxgep);
1073dec9fcdSqs static void hxge_suspend(p_hxge_t);
1083dec9fcdSqs static hxge_status_t hxge_resume(p_hxge_t);
109f043ebedSMichael Speer static hxge_status_t hxge_setup_dev(p_hxge_t);
1103dec9fcdSqs static void hxge_destroy_dev(p_hxge_t);
111f043ebedSMichael Speer static hxge_status_t hxge_alloc_mem_pool(p_hxge_t);
1123dec9fcdSqs static void hxge_free_mem_pool(p_hxge_t);
1133dec9fcdSqs static hxge_status_t hxge_alloc_rx_mem_pool(p_hxge_t);
1143dec9fcdSqs static void hxge_free_rx_mem_pool(p_hxge_t);
1153dec9fcdSqs static hxge_status_t hxge_alloc_tx_mem_pool(p_hxge_t);
1163dec9fcdSqs static void hxge_free_tx_mem_pool(p_hxge_t);
1173dec9fcdSqs static hxge_status_t hxge_dma_mem_alloc(p_hxge_t, dma_method_t,
1183dec9fcdSqs struct ddi_dma_attr *, size_t, ddi_device_acc_attr_t *, uint_t,
1193dec9fcdSqs p_hxge_dma_common_t);
1203dec9fcdSqs static void hxge_dma_mem_free(p_hxge_dma_common_t);
1213dec9fcdSqs static hxge_status_t hxge_alloc_rx_buf_dma(p_hxge_t, uint16_t,
1223dec9fcdSqs p_hxge_dma_common_t *, size_t, size_t, uint32_t *);
1233dec9fcdSqs static void hxge_free_rx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
1243dec9fcdSqs static hxge_status_t hxge_alloc_rx_cntl_dma(p_hxge_t, uint16_t,
1258ad8db65SMichael Speer p_hxge_dma_common_t *, struct ddi_dma_attr *, size_t);
1263dec9fcdSqs static void hxge_free_rx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
1273dec9fcdSqs static hxge_status_t hxge_alloc_tx_buf_dma(p_hxge_t, uint16_t,
1283dec9fcdSqs p_hxge_dma_common_t *, size_t, size_t, uint32_t *);
1293dec9fcdSqs static void hxge_free_tx_buf_dma(p_hxge_t, p_hxge_dma_common_t, uint32_t);
1303dec9fcdSqs static hxge_status_t hxge_alloc_tx_cntl_dma(p_hxge_t, uint16_t,
1313dec9fcdSqs p_hxge_dma_common_t *, size_t);
1323dec9fcdSqs static void hxge_free_tx_cntl_dma(p_hxge_t, p_hxge_dma_common_t);
1333dec9fcdSqs static int hxge_init_common_dev(p_hxge_t);
1343dec9fcdSqs static void hxge_uninit_common_dev(p_hxge_t);
1353dec9fcdSqs
1363dec9fcdSqs /*
1373dec9fcdSqs * The next declarations are for the GLDv3 interface.
1383dec9fcdSqs */
1393dec9fcdSqs static int hxge_m_start(void *);
1403dec9fcdSqs static void hxge_m_stop(void *);
1413dec9fcdSqs static int hxge_m_multicst(void *, boolean_t, const uint8_t *);
1423dec9fcdSqs static int hxge_m_promisc(void *, boolean_t);
1433dec9fcdSqs static void hxge_m_ioctl(void *, queue_t *, mblk_t *);
1443dec9fcdSqs static hxge_status_t hxge_mac_register(p_hxge_t hxgep);
1453dec9fcdSqs
1463dec9fcdSqs static boolean_t hxge_m_getcapab(void *, mac_capab_t, void *);
147a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static boolean_t hxge_param_locked(mac_prop_id_t pr_num);
148a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
149a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint_t pr_valsize, const void *pr_val);
150a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
151a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint_t pr_valsize, void *pr_val);
1520dc2366fSVenugopal Iyer static void hxge_m_propinfo(void *barg, const char *pr_name,
1530dc2366fSVenugopal Iyer mac_prop_id_t pr_num, mac_prop_info_handle_t mph);
154a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_set_priv_prop(p_hxge_t hxgep, const char *pr_name,
155a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint_t pr_valsize, const void *pr_val);
156a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int hxge_get_priv_prop(p_hxge_t hxgep, const char *pr_name,
1570dc2366fSVenugopal Iyer uint_t pr_valsize, void *pr_val);
158a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_link_poll(void *arg);
159e5d97391SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_link_update(p_hxge_t hxge, link_state_t state);
1601c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States static void hxge_msix_init(p_hxge_t hxgep);
161a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
1620dc2366fSVenugopal Iyer char *hxge_priv_props[] = {
1630dc2366fSVenugopal Iyer "_rxdma_intr_time",
1640dc2366fSVenugopal Iyer "_rxdma_intr_pkts",
1650dc2366fSVenugopal Iyer "_class_opt_ipv4_tcp",
1660dc2366fSVenugopal Iyer "_class_opt_ipv4_udp",
1670dc2366fSVenugopal Iyer "_class_opt_ipv4_ah",
1680dc2366fSVenugopal Iyer "_class_opt_ipv4_sctp",
1690dc2366fSVenugopal Iyer "_class_opt_ipv6_tcp",
1700dc2366fSVenugopal Iyer "_class_opt_ipv6_udp",
1710dc2366fSVenugopal Iyer "_class_opt_ipv6_ah",
1720dc2366fSVenugopal Iyer "_class_opt_ipv6_sctp",
1730dc2366fSVenugopal Iyer NULL
174a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States };
175a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
176a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_MAX_PRIV_PROPS \
177a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (sizeof (hxge_priv_props)/sizeof (mac_priv_prop_t))
1783dec9fcdSqs
1793dec9fcdSqs #define HXGE_MAGIC 0x4E584745UL
1803dec9fcdSqs #define MAX_DUMP_SZ 256
1813dec9fcdSqs
182a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_M_CALLBACK_FLAGS \
1830dc2366fSVenugopal Iyer (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
1843dec9fcdSqs
1853dec9fcdSqs extern hxge_status_t hxge_pfc_set_default_mac_addr(p_hxge_t hxgep);
1863dec9fcdSqs
1873dec9fcdSqs static mac_callbacks_t hxge_m_callbacks = {
1883dec9fcdSqs HXGE_M_CALLBACK_FLAGS,
1893dec9fcdSqs hxge_m_stat,
1903dec9fcdSqs hxge_m_start,
1913dec9fcdSqs hxge_m_stop,
1923dec9fcdSqs hxge_m_promisc,
1933dec9fcdSqs hxge_m_multicst,
1941ed83081SMichael Speer NULL,
1951ed83081SMichael Speer NULL,
1960dc2366fSVenugopal Iyer NULL,
1973dec9fcdSqs hxge_m_ioctl,
198a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_m_getcapab,
199a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States NULL,
200a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States NULL,
201a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_m_setprop,
2020dc2366fSVenugopal Iyer hxge_m_getprop,
2030dc2366fSVenugopal Iyer hxge_m_propinfo
2043dec9fcdSqs };
2053dec9fcdSqs
20657c5371aSQiyan Sun - Sun Microsystems - San Diego United States /* PSARC/2007/453 MSI-X interrupt limit override. */
20757c5371aSQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_MSIX_REQUEST_10G 8
20857c5371aSQiyan Sun - Sun Microsystems - San Diego United States static int hxge_create_msi_property(p_hxge_t);
20957c5371aSQiyan Sun - Sun Microsystems - San Diego United States
2103dec9fcdSqs /* Enable debug messages as necessary. */
211a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint64_t hxge_debug_level = 0;
2123dec9fcdSqs
2133dec9fcdSqs /*
2143dec9fcdSqs * This list contains the instance structures for the Hydra
2153dec9fcdSqs * devices present in the system. The lock exists to guarantee
2163dec9fcdSqs * mutually exclusive access to the list.
2173dec9fcdSqs */
2183dec9fcdSqs void *hxge_list = NULL;
2193dec9fcdSqs void *hxge_hw_list = NULL;
2203dec9fcdSqs hxge_os_mutex_t hxge_common_lock;
2213dec9fcdSqs
2223dec9fcdSqs extern uint64_t hpi_debug_level;
2233dec9fcdSqs
224b97d6ca7SMilan Jurik extern hxge_status_t hxge_ldgv_init(p_hxge_t, int *, int *);
225b97d6ca7SMilan Jurik extern hxge_status_t hxge_ldgv_uninit(p_hxge_t);
226b97d6ca7SMilan Jurik extern hxge_status_t hxge_intr_ldgv_init(p_hxge_t);
2273dec9fcdSqs extern void hxge_fm_init(p_hxge_t hxgep, ddi_device_acc_attr_t *reg_attr,
228f043ebedSMichael Speer ddi_device_acc_attr_t *desc_attr, ddi_dma_attr_t *dma_attr);
2293dec9fcdSqs extern void hxge_fm_fini(p_hxge_t hxgep);
2303dec9fcdSqs
2313dec9fcdSqs /*
2323dec9fcdSqs * Count used to maintain the number of buffers being used
2333dec9fcdSqs * by Hydra instances and loaned up to the upper layers.
2343dec9fcdSqs */
2353dec9fcdSqs uint32_t hxge_mblks_pending = 0;
2363dec9fcdSqs
2373dec9fcdSqs /*
2383dec9fcdSqs * Device register access attributes for PIO.
2393dec9fcdSqs */
2403dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_reg_acc_attr = {
241f043ebedSMichael Speer DDI_DEVICE_ATTR_V0,
2423dec9fcdSqs DDI_STRUCTURE_LE_ACC,
2433dec9fcdSqs DDI_STRICTORDER_ACC,
2443dec9fcdSqs };
2453dec9fcdSqs
2463dec9fcdSqs /*
2473dec9fcdSqs * Device descriptor access attributes for DMA.
2483dec9fcdSqs */
2493dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_desc_dma_acc_attr = {
2503dec9fcdSqs DDI_DEVICE_ATTR_V0,
2513dec9fcdSqs DDI_STRUCTURE_LE_ACC,
2523dec9fcdSqs DDI_STRICTORDER_ACC
2533dec9fcdSqs };
2543dec9fcdSqs
2553dec9fcdSqs /*
2563dec9fcdSqs * Device buffer access attributes for DMA.
2573dec9fcdSqs */
2583dec9fcdSqs static ddi_device_acc_attr_t hxge_dev_buf_dma_acc_attr = {
2593dec9fcdSqs DDI_DEVICE_ATTR_V0,
2603dec9fcdSqs DDI_STRUCTURE_BE_ACC,
2613dec9fcdSqs DDI_STRICTORDER_ACC
2623dec9fcdSqs };
2633dec9fcdSqs
2648ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_rcr_desc_dma_attr = {
2658ad8db65SMichael Speer DMA_ATTR_V0, /* version number. */
2668ad8db65SMichael Speer 0, /* low address */
2678ad8db65SMichael Speer 0xffffffffffffffff, /* high address */
2688ad8db65SMichael Speer 0xffffffffffffffff, /* address counter max */
2698ad8db65SMichael Speer 0x80000, /* alignment */
2708ad8db65SMichael Speer 0xfc00fc, /* dlim_burstsizes */
2718ad8db65SMichael Speer 0x1, /* minimum transfer size */
2728ad8db65SMichael Speer 0xffffffffffffffff, /* maximum transfer size */
2738ad8db65SMichael Speer 0xffffffffffffffff, /* maximum segment size */
2748ad8db65SMichael Speer 1, /* scatter/gather list length */
2758ad8db65SMichael Speer (unsigned int)1, /* granularity */
2768ad8db65SMichael Speer 0 /* attribute flags */
2778ad8db65SMichael Speer };
2788ad8db65SMichael Speer
2798ad8db65SMichael Speer ddi_dma_attr_t hxge_tx_desc_dma_attr = {
2803dec9fcdSqs DMA_ATTR_V0, /* version number. */
2813dec9fcdSqs 0, /* low address */
2823dec9fcdSqs 0xffffffffffffffff, /* high address */
2833dec9fcdSqs 0xffffffffffffffff, /* address counter max */
2843dec9fcdSqs 0x100000, /* alignment */
2853dec9fcdSqs 0xfc00fc, /* dlim_burstsizes */
2863dec9fcdSqs 0x1, /* minimum transfer size */
2873dec9fcdSqs 0xffffffffffffffff, /* maximum transfer size */
2883dec9fcdSqs 0xffffffffffffffff, /* maximum segment size */
2893dec9fcdSqs 1, /* scatter/gather list length */
2903dec9fcdSqs (unsigned int)1, /* granularity */
2913dec9fcdSqs 0 /* attribute flags */
2923dec9fcdSqs };
2933dec9fcdSqs
2948ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_rbr_desc_dma_attr = {
2958ad8db65SMichael Speer DMA_ATTR_V0, /* version number. */
2968ad8db65SMichael Speer 0, /* low address */
2978ad8db65SMichael Speer 0xffffffffffffffff, /* high address */
2988ad8db65SMichael Speer 0xffffffffffffffff, /* address counter max */
2998ad8db65SMichael Speer 0x40000, /* alignment */
3008ad8db65SMichael Speer 0xfc00fc, /* dlim_burstsizes */
3018ad8db65SMichael Speer 0x1, /* minimum transfer size */
3028ad8db65SMichael Speer 0xffffffffffffffff, /* maximum transfer size */
3038ad8db65SMichael Speer 0xffffffffffffffff, /* maximum segment size */
3048ad8db65SMichael Speer 1, /* scatter/gather list length */
3058ad8db65SMichael Speer (unsigned int)1, /* granularity */
3068ad8db65SMichael Speer 0 /* attribute flags */
3078ad8db65SMichael Speer };
3088ad8db65SMichael Speer
3098ad8db65SMichael Speer ddi_dma_attr_t hxge_rx_mbox_dma_attr = {
3108ad8db65SMichael Speer DMA_ATTR_V0, /* version number. */
3118ad8db65SMichael Speer 0, /* low address */
3128ad8db65SMichael Speer 0xffffffffffffffff, /* high address */
3138ad8db65SMichael Speer 0xffffffffffffffff, /* address counter max */
3148ad8db65SMichael Speer #if defined(_BIG_ENDIAN)
3158ad8db65SMichael Speer 0x2000, /* alignment */
3168ad8db65SMichael Speer #else
3178ad8db65SMichael Speer 0x1000, /* alignment */
3188ad8db65SMichael Speer #endif
3198ad8db65SMichael Speer 0xfc00fc, /* dlim_burstsizes */
3208ad8db65SMichael Speer 0x1, /* minimum transfer size */
3218ad8db65SMichael Speer 0xffffffffffffffff, /* maximum transfer size */
3228ad8db65SMichael Speer 0xffffffffffffffff, /* maximum segment size */
3238ad8db65SMichael Speer 5, /* scatter/gather list length */
3248ad8db65SMichael Speer (unsigned int)1, /* granularity */
3258ad8db65SMichael Speer 0 /* attribute flags */
3268ad8db65SMichael Speer };
3278ad8db65SMichael Speer
3283dec9fcdSqs ddi_dma_attr_t hxge_tx_dma_attr = {
3293dec9fcdSqs DMA_ATTR_V0, /* version number. */
3303dec9fcdSqs 0, /* low address */
3313dec9fcdSqs 0xffffffffffffffff, /* high address */
3323dec9fcdSqs 0xffffffffffffffff, /* address counter max */
3333dec9fcdSqs #if defined(_BIG_ENDIAN)
3343dec9fcdSqs 0x2000, /* alignment */
3353dec9fcdSqs #else
3363dec9fcdSqs 0x1000, /* alignment */
3373dec9fcdSqs #endif
3383dec9fcdSqs 0xfc00fc, /* dlim_burstsizes */
3393dec9fcdSqs 0x1, /* minimum transfer size */
3403dec9fcdSqs 0xffffffffffffffff, /* maximum transfer size */
3413dec9fcdSqs 0xffffffffffffffff, /* maximum segment size */
3423dec9fcdSqs 5, /* scatter/gather list length */
3433dec9fcdSqs (unsigned int)1, /* granularity */
3443dec9fcdSqs 0 /* attribute flags */
3453dec9fcdSqs };
3463dec9fcdSqs
3473dec9fcdSqs ddi_dma_attr_t hxge_rx_dma_attr = {
3483dec9fcdSqs DMA_ATTR_V0, /* version number. */
3493dec9fcdSqs 0, /* low address */
3503dec9fcdSqs 0xffffffffffffffff, /* high address */
3513dec9fcdSqs 0xffffffffffffffff, /* address counter max */
3523dec9fcdSqs 0x10000, /* alignment */
3533dec9fcdSqs 0xfc00fc, /* dlim_burstsizes */
3543dec9fcdSqs 0x1, /* minimum transfer size */
3553dec9fcdSqs 0xffffffffffffffff, /* maximum transfer size */
3563dec9fcdSqs 0xffffffffffffffff, /* maximum segment size */
3573dec9fcdSqs 1, /* scatter/gather list length */
3583dec9fcdSqs (unsigned int)1, /* granularity */
3593dec9fcdSqs DDI_DMA_RELAXED_ORDERING /* attribute flags */
3603dec9fcdSqs };
3613dec9fcdSqs
3623dec9fcdSqs ddi_dma_lim_t hxge_dma_limits = {
3633dec9fcdSqs (uint_t)0, /* dlim_addr_lo */
3643dec9fcdSqs (uint_t)0xffffffff, /* dlim_addr_hi */
3653dec9fcdSqs (uint_t)0xffffffff, /* dlim_cntr_max */
3663dec9fcdSqs (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */
3673dec9fcdSqs 0x1, /* dlim_minxfer */
3683dec9fcdSqs 1024 /* dlim_speed */
3693dec9fcdSqs };
3703dec9fcdSqs
3713dec9fcdSqs dma_method_t hxge_force_dma = DVMA;
3723dec9fcdSqs
3733dec9fcdSqs /*
3743dec9fcdSqs * dma chunk sizes.
3753dec9fcdSqs *
3763dec9fcdSqs * Try to allocate the largest possible size
3773dec9fcdSqs * so that fewer number of dma chunks would be managed
3783dec9fcdSqs */
3793dec9fcdSqs size_t alloc_sizes[] = {
3803dec9fcdSqs 0x1000, 0x2000, 0x4000, 0x8000,
3813dec9fcdSqs 0x10000, 0x20000, 0x40000, 0x80000,
3823dec9fcdSqs 0x100000, 0x200000, 0x400000, 0x800000, 0x1000000
3833dec9fcdSqs };
3843dec9fcdSqs
3853dec9fcdSqs /*
3863dec9fcdSqs * Translate "dev_t" to a pointer to the associated "dev_info_t".
3873dec9fcdSqs */
3883dec9fcdSqs static int
hxge_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)3893dec9fcdSqs hxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
3903dec9fcdSqs {
3913dec9fcdSqs p_hxge_t hxgep = NULL;
3923dec9fcdSqs int instance;
3933dec9fcdSqs int status = DDI_SUCCESS;
3941ed83081SMichael Speer int i;
3953dec9fcdSqs
3963dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_attach"));
3973dec9fcdSqs
3983dec9fcdSqs /*
3993dec9fcdSqs * Get the device instance since we'll need to setup or retrieve a soft
4003dec9fcdSqs * state for this instance.
4013dec9fcdSqs */
4023dec9fcdSqs instance = ddi_get_instance(dip);
4033dec9fcdSqs
4043dec9fcdSqs switch (cmd) {
4053dec9fcdSqs case DDI_ATTACH:
4063dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_ATTACH"));
4073dec9fcdSqs break;
4083dec9fcdSqs
4093dec9fcdSqs case DDI_RESUME:
4103dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_RESUME"));
4113dec9fcdSqs hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
4123dec9fcdSqs if (hxgep == NULL) {
4133dec9fcdSqs status = DDI_FAILURE;
4143dec9fcdSqs break;
4153dec9fcdSqs }
4163dec9fcdSqs if (hxgep->dip != dip) {
4173dec9fcdSqs status = DDI_FAILURE;
4183dec9fcdSqs break;
4193dec9fcdSqs }
4203dec9fcdSqs if (hxgep->suspended == DDI_PM_SUSPEND) {
4213dec9fcdSqs status = ddi_dev_is_needed(hxgep->dip, 0, 1);
4223dec9fcdSqs } else {
4233dec9fcdSqs (void) hxge_resume(hxgep);
4243dec9fcdSqs }
4253dec9fcdSqs goto hxge_attach_exit;
4263dec9fcdSqs
4273dec9fcdSqs case DDI_PM_RESUME:
4283dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_RESUME"));
4293dec9fcdSqs hxgep = (p_hxge_t)ddi_get_soft_state(hxge_list, instance);
4303dec9fcdSqs if (hxgep == NULL) {
4313dec9fcdSqs status = DDI_FAILURE;
4323dec9fcdSqs break;
4333dec9fcdSqs }
4343dec9fcdSqs if (hxgep->dip != dip) {
4353dec9fcdSqs status = DDI_FAILURE;
4363dec9fcdSqs break;
4373dec9fcdSqs }
4383dec9fcdSqs (void) hxge_resume(hxgep);
4393dec9fcdSqs goto hxge_attach_exit;
4403dec9fcdSqs
4413dec9fcdSqs default:
4423dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing unknown"));
4433dec9fcdSqs status = DDI_FAILURE;
4443dec9fcdSqs goto hxge_attach_exit;
4453dec9fcdSqs }
4463dec9fcdSqs
4473dec9fcdSqs if (ddi_soft_state_zalloc(hxge_list, instance) == DDI_FAILURE) {
4483dec9fcdSqs status = DDI_FAILURE;
4493dec9fcdSqs HXGE_ERROR_MSG((hxgep, DDI_CTL,
4503dec9fcdSqs "ddi_soft_state_zalloc failed"));
4513dec9fcdSqs goto hxge_attach_exit;
4523dec9fcdSqs }
4533dec9fcdSqs
4543dec9fcdSqs hxgep = ddi_get_soft_state(hxge_list, instance);
4553dec9fcdSqs if (hxgep == NULL) {
4563dec9fcdSqs status = HXGE_ERROR;
4573dec9fcdSqs HXGE_ERROR_MSG((hxgep, DDI_CTL,
4583dec9fcdSqs "ddi_get_soft_state failed"));
4593dec9fcdSqs goto hxge_attach_fail2;
4603dec9fcdSqs }
4613dec9fcdSqs
4623dec9fcdSqs hxgep->drv_state = 0;
4633dec9fcdSqs hxgep->dip = dip;
4643dec9fcdSqs hxgep->instance = instance;
4653dec9fcdSqs hxgep->p_dip = ddi_get_parent(dip);
4663dec9fcdSqs hxgep->hxge_debug_level = hxge_debug_level;
4673dec9fcdSqs hpi_debug_level = hxge_debug_level;
4683dec9fcdSqs
4691ed83081SMichael Speer /*
4701ed83081SMichael Speer * Initialize MMAC struture.
4711ed83081SMichael Speer */
4721ed83081SMichael Speer (void) hxge_pfc_num_macs_get(hxgep, &hxgep->mmac.total);
4731ed83081SMichael Speer hxgep->mmac.available = hxgep->mmac.total;
4741ed83081SMichael Speer for (i = 0; i < hxgep->mmac.total; i++) {
4751ed83081SMichael Speer hxgep->mmac.addrs[i].set = B_FALSE;
4761ed83081SMichael Speer hxgep->mmac.addrs[i].primary = B_FALSE;
4771ed83081SMichael Speer }
4781ed83081SMichael Speer
479f043ebedSMichael Speer hxge_fm_init(hxgep, &hxge_dev_reg_acc_attr, &hxge_dev_desc_dma_acc_attr,
480f043ebedSMichael Speer &hxge_rx_dma_attr);
4813dec9fcdSqs
4823dec9fcdSqs status = hxge_map_regs(hxgep);
4833dec9fcdSqs if (status != HXGE_OK) {
4843dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "hxge_map_regs failed"));
4853dec9fcdSqs goto hxge_attach_fail3;
4863dec9fcdSqs }
4873dec9fcdSqs
4883dec9fcdSqs status = hxge_init_common_dev(hxgep);
4893dec9fcdSqs if (status != HXGE_OK) {
4903dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
4913dec9fcdSqs "hxge_init_common_dev failed"));
4923dec9fcdSqs goto hxge_attach_fail4;
4933dec9fcdSqs }
4943dec9fcdSqs
4953dec9fcdSqs /*
4963dec9fcdSqs * Setup the Ndd parameters for this instance.
4973dec9fcdSqs */
4983dec9fcdSqs hxge_init_param(hxgep);
4993dec9fcdSqs
5003dec9fcdSqs /*
5013dec9fcdSqs * Setup Register Tracing Buffer.
5023dec9fcdSqs */
5033dec9fcdSqs hpi_rtrace_buf_init((rtrace_t *)&hpi_rtracebuf);
5043dec9fcdSqs
5053dec9fcdSqs /* init stats ptr */
5063dec9fcdSqs hxge_init_statsp(hxgep);
5073dec9fcdSqs
508a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States status = hxge_setup_mutexes(hxgep);
509a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (status != HXGE_OK) {
510a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set mutex failed"));
511a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States goto hxge_attach_fail;
512a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
513a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
51423b519b2SMichael Speer /* Scrub the MSI-X memory */
51523b519b2SMichael Speer hxge_msix_init(hxgep);
51623b519b2SMichael Speer
5173dec9fcdSqs status = hxge_get_config_properties(hxgep);
5183dec9fcdSqs if (status != HXGE_OK) {
5193dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "get_hw create failed"));
5203dec9fcdSqs goto hxge_attach_fail;
5213dec9fcdSqs }
5223dec9fcdSqs
5233dec9fcdSqs /*
5243dec9fcdSqs * Setup the Kstats for the driver.
5253dec9fcdSqs */
5263dec9fcdSqs hxge_setup_kstats(hxgep);
5273dec9fcdSqs hxge_setup_param(hxgep);
5283dec9fcdSqs
5293dec9fcdSqs status = hxge_setup_system_dma_pages(hxgep);
5303dec9fcdSqs if (status != HXGE_OK) {
5313dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "set dma page failed"));
5323dec9fcdSqs goto hxge_attach_fail;
5333dec9fcdSqs }
5343dec9fcdSqs
5353dec9fcdSqs hxge_hw_id_init(hxgep);
5363dec9fcdSqs hxge_hw_init_niu_common(hxgep);
5373dec9fcdSqs
5383dec9fcdSqs status = hxge_setup_dev(hxgep);
5393dec9fcdSqs if (status != DDI_SUCCESS) {
5403dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "set dev failed"));
5413dec9fcdSqs goto hxge_attach_fail;
5423dec9fcdSqs }
5433dec9fcdSqs
5443dec9fcdSqs status = hxge_add_intrs(hxgep);
5453dec9fcdSqs if (status != DDI_SUCCESS) {
5463dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "add_intr failed"));
5473dec9fcdSqs goto hxge_attach_fail;
5483dec9fcdSqs }
5493dec9fcdSqs
5503dec9fcdSqs /*
5513dec9fcdSqs * Enable interrupts.
5523dec9fcdSqs */
5533dec9fcdSqs hxge_intrs_enable(hxgep);
5543dec9fcdSqs
5553dec9fcdSqs if ((status = hxge_mac_register(hxgep)) != HXGE_OK) {
5563dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
5573dec9fcdSqs "unable to register to mac layer (%d)", status));
5583dec9fcdSqs goto hxge_attach_fail;
5593dec9fcdSqs }
560a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States mac_link_update(hxgep->mach, LINK_STATE_UNKNOWN);
5613dec9fcdSqs
5623dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "registered to mac (instance %d)",
5633dec9fcdSqs instance));
5643dec9fcdSqs
5653dec9fcdSqs goto hxge_attach_exit;
5663dec9fcdSqs
5673dec9fcdSqs hxge_attach_fail:
5683dec9fcdSqs hxge_unattach(hxgep);
5693dec9fcdSqs goto hxge_attach_fail1;
5703dec9fcdSqs
5713dec9fcdSqs hxge_attach_fail5:
5723dec9fcdSqs /*
5733dec9fcdSqs * Tear down the ndd parameters setup.
5743dec9fcdSqs */
5753dec9fcdSqs hxge_destroy_param(hxgep);
5763dec9fcdSqs
5773dec9fcdSqs /*
5783dec9fcdSqs * Tear down the kstat setup.
5793dec9fcdSqs */
5803dec9fcdSqs hxge_destroy_kstats(hxgep);
5813dec9fcdSqs
5823dec9fcdSqs hxge_attach_fail4:
5833dec9fcdSqs if (hxgep->hxge_hw_p) {
5843dec9fcdSqs hxge_uninit_common_dev(hxgep);
5853dec9fcdSqs hxgep->hxge_hw_p = NULL;
5863dec9fcdSqs }
5873dec9fcdSqs hxge_attach_fail3:
5883dec9fcdSqs /*
5893dec9fcdSqs * Unmap the register setup.
5903dec9fcdSqs */
5913dec9fcdSqs hxge_unmap_regs(hxgep);
5923dec9fcdSqs
5933dec9fcdSqs hxge_fm_fini(hxgep);
5943dec9fcdSqs
5953dec9fcdSqs hxge_attach_fail2:
5963dec9fcdSqs ddi_soft_state_free(hxge_list, hxgep->instance);
5973dec9fcdSqs
5983dec9fcdSqs hxge_attach_fail1:
5993dec9fcdSqs if (status != HXGE_OK)
6003dec9fcdSqs status = (HXGE_ERROR | HXGE_DDI_FAILED);
6013dec9fcdSqs hxgep = NULL;
6023dec9fcdSqs
6033dec9fcdSqs hxge_attach_exit:
6043dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_attach status = 0x%08x",
6053dec9fcdSqs status));
6063dec9fcdSqs
6073dec9fcdSqs return (status);
6083dec9fcdSqs }
6093dec9fcdSqs
6103dec9fcdSqs static int
hxge_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)6113dec9fcdSqs hxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
6123dec9fcdSqs {
6133dec9fcdSqs int status = DDI_SUCCESS;
6143dec9fcdSqs int instance;
6153dec9fcdSqs p_hxge_t hxgep = NULL;
6163dec9fcdSqs
6173dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_detach"));
6183dec9fcdSqs instance = ddi_get_instance(dip);
6193dec9fcdSqs hxgep = ddi_get_soft_state(hxge_list, instance);
6203dec9fcdSqs if (hxgep == NULL) {
6213dec9fcdSqs status = DDI_FAILURE;
6223dec9fcdSqs goto hxge_detach_exit;
6233dec9fcdSqs }
6243dec9fcdSqs
6253dec9fcdSqs switch (cmd) {
6263dec9fcdSqs case DDI_DETACH:
6273dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_DETACH"));
6283dec9fcdSqs break;
6293dec9fcdSqs
6303dec9fcdSqs case DDI_PM_SUSPEND:
6313dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_PM_SUSPEND"));
6323dec9fcdSqs hxgep->suspended = DDI_PM_SUSPEND;
6333dec9fcdSqs hxge_suspend(hxgep);
6343dec9fcdSqs break;
6353dec9fcdSqs
6363dec9fcdSqs case DDI_SUSPEND:
6373dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "doing DDI_SUSPEND"));
6383dec9fcdSqs if (hxgep->suspended != DDI_PM_SUSPEND) {
6393dec9fcdSqs hxgep->suspended = DDI_SUSPEND;
6403dec9fcdSqs hxge_suspend(hxgep);
6413dec9fcdSqs }
6423dec9fcdSqs break;
6433dec9fcdSqs
6443dec9fcdSqs default:
6453dec9fcdSqs status = DDI_FAILURE;
6463dec9fcdSqs break;
6473dec9fcdSqs }
6483dec9fcdSqs
6493dec9fcdSqs if (cmd != DDI_DETACH)
6503dec9fcdSqs goto hxge_detach_exit;
6513dec9fcdSqs
6523dec9fcdSqs /*
6533dec9fcdSqs * Stop the xcvr polling.
6543dec9fcdSqs */
6553dec9fcdSqs hxgep->suspended = cmd;
6563dec9fcdSqs
6573dec9fcdSqs if (hxgep->mach && (status = mac_unregister(hxgep->mach)) != 0) {
6583dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
6593dec9fcdSqs "<== hxge_detach status = 0x%08X", status));
6603dec9fcdSqs return (DDI_FAILURE);
6613dec9fcdSqs }
6623dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
6633dec9fcdSqs "<== hxge_detach (mac_unregister) status = 0x%08X", status));
6643dec9fcdSqs
6653dec9fcdSqs hxge_unattach(hxgep);
6663dec9fcdSqs hxgep = NULL;
6673dec9fcdSqs
6683dec9fcdSqs hxge_detach_exit:
6693dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_detach status = 0x%08X",
6703dec9fcdSqs status));
6713dec9fcdSqs
6723dec9fcdSqs return (status);
6733dec9fcdSqs }
6743dec9fcdSqs
6753dec9fcdSqs static void
hxge_unattach(p_hxge_t hxgep)6763dec9fcdSqs hxge_unattach(p_hxge_t hxgep)
6773dec9fcdSqs {
6783dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unattach"));
6793dec9fcdSqs
6803dec9fcdSqs if (hxgep == NULL || hxgep->dev_regs == NULL) {
6813dec9fcdSqs return;
6823dec9fcdSqs }
6833dec9fcdSqs
6843dec9fcdSqs if (hxgep->hxge_hw_p) {
6853dec9fcdSqs hxge_uninit_common_dev(hxgep);
6863dec9fcdSqs hxgep->hxge_hw_p = NULL;
6873dec9fcdSqs }
6883dec9fcdSqs
6893dec9fcdSqs if (hxgep->hxge_timerid) {
6903dec9fcdSqs hxge_stop_timer(hxgep, hxgep->hxge_timerid);
6913dec9fcdSqs hxgep->hxge_timerid = 0;
6923dec9fcdSqs }
6933dec9fcdSqs
694f043ebedSMichael Speer /* Stop interrupts. */
695f043ebedSMichael Speer hxge_intrs_disable(hxgep);
696f043ebedSMichael Speer
6973dec9fcdSqs /* Stop any further interrupts. */
6983dec9fcdSqs hxge_remove_intrs(hxgep);
6993dec9fcdSqs
7003dec9fcdSqs /* Stop the device and free resources. */
7013dec9fcdSqs hxge_destroy_dev(hxgep);
7023dec9fcdSqs
7033dec9fcdSqs /* Tear down the ndd parameters setup. */
7043dec9fcdSqs hxge_destroy_param(hxgep);
7053dec9fcdSqs
7063dec9fcdSqs /* Tear down the kstat setup. */
7073dec9fcdSqs hxge_destroy_kstats(hxgep);
7083dec9fcdSqs
7093dec9fcdSqs /*
7103dec9fcdSqs * Remove the list of ndd parameters which were setup during attach.
7113dec9fcdSqs */
7123dec9fcdSqs if (hxgep->dip) {
7133dec9fcdSqs HXGE_DEBUG_MSG((hxgep, OBP_CTL,
7143dec9fcdSqs " hxge_unattach: remove all properties"));
7153dec9fcdSqs (void) ddi_prop_remove_all(hxgep->dip);
7163dec9fcdSqs }
7173dec9fcdSqs
718fe930412Sqs /*
719fe930412Sqs * Reset RDC, TDC, PFC, and VMAC blocks from PEU to clear any
720fe930412Sqs * previous state before unmapping the registers.
721fe930412Sqs */
722fe930412Sqs HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, 0x0000001E);
723fe930412Sqs HXGE_DELAY(1000);
724fe930412Sqs
7253dec9fcdSqs /*
7263dec9fcdSqs * Unmap the register setup.
7273dec9fcdSqs */
7283dec9fcdSqs hxge_unmap_regs(hxgep);
7293dec9fcdSqs
7303dec9fcdSqs hxge_fm_fini(hxgep);
7313dec9fcdSqs
732a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* Destroy all mutexes. */
733a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_destroy_mutexes(hxgep);
734a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
7353dec9fcdSqs /*
7363dec9fcdSqs * Free the soft state data structures allocated with this instance.
7373dec9fcdSqs */
7383dec9fcdSqs ddi_soft_state_free(hxge_list, hxgep->instance);
7393dec9fcdSqs
7403dec9fcdSqs HXGE_DEBUG_MSG((NULL, DDI_CTL, "<== hxge_unattach"));
7413dec9fcdSqs }
7423dec9fcdSqs
7433dec9fcdSqs static hxge_status_t
hxge_map_regs(p_hxge_t hxgep)7443dec9fcdSqs hxge_map_regs(p_hxge_t hxgep)
7453dec9fcdSqs {
7463dec9fcdSqs int ddi_status = DDI_SUCCESS;
7473dec9fcdSqs p_dev_regs_t dev_regs;
7483dec9fcdSqs
7493dec9fcdSqs #ifdef HXGE_DEBUG
7503dec9fcdSqs char *sysname;
7513dec9fcdSqs #endif
7523dec9fcdSqs
7533dec9fcdSqs off_t regsize;
7543dec9fcdSqs hxge_status_t status = HXGE_OK;
7553dec9fcdSqs int nregs;
7563dec9fcdSqs
7573dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_map_regs"));
7583dec9fcdSqs
7593dec9fcdSqs if (ddi_dev_nregs(hxgep->dip, &nregs) != DDI_SUCCESS)
7603dec9fcdSqs return (HXGE_ERROR);
7613dec9fcdSqs
7623dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_regs: nregs: %d", nregs));
7633dec9fcdSqs
7643dec9fcdSqs hxgep->dev_regs = NULL;
7653dec9fcdSqs dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP);
7663dec9fcdSqs dev_regs->hxge_regh = NULL;
7673dec9fcdSqs dev_regs->hxge_pciregh = NULL;
7683dec9fcdSqs dev_regs->hxge_msix_regh = NULL;
7693dec9fcdSqs
7703dec9fcdSqs (void) ddi_dev_regsize(hxgep->dip, 0, ®size);
7713dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7723dec9fcdSqs "hxge_map_regs: pci config size 0x%x", regsize));
7733dec9fcdSqs
7743dec9fcdSqs ddi_status = ddi_regs_map_setup(hxgep->dip, 0,
7753dec9fcdSqs (caddr_t *)&(dev_regs->hxge_pciregp), 0, 0,
7763dec9fcdSqs &hxge_dev_reg_acc_attr, &dev_regs->hxge_pciregh);
7773dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
7783dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
7793dec9fcdSqs "ddi_map_regs, hxge bus config regs failed"));
7803dec9fcdSqs goto hxge_map_regs_fail0;
7813dec9fcdSqs }
7823dec9fcdSqs
7833dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7843dec9fcdSqs "hxge_map_reg: PCI config addr 0x%0llx handle 0x%0llx",
7853dec9fcdSqs dev_regs->hxge_pciregp,
7863dec9fcdSqs dev_regs->hxge_pciregh));
7873dec9fcdSqs
7883dec9fcdSqs (void) ddi_dev_regsize(hxgep->dip, 1, ®size);
7893dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
7903dec9fcdSqs "hxge_map_regs: pio size 0x%x", regsize));
7913dec9fcdSqs
7923dec9fcdSqs /* set up the device mapped register */
7933dec9fcdSqs ddi_status = ddi_regs_map_setup(hxgep->dip, 1,
7943dec9fcdSqs (caddr_t *)&(dev_regs->hxge_regp), 0, 0,
7953dec9fcdSqs &hxge_dev_reg_acc_attr, &dev_regs->hxge_regh);
7963dec9fcdSqs
7973dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
7983dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
7993dec9fcdSqs "ddi_map_regs for Hydra global reg failed"));
8003dec9fcdSqs goto hxge_map_regs_fail1;
8013dec9fcdSqs }
8023dec9fcdSqs
8033dec9fcdSqs /* set up the msi/msi-x mapped register */
8043dec9fcdSqs (void) ddi_dev_regsize(hxgep->dip, 2, ®size);
8053dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8063dec9fcdSqs "hxge_map_regs: msix size 0x%x", regsize));
8073dec9fcdSqs
8083dec9fcdSqs ddi_status = ddi_regs_map_setup(hxgep->dip, 2,
8093dec9fcdSqs (caddr_t *)&(dev_regs->hxge_msix_regp), 0, 0,
8103dec9fcdSqs &hxge_dev_reg_acc_attr, &dev_regs->hxge_msix_regh);
8113dec9fcdSqs
8123dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
8133dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
8143dec9fcdSqs "ddi_map_regs for msi reg failed"));
8153dec9fcdSqs goto hxge_map_regs_fail2;
8163dec9fcdSqs }
8173dec9fcdSqs
8183dec9fcdSqs hxgep->dev_regs = dev_regs;
8193dec9fcdSqs
8203dec9fcdSqs HPI_PCI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_pciregh);
8213dec9fcdSqs HPI_PCI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_pciregp);
8223dec9fcdSqs HPI_MSI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_msix_regh);
8233dec9fcdSqs HPI_MSI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_msix_regp);
8243dec9fcdSqs
8253dec9fcdSqs HPI_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
8263dec9fcdSqs HPI_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
8273dec9fcdSqs
8283dec9fcdSqs HPI_REG_ACC_HANDLE_SET(hxgep, dev_regs->hxge_regh);
8293dec9fcdSqs HPI_REG_ADD_HANDLE_SET(hxgep, (hpi_reg_ptr_t)dev_regs->hxge_regp);
8303dec9fcdSqs
8313dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "hxge_map_reg: hardware addr 0x%0llx "
8323dec9fcdSqs " handle 0x%0llx", dev_regs->hxge_regp, dev_regs->hxge_regh));
8333dec9fcdSqs
8343dec9fcdSqs goto hxge_map_regs_exit;
8353dec9fcdSqs
8363dec9fcdSqs hxge_map_regs_fail3:
8373dec9fcdSqs if (dev_regs->hxge_msix_regh) {
8383dec9fcdSqs ddi_regs_map_free(&dev_regs->hxge_msix_regh);
8393dec9fcdSqs }
8403dec9fcdSqs
8413dec9fcdSqs hxge_map_regs_fail2:
8423dec9fcdSqs if (dev_regs->hxge_regh) {
8433dec9fcdSqs ddi_regs_map_free(&dev_regs->hxge_regh);
8443dec9fcdSqs }
8453dec9fcdSqs
8463dec9fcdSqs hxge_map_regs_fail1:
8473dec9fcdSqs if (dev_regs->hxge_pciregh) {
8483dec9fcdSqs ddi_regs_map_free(&dev_regs->hxge_pciregh);
8493dec9fcdSqs }
8503dec9fcdSqs
8513dec9fcdSqs hxge_map_regs_fail0:
8523dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "Freeing register set memory"));
8533dec9fcdSqs kmem_free(dev_regs, sizeof (dev_regs_t));
8543dec9fcdSqs
8553dec9fcdSqs hxge_map_regs_exit:
8563dec9fcdSqs if (ddi_status != DDI_SUCCESS)
8573dec9fcdSqs status |= (HXGE_ERROR | HXGE_DDI_FAILED);
8583dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_map_regs"));
8593dec9fcdSqs return (status);
8603dec9fcdSqs }
8613dec9fcdSqs
8623dec9fcdSqs static void
hxge_unmap_regs(p_hxge_t hxgep)8633dec9fcdSqs hxge_unmap_regs(p_hxge_t hxgep)
8643dec9fcdSqs {
8653dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_unmap_regs"));
8663dec9fcdSqs if (hxgep->dev_regs) {
8673dec9fcdSqs if (hxgep->dev_regs->hxge_pciregh) {
8683dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8693dec9fcdSqs "==> hxge_unmap_regs: bus"));
8703dec9fcdSqs ddi_regs_map_free(&hxgep->dev_regs->hxge_pciregh);
8713dec9fcdSqs hxgep->dev_regs->hxge_pciregh = NULL;
8723dec9fcdSqs }
8733dec9fcdSqs
8743dec9fcdSqs if (hxgep->dev_regs->hxge_regh) {
8753dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8763dec9fcdSqs "==> hxge_unmap_regs: device registers"));
8773dec9fcdSqs ddi_regs_map_free(&hxgep->dev_regs->hxge_regh);
8783dec9fcdSqs hxgep->dev_regs->hxge_regh = NULL;
8793dec9fcdSqs }
8803dec9fcdSqs
8813dec9fcdSqs if (hxgep->dev_regs->hxge_msix_regh) {
8823dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
8833dec9fcdSqs "==> hxge_unmap_regs: device interrupts"));
8843dec9fcdSqs ddi_regs_map_free(&hxgep->dev_regs->hxge_msix_regh);
8853dec9fcdSqs hxgep->dev_regs->hxge_msix_regh = NULL;
8863dec9fcdSqs }
8873dec9fcdSqs kmem_free(hxgep->dev_regs, sizeof (dev_regs_t));
8883dec9fcdSqs hxgep->dev_regs = NULL;
8893dec9fcdSqs }
8903dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_unmap_regs"));
8913dec9fcdSqs }
8923dec9fcdSqs
8933dec9fcdSqs static hxge_status_t
hxge_setup_mutexes(p_hxge_t hxgep)8943dec9fcdSqs hxge_setup_mutexes(p_hxge_t hxgep)
8953dec9fcdSqs {
8963dec9fcdSqs int ddi_status = DDI_SUCCESS;
8973dec9fcdSqs hxge_status_t status = HXGE_OK;
8983dec9fcdSqs
8993dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_mutexes"));
9003dec9fcdSqs
9013dec9fcdSqs /*
9023dec9fcdSqs * Get the interrupt cookie so the mutexes can be Initialised.
9033dec9fcdSqs */
9043dec9fcdSqs ddi_status = ddi_get_iblock_cookie(hxgep->dip, 0,
9053dec9fcdSqs &hxgep->interrupt_cookie);
9063dec9fcdSqs
9073dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
9083dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
9093dec9fcdSqs "<== hxge_setup_mutexes: failed 0x%x", ddi_status));
9103dec9fcdSqs goto hxge_setup_mutexes_exit;
9113dec9fcdSqs }
9123dec9fcdSqs
9133dec9fcdSqs /*
9143dec9fcdSqs * Initialize mutex's for this device.
9153dec9fcdSqs */
9163dec9fcdSqs MUTEX_INIT(hxgep->genlock, NULL,
9173dec9fcdSqs MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9186ffca240SMichael Speer MUTEX_INIT(&hxgep->vmac_lock, NULL,
9196ffca240SMichael Speer MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9203dec9fcdSqs MUTEX_INIT(&hxgep->ouraddr_lock, NULL,
9213dec9fcdSqs MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9223dec9fcdSqs RW_INIT(&hxgep->filter_lock, NULL,
9233dec9fcdSqs RW_DRIVER, (void *) hxgep->interrupt_cookie);
924fe930412Sqs MUTEX_INIT(&hxgep->pio_lock, NULL,
925fe930412Sqs MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
926a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_INIT(&hxgep->timeout.lock, NULL,
927a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_DRIVER, (void *) hxgep->interrupt_cookie);
9283dec9fcdSqs
9293dec9fcdSqs hxge_setup_mutexes_exit:
9303dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
9313dec9fcdSqs "<== hxge_setup_mutexes status = %x", status));
9323dec9fcdSqs
9333dec9fcdSqs if (ddi_status != DDI_SUCCESS)
9343dec9fcdSqs status |= (HXGE_ERROR | HXGE_DDI_FAILED);
9353dec9fcdSqs
9363dec9fcdSqs return (status);
9373dec9fcdSqs }
9383dec9fcdSqs
9393dec9fcdSqs static void
hxge_destroy_mutexes(p_hxge_t hxgep)9403dec9fcdSqs hxge_destroy_mutexes(p_hxge_t hxgep)
9413dec9fcdSqs {
9423dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_mutexes"));
9433dec9fcdSqs RW_DESTROY(&hxgep->filter_lock);
9446ffca240SMichael Speer MUTEX_DESTROY(&hxgep->vmac_lock);
9453dec9fcdSqs MUTEX_DESTROY(&hxgep->ouraddr_lock);
9463dec9fcdSqs MUTEX_DESTROY(hxgep->genlock);
947fe930412Sqs MUTEX_DESTROY(&hxgep->pio_lock);
948a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_DESTROY(&hxgep->timeout.lock);
9493dec9fcdSqs
9503dec9fcdSqs if (hxge_debug_init == 1) {
9513dec9fcdSqs MUTEX_DESTROY(&hxgedebuglock);
9523dec9fcdSqs hxge_debug_init = 0;
9533dec9fcdSqs }
9543dec9fcdSqs
9553dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_mutexes"));
9563dec9fcdSqs }
9573dec9fcdSqs
9583dec9fcdSqs hxge_status_t
hxge_init(p_hxge_t hxgep)9593dec9fcdSqs hxge_init(p_hxge_t hxgep)
9603dec9fcdSqs {
9613dec9fcdSqs hxge_status_t status = HXGE_OK;
9623dec9fcdSqs
9633dec9fcdSqs HXGE_DEBUG_MSG((hxgep, STR_CTL, "==> hxge_init"));
9643dec9fcdSqs
9653dec9fcdSqs if (hxgep->drv_state & STATE_HW_INITIALIZED) {
9663dec9fcdSqs return (status);
9673dec9fcdSqs }
9683dec9fcdSqs
9693dec9fcdSqs /*
9703dec9fcdSqs * Allocate system memory for the receive/transmit buffer blocks and
9713dec9fcdSqs * receive/transmit descriptor rings.
9723dec9fcdSqs */
9733dec9fcdSqs status = hxge_alloc_mem_pool(hxgep);
9743dec9fcdSqs if (status != HXGE_OK) {
9753dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "alloc mem failed\n"));
9763dec9fcdSqs goto hxge_init_fail1;
9773dec9fcdSqs }
9783dec9fcdSqs
9793dec9fcdSqs /*
9803dec9fcdSqs * Initialize and enable TXDMA channels.
9813dec9fcdSqs */
9823dec9fcdSqs status = hxge_init_txdma_channels(hxgep);
9833dec9fcdSqs if (status != HXGE_OK) {
9843dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init txdma failed\n"));
9853dec9fcdSqs goto hxge_init_fail3;
9863dec9fcdSqs }
9873dec9fcdSqs
9883dec9fcdSqs /*
9893dec9fcdSqs * Initialize and enable RXDMA channels.
9903dec9fcdSqs */
9913dec9fcdSqs status = hxge_init_rxdma_channels(hxgep);
9923dec9fcdSqs if (status != HXGE_OK) {
9933dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init rxdma failed\n"));
9943dec9fcdSqs goto hxge_init_fail4;
9953dec9fcdSqs }
9963dec9fcdSqs
9973dec9fcdSqs /*
9983dec9fcdSqs * Initialize TCAM
9993dec9fcdSqs */
10003dec9fcdSqs status = hxge_classify_init(hxgep);
10013dec9fcdSqs if (status != HXGE_OK) {
10023dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init classify failed\n"));
10033dec9fcdSqs goto hxge_init_fail5;
10043dec9fcdSqs }
10053dec9fcdSqs
10063dec9fcdSqs /*
10073dec9fcdSqs * Initialize the VMAC block.
10083dec9fcdSqs */
10093dec9fcdSqs status = hxge_vmac_init(hxgep);
10103dec9fcdSqs if (status != HXGE_OK) {
10113dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "init MAC failed\n"));
10123dec9fcdSqs goto hxge_init_fail5;
10133dec9fcdSqs }
10143dec9fcdSqs
10153dec9fcdSqs /* Bringup - this may be unnecessary when PXE and FCODE available */
10163dec9fcdSqs status = hxge_pfc_set_default_mac_addr(hxgep);
10173dec9fcdSqs if (status != HXGE_OK) {
10183dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
10193dec9fcdSqs "Default Address Failure\n"));
10203dec9fcdSqs goto hxge_init_fail5;
10213dec9fcdSqs }
10223dec9fcdSqs
10233dec9fcdSqs /*
10243dec9fcdSqs * Enable hardware interrupts.
10253dec9fcdSqs */
10263dec9fcdSqs hxge_intr_hw_enable(hxgep);
10273dec9fcdSqs hxgep->drv_state |= STATE_HW_INITIALIZED;
10283dec9fcdSqs
10293dec9fcdSqs goto hxge_init_exit;
10303dec9fcdSqs
10313dec9fcdSqs hxge_init_fail5:
10323dec9fcdSqs hxge_uninit_rxdma_channels(hxgep);
10333dec9fcdSqs hxge_init_fail4:
10343dec9fcdSqs hxge_uninit_txdma_channels(hxgep);
10353dec9fcdSqs hxge_init_fail3:
10363dec9fcdSqs hxge_free_mem_pool(hxgep);
10373dec9fcdSqs hxge_init_fail1:
10383dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
10393dec9fcdSqs "<== hxge_init status (failed) = 0x%08x", status));
10403dec9fcdSqs return (status);
10413dec9fcdSqs
10423dec9fcdSqs hxge_init_exit:
10433dec9fcdSqs
10443dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_init status = 0x%08x",
10453dec9fcdSqs status));
10463dec9fcdSqs
10473dec9fcdSqs return (status);
10483dec9fcdSqs }
10493dec9fcdSqs
10503dec9fcdSqs timeout_id_t
hxge_start_timer(p_hxge_t hxgep,fptrv_t func,int msec)10513dec9fcdSqs hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec)
10523dec9fcdSqs {
10533dec9fcdSqs if ((hxgep->suspended == 0) || (hxgep->suspended == DDI_RESUME)) {
10543dec9fcdSqs return (timeout(func, (caddr_t)hxgep,
10553dec9fcdSqs drv_usectohz(1000 * msec)));
10563dec9fcdSqs }
10573dec9fcdSqs return (NULL);
10583dec9fcdSqs }
10593dec9fcdSqs
10603dec9fcdSqs /*ARGSUSED*/
10613dec9fcdSqs void
hxge_stop_timer(p_hxge_t hxgep,timeout_id_t timerid)10623dec9fcdSqs hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid)
10633dec9fcdSqs {
10643dec9fcdSqs if (timerid) {
10653dec9fcdSqs (void) untimeout(timerid);
10663dec9fcdSqs }
10673dec9fcdSqs }
10683dec9fcdSqs
10693dec9fcdSqs void
hxge_uninit(p_hxge_t hxgep)10703dec9fcdSqs hxge_uninit(p_hxge_t hxgep)
10713dec9fcdSqs {
10723dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_uninit"));
10733dec9fcdSqs
10743dec9fcdSqs if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) {
10753dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
10763dec9fcdSqs "==> hxge_uninit: not initialized"));
10773dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_uninit"));
10783dec9fcdSqs return;
10793dec9fcdSqs }
10803dec9fcdSqs
10813dec9fcdSqs /* Stop timer */
10823dec9fcdSqs if (hxgep->hxge_timerid) {
10833dec9fcdSqs hxge_stop_timer(hxgep, hxgep->hxge_timerid);
10843dec9fcdSqs hxgep->hxge_timerid = 0;
10853dec9fcdSqs }
10863dec9fcdSqs
10873dec9fcdSqs (void) hxge_intr_hw_disable(hxgep);
10883dec9fcdSqs
10893dec9fcdSqs /* Reset the receive VMAC side. */
10903dec9fcdSqs (void) hxge_rx_vmac_disable(hxgep);
10913dec9fcdSqs
10923dec9fcdSqs /* Free classification resources */
10933dec9fcdSqs (void) hxge_classify_uninit(hxgep);
10943dec9fcdSqs
10953dec9fcdSqs /* Reset the transmit/receive DMA side. */
10963dec9fcdSqs (void) hxge_txdma_hw_mode(hxgep, HXGE_DMA_STOP);
10973dec9fcdSqs (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP);
10983dec9fcdSqs
10993dec9fcdSqs hxge_uninit_txdma_channels(hxgep);
11003dec9fcdSqs hxge_uninit_rxdma_channels(hxgep);
11013dec9fcdSqs
11023dec9fcdSqs /* Reset the transmit VMAC side. */
11033dec9fcdSqs (void) hxge_tx_vmac_disable(hxgep);
11043dec9fcdSqs
11053dec9fcdSqs hxge_free_mem_pool(hxgep);
11063dec9fcdSqs
11073dec9fcdSqs hxgep->drv_state &= ~STATE_HW_INITIALIZED;
11083dec9fcdSqs
11093dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_uninit"));
11103dec9fcdSqs }
11113dec9fcdSqs
11123dec9fcdSqs /*ARGSUSED*/
11133dec9fcdSqs /*VARARGS*/
11143dec9fcdSqs void
hxge_debug_msg(p_hxge_t hxgep,uint64_t level,char * fmt,...)11153dec9fcdSqs hxge_debug_msg(p_hxge_t hxgep, uint64_t level, char *fmt, ...)
11163dec9fcdSqs {
11173dec9fcdSqs char msg_buffer[1048];
11183dec9fcdSqs char prefix_buffer[32];
11193dec9fcdSqs int instance;
11203dec9fcdSqs uint64_t debug_level;
11213dec9fcdSqs int cmn_level = CE_CONT;
11223dec9fcdSqs va_list ap;
11233dec9fcdSqs
11243dec9fcdSqs debug_level = (hxgep == NULL) ? hxge_debug_level :
11253dec9fcdSqs hxgep->hxge_debug_level;
11263dec9fcdSqs
11273dec9fcdSqs if ((level & debug_level) || (level == HXGE_NOTE) ||
11283dec9fcdSqs (level == HXGE_ERR_CTL)) {
11293dec9fcdSqs /* do the msg processing */
11303dec9fcdSqs if (hxge_debug_init == 0) {
11313dec9fcdSqs MUTEX_INIT(&hxgedebuglock, NULL, MUTEX_DRIVER, NULL);
11323dec9fcdSqs hxge_debug_init = 1;
11333dec9fcdSqs }
11343dec9fcdSqs
11353dec9fcdSqs MUTEX_ENTER(&hxgedebuglock);
11363dec9fcdSqs
11373dec9fcdSqs if ((level & HXGE_NOTE)) {
11383dec9fcdSqs cmn_level = CE_NOTE;
11393dec9fcdSqs }
11403dec9fcdSqs
11413dec9fcdSqs if (level & HXGE_ERR_CTL) {
11423dec9fcdSqs cmn_level = CE_WARN;
11433dec9fcdSqs }
11443dec9fcdSqs
11453dec9fcdSqs va_start(ap, fmt);
11463dec9fcdSqs (void) vsprintf(msg_buffer, fmt, ap);
11473dec9fcdSqs va_end(ap);
11483dec9fcdSqs
11493dec9fcdSqs if (hxgep == NULL) {
11503dec9fcdSqs instance = -1;
11513dec9fcdSqs (void) sprintf(prefix_buffer, "%s :", "hxge");
11523dec9fcdSqs } else {
11533dec9fcdSqs instance = hxgep->instance;
11543dec9fcdSqs (void) sprintf(prefix_buffer,
11553dec9fcdSqs "%s%d :", "hxge", instance);
11563dec9fcdSqs }
11573dec9fcdSqs
11583dec9fcdSqs MUTEX_EXIT(&hxgedebuglock);
11593dec9fcdSqs cmn_err(cmn_level, "%s %s\n", prefix_buffer, msg_buffer);
11603dec9fcdSqs }
11613dec9fcdSqs }
11623dec9fcdSqs
11633dec9fcdSqs char *
hxge_dump_packet(char * addr,int size)11643dec9fcdSqs hxge_dump_packet(char *addr, int size)
11653dec9fcdSqs {
11663dec9fcdSqs uchar_t *ap = (uchar_t *)addr;
11673dec9fcdSqs int i;
11683dec9fcdSqs static char etherbuf[1024];
11693dec9fcdSqs char *cp = etherbuf;
11703dec9fcdSqs char digits[] = "0123456789abcdef";
11713dec9fcdSqs
11723dec9fcdSqs if (!size)
11733dec9fcdSqs size = 60;
11743dec9fcdSqs
11753dec9fcdSqs if (size > MAX_DUMP_SZ) {
11763dec9fcdSqs /* Dump the leading bytes */
11773dec9fcdSqs for (i = 0; i < MAX_DUMP_SZ / 2; i++) {
11783dec9fcdSqs if (*ap > 0x0f)
11793dec9fcdSqs *cp++ = digits[*ap >> 4];
11803dec9fcdSqs *cp++ = digits[*ap++ & 0xf];
11813dec9fcdSqs *cp++ = ':';
11823dec9fcdSqs }
11833dec9fcdSqs for (i = 0; i < 20; i++)
11843dec9fcdSqs *cp++ = '.';
11853dec9fcdSqs /* Dump the last MAX_DUMP_SZ/2 bytes */
11863dec9fcdSqs ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ / 2));
11873dec9fcdSqs for (i = 0; i < MAX_DUMP_SZ / 2; i++) {
11883dec9fcdSqs if (*ap > 0x0f)
11893dec9fcdSqs *cp++ = digits[*ap >> 4];
11903dec9fcdSqs *cp++ = digits[*ap++ & 0xf];
11913dec9fcdSqs *cp++ = ':';
11923dec9fcdSqs }
11933dec9fcdSqs } else {
11943dec9fcdSqs for (i = 0; i < size; i++) {
11953dec9fcdSqs if (*ap > 0x0f)
11963dec9fcdSqs *cp++ = digits[*ap >> 4];
11973dec9fcdSqs *cp++ = digits[*ap++ & 0xf];
11983dec9fcdSqs *cp++ = ':';
11993dec9fcdSqs }
12003dec9fcdSqs }
12013dec9fcdSqs *--cp = 0;
12023dec9fcdSqs return (etherbuf);
12033dec9fcdSqs }
12043dec9fcdSqs
12053dec9fcdSqs static void
hxge_suspend(p_hxge_t hxgep)12063dec9fcdSqs hxge_suspend(p_hxge_t hxgep)
12073dec9fcdSqs {
12083dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_suspend"));
12093dec9fcdSqs
12101c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States /*
12111c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States * Stop the link status timer before hxge_intrs_disable() to avoid
12121c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States * accessing the the MSIX table simultaneously. Note that the timer
12131c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States * routine polls for MSIX parity errors.
12141c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States */
1215a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_ENTER(&hxgep->timeout.lock);
1216a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (hxgep->timeout.id)
1217a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (void) untimeout(hxgep->timeout.id);
1218a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_EXIT(&hxgep->timeout.lock);
1219a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
12201c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States hxge_intrs_disable(hxgep);
12211c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States hxge_destroy_dev(hxgep);
12221c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
12233dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_suspend"));
12243dec9fcdSqs }
12253dec9fcdSqs
12263dec9fcdSqs static hxge_status_t
hxge_resume(p_hxge_t hxgep)12273dec9fcdSqs hxge_resume(p_hxge_t hxgep)
12283dec9fcdSqs {
12293dec9fcdSqs hxge_status_t status = HXGE_OK;
12303dec9fcdSqs
12313dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_resume"));
12323dec9fcdSqs hxgep->suspended = DDI_RESUME;
12333dec9fcdSqs
12343dec9fcdSqs (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_START);
12353dec9fcdSqs (void) hxge_txdma_hw_mode(hxgep, HXGE_DMA_START);
12363dec9fcdSqs
12373dec9fcdSqs (void) hxge_rx_vmac_enable(hxgep);
12383dec9fcdSqs (void) hxge_tx_vmac_enable(hxgep);
12393dec9fcdSqs
12403dec9fcdSqs hxge_intrs_enable(hxgep);
12413dec9fcdSqs
12423dec9fcdSqs hxgep->suspended = 0;
12433dec9fcdSqs
12441c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States /*
12451c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States * Resume the link status timer after hxge_intrs_enable to avoid
12461c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States * accessing MSIX table simultaneously.
12471c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States */
1248a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_ENTER(&hxgep->timeout.lock);
1249a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.id = timeout(hxge_link_poll, (void *)hxgep,
1250a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.ticks);
1251a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_EXIT(&hxgep->timeout.lock);
1252a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
12533dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
12543dec9fcdSqs "<== hxge_resume status = 0x%x", status));
12553dec9fcdSqs
12563dec9fcdSqs return (status);
12573dec9fcdSqs }
12583dec9fcdSqs
1259f043ebedSMichael Speer static hxge_status_t
hxge_setup_dev(p_hxge_t hxgep)12603dec9fcdSqs hxge_setup_dev(p_hxge_t hxgep)
12613dec9fcdSqs {
12623dec9fcdSqs hxge_status_t status = HXGE_OK;
12633dec9fcdSqs
12643dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_dev"));
12653dec9fcdSqs
12663dec9fcdSqs status = hxge_link_init(hxgep);
12673dec9fcdSqs if (fm_check_acc_handle(hxgep->dev_regs->hxge_regh) != DDI_FM_OK) {
12683dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
12693dec9fcdSqs "Bad register acc handle"));
12703dec9fcdSqs status = HXGE_ERROR;
12713dec9fcdSqs }
12723dec9fcdSqs
12733dec9fcdSqs if (status != HXGE_OK) {
12743dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MAC_CTL,
12753dec9fcdSqs " hxge_setup_dev status (link init 0x%08x)", status));
12763dec9fcdSqs goto hxge_setup_dev_exit;
12773dec9fcdSqs }
12783dec9fcdSqs
12793dec9fcdSqs hxge_setup_dev_exit:
12803dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
12813dec9fcdSqs "<== hxge_setup_dev status = 0x%08x", status));
12823dec9fcdSqs
12833dec9fcdSqs return (status);
12843dec9fcdSqs }
12853dec9fcdSqs
12863dec9fcdSqs static void
hxge_destroy_dev(p_hxge_t hxgep)12873dec9fcdSqs hxge_destroy_dev(p_hxge_t hxgep)
12883dec9fcdSqs {
12893dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_destroy_dev"));
12903dec9fcdSqs
12913dec9fcdSqs (void) hxge_hw_stop(hxgep);
12923dec9fcdSqs
12933dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_destroy_dev"));
12943dec9fcdSqs }
12953dec9fcdSqs
12963dec9fcdSqs static hxge_status_t
hxge_setup_system_dma_pages(p_hxge_t hxgep)12973dec9fcdSqs hxge_setup_system_dma_pages(p_hxge_t hxgep)
12983dec9fcdSqs {
12993dec9fcdSqs int ddi_status = DDI_SUCCESS;
13003dec9fcdSqs uint_t count;
13013dec9fcdSqs ddi_dma_cookie_t cookie;
13023dec9fcdSqs uint_t iommu_pagesize;
13033dec9fcdSqs hxge_status_t status = HXGE_OK;
13043dec9fcdSqs
13053dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_setup_system_dma_pages"));
13063dec9fcdSqs
13073dec9fcdSqs hxgep->sys_page_sz = ddi_ptob(hxgep->dip, (ulong_t)1);
13083dec9fcdSqs iommu_pagesize = dvma_pagesize(hxgep->dip);
13093dec9fcdSqs
13103dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
13113dec9fcdSqs " hxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
13123dec9fcdSqs " default_block_size %d iommu_pagesize %d",
13133dec9fcdSqs hxgep->sys_page_sz, ddi_ptob(hxgep->dip, (ulong_t)1),
13143dec9fcdSqs hxgep->rx_default_block_size, iommu_pagesize));
13153dec9fcdSqs
13163dec9fcdSqs if (iommu_pagesize != 0) {
13173dec9fcdSqs if (hxgep->sys_page_sz == iommu_pagesize) {
13183dec9fcdSqs /* Hydra support up to 8K pages */
13193dec9fcdSqs if (iommu_pagesize > 0x2000)
13203dec9fcdSqs hxgep->sys_page_sz = 0x2000;
13213dec9fcdSqs } else {
13223dec9fcdSqs if (hxgep->sys_page_sz > iommu_pagesize)
13233dec9fcdSqs hxgep->sys_page_sz = iommu_pagesize;
13243dec9fcdSqs }
13253dec9fcdSqs }
13263dec9fcdSqs
13273dec9fcdSqs hxgep->sys_page_mask = ~(hxgep->sys_page_sz - 1);
13283dec9fcdSqs
13293dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
13303dec9fcdSqs "==> hxge_setup_system_dma_pages: page %d (ddi_ptob %d) "
13313dec9fcdSqs "default_block_size %d page mask %d",
13323dec9fcdSqs hxgep->sys_page_sz, ddi_ptob(hxgep->dip, (ulong_t)1),
13333dec9fcdSqs hxgep->rx_default_block_size, hxgep->sys_page_mask));
13343dec9fcdSqs
13353dec9fcdSqs switch (hxgep->sys_page_sz) {
13363dec9fcdSqs default:
13373dec9fcdSqs hxgep->sys_page_sz = 0x1000;
13383dec9fcdSqs hxgep->sys_page_mask = ~(hxgep->sys_page_sz - 1);
13393dec9fcdSqs hxgep->rx_default_block_size = 0x1000;
13403dec9fcdSqs hxgep->rx_bksize_code = RBR_BKSIZE_4K;
13413dec9fcdSqs break;
13423dec9fcdSqs case 0x1000:
13433dec9fcdSqs hxgep->rx_default_block_size = 0x1000;
13443dec9fcdSqs hxgep->rx_bksize_code = RBR_BKSIZE_4K;
13453dec9fcdSqs break;
13463dec9fcdSqs case 0x2000:
13473dec9fcdSqs hxgep->rx_default_block_size = 0x2000;
13483dec9fcdSqs hxgep->rx_bksize_code = RBR_BKSIZE_8K;
13493dec9fcdSqs break;
13503dec9fcdSqs }
13513dec9fcdSqs
13523dec9fcdSqs hxge_rx_dma_attr.dma_attr_align = hxgep->sys_page_sz;
13533dec9fcdSqs hxge_tx_dma_attr.dma_attr_align = hxgep->sys_page_sz;
13543dec9fcdSqs
13553dec9fcdSqs /*
13563dec9fcdSqs * Get the system DMA burst size.
13573dec9fcdSqs */
13583dec9fcdSqs ddi_status = ddi_dma_alloc_handle(hxgep->dip, &hxge_tx_dma_attr,
13593dec9fcdSqs DDI_DMA_DONTWAIT, 0, &hxgep->dmasparehandle);
13603dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
13613dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
13623dec9fcdSqs "ddi_dma_alloc_handle: failed status 0x%x", ddi_status));
13633dec9fcdSqs goto hxge_get_soft_properties_exit;
13643dec9fcdSqs }
13653dec9fcdSqs
13663dec9fcdSqs ddi_status = ddi_dma_addr_bind_handle(hxgep->dmasparehandle, NULL,
13673dec9fcdSqs (caddr_t)hxgep->dmasparehandle, sizeof (hxgep->dmasparehandle),
13683dec9fcdSqs DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, 0,
13693dec9fcdSqs &cookie, &count);
13703dec9fcdSqs if (ddi_status != DDI_DMA_MAPPED) {
13713dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
13723dec9fcdSqs "Binding spare handle to find system burstsize failed."));
13733dec9fcdSqs ddi_status = DDI_FAILURE;
13743dec9fcdSqs goto hxge_get_soft_properties_fail1;
13753dec9fcdSqs }
13763dec9fcdSqs
13773dec9fcdSqs hxgep->sys_burst_sz = ddi_dma_burstsizes(hxgep->dmasparehandle);
13783dec9fcdSqs (void) ddi_dma_unbind_handle(hxgep->dmasparehandle);
13793dec9fcdSqs
13803dec9fcdSqs hxge_get_soft_properties_fail1:
13813dec9fcdSqs ddi_dma_free_handle(&hxgep->dmasparehandle);
13823dec9fcdSqs
13833dec9fcdSqs hxge_get_soft_properties_exit:
13843dec9fcdSqs
13853dec9fcdSqs if (ddi_status != DDI_SUCCESS)
13863dec9fcdSqs status |= (HXGE_ERROR | HXGE_DDI_FAILED);
13873dec9fcdSqs
13883dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
13893dec9fcdSqs "<== hxge_setup_system_dma_pages status = 0x%08x", status));
13903dec9fcdSqs
13913dec9fcdSqs return (status);
13923dec9fcdSqs }
13933dec9fcdSqs
1394f043ebedSMichael Speer static hxge_status_t
hxge_alloc_mem_pool(p_hxge_t hxgep)13953dec9fcdSqs hxge_alloc_mem_pool(p_hxge_t hxgep)
13963dec9fcdSqs {
13973dec9fcdSqs hxge_status_t status = HXGE_OK;
13983dec9fcdSqs
13993dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_alloc_mem_pool"));
14003dec9fcdSqs
14013dec9fcdSqs status = hxge_alloc_rx_mem_pool(hxgep);
14023dec9fcdSqs if (status != HXGE_OK) {
14033dec9fcdSqs return (HXGE_ERROR);
14043dec9fcdSqs }
14053dec9fcdSqs
14063dec9fcdSqs status = hxge_alloc_tx_mem_pool(hxgep);
14073dec9fcdSqs if (status != HXGE_OK) {
14083dec9fcdSqs hxge_free_rx_mem_pool(hxgep);
14093dec9fcdSqs return (HXGE_ERROR);
14103dec9fcdSqs }
14113dec9fcdSqs
14123dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_alloc_mem_pool"));
14133dec9fcdSqs return (HXGE_OK);
14143dec9fcdSqs }
14153dec9fcdSqs
14163dec9fcdSqs static void
hxge_free_mem_pool(p_hxge_t hxgep)14173dec9fcdSqs hxge_free_mem_pool(p_hxge_t hxgep)
14183dec9fcdSqs {
14193dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_mem_pool"));
14203dec9fcdSqs
14213dec9fcdSqs hxge_free_rx_mem_pool(hxgep);
14223dec9fcdSqs hxge_free_tx_mem_pool(hxgep);
14233dec9fcdSqs
14243dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_mem_pool"));
14253dec9fcdSqs }
14263dec9fcdSqs
14273dec9fcdSqs static hxge_status_t
hxge_alloc_rx_mem_pool(p_hxge_t hxgep)14283dec9fcdSqs hxge_alloc_rx_mem_pool(p_hxge_t hxgep)
14293dec9fcdSqs {
14303dec9fcdSqs int i, j;
14313dec9fcdSqs uint32_t ndmas, st_rdc;
14323dec9fcdSqs p_hxge_dma_pt_cfg_t p_all_cfgp;
14333dec9fcdSqs p_hxge_hw_pt_cfg_t p_cfgp;
14343dec9fcdSqs p_hxge_dma_pool_t dma_poolp;
14353dec9fcdSqs p_hxge_dma_common_t *dma_buf_p;
14368ad8db65SMichael Speer p_hxge_dma_pool_t dma_rbr_cntl_poolp;
14378ad8db65SMichael Speer p_hxge_dma_common_t *dma_rbr_cntl_p;
14388ad8db65SMichael Speer p_hxge_dma_pool_t dma_rcr_cntl_poolp;
14398ad8db65SMichael Speer p_hxge_dma_common_t *dma_rcr_cntl_p;
14408ad8db65SMichael Speer p_hxge_dma_pool_t dma_mbox_cntl_poolp;
14418ad8db65SMichael Speer p_hxge_dma_common_t *dma_mbox_cntl_p;
14423dec9fcdSqs size_t rx_buf_alloc_size;
14438ad8db65SMichael Speer size_t rx_rbr_cntl_alloc_size;
14448ad8db65SMichael Speer size_t rx_rcr_cntl_alloc_size;
14458ad8db65SMichael Speer size_t rx_mbox_cntl_alloc_size;
14463dec9fcdSqs uint32_t *num_chunks; /* per dma */
14473dec9fcdSqs hxge_status_t status = HXGE_OK;
14483dec9fcdSqs
14493dec9fcdSqs uint32_t hxge_port_rbr_size;
14503dec9fcdSqs uint32_t hxge_port_rbr_spare_size;
14513dec9fcdSqs uint32_t hxge_port_rcr_size;
14523dec9fcdSqs
14533dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_mem_pool"));
14543dec9fcdSqs
14553dec9fcdSqs p_all_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
14563dec9fcdSqs p_cfgp = (p_hxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
14573dec9fcdSqs st_rdc = p_cfgp->start_rdc;
14583dec9fcdSqs ndmas = p_cfgp->max_rdcs;
14593dec9fcdSqs
14603dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
14613dec9fcdSqs " hxge_alloc_rx_mem_pool st_rdc %d ndmas %d", st_rdc, ndmas));
14623dec9fcdSqs
14633dec9fcdSqs /*
14643dec9fcdSqs * Allocate memory for each receive DMA channel.
14653dec9fcdSqs */
14663dec9fcdSqs dma_poolp = (p_hxge_dma_pool_t)KMEM_ZALLOC(sizeof (hxge_dma_pool_t),
14673dec9fcdSqs KM_SLEEP);
14683dec9fcdSqs dma_buf_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
14693dec9fcdSqs sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
14703dec9fcdSqs
14718ad8db65SMichael Speer dma_rbr_cntl_poolp = (p_hxge_dma_pool_t)
14723dec9fcdSqs KMEM_ZALLOC(sizeof (hxge_dma_pool_t), KM_SLEEP);
14738ad8db65SMichael Speer dma_rbr_cntl_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
14748ad8db65SMichael Speer sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
14758ad8db65SMichael Speer dma_rcr_cntl_poolp = (p_hxge_dma_pool_t)
14768ad8db65SMichael Speer KMEM_ZALLOC(sizeof (hxge_dma_pool_t), KM_SLEEP);
14778ad8db65SMichael Speer dma_rcr_cntl_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
14788ad8db65SMichael Speer sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
14798ad8db65SMichael Speer dma_mbox_cntl_poolp = (p_hxge_dma_pool_t)
14808ad8db65SMichael Speer KMEM_ZALLOC(sizeof (hxge_dma_pool_t), KM_SLEEP);
14818ad8db65SMichael Speer dma_mbox_cntl_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
14823dec9fcdSqs sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
14833dec9fcdSqs
14843dec9fcdSqs num_chunks = (uint32_t *)KMEM_ZALLOC(sizeof (uint32_t) * ndmas,
14853dec9fcdSqs KM_SLEEP);
14863dec9fcdSqs
14873dec9fcdSqs /*
14883dec9fcdSqs * Assume that each DMA channel will be configured with default block
14893dec9fcdSqs * size. rbr block counts are mod of batch count (16).
14903dec9fcdSqs */
14913dec9fcdSqs hxge_port_rbr_size = p_all_cfgp->rbr_size;
14923dec9fcdSqs hxge_port_rcr_size = p_all_cfgp->rcr_size;
14933dec9fcdSqs
14943dec9fcdSqs if (!hxge_port_rbr_size) {
14953dec9fcdSqs hxge_port_rbr_size = HXGE_RBR_RBB_DEFAULT;
14963dec9fcdSqs }
14973dec9fcdSqs
14983dec9fcdSqs if (hxge_port_rbr_size % HXGE_RXDMA_POST_BATCH) {
14993dec9fcdSqs hxge_port_rbr_size = (HXGE_RXDMA_POST_BATCH *
15003dec9fcdSqs (hxge_port_rbr_size / HXGE_RXDMA_POST_BATCH + 1));
15013dec9fcdSqs }
15023dec9fcdSqs
15033dec9fcdSqs p_all_cfgp->rbr_size = hxge_port_rbr_size;
15043dec9fcdSqs hxge_port_rbr_spare_size = hxge_rbr_spare_size;
15053dec9fcdSqs
15063dec9fcdSqs if (hxge_port_rbr_spare_size % HXGE_RXDMA_POST_BATCH) {
15073dec9fcdSqs hxge_port_rbr_spare_size = (HXGE_RXDMA_POST_BATCH *
15083dec9fcdSqs (hxge_port_rbr_spare_size / HXGE_RXDMA_POST_BATCH + 1));
15093dec9fcdSqs }
15103dec9fcdSqs
15113dec9fcdSqs rx_buf_alloc_size = (hxgep->rx_default_block_size *
15123dec9fcdSqs (hxge_port_rbr_size + hxge_port_rbr_spare_size));
15133dec9fcdSqs
15143dec9fcdSqs /*
15153dec9fcdSqs * Addresses of receive block ring, receive completion ring and the
15163dec9fcdSqs * mailbox must be all cache-aligned (64 bytes).
15173dec9fcdSqs */
15188ad8db65SMichael Speer rx_rbr_cntl_alloc_size = hxge_port_rbr_size + hxge_port_rbr_spare_size;
15198ad8db65SMichael Speer rx_rbr_cntl_alloc_size *= sizeof (rx_desc_t);
15208ad8db65SMichael Speer rx_rcr_cntl_alloc_size = sizeof (rcr_entry_t) * hxge_port_rcr_size;
15218ad8db65SMichael Speer rx_mbox_cntl_alloc_size = sizeof (rxdma_mailbox_t);
15223dec9fcdSqs
15233dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_alloc_rx_mem_pool: "
15243dec9fcdSqs "hxge_port_rbr_size = %d hxge_port_rbr_spare_size = %d "
15253dec9fcdSqs "hxge_port_rcr_size = %d rx_cntl_alloc_size = %d",
15263dec9fcdSqs hxge_port_rbr_size, hxge_port_rbr_spare_size,
15273dec9fcdSqs hxge_port_rcr_size, rx_cntl_alloc_size));
15283dec9fcdSqs
15293dec9fcdSqs hxgep->hxge_port_rbr_size = hxge_port_rbr_size;
15303dec9fcdSqs hxgep->hxge_port_rcr_size = hxge_port_rcr_size;
15313dec9fcdSqs
15323dec9fcdSqs /*
15333dec9fcdSqs * Allocate memory for receive buffers and descriptor rings. Replace
15343dec9fcdSqs * allocation functions with interface functions provided by the
15353dec9fcdSqs * partition manager when it is available.
15363dec9fcdSqs */
15373dec9fcdSqs /*
15383dec9fcdSqs * Allocate memory for the receive buffer blocks.
15393dec9fcdSqs */
15403dec9fcdSqs for (i = 0; i < ndmas; i++) {
15413dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
15423dec9fcdSqs " hxge_alloc_rx_mem_pool to alloc mem: "
15433dec9fcdSqs " dma %d dma_buf_p %llx &dma_buf_p %llx",
15443dec9fcdSqs i, dma_buf_p[i], &dma_buf_p[i]));
15453dec9fcdSqs
15463dec9fcdSqs num_chunks[i] = 0;
15473dec9fcdSqs
15483dec9fcdSqs status = hxge_alloc_rx_buf_dma(hxgep, st_rdc, &dma_buf_p[i],
15493dec9fcdSqs rx_buf_alloc_size, hxgep->rx_default_block_size,
15503dec9fcdSqs &num_chunks[i]);
15513dec9fcdSqs if (status != HXGE_OK) {
15523dec9fcdSqs break;
15533dec9fcdSqs }
15543dec9fcdSqs
15553dec9fcdSqs st_rdc++;
15563dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
15573dec9fcdSqs " hxge_alloc_rx_mem_pool DONE alloc mem: "
15583dec9fcdSqs "dma %d dma_buf_p %llx &dma_buf_p %llx", i,
15593dec9fcdSqs dma_buf_p[i], &dma_buf_p[i]));
15603dec9fcdSqs }
15613dec9fcdSqs
15623dec9fcdSqs if (i < ndmas) {
15633dec9fcdSqs goto hxge_alloc_rx_mem_fail1;
15643dec9fcdSqs }
15653dec9fcdSqs
15663dec9fcdSqs /*
15673dec9fcdSqs * Allocate memory for descriptor rings and mailbox.
15683dec9fcdSqs */
15693dec9fcdSqs st_rdc = p_cfgp->start_rdc;
15703dec9fcdSqs for (j = 0; j < ndmas; j++) {
15718ad8db65SMichael Speer if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
15728ad8db65SMichael Speer &dma_rbr_cntl_p[j], &hxge_rx_rbr_desc_dma_attr,
15738ad8db65SMichael Speer rx_rbr_cntl_alloc_size)) != HXGE_OK) {
15748ad8db65SMichael Speer break;
15758ad8db65SMichael Speer }
15768ad8db65SMichael Speer
15778ad8db65SMichael Speer if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
15788ad8db65SMichael Speer &dma_rcr_cntl_p[j], &hxge_rx_rcr_desc_dma_attr,
15798ad8db65SMichael Speer rx_rcr_cntl_alloc_size)) != HXGE_OK) {
15808ad8db65SMichael Speer break;
15818ad8db65SMichael Speer }
15828ad8db65SMichael Speer
15838ad8db65SMichael Speer if ((status = hxge_alloc_rx_cntl_dma(hxgep, st_rdc,
15848ad8db65SMichael Speer &dma_mbox_cntl_p[j], &hxge_rx_mbox_dma_attr,
15858ad8db65SMichael Speer rx_mbox_cntl_alloc_size)) != HXGE_OK) {
15863dec9fcdSqs break;
15873dec9fcdSqs }
15883dec9fcdSqs st_rdc++;
15893dec9fcdSqs }
15903dec9fcdSqs
15913dec9fcdSqs if (j < ndmas) {
15923dec9fcdSqs goto hxge_alloc_rx_mem_fail2;
15933dec9fcdSqs }
15943dec9fcdSqs
15953dec9fcdSqs dma_poolp->ndmas = ndmas;
15963dec9fcdSqs dma_poolp->num_chunks = num_chunks;
15973dec9fcdSqs dma_poolp->buf_allocated = B_TRUE;
15983dec9fcdSqs hxgep->rx_buf_pool_p = dma_poolp;
15993dec9fcdSqs dma_poolp->dma_buf_pool_p = dma_buf_p;
16003dec9fcdSqs
16018ad8db65SMichael Speer dma_rbr_cntl_poolp->ndmas = ndmas;
16028ad8db65SMichael Speer dma_rbr_cntl_poolp->buf_allocated = B_TRUE;
16038ad8db65SMichael Speer hxgep->rx_rbr_cntl_pool_p = dma_rbr_cntl_poolp;
16048ad8db65SMichael Speer dma_rbr_cntl_poolp->dma_buf_pool_p = dma_rbr_cntl_p;
16058ad8db65SMichael Speer
16068ad8db65SMichael Speer dma_rcr_cntl_poolp->ndmas = ndmas;
16078ad8db65SMichael Speer dma_rcr_cntl_poolp->buf_allocated = B_TRUE;
16088ad8db65SMichael Speer hxgep->rx_rcr_cntl_pool_p = dma_rcr_cntl_poolp;
16098ad8db65SMichael Speer dma_rcr_cntl_poolp->dma_buf_pool_p = dma_rcr_cntl_p;
16108ad8db65SMichael Speer
16118ad8db65SMichael Speer dma_mbox_cntl_poolp->ndmas = ndmas;
16128ad8db65SMichael Speer dma_mbox_cntl_poolp->buf_allocated = B_TRUE;
16138ad8db65SMichael Speer hxgep->rx_mbox_cntl_pool_p = dma_mbox_cntl_poolp;
16148ad8db65SMichael Speer dma_mbox_cntl_poolp->dma_buf_pool_p = dma_mbox_cntl_p;
16153dec9fcdSqs
16163dec9fcdSqs goto hxge_alloc_rx_mem_pool_exit;
16173dec9fcdSqs
16183dec9fcdSqs hxge_alloc_rx_mem_fail2:
16193dec9fcdSqs /* Free control buffers */
16203dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16213dec9fcdSqs "==> hxge_alloc_rx_mem_pool: freeing control bufs (%d)", j));
16223dec9fcdSqs for (; j >= 0; j--) {
16233dec9fcdSqs hxge_free_rx_cntl_dma(hxgep,
16248ad8db65SMichael Speer (p_hxge_dma_common_t)dma_rbr_cntl_p[j]);
16258ad8db65SMichael Speer hxge_free_rx_cntl_dma(hxgep,
16268ad8db65SMichael Speer (p_hxge_dma_common_t)dma_rcr_cntl_p[j]);
16278ad8db65SMichael Speer hxge_free_rx_cntl_dma(hxgep,
16288ad8db65SMichael Speer (p_hxge_dma_common_t)dma_mbox_cntl_p[j]);
16293dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16303dec9fcdSqs "==> hxge_alloc_rx_mem_pool: control bufs freed (%d)", j));
16313dec9fcdSqs }
16323dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16333dec9fcdSqs "==> hxge_alloc_rx_mem_pool: control bufs freed (%d)", j));
16343dec9fcdSqs
16353dec9fcdSqs hxge_alloc_rx_mem_fail1:
16363dec9fcdSqs /* Free data buffers */
16373dec9fcdSqs i--;
16383dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16393dec9fcdSqs "==> hxge_alloc_rx_mem_pool: freeing data bufs (%d)", i));
16403dec9fcdSqs for (; i >= 0; i--) {
16413dec9fcdSqs hxge_free_rx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
16423dec9fcdSqs num_chunks[i]);
16433dec9fcdSqs }
16443dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16453dec9fcdSqs "==> hxge_alloc_rx_mem_pool: data bufs freed (%d)", i));
16463dec9fcdSqs
16473dec9fcdSqs KMEM_FREE(num_chunks, sizeof (uint32_t) * ndmas);
16483dec9fcdSqs KMEM_FREE(dma_poolp, sizeof (hxge_dma_pool_t));
16493dec9fcdSqs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
16508ad8db65SMichael Speer KMEM_FREE(dma_rbr_cntl_poolp, sizeof (hxge_dma_pool_t));
16518ad8db65SMichael Speer KMEM_FREE(dma_rbr_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
16528ad8db65SMichael Speer KMEM_FREE(dma_rcr_cntl_poolp, sizeof (hxge_dma_pool_t));
16538ad8db65SMichael Speer KMEM_FREE(dma_rcr_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
16548ad8db65SMichael Speer KMEM_FREE(dma_mbox_cntl_poolp, sizeof (hxge_dma_pool_t));
16558ad8db65SMichael Speer KMEM_FREE(dma_mbox_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
16563dec9fcdSqs
16573dec9fcdSqs hxge_alloc_rx_mem_pool_exit:
16583dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
16593dec9fcdSqs "<== hxge_alloc_rx_mem_pool:status 0x%08x", status));
16603dec9fcdSqs
16613dec9fcdSqs return (status);
16623dec9fcdSqs }
16633dec9fcdSqs
16643dec9fcdSqs static void
hxge_free_rx_mem_pool(p_hxge_t hxgep)16653dec9fcdSqs hxge_free_rx_mem_pool(p_hxge_t hxgep)
16663dec9fcdSqs {
16673dec9fcdSqs uint32_t i, ndmas;
16683dec9fcdSqs p_hxge_dma_pool_t dma_poolp;
16693dec9fcdSqs p_hxge_dma_common_t *dma_buf_p;
16708ad8db65SMichael Speer p_hxge_dma_pool_t dma_rbr_cntl_poolp;
16718ad8db65SMichael Speer p_hxge_dma_common_t *dma_rbr_cntl_p;
16728ad8db65SMichael Speer p_hxge_dma_pool_t dma_rcr_cntl_poolp;
16738ad8db65SMichael Speer p_hxge_dma_common_t *dma_rcr_cntl_p;
16748ad8db65SMichael Speer p_hxge_dma_pool_t dma_mbox_cntl_poolp;
16758ad8db65SMichael Speer p_hxge_dma_common_t *dma_mbox_cntl_p;
16763dec9fcdSqs uint32_t *num_chunks;
16773dec9fcdSqs
16783dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_free_rx_mem_pool"));
16793dec9fcdSqs
16803dec9fcdSqs dma_poolp = hxgep->rx_buf_pool_p;
16813dec9fcdSqs if (dma_poolp == NULL || (!dma_poolp->buf_allocated)) {
16823dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool "
16833dec9fcdSqs "(null rx buf pool or buf not allocated"));
16843dec9fcdSqs return;
16853dec9fcdSqs }
16863dec9fcdSqs
16878ad8db65SMichael Speer dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p;
16888ad8db65SMichael Speer if (dma_rbr_cntl_poolp == NULL ||
16898ad8db65SMichael Speer (!dma_rbr_cntl_poolp->buf_allocated)) {
16908ad8db65SMichael Speer HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
16918ad8db65SMichael Speer "<== hxge_free_rx_mem_pool "
16928ad8db65SMichael Speer "(null rbr cntl buf pool or rbr cntl buf not allocated"));
16938ad8db65SMichael Speer return;
16948ad8db65SMichael Speer }
16958ad8db65SMichael Speer
16968ad8db65SMichael Speer dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p;
16978ad8db65SMichael Speer if (dma_rcr_cntl_poolp == NULL ||
16988ad8db65SMichael Speer (!dma_rcr_cntl_poolp->buf_allocated)) {
16993dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
17003dec9fcdSqs "<== hxge_free_rx_mem_pool "
17018ad8db65SMichael Speer "(null rcr cntl buf pool or rcr cntl buf not allocated"));
17028ad8db65SMichael Speer return;
17038ad8db65SMichael Speer }
17048ad8db65SMichael Speer
17058ad8db65SMichael Speer dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p;
17068ad8db65SMichael Speer if (dma_mbox_cntl_poolp == NULL ||
17078ad8db65SMichael Speer (!dma_mbox_cntl_poolp->buf_allocated)) {
17088ad8db65SMichael Speer HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
17098ad8db65SMichael Speer "<== hxge_free_rx_mem_pool "
17108ad8db65SMichael Speer "(null mbox cntl buf pool or mbox cntl buf not allocated"));
17113dec9fcdSqs return;
17123dec9fcdSqs }
17133dec9fcdSqs
17143dec9fcdSqs dma_buf_p = dma_poolp->dma_buf_pool_p;
17153dec9fcdSqs num_chunks = dma_poolp->num_chunks;
17163dec9fcdSqs
17178ad8db65SMichael Speer dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p;
17188ad8db65SMichael Speer dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p;
17198ad8db65SMichael Speer dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p;
17208ad8db65SMichael Speer ndmas = dma_rbr_cntl_poolp->ndmas;
17213dec9fcdSqs
17223dec9fcdSqs for (i = 0; i < ndmas; i++) {
17233dec9fcdSqs hxge_free_rx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
17243dec9fcdSqs }
17253dec9fcdSqs
17263dec9fcdSqs for (i = 0; i < ndmas; i++) {
17278ad8db65SMichael Speer hxge_free_rx_cntl_dma(hxgep, dma_rbr_cntl_p[i]);
17288ad8db65SMichael Speer hxge_free_rx_cntl_dma(hxgep, dma_rcr_cntl_p[i]);
17298ad8db65SMichael Speer hxge_free_rx_cntl_dma(hxgep, dma_mbox_cntl_p[i]);
17303dec9fcdSqs }
17313dec9fcdSqs
17323dec9fcdSqs for (i = 0; i < ndmas; i++) {
17333dec9fcdSqs KMEM_FREE(dma_buf_p[i],
17343dec9fcdSqs sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
17358ad8db65SMichael Speer KMEM_FREE(dma_rbr_cntl_p[i], sizeof (hxge_dma_common_t));
17368ad8db65SMichael Speer KMEM_FREE(dma_rcr_cntl_p[i], sizeof (hxge_dma_common_t));
17378ad8db65SMichael Speer KMEM_FREE(dma_mbox_cntl_p[i], sizeof (hxge_dma_common_t));
17383dec9fcdSqs }
17393dec9fcdSqs
17403dec9fcdSqs KMEM_FREE(num_chunks, sizeof (uint32_t) * ndmas);
17418ad8db65SMichael Speer KMEM_FREE(dma_rbr_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
17428ad8db65SMichael Speer KMEM_FREE(dma_rbr_cntl_poolp, sizeof (hxge_dma_pool_t));
17438ad8db65SMichael Speer KMEM_FREE(dma_rcr_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
17448ad8db65SMichael Speer KMEM_FREE(dma_rcr_cntl_poolp, sizeof (hxge_dma_pool_t));
17458ad8db65SMichael Speer KMEM_FREE(dma_mbox_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
17468ad8db65SMichael Speer KMEM_FREE(dma_mbox_cntl_poolp, sizeof (hxge_dma_pool_t));
17473dec9fcdSqs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
17483dec9fcdSqs KMEM_FREE(dma_poolp, sizeof (hxge_dma_pool_t));
17493dec9fcdSqs
17503dec9fcdSqs hxgep->rx_buf_pool_p = NULL;
17518ad8db65SMichael Speer hxgep->rx_rbr_cntl_pool_p = NULL;
17528ad8db65SMichael Speer hxgep->rx_rcr_cntl_pool_p = NULL;
17538ad8db65SMichael Speer hxgep->rx_mbox_cntl_pool_p = NULL;
17543dec9fcdSqs
17553dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_mem_pool"));
17563dec9fcdSqs }
17573dec9fcdSqs
17583dec9fcdSqs static hxge_status_t
hxge_alloc_rx_buf_dma(p_hxge_t hxgep,uint16_t dma_channel,p_hxge_dma_common_t * dmap,size_t alloc_size,size_t block_size,uint32_t * num_chunks)17593dec9fcdSqs hxge_alloc_rx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
17603dec9fcdSqs p_hxge_dma_common_t *dmap,
17613dec9fcdSqs size_t alloc_size, size_t block_size, uint32_t *num_chunks)
17623dec9fcdSqs {
17633dec9fcdSqs p_hxge_dma_common_t rx_dmap;
17643dec9fcdSqs hxge_status_t status = HXGE_OK;
17653dec9fcdSqs size_t total_alloc_size;
17663dec9fcdSqs size_t allocated = 0;
17673dec9fcdSqs int i, size_index, array_size;
17683dec9fcdSqs
17693dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_buf_dma"));
17703dec9fcdSqs
17713dec9fcdSqs rx_dmap = (p_hxge_dma_common_t)
17723dec9fcdSqs KMEM_ZALLOC(sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK, KM_SLEEP);
17733dec9fcdSqs
17743dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
17753dec9fcdSqs " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ",
17763dec9fcdSqs dma_channel, alloc_size, block_size, dmap));
17773dec9fcdSqs
17783dec9fcdSqs total_alloc_size = alloc_size;
17793dec9fcdSqs
17803dec9fcdSqs i = 0;
17813dec9fcdSqs size_index = 0;
17823dec9fcdSqs array_size = sizeof (alloc_sizes) / sizeof (size_t);
1783b83cd2c3SMichael Speer while ((size_index < array_size) &&
1784b83cd2c3SMichael Speer (alloc_sizes[size_index] < alloc_size))
17853dec9fcdSqs size_index++;
17863dec9fcdSqs if (size_index >= array_size) {
17873dec9fcdSqs size_index = array_size - 1;
17883dec9fcdSqs }
17893dec9fcdSqs
17903dec9fcdSqs while ((allocated < total_alloc_size) &&
17913dec9fcdSqs (size_index >= 0) && (i < HXGE_DMA_BLOCK)) {
17923dec9fcdSqs rx_dmap[i].dma_chunk_index = i;
17933dec9fcdSqs rx_dmap[i].block_size = block_size;
17943dec9fcdSqs rx_dmap[i].alength = alloc_sizes[size_index];
17953dec9fcdSqs rx_dmap[i].orig_alength = rx_dmap[i].alength;
17963dec9fcdSqs rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
17973dec9fcdSqs rx_dmap[i].dma_channel = dma_channel;
17983dec9fcdSqs rx_dmap[i].contig_alloc_type = B_FALSE;
17993dec9fcdSqs
18003dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
18013dec9fcdSqs "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x "
18023dec9fcdSqs "i %d nblocks %d alength %d",
18033dec9fcdSqs dma_channel, i, &rx_dmap[i], block_size,
18043dec9fcdSqs i, rx_dmap[i].nblocks, rx_dmap[i].alength));
18053dec9fcdSqs status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
18063dec9fcdSqs &hxge_rx_dma_attr, rx_dmap[i].alength,
18073dec9fcdSqs &hxge_dev_buf_dma_acc_attr,
18083dec9fcdSqs DDI_DMA_READ | DDI_DMA_STREAMING,
18093dec9fcdSqs (p_hxge_dma_common_t)(&rx_dmap[i]));
18103dec9fcdSqs if (status != HXGE_OK) {
18113dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
18123dec9fcdSqs " hxge_alloc_rx_buf_dma: Alloc Failed: "
18133dec9fcdSqs " for size: %d", alloc_sizes[size_index]));
18143dec9fcdSqs size_index--;
18153dec9fcdSqs } else {
18163dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
18173dec9fcdSqs " alloc_rx_buf_dma allocated rdc %d "
18183dec9fcdSqs "chunk %d size %x dvma %x bufp %llx ",
18193dec9fcdSqs dma_channel, i, rx_dmap[i].alength,
18203dec9fcdSqs rx_dmap[i].ioaddr_pp, &rx_dmap[i]));
18213dec9fcdSqs i++;
18223dec9fcdSqs allocated += alloc_sizes[size_index];
18233dec9fcdSqs }
18243dec9fcdSqs }
18253dec9fcdSqs
18263dec9fcdSqs if (allocated < total_alloc_size) {
18273dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
18283dec9fcdSqs " hxge_alloc_rx_buf_dma failed due to"
18293dec9fcdSqs " allocated(%d) < required(%d)",
18303dec9fcdSqs allocated, total_alloc_size));
18313dec9fcdSqs goto hxge_alloc_rx_mem_fail1;
18323dec9fcdSqs }
18333dec9fcdSqs
18343dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
18353dec9fcdSqs " alloc_rx_buf_dma rdc %d allocated %d chunks", dma_channel, i));
18363dec9fcdSqs
18373dec9fcdSqs *num_chunks = i;
18383dec9fcdSqs *dmap = rx_dmap;
18393dec9fcdSqs
18403dec9fcdSqs goto hxge_alloc_rx_mem_exit;
18413dec9fcdSqs
18423dec9fcdSqs hxge_alloc_rx_mem_fail1:
18433dec9fcdSqs KMEM_FREE(rx_dmap, sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
18443dec9fcdSqs
18453dec9fcdSqs hxge_alloc_rx_mem_exit:
18463dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
18473dec9fcdSqs "<== hxge_alloc_rx_buf_dma status 0x%08x", status));
18483dec9fcdSqs
18493dec9fcdSqs return (status);
18503dec9fcdSqs }
18513dec9fcdSqs
18523dec9fcdSqs /*ARGSUSED*/
18533dec9fcdSqs static void
hxge_free_rx_buf_dma(p_hxge_t hxgep,p_hxge_dma_common_t dmap,uint32_t num_chunks)18543dec9fcdSqs hxge_free_rx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
18553dec9fcdSqs uint32_t num_chunks)
18563dec9fcdSqs {
18573dec9fcdSqs int i;
18583dec9fcdSqs
18593dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
18603dec9fcdSqs "==> hxge_free_rx_buf_dma: # of chunks %d", num_chunks));
18613dec9fcdSqs
18623dec9fcdSqs for (i = 0; i < num_chunks; i++) {
18633dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL,
18643dec9fcdSqs "==> hxge_free_rx_buf_dma: chunk %d dmap 0x%llx", i, dmap));
18653dec9fcdSqs hxge_dma_mem_free(dmap++);
18663dec9fcdSqs }
18673dec9fcdSqs
18683dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_free_rx_buf_dma"));
18693dec9fcdSqs }
18703dec9fcdSqs
18713dec9fcdSqs /*ARGSUSED*/
18723dec9fcdSqs static hxge_status_t
hxge_alloc_rx_cntl_dma(p_hxge_t hxgep,uint16_t dma_channel,p_hxge_dma_common_t * dmap,struct ddi_dma_attr * attr,size_t size)18733dec9fcdSqs hxge_alloc_rx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
18748ad8db65SMichael Speer p_hxge_dma_common_t *dmap, struct ddi_dma_attr *attr, size_t size)
18753dec9fcdSqs {
18763dec9fcdSqs p_hxge_dma_common_t rx_dmap;
18773dec9fcdSqs hxge_status_t status = HXGE_OK;
18783dec9fcdSqs
18793dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_rx_cntl_dma"));
18803dec9fcdSqs
18813dec9fcdSqs rx_dmap = (p_hxge_dma_common_t)
18823dec9fcdSqs KMEM_ZALLOC(sizeof (hxge_dma_common_t), KM_SLEEP);
18833dec9fcdSqs
18843dec9fcdSqs rx_dmap->contig_alloc_type = B_FALSE;
18853dec9fcdSqs
18863dec9fcdSqs status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
18878ad8db65SMichael Speer attr, size, &hxge_dev_desc_dma_acc_attr,
18883dec9fcdSqs DDI_DMA_RDWR | DDI_DMA_CONSISTENT, rx_dmap);
18893dec9fcdSqs if (status != HXGE_OK) {
18903dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
18913dec9fcdSqs " hxge_alloc_rx_cntl_dma: Alloc Failed: "
18923dec9fcdSqs " for size: %d", size));
18933dec9fcdSqs goto hxge_alloc_rx_cntl_dma_fail1;
18943dec9fcdSqs }
18953dec9fcdSqs
18963dec9fcdSqs *dmap = rx_dmap;
18973dec9fcdSqs
18983dec9fcdSqs goto hxge_alloc_rx_cntl_dma_exit;
18993dec9fcdSqs
19003dec9fcdSqs hxge_alloc_rx_cntl_dma_fail1:
19013dec9fcdSqs KMEM_FREE(rx_dmap, sizeof (hxge_dma_common_t));
19023dec9fcdSqs
19033dec9fcdSqs hxge_alloc_rx_cntl_dma_exit:
19043dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
19053dec9fcdSqs "<== hxge_alloc_rx_cntl_dma status 0x%08x", status));
19063dec9fcdSqs
19073dec9fcdSqs return (status);
19083dec9fcdSqs }
19093dec9fcdSqs
19103dec9fcdSqs /*ARGSUSED*/
19113dec9fcdSqs static void
hxge_free_rx_cntl_dma(p_hxge_t hxgep,p_hxge_dma_common_t dmap)19123dec9fcdSqs hxge_free_rx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
19133dec9fcdSqs {
19143dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_rx_cntl_dma"));
19153dec9fcdSqs
19163dec9fcdSqs hxge_dma_mem_free(dmap);
19173dec9fcdSqs
19183dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_rx_cntl_dma"));
19193dec9fcdSqs }
19203dec9fcdSqs
19213dec9fcdSqs static hxge_status_t
hxge_alloc_tx_mem_pool(p_hxge_t hxgep)19223dec9fcdSqs hxge_alloc_tx_mem_pool(p_hxge_t hxgep)
19233dec9fcdSqs {
19243dec9fcdSqs hxge_status_t status = HXGE_OK;
19253dec9fcdSqs int i, j;
19263dec9fcdSqs uint32_t ndmas, st_tdc;
19273dec9fcdSqs p_hxge_dma_pt_cfg_t p_all_cfgp;
19283dec9fcdSqs p_hxge_hw_pt_cfg_t p_cfgp;
19293dec9fcdSqs p_hxge_dma_pool_t dma_poolp;
19303dec9fcdSqs p_hxge_dma_common_t *dma_buf_p;
19313dec9fcdSqs p_hxge_dma_pool_t dma_cntl_poolp;
19323dec9fcdSqs p_hxge_dma_common_t *dma_cntl_p;
19333dec9fcdSqs size_t tx_buf_alloc_size;
19343dec9fcdSqs size_t tx_cntl_alloc_size;
19353dec9fcdSqs uint32_t *num_chunks; /* per dma */
19363dec9fcdSqs
19373dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool"));
19383dec9fcdSqs
19393dec9fcdSqs p_all_cfgp = (p_hxge_dma_pt_cfg_t)&hxgep->pt_config;
19403dec9fcdSqs p_cfgp = (p_hxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
19413dec9fcdSqs st_tdc = p_cfgp->start_tdc;
19423dec9fcdSqs ndmas = p_cfgp->max_tdcs;
19433dec9fcdSqs
19443dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_alloc_tx_mem_pool: "
19453dec9fcdSqs "p_cfgp 0x%016llx start_tdc %d ndmas %d hxgep->max_tdcs %d",
19463dec9fcdSqs p_cfgp, p_cfgp->start_tdc, p_cfgp->max_tdcs, hxgep->max_tdcs));
19473dec9fcdSqs /*
19483dec9fcdSqs * Allocate memory for each transmit DMA channel.
19493dec9fcdSqs */
19503dec9fcdSqs dma_poolp = (p_hxge_dma_pool_t)KMEM_ZALLOC(sizeof (hxge_dma_pool_t),
19513dec9fcdSqs KM_SLEEP);
19523dec9fcdSqs dma_buf_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
19533dec9fcdSqs sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
19543dec9fcdSqs
19553dec9fcdSqs dma_cntl_poolp = (p_hxge_dma_pool_t)
19563dec9fcdSqs KMEM_ZALLOC(sizeof (hxge_dma_pool_t), KM_SLEEP);
19573dec9fcdSqs dma_cntl_p = (p_hxge_dma_common_t *)KMEM_ZALLOC(
19583dec9fcdSqs sizeof (p_hxge_dma_common_t) * ndmas, KM_SLEEP);
19593dec9fcdSqs
19603dec9fcdSqs hxgep->hxge_port_tx_ring_size = hxge_tx_ring_size;
19613dec9fcdSqs
19623dec9fcdSqs /*
19633dec9fcdSqs * Assume that each DMA channel will be configured with default
19643dec9fcdSqs * transmit bufer size for copying transmit data. (For packet payload
19653dec9fcdSqs * over this limit, packets will not be copied.)
19663dec9fcdSqs */
19673dec9fcdSqs tx_buf_alloc_size = (hxge_bcopy_thresh * hxge_tx_ring_size);
19683dec9fcdSqs
19693dec9fcdSqs /*
19703dec9fcdSqs * Addresses of transmit descriptor ring and the mailbox must be all
19713dec9fcdSqs * cache-aligned (64 bytes).
19723dec9fcdSqs */
19733dec9fcdSqs tx_cntl_alloc_size = hxge_tx_ring_size;
19743dec9fcdSqs tx_cntl_alloc_size *= (sizeof (tx_desc_t));
19753dec9fcdSqs tx_cntl_alloc_size += sizeof (txdma_mailbox_t);
19763dec9fcdSqs
19773dec9fcdSqs num_chunks = (uint32_t *)KMEM_ZALLOC(sizeof (uint32_t) * ndmas,
19783dec9fcdSqs KM_SLEEP);
19793dec9fcdSqs
19803dec9fcdSqs /*
19813dec9fcdSqs * Allocate memory for transmit buffers and descriptor rings. Replace
19823dec9fcdSqs * allocation functions with interface functions provided by the
19833dec9fcdSqs * partition manager when it is available.
19843dec9fcdSqs *
19853dec9fcdSqs * Allocate memory for the transmit buffer pool.
19863dec9fcdSqs */
19873dec9fcdSqs for (i = 0; i < ndmas; i++) {
19883dec9fcdSqs num_chunks[i] = 0;
19893dec9fcdSqs status = hxge_alloc_tx_buf_dma(hxgep, st_tdc, &dma_buf_p[i],
19903dec9fcdSqs tx_buf_alloc_size, hxge_bcopy_thresh, &num_chunks[i]);
19913dec9fcdSqs if (status != HXGE_OK) {
19923dec9fcdSqs break;
19933dec9fcdSqs }
19943dec9fcdSqs st_tdc++;
19953dec9fcdSqs }
19963dec9fcdSqs
19973dec9fcdSqs if (i < ndmas) {
19983dec9fcdSqs goto hxge_alloc_tx_mem_pool_fail1;
19993dec9fcdSqs }
20003dec9fcdSqs
20013dec9fcdSqs st_tdc = p_cfgp->start_tdc;
20023dec9fcdSqs
20033dec9fcdSqs /*
20043dec9fcdSqs * Allocate memory for descriptor rings and mailbox.
20053dec9fcdSqs */
20063dec9fcdSqs for (j = 0; j < ndmas; j++) {
20073dec9fcdSqs status = hxge_alloc_tx_cntl_dma(hxgep, st_tdc, &dma_cntl_p[j],
20083dec9fcdSqs tx_cntl_alloc_size);
20093dec9fcdSqs if (status != HXGE_OK) {
20103dec9fcdSqs break;
20113dec9fcdSqs }
20123dec9fcdSqs st_tdc++;
20133dec9fcdSqs }
20143dec9fcdSqs
20153dec9fcdSqs if (j < ndmas) {
20163dec9fcdSqs goto hxge_alloc_tx_mem_pool_fail2;
20173dec9fcdSqs }
20183dec9fcdSqs
20193dec9fcdSqs dma_poolp->ndmas = ndmas;
20203dec9fcdSqs dma_poolp->num_chunks = num_chunks;
20213dec9fcdSqs dma_poolp->buf_allocated = B_TRUE;
20223dec9fcdSqs dma_poolp->dma_buf_pool_p = dma_buf_p;
20233dec9fcdSqs hxgep->tx_buf_pool_p = dma_poolp;
20243dec9fcdSqs
20253dec9fcdSqs dma_cntl_poolp->ndmas = ndmas;
20263dec9fcdSqs dma_cntl_poolp->buf_allocated = B_TRUE;
20273dec9fcdSqs dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p;
20283dec9fcdSqs hxgep->tx_cntl_pool_p = dma_cntl_poolp;
20293dec9fcdSqs
20303dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL,
20313dec9fcdSqs "==> hxge_alloc_tx_mem_pool: start_tdc %d "
20323dec9fcdSqs "ndmas %d poolp->ndmas %d", st_tdc, ndmas, dma_poolp->ndmas));
20333dec9fcdSqs
20343dec9fcdSqs goto hxge_alloc_tx_mem_pool_exit;
20353dec9fcdSqs
20363dec9fcdSqs hxge_alloc_tx_mem_pool_fail2:
20373dec9fcdSqs /* Free control buffers */
20383dec9fcdSqs j--;
20393dec9fcdSqs for (; j >= 0; j--) {
20403dec9fcdSqs hxge_free_tx_cntl_dma(hxgep,
20413dec9fcdSqs (p_hxge_dma_common_t)dma_cntl_p[j]);
20423dec9fcdSqs }
20433dec9fcdSqs
20443dec9fcdSqs hxge_alloc_tx_mem_pool_fail1:
20453dec9fcdSqs /* Free data buffers */
20463dec9fcdSqs i--;
20473dec9fcdSqs for (; i >= 0; i--) {
20483dec9fcdSqs hxge_free_tx_buf_dma(hxgep, (p_hxge_dma_common_t)dma_buf_p[i],
20493dec9fcdSqs num_chunks[i]);
20503dec9fcdSqs }
20513dec9fcdSqs
20523dec9fcdSqs KMEM_FREE(dma_poolp, sizeof (hxge_dma_pool_t));
20533dec9fcdSqs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
20543dec9fcdSqs KMEM_FREE(dma_cntl_poolp, sizeof (hxge_dma_pool_t));
20553dec9fcdSqs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
20563dec9fcdSqs KMEM_FREE(num_chunks, sizeof (uint32_t) * ndmas);
20573dec9fcdSqs
20583dec9fcdSqs hxge_alloc_tx_mem_pool_exit:
20593dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL,
20603dec9fcdSqs "<== hxge_alloc_tx_mem_pool:status 0x%08x", status));
20613dec9fcdSqs
20623dec9fcdSqs return (status);
20633dec9fcdSqs }
20643dec9fcdSqs
20653dec9fcdSqs static hxge_status_t
hxge_alloc_tx_buf_dma(p_hxge_t hxgep,uint16_t dma_channel,p_hxge_dma_common_t * dmap,size_t alloc_size,size_t block_size,uint32_t * num_chunks)20663dec9fcdSqs hxge_alloc_tx_buf_dma(p_hxge_t hxgep, uint16_t dma_channel,
20673dec9fcdSqs p_hxge_dma_common_t *dmap, size_t alloc_size,
20683dec9fcdSqs size_t block_size, uint32_t *num_chunks)
20693dec9fcdSqs {
20703dec9fcdSqs p_hxge_dma_common_t tx_dmap;
20713dec9fcdSqs hxge_status_t status = HXGE_OK;
20723dec9fcdSqs size_t total_alloc_size;
20733dec9fcdSqs size_t allocated = 0;
20743dec9fcdSqs int i, size_index, array_size;
20753dec9fcdSqs
20763dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_buf_dma"));
20773dec9fcdSqs
20783dec9fcdSqs tx_dmap = (p_hxge_dma_common_t)
20793dec9fcdSqs KMEM_ZALLOC(sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK, KM_SLEEP);
20803dec9fcdSqs
20813dec9fcdSqs total_alloc_size = alloc_size;
20823dec9fcdSqs i = 0;
20833dec9fcdSqs size_index = 0;
20843dec9fcdSqs array_size = sizeof (alloc_sizes) / sizeof (size_t);
2085b83cd2c3SMichael Speer while ((size_index < array_size) &&
2086b83cd2c3SMichael Speer (alloc_sizes[size_index] < alloc_size))
20873dec9fcdSqs size_index++;
20883dec9fcdSqs if (size_index >= array_size) {
20893dec9fcdSqs size_index = array_size - 1;
20903dec9fcdSqs }
20913dec9fcdSqs
20923dec9fcdSqs while ((allocated < total_alloc_size) &&
20933dec9fcdSqs (size_index >= 0) && (i < HXGE_DMA_BLOCK)) {
20943dec9fcdSqs tx_dmap[i].dma_chunk_index = i;
20953dec9fcdSqs tx_dmap[i].block_size = block_size;
20963dec9fcdSqs tx_dmap[i].alength = alloc_sizes[size_index];
20973dec9fcdSqs tx_dmap[i].orig_alength = tx_dmap[i].alength;
20983dec9fcdSqs tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size;
20993dec9fcdSqs tx_dmap[i].dma_channel = dma_channel;
21003dec9fcdSqs tx_dmap[i].contig_alloc_type = B_FALSE;
21013dec9fcdSqs
21023dec9fcdSqs status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
21033dec9fcdSqs &hxge_tx_dma_attr, tx_dmap[i].alength,
21043dec9fcdSqs &hxge_dev_buf_dma_acc_attr,
21053dec9fcdSqs DDI_DMA_WRITE | DDI_DMA_STREAMING,
21063dec9fcdSqs (p_hxge_dma_common_t)(&tx_dmap[i]));
21073dec9fcdSqs if (status != HXGE_OK) {
21083dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
21093dec9fcdSqs " hxge_alloc_tx_buf_dma: Alloc Failed: "
21103dec9fcdSqs " for size: %d", alloc_sizes[size_index]));
21113dec9fcdSqs size_index--;
21123dec9fcdSqs } else {
21133dec9fcdSqs i++;
21143dec9fcdSqs allocated += alloc_sizes[size_index];
21153dec9fcdSqs }
21163dec9fcdSqs }
21173dec9fcdSqs
21183dec9fcdSqs if (allocated < total_alloc_size) {
21193dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
21203dec9fcdSqs " hxge_alloc_tx_buf_dma: failed due to"
21213dec9fcdSqs " allocated(%d) < required(%d)",
21223dec9fcdSqs allocated, total_alloc_size));
21233dec9fcdSqs goto hxge_alloc_tx_mem_fail1;
21243dec9fcdSqs }
21253dec9fcdSqs
21263dec9fcdSqs *num_chunks = i;
21273dec9fcdSqs *dmap = tx_dmap;
21283dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
21293dec9fcdSqs "==> hxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d",
21303dec9fcdSqs *dmap, i));
21313dec9fcdSqs goto hxge_alloc_tx_mem_exit;
21323dec9fcdSqs
21333dec9fcdSqs hxge_alloc_tx_mem_fail1:
21343dec9fcdSqs KMEM_FREE(tx_dmap, sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
21353dec9fcdSqs
21363dec9fcdSqs hxge_alloc_tx_mem_exit:
21373dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
21383dec9fcdSqs "<== hxge_alloc_tx_buf_dma status 0x%08x", status));
21393dec9fcdSqs
21403dec9fcdSqs return (status);
21413dec9fcdSqs }
21423dec9fcdSqs
21433dec9fcdSqs /*ARGSUSED*/
21443dec9fcdSqs static void
hxge_free_tx_buf_dma(p_hxge_t hxgep,p_hxge_dma_common_t dmap,uint32_t num_chunks)21453dec9fcdSqs hxge_free_tx_buf_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap,
21463dec9fcdSqs uint32_t num_chunks)
21473dec9fcdSqs {
21483dec9fcdSqs int i;
21493dec9fcdSqs
21503dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "==> hxge_free_tx_buf_dma"));
21513dec9fcdSqs
21523dec9fcdSqs for (i = 0; i < num_chunks; i++) {
21533dec9fcdSqs hxge_dma_mem_free(dmap++);
21543dec9fcdSqs }
21553dec9fcdSqs
21563dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM_CTL, "<== hxge_free_tx_buf_dma"));
21573dec9fcdSqs }
21583dec9fcdSqs
21593dec9fcdSqs /*ARGSUSED*/
21603dec9fcdSqs static hxge_status_t
hxge_alloc_tx_cntl_dma(p_hxge_t hxgep,uint16_t dma_channel,p_hxge_dma_common_t * dmap,size_t size)21613dec9fcdSqs hxge_alloc_tx_cntl_dma(p_hxge_t hxgep, uint16_t dma_channel,
21623dec9fcdSqs p_hxge_dma_common_t *dmap, size_t size)
21633dec9fcdSqs {
21643dec9fcdSqs p_hxge_dma_common_t tx_dmap;
21653dec9fcdSqs hxge_status_t status = HXGE_OK;
21663dec9fcdSqs
21673dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_alloc_tx_cntl_dma"));
21683dec9fcdSqs
21693dec9fcdSqs tx_dmap = (p_hxge_dma_common_t)KMEM_ZALLOC(sizeof (hxge_dma_common_t),
21703dec9fcdSqs KM_SLEEP);
21713dec9fcdSqs
21723dec9fcdSqs tx_dmap->contig_alloc_type = B_FALSE;
21733dec9fcdSqs
21743dec9fcdSqs status = hxge_dma_mem_alloc(hxgep, hxge_force_dma,
21758ad8db65SMichael Speer &hxge_tx_desc_dma_attr, size, &hxge_dev_desc_dma_acc_attr,
21763dec9fcdSqs DDI_DMA_RDWR | DDI_DMA_CONSISTENT, tx_dmap);
21773dec9fcdSqs if (status != HXGE_OK) {
21783dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
21793dec9fcdSqs " hxge_alloc_tx_cntl_dma: Alloc Failed: "
21803dec9fcdSqs " for size: %d", size));
21813dec9fcdSqs goto hxge_alloc_tx_cntl_dma_fail1;
21823dec9fcdSqs }
21833dec9fcdSqs
21843dec9fcdSqs *dmap = tx_dmap;
21853dec9fcdSqs
21863dec9fcdSqs goto hxge_alloc_tx_cntl_dma_exit;
21873dec9fcdSqs
21883dec9fcdSqs hxge_alloc_tx_cntl_dma_fail1:
21893dec9fcdSqs KMEM_FREE(tx_dmap, sizeof (hxge_dma_common_t));
21903dec9fcdSqs
21913dec9fcdSqs hxge_alloc_tx_cntl_dma_exit:
21923dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
21933dec9fcdSqs "<== hxge_alloc_tx_cntl_dma status 0x%08x", status));
21943dec9fcdSqs
21953dec9fcdSqs return (status);
21963dec9fcdSqs }
21973dec9fcdSqs
21983dec9fcdSqs /*ARGSUSED*/
21993dec9fcdSqs static void
hxge_free_tx_cntl_dma(p_hxge_t hxgep,p_hxge_dma_common_t dmap)22003dec9fcdSqs hxge_free_tx_cntl_dma(p_hxge_t hxgep, p_hxge_dma_common_t dmap)
22013dec9fcdSqs {
22023dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_free_tx_cntl_dma"));
22033dec9fcdSqs
22043dec9fcdSqs hxge_dma_mem_free(dmap);
22053dec9fcdSqs
22063dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_free_tx_cntl_dma"));
22073dec9fcdSqs }
22083dec9fcdSqs
22093dec9fcdSqs static void
hxge_free_tx_mem_pool(p_hxge_t hxgep)22103dec9fcdSqs hxge_free_tx_mem_pool(p_hxge_t hxgep)
22113dec9fcdSqs {
22123dec9fcdSqs uint32_t i, ndmas;
22133dec9fcdSqs p_hxge_dma_pool_t dma_poolp;
22143dec9fcdSqs p_hxge_dma_common_t *dma_buf_p;
22153dec9fcdSqs p_hxge_dma_pool_t dma_cntl_poolp;
22163dec9fcdSqs p_hxge_dma_common_t *dma_cntl_p;
22173dec9fcdSqs uint32_t *num_chunks;
22183dec9fcdSqs
22193dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "==> hxge_free_tx_mem_pool"));
22203dec9fcdSqs
22213dec9fcdSqs dma_poolp = hxgep->tx_buf_pool_p;
22223dec9fcdSqs if (dma_poolp == NULL || (!dma_poolp->buf_allocated)) {
22233dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM3_CTL,
22243dec9fcdSqs "<== hxge_free_tx_mem_pool "
22253dec9fcdSqs "(null rx buf pool or buf not allocated"));
22263dec9fcdSqs return;
22273dec9fcdSqs }
22283dec9fcdSqs
22293dec9fcdSqs dma_cntl_poolp = hxgep->tx_cntl_pool_p;
22303dec9fcdSqs if (dma_cntl_poolp == NULL || (!dma_cntl_poolp->buf_allocated)) {
22313dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM3_CTL,
22323dec9fcdSqs "<== hxge_free_tx_mem_pool "
22333dec9fcdSqs "(null tx cntl buf pool or cntl buf not allocated"));
22343dec9fcdSqs return;
22353dec9fcdSqs }
22363dec9fcdSqs
22373dec9fcdSqs dma_buf_p = dma_poolp->dma_buf_pool_p;
22383dec9fcdSqs num_chunks = dma_poolp->num_chunks;
22393dec9fcdSqs
22403dec9fcdSqs dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p;
22413dec9fcdSqs ndmas = dma_cntl_poolp->ndmas;
22423dec9fcdSqs
22433dec9fcdSqs for (i = 0; i < ndmas; i++) {
22443dec9fcdSqs hxge_free_tx_buf_dma(hxgep, dma_buf_p[i], num_chunks[i]);
22453dec9fcdSqs }
22463dec9fcdSqs
22473dec9fcdSqs for (i = 0; i < ndmas; i++) {
22483dec9fcdSqs hxge_free_tx_cntl_dma(hxgep, dma_cntl_p[i]);
22493dec9fcdSqs }
22503dec9fcdSqs
22513dec9fcdSqs for (i = 0; i < ndmas; i++) {
22523dec9fcdSqs KMEM_FREE(dma_buf_p[i],
22533dec9fcdSqs sizeof (hxge_dma_common_t) * HXGE_DMA_BLOCK);
22543dec9fcdSqs KMEM_FREE(dma_cntl_p[i], sizeof (hxge_dma_common_t));
22553dec9fcdSqs }
22563dec9fcdSqs
22573dec9fcdSqs KMEM_FREE(num_chunks, sizeof (uint32_t) * ndmas);
22583dec9fcdSqs KMEM_FREE(dma_cntl_p, ndmas * sizeof (p_hxge_dma_common_t));
22593dec9fcdSqs KMEM_FREE(dma_cntl_poolp, sizeof (hxge_dma_pool_t));
22603dec9fcdSqs KMEM_FREE(dma_buf_p, ndmas * sizeof (p_hxge_dma_common_t));
22613dec9fcdSqs KMEM_FREE(dma_poolp, sizeof (hxge_dma_pool_t));
22623dec9fcdSqs
22633dec9fcdSqs hxgep->tx_buf_pool_p = NULL;
22643dec9fcdSqs hxgep->tx_cntl_pool_p = NULL;
22653dec9fcdSqs
22663dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MEM3_CTL, "<== hxge_free_tx_mem_pool"));
22673dec9fcdSqs }
22683dec9fcdSqs
22693dec9fcdSqs /*ARGSUSED*/
22703dec9fcdSqs static hxge_status_t
hxge_dma_mem_alloc(p_hxge_t hxgep,dma_method_t method,struct ddi_dma_attr * dma_attrp,size_t length,ddi_device_acc_attr_t * acc_attr_p,uint_t xfer_flags,p_hxge_dma_common_t dma_p)22713dec9fcdSqs hxge_dma_mem_alloc(p_hxge_t hxgep, dma_method_t method,
22723dec9fcdSqs struct ddi_dma_attr *dma_attrp,
22733dec9fcdSqs size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags,
22743dec9fcdSqs p_hxge_dma_common_t dma_p)
22753dec9fcdSqs {
22763dec9fcdSqs caddr_t kaddrp;
22773dec9fcdSqs int ddi_status = DDI_SUCCESS;
22783dec9fcdSqs
22793dec9fcdSqs dma_p->dma_handle = NULL;
22803dec9fcdSqs dma_p->acc_handle = NULL;
22813dec9fcdSqs dma_p->kaddrp = NULL;
22823dec9fcdSqs
22833dec9fcdSqs ddi_status = ddi_dma_alloc_handle(hxgep->dip, dma_attrp,
22843dec9fcdSqs DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle);
22853dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
22863dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
22873dec9fcdSqs "hxge_dma_mem_alloc:ddi_dma_alloc_handle failed."));
22883dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
22893dec9fcdSqs }
22903dec9fcdSqs
22913dec9fcdSqs ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, length, acc_attr_p,
22923dec9fcdSqs xfer_flags, DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength,
22933dec9fcdSqs &dma_p->acc_handle);
22943dec9fcdSqs if (ddi_status != DDI_SUCCESS) {
22953dec9fcdSqs /* The caller will decide whether it is fatal */
22963dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
22973dec9fcdSqs "hxge_dma_mem_alloc:ddi_dma_mem_alloc failed"));
22983dec9fcdSqs ddi_dma_free_handle(&dma_p->dma_handle);
22993dec9fcdSqs dma_p->dma_handle = NULL;
23003dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
23013dec9fcdSqs }
23023dec9fcdSqs
23033dec9fcdSqs if (dma_p->alength < length) {
23043dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
23053dec9fcdSqs "hxge_dma_mem_alloc:ddi_dma_mem_alloc < length."));
23063dec9fcdSqs ddi_dma_mem_free(&dma_p->acc_handle);
23073dec9fcdSqs ddi_dma_free_handle(&dma_p->dma_handle);
23083dec9fcdSqs dma_p->acc_handle = NULL;
23093dec9fcdSqs dma_p->dma_handle = NULL;
23103dec9fcdSqs return (HXGE_ERROR);
23113dec9fcdSqs }
23123dec9fcdSqs
23133dec9fcdSqs ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL,
23143dec9fcdSqs kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0,
23153dec9fcdSqs &dma_p->dma_cookie, &dma_p->ncookies);
23163dec9fcdSqs if (ddi_status != DDI_DMA_MAPPED) {
23173dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
23183dec9fcdSqs "hxge_dma_mem_alloc:di_dma_addr_bind failed "
23193dec9fcdSqs "(staus 0x%x ncookies %d.)", ddi_status, dma_p->ncookies));
23203dec9fcdSqs if (dma_p->acc_handle) {
23213dec9fcdSqs ddi_dma_mem_free(&dma_p->acc_handle);
23223dec9fcdSqs dma_p->acc_handle = NULL;
23233dec9fcdSqs }
23243dec9fcdSqs ddi_dma_free_handle(&dma_p->dma_handle);
23253dec9fcdSqs dma_p->dma_handle = NULL;
23263dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
23273dec9fcdSqs }
23283dec9fcdSqs
23293dec9fcdSqs if (dma_p->ncookies != 1) {
23303dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL,
23313dec9fcdSqs "hxge_dma_mem_alloc:ddi_dma_addr_bind > 1 cookie"
23323dec9fcdSqs "(staus 0x%x ncookies %d.)", ddi_status, dma_p->ncookies));
23333dec9fcdSqs if (dma_p->acc_handle) {
23343dec9fcdSqs ddi_dma_mem_free(&dma_p->acc_handle);
23353dec9fcdSqs dma_p->acc_handle = NULL;
23363dec9fcdSqs }
23373dec9fcdSqs (void) ddi_dma_unbind_handle(dma_p->dma_handle);
23383dec9fcdSqs ddi_dma_free_handle(&dma_p->dma_handle);
23393dec9fcdSqs dma_p->dma_handle = NULL;
23403dec9fcdSqs return (HXGE_ERROR);
23413dec9fcdSqs }
23423dec9fcdSqs
23433dec9fcdSqs dma_p->kaddrp = kaddrp;
23443dec9fcdSqs dma_p->ioaddr_pp = (unsigned char *) dma_p->dma_cookie.dmac_laddress;
23453dec9fcdSqs
23463dec9fcdSqs HPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle);
23473dec9fcdSqs
23483dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_dma_mem_alloc: "
23493dec9fcdSqs "dma buffer allocated: dma_p $%p "
23503dec9fcdSqs "return dmac_ladress from cookie $%p dmac_size %d "
23513dec9fcdSqs "dma_p->ioaddr_p $%p "
23523dec9fcdSqs "dma_p->orig_ioaddr_p $%p "
23533dec9fcdSqs "orig_vatopa $%p "
23543dec9fcdSqs "alength %d (0x%x) "
23553dec9fcdSqs "kaddrp $%p "
23563dec9fcdSqs "length %d (0x%x)",
23573dec9fcdSqs dma_p,
23583dec9fcdSqs dma_p->dma_cookie.dmac_laddress,
23593dec9fcdSqs dma_p->dma_cookie.dmac_size,
23603dec9fcdSqs dma_p->ioaddr_pp,
23613dec9fcdSqs dma_p->orig_ioaddr_pp,
23623dec9fcdSqs dma_p->orig_vatopa,
23633dec9fcdSqs dma_p->alength, dma_p->alength,
23643dec9fcdSqs kaddrp,
23653dec9fcdSqs length, length));
23663dec9fcdSqs
23673dec9fcdSqs return (HXGE_OK);
23683dec9fcdSqs }
23693dec9fcdSqs
23703dec9fcdSqs static void
hxge_dma_mem_free(p_hxge_dma_common_t dma_p)23713dec9fcdSqs hxge_dma_mem_free(p_hxge_dma_common_t dma_p)
23723dec9fcdSqs {
23738ad8db65SMichael Speer if (dma_p == NULL)
23748ad8db65SMichael Speer return;
23758ad8db65SMichael Speer
23763dec9fcdSqs if (dma_p->dma_handle != NULL) {
23773dec9fcdSqs if (dma_p->ncookies) {
23783dec9fcdSqs (void) ddi_dma_unbind_handle(dma_p->dma_handle);
23793dec9fcdSqs dma_p->ncookies = 0;
23803dec9fcdSqs }
23813dec9fcdSqs ddi_dma_free_handle(&dma_p->dma_handle);
23823dec9fcdSqs dma_p->dma_handle = NULL;
23833dec9fcdSqs }
23848ad8db65SMichael Speer
23853dec9fcdSqs if (dma_p->acc_handle != NULL) {
23863dec9fcdSqs ddi_dma_mem_free(&dma_p->acc_handle);
23873dec9fcdSqs dma_p->acc_handle = NULL;
23883dec9fcdSqs HPI_DMA_ACC_HANDLE_SET(dma_p, NULL);
23893dec9fcdSqs }
23908ad8db65SMichael Speer
23913dec9fcdSqs dma_p->kaddrp = NULL;
2392*c11cea93SToomas Soome dma_p->alength = 0;
23933dec9fcdSqs }
23943dec9fcdSqs
23953dec9fcdSqs /*
23963dec9fcdSqs * hxge_m_start() -- start transmitting and receiving.
23973dec9fcdSqs *
23983dec9fcdSqs * This function is called by the MAC layer when the first
23993dec9fcdSqs * stream is open to prepare the hardware ready for sending
24003dec9fcdSqs * and transmitting packets.
24013dec9fcdSqs */
24023dec9fcdSqs static int
hxge_m_start(void * arg)24033dec9fcdSqs hxge_m_start(void *arg)
24043dec9fcdSqs {
24053dec9fcdSqs p_hxge_t hxgep = (p_hxge_t)arg;
24063dec9fcdSqs
24073dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_start"));
24083dec9fcdSqs
24093dec9fcdSqs MUTEX_ENTER(hxgep->genlock);
24103dec9fcdSqs
24113dec9fcdSqs if (hxge_init(hxgep) != DDI_SUCCESS) {
24123dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
24133dec9fcdSqs "<== hxge_m_start: initialization failed"));
24143dec9fcdSqs MUTEX_EXIT(hxgep->genlock);
24153dec9fcdSqs return (EIO);
24163dec9fcdSqs }
24173dec9fcdSqs
24183dec9fcdSqs if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) {
24193dec9fcdSqs /*
24203dec9fcdSqs * Start timer to check the system error and tx hangs
24213dec9fcdSqs */
24223dec9fcdSqs hxgep->hxge_timerid = hxge_start_timer(hxgep,
24233dec9fcdSqs hxge_check_hw_state, HXGE_CHECK_TIMER);
24243dec9fcdSqs
24253dec9fcdSqs hxgep->hxge_mac_state = HXGE_MAC_STARTED;
2426e5d97391SQiyan Sun - Sun Microsystems - San Diego United States
2427e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.link_status = 0;
2428e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.report_link_status = B_TRUE;
2429e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.ticks = drv_usectohz(2 * 1000000);
2430e5d97391SQiyan Sun - Sun Microsystems - San Diego United States
2431e5d97391SQiyan Sun - Sun Microsystems - San Diego United States /* Start the link status timer to check the link status */
2432e5d97391SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_ENTER(&hxgep->timeout.lock);
2433e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.id = timeout(hxge_link_poll, (void *)hxgep,
2434e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.ticks);
2435e5d97391SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_EXIT(&hxgep->timeout.lock);
24363dec9fcdSqs }
24373dec9fcdSqs
24383dec9fcdSqs MUTEX_EXIT(hxgep->genlock);
24393dec9fcdSqs
24403dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_start"));
24413dec9fcdSqs
24423dec9fcdSqs return (0);
24433dec9fcdSqs }
24443dec9fcdSqs
24453dec9fcdSqs /*
24463dec9fcdSqs * hxge_m_stop(): stop transmitting and receiving.
24473dec9fcdSqs */
24483dec9fcdSqs static void
hxge_m_stop(void * arg)24493dec9fcdSqs hxge_m_stop(void *arg)
24503dec9fcdSqs {
24513dec9fcdSqs p_hxge_t hxgep = (p_hxge_t)arg;
24523dec9fcdSqs
24533dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_stop"));
24543dec9fcdSqs
24553dec9fcdSqs if (hxgep->hxge_timerid) {
24563dec9fcdSqs hxge_stop_timer(hxgep, hxgep->hxge_timerid);
24573dec9fcdSqs hxgep->hxge_timerid = 0;
24583dec9fcdSqs }
24593dec9fcdSqs
2460e5d97391SQiyan Sun - Sun Microsystems - San Diego United States /* Stop the link status timer before unregistering */
2461e5d97391SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_ENTER(&hxgep->timeout.lock);
2462e5d97391SQiyan Sun - Sun Microsystems - San Diego United States if (hxgep->timeout.id) {
2463e5d97391SQiyan Sun - Sun Microsystems - San Diego United States (void) untimeout(hxgep->timeout.id);
2464e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxgep->timeout.id = 0;
2465e5d97391SQiyan Sun - Sun Microsystems - San Diego United States }
2466e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxge_link_update(hxgep, LINK_STATE_DOWN);
2467e5d97391SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_EXIT(&hxgep->timeout.lock);
2468e5d97391SQiyan Sun - Sun Microsystems - San Diego United States
24693dec9fcdSqs MUTEX_ENTER(hxgep->genlock);
24703dec9fcdSqs
24713dec9fcdSqs hxge_uninit(hxgep);
24723dec9fcdSqs
24733dec9fcdSqs hxgep->hxge_mac_state = HXGE_MAC_STOPPED;
24743dec9fcdSqs
24753dec9fcdSqs MUTEX_EXIT(hxgep->genlock);
24763dec9fcdSqs
24773dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_stop"));
24783dec9fcdSqs }
24793dec9fcdSqs
24803dec9fcdSqs static int
hxge_m_multicst(void * arg,boolean_t add,const uint8_t * mca)24813dec9fcdSqs hxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
24823dec9fcdSqs {
24833dec9fcdSqs p_hxge_t hxgep = (p_hxge_t)arg;
24843dec9fcdSqs struct ether_addr addrp;
24853dec9fcdSqs
24863dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_multicst: add %d", add));
24873dec9fcdSqs
24883dec9fcdSqs bcopy(mca, (uint8_t *)&addrp, ETHERADDRL);
24893dec9fcdSqs
24903dec9fcdSqs if (add) {
24913dec9fcdSqs if (hxge_add_mcast_addr(hxgep, &addrp)) {
24923dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
24933dec9fcdSqs "<== hxge_m_multicst: add multicast failed"));
24943dec9fcdSqs return (EINVAL);
24953dec9fcdSqs }
24963dec9fcdSqs } else {
24973dec9fcdSqs if (hxge_del_mcast_addr(hxgep, &addrp)) {
24983dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
24993dec9fcdSqs "<== hxge_m_multicst: del multicast failed"));
25003dec9fcdSqs return (EINVAL);
25013dec9fcdSqs }
25023dec9fcdSqs }
25033dec9fcdSqs
25043dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "<== hxge_m_multicst"));
25053dec9fcdSqs
25063dec9fcdSqs return (0);
25073dec9fcdSqs }
25083dec9fcdSqs
25093dec9fcdSqs static int
hxge_m_promisc(void * arg,boolean_t on)25103dec9fcdSqs hxge_m_promisc(void *arg, boolean_t on)
25113dec9fcdSqs {
25123dec9fcdSqs p_hxge_t hxgep = (p_hxge_t)arg;
25133dec9fcdSqs
25143dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "==> hxge_m_promisc: on %d", on));
25153dec9fcdSqs
25163dec9fcdSqs if (hxge_set_promisc(hxgep, on)) {
25173dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
25183dec9fcdSqs "<== hxge_m_promisc: set promisc failed"));
25193dec9fcdSqs return (EINVAL);
25203dec9fcdSqs }
25213dec9fcdSqs
25223dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MAC_CTL, "<== hxge_m_promisc: on %d", on));
25233dec9fcdSqs
25243dec9fcdSqs return (0);
25253dec9fcdSqs }
25263dec9fcdSqs
25273dec9fcdSqs static void
hxge_m_ioctl(void * arg,queue_t * wq,mblk_t * mp)25283dec9fcdSqs hxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp)
25293dec9fcdSqs {
25303dec9fcdSqs p_hxge_t hxgep = (p_hxge_t)arg;
25313dec9fcdSqs struct iocblk *iocp = (struct iocblk *)mp->b_rptr;
25323dec9fcdSqs boolean_t need_privilege;
25333dec9fcdSqs int err;
25343dec9fcdSqs int cmd;
25353dec9fcdSqs
25363dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_ioctl"));
25373dec9fcdSqs
25383dec9fcdSqs iocp = (struct iocblk *)mp->b_rptr;
25393dec9fcdSqs iocp->ioc_error = 0;
25403dec9fcdSqs need_privilege = B_TRUE;
25413dec9fcdSqs cmd = iocp->ioc_cmd;
25423dec9fcdSqs
25433dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "==> hxge_m_ioctl: cmd 0x%08x", cmd));
25443dec9fcdSqs switch (cmd) {
25453dec9fcdSqs default:
25463dec9fcdSqs miocnak(wq, mp, 0, EINVAL);
25473dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_ioctl: invalid"));
25483dec9fcdSqs return;
25493dec9fcdSqs
25503dec9fcdSqs case LB_GET_INFO_SIZE:
25513dec9fcdSqs case LB_GET_INFO:
25523dec9fcdSqs case LB_GET_MODE:
25533dec9fcdSqs need_privilege = B_FALSE;
25543dec9fcdSqs break;
25553dec9fcdSqs
25563dec9fcdSqs case LB_SET_MODE:
25573dec9fcdSqs break;
25583dec9fcdSqs
25593dec9fcdSqs case ND_GET:
25603dec9fcdSqs need_privilege = B_FALSE;
25613dec9fcdSqs break;
25623dec9fcdSqs case ND_SET:
25633dec9fcdSqs break;
25643dec9fcdSqs
25653dec9fcdSqs case HXGE_GET_TX_RING_SZ:
25663dec9fcdSqs case HXGE_GET_TX_DESC:
25673dec9fcdSqs case HXGE_TX_SIDE_RESET:
25683dec9fcdSqs case HXGE_RX_SIDE_RESET:
25693dec9fcdSqs case HXGE_GLOBAL_RESET:
25703dec9fcdSqs case HXGE_RESET_MAC:
25713dec9fcdSqs case HXGE_PUT_TCAM:
25723dec9fcdSqs case HXGE_GET_TCAM:
25733dec9fcdSqs case HXGE_RTRACE:
25743dec9fcdSqs
25753dec9fcdSqs need_privilege = B_FALSE;
25763dec9fcdSqs break;
25773dec9fcdSqs }
25783dec9fcdSqs
25793dec9fcdSqs if (need_privilege) {
25803dec9fcdSqs err = secpolicy_net_config(iocp->ioc_cr, B_FALSE);
25813dec9fcdSqs if (err != 0) {
25823dec9fcdSqs miocnak(wq, mp, 0, err);
25833dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
25843dec9fcdSqs "<== hxge_m_ioctl: no priv"));
25853dec9fcdSqs return;
25863dec9fcdSqs }
25873dec9fcdSqs }
25883dec9fcdSqs
25893dec9fcdSqs switch (cmd) {
25903dec9fcdSqs case ND_GET:
25913dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "ND_GET command"));
25923dec9fcdSqs case ND_SET:
25933dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "ND_SET command"));
25943dec9fcdSqs hxge_param_ioctl(hxgep, wq, mp, iocp);
25953dec9fcdSqs break;
25963dec9fcdSqs
25973dec9fcdSqs case LB_GET_MODE:
25983dec9fcdSqs case LB_SET_MODE:
25993dec9fcdSqs case LB_GET_INFO_SIZE:
26003dec9fcdSqs case LB_GET_INFO:
26013dec9fcdSqs hxge_loopback_ioctl(hxgep, wq, mp, iocp);
26023dec9fcdSqs break;
26033dec9fcdSqs
26043dec9fcdSqs case HXGE_PUT_TCAM:
26053dec9fcdSqs case HXGE_GET_TCAM:
26063dec9fcdSqs case HXGE_GET_TX_RING_SZ:
26073dec9fcdSqs case HXGE_GET_TX_DESC:
26083dec9fcdSqs case HXGE_TX_SIDE_RESET:
26093dec9fcdSqs case HXGE_RX_SIDE_RESET:
26103dec9fcdSqs case HXGE_GLOBAL_RESET:
26113dec9fcdSqs case HXGE_RESET_MAC:
26123dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL,
26133dec9fcdSqs "==> hxge_m_ioctl: cmd 0x%x", cmd));
26143dec9fcdSqs hxge_hw_ioctl(hxgep, wq, mp, iocp);
26153dec9fcdSqs break;
26163dec9fcdSqs }
26173dec9fcdSqs
26183dec9fcdSqs HXGE_DEBUG_MSG((hxgep, NEMO_CTL, "<== hxge_m_ioctl"));
26193dec9fcdSqs }
26203dec9fcdSqs
26211ed83081SMichael Speer /*ARGSUSED*/
26221ed83081SMichael Speer static int
hxge_tx_ring_start(mac_ring_driver_t rdriver,uint64_t mr_gen_num)26231ed83081SMichael Speer hxge_tx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num)
26241ed83081SMichael Speer {
26251ed83081SMichael Speer p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)rdriver;
26261ed83081SMichael Speer p_hxge_t hxgep;
26271ed83081SMichael Speer p_tx_ring_t ring;
26281ed83081SMichael Speer
26291ed83081SMichael Speer ASSERT(rhp != NULL);
26301ed83081SMichael Speer ASSERT((rhp->index >= 0) && (rhp->index < HXGE_MAX_TDCS));
26311ed83081SMichael Speer
26321ed83081SMichael Speer hxgep = rhp->hxgep;
26331ed83081SMichael Speer
26341ed83081SMichael Speer /*
26351ed83081SMichael Speer * Get the ring pointer.
26361ed83081SMichael Speer */
26371ed83081SMichael Speer ring = hxgep->tx_rings->rings[rhp->index];
26381ed83081SMichael Speer
26391ed83081SMichael Speer /*
26401ed83081SMichael Speer * Fill in the handle for the transmit.
26411ed83081SMichael Speer */
26421ed83081SMichael Speer MUTEX_ENTER(&ring->lock);
26436ffca240SMichael Speer rhp->started = B_TRUE;
26441ed83081SMichael Speer ring->ring_handle = rhp->ring_handle;
26451ed83081SMichael Speer MUTEX_EXIT(&ring->lock);
26461ed83081SMichael Speer
26471ed83081SMichael Speer return (0);
26481ed83081SMichael Speer }
26491ed83081SMichael Speer
26501ed83081SMichael Speer static void
hxge_tx_ring_stop(mac_ring_driver_t rdriver)26511ed83081SMichael Speer hxge_tx_ring_stop(mac_ring_driver_t rdriver)
26521ed83081SMichael Speer {
26531ed83081SMichael Speer p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)rdriver;
26541ed83081SMichael Speer p_hxge_t hxgep;
26551ed83081SMichael Speer p_tx_ring_t ring;
26561ed83081SMichael Speer
26571ed83081SMichael Speer ASSERT(rhp != NULL);
26581ed83081SMichael Speer ASSERT((rhp->index >= 0) && (rhp->index < HXGE_MAX_TDCS));
26591ed83081SMichael Speer
26601ed83081SMichael Speer hxgep = rhp->hxgep;
26611ed83081SMichael Speer ring = hxgep->tx_rings->rings[rhp->index];
26621ed83081SMichael Speer
26631ed83081SMichael Speer MUTEX_ENTER(&ring->lock);
26641ed83081SMichael Speer ring->ring_handle = (mac_ring_handle_t)NULL;
26656ffca240SMichael Speer rhp->started = B_FALSE;
26661ed83081SMichael Speer MUTEX_EXIT(&ring->lock);
26671ed83081SMichael Speer }
26681ed83081SMichael Speer
26691ed83081SMichael Speer static int
hxge_rx_ring_start(mac_ring_driver_t rdriver,uint64_t mr_gen_num)26701ed83081SMichael Speer hxge_rx_ring_start(mac_ring_driver_t rdriver, uint64_t mr_gen_num)
26711ed83081SMichael Speer {
26721ed83081SMichael Speer p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)rdriver;
26731ed83081SMichael Speer p_hxge_t hxgep;
26741ed83081SMichael Speer p_rx_rcr_ring_t ring;
26751ed83081SMichael Speer int i;
26761ed83081SMichael Speer
26771ed83081SMichael Speer ASSERT(rhp != NULL);
26781ed83081SMichael Speer ASSERT((rhp->index >= 0) && (rhp->index < HXGE_MAX_TDCS));
26791ed83081SMichael Speer
26801ed83081SMichael Speer hxgep = rhp->hxgep;
26811ed83081SMichael Speer
26821ed83081SMichael Speer /*
26831ed83081SMichael Speer * Get pointer to ring.
26841ed83081SMichael Speer */
26851ed83081SMichael Speer ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index];
26861ed83081SMichael Speer
26871ed83081SMichael Speer MUTEX_ENTER(&ring->lock);
26881ed83081SMichael Speer
26891ed83081SMichael Speer if (rhp->started) {
26901ed83081SMichael Speer MUTEX_EXIT(&ring->lock);
26911ed83081SMichael Speer return (0);
26921ed83081SMichael Speer }
26931ed83081SMichael Speer
26941ed83081SMichael Speer /*
26951ed83081SMichael Speer * Set the ldvp and ldgp pointers to enable/disable
26961ed83081SMichael Speer * polling.
26971ed83081SMichael Speer */
26981ed83081SMichael Speer for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
26991ed83081SMichael Speer if ((hxgep->ldgvp->ldvp[i].is_rxdma == 1) &&
27001ed83081SMichael Speer (hxgep->ldgvp->ldvp[i].channel == rhp->index)) {
27011ed83081SMichael Speer ring->ldvp = &hxgep->ldgvp->ldvp[i];
27021ed83081SMichael Speer ring->ldgp = hxgep->ldgvp->ldvp[i].ldgp;
27031ed83081SMichael Speer break;
27041ed83081SMichael Speer }
27051ed83081SMichael Speer }
27061ed83081SMichael Speer
27071ed83081SMichael Speer rhp->started = B_TRUE;
27081ed83081SMichael Speer ring->rcr_mac_handle = rhp->ring_handle;
27091ed83081SMichael Speer ring->rcr_gen_num = mr_gen_num;
27101ed83081SMichael Speer MUTEX_EXIT(&ring->lock);
27111ed83081SMichael Speer
27121ed83081SMichael Speer return (0);
27131ed83081SMichael Speer }
27141ed83081SMichael Speer
27151ed83081SMichael Speer static void
hxge_rx_ring_stop(mac_ring_driver_t rdriver)27161ed83081SMichael Speer hxge_rx_ring_stop(mac_ring_driver_t rdriver)
27171ed83081SMichael Speer {
27181ed83081SMichael Speer p_hxge_ring_handle_t rhp = (p_hxge_ring_handle_t)rdriver;
27191ed83081SMichael Speer p_hxge_t hxgep;
27201ed83081SMichael Speer p_rx_rcr_ring_t ring;
27211ed83081SMichael Speer
27221ed83081SMichael Speer ASSERT(rhp != NULL);
27231ed83081SMichael Speer ASSERT((rhp->index >= 0) && (rhp->index < HXGE_MAX_TDCS));
27241ed83081SMichael Speer
27251ed83081SMichael Speer hxgep = rhp->hxgep;
27261ed83081SMichael Speer ring = hxgep->rx_rcr_rings->rcr_rings[rhp->index];
27271ed83081SMichael Speer
27281ed83081SMichael Speer MUTEX_ENTER(&ring->lock);
27291ed83081SMichael Speer rhp->started = B_TRUE;
27301ed83081SMichael Speer ring->rcr_mac_handle = NULL;
27311ed83081SMichael Speer ring->ldvp = NULL;
27321ed83081SMichael Speer ring->ldgp = NULL;
27331ed83081SMichael Speer MUTEX_EXIT(&ring->lock);
27341ed83081SMichael Speer }
27351ed83081SMichael Speer
27361ed83081SMichael Speer static int
hxge_rx_group_start(mac_group_driver_t gdriver)27371ed83081SMichael Speer hxge_rx_group_start(mac_group_driver_t gdriver)
27381ed83081SMichael Speer {
27391ed83081SMichael Speer hxge_ring_group_t *group = (hxge_ring_group_t *)gdriver;
27401ed83081SMichael Speer
27411ed83081SMichael Speer ASSERT(group->hxgep != NULL);
27421ed83081SMichael Speer ASSERT(group->hxgep->hxge_mac_state == HXGE_MAC_STARTED);
27431ed83081SMichael Speer
27441ed83081SMichael Speer MUTEX_ENTER(group->hxgep->genlock);
27451ed83081SMichael Speer group->started = B_TRUE;
27461ed83081SMichael Speer MUTEX_EXIT(group->hxgep->genlock);
27471ed83081SMichael Speer
27481ed83081SMichael Speer return (0);
27491ed83081SMichael Speer }
27501ed83081SMichael Speer
27511ed83081SMichael Speer static void
hxge_rx_group_stop(mac_group_driver_t gdriver)27521ed83081SMichael Speer hxge_rx_group_stop(mac_group_driver_t gdriver)
27531ed83081SMichael Speer {
27541ed83081SMichael Speer hxge_ring_group_t *group = (hxge_ring_group_t *)gdriver;
27551ed83081SMichael Speer
27561ed83081SMichael Speer ASSERT(group->hxgep != NULL);
27571ed83081SMichael Speer ASSERT(group->hxgep->hxge_mac_state == HXGE_MAC_STARTED);
27581ed83081SMichael Speer ASSERT(group->started == B_TRUE);
27591ed83081SMichael Speer
27601ed83081SMichael Speer MUTEX_ENTER(group->hxgep->genlock);
27611ed83081SMichael Speer group->started = B_FALSE;
27621ed83081SMichael Speer MUTEX_EXIT(group->hxgep->genlock);
27631ed83081SMichael Speer }
27641ed83081SMichael Speer
27651ed83081SMichael Speer static int
hxge_mmac_get_slot(p_hxge_t hxgep,int * slot)27661ed83081SMichael Speer hxge_mmac_get_slot(p_hxge_t hxgep, int *slot)
27671ed83081SMichael Speer {
27681ed83081SMichael Speer int i;
27691ed83081SMichael Speer
27701ed83081SMichael Speer /*
27711ed83081SMichael Speer * Find an open slot.
27721ed83081SMichael Speer */
27731ed83081SMichael Speer for (i = 0; i < hxgep->mmac.total; i++) {
27741ed83081SMichael Speer if (!hxgep->mmac.addrs[i].set) {
27751ed83081SMichael Speer *slot = i;
27761ed83081SMichael Speer return (0);
27771ed83081SMichael Speer }
27781ed83081SMichael Speer }
27791ed83081SMichael Speer
27801ed83081SMichael Speer return (ENXIO);
27811ed83081SMichael Speer }
27821ed83081SMichael Speer
27831ed83081SMichael Speer static int
hxge_mmac_set_addr(p_hxge_t hxgep,int slot,const uint8_t * addr)27841ed83081SMichael Speer hxge_mmac_set_addr(p_hxge_t hxgep, int slot, const uint8_t *addr)
27851ed83081SMichael Speer {
27861ed83081SMichael Speer struct ether_addr eaddr;
27871ed83081SMichael Speer hxge_status_t status = HXGE_OK;
27881ed83081SMichael Speer
27891ed83081SMichael Speer bcopy(addr, (uint8_t *)&eaddr, ETHERADDRL);
27901ed83081SMichael Speer
27911ed83081SMichael Speer /*
27921ed83081SMichael Speer * Set new interface local address and re-init device.
27931ed83081SMichael Speer * This is destructive to any other streams attached
27941ed83081SMichael Speer * to this device.
27951ed83081SMichael Speer */
27961ed83081SMichael Speer RW_ENTER_WRITER(&hxgep->filter_lock);
27971ed83081SMichael Speer status = hxge_pfc_set_mac_address(hxgep, slot, &eaddr);
27981ed83081SMichael Speer RW_EXIT(&hxgep->filter_lock);
27991ed83081SMichael Speer if (status != HXGE_OK)
28001ed83081SMichael Speer return (status);
28011ed83081SMichael Speer
28021ed83081SMichael Speer hxgep->mmac.addrs[slot].set = B_TRUE;
28031ed83081SMichael Speer bcopy(addr, hxgep->mmac.addrs[slot].addr, ETHERADDRL);
28041ed83081SMichael Speer hxgep->mmac.available--;
28051ed83081SMichael Speer if (slot == HXGE_MAC_DEFAULT_ADDR_SLOT)
28061ed83081SMichael Speer hxgep->mmac.addrs[slot].primary = B_TRUE;
28071ed83081SMichael Speer
28081ed83081SMichael Speer return (0);
28091ed83081SMichael Speer }
28101ed83081SMichael Speer
28111ed83081SMichael Speer static int
hxge_mmac_find_addr(p_hxge_t hxgep,const uint8_t * addr,int * slot)28121ed83081SMichael Speer hxge_mmac_find_addr(p_hxge_t hxgep, const uint8_t *addr, int *slot)
28131ed83081SMichael Speer {
28141ed83081SMichael Speer int i, result;
28151ed83081SMichael Speer
28161ed83081SMichael Speer for (i = 0; i < hxgep->mmac.total; i++) {
28171ed83081SMichael Speer if (hxgep->mmac.addrs[i].set) {
28181ed83081SMichael Speer result = memcmp(hxgep->mmac.addrs[i].addr,
28191ed83081SMichael Speer addr, ETHERADDRL);
28201ed83081SMichael Speer if (result == 0) {
28211ed83081SMichael Speer *slot = i;
28221ed83081SMichael Speer return (0);
28231ed83081SMichael Speer }
28241ed83081SMichael Speer }
28251ed83081SMichael Speer }
28261ed83081SMichael Speer
28271ed83081SMichael Speer return (EINVAL);
28281ed83081SMichael Speer }
28291ed83081SMichael Speer
28301ed83081SMichael Speer static int
hxge_mmac_unset_addr(p_hxge_t hxgep,int slot)28311ed83081SMichael Speer hxge_mmac_unset_addr(p_hxge_t hxgep, int slot)
28321ed83081SMichael Speer {
28331ed83081SMichael Speer hxge_status_t status;
28341ed83081SMichael Speer int i;
28351ed83081SMichael Speer
28361ed83081SMichael Speer status = hxge_pfc_clear_mac_address(hxgep, slot);
28371ed83081SMichael Speer if (status != HXGE_OK)
28381ed83081SMichael Speer return (status);
28391ed83081SMichael Speer
28401ed83081SMichael Speer for (i = 0; i < ETHERADDRL; i++)
28411ed83081SMichael Speer hxgep->mmac.addrs[slot].addr[i] = 0;
28421ed83081SMichael Speer
28431ed83081SMichael Speer hxgep->mmac.addrs[slot].set = B_FALSE;
28441ed83081SMichael Speer if (slot == HXGE_MAC_DEFAULT_ADDR_SLOT)
28451ed83081SMichael Speer hxgep->mmac.addrs[slot].primary = B_FALSE;
28461ed83081SMichael Speer hxgep->mmac.available++;
28471ed83081SMichael Speer
28481ed83081SMichael Speer return (0);
28491ed83081SMichael Speer }
28501ed83081SMichael Speer
28511ed83081SMichael Speer static int
hxge_rx_group_add_mac(void * arg,const uint8_t * mac_addr)28521ed83081SMichael Speer hxge_rx_group_add_mac(void *arg, const uint8_t *mac_addr)
28531ed83081SMichael Speer {
28541ed83081SMichael Speer hxge_ring_group_t *group = arg;
28551ed83081SMichael Speer p_hxge_t hxgep = group->hxgep;
28561ed83081SMichael Speer int slot = 0;
28571ed83081SMichael Speer
28581ed83081SMichael Speer ASSERT(group->type == MAC_RING_TYPE_RX);
28591ed83081SMichael Speer
28601ed83081SMichael Speer MUTEX_ENTER(hxgep->genlock);
28611ed83081SMichael Speer
28621ed83081SMichael Speer /*
28631ed83081SMichael Speer * Find a slot for the address.
28641ed83081SMichael Speer */
28651ed83081SMichael Speer if (hxge_mmac_get_slot(hxgep, &slot) != 0) {
28661ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
28671ed83081SMichael Speer return (ENOSPC);
28681ed83081SMichael Speer }
28691ed83081SMichael Speer
28701ed83081SMichael Speer /*
28711ed83081SMichael Speer * Program the MAC address.
28721ed83081SMichael Speer */
28731ed83081SMichael Speer if (hxge_mmac_set_addr(hxgep, slot, mac_addr) != 0) {
28741ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
28751ed83081SMichael Speer return (ENOSPC);
28761ed83081SMichael Speer }
28771ed83081SMichael Speer
28781ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
28791ed83081SMichael Speer return (0);
28801ed83081SMichael Speer }
28811ed83081SMichael Speer
28821ed83081SMichael Speer static int
hxge_rx_group_rem_mac(void * arg,const uint8_t * mac_addr)28831ed83081SMichael Speer hxge_rx_group_rem_mac(void *arg, const uint8_t *mac_addr)
28841ed83081SMichael Speer {
28851ed83081SMichael Speer hxge_ring_group_t *group = arg;
28861ed83081SMichael Speer p_hxge_t hxgep = group->hxgep;
28871ed83081SMichael Speer int rv, slot;
28881ed83081SMichael Speer
28891ed83081SMichael Speer ASSERT(group->type == MAC_RING_TYPE_RX);
28901ed83081SMichael Speer
28911ed83081SMichael Speer MUTEX_ENTER(hxgep->genlock);
28921ed83081SMichael Speer
28931ed83081SMichael Speer if ((rv = hxge_mmac_find_addr(hxgep, mac_addr, &slot)) != 0) {
28941ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
28951ed83081SMichael Speer return (rv);
28961ed83081SMichael Speer }
28971ed83081SMichael Speer
28981ed83081SMichael Speer if ((rv = hxge_mmac_unset_addr(hxgep, slot)) != 0) {
28991ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
29001ed83081SMichael Speer return (rv);
29011ed83081SMichael Speer }
29021ed83081SMichael Speer
29031ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
29041ed83081SMichael Speer return (0);
29051ed83081SMichael Speer }
29061ed83081SMichael Speer
29071ed83081SMichael Speer static void
hxge_group_get(void * arg,mac_ring_type_t type,int groupid,mac_group_info_t * infop,mac_group_handle_t gh)29081ed83081SMichael Speer hxge_group_get(void *arg, mac_ring_type_t type, int groupid,
29091ed83081SMichael Speer mac_group_info_t *infop, mac_group_handle_t gh)
29101ed83081SMichael Speer {
29111ed83081SMichael Speer p_hxge_t hxgep = arg;
29121ed83081SMichael Speer hxge_ring_group_t *group;
29131ed83081SMichael Speer
29141ed83081SMichael Speer ASSERT(type == MAC_RING_TYPE_RX);
29151ed83081SMichael Speer
29161ed83081SMichael Speer switch (type) {
29171ed83081SMichael Speer case MAC_RING_TYPE_RX:
29181ed83081SMichael Speer group = &hxgep->rx_groups[groupid];
29191ed83081SMichael Speer group->hxgep = hxgep;
29201ed83081SMichael Speer group->ghandle = gh;
29211ed83081SMichael Speer group->index = groupid;
29221ed83081SMichael Speer group->type = type;
29231ed83081SMichael Speer
29241ed83081SMichael Speer infop->mgi_driver = (mac_group_driver_t)group;
29251ed83081SMichael Speer infop->mgi_start = hxge_rx_group_start;
29261ed83081SMichael Speer infop->mgi_stop = hxge_rx_group_stop;
29271ed83081SMichael Speer infop->mgi_addmac = hxge_rx_group_add_mac;
29281ed83081SMichael Speer infop->mgi_remmac = hxge_rx_group_rem_mac;
29291ed83081SMichael Speer infop->mgi_count = HXGE_MAX_RDCS;
29301ed83081SMichael Speer break;
29311ed83081SMichael Speer
29321ed83081SMichael Speer case MAC_RING_TYPE_TX:
29331ed83081SMichael Speer default:
29341ed83081SMichael Speer break;
29351ed83081SMichael Speer }
29361ed83081SMichael Speer }
29371ed83081SMichael Speer
29380dc2366fSVenugopal Iyer static int
hxge_ring_get_htable_idx(p_hxge_t hxgep,mac_ring_type_t type,uint32_t channel)29390dc2366fSVenugopal Iyer hxge_ring_get_htable_idx(p_hxge_t hxgep, mac_ring_type_t type, uint32_t channel)
29400dc2366fSVenugopal Iyer {
29410dc2366fSVenugopal Iyer int i;
29420dc2366fSVenugopal Iyer
29430dc2366fSVenugopal Iyer ASSERT(hxgep->ldgvp != NULL);
29440dc2366fSVenugopal Iyer
29450dc2366fSVenugopal Iyer switch (type) {
29460dc2366fSVenugopal Iyer case MAC_RING_TYPE_RX:
29470dc2366fSVenugopal Iyer for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
29480dc2366fSVenugopal Iyer if ((hxgep->ldgvp->ldvp[i].is_rxdma) &&
29490dc2366fSVenugopal Iyer (hxgep->ldgvp->ldvp[i].channel == channel)) {
29500dc2366fSVenugopal Iyer return ((int)
29510dc2366fSVenugopal Iyer hxgep->ldgvp->ldvp[i].ldgp->htable_idx);
29520dc2366fSVenugopal Iyer }
29530dc2366fSVenugopal Iyer }
29540dc2366fSVenugopal Iyer break;
29550dc2366fSVenugopal Iyer
29560dc2366fSVenugopal Iyer case MAC_RING_TYPE_TX:
29570dc2366fSVenugopal Iyer for (i = 0; i < hxgep->ldgvp->maxldvs; i++) {
29580dc2366fSVenugopal Iyer if ((hxgep->ldgvp->ldvp[i].is_txdma) &&
29590dc2366fSVenugopal Iyer (hxgep->ldgvp->ldvp[i].channel == channel)) {
29600dc2366fSVenugopal Iyer return ((int)
29610dc2366fSVenugopal Iyer hxgep->ldgvp->ldvp[i].ldgp->htable_idx);
29620dc2366fSVenugopal Iyer }
29630dc2366fSVenugopal Iyer }
29640dc2366fSVenugopal Iyer break;
29650dc2366fSVenugopal Iyer
29660dc2366fSVenugopal Iyer default:
29670dc2366fSVenugopal Iyer break;
29680dc2366fSVenugopal Iyer }
29690dc2366fSVenugopal Iyer
29700dc2366fSVenugopal Iyer return (-1);
29710dc2366fSVenugopal Iyer }
29720dc2366fSVenugopal Iyer
29731ed83081SMichael Speer /*
29741ed83081SMichael Speer * Callback function for the GLDv3 layer to register all rings.
29751ed83081SMichael Speer */
29761ed83081SMichael Speer /*ARGSUSED*/
29771ed83081SMichael Speer static void
hxge_fill_ring(void * arg,mac_ring_type_t type,const int rg_index,const int index,mac_ring_info_t * infop,mac_ring_handle_t rh)29781ed83081SMichael Speer hxge_fill_ring(void *arg, mac_ring_type_t type, const int rg_index,
29791ed83081SMichael Speer const int index, mac_ring_info_t *infop, mac_ring_handle_t rh)
29801ed83081SMichael Speer {
29811ed83081SMichael Speer p_hxge_t hxgep = arg;
29821ed83081SMichael Speer
29830dc2366fSVenugopal Iyer ASSERT(hxgep != NULL);
29840dc2366fSVenugopal Iyer ASSERT(infop != NULL);
29850dc2366fSVenugopal Iyer
29861ed83081SMichael Speer switch (type) {
29871ed83081SMichael Speer case MAC_RING_TYPE_TX: {
29881ed83081SMichael Speer p_hxge_ring_handle_t rhp;
29890dc2366fSVenugopal Iyer mac_intr_t *mintr = &infop->mri_intr;
29900dc2366fSVenugopal Iyer p_hxge_intr_t intrp;
29910dc2366fSVenugopal Iyer int htable_idx;
29921ed83081SMichael Speer
29931ed83081SMichael Speer ASSERT((index >= 0) && (index < HXGE_MAX_TDCS));
29941ed83081SMichael Speer rhp = &hxgep->tx_ring_handles[index];
29951ed83081SMichael Speer rhp->hxgep = hxgep;
29961ed83081SMichael Speer rhp->index = index;
29971ed83081SMichael Speer rhp->ring_handle = rh;
29981ed83081SMichael Speer infop->mri_driver = (mac_ring_driver_t)rhp;
29991ed83081SMichael Speer infop->mri_start = hxge_tx_ring_start;
30001ed83081SMichael Speer infop->mri_stop = hxge_tx_ring_stop;
30011ed83081SMichael Speer infop->mri_tx = hxge_tx_ring_send;
30020dc2366fSVenugopal Iyer infop->mri_stat = hxge_tx_ring_stat;
30030dc2366fSVenugopal Iyer
30040dc2366fSVenugopal Iyer intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
30050dc2366fSVenugopal Iyer htable_idx = hxge_ring_get_htable_idx(hxgep, type, index);
30060dc2366fSVenugopal Iyer if (htable_idx >= 0)
30070dc2366fSVenugopal Iyer mintr->mi_ddi_handle = intrp->htable[htable_idx];
30080dc2366fSVenugopal Iyer else
30090dc2366fSVenugopal Iyer mintr->mi_ddi_handle = NULL;
30101ed83081SMichael Speer break;
30111ed83081SMichael Speer }
30120dc2366fSVenugopal Iyer
30131ed83081SMichael Speer case MAC_RING_TYPE_RX: {
30141ed83081SMichael Speer p_hxge_ring_handle_t rhp;
30151ed83081SMichael Speer mac_intr_t hxge_mac_intr;
30160dc2366fSVenugopal Iyer p_hxge_intr_t intrp;
30170dc2366fSVenugopal Iyer int htable_idx;
30181ed83081SMichael Speer
30191ed83081SMichael Speer ASSERT((index >= 0) && (index < HXGE_MAX_RDCS));
30201ed83081SMichael Speer rhp = &hxgep->rx_ring_handles[index];
30211ed83081SMichael Speer rhp->hxgep = hxgep;
30221ed83081SMichael Speer rhp->index = index;
30231ed83081SMichael Speer rhp->ring_handle = rh;
30241ed83081SMichael Speer
30251ed83081SMichael Speer /*
30261ed83081SMichael Speer * Entrypoint to enable interrupt (disable poll) and
30271ed83081SMichael Speer * disable interrupt (enable poll).
30281ed83081SMichael Speer */
30291ed83081SMichael Speer hxge_mac_intr.mi_handle = (mac_intr_handle_t)rhp;
30300dc2366fSVenugopal Iyer hxge_mac_intr.mi_enable = (mac_intr_enable_t)hxge_disable_poll;
30310dc2366fSVenugopal Iyer hxge_mac_intr.mi_disable = (mac_intr_disable_t)hxge_enable_poll;
30320dc2366fSVenugopal Iyer
30330dc2366fSVenugopal Iyer intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
30340dc2366fSVenugopal Iyer htable_idx = hxge_ring_get_htable_idx(hxgep, type, index);
30350dc2366fSVenugopal Iyer if (htable_idx >= 0)
30360dc2366fSVenugopal Iyer hxge_mac_intr.mi_ddi_handle = intrp->htable[htable_idx];
30370dc2366fSVenugopal Iyer else
30380dc2366fSVenugopal Iyer hxge_mac_intr.mi_ddi_handle = NULL;
30390dc2366fSVenugopal Iyer
30401ed83081SMichael Speer infop->mri_driver = (mac_ring_driver_t)rhp;
30411ed83081SMichael Speer infop->mri_start = hxge_rx_ring_start;
30421ed83081SMichael Speer infop->mri_stop = hxge_rx_ring_stop;
30431ed83081SMichael Speer infop->mri_intr = hxge_mac_intr;
30441ed83081SMichael Speer infop->mri_poll = hxge_rx_poll;
30450dc2366fSVenugopal Iyer infop->mri_stat = hxge_rx_ring_stat;
30461ed83081SMichael Speer break;
30471ed83081SMichael Speer }
30480dc2366fSVenugopal Iyer
30491ed83081SMichael Speer default:
30501ed83081SMichael Speer break;
30511ed83081SMichael Speer }
30521ed83081SMichael Speer }
30531ed83081SMichael Speer
30543dec9fcdSqs /*ARGSUSED*/
30553dec9fcdSqs boolean_t
hxge_m_getcapab(void * arg,mac_capab_t cap,void * cap_data)30563dec9fcdSqs hxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
30573dec9fcdSqs {
30581ed83081SMichael Speer p_hxge_t hxgep = arg;
30593dec9fcdSqs
30603dec9fcdSqs switch (cap) {
30611ed83081SMichael Speer case MAC_CAPAB_HCKSUM: {
30621ed83081SMichael Speer uint32_t *txflags = cap_data;
30631ed83081SMichael Speer
30643dec9fcdSqs *txflags = HCKSUM_INET_PARTIAL;
30653dec9fcdSqs break;
30661ed83081SMichael Speer }
30671ed83081SMichael Speer
30681ed83081SMichael Speer case MAC_CAPAB_RINGS: {
30691ed83081SMichael Speer mac_capab_rings_t *cap_rings = cap_data;
30701ed83081SMichael Speer
30711ed83081SMichael Speer MUTEX_ENTER(hxgep->genlock);
30721ed83081SMichael Speer if (cap_rings->mr_type == MAC_RING_TYPE_RX) {
30731ed83081SMichael Speer cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
30741ed83081SMichael Speer cap_rings->mr_rnum = HXGE_MAX_RDCS;
30751ed83081SMichael Speer cap_rings->mr_rget = hxge_fill_ring;
30761ed83081SMichael Speer cap_rings->mr_gnum = HXGE_MAX_RX_GROUPS;
30771ed83081SMichael Speer cap_rings->mr_gget = hxge_group_get;
30781ed83081SMichael Speer cap_rings->mr_gaddring = NULL;
30791ed83081SMichael Speer cap_rings->mr_gremring = NULL;
30801ed83081SMichael Speer } else {
30811ed83081SMichael Speer cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
30821ed83081SMichael Speer cap_rings->mr_rnum = HXGE_MAX_TDCS;
30831ed83081SMichael Speer cap_rings->mr_rget = hxge_fill_ring;
30841ed83081SMichael Speer cap_rings->mr_gnum = 0;
30851ed83081SMichael Speer cap_rings->mr_gget = NULL;
30861ed83081SMichael Speer cap_rings->mr_gaddring = NULL;
30871ed83081SMichael Speer cap_rings->mr_gremring = NULL;
30881ed83081SMichael Speer }
30891ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
30901ed83081SMichael Speer break;
30911ed83081SMichael Speer }
30923dec9fcdSqs
30933dec9fcdSqs default:
30943dec9fcdSqs return (B_FALSE);
30953dec9fcdSqs }
30963dec9fcdSqs return (B_TRUE);
30973dec9fcdSqs }
30983dec9fcdSqs
3099a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static boolean_t
hxge_param_locked(mac_prop_id_t pr_num)3100a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_param_locked(mac_prop_id_t pr_num)
3101a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
3102a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3103a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * All adv_* parameters are locked (read-only) while
3104a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * the device is in any sort of loopback mode ...
3105a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
3106a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States switch (pr_num) {
3107a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000FDX_CAP:
3108a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000FDX_CAP:
3109a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000HDX_CAP:
3110a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000HDX_CAP:
3111a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100FDX_CAP:
3112a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100FDX_CAP:
3113a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100HDX_CAP:
3114a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100HDX_CAP:
3115a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10FDX_CAP:
3116a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10FDX_CAP:
3117a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10HDX_CAP:
3118a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10HDX_CAP:
3119a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_AUTONEG:
3120a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_FLOWCTRL:
3121a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (B_TRUE);
3122a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3123a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (B_FALSE);
3124a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3125a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3126a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3127a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * callback functions for set/get of properties
3128a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
3129a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int
hxge_m_setprop(void * barg,const char * pr_name,mac_prop_id_t pr_num,uint_t pr_valsize,const void * pr_val)3130a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
3131a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint_t pr_valsize, const void *pr_val)
3132a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
3133a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_t *hxgep = barg;
3134a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_stats_t statsp;
3135a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int err = 0;
3136a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint32_t new_mtu, old_framesize, new_framesize;
3137a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3138a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL, "==> hxge_m_setprop"));
3139a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3140a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States statsp = hxgep->statsp;
31411ed83081SMichael Speer MUTEX_ENTER(hxgep->genlock);
3142a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (statsp->port_stats.lb_mode != hxge_lb_normal &&
3143a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_param_locked(pr_num)) {
3144a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3145a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * All adv_* parameters are locked (read-only)
3146a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * while the device is in any sort of loopback mode.
3147a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
3148a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3149a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_setprop: loopback mode: read only"));
31501ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
3151a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (EBUSY);
3152a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3153a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3154a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States switch (pr_num) {
3155a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3156a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * These properties are either not exist or read only
3157a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
3158a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000FDX_CAP:
3159a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100FDX_CAP:
3160a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10FDX_CAP:
3161a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000HDX_CAP:
3162a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100HDX_CAP:
3163a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10HDX_CAP:
3164a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000FDX_CAP:
3165a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000HDX_CAP:
3166a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100FDX_CAP:
3167a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100HDX_CAP:
3168a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10FDX_CAP:
3169a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10HDX_CAP:
3170a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_STATUS:
3171a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_SPEED:
3172a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_DUPLEX:
3173a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_AUTONEG:
3174a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3175a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * Flow control is handled in the shared domain and
3176a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * it is readonly here.
3177a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
3178a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_FLOWCTRL:
3179a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = EINVAL;
3180a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3181a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_setprop: read only property %d",
3182a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States pr_num));
3183a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3184a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3185a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_MTU:
3186a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States bcopy(pr_val, &new_mtu, sizeof (new_mtu));
3187a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3188a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_setprop: set MTU: %d", new_mtu));
3189a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3190a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States new_framesize = new_mtu + MTU_TO_FRAME_SIZE;
3191a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (new_framesize == hxgep->vmac.maxframesize) {
3192a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = 0;
3193a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3194a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3195a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3196afdda45fSVasumathi Sundaram - Sun Microsystems if (hxgep->hxge_mac_state == HXGE_MAC_STARTED) {
3197afdda45fSVasumathi Sundaram - Sun Microsystems err = EBUSY;
3198afdda45fSVasumathi Sundaram - Sun Microsystems break;
3199afdda45fSVasumathi Sundaram - Sun Microsystems }
3200afdda45fSVasumathi Sundaram - Sun Microsystems
3201a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (new_framesize < MIN_FRAME_SIZE ||
3202a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States new_framesize > MAX_FRAME_SIZE) {
3203a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = EINVAL;
3204a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3205a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3206a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3207a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States old_framesize = hxgep->vmac.maxframesize;
3208a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxgep->vmac.maxframesize = (uint16_t)new_framesize;
3209a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3210a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (hxge_vmac_set_framesize(hxgep)) {
3211a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxgep->vmac.maxframesize =
3212a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (uint16_t)old_framesize;
3213a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = EINVAL;
3214a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3215a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3216a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3217a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = mac_maxsdu_update(hxgep->mach, new_mtu);
3218a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (err) {
3219a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxgep->vmac.maxframesize =
3220a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (uint16_t)old_framesize;
3221a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (void) hxge_vmac_set_framesize(hxgep);
3222a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3223a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3224a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3225a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_setprop: set MTU: %d maxframe %d",
3226a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States new_mtu, hxgep->vmac.maxframesize));
3227a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3228a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3229a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_PRIVATE:
3230a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3231a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_setprop: private property"));
3232a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_set_priv_prop(hxgep, pr_name, pr_valsize,
3233a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States pr_val);
3234a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3235a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3236a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States default:
3237a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = ENOTSUP;
3238a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3239a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3240a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
32411ed83081SMichael Speer MUTEX_EXIT(hxgep->genlock);
3242a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3243a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3244a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "<== hxge_m_setprop (return %d)", err));
3245a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3246a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (err);
3247a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3248a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3249a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int
hxge_m_getprop(void * barg,const char * pr_name,mac_prop_id_t pr_num,uint_t pr_valsize,void * pr_val)3250a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num,
32510dc2366fSVenugopal Iyer uint_t pr_valsize, void *pr_val)
3252a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
3253*c11cea93SToomas Soome hxge_t *hxgep = barg;
3254a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_stats_t statsp = hxgep->statsp;
3255a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int err = 0;
3256a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States link_flowctrl_t fl;
3257a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint64_t tmp = 0;
3258a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States link_state_t ls;
3259a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3260a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3261a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_getprop: pr_num %d", pr_num));
3262a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3263a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States switch (pr_num) {
3264a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_DUPLEX:
3265a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States *(uint8_t *)pr_val = statsp->mac_stats.link_duplex;
3266a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3267a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_m_getprop: duplex mode %d",
3268a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States *(uint8_t *)pr_val));
3269a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3270a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3271a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_SPEED:
32720dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (uint64_t));
3273a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States tmp = statsp->mac_stats.link_speed * 1000000ull;
3274a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States bcopy(&tmp, pr_val, sizeof (tmp));
3275a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3276a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3277a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_STATUS:
32780dc2366fSVenugopal Iyer ASSERT(pr_valsize >= sizeof (link_state_t));
3279a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (!statsp->mac_stats.link_up)
3280a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States ls = LINK_STATE_DOWN;
3281a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States else
3282a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States ls = LINK_STATE_UP;
3283a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States bcopy(&ls, pr_val, sizeof (ls));
3284a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3285a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3286a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_FLOWCTRL:
3287a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /*
3288a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * Flow control is supported by the shared domain and
3289a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States * it is currently transmit only
3290a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States */
32910dc2366fSVenugopal Iyer ASSERT(pr_valsize < sizeof (link_flowctrl_t));
3292a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States fl = LINK_FLOWCTRL_TX;
3293a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States bcopy(&fl, pr_val, sizeof (fl));
3294a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3295a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_AUTONEG:
3296a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* 10G link only and it is not negotiable */
3297a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States *(uint8_t *)pr_val = 0;
3298a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3299a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000FDX_CAP:
3300a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100FDX_CAP:
3301a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10FDX_CAP:
3302a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_1000HDX_CAP:
3303a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_100HDX_CAP:
3304a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_ADV_10HDX_CAP:
3305a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000FDX_CAP:
3306a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100FDX_CAP:
3307a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10FDX_CAP:
3308a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_1000HDX_CAP:
3309a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_100HDX_CAP:
3310a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_EN_10HDX_CAP:
3311a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = ENOTSUP;
3312a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3313a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3314a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States case MAC_PROP_PRIVATE:
33150dc2366fSVenugopal Iyer err = hxge_get_priv_prop(hxgep, pr_name, pr_valsize,
33160dc2366fSVenugopal Iyer pr_val);
3317f0f2c3a5SGirish Moodalbail break;
33180dc2366fSVenugopal Iyer
3319a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States default:
3320238d8f47SDale Ghent err = ENOTSUP;
3321a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States break;
3322a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3323a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3324a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL, "<== hxge_m_getprop"));
3325a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3326a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (err);
3327a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3328a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
33290dc2366fSVenugopal Iyer static void
hxge_m_propinfo(void * arg,const char * pr_name,mac_prop_id_t pr_num,mac_prop_info_handle_t prh)33300dc2366fSVenugopal Iyer hxge_m_propinfo(void *arg, const char *pr_name,
33310dc2366fSVenugopal Iyer mac_prop_id_t pr_num, mac_prop_info_handle_t prh)
33320dc2366fSVenugopal Iyer {
33330dc2366fSVenugopal Iyer _NOTE(ARGUNUSED(arg));
33340dc2366fSVenugopal Iyer switch (pr_num) {
33350dc2366fSVenugopal Iyer case MAC_PROP_DUPLEX:
33360dc2366fSVenugopal Iyer case MAC_PROP_SPEED:
33370dc2366fSVenugopal Iyer case MAC_PROP_STATUS:
33380dc2366fSVenugopal Iyer case MAC_PROP_AUTONEG:
33390dc2366fSVenugopal Iyer case MAC_PROP_FLOWCTRL:
33400dc2366fSVenugopal Iyer mac_prop_info_set_perm(prh, MAC_PROP_PERM_READ);
33410dc2366fSVenugopal Iyer break;
33420dc2366fSVenugopal Iyer
33430dc2366fSVenugopal Iyer case MAC_PROP_MTU:
33440dc2366fSVenugopal Iyer mac_prop_info_set_range_uint32(prh,
33450dc2366fSVenugopal Iyer MIN_FRAME_SIZE - MTU_TO_FRAME_SIZE,
33460dc2366fSVenugopal Iyer MAX_FRAME_SIZE - MTU_TO_FRAME_SIZE);
33470dc2366fSVenugopal Iyer break;
33480dc2366fSVenugopal Iyer
33490dc2366fSVenugopal Iyer case MAC_PROP_PRIVATE: {
33500dc2366fSVenugopal Iyer char valstr[MAXNAMELEN];
33510dc2366fSVenugopal Iyer
33520dc2366fSVenugopal Iyer bzero(valstr, sizeof (valstr));
33530dc2366fSVenugopal Iyer
33540dc2366fSVenugopal Iyer /* Receive Interrupt Blanking Parameters */
33550dc2366fSVenugopal Iyer if (strcmp(pr_name, "_rxdma_intr_time") == 0) {
33560dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d",
33570dc2366fSVenugopal Iyer RXDMA_RCR_TO_DEFAULT);
33580dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) {
33590dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d",
33600dc2366fSVenugopal Iyer RXDMA_RCR_PTHRES_DEFAULT);
33610dc2366fSVenugopal Iyer
33620dc2366fSVenugopal Iyer /* Classification and Load Distribution Configuration */
33630dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0 ||
33640dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_udp") == 0 ||
33650dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_ah") == 0 ||
33660dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv4_sctp") == 0 ||
33670dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_tcp") == 0 ||
33680dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_udp") == 0 ||
33690dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_ah") == 0 ||
33700dc2366fSVenugopal Iyer strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) {
33710dc2366fSVenugopal Iyer (void) snprintf(valstr, sizeof (valstr), "%d",
33720dc2366fSVenugopal Iyer HXGE_CLASS_TCAM_LOOKUP);
33730dc2366fSVenugopal Iyer }
33740dc2366fSVenugopal Iyer
33750dc2366fSVenugopal Iyer if (strlen(valstr) > 0)
33760dc2366fSVenugopal Iyer mac_prop_info_set_default_str(prh, valstr);
33770dc2366fSVenugopal Iyer break;
33780dc2366fSVenugopal Iyer }
33790dc2366fSVenugopal Iyer }
33800dc2366fSVenugopal Iyer }
33810dc2366fSVenugopal Iyer
33820dc2366fSVenugopal Iyer
3383a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* ARGSUSED */
3384a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int
hxge_set_priv_prop(p_hxge_t hxgep,const char * pr_name,uint_t pr_valsize,const void * pr_val)3385a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_set_priv_prop(p_hxge_t hxgep, const char *pr_name, uint_t pr_valsize,
3386a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States const void *pr_val)
3387a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
3388a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_param_t param_arr = hxgep->param_arr;
3389a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int err = 0;
3390a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3391a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3392a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_set_priv_prop: name %s (value %s)", pr_name, pr_val));
3393a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3394a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (pr_val == NULL) {
3395a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (EINVAL);
3396a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3397a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3398a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* Blanking */
3399a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (strcmp(pr_name, "_rxdma_intr_time") == 0) {
3400a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_rx_intr_time(hxgep, NULL, NULL,
3401a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (char *)pr_val, (caddr_t)¶m_arr[param_rxdma_intr_time]);
3402a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) {
3403a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_rx_intr_pkts(hxgep, NULL, NULL,
3404a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (char *)pr_val, (caddr_t)¶m_arr[param_rxdma_intr_pkts]);
3405a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3406a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* Classification */
3407a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) {
3408a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3409a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]);
3410a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) {
3411a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3412a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv4_udp]);
3413a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) {
3414a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3415a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv4_ah]);
3416a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) {
3417a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3418a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]);
3419a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) {
3420a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3421a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]);
3422a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) {
3423a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3424a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv6_udp]);
3425a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) {
3426a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3427a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv6_ah]);
3428a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) {
3429a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = hxge_param_set_ip_opt(hxgep, NULL, NULL, (char *)pr_val,
3430a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]);
3431a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else {
3432238d8f47SDale Ghent err = ENOTSUP;
3433a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3434a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3435a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3436a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "<== hxge_set_priv_prop: err %d", err));
3437a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3438a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (err);
3439a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3440a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3441a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static int
hxge_get_priv_prop(p_hxge_t hxgep,const char * pr_name,uint_t pr_valsize,void * pr_val)34420dc2366fSVenugopal Iyer hxge_get_priv_prop(p_hxge_t hxgep, const char *pr_name, uint_t pr_valsize,
34430dc2366fSVenugopal Iyer void *pr_val)
3444a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
3445a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_param_t param_arr = hxgep->param_arr;
3446a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States char valstr[MAXNAMELEN];
3447a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int err = 0;
3448a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States uint_t strsize;
3449a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States int value = 0;
3450a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3451a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3452a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "==> hxge_get_priv_prop: property %s", pr_name));
3453a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
34540dc2366fSVenugopal Iyer /* Receive Interrupt Blanking Parameters */
34550dc2366fSVenugopal Iyer if (strcmp(pr_name, "_rxdma_intr_time") == 0) {
34560dc2366fSVenugopal Iyer value = hxgep->intr_timeout;
34570dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) {
34580dc2366fSVenugopal Iyer value = hxgep->intr_threshold;
3459a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
34600dc2366fSVenugopal Iyer /* Classification and Load Distribution Configuration */
34610dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) {
34620dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34630dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]);
3464a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
34650dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv4_tcp].value;
34660dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) {
34670dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34680dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv4_udp]);
34690dc2366fSVenugopal Iyer
34700dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv4_udp].value;
34710dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) {
34720dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34730dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv4_ah]);
34740dc2366fSVenugopal Iyer
34750dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv4_ah].value;
34760dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) {
34770dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34780dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]);
34790dc2366fSVenugopal Iyer
34800dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv4_sctp].value;
34810dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) {
34820dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34830dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]);
34840dc2366fSVenugopal Iyer
34850dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv6_tcp].value;
34860dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) {
34870dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34880dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv6_udp]);
34890dc2366fSVenugopal Iyer
34900dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv6_udp].value;
34910dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) {
34920dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34930dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv6_ah]);
34940dc2366fSVenugopal Iyer
34950dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv6_ah].value;
34960dc2366fSVenugopal Iyer } else if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) {
34970dc2366fSVenugopal Iyer err = hxge_param_get_ip_opt(hxgep, NULL, NULL,
34980dc2366fSVenugopal Iyer (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]);
34990dc2366fSVenugopal Iyer
35000dc2366fSVenugopal Iyer value = (int)param_arr[param_class_opt_ipv6_sctp].value;
35010dc2366fSVenugopal Iyer } else {
3502238d8f47SDale Ghent err = ENOTSUP;
3503a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3504a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3505a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (err == 0) {
3506a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (void) snprintf(valstr, sizeof (valstr), "0x%x", value);
3507a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3508a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States strsize = (uint_t)strlen(valstr);
3509a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (pr_valsize < strsize) {
3510a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States err = ENOBUFS;
3511a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else {
3512a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States (void) strlcpy(pr_val, valstr, pr_valsize);
3513a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3514a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
3515a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3516a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, DLADM_CTL,
3517a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States "<== hxge_get_priv_prop: return %d", err));
3518a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
3519a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States return (err);
3520a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
35213dec9fcdSqs /*
35223dec9fcdSqs * Module loading and removing entry points.
35233dec9fcdSqs */
35243dec9fcdSqs DDI_DEFINE_STREAM_OPS(hxge_dev_ops, nulldev, nulldev, hxge_attach, hxge_detach,
35253a109ad9SQiyan Sun - Sun Microsystems - San Diego United States nodev, NULL, D_MP, NULL, NULL);
35263dec9fcdSqs
35273dec9fcdSqs extern struct mod_ops mod_driverops;
35283dec9fcdSqs
35293dec9fcdSqs #define HXGE_DESC_VER "HXGE 10Gb Ethernet Driver"
35303dec9fcdSqs
35313dec9fcdSqs /*
35323dec9fcdSqs * Module linkage information for the kernel.
35333dec9fcdSqs */
35343dec9fcdSqs static struct modldrv hxge_modldrv = {
35353dec9fcdSqs &mod_driverops,
35363dec9fcdSqs HXGE_DESC_VER,
35373dec9fcdSqs &hxge_dev_ops
35383dec9fcdSqs };
35393dec9fcdSqs
35403dec9fcdSqs static struct modlinkage modlinkage = {
35413dec9fcdSqs MODREV_1, (void *) &hxge_modldrv, NULL
35423dec9fcdSqs };
35433dec9fcdSqs
35443dec9fcdSqs int
_init(void)35453dec9fcdSqs _init(void)
35463dec9fcdSqs {
35473dec9fcdSqs int status;
35483dec9fcdSqs
35493dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init"));
35503dec9fcdSqs mac_init_ops(&hxge_dev_ops, "hxge");
35513dec9fcdSqs status = ddi_soft_state_init(&hxge_list, sizeof (hxge_t), 0);
35523dec9fcdSqs if (status != 0) {
35533dec9fcdSqs HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL,
35543dec9fcdSqs "failed to init device soft state"));
35553dec9fcdSqs mac_fini_ops(&hxge_dev_ops);
35563dec9fcdSqs goto _init_exit;
35573dec9fcdSqs }
35583dec9fcdSqs
35593dec9fcdSqs status = mod_install(&modlinkage);
35603dec9fcdSqs if (status != 0) {
35613dec9fcdSqs ddi_soft_state_fini(&hxge_list);
35623dec9fcdSqs HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "Mod install failed"));
35633dec9fcdSqs goto _init_exit;
35643dec9fcdSqs }
35653dec9fcdSqs
35663dec9fcdSqs MUTEX_INIT(&hxge_common_lock, NULL, MUTEX_DRIVER, NULL);
35673dec9fcdSqs
35683dec9fcdSqs _init_exit:
35693dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status));
35703dec9fcdSqs
35713dec9fcdSqs return (status);
35723dec9fcdSqs }
35733dec9fcdSqs
35743dec9fcdSqs int
_fini(void)35753dec9fcdSqs _fini(void)
35763dec9fcdSqs {
35773dec9fcdSqs int status;
35783dec9fcdSqs
35793dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini"));
35803dec9fcdSqs
35813dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove"));
35823dec9fcdSqs
35833dec9fcdSqs if (hxge_mblks_pending)
35843dec9fcdSqs return (EBUSY);
35853dec9fcdSqs
35863dec9fcdSqs status = mod_remove(&modlinkage);
35873dec9fcdSqs if (status != DDI_SUCCESS) {
35883dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL,
35893dec9fcdSqs "Module removal failed 0x%08x", status));
35903dec9fcdSqs goto _fini_exit;
35913dec9fcdSqs }
35923dec9fcdSqs
35933dec9fcdSqs mac_fini_ops(&hxge_dev_ops);
35943dec9fcdSqs
35953dec9fcdSqs ddi_soft_state_fini(&hxge_list);
35963dec9fcdSqs
35973dec9fcdSqs MUTEX_DESTROY(&hxge_common_lock);
35983dec9fcdSqs
35993dec9fcdSqs _fini_exit:
36003dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status));
36013dec9fcdSqs
36023dec9fcdSqs return (status);
36033dec9fcdSqs }
36043dec9fcdSqs
36053dec9fcdSqs int
_info(struct modinfo * modinfop)36063dec9fcdSqs _info(struct modinfo *modinfop)
36073dec9fcdSqs {
36083dec9fcdSqs int status;
36093dec9fcdSqs
36103dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info"));
36113dec9fcdSqs status = mod_info(&modlinkage, modinfop);
36123dec9fcdSqs HXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status));
36133dec9fcdSqs
36143dec9fcdSqs return (status);
36153dec9fcdSqs }
36163dec9fcdSqs
36173dec9fcdSqs /*ARGSUSED*/
3618f043ebedSMichael Speer static hxge_status_t
hxge_add_intrs(p_hxge_t hxgep)36193dec9fcdSqs hxge_add_intrs(p_hxge_t hxgep)
36203dec9fcdSqs {
36213dec9fcdSqs int intr_types;
36223dec9fcdSqs int type = 0;
36233dec9fcdSqs int ddi_status = DDI_SUCCESS;
36243dec9fcdSqs hxge_status_t status = HXGE_OK;
36253dec9fcdSqs
36263dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs"));
36273dec9fcdSqs
36283dec9fcdSqs hxgep->hxge_intr_type.intr_registered = B_FALSE;
36293dec9fcdSqs hxgep->hxge_intr_type.intr_enabled = B_FALSE;
36303dec9fcdSqs hxgep->hxge_intr_type.msi_intx_cnt = 0;
36313dec9fcdSqs hxgep->hxge_intr_type.intr_added = 0;
36323dec9fcdSqs hxgep->hxge_intr_type.niu_msi_enable = B_FALSE;
36333dec9fcdSqs hxgep->hxge_intr_type.intr_type = 0;
36343dec9fcdSqs
36353dec9fcdSqs if (hxge_msi_enable) {
36363dec9fcdSqs hxgep->hxge_intr_type.niu_msi_enable = B_TRUE;
36373dec9fcdSqs }
36383dec9fcdSqs
36393dec9fcdSqs /* Get the supported interrupt types */
36403dec9fcdSqs if ((ddi_status = ddi_intr_get_supported_types(hxgep->dip, &intr_types))
36413dec9fcdSqs != DDI_SUCCESS) {
36423dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_add_intrs: "
36433dec9fcdSqs "ddi_intr_get_supported_types failed: status 0x%08x",
36443dec9fcdSqs ddi_status));
36453dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
36463dec9fcdSqs }
36473dec9fcdSqs
36483dec9fcdSqs hxgep->hxge_intr_type.intr_types = intr_types;
36493dec9fcdSqs
36503dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
36513dec9fcdSqs "ddi_intr_get_supported_types: 0x%08x", intr_types));
36523dec9fcdSqs
36533dec9fcdSqs /*
36543dec9fcdSqs * Pick the interrupt type to use MSIX, MSI, INTX hxge_msi_enable:
36553dec9fcdSqs * (1): 1 - MSI
36563dec9fcdSqs * (2): 2 - MSI-X
36573dec9fcdSqs * others - FIXED
36583dec9fcdSqs */
36593dec9fcdSqs switch (hxge_msi_enable) {
36603dec9fcdSqs default:
36613dec9fcdSqs type = DDI_INTR_TYPE_FIXED;
36623dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
36633dec9fcdSqs "use fixed (intx emulation) type %08x", type));
36643dec9fcdSqs break;
36653dec9fcdSqs
36663dec9fcdSqs case 2:
36673dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
36683dec9fcdSqs "ddi_intr_get_supported_types: 0x%08x", intr_types));
36693dec9fcdSqs if (intr_types & DDI_INTR_TYPE_MSIX) {
36703dec9fcdSqs type = DDI_INTR_TYPE_MSIX;
36713dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
36723dec9fcdSqs "==> hxge_add_intrs: "
36733dec9fcdSqs "ddi_intr_get_supported_types: MSIX 0x%08x", type));
36743dec9fcdSqs } else if (intr_types & DDI_INTR_TYPE_MSI) {
36753dec9fcdSqs type = DDI_INTR_TYPE_MSI;
36763dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
36773dec9fcdSqs "==> hxge_add_intrs: "
36783dec9fcdSqs "ddi_intr_get_supported_types: MSI 0x%08x", type));
36793dec9fcdSqs } else if (intr_types & DDI_INTR_TYPE_FIXED) {
36803dec9fcdSqs type = DDI_INTR_TYPE_FIXED;
36813dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs: "
36823dec9fcdSqs "ddi_intr_get_supported_types: MSXED0x%08x", type));
36833dec9fcdSqs }
36843dec9fcdSqs break;
36853dec9fcdSqs
36863dec9fcdSqs case 1:
36873dec9fcdSqs if (intr_types & DDI_INTR_TYPE_MSI) {
36883dec9fcdSqs type = DDI_INTR_TYPE_MSI;
36893dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
36903dec9fcdSqs "==> hxge_add_intrs: "
36913dec9fcdSqs "ddi_intr_get_supported_types: MSI 0x%08x", type));
36923dec9fcdSqs } else if (intr_types & DDI_INTR_TYPE_MSIX) {
36933dec9fcdSqs type = DDI_INTR_TYPE_MSIX;
36943dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
36953dec9fcdSqs "==> hxge_add_intrs: "
36963dec9fcdSqs "ddi_intr_get_supported_types: MSIX 0x%08x", type));
36973dec9fcdSqs } else if (intr_types & DDI_INTR_TYPE_FIXED) {
36983dec9fcdSqs type = DDI_INTR_TYPE_FIXED;
36993dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
37003dec9fcdSqs "==> hxge_add_intrs: "
37013dec9fcdSqs "ddi_intr_get_supported_types: MSXED0x%08x", type));
37023dec9fcdSqs }
37033dec9fcdSqs }
37043dec9fcdSqs
37053dec9fcdSqs hxgep->hxge_intr_type.intr_type = type;
37063dec9fcdSqs if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI ||
37073dec9fcdSqs type == DDI_INTR_TYPE_FIXED) &&
37083dec9fcdSqs hxgep->hxge_intr_type.niu_msi_enable) {
37093dec9fcdSqs if ((status = hxge_add_intrs_adv(hxgep)) != DDI_SUCCESS) {
37103dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
37113dec9fcdSqs " hxge_add_intrs: "
37123dec9fcdSqs " hxge_add_intrs_adv failed: status 0x%08x",
37133dec9fcdSqs status));
37143dec9fcdSqs return (status);
37153dec9fcdSqs } else {
37163dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_add_intrs: "
37173dec9fcdSqs "interrupts registered : type %d", type));
37183dec9fcdSqs hxgep->hxge_intr_type.intr_registered = B_TRUE;
37193dec9fcdSqs
37203dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
37213dec9fcdSqs "\nAdded advanced hxge add_intr_adv "
37223dec9fcdSqs "intr type 0x%x\n", type));
37233dec9fcdSqs
37243dec9fcdSqs return (status);
37253dec9fcdSqs }
37263dec9fcdSqs }
37273dec9fcdSqs
37283dec9fcdSqs if (!hxgep->hxge_intr_type.intr_registered) {
37293dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
37303dec9fcdSqs "==> hxge_add_intrs: failed to register interrupts"));
37313dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
37323dec9fcdSqs }
37333dec9fcdSqs
37343dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs"));
37353dec9fcdSqs
37363dec9fcdSqs return (status);
37373dec9fcdSqs }
37383dec9fcdSqs
37393dec9fcdSqs /*ARGSUSED*/
37403dec9fcdSqs static hxge_status_t
hxge_add_intrs_adv(p_hxge_t hxgep)37413dec9fcdSqs hxge_add_intrs_adv(p_hxge_t hxgep)
37423dec9fcdSqs {
37433dec9fcdSqs int intr_type;
37443dec9fcdSqs p_hxge_intr_t intrp;
37453dec9fcdSqs hxge_status_t status;
37463dec9fcdSqs
37473dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv"));
37483dec9fcdSqs
37493dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
37503dec9fcdSqs intr_type = intrp->intr_type;
37513dec9fcdSqs
37523dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv: type 0x%x",
37533dec9fcdSqs intr_type));
37543dec9fcdSqs
37553dec9fcdSqs switch (intr_type) {
37563dec9fcdSqs case DDI_INTR_TYPE_MSI: /* 0x2 */
37573dec9fcdSqs case DDI_INTR_TYPE_MSIX: /* 0x4 */
37583dec9fcdSqs status = hxge_add_intrs_adv_type(hxgep, intr_type);
37593dec9fcdSqs break;
37603dec9fcdSqs
37613dec9fcdSqs case DDI_INTR_TYPE_FIXED: /* 0x1 */
37623dec9fcdSqs status = hxge_add_intrs_adv_type_fix(hxgep, intr_type);
37633dec9fcdSqs break;
37643dec9fcdSqs
37653dec9fcdSqs default:
37663dec9fcdSqs status = HXGE_ERROR;
37673dec9fcdSqs break;
37683dec9fcdSqs }
37693dec9fcdSqs
37703dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv"));
37713dec9fcdSqs
37723dec9fcdSqs return (status);
37733dec9fcdSqs }
37743dec9fcdSqs
37753dec9fcdSqs /*ARGSUSED*/
37763dec9fcdSqs static hxge_status_t
hxge_add_intrs_adv_type(p_hxge_t hxgep,uint32_t int_type)37773dec9fcdSqs hxge_add_intrs_adv_type(p_hxge_t hxgep, uint32_t int_type)
37783dec9fcdSqs {
37793dec9fcdSqs dev_info_t *dip = hxgep->dip;
37803dec9fcdSqs p_hxge_ldg_t ldgp;
37813dec9fcdSqs p_hxge_intr_t intrp;
37823dec9fcdSqs uint_t *inthandler;
37833dec9fcdSqs void *arg1, *arg2;
37843dec9fcdSqs int behavior;
37853dec9fcdSqs int nintrs, navail;
378657c5371aSQiyan Sun - Sun Microsystems - San Diego United States int nactual, nrequired, nrequest;
37873dec9fcdSqs int inum = 0;
37883dec9fcdSqs int loop = 0;
37893dec9fcdSqs int x, y;
37903dec9fcdSqs int ddi_status = DDI_SUCCESS;
37913dec9fcdSqs hxge_status_t status = HXGE_OK;
37923dec9fcdSqs
37933dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type"));
37943dec9fcdSqs
37953dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
37963dec9fcdSqs
37973dec9fcdSqs ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs);
37983dec9fcdSqs if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) {
37993dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
38003dec9fcdSqs "ddi_intr_get_nintrs() failed, status: 0x%x%, "
38013dec9fcdSqs "nintrs: %d", ddi_status, nintrs));
38023dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
38033dec9fcdSqs }
38043dec9fcdSqs
38053dec9fcdSqs ddi_status = ddi_intr_get_navail(dip, int_type, &navail);
38063dec9fcdSqs if ((ddi_status != DDI_SUCCESS) || (navail == 0)) {
38073dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
38083dec9fcdSqs "ddi_intr_get_navail() failed, status: 0x%x%, "
38093dec9fcdSqs "nintrs: %d", ddi_status, navail));
38103dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
38113dec9fcdSqs }
38123dec9fcdSqs
38133dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
38143dec9fcdSqs "ddi_intr_get_navail() returned: intr type %d nintrs %d, navail %d",
38153dec9fcdSqs int_type, nintrs, navail));
38163dec9fcdSqs
381757c5371aSQiyan Sun - Sun Microsystems - San Diego United States /* PSARC/2007/453 MSI-X interrupt limit override */
381857c5371aSQiyan Sun - Sun Microsystems - San Diego United States if (int_type == DDI_INTR_TYPE_MSIX) {
381957c5371aSQiyan Sun - Sun Microsystems - San Diego United States nrequest = hxge_create_msi_property(hxgep);
382057c5371aSQiyan Sun - Sun Microsystems - San Diego United States if (nrequest < navail) {
382157c5371aSQiyan Sun - Sun Microsystems - San Diego United States navail = nrequest;
382257c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, INT_CTL,
382357c5371aSQiyan Sun - Sun Microsystems - San Diego United States "hxge_add_intrs_adv_type: nintrs %d "
382457c5371aSQiyan Sun - Sun Microsystems - San Diego United States "navail %d (nrequest %d)",
382557c5371aSQiyan Sun - Sun Microsystems - San Diego United States nintrs, navail, nrequest));
382657c5371aSQiyan Sun - Sun Microsystems - San Diego United States }
382757c5371aSQiyan Sun - Sun Microsystems - San Diego United States }
382857c5371aSQiyan Sun - Sun Microsystems - San Diego United States
38293dec9fcdSqs if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) {
38303dec9fcdSqs /* MSI must be power of 2 */
38313dec9fcdSqs if ((navail & 16) == 16) {
38323dec9fcdSqs navail = 16;
38333dec9fcdSqs } else if ((navail & 8) == 8) {
38343dec9fcdSqs navail = 8;
38353dec9fcdSqs } else if ((navail & 4) == 4) {
38363dec9fcdSqs navail = 4;
38373dec9fcdSqs } else if ((navail & 2) == 2) {
38383dec9fcdSqs navail = 2;
38393dec9fcdSqs } else {
38403dec9fcdSqs navail = 1;
38413dec9fcdSqs }
38423dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
38433dec9fcdSqs "ddi_intr_get_navail(): (msi power of 2) nintrs %d, "
38443dec9fcdSqs "navail %d", nintrs, navail));
38453dec9fcdSqs }
38463dec9fcdSqs
38473dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
38483dec9fcdSqs "requesting: intr type %d nintrs %d, navail %d",
38493dec9fcdSqs int_type, nintrs, navail));
38503dec9fcdSqs
38513dec9fcdSqs behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT :
38523dec9fcdSqs DDI_INTR_ALLOC_NORMAL);
38533dec9fcdSqs intrp->intr_size = navail * sizeof (ddi_intr_handle_t);
38543dec9fcdSqs intrp->htable = kmem_zalloc(intrp->intr_size, KM_SLEEP);
38553dec9fcdSqs
38563dec9fcdSqs ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum,
38573dec9fcdSqs navail, &nactual, behavior);
38583dec9fcdSqs if (ddi_status != DDI_SUCCESS || nactual == 0) {
38593dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
38603dec9fcdSqs " ddi_intr_alloc() failed: %d", ddi_status));
38613dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
38623dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
38633dec9fcdSqs }
38643dec9fcdSqs
38653dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
38663dec9fcdSqs "ddi_intr_alloc() returned: navail %d nactual %d",
38673dec9fcdSqs navail, nactual));
38683dec9fcdSqs
38693dec9fcdSqs if ((ddi_status = ddi_intr_get_pri(intrp->htable[0],
38703dec9fcdSqs (uint_t *)&intrp->pri)) != DDI_SUCCESS) {
38713dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
38723dec9fcdSqs " ddi_intr_get_pri() failed: %d", ddi_status));
38733dec9fcdSqs /* Free already allocated interrupts */
38743dec9fcdSqs for (y = 0; y < nactual; y++) {
38753dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
38763dec9fcdSqs }
38773dec9fcdSqs
38783dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
38793dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
38803dec9fcdSqs }
38813dec9fcdSqs
38823dec9fcdSqs nrequired = 0;
38833dec9fcdSqs status = hxge_ldgv_init(hxgep, &nactual, &nrequired);
38843dec9fcdSqs if (status != HXGE_OK) {
38853dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
38863dec9fcdSqs "hxge_add_intrs_adv_typ:hxge_ldgv_init "
38873dec9fcdSqs "failed: 0x%x", status));
38883dec9fcdSqs /* Free already allocated interrupts */
38893dec9fcdSqs for (y = 0; y < nactual; y++) {
38903dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
38913dec9fcdSqs }
38923dec9fcdSqs
38933dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
38943dec9fcdSqs return (status);
38953dec9fcdSqs }
38963dec9fcdSqs
38973dec9fcdSqs ldgp = hxgep->ldgvp->ldgp;
38983dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
38993dec9fcdSqs "After hxge_ldgv_init(): nreq %d nactual %d", nrequired, nactual));
39003dec9fcdSqs
39013dec9fcdSqs if (nactual < nrequired)
39023dec9fcdSqs loop = nactual;
39033dec9fcdSqs else
39043dec9fcdSqs loop = nrequired;
39053dec9fcdSqs
39063dec9fcdSqs for (x = 0; x < loop; x++, ldgp++) {
39073dec9fcdSqs ldgp->vector = (uint8_t)x;
39083dec9fcdSqs arg1 = ldgp->ldvp;
39093dec9fcdSqs arg2 = hxgep;
39103dec9fcdSqs if (ldgp->nldvs == 1) {
39113dec9fcdSqs inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler;
39123dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
39133dec9fcdSqs "hxge_add_intrs_adv_type: arg1 0x%x arg2 0x%x: "
39143dec9fcdSqs "1-1 int handler (entry %d)\n",
39153dec9fcdSqs arg1, arg2, x));
39163dec9fcdSqs } else if (ldgp->nldvs > 1) {
39173dec9fcdSqs inthandler = (uint_t *)ldgp->sys_intr_handler;
39183dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
39193dec9fcdSqs "hxge_add_intrs_adv_type: arg1 0x%x arg2 0x%x: "
39203dec9fcdSqs "nldevs %d int handler (entry %d)\n",
39213dec9fcdSqs arg1, arg2, ldgp->nldvs, x));
39223dec9fcdSqs }
39233dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
39243dec9fcdSqs "==> hxge_add_intrs_adv_type: ddi_add_intr(inum) #%d "
39253dec9fcdSqs "htable 0x%llx", x, intrp->htable[x]));
39263dec9fcdSqs
39273dec9fcdSqs if ((ddi_status = ddi_intr_add_handler(intrp->htable[x],
39283dec9fcdSqs (ddi_intr_handler_t *)inthandler, arg1, arg2)) !=
39293dec9fcdSqs DDI_SUCCESS) {
39303dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
39313dec9fcdSqs "==> hxge_add_intrs_adv_type: failed #%d "
39323dec9fcdSqs "status 0x%x", x, ddi_status));
39333dec9fcdSqs for (y = 0; y < intrp->intr_added; y++) {
39343dec9fcdSqs (void) ddi_intr_remove_handler(
39353dec9fcdSqs intrp->htable[y]);
39363dec9fcdSqs }
39373dec9fcdSqs
39383dec9fcdSqs /* Free already allocated intr */
39393dec9fcdSqs for (y = 0; y < nactual; y++) {
39403dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
39413dec9fcdSqs }
39423dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
39433dec9fcdSqs
39443dec9fcdSqs (void) hxge_ldgv_uninit(hxgep);
39453dec9fcdSqs
39463dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
39473dec9fcdSqs }
39483dec9fcdSqs
39490dc2366fSVenugopal Iyer ldgp->htable_idx = x;
39503dec9fcdSqs intrp->intr_added++;
39513dec9fcdSqs }
39523dec9fcdSqs intrp->msi_intx_cnt = nactual;
39533dec9fcdSqs
39543dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
39553dec9fcdSqs "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d",
39563dec9fcdSqs navail, nactual, intrp->msi_intx_cnt, intrp->intr_added));
39573dec9fcdSqs
39583dec9fcdSqs (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap);
39593dec9fcdSqs (void) hxge_intr_ldgv_init(hxgep);
39603dec9fcdSqs
39613dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type"));
39623dec9fcdSqs
39633dec9fcdSqs return (status);
39643dec9fcdSqs }
39653dec9fcdSqs
39663dec9fcdSqs /*ARGSUSED*/
39673dec9fcdSqs static hxge_status_t
hxge_add_intrs_adv_type_fix(p_hxge_t hxgep,uint32_t int_type)39683dec9fcdSqs hxge_add_intrs_adv_type_fix(p_hxge_t hxgep, uint32_t int_type)
39693dec9fcdSqs {
39703dec9fcdSqs dev_info_t *dip = hxgep->dip;
39713dec9fcdSqs p_hxge_ldg_t ldgp;
39723dec9fcdSqs p_hxge_intr_t intrp;
39733dec9fcdSqs uint_t *inthandler;
39743dec9fcdSqs void *arg1, *arg2;
39753dec9fcdSqs int behavior;
39763dec9fcdSqs int nintrs, navail;
39773dec9fcdSqs int nactual, nrequired;
39783dec9fcdSqs int inum = 0;
39793dec9fcdSqs int x, y;
39803dec9fcdSqs int ddi_status = DDI_SUCCESS;
39813dec9fcdSqs hxge_status_t status = HXGE_OK;
39823dec9fcdSqs
39833dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_add_intrs_adv_type_fix"));
39843dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
39853dec9fcdSqs
39863dec9fcdSqs ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs);
39873dec9fcdSqs if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) {
39883dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
39893dec9fcdSqs "ddi_intr_get_nintrs() failed, status: 0x%x%, "
39903dec9fcdSqs "nintrs: %d", status, nintrs));
39913dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
39923dec9fcdSqs }
39933dec9fcdSqs
39943dec9fcdSqs ddi_status = ddi_intr_get_navail(dip, int_type, &navail);
39953dec9fcdSqs if ((ddi_status != DDI_SUCCESS) || (navail == 0)) {
39963dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
39973dec9fcdSqs "ddi_intr_get_navail() failed, status: 0x%x%, "
39983dec9fcdSqs "nintrs: %d", ddi_status, navail));
39993dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
40003dec9fcdSqs }
40013dec9fcdSqs
40023dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
40033dec9fcdSqs "ddi_intr_get_navail() returned: nintrs %d, naavail %d",
40043dec9fcdSqs nintrs, navail));
40053dec9fcdSqs
40063dec9fcdSqs behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT :
40073dec9fcdSqs DDI_INTR_ALLOC_NORMAL);
40083dec9fcdSqs intrp->intr_size = navail * sizeof (ddi_intr_handle_t);
40093dec9fcdSqs intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP);
40103dec9fcdSqs ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum,
40113dec9fcdSqs navail, &nactual, behavior);
40123dec9fcdSqs if (ddi_status != DDI_SUCCESS || nactual == 0) {
40133dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
40143dec9fcdSqs " ddi_intr_alloc() failed: %d", ddi_status));
40153dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
40163dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
40173dec9fcdSqs }
40183dec9fcdSqs
40193dec9fcdSqs if ((ddi_status = ddi_intr_get_pri(intrp->htable[0],
40203dec9fcdSqs (uint_t *)&intrp->pri)) != DDI_SUCCESS) {
40213dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
40223dec9fcdSqs " ddi_intr_get_pri() failed: %d", ddi_status));
40233dec9fcdSqs /* Free already allocated interrupts */
40243dec9fcdSqs for (y = 0; y < nactual; y++) {
40253dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
40263dec9fcdSqs }
40273dec9fcdSqs
40283dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
40293dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
40303dec9fcdSqs }
40313dec9fcdSqs
40323dec9fcdSqs nrequired = 0;
40333dec9fcdSqs status = hxge_ldgv_init(hxgep, &nactual, &nrequired);
40343dec9fcdSqs if (status != HXGE_OK) {
40353dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
40363dec9fcdSqs "hxge_add_intrs_adv_type_fix:hxge_ldgv_init "
40373dec9fcdSqs "failed: 0x%x", status));
40383dec9fcdSqs /* Free already allocated interrupts */
40393dec9fcdSqs for (y = 0; y < nactual; y++) {
40403dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
40413dec9fcdSqs }
40423dec9fcdSqs
40433dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
40443dec9fcdSqs return (status);
40453dec9fcdSqs }
40463dec9fcdSqs
40473dec9fcdSqs ldgp = hxgep->ldgvp->ldgp;
40483dec9fcdSqs for (x = 0; x < nrequired; x++, ldgp++) {
40493dec9fcdSqs ldgp->vector = (uint8_t)x;
40503dec9fcdSqs arg1 = ldgp->ldvp;
40513dec9fcdSqs arg2 = hxgep;
40523dec9fcdSqs if (ldgp->nldvs == 1) {
40533dec9fcdSqs inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler;
40543dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
40553dec9fcdSqs "hxge_add_intrs_adv_type_fix: "
40563dec9fcdSqs "1-1 int handler(%d) ldg %d ldv %d "
40573dec9fcdSqs "arg1 $%p arg2 $%p\n",
40583dec9fcdSqs x, ldgp->ldg, ldgp->ldvp->ldv, arg1, arg2));
40593dec9fcdSqs } else if (ldgp->nldvs > 1) {
40603dec9fcdSqs inthandler = (uint_t *)ldgp->sys_intr_handler;
40613dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
40623dec9fcdSqs "hxge_add_intrs_adv_type_fix: "
40633dec9fcdSqs "shared ldv %d int handler(%d) ldv %d ldg %d"
40643dec9fcdSqs "arg1 0x%016llx arg2 0x%016llx\n",
40653dec9fcdSqs x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv,
40663dec9fcdSqs arg1, arg2));
40673dec9fcdSqs }
40683dec9fcdSqs
40693dec9fcdSqs if ((ddi_status = ddi_intr_add_handler(intrp->htable[x],
40703dec9fcdSqs (ddi_intr_handler_t *)inthandler, arg1, arg2)) !=
40713dec9fcdSqs DDI_SUCCESS) {
40723dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL,
40733dec9fcdSqs "==> hxge_add_intrs_adv_type_fix: failed #%d "
40743dec9fcdSqs "status 0x%x", x, ddi_status));
40753dec9fcdSqs for (y = 0; y < intrp->intr_added; y++) {
40763dec9fcdSqs (void) ddi_intr_remove_handler(
40773dec9fcdSqs intrp->htable[y]);
40783dec9fcdSqs }
40793dec9fcdSqs for (y = 0; y < nactual; y++) {
40803dec9fcdSqs (void) ddi_intr_free(intrp->htable[y]);
40813dec9fcdSqs }
40823dec9fcdSqs /* Free already allocated intr */
40833dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
40843dec9fcdSqs
40853dec9fcdSqs (void) hxge_ldgv_uninit(hxgep);
40863dec9fcdSqs
40873dec9fcdSqs return (HXGE_ERROR | HXGE_DDI_FAILED);
40883dec9fcdSqs }
40893dec9fcdSqs intrp->intr_added++;
40903dec9fcdSqs }
40913dec9fcdSqs
40923dec9fcdSqs intrp->msi_intx_cnt = nactual;
40933dec9fcdSqs
40943dec9fcdSqs (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap);
40953dec9fcdSqs
40963dec9fcdSqs status = hxge_intr_ldgv_init(hxgep);
40973dec9fcdSqs
40983dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_add_intrs_adv_type_fix"));
40993dec9fcdSqs
41003dec9fcdSqs return (status);
41013dec9fcdSqs }
41023dec9fcdSqs
41033dec9fcdSqs /*ARGSUSED*/
41043dec9fcdSqs static void
hxge_remove_intrs(p_hxge_t hxgep)41053dec9fcdSqs hxge_remove_intrs(p_hxge_t hxgep)
41063dec9fcdSqs {
41073dec9fcdSqs int i, inum;
41083dec9fcdSqs p_hxge_intr_t intrp;
41093dec9fcdSqs
41103dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs"));
41113dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
41123dec9fcdSqs if (!intrp->intr_registered) {
41133dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
41143dec9fcdSqs "<== hxge_remove_intrs: interrupts not registered"));
41153dec9fcdSqs return;
41163dec9fcdSqs }
41173dec9fcdSqs
41183dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_remove_intrs:advanced"));
41193dec9fcdSqs
41203dec9fcdSqs if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) {
41213dec9fcdSqs (void) ddi_intr_block_disable(intrp->htable,
41223dec9fcdSqs intrp->intr_added);
41233dec9fcdSqs } else {
41243dec9fcdSqs for (i = 0; i < intrp->intr_added; i++) {
41253dec9fcdSqs (void) ddi_intr_disable(intrp->htable[i]);
41263dec9fcdSqs }
41273dec9fcdSqs }
41283dec9fcdSqs
41293dec9fcdSqs for (inum = 0; inum < intrp->intr_added; inum++) {
41303dec9fcdSqs if (intrp->htable[inum]) {
41313dec9fcdSqs (void) ddi_intr_remove_handler(intrp->htable[inum]);
41323dec9fcdSqs }
41333dec9fcdSqs }
41343dec9fcdSqs
41353dec9fcdSqs for (inum = 0; inum < intrp->msi_intx_cnt; inum++) {
41363dec9fcdSqs if (intrp->htable[inum]) {
41373dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
41383dec9fcdSqs "hxge_remove_intrs: ddi_intr_free inum %d "
41393dec9fcdSqs "msi_intx_cnt %d intr_added %d",
41403dec9fcdSqs inum, intrp->msi_intx_cnt, intrp->intr_added));
41413dec9fcdSqs
41423dec9fcdSqs (void) ddi_intr_free(intrp->htable[inum]);
41433dec9fcdSqs }
41443dec9fcdSqs }
41453dec9fcdSqs
41463dec9fcdSqs kmem_free(intrp->htable, intrp->intr_size);
41473dec9fcdSqs intrp->intr_registered = B_FALSE;
41483dec9fcdSqs intrp->intr_enabled = B_FALSE;
41493dec9fcdSqs intrp->msi_intx_cnt = 0;
41503dec9fcdSqs intrp->intr_added = 0;
41513dec9fcdSqs
41523dec9fcdSqs (void) hxge_ldgv_uninit(hxgep);
41533dec9fcdSqs
41543dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_remove_intrs"));
41553dec9fcdSqs }
41563dec9fcdSqs
41573dec9fcdSqs /*ARGSUSED*/
4158f043ebedSMichael Speer static void
hxge_intrs_enable(p_hxge_t hxgep)41593dec9fcdSqs hxge_intrs_enable(p_hxge_t hxgep)
41603dec9fcdSqs {
41613dec9fcdSqs p_hxge_intr_t intrp;
41623dec9fcdSqs int i;
41633dec9fcdSqs int status;
41643dec9fcdSqs
41653dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable"));
41663dec9fcdSqs
41673dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
41683dec9fcdSqs
41693dec9fcdSqs if (!intrp->intr_registered) {
41703dec9fcdSqs HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "<== hxge_intrs_enable: "
41713dec9fcdSqs "interrupts are not registered"));
41723dec9fcdSqs return;
41733dec9fcdSqs }
41743dec9fcdSqs
41753dec9fcdSqs if (intrp->intr_enabled) {
41763dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL,
41773dec9fcdSqs "<== hxge_intrs_enable: already enabled"));
41783dec9fcdSqs return;
41793dec9fcdSqs }
41803dec9fcdSqs
41813dec9fcdSqs if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) {
41823dec9fcdSqs status = ddi_intr_block_enable(intrp->htable,
41833dec9fcdSqs intrp->intr_added);
41843dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable "
41853dec9fcdSqs "block enable - status 0x%x total inums #%d\n",
41863dec9fcdSqs status, intrp->intr_added));
41873dec9fcdSqs } else {
41883dec9fcdSqs for (i = 0; i < intrp->intr_added; i++) {
41893dec9fcdSqs status = ddi_intr_enable(intrp->htable[i]);
41903dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_enable "
41913dec9fcdSqs "ddi_intr_enable:enable - status 0x%x "
41923dec9fcdSqs "total inums %d enable inum #%d\n",
41933dec9fcdSqs status, intrp->intr_added, i));
41943dec9fcdSqs if (status == DDI_SUCCESS) {
41953dec9fcdSqs intrp->intr_enabled = B_TRUE;
41963dec9fcdSqs }
41973dec9fcdSqs }
41983dec9fcdSqs }
41993dec9fcdSqs
42003dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_enable"));
42013dec9fcdSqs }
42023dec9fcdSqs
42033dec9fcdSqs /*ARGSUSED*/
42043dec9fcdSqs static void
hxge_intrs_disable(p_hxge_t hxgep)42053dec9fcdSqs hxge_intrs_disable(p_hxge_t hxgep)
42063dec9fcdSqs {
42073dec9fcdSqs p_hxge_intr_t intrp;
42083dec9fcdSqs int i;
42093dec9fcdSqs
42103dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_intrs_disable"));
42113dec9fcdSqs
42123dec9fcdSqs intrp = (p_hxge_intr_t)&hxgep->hxge_intr_type;
42133dec9fcdSqs
42143dec9fcdSqs if (!intrp->intr_registered) {
42153dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable: "
42163dec9fcdSqs "interrupts are not registered"));
42173dec9fcdSqs return;
42183dec9fcdSqs }
42193dec9fcdSqs
42203dec9fcdSqs if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) {
42213dec9fcdSqs (void) ddi_intr_block_disable(intrp->htable,
42223dec9fcdSqs intrp->intr_added);
42233dec9fcdSqs } else {
42243dec9fcdSqs for (i = 0; i < intrp->intr_added; i++) {
42253dec9fcdSqs (void) ddi_intr_disable(intrp->htable[i]);
42263dec9fcdSqs }
42273dec9fcdSqs }
42283dec9fcdSqs
42293dec9fcdSqs intrp->intr_enabled = B_FALSE;
42303dec9fcdSqs HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_intrs_disable"));
42313dec9fcdSqs }
42323dec9fcdSqs
42333dec9fcdSqs static hxge_status_t
hxge_mac_register(p_hxge_t hxgep)42343dec9fcdSqs hxge_mac_register(p_hxge_t hxgep)
42353dec9fcdSqs {
42363dec9fcdSqs mac_register_t *macp;
42373dec9fcdSqs int status;
42383dec9fcdSqs
42393dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "==> hxge_mac_register"));
42403dec9fcdSqs
42413dec9fcdSqs if ((macp = mac_alloc(MAC_VERSION)) == NULL)
42423dec9fcdSqs return (HXGE_ERROR);
42433dec9fcdSqs
42443dec9fcdSqs macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
42453dec9fcdSqs macp->m_driver = hxgep;
42463dec9fcdSqs macp->m_dip = hxgep->dip;
42473dec9fcdSqs macp->m_src_addr = hxgep->ouraddr.ether_addr_octet;
42481ed83081SMichael Speer macp->m_callbacks = &hxge_m_callbacks;
42491ed83081SMichael Speer macp->m_min_sdu = 0;
42501ed83081SMichael Speer macp->m_max_sdu = hxgep->vmac.maxframesize - MTU_TO_FRAME_SIZE;
42511ed83081SMichael Speer macp->m_margin = VLAN_TAGSZ;
42521ed83081SMichael Speer macp->m_priv_props = hxge_priv_props;
42531ed83081SMichael Speer macp->m_v12n = MAC_VIRT_LEVEL1;
42543dec9fcdSqs
42553dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL,
42563dec9fcdSqs "hxge_mac_register: ether addr is %x:%x:%x:%x:%x:%x",
42573dec9fcdSqs macp->m_src_addr[0],
42583dec9fcdSqs macp->m_src_addr[1],
42593dec9fcdSqs macp->m_src_addr[2],
42603dec9fcdSqs macp->m_src_addr[3],
42613dec9fcdSqs macp->m_src_addr[4],
42623dec9fcdSqs macp->m_src_addr[5]));
42633dec9fcdSqs
42643dec9fcdSqs status = mac_register(macp, &hxgep->mach);
42653dec9fcdSqs mac_free(macp);
42663dec9fcdSqs
42673dec9fcdSqs if (status != 0) {
42683dec9fcdSqs cmn_err(CE_WARN,
42693dec9fcdSqs "hxge_mac_register failed (status %d instance %d)",
42703dec9fcdSqs status, hxgep->instance);
42713dec9fcdSqs return (HXGE_ERROR);
42723dec9fcdSqs }
42733dec9fcdSqs
42743dec9fcdSqs HXGE_DEBUG_MSG((hxgep, DDI_CTL, "<== hxge_mac_register success "
42753dec9fcdSqs "(instance %d)", hxgep->instance));
42763dec9fcdSqs
42773dec9fcdSqs return (HXGE_OK);
42783dec9fcdSqs }
42793dec9fcdSqs
42803dec9fcdSqs static int
hxge_init_common_dev(p_hxge_t hxgep)42813dec9fcdSqs hxge_init_common_dev(p_hxge_t hxgep)
42823dec9fcdSqs {
42833dec9fcdSqs p_hxge_hw_list_t hw_p;
42843dec9fcdSqs dev_info_t *p_dip;
42853dec9fcdSqs
42863dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_init_common_dev"));
42873dec9fcdSqs
42883dec9fcdSqs p_dip = hxgep->p_dip;
42893dec9fcdSqs MUTEX_ENTER(&hxge_common_lock);
42903dec9fcdSqs
42913dec9fcdSqs /*
42923dec9fcdSqs * Loop through existing per Hydra hardware list.
42933dec9fcdSqs */
42943dec9fcdSqs for (hw_p = hxge_hw_list; hw_p; hw_p = hw_p->next) {
42953dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
42963dec9fcdSqs "==> hxge_init_common_dev: hw_p $%p parent dip $%p",
42973dec9fcdSqs hw_p, p_dip));
42983dec9fcdSqs if (hw_p->parent_devp == p_dip) {
42993dec9fcdSqs hxgep->hxge_hw_p = hw_p;
43003dec9fcdSqs hw_p->ndevs++;
43013dec9fcdSqs hw_p->hxge_p = hxgep;
43023dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43033dec9fcdSqs "==> hxge_init_common_device: "
43043dec9fcdSqs "hw_p $%p parent dip $%p ndevs %d (found)",
43053dec9fcdSqs hw_p, p_dip, hw_p->ndevs));
43063dec9fcdSqs break;
43073dec9fcdSqs }
43083dec9fcdSqs }
43093dec9fcdSqs
43103dec9fcdSqs if (hw_p == NULL) {
43113dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43123dec9fcdSqs "==> hxge_init_common_dev: parent dip $%p (new)", p_dip));
43133dec9fcdSqs hw_p = kmem_zalloc(sizeof (hxge_hw_list_t), KM_SLEEP);
43143dec9fcdSqs hw_p->parent_devp = p_dip;
43153dec9fcdSqs hw_p->magic = HXGE_MAGIC;
43163dec9fcdSqs hxgep->hxge_hw_p = hw_p;
43173dec9fcdSqs hw_p->ndevs++;
43183dec9fcdSqs hw_p->hxge_p = hxgep;
43193dec9fcdSqs hw_p->next = hxge_hw_list;
43203dec9fcdSqs
43213dec9fcdSqs MUTEX_INIT(&hw_p->hxge_cfg_lock, NULL, MUTEX_DRIVER, NULL);
43223dec9fcdSqs MUTEX_INIT(&hw_p->hxge_tcam_lock, NULL, MUTEX_DRIVER, NULL);
43233dec9fcdSqs MUTEX_INIT(&hw_p->hxge_vlan_lock, NULL, MUTEX_DRIVER, NULL);
43243dec9fcdSqs
43253dec9fcdSqs hxge_hw_list = hw_p;
43263dec9fcdSqs }
43273dec9fcdSqs MUTEX_EXIT(&hxge_common_lock);
43283dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43293dec9fcdSqs "==> hxge_init_common_dev (hxge_hw_list) $%p", hxge_hw_list));
43303dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<== hxge_init_common_dev"));
43313dec9fcdSqs
43323dec9fcdSqs return (HXGE_OK);
43333dec9fcdSqs }
43343dec9fcdSqs
43353dec9fcdSqs static void
hxge_uninit_common_dev(p_hxge_t hxgep)43363dec9fcdSqs hxge_uninit_common_dev(p_hxge_t hxgep)
43373dec9fcdSqs {
43383dec9fcdSqs p_hxge_hw_list_t hw_p, h_hw_p;
43393dec9fcdSqs dev_info_t *p_dip;
43403dec9fcdSqs
43413dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==> hxge_uninit_common_dev"));
43423dec9fcdSqs if (hxgep->hxge_hw_p == NULL) {
43433dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43443dec9fcdSqs "<== hxge_uninit_common_dev (no common)"));
43453dec9fcdSqs return;
43463dec9fcdSqs }
43473dec9fcdSqs
43483dec9fcdSqs MUTEX_ENTER(&hxge_common_lock);
43493dec9fcdSqs h_hw_p = hxge_hw_list;
43503dec9fcdSqs for (hw_p = hxge_hw_list; hw_p; hw_p = hw_p->next) {
43513dec9fcdSqs p_dip = hw_p->parent_devp;
43523dec9fcdSqs if (hxgep->hxge_hw_p == hw_p && p_dip == hxgep->p_dip &&
43533dec9fcdSqs hxgep->hxge_hw_p->magic == HXGE_MAGIC &&
43543dec9fcdSqs hw_p->magic == HXGE_MAGIC) {
43553dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43563dec9fcdSqs "==> hxge_uninit_common_dev: "
43573dec9fcdSqs "hw_p $%p parent dip $%p ndevs %d (found)",
43583dec9fcdSqs hw_p, p_dip, hw_p->ndevs));
43593dec9fcdSqs
43603dec9fcdSqs hxgep->hxge_hw_p = NULL;
43613dec9fcdSqs if (hw_p->ndevs) {
43623dec9fcdSqs hw_p->ndevs--;
43633dec9fcdSqs }
43643dec9fcdSqs hw_p->hxge_p = NULL;
43653dec9fcdSqs if (!hw_p->ndevs) {
43663dec9fcdSqs MUTEX_DESTROY(&hw_p->hxge_vlan_lock);
43673dec9fcdSqs MUTEX_DESTROY(&hw_p->hxge_tcam_lock);
43683dec9fcdSqs MUTEX_DESTROY(&hw_p->hxge_cfg_lock);
43693dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43703dec9fcdSqs "==> hxge_uninit_common_dev: "
43713dec9fcdSqs "hw_p $%p parent dip $%p ndevs %d (last)",
43723dec9fcdSqs hw_p, p_dip, hw_p->ndevs));
43733dec9fcdSqs
43743dec9fcdSqs if (hw_p == hxge_hw_list) {
43753dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43763dec9fcdSqs "==> hxge_uninit_common_dev:"
43773dec9fcdSqs "remove head "
43783dec9fcdSqs "hw_p $%p parent dip $%p "
43793dec9fcdSqs "ndevs %d (head)",
43803dec9fcdSqs hw_p, p_dip, hw_p->ndevs));
43813dec9fcdSqs hxge_hw_list = hw_p->next;
43823dec9fcdSqs } else {
43833dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
43843dec9fcdSqs "==> hxge_uninit_common_dev:"
43853dec9fcdSqs "remove middle "
43863dec9fcdSqs "hw_p $%p parent dip $%p "
43873dec9fcdSqs "ndevs %d (middle)",
43883dec9fcdSqs hw_p, p_dip, hw_p->ndevs));
43893dec9fcdSqs h_hw_p->next = hw_p->next;
43903dec9fcdSqs }
43913dec9fcdSqs
43923dec9fcdSqs KMEM_FREE(hw_p, sizeof (hxge_hw_list_t));
43933dec9fcdSqs }
43943dec9fcdSqs break;
43953dec9fcdSqs } else {
43963dec9fcdSqs h_hw_p = hw_p;
43973dec9fcdSqs }
43983dec9fcdSqs }
43993dec9fcdSqs
44003dec9fcdSqs MUTEX_EXIT(&hxge_common_lock);
44013dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL,
44023dec9fcdSqs "==> hxge_uninit_common_dev (hxge_hw_list) $%p", hxge_hw_list));
44033dec9fcdSqs
44043dec9fcdSqs HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<= hxge_uninit_common_dev"));
44053dec9fcdSqs }
4406a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
44071c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_MSIX_ENTRIES 32
44081c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_MSIX_WAIT_COUNT 10
44091c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States #define HXGE_MSIX_PARITY_CHECK_COUNT 30
44101c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
4411a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States static void
hxge_link_poll(void * arg)4412a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_link_poll(void *arg)
4413a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States {
4414a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_t hxgep = (p_hxge_t)arg;
4415a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hpi_handle_t handle;
4416a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States cip_link_stat_t link_stat;
4417a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States hxge_timeout *to = &hxgep->timeout;
4418a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
4419a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States handle = HXGE_DEV_HPI_HANDLE(hxgep);
4420a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_RD32(handle, CIP_LINK_STAT, &link_stat.value);
4421a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
4422e5d97391SQiyan Sun - Sun Microsystems - San Diego United States if (to->report_link_status ||
4423e5d97391SQiyan Sun - Sun Microsystems - San Diego United States (to->link_status != link_stat.bits.xpcs0_link_up)) {
4424a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States to->link_status = link_stat.bits.xpcs0_link_up;
4425e5d97391SQiyan Sun - Sun Microsystems - San Diego United States to->report_link_status = B_FALSE;
4426a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
4427a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States if (link_stat.bits.xpcs0_link_up) {
4428e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxge_link_update(hxgep, LINK_STATE_UP);
4429a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States } else {
4430e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxge_link_update(hxgep, LINK_STATE_DOWN);
4431a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
4432a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
4433a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States
4434a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States /* Restart the link status timer to check the link status */
4435a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_ENTER(&to->lock);
4436a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States to->id = timeout(hxge_link_poll, arg, to->ticks);
4437a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States MUTEX_EXIT(&to->lock);
4438a512c5d1SQiyan Sun - Sun Microsystems - San Diego United States }
4439e5d97391SQiyan Sun - Sun Microsystems - San Diego United States
4440e5d97391SQiyan Sun - Sun Microsystems - San Diego United States static void
hxge_link_update(p_hxge_t hxgep,link_state_t state)4441e5d97391SQiyan Sun - Sun Microsystems - San Diego United States hxge_link_update(p_hxge_t hxgep, link_state_t state)
4442e5d97391SQiyan Sun - Sun Microsystems - San Diego United States {
4443e5d97391SQiyan Sun - Sun Microsystems - San Diego United States p_hxge_stats_t statsp = (p_hxge_stats_t)hxgep->statsp;
4444e5d97391SQiyan Sun - Sun Microsystems - San Diego United States
4445e5d97391SQiyan Sun - Sun Microsystems - San Diego United States mac_link_update(hxgep->mach, state);
4446e5d97391SQiyan Sun - Sun Microsystems - San Diego United States if (state == LINK_STATE_UP) {
4447e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_speed = 10000;
4448e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_duplex = 2;
4449e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_up = 1;
4450e5d97391SQiyan Sun - Sun Microsystems - San Diego United States } else {
4451e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_speed = 0;
4452e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_duplex = 0;
4453e5d97391SQiyan Sun - Sun Microsystems - San Diego United States statsp->mac_stats.link_up = 0;
4454e5d97391SQiyan Sun - Sun Microsystems - San Diego United States }
4455e5d97391SQiyan Sun - Sun Microsystems - San Diego United States }
44561c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
44571c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States static void
hxge_msix_init(p_hxge_t hxgep)44581c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States hxge_msix_init(p_hxge_t hxgep)
44591c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States {
4460*c11cea93SToomas Soome uint32_t data0;
4461*c11cea93SToomas Soome uint32_t data1;
4462*c11cea93SToomas Soome uint32_t data2;
44631c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States int i;
446457c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_entry0;
446557c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_entry1;
446657c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_entry2;
446757c5371aSQiyan Sun - Sun Microsystems - San Diego United States uint32_t msix_entry3;
44681c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
446957c5371aSQiyan Sun - Sun Microsystems - San Diego United States /* Change to use MSIx bar instead of indirect access */
44701c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States for (i = 0; i < HXGE_MSIX_ENTRIES; i++) {
447157c5371aSQiyan Sun - Sun Microsystems - San Diego United States data0 = 0xffffffff - i;
447257c5371aSQiyan Sun - Sun Microsystems - San Diego United States data1 = 0xffffffff - i - 1;
447357c5371aSQiyan Sun - Sun Microsystems - San Diego United States data2 = 0xffffffff - i - 2;
447457c5371aSQiyan Sun - Sun Microsystems - San Diego United States
447557c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16, data0);
447657c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 4, data1);
447757c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 8, data2);
4478f043ebedSMichael Speer HXGE_REG_WR32(hxgep->hpi_msi_handle, i * 16 + 12, 0);
44791c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States }
44801c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
448157c5371aSQiyan Sun - Sun Microsystems - San Diego United States /* Initialize ram data out buffer. */
44821c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States for (i = 0; i < HXGE_MSIX_ENTRIES; i++) {
448357c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16, &msix_entry0);
448457c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 4, &msix_entry1);
448557c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 8, &msix_entry2);
448657c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_REG_RD32(hxgep->hpi_msi_handle, i * 16 + 12, &msix_entry3);
448757c5371aSQiyan Sun - Sun Microsystems - San Diego United States }
448857c5371aSQiyan Sun - Sun Microsystems - San Diego United States }
44891c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
449057c5371aSQiyan Sun - Sun Microsystems - San Diego United States /*
449157c5371aSQiyan Sun - Sun Microsystems - San Diego United States * The following function is to support
449257c5371aSQiyan Sun - Sun Microsystems - San Diego United States * PSARC/2007/453 MSI-X interrupt limit override.
449357c5371aSQiyan Sun - Sun Microsystems - San Diego United States */
449457c5371aSQiyan Sun - Sun Microsystems - San Diego United States static int
hxge_create_msi_property(p_hxge_t hxgep)449557c5371aSQiyan Sun - Sun Microsystems - San Diego United States hxge_create_msi_property(p_hxge_t hxgep)
44961c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States {
449757c5371aSQiyan Sun - Sun Microsystems - San Diego United States int nmsi;
449857c5371aSQiyan Sun - Sun Microsystems - San Diego United States extern int ncpus;
449957c5371aSQiyan Sun - Sun Microsystems - San Diego United States
450057c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, MOD_CTL, "==>hxge_create_msi_property"));
450157c5371aSQiyan Sun - Sun Microsystems - San Diego United States
450257c5371aSQiyan Sun - Sun Microsystems - San Diego United States (void) ddi_prop_create(DDI_DEV_T_NONE, hxgep->dip,
450357c5371aSQiyan Sun - Sun Microsystems - San Diego United States DDI_PROP_CANSLEEP, "#msix-request", NULL, 0);
450457c5371aSQiyan Sun - Sun Microsystems - San Diego United States /*
450557c5371aSQiyan Sun - Sun Microsystems - San Diego United States * The maximum MSI-X requested will be 8.
450657c5371aSQiyan Sun - Sun Microsystems - San Diego United States * If the # of CPUs is less than 8, we will reqeust
450757c5371aSQiyan Sun - Sun Microsystems - San Diego United States * # MSI-X based on the # of CPUs.
450857c5371aSQiyan Sun - Sun Microsystems - San Diego United States */
450957c5371aSQiyan Sun - Sun Microsystems - San Diego United States if (ncpus >= HXGE_MSIX_REQUEST_10G) {
451057c5371aSQiyan Sun - Sun Microsystems - San Diego United States nmsi = HXGE_MSIX_REQUEST_10G;
451157c5371aSQiyan Sun - Sun Microsystems - San Diego United States } else {
451257c5371aSQiyan Sun - Sun Microsystems - San Diego United States nmsi = ncpus;
45131c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States }
45141c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States
451557c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, MOD_CTL,
451657c5371aSQiyan Sun - Sun Microsystems - San Diego United States "==>hxge_create_msi_property(10G): exists 0x%x (nmsi %d)",
451757c5371aSQiyan Sun - Sun Microsystems - San Diego United States ddi_prop_exists(DDI_DEV_T_NONE, hxgep->dip,
451857c5371aSQiyan Sun - Sun Microsystems - San Diego United States DDI_PROP_CANSLEEP, "#msix-request"), nmsi));
451957c5371aSQiyan Sun - Sun Microsystems - San Diego United States
452057c5371aSQiyan Sun - Sun Microsystems - San Diego United States HXGE_DEBUG_MSG((hxgep, MOD_CTL, "<==hxge_create_msi_property"));
452157c5371aSQiyan Sun - Sun Microsystems - San Diego United States return (nmsi);
45221c29f7e3SQiyan Sun - Sun Microsystems - San Diego United States }
4523