1*3dec9fcdSqs /* 2*3dec9fcdSqs * CDDL HEADER START 3*3dec9fcdSqs * 4*3dec9fcdSqs * The contents of this file are subject to the terms of the 5*3dec9fcdSqs * Common Development and Distribution License (the "License"). 6*3dec9fcdSqs * You may not use this file except in compliance with the License. 7*3dec9fcdSqs * 8*3dec9fcdSqs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*3dec9fcdSqs * or http://www.opensolaris.org/os/licensing. 10*3dec9fcdSqs * See the License for the specific language governing permissions 11*3dec9fcdSqs * and limitations under the License. 12*3dec9fcdSqs * 13*3dec9fcdSqs * When distributing Covered Code, include this CDDL HEADER in each 14*3dec9fcdSqs * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*3dec9fcdSqs * If applicable, add the following below this CDDL HEADER, with the 16*3dec9fcdSqs * fields enclosed by brackets "[]" replaced with your own identifying 17*3dec9fcdSqs * information: Portions Copyright [yyyy] [name of copyright owner] 18*3dec9fcdSqs * 19*3dec9fcdSqs * CDDL HEADER END 20*3dec9fcdSqs */ 21*3dec9fcdSqs /* 22*3dec9fcdSqs * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23*3dec9fcdSqs * Use is subject to license terms. 24*3dec9fcdSqs */ 25*3dec9fcdSqs 26*3dec9fcdSqs #ifndef _SYS_HXGE_HXGE_COMMON_H 27*3dec9fcdSqs #define _SYS_HXGE_HXGE_COMMON_H 28*3dec9fcdSqs 29*3dec9fcdSqs #pragma ident "%Z%%M% %I% %E% SMI" 30*3dec9fcdSqs 31*3dec9fcdSqs #include <sys/types.h> 32*3dec9fcdSqs #include <hxge_defs.h> 33*3dec9fcdSqs #include <hxge_pfc.h> 34*3dec9fcdSqs #include <hxge_common_impl.h> 35*3dec9fcdSqs 36*3dec9fcdSqs #ifdef __cplusplus 37*3dec9fcdSqs extern "C" { 38*3dec9fcdSqs #endif 39*3dec9fcdSqs 40*3dec9fcdSqs #define HXGE_DMA_START B_TRUE 41*3dec9fcdSqs #define HXGE_DMA_STOP B_FALSE 42*3dec9fcdSqs #define HXGE_TIMER_RESO 2 43*3dec9fcdSqs #define HXGE_TIMER_LDG 2 44*3dec9fcdSqs 45*3dec9fcdSqs /* 46*3dec9fcdSqs * Receive and Transmit DMA definitions 47*3dec9fcdSqs */ 48*3dec9fcdSqs #ifdef _DMA_USES_VIRTADDR 49*3dec9fcdSqs #define HXGE_DMA_BLOCK 1 50*3dec9fcdSqs #else 51*3dec9fcdSqs #define HXGE_DMA_BLOCK (64 * 64) 52*3dec9fcdSqs #endif 53*3dec9fcdSqs 54*3dec9fcdSqs #define HXGE_RBR_RBB_MIN (128) 55*3dec9fcdSqs #define HXGE_RBR_RBB_MAX (64 * 128 -1) 56*3dec9fcdSqs #define HXGE_RBR_RBB_DEFAULT (64 * 16) /* x86 hello */ 57*3dec9fcdSqs #define HXGE_RCR_MIN (HXGE_RBR_RBB_MIN * 2) 58*3dec9fcdSqs #define HXGE_RCR_MAX (65504) /* 2^16 - 32 */ 59*3dec9fcdSqs 60*3dec9fcdSqs #if defined(_BIG_ENDIAN) 61*3dec9fcdSqs #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 8) 62*3dec9fcdSqs #else /* _BIG_ENDIAN */ 63*3dec9fcdSqs #ifdef USE_RX_BIG_BUF 64*3dec9fcdSqs #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 8) 65*3dec9fcdSqs #else 66*3dec9fcdSqs #define HXGE_RCR_DEFAULT (HXGE_RBR_RBB_DEFAULT * 4) 67*3dec9fcdSqs #endif 68*3dec9fcdSqs #endif /* _BIG_ENDIAN */ 69*3dec9fcdSqs 70*3dec9fcdSqs #define HXGE_TX_RING_DEFAULT (1024) 71*3dec9fcdSqs #define HXGE_TX_RING_MAX (64 * 128 - 1) 72*3dec9fcdSqs 73*3dec9fcdSqs #define RBR_BKSIZE_4K 0 74*3dec9fcdSqs #define RBR_BKSIZE_8K 1 75*3dec9fcdSqs #define RBR_BKSIZE_4K_BYTES (4 * 1024) 76*3dec9fcdSqs 77*3dec9fcdSqs #define RBR_BUFSZ2_2K 0 78*3dec9fcdSqs #define RBR_BUFSZ2_4K 1 79*3dec9fcdSqs #define RBR_BUFSZ2_2K_BYTES (2 * 1024) 80*3dec9fcdSqs #define RBR_BUFSZ2_4K_BYTES (4 * 1024) 81*3dec9fcdSqs 82*3dec9fcdSqs #define RBR_BUFSZ1_1K 0 83*3dec9fcdSqs #define RBR_BUFSZ1_2K 1 84*3dec9fcdSqs #define RBR_BUFSZ1_1K_BYTES 1024 85*3dec9fcdSqs #define RBR_BUFSZ1_2K_BYTES (2 * 1024) 86*3dec9fcdSqs 87*3dec9fcdSqs #define RBR_BUFSZ0_256B 0 88*3dec9fcdSqs #define RBR_BUFSZ0_512B 1 89*3dec9fcdSqs #define RBR_BUFSZ0_1K 2 90*3dec9fcdSqs #define RBR_BUFSZ0_256_BYTES 256 91*3dec9fcdSqs #define RBR_BUFSZ0_512B_BYTES 512 92*3dec9fcdSqs #define RBR_BUFSZ0_1K_BYTES (1024) 93*3dec9fcdSqs 94*3dec9fcdSqs /* 95*3dec9fcdSqs * VLAN table configuration 96*3dec9fcdSqs */ 97*3dec9fcdSqs typedef struct hxge_mv_cfg { 98*3dec9fcdSqs uint8_t flag; /* 0:unconfigure 1:configured */ 99*3dec9fcdSqs } hxge_mv_cfg_t, *p_hxge_mv_cfg_t; 100*3dec9fcdSqs 101*3dec9fcdSqs typedef struct hxge_param_map { 102*3dec9fcdSqs #if defined(_BIG_ENDIAN) 103*3dec9fcdSqs uint32_t rsrvd2:2; /* [30:31] rsrvd */ 104*3dec9fcdSqs uint32_t remove:1; /* [29] Remove */ 105*3dec9fcdSqs uint32_t pref:1; /* [28] preference */ 106*3dec9fcdSqs uint32_t rsrv:4; /* [27:24] preference */ 107*3dec9fcdSqs uint32_t map_to:8; /* [23:16] map to resource */ 108*3dec9fcdSqs uint32_t param_id:16; /* [15:0] Param ID */ 109*3dec9fcdSqs #else 110*3dec9fcdSqs uint32_t param_id:16; /* [15:0] Param ID */ 111*3dec9fcdSqs uint32_t map_to:8; /* [23:16] map to resource */ 112*3dec9fcdSqs uint32_t rsrv:4; /* [27:24] preference */ 113*3dec9fcdSqs uint32_t pref:1; /* [28] preference */ 114*3dec9fcdSqs uint32_t remove:1; /* [29] Remove */ 115*3dec9fcdSqs uint32_t rsrvd2:2; /* [30:31] rsrvd */ 116*3dec9fcdSqs #endif 117*3dec9fcdSqs } hxge_param_map_t, *p_hxge_param_map_t; 118*3dec9fcdSqs 119*3dec9fcdSqs typedef struct hxge_hw_pt_cfg { 120*3dec9fcdSqs uint32_t start_tdc; /* start TDC (0 - 3) */ 121*3dec9fcdSqs uint32_t max_tdcs; /* max TDC in sequence */ 122*3dec9fcdSqs uint32_t start_rdc; /* start RDC (0 - 3) */ 123*3dec9fcdSqs uint32_t max_rdcs; /* max rdc in sequence */ 124*3dec9fcdSqs uint32_t rx_full_header; /* select the header flag */ 125*3dec9fcdSqs uint32_t start_ldg; /* starting logical group # */ 126*3dec9fcdSqs uint32_t max_ldgs; /* max logical device group */ 127*3dec9fcdSqs uint32_t max_ldvs; /* max logical devices */ 128*3dec9fcdSqs } hxge_hw_pt_cfg_t, *p_hxge_hw_pt_cfg_t; 129*3dec9fcdSqs 130*3dec9fcdSqs /* per port configuration */ 131*3dec9fcdSqs typedef struct hxge_dma_pt_cfg { 132*3dec9fcdSqs hxge_hw_pt_cfg_t hw_config; /* hardware configuration */ 133*3dec9fcdSqs 134*3dec9fcdSqs uint32_t alloc_buf_size; 135*3dec9fcdSqs uint32_t rbr_size; 136*3dec9fcdSqs uint32_t rcr_size; 137*3dec9fcdSqs } hxge_dma_pt_cfg_t, *p_hxge_dma_pt_cfg_t; 138*3dec9fcdSqs 139*3dec9fcdSqs /* classification configuration */ 140*3dec9fcdSqs typedef struct hxge_class_pt_cfg { 141*3dec9fcdSqs /* VLAN table */ 142*3dec9fcdSqs hxge_mv_cfg_t vlan_tbl[VLAN_ID_MAX + 1]; 143*3dec9fcdSqs /* class config value */ 144*3dec9fcdSqs uint32_t init_hash; 145*3dec9fcdSqs uint32_t class_cfg[TCAM_CLASS_MAX]; 146*3dec9fcdSqs } hxge_class_pt_cfg_t, *p_hxge_class_pt_cfg_t; 147*3dec9fcdSqs 148*3dec9fcdSqs typedef struct hxge_hw_list { 149*3dec9fcdSqs struct hxge_hw_list *next; 150*3dec9fcdSqs hxge_os_mutex_t hxge_cfg_lock; 151*3dec9fcdSqs hxge_os_mutex_t hxge_tcam_lock; 152*3dec9fcdSqs hxge_os_mutex_t hxge_vlan_lock; 153*3dec9fcdSqs 154*3dec9fcdSqs hxge_dev_info_t *parent_devp; 155*3dec9fcdSqs struct _hxge_t *hxge_p; 156*3dec9fcdSqs uint32_t ndevs; 157*3dec9fcdSqs uint32_t flags; 158*3dec9fcdSqs uint32_t magic; 159*3dec9fcdSqs } hxge_hw_list_t, *p_hxge_hw_list_t; 160*3dec9fcdSqs 161*3dec9fcdSqs #ifdef __cplusplus 162*3dec9fcdSqs } 163*3dec9fcdSqs #endif 164*3dec9fcdSqs 165*3dec9fcdSqs #endif /* _SYS_HXGE_HXGE_COMMON_H */ 166