xref: /illumos-gate/usr/src/uts/common/io/hxge/hxge.h (revision b83cd2c3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_HXGE_HXGE_H
27 #define	_SYS_HXGE_HXGE_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <hxge_vmac.h>
34 #include <hxge_pfc.h>
35 #include <hxge_classify.h>
36 
37 /*
38  * HXGE diagnostics IOCTLS.
39  */
40 #define	HXGE_IOC		((((('N' << 8) + 'X') << 8) + 'G') << 8)
41 
42 #define	HXGE_GET64		(HXGE_IOC|1)
43 #define	HXGE_PUT64		(HXGE_IOC|2)
44 #define	HXGE_GET_TX_RING_SZ	(HXGE_IOC|3)
45 #define	HXGE_GET_TX_DESC	(HXGE_IOC|4)
46 #define	HXGE_GLOBAL_RESET	(HXGE_IOC|5)
47 #define	HXGE_TX_SIDE_RESET	(HXGE_IOC|6)
48 #define	HXGE_RX_SIDE_RESET	(HXGE_IOC|7)
49 #define	HXGE_RESET_MAC		(HXGE_IOC|8)
50 #define	HXGE_RTRACE		(HXGE_IOC|9)
51 #define	HXGE_GET_TCAM		(HXGE_IOC|10)
52 #define	HXGE_PUT_TCAM		(HXGE_IOC|11)
53 
54 #define	HXGE_OK			0
55 #define	HXGE_ERROR		0x40000000
56 #define	HXGE_DDI_FAILED		0x20000000
57 
58 /*
59  * Definitions for module_info.
60  */
61 #define	HXGE_DRIVER_NAME	"hxge"			/* module name */
62 #define	HXGE_CHECK_TIMER	(5000)
63 
64 typedef enum {
65 	param_instance,
66 
67 	param_accept_jumbo,
68 	param_rxdma_rbr_size,
69 	param_rxdma_rcr_size,
70 	param_rxdma_intr_time,
71 	param_rxdma_intr_pkts,
72 	param_vlan_ids,
73 	param_implicit_vlan_id,
74 	param_tcam_enable,
75 
76 	param_hash_init_value,
77 	param_class_cfg_ether_usr1,
78 	param_class_cfg_ether_usr2,
79 	param_class_opt_ipv4_tcp,
80 	param_class_opt_ipv4_udp,
81 	param_class_opt_ipv4_ah,
82 	param_class_opt_ipv4_sctp,
83 	param_class_opt_ipv6_tcp,
84 	param_class_opt_ipv6_udp,
85 	param_class_opt_ipv6_ah,
86 	param_class_opt_ipv6_sctp,
87 	param_hxge_debug_flag,
88 	param_hpi_debug_flag,
89 	param_dump_ptrs,
90 	param_end
91 } hxge_param_index_t;
92 
93 
94 #define	HXGE_PARAM_READ			0x00000001ULL
95 #define	HXGE_PARAM_WRITE		0x00000002ULL
96 #define	HXGE_PARAM_SHARED		0x00000004ULL
97 #define	HXGE_PARAM_PRIV			0x00000008ULL
98 #define	HXGE_PARAM_RW			HXGE_PARAM_READ | HXGE_PARAM_WRITE
99 #define	HXGE_PARAM_RWS			HXGE_PARAM_RW | HXGE_PARAM_SHARED
100 #define	HXGE_PARAM_RWP			HXGE_PARAM_RW | HXGE_PARAM_PRIV
101 
102 #define	HXGE_PARAM_RXDMA		0x00000010ULL
103 #define	HXGE_PARAM_TXDMA		0x00000020ULL
104 #define	HXGE_PARAM_MAC			0x00000040ULL
105 
106 #define	HXGE_PARAM_CMPLX		0x00010000ULL
107 #define	HXGE_PARAM_NDD_WR_OK		0x00020000ULL
108 #define	HXGE_PARAM_INIT_ONLY		0x00040000ULL
109 #define	HXGE_PARAM_INIT_CONFIG		0x00080000ULL
110 
111 #define	HXGE_PARAM_READ_PROP		0x00100000ULL
112 #define	HXGE_PARAM_PROP_ARR32		0x00200000ULL
113 #define	HXGE_PARAM_PROP_ARR64		0x00400000ULL
114 #define	HXGE_PARAM_PROP_STR		0x00800000ULL
115 
116 #define	HXGE_PARAM_DONT_SHOW		0x80000000ULL
117 
118 #define	HXGE_PARAM_ARRAY_CNT_MASK	0x0000ffff00000000ULL
119 #define	HXGE_PARAM_ARRAY_CNT_SHIFT	32ULL
120 #define	HXGE_PARAM_ARRAY_ALLOC_MASK	0xffff000000000000ULL
121 #define	HXGE_PARAM_ARRAY_ALLOC_SHIFT	48ULL
122 
123 typedef struct _hxge_param_t {
124 	int (*getf)();
125 	int (*setf)();		/* null for read only */
126 	uint64_t type;		/* R/W/ Common/Port/ .... */
127 	uint64_t minimum;
128 	uint64_t maximum;
129 	uint64_t value;		/* for array params, pointer to value array */
130 	uint64_t old_value; /* for array params, pointer to old_value array */
131 	char   *fcode_name;
132 	char   *name;
133 } hxge_param_t, *p_hxge_param_t;
134 
135 
136 typedef enum {
137 	hxge_lb_normal,
138 	hxge_lb_mac10g
139 } hxge_lb_t;
140 
141 enum hxge_mac_state {
142 	HXGE_MAC_STOPPED = 0,
143 	HXGE_MAC_STARTED
144 };
145 
146 typedef struct _filter_t {
147 	uint32_t all_phys_cnt;
148 	uint32_t all_multicast_cnt;
149 	uint32_t all_sap_cnt;
150 } filter_t, *p_filter_t;
151 
152 typedef struct _hxge_port_stats_t {
153 	hxge_lb_t		lb_mode;
154 	uint32_t		poll_mode;
155 } hxge_port_stats_t, *p_hxge_port_stats_t;
156 
157 
158 typedef struct _hxge_peu_sys_stats {
159 	uint32_t	spc_acc_err;
160 	uint32_t	tdc_pioacc_err;
161 	uint32_t	rdc_pioacc_err;
162 	uint32_t	pfc_pioacc_err;
163 	uint32_t	vmac_pioacc_err;
164 	uint32_t	cpl_hdrq_parerr;
165 	uint32_t	cpl_dataq_parerr;
166 	uint32_t	retryram_xdlh_parerr;
167 	uint32_t	retrysotram_xdlh_parerr;
168 	uint32_t	p_hdrq_parerr;
169 	uint32_t	p_dataq_parerr;
170 	uint32_t	np_hdrq_parerr;
171 	uint32_t	np_dataq_parerr;
172 	uint32_t	eic_msix_parerr;
173 	uint32_t	hcr_parerr;
174 } hxge_peu_sys_stats_t, *p_hxge_peu_sys_stats_t;
175 
176 
177 typedef struct _hxge_stats_t {
178 	/*
179 	 *  Overall structure size
180 	 */
181 	size_t			stats_size;
182 
183 	kstat_t			*ksp;
184 	kstat_t			*rdc_ksp[HXGE_MAX_RDCS];
185 	kstat_t			*tdc_ksp[HXGE_MAX_TDCS];
186 	kstat_t			*rdc_sys_ksp;
187 	kstat_t			*tdc_sys_ksp;
188 	kstat_t			*pfc_ksp;
189 	kstat_t			*vmac_ksp;
190 	kstat_t			*port_ksp;
191 	kstat_t			*mmac_ksp;
192 	kstat_t			*peu_sys_ksp;
193 
194 	hxge_mac_stats_t	mac_stats;
195 	hxge_vmac_stats_t	vmac_stats;	/* VMAC Statistics */
196 
197 	hxge_rx_ring_stats_t	rdc_stats[HXGE_MAX_RDCS]; /* per rdc stats */
198 	hxge_rdc_sys_stats_t	rdc_sys_stats;	/* RDC system stats */
199 
200 	hxge_tx_ring_stats_t	tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */
201 	hxge_tdc_sys_stats_t	tdc_sys_stats;	/* TDC system stats */
202 
203 	hxge_pfc_stats_t	pfc_stats;	/* pfc stats */
204 	hxge_port_stats_t	port_stats;	/* port stats */
205 	hxge_mmac_stats_t	mmac_stats;	/* Multi mac. stats */
206 
207 	hxge_peu_sys_stats_t	peu_sys_stats;	/* PEU system stats */
208 } hxge_stats_t, *p_hxge_stats_t;
209 
210 typedef struct _hxge_intr_t {
211 	boolean_t		intr_registered; /* interrupts are registered */
212 	boolean_t		intr_enabled; 	/* interrupts are enabled */
213 	boolean_t		niu_msi_enable;	/* debug or configurable? */
214 	uint8_t			nldevs;		/* # of logical devices */
215 	int			intr_types;	/* interrupt types supported */
216 	int			intr_type;	/* interrupt type to add */
217 	int			msi_intx_cnt;	/* # msi/intx ints returned */
218 	int			intr_added;	/* # ints actually needed */
219 	int			intr_cap;	/* interrupt capabilities */
220 	size_t			intr_size;	/* size of array to allocate */
221 	ddi_intr_handle_t 	*htable;	/* For array of interrupts */
222 	/* Add interrupt number for each interrupt vector */
223 	int			pri;
224 } hxge_intr_t, *p_hxge_intr_t;
225 
226 typedef struct _hxge_ldgv_t {
227 	uint8_t			ndma_ldvs;
228 	uint8_t			nldvs;
229 	uint8_t			start_ldg;
230 	uint8_t			maxldgs;
231 	uint8_t			maxldvs;
232 	uint8_t			ldg_intrs;
233 	uint32_t		tmres;
234 	p_hxge_ldg_t		ldgp;
235 	p_hxge_ldv_t		ldvp;
236 	p_hxge_ldv_t		ldvp_syserr;
237 } hxge_ldgv_t, *p_hxge_ldgv_t;
238 
239 typedef struct _hxge_timeout {
240 	timeout_id_t	id;
241 	clock_t		ticks;
242 	kmutex_t	lock;
243 	uint32_t	link_status;
244 	boolean_t	report_link_status;
245 } hxge_timeout;
246 
247 /*
248  * Hydra Device instance state information.
249  * Each instance is dynamically allocated on first attach.
250  */
251 struct _hxge_t {
252 	dev_info_t		*dip;		/* device instance */
253 	dev_info_t		*p_dip;		/* Parent's device instance */
254 	int			instance;	/* instance number */
255 	uint32_t		drv_state;	/* driver state bit flags */
256 	uint64_t		hxge_debug_level; /* driver state bit flags */
257 	kmutex_t		genlock[1];
258 	enum hxge_mac_state	hxge_mac_state;
259 	ddi_softintr_t		resched_id;	/* reschedule callback */
260 	boolean_t		resched_needed;
261 	boolean_t		resched_running;
262 
263 	p_dev_regs_t		dev_regs;
264 	hpi_handle_t		hpi_handle;
265 	hpi_handle_t		hpi_pci_handle;
266 	hpi_handle_t		hpi_reg_handle;
267 	hpi_handle_t		hpi_msi_handle;
268 
269 	hxge_vmac_t		vmac;
270 	hxge_classify_t		classifier;
271 
272 	mac_handle_t		mach;		/* mac module handle */
273 
274 	p_hxge_stats_t		statsp;
275 	uint32_t		param_count;
276 	p_hxge_param_t		param_arr;
277 	hxge_hw_list_t		*hxge_hw_p; 	/* pointer to per Hydra */
278 	uint8_t			nrdc;
279 	uint8_t			rdc[HXGE_MAX_RDCS];
280 	uint8_t			ntdc;
281 	uint8_t			tdc[HXGE_MAX_TDCS];
282 
283 	hxge_intr_t		hxge_intr_type;
284 	hxge_dma_pt_cfg_t 	pt_config;
285 	hxge_class_pt_cfg_t 	class_config;
286 
287 	/* Logical device and group data structures. */
288 	p_hxge_ldgv_t		ldgvp;
289 
290 	caddr_t			param_list;	/* Parameter list */
291 
292 	ether_addr_st		factaddr;	/* factory mac address	    */
293 	ether_addr_st		ouraddr;	/* individual address	    */
294 	kmutex_t		ouraddr_lock;	/* lock to protect to uradd */
295 
296 	ddi_iblock_cookie_t	interrupt_cookie;
297 
298 	/*
299 	 * Blocks of memory may be pre-allocated by the
300 	 * partition manager or the driver. They may include
301 	 * blocks for configuration and buffers. The idea is
302 	 * to preallocate big blocks of contiguous areas in
303 	 * system memory (i.e. with IOMMU). These blocks then
304 	 * will be broken up to a fixed number of blocks with
305 	 * each block having the same block size (4K, 8K, 16K or
306 	 * 32K) in the case of buffer blocks. For systems that
307 	 * do not support DVMA, more than one big block will be
308 	 * allocated.
309 	 */
310 	uint32_t		rx_default_block_size;
311 	hxge_rx_block_size_t	rx_bksize_code;
312 
313 	p_hxge_dma_pool_t	rx_buf_pool_p;
314 	p_hxge_dma_pool_t	rx_rbr_cntl_pool_p;
315 	p_hxge_dma_pool_t	rx_rcr_cntl_pool_p;
316 	p_hxge_dma_pool_t	rx_mbox_cntl_pool_p;
317 
318 	p_hxge_dma_pool_t	tx_buf_pool_p;
319 	p_hxge_dma_pool_t	tx_cntl_pool_p;
320 
321 	/* Receive buffer block ring and completion ring. */
322 	p_rx_rbr_rings_t 	rx_rbr_rings;
323 	p_rx_rcr_rings_t 	rx_rcr_rings;
324 	p_rx_mbox_areas_t 	rx_mbox_areas_p;
325 
326 	uint32_t		start_rdc;
327 	uint32_t		max_rdcs;
328 
329 	/* Transmit descriptors rings */
330 	p_tx_rings_t 		tx_rings;
331 	p_tx_mbox_areas_t	tx_mbox_areas_p;
332 
333 	uint32_t		start_tdc;
334 	uint32_t		max_tdcs;
335 	uint32_t		tdc_mask;
336 
337 	ddi_dma_handle_t 	dmasparehandle;
338 
339 	ulong_t 		sys_page_sz;
340 	ulong_t 		sys_page_mask;
341 	int 			suspended;
342 
343 	filter_t 		filter;		/* Current instance filter */
344 	p_hash_filter_t 	hash_filter;	/* Multicast hash filter. */
345 	krwlock_t		filter_lock;	/* Lock to protect filters. */
346 
347 	ulong_t 		sys_burst_sz;
348 	timeout_id_t 		hxge_timerid;
349 	uint8_t 		msg_min;
350 
351 	uint16_t		intr_timeout;
352 	uint16_t		intr_threshold;
353 
354 	rtrace_t		rtrace;
355 	int			fm_capabilities; /* FMA capabilities */
356 
357 	uint32_t 		hxge_port_rbr_size;
358 	uint32_t 		hxge_port_rcr_size;
359 	uint32_t 		hxge_port_tx_ring_size;
360 	hxge_mmac_t		hxge_mmac_info;
361 
362 	kmutex_t		pio_lock;
363 	hxge_timeout		timeout;
364 };
365 
366 /*
367  * Driver state flags.
368  */
369 #define	STATE_REGS_MAPPED	0x000000001	/* device registers mapped */
370 #define	STATE_KSTATS_SETUP	0x000000002	/* kstats allocated	*/
371 #define	STATE_NODE_CREATED	0x000000004	/* device node created	*/
372 #define	STATE_HW_CONFIG_CREATED	0x000000008	/* hardware properties	*/
373 #define	STATE_HW_INITIALIZED	0x000000010	/* hardware initialized	*/
374 
375 typedef struct _hxge_port_kstat_t {
376 	/*
377 	 * Transciever state informations.
378 	 */
379 	kstat_named_t	cap_autoneg;
380 	kstat_named_t	cap_10gfdx;
381 
382 	/*
383 	 * Link partner capabilities.
384 	 */
385 	kstat_named_t	lp_cap_autoneg;
386 	kstat_named_t	lp_cap_10gfdx;
387 
388 	/*
389 	 * Shared link setup.
390 	 */
391 	kstat_named_t	link_speed;
392 	kstat_named_t	link_duplex;
393 	kstat_named_t	link_up;
394 
395 	/*
396 	 * Lets the user know the MTU currently in use by
397 	 * the physical MAC port.
398 	 */
399 	kstat_named_t	lb_mode;
400 
401 	kstat_named_t	tx_max_pend;
402 	kstat_named_t	rx_jumbo_pkts;
403 
404 	/*
405 	 * Misc MAC statistics.
406 	 */
407 	kstat_named_t	ifspeed;
408 	kstat_named_t	promisc;
409 } hxge_port_kstat_t, *p_hxge_port_kstat_t;
410 
411 typedef struct _hxge_rdc_kstat {
412 	/*
413 	 * Receive DMA channel statistics.
414 	 * This structure needs to be consistent with hxge_rdc_stat_index_t
415 	 * in hxge_kstat.c
416 	 */
417 	kstat_named_t	ipackets;
418 	kstat_named_t	rbytes;
419 	kstat_named_t	errors;
420 	kstat_named_t	jumbo_pkts;
421 
422 	kstat_named_t	rcr_unknown_err;
423 	kstat_named_t	rcr_sha_par_err;
424 	kstat_named_t	rbr_pre_par_err;
425 	kstat_named_t	rbr_pre_emty;
426 
427 	kstat_named_t	rcr_shadow_full;
428 	kstat_named_t	rbr_tmout;
429 	kstat_named_t	peu_resp_err;
430 
431 	kstat_named_t	ctrl_fifo_ecc_err;
432 	kstat_named_t	data_fifo_ecc_err;
433 
434 	kstat_named_t	rcrfull;
435 	kstat_named_t	rbr_empty;
436 	kstat_named_t	rbr_empty_fail;
437 	kstat_named_t	rbrfull;
438 	kstat_named_t	rcr_invalids;	/* Account for invalid RCR entries. */
439 
440 	kstat_named_t	rcr_to;
441 	kstat_named_t	rcr_thresh;
442 	kstat_named_t	pkt_drop;
443 } hxge_rdc_kstat_t, *p_hxge_rdc_kstat_t;
444 
445 typedef struct _hxge_rdc_sys_kstat {
446 	/*
447 	 * Receive DMA system statistics.
448 	 * This structure needs to be consistent with hxge_rdc_sys_stat_idx_t
449 	 * in hxge_kstat.c
450 	 */
451 	kstat_named_t	ctrl_fifo_sec;
452 	kstat_named_t	ctrl_fifo_ded;
453 	kstat_named_t	data_fifo_sec;
454 	kstat_named_t	data_fifo_ded;
455 } hxge_rdc_sys_kstat_t, *p_hxge_rdc_sys_kstat_t;
456 
457 typedef	struct _hxge_tdc_kstat {
458 	/*
459 	 * Transmit DMA channel statistics.
460 	 * This structure needs to be consistent with hxge_tdc_stats_index_t
461 	 * in hxge_kstat.c
462 	 */
463 	kstat_named_t	opackets;
464 	kstat_named_t	obytes;
465 	kstat_named_t	obytes_with_pad;
466 	kstat_named_t	oerrors;
467 	kstat_named_t	tx_inits;
468 	kstat_named_t	tx_no_buf;
469 
470 	kstat_named_t	peu_resp_err;
471 	kstat_named_t	pkt_size_err;
472 	kstat_named_t	tx_rng_oflow;
473 	kstat_named_t	pkt_size_hdr_err;
474 	kstat_named_t	runt_pkt_drop_err;
475 	kstat_named_t	pref_par_err;
476 	kstat_named_t	tdr_pref_cpl_to;
477 	kstat_named_t	pkt_cpl_to;
478 	kstat_named_t	invalid_sop;
479 	kstat_named_t	unexpected_sop;
480 
481 	kstat_named_t	count_hdr_size_err;
482 	kstat_named_t	count_runt;
483 	kstat_named_t	count_abort;
484 
485 	kstat_named_t	tx_starts;
486 	kstat_named_t	tx_no_desc;
487 	kstat_named_t	tx_dma_bind_fail;
488 	kstat_named_t	tx_hdr_pkts;
489 	kstat_named_t	tx_ddi_pkts;
490 	kstat_named_t	tx_jumbo_pkts;
491 	kstat_named_t	tx_max_pend;
492 	kstat_named_t	tx_marks;
493 } hxge_tdc_kstat_t, *p_hxge_tdc_kstat_t;
494 
495 typedef struct _hxge_tdc_sys_kstat {
496 	/*
497 	 * Transmit DMA system statistics.
498 	 * This structure needs to be consistent with hxge_tdc_sys_stat_idx_t
499 	 * in hxge_kstat.c
500 	 */
501 	kstat_named_t	reord_tbl_par_err;
502 	kstat_named_t	reord_buf_ded_err;
503 	kstat_named_t	reord_buf_sec_err;
504 } hxge_tdc_sys_kstat_t, *p_hxge_tdc_sys_kstat_t;
505 
506 typedef	struct _hxge_vmac_kstat {
507 	/*
508 	 * VMAC statistics.
509 	 * This structure needs to be consistent with hxge_vmac_stat_index_t
510 	 * in hxge_kstat.c
511 	 */
512 	kstat_named_t	tx_frame_cnt;
513 	kstat_named_t	tx_byte_cnt;
514 
515 	kstat_named_t	rx_frame_cnt;
516 	kstat_named_t	rx_byte_cnt;
517 	kstat_named_t	rx_drop_frame_cnt;
518 	kstat_named_t	rx_drop_byte_cnt;
519 	kstat_named_t	rx_crc_cnt;
520 	kstat_named_t	rx_pause_cnt;
521 	kstat_named_t	rx_bcast_fr_cnt;
522 	kstat_named_t	rx_mcast_fr_cnt;
523 } hxge_vmac_kstat_t, *p_hxge_vmac_kstat_t;
524 
525 typedef struct _hxge_pfc_kstat {
526 	/*
527 	 * This structure needs to be consistent with hxge_pfc_stat_index_t
528 	 * in hxge_kstat.c
529 	 */
530 	kstat_named_t	pfc_pkt_drop;
531 	kstat_named_t	pfc_tcam_parity_err;
532 	kstat_named_t	pfc_vlan_parity_err;
533 	kstat_named_t	pfc_bad_cs_count;
534 	kstat_named_t	pfc_drop_count;
535 	kstat_named_t	pfc_tcp_ctrl_drop;
536 	kstat_named_t	pfc_l2_addr_drop;
537 	kstat_named_t	pfc_class_code_drop;
538 	kstat_named_t	pfc_tcam_drop;
539 	kstat_named_t	pfc_vlan_drop;
540 } hxge_pfc_kstat_t, *p_hxge_pfc_kstat_t;
541 
542 typedef struct _hxge_mmac_kstat {
543 	/*
544 	 * This structure needs to be consistent with hxge_mmac_stat_index_t
545 	 * in hxge_kstat.c
546 	 */
547 	kstat_named_t	mmac_max_addr_cnt;
548 	kstat_named_t	mmac_avail_addr_cnt;
549 	kstat_named_t	mmac_addr1;
550 	kstat_named_t	mmac_addr2;
551 	kstat_named_t	mmac_addr3;
552 	kstat_named_t	mmac_addr4;
553 	kstat_named_t	mmac_addr5;
554 	kstat_named_t	mmac_addr6;
555 	kstat_named_t	mmac_addr7;
556 	kstat_named_t	mmac_addr8;
557 	kstat_named_t	mmac_addr9;
558 	kstat_named_t	mmac_addr10;
559 	kstat_named_t	mmac_addr11;
560 	kstat_named_t	mmac_addr12;
561 	kstat_named_t	mmac_addr13;
562 	kstat_named_t	mmac_addr14;
563 	kstat_named_t	mmac_addr15;
564 	kstat_named_t	mmac_addr16;
565 } hxge_mmac_kstat_t, *p_hxge_mmac_kstat_t;
566 
567 typedef struct _hxge_peu_sys_kstat {
568 	/*
569 	 * This structure needs to be consistent with hxge_peu_sys_stat_idx_t
570 	 * in hxge_kstat.c
571 	 */
572 	kstat_named_t	spc_acc_err;
573 	kstat_named_t	tdc_pioacc_err;
574 	kstat_named_t	rdc_pioacc_err;
575 	kstat_named_t	pfc_pioacc_err;
576 	kstat_named_t	vmac_pioacc_err;
577 	kstat_named_t	cpl_hdrq_parerr;
578 	kstat_named_t	cpl_dataq_parerr;
579 	kstat_named_t	retryram_xdlh_parerr;
580 	kstat_named_t	retrysotram_xdlh_parerr;
581 	kstat_named_t	p_hdrq_parerr;
582 	kstat_named_t	p_dataq_parerr;
583 	kstat_named_t	np_hdrq_parerr;
584 	kstat_named_t	np_dataq_parerr;
585 	kstat_named_t	eic_msix_parerr;
586 	kstat_named_t	hcr_parerr;
587 } hxge_peu_sys_kstat_t, *p_hxge_peu_sys_kstat_t;
588 
589 /*
590  * Prototype definitions.
591  */
592 hxge_status_t hxge_init(p_hxge_t);
593 void hxge_uninit(p_hxge_t);
594 void hxge_get64(p_hxge_t hxgep, p_mblk_t mp);
595 void hxge_put64(p_hxge_t hxgep, p_mblk_t mp);
596 
597 typedef	void	(*fptrv_t)();
598 timeout_id_t hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec);
599 void hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid);
600 
601 #ifdef	__cplusplus
602 }
603 #endif
604 
605 #endif	/* _SYS_HXGE_HXGE_H */
606