1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /* Copyright 2010 QLogic Corporation */
23 
24 /*
25  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
26  * Use is subject to license terms.
27  */
28 
29 #pragma ident	"Copyright 2010 QLogic Corporation; ql_init.c"
30 
31 /*
32  * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver source file.
33  *
34  * ***********************************************************************
35  * *									**
36  * *				NOTICE					**
37  * *		COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION		**
38  * *			ALL RIGHTS RESERVED				**
39  * *									**
40  * ***********************************************************************
41  *
42  */
43 
44 #include <ql_apps.h>
45 #include <ql_api.h>
46 #include <ql_debug.h>
47 #include <ql_init.h>
48 #include <ql_iocb.h>
49 #include <ql_isr.h>
50 #include <ql_mbx.h>
51 #include <ql_nx.h>
52 #include <ql_xioctl.h>
53 
54 /*
55  * Local data
56  */
57 
58 /*
59  * Local prototypes
60  */
61 static uint16_t ql_nvram_request(ql_adapter_state_t *, uint32_t);
62 static int ql_nvram_24xx_config(ql_adapter_state_t *);
63 static void ql_23_properties(ql_adapter_state_t *, nvram_t *);
64 static void ql_24xx_properties(ql_adapter_state_t *, nvram_24xx_t *);
65 static int ql_check_isp_firmware(ql_adapter_state_t *);
66 static int ql_chip_diag(ql_adapter_state_t *);
67 static int ql_load_flash_fw(ql_adapter_state_t *);
68 static int ql_configure_loop(ql_adapter_state_t *);
69 static int ql_configure_hba(ql_adapter_state_t *);
70 static int ql_configure_fabric(ql_adapter_state_t *);
71 static int ql_configure_device_d_id(ql_adapter_state_t *);
72 static void ql_set_max_read_req(ql_adapter_state_t *);
73 static void ql_configure_n_port_info(ql_adapter_state_t *);
74 static void ql_clear_mcp(ql_adapter_state_t *);
75 static void ql_mps_reset(ql_adapter_state_t *);
76 
77 /*
78  * ql_initialize_adapter
79  *	Initialize board.
80  *
81  * Input:
82  *	ha = adapter state pointer.
83  *
84  * Returns:
85  *	ql local function return status code.
86  *
87  * Context:
88  *	Kernel context.
89  */
90 int
91 ql_initialize_adapter(ql_adapter_state_t *ha)
92 {
93 	int			rval;
94 	class_svc_param_t	*class3_param;
95 	caddr_t			msg;
96 	la_els_logi_t		*els = &ha->loginparams;
97 	int			retries = 5;
98 
99 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
100 
101 	do {
102 		/* Clear adapter flags. */
103 		TASK_DAEMON_LOCK(ha);
104 		ha->task_daemon_flags &= TASK_DAEMON_STOP_FLG |
105 		    TASK_DAEMON_SLEEPING_FLG | TASK_DAEMON_ALIVE_FLG |
106 		    TASK_DAEMON_IDLE_CHK_FLG;
107 		ha->task_daemon_flags |= LOOP_DOWN;
108 		TASK_DAEMON_UNLOCK(ha);
109 
110 		ha->loop_down_timer = LOOP_DOWN_TIMER_OFF;
111 		ADAPTER_STATE_LOCK(ha);
112 		ha->flags |= ABORT_CMDS_LOOP_DOWN_TMO;
113 		ha->flags &= ~ONLINE;
114 		ADAPTER_STATE_UNLOCK(ha);
115 
116 		ha->state = FC_STATE_OFFLINE;
117 		msg = "Loop OFFLINE";
118 
119 		rval = ql_pci_sbus_config(ha);
120 		if (rval != QL_SUCCESS) {
121 			TASK_DAEMON_LOCK(ha);
122 			if (!(ha->task_daemon_flags & ABORT_ISP_ACTIVE)) {
123 				EL(ha, "ql_pci_sbus_cfg, isp_abort_needed\n");
124 				ha->task_daemon_flags |= ISP_ABORT_NEEDED;
125 			}
126 			TASK_DAEMON_UNLOCK(ha);
127 			continue;
128 		}
129 
130 		(void) ql_setup_fcache(ha);
131 
132 		/* Reset ISP chip. */
133 		ql_reset_chip(ha);
134 
135 		/* Get NVRAM configuration if needed. */
136 		if (ha->init_ctrl_blk.cb.version == 0) {
137 			(void) ql_nvram_config(ha);
138 		}
139 
140 		/* Set login parameters. */
141 		if (CFG_IST(ha, CFG_CTRL_24258081)) {
142 			els->common_service.rx_bufsize = CHAR_TO_SHORT(
143 			    ha->init_ctrl_blk.cb24.max_frame_length[0],
144 			    ha->init_ctrl_blk.cb24.max_frame_length[1]);
145 			bcopy((void *)&ha->init_ctrl_blk.cb24.port_name[0],
146 			    (void *)&els->nport_ww_name.raw_wwn[0], 8);
147 			bcopy((void *)&ha->init_ctrl_blk.cb24.node_name[0],
148 			    (void *)&els->node_ww_name.raw_wwn[0], 8);
149 		} else {
150 			els->common_service.rx_bufsize = CHAR_TO_SHORT(
151 			    ha->init_ctrl_blk.cb.max_frame_length[0],
152 			    ha->init_ctrl_blk.cb.max_frame_length[1]);
153 			bcopy((void *)&ha->init_ctrl_blk.cb.port_name[0],
154 			    (void *)&els->nport_ww_name.raw_wwn[0], 8);
155 			bcopy((void *)&ha->init_ctrl_blk.cb.node_name[0],
156 			    (void *)&els->node_ww_name.raw_wwn[0], 8);
157 		}
158 
159 		/* Determine which RISC code to use. */
160 		if ((rval = ql_check_isp_firmware(ha)) != QL_SUCCESS) {
161 			if ((rval = ql_chip_diag(ha)) == QL_SUCCESS) {
162 				rval = ql_load_isp_firmware(ha);
163 			}
164 		}
165 
166 		if (rval == QL_SUCCESS && (rval = ql_set_cache_line(ha)) ==
167 		    QL_SUCCESS && (rval = ql_init_rings(ha)) == QL_SUCCESS) {
168 
169 			(void) ql_fw_ready(ha, ha->fwwait);
170 
171 			if (!(ha->task_daemon_flags & QL_SUSPENDED) &&
172 			    ha->loop_down_timer == LOOP_DOWN_TIMER_OFF) {
173 				if (ha->topology & QL_LOOP_CONNECTION) {
174 					ha->state = ha->state | FC_STATE_LOOP;
175 					msg = "Loop ONLINE";
176 					ha->task_daemon_flags |= STATE_ONLINE;
177 				} else if (ha->topology & QL_P2P_CONNECTION) {
178 					ha->state = ha->state |
179 					    FC_STATE_ONLINE;
180 					msg = "Link ONLINE";
181 					ha->task_daemon_flags |= STATE_ONLINE;
182 				} else {
183 					msg = "Unknown Link state";
184 				}
185 			}
186 		} else {
187 			TASK_DAEMON_LOCK(ha);
188 			if (!(ha->task_daemon_flags & ABORT_ISP_ACTIVE)) {
189 				EL(ha, "failed, isp_abort_needed\n");
190 				ha->task_daemon_flags |= ISP_ABORT_NEEDED |
191 				    LOOP_DOWN;
192 			}
193 			TASK_DAEMON_UNLOCK(ha);
194 		}
195 
196 	} while (retries-- != 0 && ha->task_daemon_flags & ISP_ABORT_NEEDED);
197 
198 	cmn_err(CE_NOTE, "!Qlogic %s(%d): %s", QL_NAME, ha->instance, msg);
199 
200 	/* Enable ISP interrupts and login parameters. */
201 	if (CFG_IST(ha, CFG_CTRL_8021)) {
202 		ql_8021_enable_intrs(ha);
203 	} else if (CFG_IST(ha, CFG_CTRL_242581)) {
204 		WRT32_IO_REG(ha, ictrl, ISP_EN_RISC);
205 	} else {
206 		WRT16_IO_REG(ha, ictrl, ISP_EN_INT + ISP_EN_RISC);
207 	}
208 
209 	ADAPTER_STATE_LOCK(ha);
210 	ha->flags |= (INTERRUPTS_ENABLED | ONLINE);
211 	ADAPTER_STATE_UNLOCK(ha);
212 
213 	ha->task_daemon_flags &= ~(FC_STATE_CHANGE | RESET_MARKER_NEEDED |
214 	    COMMAND_WAIT_NEEDED);
215 
216 	/*
217 	 * Setup login parameters.
218 	 */
219 	els->common_service.fcph_version = 0x2006;
220 	els->common_service.btob_credit = 3;
221 	els->common_service.cmn_features = 0x8800;
222 	els->common_service.conc_sequences = 0xff;
223 	els->common_service.relative_offset = 3;
224 	els->common_service.e_d_tov = 0x07d0;
225 
226 	class3_param = (class_svc_param_t *)&els->class_3;
227 	class3_param->class_valid_svc_opt = 0x8800;
228 	class3_param->rcv_data_size = els->common_service.rx_bufsize;
229 	class3_param->conc_sequences = 0xff;
230 
231 	if (rval != QL_SUCCESS) {
232 		EL(ha, "failed, rval = %xh\n", rval);
233 	} else {
234 		/*EMPTY*/
235 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
236 	}
237 	return (rval);
238 }
239 
240 /*
241  * ql_pci_sbus_config
242  *	Setup device PCI/SBUS configuration registers.
243  *
244  * Input:
245  *	ha = adapter state pointer.
246  *
247  * Returns:
248  *	ql local function return status code.
249  *
250  * Context:
251  *	Kernel context.
252  */
253 int
254 ql_pci_sbus_config(ql_adapter_state_t *ha)
255 {
256 	uint32_t	timer;
257 	uint16_t	cmd, w16;
258 
259 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
260 
261 	if (CFG_IST(ha, CFG_SBUS_CARD)) {
262 		w16 = (uint16_t)ddi_get16(ha->sbus_fpga_dev_handle,
263 		    (uint16_t *)(ha->sbus_fpga_iobase + FPGA_REVISION));
264 		EL(ha, "FPGA rev is %d.%d", (w16 & 0xf0) >> 4,
265 		    w16 & 0xf);
266 	} else {
267 		/*
268 		 * we want to respect framework's setting of PCI
269 		 * configuration space command register and also
270 		 * want to make sure that all bits of interest to us
271 		 * are properly set in command register.
272 		 */
273 		cmd = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_COMM);
274 		cmd = (uint16_t)(cmd | PCI_COMM_IO | PCI_COMM_MAE |
275 		    PCI_COMM_ME | PCI_COMM_MEMWR_INVAL |
276 		    PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE);
277 
278 		/*
279 		 * If this is a 2300 card and not 2312, reset the
280 		 * MEMWR_INVAL due to a bug in the 2300. Unfortunately, the
281 		 * 2310 also reports itself as a 2300 so we need to get the
282 		 * fb revision level -- a 6 indicates it really is a 2300 and
283 		 * not a 2310.
284 		 */
285 
286 		if (ha->device_id == 0x2300) {
287 			/* Pause RISC. */
288 			WRT16_IO_REG(ha, hccr, HC_PAUSE_RISC);
289 			for (timer = 0; timer < 30000; timer++) {
290 				if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) !=
291 				    0) {
292 					break;
293 				} else {
294 					drv_usecwait(MILLISEC);
295 				}
296 			}
297 
298 			/* Select FPM registers. */
299 			WRT16_IO_REG(ha, ctrl_status, 0x20);
300 
301 			/* Get the fb rev level */
302 			if (RD16_IO_REG(ha, fb_cmd) == 6) {
303 				cmd = (uint16_t)(cmd & ~PCI_COMM_MEMWR_INVAL);
304 			}
305 
306 			/* Deselect FPM registers. */
307 			WRT16_IO_REG(ha, ctrl_status, 0x0);
308 
309 			/* Release RISC module. */
310 			WRT16_IO_REG(ha, hccr, HC_RELEASE_RISC);
311 			for (timer = 0; timer < 30000; timer++) {
312 				if ((RD16_IO_REG(ha, hccr) & HC_RISC_PAUSE) ==
313 				    0) {
314 					break;
315 				} else {
316 					drv_usecwait(MILLISEC);
317 				}
318 			}
319 		} else if (ha->device_id == 0x2312) {
320 			/*
321 			 * cPCI ISP2312 specific code to service function 1
322 			 * hot-swap registers.
323 			 */
324 			if ((RD16_IO_REG(ha, ctrl_status) & ISP_FUNC_NUM_MASK)
325 			    != 0) {
326 				ql_pci_config_put8(ha, 0x66, 0xc2);
327 			}
328 		}
329 
330 		if (!(CFG_IST(ha, CFG_CTRL_8021)) &&
331 		    ha->pci_max_read_req != 0) {
332 			ql_set_max_read_req(ha);
333 		}
334 
335 		ql_pci_config_put16(ha, PCI_CONF_COMM, cmd);
336 
337 		/* Set cache line register. */
338 		ql_pci_config_put8(ha, PCI_CONF_CACHE_LINESZ, 0x10);
339 
340 		/* Set latency register. */
341 		ql_pci_config_put8(ha, PCI_CONF_LATENCY_TIMER, 0x40);
342 
343 		/* Reset expansion ROM address decode enable. */
344 		w16 = (uint16_t)ql_pci_config_get16(ha, PCI_CONF_ROM);
345 		w16 = (uint16_t)(w16 & ~BIT_0);
346 		ql_pci_config_put16(ha, PCI_CONF_ROM, w16);
347 	}
348 
349 	QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
350 
351 	return (QL_SUCCESS);
352 }
353 
354 /*
355  * Set the PCI max read request value.
356  *
357  * Input:
358  *	ha:		adapter state pointer.
359  *
360  * Output:
361  *	none.
362  *
363  * Returns:
364  *
365  * Context:
366  *	Kernel context.
367  */
368 
369 static void
370 ql_set_max_read_req(ql_adapter_state_t *ha)
371 {
372 	uint16_t	read_req, w16;
373 	uint16_t	tmp = ha->pci_max_read_req;
374 
375 	if ((ha->device_id == 0x2422) ||
376 	    ((ha->device_id & 0xff00) == 0x2300)) {
377 		/* check for vaild override value */
378 		if (tmp == 512 || tmp == 1024 || tmp == 2048 ||
379 		    tmp == 4096) {
380 			/* shift away the don't cares */
381 			tmp = (uint16_t)(tmp >> 10);
382 			/* convert bit pos to request value */
383 			for (read_req = 0; tmp != 0; read_req++) {
384 				tmp = (uint16_t)(tmp >> 1);
385 			}
386 			w16 = (uint16_t)ql_pci_config_get16(ha, 0x4e);
387 			w16 = (uint16_t)(w16 & ~(BIT_3 & BIT_2));
388 			w16 = (uint16_t)(w16 | (read_req << 2));
389 			ql_pci_config_put16(ha, 0x4e, w16);
390 		} else {
391 			EL(ha, "invalid parameter value for "
392 			    "'pci-max-read-request': %d; using system "
393 			    "default\n", tmp);
394 		}
395 	} else if ((ha->device_id == 0x2432) || ((ha->device_id & 0xff00) ==
396 	    0x2500) || (ha->device_id == 0x8432)) {
397 		/* check for vaild override value */
398 		if (tmp == 128 || tmp == 256 || tmp == 512 ||
399 		    tmp == 1024 || tmp == 2048 || tmp == 4096) {
400 			/* shift away the don't cares */
401 			tmp = (uint16_t)(tmp >> 8);
402 			/* convert bit pos to request value */
403 			for (read_req = 0; tmp != 0; read_req++) {
404 				tmp = (uint16_t)(tmp >> 1);
405 			}
406 			w16 = (uint16_t)ql_pci_config_get16(ha, 0x54);
407 			w16 = (uint16_t)(w16 & ~(BIT_14 | BIT_13 |
408 			    BIT_12));
409 			w16 = (uint16_t)(w16 | (read_req << 12));
410 			ql_pci_config_put16(ha, 0x54, w16);
411 		} else {
412 			EL(ha, "invalid parameter value for "
413 			    "'pci-max-read-request': %d; using system "
414 			    "default\n", tmp);
415 		}
416 	}
417 }
418 
419 /*
420  * NVRAM configuration.
421  *
422  * Input:
423  *	ha:		adapter state pointer.
424  *	ha->hba_buf = request and response rings
425  *
426  * Output:
427  *	ha->init_ctrl_blk = initialization control block
428  *	host adapters parameters in host adapter block
429  *
430  * Returns:
431  *	ql local function return status code.
432  *
433  * Context:
434  *	Kernel context.
435  */
436 int
437 ql_nvram_config(ql_adapter_state_t *ha)
438 {
439 	uint32_t	cnt;
440 	caddr_t		dptr1, dptr2;
441 	ql_init_cb_t	*icb = &ha->init_ctrl_blk.cb;
442 	ql_ip_init_cb_t	*ip_icb = &ha->ip_init_ctrl_blk.cb;
443 	nvram_t		*nv = (nvram_t *)ha->request_ring_bp;
444 	uint16_t	*wptr = (uint16_t *)ha->request_ring_bp;
445 	uint8_t		chksum = 0;
446 	int		rval;
447 	int		idpromlen;
448 	char		idprombuf[32];
449 	uint32_t	start_addr;
450 
451 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
452 
453 	if (CFG_IST(ha, CFG_CTRL_24258081)) {
454 		return (ql_nvram_24xx_config(ha));
455 	}
456 
457 	start_addr = 0;
458 	if ((rval = ql_lock_nvram(ha, &start_addr, LNF_NVRAM_DATA)) ==
459 	    QL_SUCCESS) {
460 		/* Verify valid NVRAM checksum. */
461 		for (cnt = 0; cnt < sizeof (nvram_t)/2; cnt++) {
462 			*wptr = (uint16_t)ql_get_nvram_word(ha,
463 			    (uint32_t)(cnt + start_addr));
464 			chksum = (uint8_t)(chksum + (uint8_t)*wptr);
465 			chksum = (uint8_t)(chksum + (uint8_t)(*wptr >> 8));
466 			wptr++;
467 		}
468 		ql_release_nvram(ha);
469 	}
470 
471 	/* Bad NVRAM data, set defaults parameters. */
472 	if (rval != QL_SUCCESS || chksum || nv->id[0] != 'I' ||
473 	    nv->id[1] != 'S' || nv->id[2] != 'P' || nv->id[3] != ' ' ||
474 	    nv->nvram_version < 1) {
475 
476 		EL(ha, "failed, rval=%xh, checksum=%xh, "
477 		    "id=%02x%02x%02x%02xh, flsz=%xh, pciconfvid=%xh, "
478 		    "nvram_version=%x\n", rval, chksum, nv->id[0], nv->id[1],
479 		    nv->id[2], nv->id[3], ha->xioctl->fdesc.flash_size,
480 		    ha->subven_id, nv->nvram_version);
481 
482 		/* Don't print nvram message if it's an on-board 2200 */
483 		if (!((CFG_IST(ha, CFG_CTRL_2200)) &&
484 		    (ha->xioctl->fdesc.flash_size == 0))) {
485 			cmn_err(CE_WARN, "%s(%d): NVRAM configuration failed,"
486 			    " using driver defaults.", QL_NAME, ha->instance);
487 		}
488 
489 		/* Reset NVRAM data. */
490 		bzero((void *)nv, sizeof (nvram_t));
491 
492 		/*
493 		 * Set default initialization control block.
494 		 */
495 		nv->parameter_block_version = ICB_VERSION;
496 		nv->firmware_options[0] = BIT_4 | BIT_3 | BIT_2 | BIT_1;
497 		nv->firmware_options[1] = BIT_7 | BIT_5 | BIT_2;
498 
499 		nv->max_frame_length[1] = 4;
500 
501 		/*
502 		 * Allow 2048 byte frames for 2300
503 		 */
504 		if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
505 			nv->max_frame_length[1] = 8;
506 		}
507 		nv->max_iocb_allocation[1] = 1;
508 		nv->execution_throttle[0] = 16;
509 		nv->login_retry_count = 8;
510 
511 		idpromlen = 32;
512 
513 		/*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
514 		if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ha->dip,
515 		    DDI_PROP_CANSLEEP, "idprom", (caddr_t)idprombuf,
516 		    &idpromlen) != DDI_PROP_SUCCESS) {
517 
518 			QL_PRINT_3(CE_CONT, "(%d): Unable to read idprom "
519 			    "property\n", ha->instance);
520 			cmn_err(CE_WARN, "%s(%d) : Unable to read idprom "
521 			    "property", QL_NAME, ha->instance);
522 
523 			nv->port_name[2] = 33;
524 			nv->port_name[3] = 224;
525 			nv->port_name[4] = 139;
526 			nv->port_name[7] = (uint8_t)
527 			    (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
528 		} else {
529 
530 			nv->port_name[2] = idprombuf[2];
531 			nv->port_name[3] = idprombuf[3];
532 			nv->port_name[4] = idprombuf[4];
533 			nv->port_name[5] = idprombuf[5];
534 			nv->port_name[6] = idprombuf[6];
535 			nv->port_name[7] = idprombuf[7];
536 			nv->port_name[0] = (uint8_t)
537 			    (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
538 		}
539 
540 		/* Don't print nvram message if it's an on-board 2200 */
541 		if (!(CFG_IST(ha, CFG_CTRL_2200)) &&
542 		    (ha->xioctl->fdesc.flash_size == 0)) {
543 			cmn_err(CE_WARN, "%s(%d): Unreliable HBA NVRAM, using"
544 			    " default HBA parameters and temporary WWPN:"
545 			    " %02x%02x%02x%02x%02x%02x%02x%02x", QL_NAME,
546 			    ha->instance, nv->port_name[0], nv->port_name[1],
547 			    nv->port_name[2], nv->port_name[3],
548 			    nv->port_name[4], nv->port_name[5],
549 			    nv->port_name[6], nv->port_name[7]);
550 		}
551 
552 		nv->login_timeout = 4;
553 
554 		/* Set default connection options for the 23xx to 2 */
555 		if (!(CFG_IST(ha, CFG_CTRL_2200))) {
556 			nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] |
557 			    BIT_5);
558 		}
559 
560 		/*
561 		 * Set default host adapter parameters
562 		 */
563 		nv->host_p[0] = BIT_1;
564 		nv->host_p[1] = BIT_2;
565 		nv->reset_delay = 5;
566 		nv->port_down_retry_count = 8;
567 		nv->maximum_luns_per_target[0] = 8;
568 
569 		rval = QL_FUNCTION_FAILED;
570 	}
571 
572 	/* Check for adapter node name (big endian). */
573 	for (cnt = 0; cnt < 8; cnt++) {
574 		if (nv->node_name[cnt] != 0) {
575 			break;
576 		}
577 	}
578 
579 	/* Copy port name if no node name (big endian). */
580 	if (cnt == 8) {
581 		bcopy((void *)&nv->port_name[0], (void *)&nv->node_name[0], 8);
582 		nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0);
583 		nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0);
584 	}
585 
586 	/* Reset initialization control blocks. */
587 	bzero((void *)icb, sizeof (ql_init_cb_t));
588 
589 	/* Get driver properties. */
590 	ql_23_properties(ha, nv);
591 
592 	cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
593 	    "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
594 	    QL_NAME, ha->instance, nv->port_name[0], nv->port_name[1],
595 	    nv->port_name[2], nv->port_name[3], nv->port_name[4],
596 	    nv->port_name[5], nv->port_name[6], nv->port_name[7],
597 	    nv->node_name[0], nv->node_name[1], nv->node_name[2],
598 	    nv->node_name[3], nv->node_name[4], nv->node_name[5],
599 	    nv->node_name[6], nv->node_name[7]);
600 
601 	/*
602 	 * Copy over NVRAM RISC parameter block
603 	 * to initialization control block.
604 	 */
605 	dptr1 = (caddr_t)icb;
606 	dptr2 = (caddr_t)&nv->parameter_block_version;
607 	cnt = (uint32_t)((uintptr_t)&icb->request_q_outpointer[0] -
608 	    (uintptr_t)&icb->version);
609 	while (cnt-- != 0) {
610 		*dptr1++ = *dptr2++;
611 	}
612 
613 	/* Copy 2nd half. */
614 	dptr1 = (caddr_t)&icb->add_fw_opt[0];
615 	cnt = (uint32_t)((uintptr_t)&icb->reserved_3[0] -
616 	    (uintptr_t)&icb->add_fw_opt[0]);
617 
618 	while (cnt-- != 0) {
619 		*dptr1++ = *dptr2++;
620 	}
621 
622 	/*
623 	 * Setup driver firmware options.
624 	 */
625 	icb->firmware_options[0] = (uint8_t)
626 	    (icb->firmware_options[0] | BIT_6 | BIT_1);
627 
628 	/*
629 	 * There is no use enabling fast post for SBUS or 2300
630 	 * Always enable 64bit addressing, except SBUS cards.
631 	 */
632 	ha->cfg_flags |= CFG_ENABLE_64BIT_ADDRESSING;
633 	if (CFG_IST(ha, (CFG_SBUS_CARD | CFG_CTRL_2300 | CFG_CTRL_6322))) {
634 		icb->firmware_options[0] = (uint8_t)
635 		    (icb->firmware_options[0] & ~BIT_3);
636 		if (CFG_IST(ha, CFG_SBUS_CARD)) {
637 			icb->special_options[0] = (uint8_t)
638 			    (icb->special_options[0] | BIT_5);
639 			ha->cfg_flags &= ~CFG_ENABLE_64BIT_ADDRESSING;
640 		}
641 	} else {
642 		icb->firmware_options[0] = (uint8_t)
643 		    (icb->firmware_options[0] | BIT_3);
644 	}
645 	/* RIO and ZIO not supported. */
646 	icb->add_fw_opt[0] = (uint8_t)(icb->add_fw_opt[0] &
647 	    ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
648 
649 	icb->firmware_options[1] = (uint8_t)(icb->firmware_options[1] |
650 	    BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0);
651 	icb->firmware_options[0] = (uint8_t)
652 	    (icb->firmware_options[0] & ~(BIT_5 | BIT_4));
653 	icb->firmware_options[1] = (uint8_t)
654 	    (icb->firmware_options[1] & ~BIT_4);
655 
656 	icb->add_fw_opt[1] = (uint8_t)(icb->add_fw_opt[1] & ~(BIT_5 | BIT_4));
657 	icb->special_options[0] = (uint8_t)(icb->special_options[0] | BIT_1);
658 
659 	if (CFG_IST(ha, (CFG_CTRL_2300 | CFG_CTRL_6322))) {
660 		if ((icb->special_options[1] & 0x20) == 0) {
661 			EL(ha, "50 ohm is not set\n");
662 		}
663 	}
664 	icb->execution_throttle[0] = 0xff;
665 	icb->execution_throttle[1] = 0xff;
666 
667 	if (CFG_IST(ha, CFG_ENABLE_FCP_2_SUPPORT)) {
668 		icb->firmware_options[1] = (uint8_t)
669 		    (icb->firmware_options[1] | BIT_7 | BIT_6);
670 		icb->add_fw_opt[1] = (uint8_t)
671 		    (icb->add_fw_opt[1] | BIT_5 | BIT_4);
672 	}
673 
674 	/*
675 	 * Set host adapter parameters
676 	 */
677 	ADAPTER_STATE_LOCK(ha);
678 	ha->nvram_version = nv->nvram_version;
679 	ha->adapter_features = CHAR_TO_SHORT(nv->adapter_features[0],
680 	    nv->adapter_features[1]);
681 
682 	nv->host_p[0] & BIT_4 ? (ha->cfg_flags |= CFG_DISABLE_RISC_CODE_LOAD) :
683 	    (ha->cfg_flags &= ~CFG_DISABLE_RISC_CODE_LOAD);
684 	nv->host_p[0] & BIT_5 ? (ha->cfg_flags |= CFG_SET_CACHE_LINE_SIZE_1) :
685 	    (ha->cfg_flags &= ~CFG_SET_CACHE_LINE_SIZE_1);
686 
687 	nv->host_p[1] & BIT_1 ? (ha->cfg_flags |= CFG_ENABLE_LIP_RESET) :
688 	    (ha->cfg_flags &= ~CFG_ENABLE_LIP_RESET);
689 	nv->host_p[1] & BIT_2 ? (ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN) :
690 	    (ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN);
691 	nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) :
692 	    (ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET);
693 
694 	nv->adapter_features[0] & BIT_3 ?
695 	    (ha->cfg_flags |= CFG_MULTI_CHIP_ADAPTER) :
696 	    (ha->cfg_flags &= ~CFG_MULTI_CHIP_ADAPTER);
697 
698 	ADAPTER_STATE_UNLOCK(ha);
699 
700 	ha->execution_throttle = CHAR_TO_SHORT(nv->execution_throttle[0],
701 	    nv->execution_throttle[1]);
702 	ha->loop_reset_delay = nv->reset_delay;
703 	ha->port_down_retry_count = nv->port_down_retry_count;
704 	ha->r_a_tov = (uint16_t)(icb->login_timeout < R_A_TOV_DEFAULT ?
705 	    R_A_TOV_DEFAULT : icb->login_timeout);
706 	ha->maximum_luns_per_target = CHAR_TO_SHORT(
707 	    nv->maximum_luns_per_target[0], nv->maximum_luns_per_target[1]);
708 	if (ha->maximum_luns_per_target == 0) {
709 		ha->maximum_luns_per_target++;
710 	}
711 
712 	/*
713 	 * Setup ring parameters in initialization control block
714 	 */
715 	cnt = REQUEST_ENTRY_CNT;
716 	icb->request_q_length[0] = LSB(cnt);
717 	icb->request_q_length[1] = MSB(cnt);
718 	cnt = RESPONSE_ENTRY_CNT;
719 	icb->response_q_length[0] = LSB(cnt);
720 	icb->response_q_length[1] = MSB(cnt);
721 
722 	icb->request_q_address[0] = LSB(LSW(LSD(ha->request_dvma)));
723 	icb->request_q_address[1] = MSB(LSW(LSD(ha->request_dvma)));
724 	icb->request_q_address[2] = LSB(MSW(LSD(ha->request_dvma)));
725 	icb->request_q_address[3] = MSB(MSW(LSD(ha->request_dvma)));
726 	icb->request_q_address[4] = LSB(LSW(MSD(ha->request_dvma)));
727 	icb->request_q_address[5] = MSB(LSW(MSD(ha->request_dvma)));
728 	icb->request_q_address[6] = LSB(MSW(MSD(ha->request_dvma)));
729 	icb->request_q_address[7] = MSB(MSW(MSD(ha->request_dvma)));
730 
731 	icb->response_q_address[0] = LSB(LSW(LSD(ha->response_dvma)));
732 	icb->response_q_address[1] = MSB(LSW(LSD(ha->response_dvma)));
733 	icb->response_q_address[2] = LSB(MSW(LSD(ha->response_dvma)));
734 	icb->response_q_address[3] = MSB(MSW(LSD(ha->response_dvma)));
735 	icb->response_q_address[4] = LSB(LSW(MSD(ha->response_dvma)));
736 	icb->response_q_address[5] = MSB(LSW(MSD(ha->response_dvma)));
737 	icb->response_q_address[6] = LSB(MSW(MSD(ha->response_dvma)));
738 	icb->response_q_address[7] = MSB(MSW(MSD(ha->response_dvma)));
739 
740 	/*
741 	 * Setup IP initialization control block
742 	 */
743 	ip_icb->version = IP_ICB_VERSION;
744 
745 	if (CFG_IST(ha, CFG_ENABLE_64BIT_ADDRESSING)) {
746 		ip_icb->ip_firmware_options[0] = (uint8_t)
747 		    (ip_icb->ip_firmware_options[0] | BIT_2 | BIT_0);
748 	} else {
749 		ip_icb->ip_firmware_options[0] = (uint8_t)
750 		    (ip_icb->ip_firmware_options[0] | BIT_2);
751 	}
752 
753 	cnt = RCVBUF_CONTAINER_CNT;
754 	ip_icb->queue_size[0] = LSB(cnt);
755 	ip_icb->queue_size[1] = MSB(cnt);
756 
757 	ip_icb->queue_address[0] = LSB(LSW(LSD(ha->rcvbuf_dvma)));
758 	ip_icb->queue_address[1] = MSB(LSW(LSD(ha->rcvbuf_dvma)));
759 	ip_icb->queue_address[2] = LSB(MSW(LSD(ha->rcvbuf_dvma)));
760 	ip_icb->queue_address[3] = MSB(MSW(LSD(ha->rcvbuf_dvma)));
761 	ip_icb->queue_address[4] = LSB(LSW(MSD(ha->rcvbuf_dvma)));
762 	ip_icb->queue_address[5] = MSB(LSW(MSD(ha->rcvbuf_dvma)));
763 	ip_icb->queue_address[6] = LSB(MSW(MSD(ha->rcvbuf_dvma)));
764 	ip_icb->queue_address[7] = MSB(MSW(MSD(ha->rcvbuf_dvma)));
765 
766 	if (rval != QL_SUCCESS) {
767 		EL(ha, "failed, rval = %xh\n", rval);
768 	} else {
769 		/*EMPTY*/
770 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
771 	}
772 	return (rval);
773 }
774 
775 /*
776  * Get NVRAM data word
777  *	Calculates word position in NVRAM and calls request routine to
778  *	get the word from NVRAM.
779  *
780  * Input:
781  *	ha = adapter state pointer.
782  *	address = NVRAM word address.
783  *
784  * Returns:
785  *	data word.
786  *
787  * Context:
788  *	Kernel context.
789  */
790 uint16_t
791 ql_get_nvram_word(ql_adapter_state_t *ha, uint32_t address)
792 {
793 	uint32_t	nv_cmd;
794 	uint16_t	rval;
795 
796 	QL_PRINT_4(CE_CONT, "(%d): started\n", ha->instance);
797 
798 	nv_cmd = address << 16;
799 	nv_cmd = nv_cmd | NV_READ_OP;
800 
801 	rval = (uint16_t)ql_nvram_request(ha, nv_cmd);
802 
803 	QL_PRINT_4(CE_CONT, "(%d): NVRAM data = %xh\n", ha->instance, rval);
804 
805 	return (rval);
806 }
807 
808 /*
809  * NVRAM request
810  *	Sends read command to NVRAM and gets data from NVRAM.
811  *
812  * Input:
813  *	ha = adapter state pointer.
814  *	nv_cmd = Bit 26= start bit
815  *	Bit 25, 24 = opcode
816  *	Bit 23-16 = address
817  *	Bit 15-0 = write data
818  *
819  * Returns:
820  *	data word.
821  *
822  * Context:
823  *	Kernel context.
824  */
825 static uint16_t
826 ql_nvram_request(ql_adapter_state_t *ha, uint32_t nv_cmd)
827 {
828 	uint8_t		cnt;
829 	uint16_t	reg_data;
830 	uint16_t	data = 0;
831 
832 	/* Send command to NVRAM. */
833 
834 	nv_cmd <<= 5;
835 	for (cnt = 0; cnt < 11; cnt++) {
836 		if (nv_cmd & BIT_31) {
837 			ql_nv_write(ha, NV_DATA_OUT);
838 		} else {
839 			ql_nv_write(ha, 0);
840 		}
841 		nv_cmd <<= 1;
842 	}
843 
844 	/* Read data from NVRAM. */
845 
846 	for (cnt = 0; cnt < 16; cnt++) {
847 		WRT16_IO_REG(ha, nvram, NV_SELECT+NV_CLOCK);
848 		ql_nv_delay();
849 		data <<= 1;
850 		reg_data = RD16_IO_REG(ha, nvram);
851 		if (reg_data & NV_DATA_IN) {
852 			data = (uint16_t)(data | BIT_0);
853 		}
854 		WRT16_IO_REG(ha, nvram, NV_SELECT);
855 		ql_nv_delay();
856 	}
857 
858 	/* Deselect chip. */
859 
860 	WRT16_IO_REG(ha, nvram, NV_DESELECT);
861 	ql_nv_delay();
862 
863 	return (data);
864 }
865 
866 void
867 ql_nv_write(ql_adapter_state_t *ha, uint16_t data)
868 {
869 	WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT));
870 	ql_nv_delay();
871 	WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT | NV_CLOCK));
872 	ql_nv_delay();
873 	WRT16_IO_REG(ha, nvram, (uint16_t)(data | NV_SELECT));
874 	ql_nv_delay();
875 }
876 
877 void
878 ql_nv_delay(void)
879 {
880 	drv_usecwait(NV_DELAY_COUNT);
881 }
882 
883 /*
884  * ql_nvram_24xx_config
885  *	ISP2400 nvram.
886  *
887  * Input:
888  *	ha:		adapter state pointer.
889  *	ha->hba_buf = request and response rings
890  *
891  * Output:
892  *	ha->init_ctrl_blk = initialization control block
893  *	host adapters parameters in host adapter block
894  *
895  * Returns:
896  *	ql local function return status code.
897  *
898  * Context:
899  *	Kernel context.
900  */
901 int
902 ql_nvram_24xx_config(ql_adapter_state_t *ha)
903 {
904 	uint32_t		index, addr, chksum, saved_chksum;
905 	uint32_t		*longptr;
906 	nvram_24xx_t		nvram;
907 	int			idpromlen;
908 	char			idprombuf[32];
909 	caddr_t			src, dst;
910 	uint16_t		w1;
911 	int			rval;
912 	nvram_24xx_t		*nv = (nvram_24xx_t *)&nvram;
913 	ql_init_24xx_cb_t	*icb =
914 	    (ql_init_24xx_cb_t *)&ha->init_ctrl_blk.cb24;
915 	ql_ip_init_24xx_cb_t	*ip_icb = &ha->ip_init_ctrl_blk.cb24;
916 
917 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
918 
919 	if ((rval = ql_lock_nvram(ha, &addr, LNF_NVRAM_DATA)) == QL_SUCCESS) {
920 
921 		/* Get NVRAM data and calculate checksum. */
922 		longptr = (uint32_t *)nv;
923 		chksum = saved_chksum = 0;
924 		for (index = 0; index < sizeof (nvram_24xx_t) / 4; index++) {
925 			rval = ql_24xx_read_flash(ha, addr++, longptr);
926 			if (rval != QL_SUCCESS) {
927 				EL(ha, "24xx_read_flash failed=%xh\n", rval);
928 				break;
929 			}
930 			saved_chksum = chksum;
931 			chksum += *longptr;
932 			LITTLE_ENDIAN_32(longptr);
933 			longptr++;
934 		}
935 
936 		ql_release_nvram(ha);
937 	}
938 
939 	/* Bad NVRAM data, set defaults parameters. */
940 	if (rval != QL_SUCCESS || chksum || nv->id[0] != 'I' ||
941 	    nv->id[1] != 'S' || nv->id[2] != 'P' || nv->id[3] != ' ' ||
942 	    (nv->nvram_version[0] | nv->nvram_version[1]) == 0) {
943 
944 		cmn_err(CE_WARN, "%s(%d): NVRAM configuration failed, using "
945 		    "driver defaults.", QL_NAME, ha->instance);
946 
947 		EL(ha, "failed, rval=%xh, checksum=%xh, id=%c%c%c%c, "
948 		    "nvram_version=%x\n", rval, chksum, nv->id[0], nv->id[1],
949 		    nv->id[2], nv->id[3], CHAR_TO_SHORT(nv->nvram_version[0],
950 		    nv->nvram_version[1]));
951 
952 		saved_chksum = ~saved_chksum + 1;
953 
954 		(void) ql_flash_errlog(ha, FLASH_ERRLOG_NVRAM_CHKSUM_ERR, 0,
955 		    MSW(saved_chksum), LSW(saved_chksum));
956 
957 		/* Reset NVRAM data. */
958 		bzero((void *)nv, sizeof (nvram_24xx_t));
959 
960 		/*
961 		 * Set default initialization control block.
962 		 */
963 		nv->nvram_version[0] = LSB(ICB_24XX_VERSION);
964 		nv->nvram_version[1] = MSB(ICB_24XX_VERSION);
965 
966 		nv->version[0] = 1;
967 		nv->max_frame_length[1] = 8;
968 		nv->execution_throttle[0] = 16;
969 		nv->exchange_count[0] = 128;
970 		nv->max_luns_per_target[0] = 8;
971 
972 		idpromlen = 32;
973 
974 		/*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
975 		if (rval = ddi_getlongprop_buf(DDI_DEV_T_ANY, ha->dip,
976 		    DDI_PROP_CANSLEEP, "idprom", (caddr_t)idprombuf,
977 		    &idpromlen) != DDI_PROP_SUCCESS) {
978 
979 			cmn_err(CE_WARN, "%s(%d) : Unable to read idprom "
980 			    "property, rval=%x", QL_NAME, ha->instance, rval);
981 
982 			nv->port_name[0] = 33;
983 			nv->port_name[3] = 224;
984 			nv->port_name[4] = 139;
985 			nv->port_name[7] = (uint8_t)
986 			    (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
987 		} else {
988 			nv->port_name[2] = idprombuf[2];
989 			nv->port_name[3] = idprombuf[3];
990 			nv->port_name[4] = idprombuf[4];
991 			nv->port_name[5] = idprombuf[5];
992 			nv->port_name[6] = idprombuf[6];
993 			nv->port_name[7] = idprombuf[7];
994 			nv->port_name[0] = (uint8_t)
995 			    (NAA_ID_IEEE_EXTENDED << 4 | ha->instance);
996 		}
997 
998 		cmn_err(CE_WARN, "%s(%d): Unreliable HBA NVRAM, using default "
999 		    "HBA parameters and temporary "
1000 		    "WWPN: %02x%02x%02x%02x%02x%02x%02x%02x", QL_NAME,
1001 		    ha->instance, nv->port_name[0], nv->port_name[1],
1002 		    nv->port_name[2], nv->port_name[3], nv->port_name[4],
1003 		    nv->port_name[5], nv->port_name[6], nv->port_name[7]);
1004 
1005 		nv->login_retry_count[0] = 8;
1006 
1007 		nv->firmware_options_1[0] = BIT_2 | BIT_1;
1008 		nv->firmware_options_1[1] = BIT_5;
1009 		nv->firmware_options_2[0] = BIT_5;
1010 		nv->firmware_options_2[1] = BIT_4;
1011 		nv->firmware_options_3[1] = BIT_6;
1012 
1013 		/*
1014 		 * Set default host adapter parameters
1015 		 */
1016 		nv->host_p[0] = BIT_4 | BIT_1;
1017 		nv->host_p[1] = BIT_3 | BIT_2;
1018 		nv->reset_delay = 5;
1019 		nv->max_luns_per_target[0] = 128;
1020 		nv->port_down_retry_count[0] = 30;
1021 		nv->link_down_timeout[0] = 30;
1022 
1023 		if (CFG_IST(ha, CFG_CTRL_8081)) {
1024 			nv->firmware_options_3[2] = BIT_4;
1025 			nv->feature_mask_l[0] = 9;
1026 			nv->ext_blk.version[0] = 1;
1027 			nv->ext_blk.fcf_vlan_match = 1;
1028 			nv->ext_blk.fcf_vlan_id[0] = LSB(1002);
1029 			nv->ext_blk.fcf_vlan_id[1] = MSB(1002);
1030 			nv->fw.isp8001.e_node_mac_addr[1] = 2;
1031 			nv->fw.isp8001.e_node_mac_addr[2] = 3;
1032 			nv->fw.isp8001.e_node_mac_addr[3] = 4;
1033 			nv->fw.isp8001.e_node_mac_addr[4] = MSB(ha->instance);
1034 			nv->fw.isp8001.e_node_mac_addr[5] = LSB(ha->instance);
1035 		}
1036 
1037 		rval = QL_FUNCTION_FAILED;
1038 	}
1039 
1040 	/* Check for adapter node name (big endian). */
1041 	for (index = 0; index < 8; index++) {
1042 		if (nv->node_name[index] != 0) {
1043 			break;
1044 		}
1045 	}
1046 
1047 	/* Copy port name if no node name (big endian). */
1048 	if (index == 8) {
1049 		bcopy((void *)&nv->port_name[0], (void *)&nv->node_name[0], 8);
1050 		nv->node_name[0] = (uint8_t)(nv->node_name[0] & ~BIT_0);
1051 		nv->port_name[0] = (uint8_t)(nv->node_name[0] | BIT_0);
1052 	}
1053 
1054 	/* Reset initialization control blocks. */
1055 	bzero((void *)icb, sizeof (ql_init_24xx_cb_t));
1056 
1057 	/* Get driver properties. */
1058 	ql_24xx_properties(ha, nv);
1059 
1060 	cmn_err(CE_CONT, "!Qlogic %s(%d) WWPN=%02x%02x%02x%02x"
1061 	    "%02x%02x%02x%02x : WWNN=%02x%02x%02x%02x%02x%02x%02x%02x\n",
1062 	    QL_NAME, ha->instance, nv->port_name[0], nv->port_name[1],
1063 	    nv->port_name[2], nv->port_name[3], nv->port_name[4],
1064 	    nv->port_name[5], nv->port_name[6], nv->port_name[7],
1065 	    nv->node_name[0], nv->node_name[1], nv->node_name[2],
1066 	    nv->node_name[3], nv->node_name[4], nv->node_name[5],
1067 	    nv->node_name[6], nv->node_name[7]);
1068 
1069 	/*
1070 	 * Copy over NVRAM Firmware Initialization Control Block.
1071 	 */
1072 	dst = (caddr_t)icb;
1073 	src = (caddr_t)&nv->version;
1074 	index = (uint32_t)((uintptr_t)&icb->response_q_inpointer[0] -
1075 	    (uintptr_t)icb);
1076 	while (index--) {
1077 		*dst++ = *src++;
1078 	}
1079 	icb->login_retry_count[0] = nv->login_retry_count[0];
1080 	icb->login_retry_count[1] = nv->login_retry_count[1];
1081 	icb->link_down_on_nos[0] = nv->link_down_on_nos[0];
1082 	icb->link_down_on_nos[1] = nv->link_down_on_nos[1];
1083 
1084 	dst = (caddr_t)&icb->interrupt_delay_timer;
1085 	src = (caddr_t)&nv->interrupt_delay_timer;
1086 	index = (uint32_t)((uintptr_t)&icb->qos -
1087 	    (uintptr_t)&icb->interrupt_delay_timer);
1088 	while (index--) {
1089 		*dst++ = *src++;
1090 	}
1091 
1092 	/*
1093 	 * Setup driver firmware options.
1094 	 */
1095 	if (CFG_IST(ha, CFG_CTRL_8081)) {
1096 		dst = (caddr_t)icb->enode_mac_addr;
1097 		src = (caddr_t)nv->fw.isp8001.e_node_mac_addr;
1098 		index = sizeof (nv->fw.isp8001.e_node_mac_addr);
1099 		while (index--) {
1100 			*dst++ = *src++;
1101 		}
1102 		dst = (caddr_t)&icb->ext_blk;
1103 		src = (caddr_t)&nv->ext_blk;
1104 		index = sizeof (ql_ext_icb_8100_t);
1105 		while (index--) {
1106 			*dst++ = *src++;
1107 		}
1108 		EL(ha, "e_node_mac_addr=%02x-%02x-%02x-%02x-%02x-%02x\n",
1109 		    icb->enode_mac_addr[0], icb->enode_mac_addr[1],
1110 		    icb->enode_mac_addr[2], icb->enode_mac_addr[3],
1111 		    icb->enode_mac_addr[4], icb->enode_mac_addr[5]);
1112 	} else {
1113 		icb->firmware_options_1[0] = (uint8_t)
1114 		    (icb->firmware_options_1[0] | BIT_1);
1115 		icb->firmware_options_1[1] = (uint8_t)
1116 		    (icb->firmware_options_1[1] | BIT_5 | BIT_2);
1117 		icb->firmware_options_3[0] = (uint8_t)
1118 		    (icb->firmware_options_3[0] | BIT_1);
1119 	}
1120 	icb->firmware_options_1[0] = (uint8_t)(icb->firmware_options_1[0] &
1121 	    ~(BIT_5 | BIT_4));
1122 	icb->firmware_options_1[1] = (uint8_t)(icb->firmware_options_1[1] |
1123 	    BIT_6);
1124 	icb->firmware_options_2[0] = (uint8_t)(icb->firmware_options_2[0] &
1125 	    ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
1126 	if (CFG_IST(ha, CFG_ENABLE_FCP_2_SUPPORT)) {
1127 		icb->firmware_options_2[1] = (uint8_t)
1128 		    (icb->firmware_options_2[1] | BIT_4);
1129 	} else {
1130 		icb->firmware_options_2[1] = (uint8_t)
1131 		    (icb->firmware_options_2[1] & ~BIT_4);
1132 	}
1133 
1134 	icb->firmware_options_3[0] = (uint8_t)(icb->firmware_options_3[0] &
1135 	    ~BIT_7);
1136 
1137 	/* enable special N port 2 N port login behaviour */
1138 	if (CFG_IST(ha, CFG_CTRL_2425)) {
1139 		icb->firmware_options_3[1] =
1140 		    (uint8_t)(icb->firmware_options_3[1] | BIT_0);
1141 	}
1142 
1143 	icb->execution_throttle[0] = 0xff;
1144 	icb->execution_throttle[1] = 0xff;
1145 
1146 	/*
1147 	 * Set host adapter parameters
1148 	 */
1149 	ADAPTER_STATE_LOCK(ha);
1150 	ha->nvram_version = CHAR_TO_SHORT(nv->nvram_version[0],
1151 	    nv->nvram_version[1]);
1152 	nv->host_p[1] & BIT_2 ? (ha->cfg_flags |= CFG_ENABLE_FULL_LIP_LOGIN) :
1153 	    (ha->cfg_flags &= ~CFG_ENABLE_FULL_LIP_LOGIN);
1154 	nv->host_p[1] & BIT_3 ? (ha->cfg_flags |= CFG_ENABLE_TARGET_RESET) :
1155 	    (ha->cfg_flags &= ~CFG_ENABLE_TARGET_RESET);
1156 	ha->cfg_flags &= ~(CFG_DISABLE_RISC_CODE_LOAD | CFG_LR_SUPPORT |
1157 	    CFG_SET_CACHE_LINE_SIZE_1 | CFG_MULTI_CHIP_ADAPTER);
1158 	ha->cfg_flags |= CFG_ENABLE_64BIT_ADDRESSING;
1159 	if (CFG_IST(ha, CFG_CTRL_81XX) && nv->enhanced_features[0] & BIT_0) {
1160 		ha->cfg_flags |= CFG_LR_SUPPORT;
1161 	}
1162 	ADAPTER_STATE_UNLOCK(ha);
1163 
1164 	ha->execution_throttle = CHAR_TO_SHORT(nv->execution_throttle[0],
1165 	    nv->execution_throttle[1]);
1166 	ha->loop_reset_delay = nv->reset_delay;
1167 	ha->port_down_retry_count = CHAR_TO_SHORT(nv->port_down_retry_count[0],
1168 	    nv->port_down_retry_count[1]);
1169 	w1 = CHAR_TO_SHORT(icb->login_timeout[0], icb->login_timeout[1]);
1170 	ha->r_a_tov = (uint16_t)(w1 < R_A_TOV_DEFAULT ? R_A_TOV_DEFAULT : w1);
1171 	ha->maximum_luns_per_target = CHAR_TO_SHORT(
1172 	    nv->max_luns_per_target[0], nv->max_luns_per_target[1]);
1173 	if (ha->maximum_luns_per_target == 0) {
1174 		ha->maximum_luns_per_target++;
1175 	}
1176 
1177 	/* ISP2422 Serial Link Control */
1178 	if (CFG_IST(ha, CFG_CTRL_2422)) {
1179 		ha->serdes_param[0] = CHAR_TO_SHORT(nv->fw.isp2400.swing_opt[0],
1180 		    nv->fw.isp2400.swing_opt[1]);
1181 		ha->serdes_param[1] = CHAR_TO_SHORT(nv->fw.isp2400.swing_1g[0],
1182 		    nv->fw.isp2400.swing_1g[1]);
1183 		ha->serdes_param[2] = CHAR_TO_SHORT(nv->fw.isp2400.swing_2g[0],
1184 		    nv->fw.isp2400.swing_2g[1]);
1185 		ha->serdes_param[3] = CHAR_TO_SHORT(nv->fw.isp2400.swing_4g[0],
1186 		    nv->fw.isp2400.swing_4g[1]);
1187 	}
1188 
1189 	/*
1190 	 * Setup ring parameters in initialization control block
1191 	 */
1192 	w1 = REQUEST_ENTRY_CNT;
1193 	icb->request_q_length[0] = LSB(w1);
1194 	icb->request_q_length[1] = MSB(w1);
1195 	w1 = RESPONSE_ENTRY_CNT;
1196 	icb->response_q_length[0] = LSB(w1);
1197 	icb->response_q_length[1] = MSB(w1);
1198 
1199 	icb->request_q_address[0] = LSB(LSW(LSD(ha->request_dvma)));
1200 	icb->request_q_address[1] = MSB(LSW(LSD(ha->request_dvma)));
1201 	icb->request_q_address[2] = LSB(MSW(LSD(ha->request_dvma)));
1202 	icb->request_q_address[3] = MSB(MSW(LSD(ha->request_dvma)));
1203 	icb->request_q_address[4] = LSB(LSW(MSD(ha->request_dvma)));
1204 	icb->request_q_address[5] = MSB(LSW(MSD(ha->request_dvma)));
1205 	icb->request_q_address[6] = LSB(MSW(MSD(ha->request_dvma)));
1206 	icb->request_q_address[7] = MSB(MSW(MSD(ha->request_dvma)));
1207 
1208 	icb->response_q_address[0] = LSB(LSW(LSD(ha->response_dvma)));
1209 	icb->response_q_address[1] = MSB(LSW(LSD(ha->response_dvma)));
1210 	icb->response_q_address[2] = LSB(MSW(LSD(ha->response_dvma)));
1211 	icb->response_q_address[3] = MSB(MSW(LSD(ha->response_dvma)));
1212 	icb->response_q_address[4] = LSB(LSW(MSD(ha->response_dvma)));
1213 	icb->response_q_address[5] = MSB(LSW(MSD(ha->response_dvma)));
1214 	icb->response_q_address[6] = LSB(MSW(MSD(ha->response_dvma)));
1215 	icb->response_q_address[7] = MSB(MSW(MSD(ha->response_dvma)));
1216 
1217 	/*
1218 	 * Setup IP initialization control block
1219 	 */
1220 	ip_icb->version = IP_ICB_24XX_VERSION;
1221 
1222 	ip_icb->ip_firmware_options[0] = (uint8_t)
1223 	    (ip_icb->ip_firmware_options[0] | BIT_2);
1224 
1225 	if (rval != QL_SUCCESS) {
1226 		EL(ha, "failed, rval = %xh\n", rval);
1227 	} else {
1228 		/*EMPTY*/
1229 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1230 	}
1231 	return (rval);
1232 }
1233 
1234 /*
1235  * ql_lock_nvram
1236  *	Locks NVRAM access and returns starting address of NVRAM.
1237  *
1238  * Input:
1239  *	ha:	adapter state pointer.
1240  *	addr:	pointer for start address.
1241  *	flags:	Are mutually exclusive:
1242  *		LNF_NVRAM_DATA --> get nvram
1243  *		LNF_VPD_DATA --> get vpd data (24/25xx only).
1244  *
1245  * Returns:
1246  *	ql local function return status code.
1247  *
1248  * Context:
1249  *	Kernel context.
1250  */
1251 int
1252 ql_lock_nvram(ql_adapter_state_t *ha, uint32_t *addr, uint32_t flags)
1253 {
1254 	int	i;
1255 
1256 	if ((flags & LNF_NVRAM_DATA) && (flags & LNF_VPD_DATA)) {
1257 		EL(ha, "invalid options for function");
1258 		return (QL_FUNCTION_FAILED);
1259 	}
1260 
1261 	if (ha->device_id == 0x2312 || ha->device_id == 0x2322) {
1262 		if ((flags & LNF_NVRAM_DATA) == 0) {
1263 			EL(ha, "invalid 2312/2322 option for HBA");
1264 			return (QL_FUNCTION_FAILED);
1265 		}
1266 
1267 		/* if function number is non-zero, then adjust offset */
1268 		*addr = ha->flash_nvram_addr;
1269 
1270 		/* Try to get resource lock. Wait for 10 seconds max */
1271 		for (i = 0; i < 10000; i++) {
1272 			/* if nvram busy bit is reset, acquire sema */
1273 			if ((RD16_IO_REG(ha, nvram) & 0x8000) == 0) {
1274 				WRT16_IO_REG(ha, host_to_host_sema, 1);
1275 				drv_usecwait(MILLISEC);
1276 				if (RD16_IO_REG(ha, host_to_host_sema) & 1) {
1277 					break;
1278 				}
1279 			}
1280 			drv_usecwait(MILLISEC);
1281 		}
1282 		if ((RD16_IO_REG(ha, host_to_host_sema) & 1) == 0) {
1283 			cmn_err(CE_WARN, "%s(%d): unable to get NVRAM lock",
1284 			    QL_NAME, ha->instance);
1285 			return (QL_FUNCTION_FAILED);
1286 		}
1287 	} else if (CFG_IST(ha, CFG_CTRL_2422)) {
1288 		if (flags & LNF_VPD_DATA) {
1289 			*addr = NVRAM_DATA_ADDR | ha->flash_vpd_addr;
1290 		} else if (flags & LNF_NVRAM_DATA) {
1291 			*addr = NVRAM_DATA_ADDR | ha->flash_nvram_addr;
1292 		} else {
1293 			EL(ha, "invalid 2422 option for HBA");
1294 			return (QL_FUNCTION_FAILED);
1295 		}
1296 
1297 		GLOBAL_HW_LOCK();
1298 	} else if (CFG_IST(ha, CFG_CTRL_258081)) {
1299 		if (flags & LNF_VPD_DATA) {
1300 			*addr = ha->flash_data_addr | ha->flash_vpd_addr;
1301 		} else if (flags & LNF_NVRAM_DATA) {
1302 			*addr = ha->flash_data_addr | ha->flash_nvram_addr;
1303 		} else {
1304 			EL(ha, "invalid 2581 option for HBA");
1305 			return (QL_FUNCTION_FAILED);
1306 		}
1307 
1308 		GLOBAL_HW_LOCK();
1309 	} else {
1310 		if ((flags & LNF_NVRAM_DATA) == 0) {
1311 			EL(ha, "invalid option for HBA");
1312 			return (QL_FUNCTION_FAILED);
1313 		}
1314 		*addr = 0;
1315 		GLOBAL_HW_LOCK();
1316 	}
1317 
1318 	return (QL_SUCCESS);
1319 }
1320 
1321 /*
1322  * ql_release_nvram
1323  *	Releases NVRAM access.
1324  *
1325  * Input:
1326  *	ha:	adapter state pointer.
1327  *
1328  * Context:
1329  *	Kernel context.
1330  */
1331 void
1332 ql_release_nvram(ql_adapter_state_t *ha)
1333 {
1334 	if (ha->device_id == 0x2312 || ha->device_id == 0x2322) {
1335 		/* Release resource lock */
1336 		WRT16_IO_REG(ha, host_to_host_sema, 0);
1337 	} else {
1338 		GLOBAL_HW_UNLOCK();
1339 	}
1340 }
1341 
1342 /*
1343  * ql_23_properties
1344  *	Copies driver properties to NVRAM or adapter structure.
1345  *
1346  *	Driver properties are by design global variables and hidden
1347  *	completely from administrators. Knowledgeable folks can
1348  *	override the default values using driver.conf
1349  *
1350  * Input:
1351  *	ha:	adapter state pointer.
1352  *	nv:	NVRAM structure pointer.
1353  *
1354  * Context:
1355  *	Kernel context.
1356  */
1357 static void
1358 ql_23_properties(ql_adapter_state_t *ha, nvram_t *nv)
1359 {
1360 	uint32_t	data, cnt;
1361 
1362 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1363 
1364 	/* Get frame payload size. */
1365 	if ((data = ql_get_prop(ha, "max-frame-length")) == 0xffffffff) {
1366 		data = 2048;
1367 	}
1368 	if (data == 512 || data == 1024 || data == 2048) {
1369 		nv->max_frame_length[0] = LSB(data);
1370 		nv->max_frame_length[1] = MSB(data);
1371 	} else {
1372 		EL(ha, "invalid parameter value for 'max-frame-length': "
1373 		    "%d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1374 		    nv->max_frame_length[0], nv->max_frame_length[1]));
1375 	}
1376 
1377 	/* Get max IOCB allocation. */
1378 	nv->max_iocb_allocation[0] = 0;
1379 	nv->max_iocb_allocation[1] = 1;
1380 
1381 	/* Get execution throttle. */
1382 	if ((data = ql_get_prop(ha, "execution-throttle")) == 0xffffffff) {
1383 		data = 32;
1384 	}
1385 	if (data != 0 && data < 65536) {
1386 		nv->execution_throttle[0] = LSB(data);
1387 		nv->execution_throttle[1] = MSB(data);
1388 	} else {
1389 		EL(ha, "invalid parameter value for 'execution-throttle': "
1390 		    "%d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1391 		    nv->execution_throttle[0], nv->execution_throttle[1]));
1392 	}
1393 
1394 	/* Get Login timeout. */
1395 	if ((data = ql_get_prop(ha, "login-timeout")) == 0xffffffff) {
1396 		data = 3;
1397 	}
1398 	if (data < 256) {
1399 		nv->login_timeout = (uint8_t)data;
1400 	} else {
1401 		EL(ha, "invalid parameter value for 'login-timeout': "
1402 		    "%d; using nvram value of %d\n", data, nv->login_timeout);
1403 	}
1404 
1405 	/* Get retry count. */
1406 	if ((data = ql_get_prop(ha, "login-retry-count")) == 0xffffffff) {
1407 		data = 4;
1408 	}
1409 	if (data < 256) {
1410 		nv->login_retry_count = (uint8_t)data;
1411 	} else {
1412 		EL(ha, "invalid parameter value for 'login-retry-count': "
1413 		    "%d; using nvram value of %d\n", data,
1414 		    nv->login_retry_count);
1415 	}
1416 
1417 	/* Get adapter hard loop ID enable. */
1418 	data =  ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1419 	if (data == 0) {
1420 		nv->firmware_options[0] =
1421 		    (uint8_t)(nv->firmware_options[0] & ~BIT_0);
1422 	} else if (data == 1) {
1423 		nv->firmware_options[0] =
1424 		    (uint8_t)(nv->firmware_options[0] | BIT_0);
1425 	} else if (data != 0xffffffff) {
1426 		EL(ha, "invalid parameter value for "
1427 		    "'enable-adapter-hard-loop-ID': %d; using nvram value "
1428 		    "of %d\n", data, nv->firmware_options[0] & BIT_0 ? 1 : 0);
1429 	}
1430 
1431 	/* Get adapter hard loop ID. */
1432 	data =  ql_get_prop(ha, "adapter-hard-loop-ID");
1433 	if (data < 126) {
1434 		nv->hard_address[0] = (uint8_t)data;
1435 	} else if (data != 0xffffffff) {
1436 		EL(ha, "invalid parameter value for 'adapter-hard-loop-ID': "
1437 		    "%d; using nvram value of %d\n",
1438 		    data, nv->hard_address[0]);
1439 	}
1440 
1441 	/* Get LIP reset. */
1442 	if ((data = ql_get_prop(ha, "enable-LIP-reset-on-bus-reset")) ==
1443 	    0xffffffff) {
1444 		data = 0;
1445 	}
1446 	if (data == 0) {
1447 		nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_1);
1448 	} else if (data == 1) {
1449 		nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_1);
1450 	} else {
1451 		EL(ha, "invalid parameter value for "
1452 		    "'enable-LIP-reset-on-bus-reset': %d; using nvram value "
1453 		    "of %d\n", data, nv->host_p[1] & BIT_1 ? 1 : 0);
1454 	}
1455 
1456 	/* Get LIP full login. */
1457 	if ((data = ql_get_prop(ha, "enable-LIP-full-login-on-bus-reset")) ==
1458 	    0xffffffff) {
1459 		data = 1;
1460 	}
1461 	if (data == 0) {
1462 		nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_2);
1463 	} else if (data == 1) {
1464 		nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_2);
1465 	} else {
1466 		EL(ha, "invalid parameter value for "
1467 		    "'enable-LIP-full-login-on-bus-reset': %d; using nvram "
1468 		    "value of %d\n", data, nv->host_p[1] & BIT_2 ? 1 : 0);
1469 	}
1470 
1471 	/* Get target reset. */
1472 	if ((data = ql_get_prop(ha, "enable-target-reset-on-bus-reset")) ==
1473 	    0xffffffff) {
1474 		data = 0;
1475 	}
1476 	if (data == 0) {
1477 		nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_3);
1478 	} else if (data == 1) {
1479 		nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_3);
1480 	} else {
1481 		EL(ha, "invalid parameter value for "
1482 		    "'enable-target-reset-on-bus-reset': %d; using nvram "
1483 		    "value of %d", data, nv->host_p[1] & BIT_3 ? 1 : 0);
1484 	}
1485 
1486 	/* Get reset delay. */
1487 	if ((data = ql_get_prop(ha, "reset-delay")) == 0xffffffff) {
1488 		data = 5;
1489 	}
1490 	if (data != 0 && data < 256) {
1491 		nv->reset_delay = (uint8_t)data;
1492 	} else {
1493 		EL(ha, "invalid parameter value for 'reset-delay': %d; "
1494 		    "using nvram value of %d", data, nv->reset_delay);
1495 	}
1496 
1497 	/* Get port down retry count. */
1498 	if ((data = ql_get_prop(ha, "port-down-retry-count")) == 0xffffffff) {
1499 		data = 8;
1500 	}
1501 	if (data < 256) {
1502 		nv->port_down_retry_count = (uint8_t)data;
1503 	} else {
1504 		EL(ha, "invalid parameter value for 'port-down-retry-count':"
1505 		    " %d; using nvram value of %d\n", data,
1506 		    nv->port_down_retry_count);
1507 	}
1508 
1509 	/* Get connection mode setting. */
1510 	if ((data = ql_get_prop(ha, "connection-options")) == 0xffffffff) {
1511 		data = 2;
1512 	}
1513 	cnt = CFG_IST(ha, CFG_CTRL_2200) ? 3 : 2;
1514 	if (data <= cnt) {
1515 		nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] &
1516 		    ~(BIT_6 | BIT_5 | BIT_4));
1517 		nv->add_fw_opt[0] = (uint8_t)(nv->add_fw_opt[0] |
1518 		    (uint8_t)(data << 4));
1519 	} else {
1520 		EL(ha, "invalid parameter value for 'connection-options': "
1521 		    "%d; using nvram value of %d\n", data,
1522 		    (nv->add_fw_opt[0] >> 4) & 0x3);
1523 	}
1524 
1525 	/* Get data rate setting. */
1526 	if ((CFG_IST(ha, CFG_CTRL_2200)) == 0) {
1527 		if ((data = ql_get_prop(ha, "fc-data-rate")) == 0xffffffff) {
1528 			data = 2;
1529 		}
1530 		if (data < 3) {
1531 			nv->special_options[1] = (uint8_t)
1532 			    (nv->special_options[1] & 0x3f);
1533 			nv->special_options[1] = (uint8_t)
1534 			    (nv->special_options[1] | (uint8_t)(data << 6));
1535 		} else {
1536 			EL(ha, "invalid parameter value for 'fc-data-rate': "
1537 			    "%d; using nvram value of %d\n", data,
1538 			    (nv->special_options[1] >> 6) & 0x3);
1539 		}
1540 	}
1541 
1542 	/* Get adapter id string for Sun branded 23xx only */
1543 	if ((CFG_IST(ha, CFG_CTRL_2300)) && nv->adapInfo[0] != 0) {
1544 		(void) snprintf((int8_t *)ha->adapInfo, 16, "%s",
1545 		    nv->adapInfo);
1546 	}
1547 
1548 	/* Get IP FW container count. */
1549 	ha->ip_init_ctrl_blk.cb.cc[0] = LSB(ql_ip_buffer_count);
1550 	ha->ip_init_ctrl_blk.cb.cc[1] = MSB(ql_ip_buffer_count);
1551 
1552 	/* Get IP low water mark. */
1553 	ha->ip_init_ctrl_blk.cb.low_water_mark[0] = LSB(ql_ip_low_water);
1554 	ha->ip_init_ctrl_blk.cb.low_water_mark[1] = MSB(ql_ip_low_water);
1555 
1556 	/* Get IP fast register post count. */
1557 	ha->ip_init_ctrl_blk.cb.fast_post_reg_count[0] =
1558 	    ql_ip_fast_post_count;
1559 
1560 	ADAPTER_STATE_LOCK(ha);
1561 
1562 	ql_common_properties(ha);
1563 
1564 	ADAPTER_STATE_UNLOCK(ha);
1565 
1566 	QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1567 }
1568 
1569 /*
1570  * ql_common_properties
1571  *	Driver properties adapter structure.
1572  *
1573  *	Driver properties are by design global variables and hidden
1574  *	completely from administrators. Knowledgeable folks can
1575  *	override the default values using driver.conf
1576  *
1577  * Input:
1578  *	ha:	adapter state pointer.
1579  *
1580  * Context:
1581  *	Kernel context.
1582  */
1583 void
1584 ql_common_properties(ql_adapter_state_t *ha)
1585 {
1586 	uint32_t	data;
1587 
1588 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1589 
1590 	/* Get extended logging trace buffer size. */
1591 	if ((data = ql_get_prop(ha, "set-ext-log-buffer-size")) !=
1592 	    0xffffffff && data != 0) {
1593 		char		*new_trace;
1594 		uint32_t	new_size;
1595 
1596 		if (ha->el_trace_desc->trace_buffer != NULL) {
1597 			new_size = 1024 * data;
1598 			new_trace = (char *)kmem_zalloc(new_size, KM_SLEEP);
1599 
1600 			if (new_trace == NULL) {
1601 				cmn_err(CE_WARN, "%s(%d): can't get new"
1602 				    " trace buffer",
1603 				    QL_NAME, ha->instance);
1604 			} else {
1605 				/* free the previous */
1606 				kmem_free(ha->el_trace_desc->trace_buffer,
1607 				    ha->el_trace_desc->trace_buffer_size);
1608 				/* Use the new one */
1609 				ha->el_trace_desc->trace_buffer = new_trace;
1610 				ha->el_trace_desc->trace_buffer_size = new_size;
1611 			}
1612 		}
1613 
1614 	}
1615 
1616 	/* Get extended logging enable. */
1617 	if ((data = ql_get_prop(ha, "extended-logging")) == 0xffffffff ||
1618 	    data == 0) {
1619 		ha->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING;
1620 	} else if (data == 1) {
1621 		ha->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING;
1622 	} else {
1623 		EL(ha, "invalid parameter value for 'extended-logging': %d;"
1624 		    " using default value of 0\n", data);
1625 		ha->cfg_flags &= ~CFG_ENABLE_EXTENDED_LOGGING;
1626 	}
1627 
1628 	/* Get extended logging trace disable. */
1629 	if ((data = ql_get_prop(ha, "disable-extended-logging-trace")) ==
1630 	    0xffffffff || data == 0) {
1631 		ha->cfg_flags &= ~CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1632 	} else if (data == 1) {
1633 		ha->cfg_flags |= CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1634 	} else {
1635 		EL(ha, "invalid parameter value for "
1636 		    "'disable-extended-logging-trace': %d;"
1637 		    " using default value of 0\n", data);
1638 		ha->cfg_flags &= ~CFG_DISABLE_EXTENDED_LOGGING_TRACE;
1639 	}
1640 
1641 	/* Get FCP 2 Error Recovery. */
1642 	if ((data = ql_get_prop(ha, "enable-FCP-2-error-recovery")) ==
1643 	    0xffffffff || data == 1) {
1644 		ha->cfg_flags |= CFG_ENABLE_FCP_2_SUPPORT;
1645 	} else if (data == 0) {
1646 		ha->cfg_flags &= ~CFG_ENABLE_FCP_2_SUPPORT;
1647 	} else {
1648 		EL(ha, "invalid parameter value for "
1649 		    "'enable-FCP-2-error-recovery': %d; using nvram value of "
1650 		    "1\n", data);
1651 		ha->cfg_flags |= CFG_ENABLE_FCP_2_SUPPORT;
1652 	}
1653 
1654 #ifdef QL_DEBUG_LEVEL_2
1655 	ha->cfg_flags |= CFG_ENABLE_EXTENDED_LOGGING;
1656 #endif
1657 
1658 	/* Get port down retry delay. */
1659 	if ((data = ql_get_prop(ha, "port-down-retry-delay")) == 0xffffffff) {
1660 		ha->port_down_retry_delay = PORT_RETRY_TIME;
1661 	} else if (data < 256) {
1662 		ha->port_down_retry_delay = (uint8_t)data;
1663 	} else {
1664 		EL(ha, "invalid parameter value for 'port-down-retry-delay':"
1665 		    " %d; using default value of %d", data, PORT_RETRY_TIME);
1666 		ha->port_down_retry_delay = PORT_RETRY_TIME;
1667 	}
1668 
1669 	/* Get queue full retry count. */
1670 	if ((data = ql_get_prop(ha, "queue-full-retry-count")) == 0xffffffff) {
1671 		ha->qfull_retry_count = 16;
1672 	} else if (data < 256) {
1673 		ha->qfull_retry_count = (uint8_t)data;
1674 	} else {
1675 		EL(ha, "invalid parameter value for 'queue-full-retry-count':"
1676 		    " %d; using default value of 16", data);
1677 		ha->qfull_retry_count = 16;
1678 	}
1679 
1680 	/* Get queue full retry delay. */
1681 	if ((data = ql_get_prop(ha, "queue-full-retry-delay")) == 0xffffffff) {
1682 		ha->qfull_retry_delay = PORT_RETRY_TIME;
1683 	} else if (data < 256) {
1684 		ha->qfull_retry_delay = (uint8_t)data;
1685 	} else {
1686 		EL(ha, "invalid parameter value for 'queue-full-retry-delay':"
1687 		    " %d; using default value of %d", data, PORT_RETRY_TIME);
1688 		ha->qfull_retry_delay = PORT_RETRY_TIME;
1689 	}
1690 
1691 	/* Get loop down timeout. */
1692 	if ((data = ql_get_prop(ha, "link-down-timeout")) == 0xffffffff) {
1693 		data = 0;
1694 	} else if (data > 255) {
1695 		EL(ha, "invalid parameter value for 'link-down-timeout': %d;"
1696 		    " using nvram value of 0\n", data);
1697 		data = 0;
1698 	}
1699 	ha->loop_down_abort_time = (uint8_t)(LOOP_DOWN_TIMER_START - data);
1700 	if (ha->loop_down_abort_time == LOOP_DOWN_TIMER_START) {
1701 		ha->loop_down_abort_time--;
1702 	} else if (ha->loop_down_abort_time <= LOOP_DOWN_TIMER_END) {
1703 		ha->loop_down_abort_time = LOOP_DOWN_TIMER_END + 1;
1704 	}
1705 
1706 	/* Get link down error enable. */
1707 	if ((data = ql_get_prop(ha, "enable-link-down-error")) == 0xffffffff ||
1708 	    data == 1) {
1709 		ha->cfg_flags |= CFG_ENABLE_LINK_DOWN_REPORTING;
1710 	} else if (data == 0) {
1711 		ha->cfg_flags &= ~CFG_ENABLE_LINK_DOWN_REPORTING;
1712 	} else {
1713 		EL(ha, "invalid parameter value for 'link-down-error': %d;"
1714 		    " using default value of 1\n", data);
1715 	}
1716 
1717 	/*
1718 	 * Get firmware dump flags.
1719 	 *	TAKE_FW_DUMP_ON_MAILBOX_TIMEOUT		BIT_0
1720 	 *	TAKE_FW_DUMP_ON_ISP_SYSTEM_ERROR	BIT_1
1721 	 *	TAKE_FW_DUMP_ON_DRIVER_COMMAND_TIMEOUT	BIT_2
1722 	 *	TAKE_FW_DUMP_ON_LOOP_OFFLINE_TIMEOUT	BIT_3
1723 	 */
1724 	ha->cfg_flags &= ~(CFG_DUMP_MAILBOX_TIMEOUT |
1725 	    CFG_DUMP_ISP_SYSTEM_ERROR | CFG_DUMP_DRIVER_COMMAND_TIMEOUT |
1726 	    CFG_DUMP_LOOP_OFFLINE_TIMEOUT);
1727 	if ((data = ql_get_prop(ha, "firmware-dump-flags")) != 0xffffffff) {
1728 		if (data & BIT_0) {
1729 			ha->cfg_flags |= CFG_DUMP_MAILBOX_TIMEOUT;
1730 		}
1731 		if (data & BIT_1) {
1732 			ha->cfg_flags |= CFG_DUMP_ISP_SYSTEM_ERROR;
1733 		}
1734 		if (data & BIT_2) {
1735 			ha->cfg_flags |= CFG_DUMP_DRIVER_COMMAND_TIMEOUT;
1736 		}
1737 		if (data & BIT_3) {
1738 			ha->cfg_flags |= CFG_DUMP_LOOP_OFFLINE_TIMEOUT;
1739 		}
1740 	}
1741 
1742 	/* Get the PCI max read request size override. */
1743 	ha->pci_max_read_req = 0;
1744 	if ((data = ql_get_prop(ha, "pci-max-read-request")) != 0xffffffff &&
1745 	    data != 0) {
1746 		ha->pci_max_read_req = (uint16_t)(data);
1747 	}
1748 
1749 	/*
1750 	 * Set default fw wait, adjusted for slow FCF's.
1751 	 * Revisit when FCF's as fast as FC switches.
1752 	 */
1753 	ha->fwwait = (uint8_t)(CFG_IST(ha, CFG_CTRL_8081) ? 45 : 10);
1754 	/* Get the attach fw_ready override value. */
1755 	if ((data = ql_get_prop(ha, "init-loop-sync-wait")) != 0xffffffff) {
1756 		if (data > 0 && data <= 240) {
1757 			ha->fwwait = (uint8_t)data;
1758 		} else {
1759 			EL(ha, "invalid parameter value for "
1760 			    "'init-loop-sync-wait': %d; using default "
1761 			    "value of %d\n", data, ha->fwwait);
1762 		}
1763 	}
1764 
1765 	QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
1766 }
1767 
1768 /*
1769  * ql_24xx_properties
1770  *	Copies driver properties to NVRAM or adapter structure.
1771  *
1772  *	Driver properties are by design global variables and hidden
1773  *	completely from administrators. Knowledgeable folks can
1774  *	override the default values using /etc/system.
1775  *
1776  * Input:
1777  *	ha:	adapter state pointer.
1778  *	nv:	NVRAM structure pointer.
1779  *
1780  * Context:
1781  *	Kernel context.
1782  */
1783 static void
1784 ql_24xx_properties(ql_adapter_state_t *ha, nvram_24xx_t *nv)
1785 {
1786 	uint32_t	data;
1787 
1788 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
1789 
1790 	/* Get frame size */
1791 	if ((data = ql_get_prop(ha, "max-frame-length")) == 0xffffffff) {
1792 		data = 2048;
1793 	}
1794 	if (data == 512 || data == 1024 || data == 2048 || data == 2112) {
1795 		nv->max_frame_length[0] = LSB(data);
1796 		nv->max_frame_length[1] = MSB(data);
1797 	} else {
1798 		EL(ha, "invalid parameter value for 'max-frame-length': %d;"
1799 		    " using nvram default of %d\n", data, CHAR_TO_SHORT(
1800 		    nv->max_frame_length[0], nv->max_frame_length[1]));
1801 	}
1802 
1803 	/* Get execution throttle. */
1804 	if ((data = ql_get_prop(ha, "execution-throttle")) == 0xffffffff) {
1805 		data = 32;
1806 	}
1807 	if (data != 0 && data < 65536) {
1808 		nv->execution_throttle[0] = LSB(data);
1809 		nv->execution_throttle[1] = MSB(data);
1810 	} else {
1811 		EL(ha, "invalid parameter value for 'execution-throttle':"
1812 		    " %d; using nvram default of %d\n", data, CHAR_TO_SHORT(
1813 		    nv->execution_throttle[0], nv->execution_throttle[1]));
1814 	}
1815 
1816 	/* Get Login timeout. */
1817 	if ((data = ql_get_prop(ha, "login-timeout")) == 0xffffffff) {
1818 		data = 3;
1819 	}
1820 	if (data < 65536) {
1821 		nv->login_timeout[0] = LSB(data);
1822 		nv->login_timeout[1] = MSB(data);
1823 	} else {
1824 		EL(ha, "invalid parameter value for 'login-timeout': %d; "
1825 		    "using nvram value of %d\n", data, CHAR_TO_SHORT(
1826 		    nv->login_timeout[0], nv->login_timeout[1]));
1827 	}
1828 
1829 	/* Get retry count. */
1830 	if ((data = ql_get_prop(ha, "login-retry-count")) == 0xffffffff) {
1831 		data = 4;
1832 	}
1833 	if (data < 65536) {
1834 		nv->login_retry_count[0] = LSB(data);
1835 		nv->login_retry_count[1] = MSB(data);
1836 	} else {
1837 		EL(ha, "invalid parameter value for 'login-retry-count': "
1838 		    "%d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1839 		    nv->login_retry_count[0], nv->login_retry_count[1]));
1840 	}
1841 
1842 	/* Get adapter hard loop ID enable. */
1843 	data =  ql_get_prop(ha, "enable-adapter-hard-loop-ID");
1844 	if (data == 0) {
1845 		nv->firmware_options_1[0] =
1846 		    (uint8_t)(nv->firmware_options_1[0] & ~BIT_0);
1847 	} else if (data == 1) {
1848 		nv->firmware_options_1[0] =
1849 		    (uint8_t)(nv->firmware_options_1[0] | BIT_0);
1850 	} else if (data != 0xffffffff) {
1851 		EL(ha, "invalid parameter value for "
1852 		    "'enable-adapter-hard-loop-ID': %d; using nvram value "
1853 		    "of %d\n", data,
1854 		    nv->firmware_options_1[0] & BIT_0 ? 1 : 0);
1855 	}
1856 
1857 	/* Get adapter hard loop ID. */
1858 	data =  ql_get_prop(ha, "adapter-hard-loop-ID");
1859 	if (data < 126) {
1860 		nv->hard_address[0] = LSB(data);
1861 		nv->hard_address[1] = MSB(data);
1862 	} else if (data != 0xffffffff) {
1863 		EL(ha, "invalid parameter value for 'adapter-hard-loop-ID':"
1864 		    " %d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1865 		    nv->hard_address[0], nv->hard_address[1]));
1866 	}
1867 
1868 	/* Get LIP reset. */
1869 	if ((data = ql_get_prop(ha, "enable-LIP-reset-on-bus-reset")) ==
1870 	    0xffffffff) {
1871 		data = 0;
1872 	}
1873 	if (data == 0) {
1874 		ha->cfg_flags &= ~CFG_ENABLE_LIP_RESET;
1875 	} else if (data == 1) {
1876 		ha->cfg_flags |= CFG_ENABLE_LIP_RESET;
1877 	} else {
1878 		EL(ha, "invalid parameter value for "
1879 		    "'enable-LIP-reset-on-bus-reset': %d; using value of 0\n",
1880 		    data);
1881 	}
1882 
1883 	/* Get LIP full login. */
1884 	if ((data = ql_get_prop(ha, "enable-LIP-full-login-on-bus-reset")) ==
1885 	    0xffffffff) {
1886 		data = 1;
1887 	}
1888 	if (data == 0) {
1889 		nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_2);
1890 	} else if (data == 1) {
1891 		nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_2);
1892 	} else {
1893 		EL(ha, "invalid parameter value for "
1894 		    "'enable-LIP-full-login-on-bus-reset': %d; using nvram "
1895 		    "value of %d\n", data, nv->host_p[1] & BIT_2 ? 1 : 0);
1896 	}
1897 
1898 	/* Get target reset. */
1899 	if ((data = ql_get_prop(ha, "enable-target-reset-on-bus-reset")) ==
1900 	    0xffffffff) {
1901 		data = 0;
1902 	}
1903 	if (data == 0) {
1904 		nv->host_p[1] = (uint8_t)(nv->host_p[1] & ~BIT_3);
1905 	} else if (data == 1) {
1906 		nv->host_p[1] = (uint8_t)(nv->host_p[1] | BIT_3);
1907 	} else {
1908 		EL(ha, "invalid parameter value for "
1909 		    "'enable-target-reset-on-bus-reset': %d; using nvram "
1910 		    "value of %d", data, nv->host_p[1] & BIT_3 ? 1 : 0);
1911 	}
1912 
1913 	/* Get reset delay. */
1914 	if ((data = ql_get_prop(ha, "reset-delay")) == 0xffffffff) {
1915 		data = 5;
1916 	}
1917 	if (data != 0 && data < 256) {
1918 		nv->reset_delay = (uint8_t)data;
1919 	} else {
1920 		EL(ha, "invalid parameter value for 'reset-delay': %d; "
1921 		    "using nvram value of %d", data, nv->reset_delay);
1922 	}
1923 
1924 	/* Get port down retry count. */
1925 	if ((data = ql_get_prop(ha, "port-down-retry-count")) == 0xffffffff) {
1926 		data = 8;
1927 	}
1928 	if (data < 256) {
1929 		nv->port_down_retry_count[0] = LSB(data);
1930 		nv->port_down_retry_count[1] = MSB(data);
1931 	} else {
1932 		EL(ha, "invalid parameter value for 'port-down-retry-count':"
1933 		    " %d; using nvram value of %d\n", data, CHAR_TO_SHORT(
1934 		    nv->port_down_retry_count[0],
1935 		    nv->port_down_retry_count[1]));
1936 	}
1937 
1938 	if (!(CFG_IST(ha, CFG_CTRL_8081))) {
1939 		/* Get connection mode setting. */
1940 		if ((data = ql_get_prop(ha, "connection-options")) ==
1941 		    0xffffffff) {
1942 			data = 2;
1943 		}
1944 		if (data <= 2) {
1945 			nv->firmware_options_2[0] = (uint8_t)
1946 			    (nv->firmware_options_2[0] &
1947 			    ~(BIT_6 | BIT_5 | BIT_4));
1948 			nv->firmware_options_2[0] = (uint8_t)
1949 			    (nv->firmware_options_2[0] | (uint8_t)(data << 4));
1950 		} else {
1951 			EL(ha, "invalid parameter value for 'connection-"
1952 			    "options': %d; using nvram value of %d\n", data,
1953 			    (nv->firmware_options_2[0] >> 4) & 0x3);
1954 		}
1955 
1956 		/* Get data rate setting. */
1957 		if ((data = ql_get_prop(ha, "fc-data-rate")) == 0xffffffff) {
1958 			data = 2;
1959 		}
1960 		if ((CFG_IST(ha, CFG_CTRL_2422) && data < 4) ||
1961 		    (CFG_IST(ha, CFG_CTRL_258081) && data < 5)) {
1962 			nv->firmware_options_3[1] = (uint8_t)
1963 			    (nv->firmware_options_3[1] & 0x1f);
1964 			nv->firmware_options_3[1] = (uint8_t)
1965 			    (nv->firmware_options_3[1] | (uint8_t)(data << 5));
1966 		} else {
1967 			EL(ha, "invalid parameter value for 'fc-data-rate': "
1968 			    "%d; using nvram value of %d\n", data,
1969 			    (nv->firmware_options_3[1] >> 5) & 0x7);
1970 		}
1971 	}
1972 
1973 	/* Get IP FW container count. */
1974 	ha->ip_init_ctrl_blk.cb24.cc[0] = LSB(ql_ip_buffer_count);
1975 	ha->ip_init_ctrl_blk.cb24.cc[1] = MSB(ql_ip_buffer_count);
1976 
1977 	/* Get IP low water mark. */
1978 	ha->ip_init_ctrl_blk.cb24.low_water_mark[0] = LSB(ql_ip_low_water);
1979 	ha->ip_init_ctrl_blk.cb24.low_water_mark[1] = MSB(ql_ip_low_water);
1980 
1981 	ADAPTER_STATE_LOCK(ha);
1982 
1983 	/* Get enable flash load. */
1984 	if ((data = ql_get_prop(ha, "enable-flash-load")) == 0xffffffff ||
1985 	    data == 0) {
1986 		ha->cfg_flags &= ~CFG_LOAD_FLASH_FW;
1987 	} else if (data == 1) {
1988 		ha->cfg_flags |= CFG_LOAD_FLASH_FW;
1989 	} else {
1990 		EL(ha, "invalid parameter value for 'enable-flash-load': "
1991 		    "%d; using default value of 0\n", data);
1992 	}
1993 
1994 	/* Enable firmware extended tracing */
1995 	if ((data = ql_get_prop(ha, "enable-fwexttrace")) != 0xffffffff) {
1996 		if (data != 0) {
1997 			ha->cfg_flags |= CFG_ENABLE_FWEXTTRACE;
1998 		}
1999 	}
2000 
2001 	/* Enable firmware fc tracing */
2002 	if ((data = ql_get_prop(ha, "enable-fwfcetrace")) != 0xffffffff) {
2003 		ha->cfg_flags |= CFG_ENABLE_FWFCETRACE;
2004 		ha->fwfcetraceopt = data;
2005 	}
2006 
2007 	/* Enable fast timeout */
2008 	if ((data = ql_get_prop(ha, "enable-fasttimeout")) != 0xffffffff) {
2009 		if (data != 0) {
2010 			ha->cfg_flags |= CFG_FAST_TIMEOUT;
2011 		}
2012 	}
2013 
2014 	ql_common_properties(ha);
2015 
2016 	ADAPTER_STATE_UNLOCK(ha);
2017 
2018 	QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2019 }
2020 
2021 /*
2022  * ql_get_prop
2023  *	Get property value from configuration file.
2024  *
2025  * Input:
2026  *	ha= adapter state pointer.
2027  *	string = property string pointer.
2028  *
2029  * Returns:
2030  *	0xFFFFFFFF = no property else property value.
2031  *
2032  * Context:
2033  *	Kernel context.
2034  */
2035 uint32_t
2036 ql_get_prop(ql_adapter_state_t *ha, char *string)
2037 {
2038 	char		buf[256];
2039 	uint32_t	data = 0xffffffff;
2040 
2041 	/*
2042 	 * Look for a adapter instance NPIV (virtual port) specific parameter
2043 	 */
2044 	if (CFG_IST(ha, CFG_CTRL_24258081)) {
2045 		(void) sprintf(buf, "hba%d-vp%d-%s", ha->instance,
2046 		    ha->vp_index, string);
2047 		/*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2048 		data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip, 0,
2049 		    buf, (int)0xffffffff);
2050 	}
2051 
2052 	/*
2053 	 * Get adapter instance parameter if a vp specific one isn't found.
2054 	 */
2055 	if (data == 0xffffffff) {
2056 		(void) sprintf(buf, "hba%d-%s", ha->instance, string);
2057 		/*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2058 		data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip,
2059 		    0, buf, (int)0xffffffff);
2060 	}
2061 
2062 	/* Adapter instance parameter found? */
2063 	if (data == 0xffffffff) {
2064 		/* No, get default parameter. */
2065 		/*LINTED [Solaris DDI_DEV_T_ANY Lint warning]*/
2066 		data = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, ha->dip, 0,
2067 		    string, (int)0xffffffff);
2068 	}
2069 
2070 	return (data);
2071 }
2072 
2073 /*
2074  * ql_check_isp_firmware
2075  *	Checks if using already loaded RISC code or drivers copy.
2076  *	If using already loaded code, save a copy of it.
2077  *
2078  * Input:
2079  *	ha = adapter state pointer.
2080  *
2081  * Returns:
2082  *	ql local function return status code.
2083  *
2084  * Context:
2085  *	Kernel context.
2086  */
2087 static int
2088 ql_check_isp_firmware(ql_adapter_state_t *ha)
2089 {
2090 	int		rval;
2091 	uint16_t	word_count;
2092 	uint32_t	byte_count;
2093 	uint32_t	fw_size, *lptr;
2094 	caddr_t		bufp;
2095 	uint16_t	risc_address = (uint16_t)ha->risc_fw[0].addr;
2096 
2097 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2098 
2099 	/* Test for firmware running. */
2100 	if (CFG_IST(ha, CFG_CTRL_8021)) {
2101 		if (ql_8021_idc_handler(ha) != NX_DEV_READY) {
2102 			rval = QL_FUNCTION_FAILED;
2103 		} else {
2104 			rval = ql_start_firmware(ha);
2105 		}
2106 	} else if (CFG_IST(ha, CFG_DISABLE_RISC_CODE_LOAD)) {
2107 		if (ha->risc_code != NULL) {
2108 			kmem_free(ha->risc_code, ha->risc_code_size);
2109 			ha->risc_code = NULL;
2110 			ha->risc_code_size = 0;
2111 		}
2112 
2113 		/* Get RISC code length. */
2114 		rval = ql_rd_risc_ram(ha, risc_address + 3, ha->request_dvma,
2115 		    1);
2116 		if (rval == QL_SUCCESS) {
2117 			lptr = (uint32_t *)ha->request_ring_bp;
2118 			fw_size = *lptr << 1;
2119 
2120 			if ((bufp = kmem_alloc(fw_size, KM_SLEEP)) != NULL) {
2121 				ha->risc_code_size = fw_size;
2122 				ha->risc_code = bufp;
2123 				ha->fw_transfer_size = 128;
2124 
2125 				/* Dump RISC code. */
2126 				do {
2127 					if (fw_size > ha->fw_transfer_size) {
2128 						byte_count =
2129 						    ha->fw_transfer_size;
2130 					} else {
2131 						byte_count = fw_size;
2132 					}
2133 
2134 					word_count =
2135 					    (uint16_t)(byte_count >> 1);
2136 
2137 					rval = ql_rd_risc_ram(ha, risc_address,
2138 					    ha->request_dvma, word_count);
2139 					if (rval != QL_SUCCESS) {
2140 						kmem_free(ha->risc_code,
2141 						    ha->risc_code_size);
2142 						ha->risc_code = NULL;
2143 						ha->risc_code_size = 0;
2144 						break;
2145 					}
2146 
2147 					(void) ddi_dma_sync(
2148 					    ha->hba_buf.dma_handle,
2149 					    REQUEST_Q_BUFFER_OFFSET,
2150 					    byte_count,
2151 					    DDI_DMA_SYNC_FORKERNEL);
2152 					ddi_rep_get16(ha->hba_buf.acc_handle,
2153 					    (uint16_t *)bufp,
2154 					    (uint16_t *)ha->request_ring_bp,
2155 					    word_count, DDI_DEV_AUTOINCR);
2156 
2157 					risc_address += word_count;
2158 					fw_size -= byte_count;
2159 					bufp	+= byte_count;
2160 				} while (fw_size != 0);
2161 			}
2162 			rval = QL_FUNCTION_FAILED;
2163 		}
2164 	} else {
2165 		rval = QL_FUNCTION_FAILED;
2166 	}
2167 
2168 	if (rval != QL_SUCCESS) {
2169 		EL(ha, "Load RISC code\n");
2170 	} else {
2171 		/*EMPTY*/
2172 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2173 	}
2174 	return (rval);
2175 }
2176 
2177 /*
2178  * Chip diagnostics
2179  *	Test chip for proper operation.
2180  *
2181  * Input:
2182  *	ha = adapter state pointer.
2183  *
2184  * Returns:
2185  *	ql local function return status code.
2186  *
2187  * Context:
2188  *	Kernel context.
2189  */
2190 static int
2191 ql_chip_diag(ql_adapter_state_t *ha)
2192 {
2193 	ql_mbx_data_t	mr;
2194 	int		rval;
2195 	int32_t		retries = 4;
2196 	uint16_t	id;
2197 
2198 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2199 
2200 	do {
2201 		/* Reset ISP chip. */
2202 		TASK_DAEMON_LOCK(ha);
2203 		ha->task_daemon_flags &= ~ISP_ABORT_NEEDED;
2204 		TASK_DAEMON_UNLOCK(ha);
2205 
2206 		/* For ISP2200A reduce firmware load size. */
2207 		if (CFG_IST(ha, CFG_CTRL_2200) &&
2208 		    RD16_IO_REG(ha, mailbox_out[7]) == 4) {
2209 			ha->fw_transfer_size = 128;
2210 		} else {
2211 			ha->fw_transfer_size = REQUEST_QUEUE_SIZE;
2212 		}
2213 
2214 		bcopy(QL_VERSION, ha->adapter_stats->revlvl.qlddv,
2215 		    strlen(QL_VERSION));
2216 
2217 		rval = QL_SUCCESS;
2218 		if (!(CFG_IST(ha, CFG_CTRL_8021))) {
2219 			ql_reset_chip(ha);
2220 
2221 			/* Check product ID of chip */
2222 			mr.mb[1] = RD16_IO_REG(ha, mailbox_out[1]);
2223 			mr.mb[2] = RD16_IO_REG(ha, mailbox_out[2]);
2224 			mr.mb[3] = RD16_IO_REG(ha, mailbox_out[3]);
2225 
2226 			if (ha->device_id == 0x5432 ||
2227 			    ha->device_id == 0x8432) {
2228 				id = 0x2432;
2229 			} else if (ha->device_id == 0x5422 ||
2230 			    ha->device_id == 0x8422) {
2231 				id = 0x2422;
2232 			} else {
2233 				id = ha->device_id;
2234 			}
2235 
2236 			if (mr.mb[1] == PROD_ID_1 &&
2237 			    (mr.mb[2] == PROD_ID_2 || mr.mb[2] == PROD_ID_2a) &&
2238 			    (mr.mb[3] == PROD_ID_3 || mr.mb[3] == id)) {
2239 				ha->adapter_stats->revlvl.isp2200 =
2240 				    RD16_IO_REG(ha, mailbox_out[4]);
2241 				ha->adapter_stats->revlvl.risc =
2242 				    RD16_IO_REG(ha, mailbox_out[5]);
2243 				ha->adapter_stats->revlvl.frmbfr =
2244 				    RD16_IO_REG(ha, mailbox_out[6]);
2245 				ha->adapter_stats->revlvl.riscrom =
2246 				    RD16_IO_REG(ha, mailbox_out[7]);
2247 			} else {
2248 				cmn_err(CE_WARN, "%s(%d) - prod id failed!, "
2249 				    "mb1=%xh, mb2=%xh, mb3=%xh", QL_NAME,
2250 				    ha->instance, mr.mb[1], mr.mb[2], mr.mb[3]);
2251 				rval = QL_FUNCTION_FAILED;
2252 			}
2253 		} else if (!(ha->task_daemon_flags & FIRMWARE_LOADED)) {
2254 			break;
2255 		}
2256 
2257 		if (rval == QL_SUCCESS) {
2258 			/* Wrap Incoming Mailboxes Test. */
2259 			mr.mb[1] = 0xAAAA;
2260 			mr.mb[2] = 0x5555;
2261 			mr.mb[3] = 0xAA55;
2262 			mr.mb[4] = 0x55AA;
2263 			mr.mb[5] = 0xA5A5;
2264 			mr.mb[6] = 0x5A5A;
2265 			mr.mb[7] = 0x2525;
2266 			rval = ql_mbx_wrap_test(ha, &mr);
2267 			if (rval == QL_SUCCESS) {
2268 				if (mr.mb[1] != 0xAAAA ||
2269 				    mr.mb[2] != 0x5555 ||
2270 				    mr.mb[3] != 0xAA55 ||
2271 				    mr.mb[4] != 0x55AA ||
2272 				    mr.mb[5] != 0xA5A5 ||
2273 				    mr.mb[6] != 0x5A5A ||
2274 				    mr.mb[7] != 0x2525) {
2275 					rval = QL_FUNCTION_FAILED;
2276 					(void) ql_flash_errlog(ha,
2277 					    FLASH_ERRLOG_ISP_ERR, 0,
2278 					    RD16_IO_REG(ha, hccr),
2279 					    RD16_IO_REG(ha, istatus));
2280 				}
2281 			} else {
2282 				cmn_err(CE_WARN, "%s(%d) - reg test failed="
2283 				    "%xh!", QL_NAME, ha->instance, rval);
2284 			}
2285 		}
2286 	} while ((retries-- != 0) && (rval != QL_SUCCESS));
2287 
2288 	if (rval != QL_SUCCESS) {
2289 		EL(ha, "failed, rval = %xh\n", rval);
2290 	} else {
2291 		/*EMPTY*/
2292 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2293 	}
2294 	return (rval);
2295 }
2296 
2297 /*
2298  * ql_load_isp_firmware
2299  *	Load and start RISC firmware.
2300  *	Uses request ring for DMA buffer.
2301  *
2302  * Input:
2303  *	ha = adapter state pointer.
2304  *
2305  * Returns:
2306  *	ql local function return status code.
2307  *
2308  * Context:
2309  *	Kernel context.
2310  */
2311 int
2312 ql_load_isp_firmware(ql_adapter_state_t *vha)
2313 {
2314 	caddr_t			risc_code_address;
2315 	uint32_t		risc_address, risc_code_size;
2316 	int			rval;
2317 	uint32_t		word_count, cnt;
2318 	size_t			byte_count;
2319 	ql_adapter_state_t	*ha = vha->pha;
2320 
2321 	if (CFG_IST(ha, CFG_CTRL_8021)) {
2322 		rval = ql_8021_load_risc(ha);
2323 	} else {
2324 		if (CFG_IST(ha, CFG_CTRL_81XX)) {
2325 			ql_mps_reset(ha);
2326 		}
2327 
2328 		if (CFG_IST(ha, CFG_LOAD_FLASH_FW)) {
2329 			return (ql_load_flash_fw(ha));
2330 		}
2331 
2332 		QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2333 
2334 		/* Load firmware segments */
2335 		for (cnt = 0; cnt < MAX_RISC_CODE_SEGMENTS &&
2336 		    ha->risc_fw[cnt].code != NULL; cnt++) {
2337 
2338 			risc_code_address = ha->risc_fw[cnt].code;
2339 			risc_address = ha->risc_fw[cnt].addr;
2340 			risc_code_size = ha->risc_fw[cnt].length;
2341 
2342 			while (risc_code_size) {
2343 				if (CFG_IST(ha, CFG_CTRL_242581)) {
2344 					word_count = ha->fw_transfer_size >> 2;
2345 					if (word_count > risc_code_size) {
2346 						word_count = risc_code_size;
2347 					}
2348 					byte_count = word_count << 2;
2349 
2350 					ddi_rep_put32(ha->hba_buf.acc_handle,
2351 					    (uint32_t *)risc_code_address,
2352 					    (uint32_t *)ha->request_ring_bp,
2353 					    word_count, DDI_DEV_AUTOINCR);
2354 				} else {
2355 					word_count = ha->fw_transfer_size >> 1;
2356 					if (word_count > risc_code_size) {
2357 						word_count = risc_code_size;
2358 					}
2359 					byte_count = word_count << 1;
2360 
2361 					ddi_rep_put16(ha->hba_buf.acc_handle,
2362 					    (uint16_t *)risc_code_address,
2363 					    (uint16_t *)ha->request_ring_bp,
2364 					    word_count, DDI_DEV_AUTOINCR);
2365 				}
2366 
2367 				(void) ddi_dma_sync(ha->hba_buf.dma_handle,
2368 				    REQUEST_Q_BUFFER_OFFSET, byte_count,
2369 				    DDI_DMA_SYNC_FORDEV);
2370 
2371 				rval = ql_wrt_risc_ram(ha, risc_address,
2372 				    ha->request_dvma, word_count);
2373 				if (rval != QL_SUCCESS) {
2374 					EL(ha, "failed, load=%xh\n", rval);
2375 					cnt = MAX_RISC_CODE_SEGMENTS;
2376 					break;
2377 				}
2378 
2379 				risc_address += word_count;
2380 				risc_code_size -= word_count;
2381 				risc_code_address += byte_count;
2382 			}
2383 		}
2384 	}
2385 
2386 	/* Start firmware. */
2387 	if (rval == QL_SUCCESS) {
2388 		rval = ql_start_firmware(ha);
2389 	}
2390 
2391 	if (rval != QL_SUCCESS) {
2392 		EL(ha, "failed, rval = %xh\n", rval);
2393 	} else {
2394 		/*EMPTY*/
2395 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2396 	}
2397 
2398 	return (rval);
2399 }
2400 
2401 /*
2402  * ql_load_flash_fw
2403  *	Gets ISP24xx firmware from flash and loads ISP.
2404  *
2405  * Input:
2406  *	ha:	adapter state pointer.
2407  *
2408  * Returns:
2409  *	ql local function return status code.
2410  */
2411 static int
2412 ql_load_flash_fw(ql_adapter_state_t *ha)
2413 {
2414 	int		rval;
2415 	uint8_t		seg_cnt;
2416 	uint32_t	risc_address, xfer_size, count,	*bp, faddr;
2417 	uint32_t	risc_code_size = 0;
2418 
2419 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2420 
2421 	faddr = ha->flash_data_addr | ha->flash_fw_addr;
2422 
2423 	for (seg_cnt = 0; seg_cnt < 2; seg_cnt++) {
2424 		xfer_size = ha->fw_transfer_size >> 2;
2425 		do {
2426 			GLOBAL_HW_LOCK();
2427 
2428 			/* Read data from flash. */
2429 			bp = (uint32_t *)ha->request_ring_bp;
2430 			for (count = 0; count < xfer_size; count++) {
2431 				rval = ql_24xx_read_flash(ha, faddr++, bp);
2432 				if (rval != QL_SUCCESS) {
2433 					break;
2434 				}
2435 				ql_chg_endian((uint8_t *)bp++, 4);
2436 			}
2437 
2438 			GLOBAL_HW_UNLOCK();
2439 
2440 			if (rval != QL_SUCCESS) {
2441 				EL(ha, "24xx_read_flash failed=%xh\n", rval);
2442 				break;
2443 			}
2444 
2445 			if (risc_code_size == 0) {
2446 				bp = (uint32_t *)ha->request_ring_bp;
2447 				risc_address = bp[2];
2448 				risc_code_size = bp[3];
2449 				ha->risc_fw[seg_cnt].addr = risc_address;
2450 			}
2451 
2452 			if (risc_code_size < xfer_size) {
2453 				faddr -= xfer_size - risc_code_size;
2454 				xfer_size = risc_code_size;
2455 			}
2456 
2457 			(void) ddi_dma_sync(ha->hba_buf.dma_handle,
2458 			    REQUEST_Q_BUFFER_OFFSET, xfer_size << 2,
2459 			    DDI_DMA_SYNC_FORDEV);
2460 
2461 			rval = ql_wrt_risc_ram(ha, risc_address,
2462 			    ha->request_dvma, xfer_size);
2463 			if (rval != QL_SUCCESS) {
2464 				EL(ha, "ql_wrt_risc_ram failed=%xh\n", rval);
2465 				break;
2466 			}
2467 
2468 			risc_address += xfer_size;
2469 			risc_code_size -= xfer_size;
2470 		} while (risc_code_size);
2471 
2472 		if (rval != QL_SUCCESS) {
2473 			break;
2474 		}
2475 	}
2476 
2477 	/* Start firmware. */
2478 	if (rval == QL_SUCCESS) {
2479 		rval = ql_start_firmware(ha);
2480 	}
2481 
2482 	if (rval != QL_SUCCESS) {
2483 		EL(ha, "failed, rval = %xh\n", rval);
2484 	} else {
2485 		/*EMPTY*/
2486 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2487 	}
2488 	return (rval);
2489 }
2490 
2491 /*
2492  * ql_start_firmware
2493  *	Starts RISC code.
2494  *
2495  * Input:
2496  *	ha = adapter state pointer.
2497  *
2498  * Returns:
2499  *	ql local function return status code.
2500  *
2501  * Context:
2502  *	Kernel context.
2503  */
2504 int
2505 ql_start_firmware(ql_adapter_state_t *vha)
2506 {
2507 	int			rval, rval2;
2508 	uint32_t		data;
2509 	ql_mbx_data_t		mr;
2510 	ql_adapter_state_t	*ha = vha->pha;
2511 
2512 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2513 
2514 	if (CFG_IST(ha, CFG_CTRL_8021)) {
2515 		/* Save firmware version. */
2516 		rval = ql_get_fw_version(ha, &mr, MAILBOX_TOV);
2517 		ha->fw_major_version = mr.mb[1];
2518 		ha->fw_minor_version = mr.mb[2];
2519 		ha->fw_subminor_version = mr.mb[3];
2520 	} else if ((rval = ql_verify_checksum(ha)) == QL_SUCCESS) {
2521 		/* Verify checksum of loaded RISC code. */
2522 		/* Start firmware execution. */
2523 		(void) ql_execute_fw(ha);
2524 
2525 		/* Save firmware version. */
2526 		(void) ql_get_fw_version(ha, &mr, MAILBOX_TOV);
2527 		ha->fw_major_version = mr.mb[1];
2528 		ha->fw_minor_version = mr.mb[2];
2529 		ha->fw_subminor_version = mr.mb[3];
2530 		ha->fw_ext_memory_size = ((SHORT_TO_LONG(mr.mb[4], mr.mb[5]) -
2531 		    0x100000) + 1) * 4;
2532 		ha->fw_attributes = mr.mb[6];
2533 
2534 		if (CFG_IST(ha, CFG_CTRL_81XX)) {
2535 			ha->phy_fw_major_version = LSB(mr.mb[8]);
2536 			ha->phy_fw_minor_version = MSB(mr.mb[9]);
2537 			ha->phy_fw_subminor_version = LSB(mr.mb[9]);
2538 			ha->mpi_fw_major_version = LSB(mr.mb[10]);
2539 			ha->mpi_fw_minor_version = MSB(mr.mb[11]);
2540 			ha->mpi_fw_subminor_version = LSB(mr.mb[11]);
2541 			ha->mpi_capability_list = SHORT_TO_LONG(mr.mb[13],
2542 			    mr.mb[12]);
2543 			if ((rval2 = ql_flash_access(ha, FAC_GET_SECTOR_SIZE,
2544 			    0, 0, &data)) == QL_SUCCESS) {
2545 				ha->xioctl->fdesc.block_size = data << 2;
2546 				QL_PRINT_10(CE_CONT, "(%d): fdesc.block_size="
2547 				    "%xh\n", ha->instance,
2548 				    ha->xioctl->fdesc.block_size);
2549 			} else {
2550 				EL(ha, "flash_access status=%xh\n", rval2);
2551 			}
2552 		}
2553 
2554 		/* Set Serdes Transmit Parameters. */
2555 		if (CFG_IST(ha, CFG_CTRL_2422) && ha->serdes_param[0] & BIT_0) {
2556 			mr.mb[1] = ha->serdes_param[0];
2557 			mr.mb[2] = ha->serdes_param[1];
2558 			mr.mb[3] = ha->serdes_param[2];
2559 			mr.mb[4] = ha->serdes_param[3];
2560 			(void) ql_serdes_param(ha, &mr);
2561 		}
2562 	}
2563 
2564 	if (rval != QL_SUCCESS) {
2565 		ha->task_daemon_flags &= ~FIRMWARE_LOADED;
2566 		EL(ha, "failed, rval = %xh\n", rval);
2567 	} else {
2568 		ha->task_daemon_flags |= FIRMWARE_LOADED;
2569 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2570 	}
2571 	return (rval);
2572 }
2573 
2574 /*
2575  * ql_set_cache_line
2576  *	Sets PCI cache line parameter.
2577  *
2578  * Input:
2579  *	ha = adapter state pointer.
2580  *
2581  * Returns:
2582  *	ql local function return status code.
2583  *
2584  * Context:
2585  *	Kernel context.
2586  */
2587 int
2588 ql_set_cache_line(ql_adapter_state_t *ha)
2589 {
2590 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2591 
2592 	/* Set the cache line. */
2593 	if (CFG_IST(ha->pha, CFG_SET_CACHE_LINE_SIZE_1)) {
2594 		/* Set cache line register. */
2595 		ql_pci_config_put8(ha->pha, PCI_CONF_CACHE_LINESZ, 1);
2596 	}
2597 
2598 	QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2599 
2600 	return (QL_SUCCESS);
2601 }
2602 
2603 /*
2604  * ql_init_rings
2605  *	Initializes firmware and ring pointers.
2606  *
2607  *	Beginning of response ring has initialization control block
2608  *	already built by nvram config routine.
2609  *
2610  * Input:
2611  *	ha = adapter state pointer.
2612  *	ha->hba_buf = request and response rings
2613  *	ha->init_ctrl_blk = initialization control block
2614  *
2615  * Returns:
2616  *	ql local function return status code.
2617  *
2618  * Context:
2619  *	Kernel context.
2620  */
2621 int
2622 ql_init_rings(ql_adapter_state_t *vha2)
2623 {
2624 	int			rval, rval2;
2625 	uint16_t		index;
2626 	ql_mbx_data_t		mr;
2627 	ql_adapter_state_t	*ha = vha2->pha;
2628 
2629 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2630 
2631 	/* Clear outstanding commands array. */
2632 	for (index = 0; index < MAX_OUTSTANDING_COMMANDS; index++) {
2633 		ha->outstanding_cmds[index] = NULL;
2634 	}
2635 	ha->osc_index = 1;
2636 
2637 	ha->pending_cmds.first = NULL;
2638 	ha->pending_cmds.last = NULL;
2639 
2640 	/* Initialize firmware. */
2641 	ha->request_ring_ptr = ha->request_ring_bp;
2642 	ha->req_ring_index = 0;
2643 	ha->req_q_cnt = REQUEST_ENTRY_CNT - 1;
2644 	ha->response_ring_ptr = ha->response_ring_bp;
2645 	ha->rsp_ring_index = 0;
2646 
2647 	if (ha->flags & VP_ENABLED) {
2648 		ql_adapter_state_t	*vha;
2649 		uint16_t		cnt;
2650 		uint32_t		max_vports;
2651 		ql_init_24xx_cb_t	*icb = &ha->init_ctrl_blk.cb24;
2652 
2653 		max_vports = (CFG_IST(ha, CFG_CTRL_2422) ?
2654 		    MAX_24_VIRTUAL_PORTS : MAX_25_VIRTUAL_PORTS);
2655 		bzero(icb->vp_count,
2656 		    ((uintptr_t)icb + sizeof (ql_init_24xx_cb_t)) -
2657 		    (uintptr_t)icb->vp_count);
2658 		icb->vp_count[0] = (uint8_t)max_vports;
2659 
2660 		/* Allow connection option 2. */
2661 		icb->global_vp_option[0] = BIT_1;
2662 
2663 		for (cnt = 0, vha = ha->vp_next; cnt < max_vports &&
2664 		    vha != NULL; vha = vha->vp_next, cnt++) {
2665 
2666 			index = (uint8_t)(vha->vp_index - 1);
2667 			bcopy(vha->loginparams.node_ww_name.raw_wwn,
2668 			    icb->vpc[index].node_name, 8);
2669 			bcopy(vha->loginparams.nport_ww_name.raw_wwn,
2670 			    icb->vpc[index].port_name, 8);
2671 
2672 			icb->vpc[index].options = VPO_TARGET_MODE_DISABLED |
2673 			    VPO_INITIATOR_MODE_ENABLED;
2674 			if (vha->flags & VP_ENABLED) {
2675 				icb->vpc[index].options = (uint8_t)
2676 				    (icb->vpc[index].options | VPO_ENABLED);
2677 			}
2678 		}
2679 	}
2680 
2681 	for (index = 0; index < 2; index++) {
2682 		rval = ql_init_firmware(ha);
2683 		if (rval == QL_COMMAND_ERROR) {
2684 			EL(ha, "stopping firmware\n");
2685 			(void) ql_stop_firmware(ha);
2686 		} else {
2687 			break;
2688 		}
2689 	}
2690 
2691 	if (rval == QL_SUCCESS && (CFG_IST(ha, CFG_CTRL_24258081)) == 0) {
2692 		/* Tell firmware to enable MBA_PORT_BYPASS_CHANGED event */
2693 		rval = ql_get_firmware_option(ha, &mr);
2694 		if (rval == QL_SUCCESS) {
2695 			mr.mb[1] = (uint16_t)(mr.mb[1] | BIT_9);
2696 			mr.mb[2] = 0;
2697 			mr.mb[3] = BIT_10;
2698 			rval = ql_set_firmware_option(ha, &mr);
2699 		}
2700 	}
2701 
2702 	if ((rval == QL_SUCCESS) && (CFG_IST(ha, CFG_ENABLE_FWFCETRACE))) {
2703 		/* Firmware Fibre Channel Event Trace Buffer */
2704 		if ((rval2 = ql_get_dma_mem(ha, &ha->fwfcetracebuf, FWFCESIZE,
2705 		    LITTLE_ENDIAN_DMA, QL_DMA_RING_ALIGN)) != QL_SUCCESS) {
2706 			EL(ha, "fcetrace buffer alloc failed: %xh\n", rval2);
2707 		} else {
2708 			if ((rval2 = ql_fw_etrace(ha, &ha->fwfcetracebuf,
2709 			    FTO_FCE_TRACE_ENABLE)) != QL_SUCCESS) {
2710 				EL(ha, "fcetrace enable failed: %xh\n", rval2);
2711 				ql_free_phys(ha, &ha->fwfcetracebuf);
2712 			}
2713 		}
2714 	}
2715 
2716 	if ((rval == QL_SUCCESS) && (CFG_IST(ha, CFG_ENABLE_FWEXTTRACE))) {
2717 		/* Firmware Extended Trace Buffer */
2718 		if ((rval2 = ql_get_dma_mem(ha, &ha->fwexttracebuf, FWEXTSIZE,
2719 		    LITTLE_ENDIAN_DMA, QL_DMA_RING_ALIGN)) != QL_SUCCESS) {
2720 			EL(ha, "exttrace buffer alloc failed: %xh\n", rval2);
2721 		} else {
2722 			if ((rval2 = ql_fw_etrace(ha, &ha->fwexttracebuf,
2723 			    FTO_EXT_TRACE_ENABLE)) != QL_SUCCESS) {
2724 				EL(ha, "exttrace enable failed: %xh\n", rval2);
2725 				ql_free_phys(ha, &ha->fwexttracebuf);
2726 			}
2727 		}
2728 	}
2729 
2730 	if (rval == QL_SUCCESS && CFG_IST(ha, CFG_CTRL_MENLO)) {
2731 		ql_mbx_iocb_t	*pkt;
2732 		clock_t		timer;
2733 
2734 		/* Wait for firmware login of menlo. */
2735 		for (timer = 3000; timer; timer--) {
2736 			if (ha->flags & MENLO_LOGIN_OPERATIONAL) {
2737 				break;
2738 			}
2739 
2740 			if (!(ha->flags & INTERRUPTS_ENABLED) ||
2741 			    ddi_in_panic()) {
2742 				if (INTERRUPT_PENDING(ha)) {
2743 					(void) ql_isr((caddr_t)ha);
2744 					INTR_LOCK(ha);
2745 					ha->intr_claimed = B_TRUE;
2746 					INTR_UNLOCK(ha);
2747 				}
2748 			}
2749 
2750 			/* Delay for 1 tick (10 milliseconds). */
2751 			ql_delay(ha, 10000);
2752 		}
2753 
2754 		if (timer == 0) {
2755 			rval = QL_FUNCTION_TIMEOUT;
2756 		} else {
2757 			pkt = kmem_zalloc(sizeof (ql_mbx_iocb_t), KM_SLEEP);
2758 			if (pkt == NULL) {
2759 				EL(ha, "failed, kmem_zalloc\n");
2760 				rval = QL_MEMORY_ALLOC_FAILED;
2761 			} else {
2762 				pkt->mvfy.entry_type = VERIFY_MENLO_TYPE;
2763 				pkt->mvfy.entry_count = 1;
2764 				pkt->mvfy.options_status =
2765 				    LE_16(VMF_DO_NOT_UPDATE_FW);
2766 
2767 				rval = ql_issue_mbx_iocb(ha, (caddr_t)pkt,
2768 				    sizeof (ql_mbx_iocb_t));
2769 				LITTLE_ENDIAN_16(&pkt->mvfy.options_status);
2770 				LITTLE_ENDIAN_16(&pkt->mvfy.failure_code);
2771 
2772 				if (rval != QL_SUCCESS ||
2773 				    (pkt->mvfy.entry_status & 0x3c) != 0 ||
2774 				    pkt->mvfy.options_status != CS_COMPLETE) {
2775 					EL(ha, "failed, status=%xh, es=%xh, "
2776 					    "cs=%xh, fc=%xh\n", rval,
2777 					    pkt->mvfy.entry_status & 0x3c,
2778 					    pkt->mvfy.options_status,
2779 					    pkt->mvfy.failure_code);
2780 					if (rval == QL_SUCCESS) {
2781 						rval = QL_FUNCTION_FAILED;
2782 					}
2783 				}
2784 
2785 				kmem_free(pkt, sizeof (ql_mbx_iocb_t));
2786 			}
2787 		}
2788 	}
2789 
2790 	if (rval != QL_SUCCESS) {
2791 		TASK_DAEMON_LOCK(ha);
2792 		ha->task_daemon_flags &= ~FIRMWARE_UP;
2793 		TASK_DAEMON_UNLOCK(ha);
2794 		EL(ha, "failed, rval = %xh\n", rval);
2795 	} else {
2796 		TASK_DAEMON_LOCK(ha);
2797 		ha->task_daemon_flags |= FIRMWARE_UP;
2798 		TASK_DAEMON_UNLOCK(ha);
2799 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2800 	}
2801 	return (rval);
2802 }
2803 
2804 /*
2805  * ql_fw_ready
2806  *	Waits for firmware ready. If firmware becomes ready
2807  *	device queues and RISC code are synchronized.
2808  *
2809  * Input:
2810  *	ha = adapter state pointer.
2811  *	secs = max wait time, in seconds (0-255).
2812  *
2813  * Returns:
2814  *	ql local function return status code.
2815  *
2816  * Context:
2817  *	Kernel context.
2818  */
2819 int
2820 ql_fw_ready(ql_adapter_state_t *ha, uint8_t secs)
2821 {
2822 	ql_mbx_data_t	mr;
2823 	clock_t		timer;
2824 	clock_t		dly = 250000;
2825 	clock_t		sec_delay = MICROSEC / dly;
2826 	clock_t		wait = secs * sec_delay;
2827 	int		rval = QL_FUNCTION_FAILED;
2828 	uint16_t	state = 0xffff;
2829 
2830 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2831 
2832 	timer = ha->r_a_tov < secs ? secs : ha->r_a_tov;
2833 	timer = (timer + 2) * sec_delay;
2834 
2835 	/* Wait for ISP to finish LIP */
2836 	while (timer != 0 && wait != 0 &&
2837 	    !(ha->task_daemon_flags & ISP_ABORT_NEEDED)) {
2838 
2839 		rval = ql_get_firmware_state(ha, &mr);
2840 		if (rval == QL_SUCCESS) {
2841 			if (ha->task_daemon_flags & (ISP_ABORT_NEEDED |
2842 			    LOOP_DOWN)) {
2843 				wait--;
2844 			} else if (mr.mb[1] != FSTATE_READY) {
2845 				if (mr.mb[1] != FSTATE_WAIT_LOGIN) {
2846 					wait--;
2847 				}
2848 				rval = QL_FUNCTION_FAILED;
2849 			} else {
2850 				/* Firmware is ready. Get 2 * R_A_TOV. */
2851 				rval = ql_get_timeout_parameters(ha,
2852 				    &ha->r_a_tov);
2853 				if (rval != QL_SUCCESS) {
2854 					EL(ha, "failed, get_timeout_param"
2855 					    "=%xh\n", rval);
2856 				}
2857 
2858 				/* Configure loop. */
2859 				rval = ql_configure_loop(ha);
2860 				(void) ql_marker(ha, 0, 0, MK_SYNC_ALL);
2861 
2862 				if (ha->task_daemon_flags &
2863 				    LOOP_RESYNC_NEEDED) {
2864 					wait--;
2865 					EL(ha, "loop trans; tdf=%xh\n",
2866 					    ha->task_daemon_flags);
2867 				} else {
2868 					break;
2869 				}
2870 			}
2871 		} else {
2872 			wait--;
2873 		}
2874 
2875 		if (state != mr.mb[1]) {
2876 			EL(ha, "mailbox_reg[1] = %xh\n", mr.mb[1]);
2877 			state = mr.mb[1];
2878 		}
2879 
2880 		/* Delay for a tick if waiting. */
2881 		if (timer-- != 0 && wait != 0) {
2882 			if (timer % 4 == 0) {
2883 				delay(drv_usectohz(dly));
2884 			} else {
2885 				drv_usecwait(dly);
2886 			}
2887 		} else {
2888 			rval = QL_FUNCTION_TIMEOUT;
2889 		}
2890 	}
2891 
2892 	if (rval != QL_SUCCESS) {
2893 		EL(ha, "failed, rval = %xh\n", rval);
2894 	} else {
2895 		/*EMPTY*/
2896 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2897 	}
2898 	return (rval);
2899 }
2900 
2901 /*
2902  * ql_configure_loop
2903  *	Setup configurations based on loop.
2904  *
2905  * Input:
2906  *	ha = adapter state pointer.
2907  *
2908  * Returns:
2909  *	ql local function return status code.
2910  *
2911  * Context:
2912  *	Kernel context.
2913  */
2914 static int
2915 ql_configure_loop(ql_adapter_state_t *ha)
2916 {
2917 	int			rval;
2918 	ql_adapter_state_t	*vha;
2919 
2920 	QL_PRINT_3(CE_CONT, "(%d): started\n", ha->instance);
2921 
2922 	for (vha = ha; vha != NULL; vha = vha->vp_next) {
2923 		TASK_DAEMON_LOCK(ha);
2924 		if (!(vha->task_daemon_flags & LOOP_RESYNC_NEEDED) &&
2925 		    vha->vp_index != 0 && !(vha->flags & VP_ENABLED)) {
2926 			TASK_DAEMON_UNLOCK(ha);
2927 			continue;
2928 		}
2929 		vha->task_daemon_flags &= ~LOOP_RESYNC_NEEDED;
2930 		TASK_DAEMON_UNLOCK(ha);
2931 
2932 		rval = ql_configure_hba(vha);
2933 		if (rval == QL_SUCCESS && !(ha->task_daemon_flags &
2934 		    (LOOP_RESYNC_NEEDED | LOOP_DOWN))) {
2935 			rval = ql_configure_device_d_id(vha);
2936 			if (rval == QL_SUCCESS && !(ha->task_daemon_flags &
2937 			    (LOOP_RESYNC_NEEDED | LOOP_DOWN))) {
2938 				(void) ql_configure_fabric(vha);
2939 			}
2940 		}
2941 	}
2942 
2943 	if (rval != QL_SUCCESS) {
2944 		EL(ha, "failed, rval = %xh\n", rval);
2945 	} else {
2946 		/*EMPTY*/
2947 		QL_PRINT_3(CE_CONT, "(%d): done\n", ha->instance);
2948 	}
2949 	return (rval);
2950 }
2951 
2952 /*
2953  * ql_configure_n_port_info
2954  *	Setup configurations based on N port 2 N port topology.
2955  *
2956  * Input:
2957  *	ha = adapter state pointer.
2958  *
2959  * Returns:
2960  *	ql local function return status code.
2961  *
2962  * Context:
2963  *	Kernel context.
2964  */
2965 static void
2966 ql_configure_n_port_info(ql_adapter_state_t *ha)
2967 {
2968 	ql_tgt_t	tmp_tq;
2969 	ql_tgt_t	*tq;
2970 	uint8_t		*cb_port_name;
2971 	ql_link_t	*link;
2972 	int		index, rval;
2973 
2974 	tq = &tmp_tq;
2975 
2976 	/* Free existing target queues. */
2977 	for (index = 0; index < DEVICE_HEAD_LIST_SIZE; index++) {
2978 		link = ha->dev[index].first;
2979 		while (link != NULL) {
2980 			tq = link->base_address;
2981 			link = link->next;
2982 			ql_remove_link(&ha->dev[index], &tq->device);
2983 			ql_dev_free(ha, tq);
2984 		}
2985 	}
2986 
2987 	/*
2988 	 * If the N_Port's WWPN is larger than our's then it has the
2989 	 * N_Port login initiative.  It will have determined that and
2990 	 * logged in with the firmware.  This results in a device
2991 	 * database entry.  In this situation we will later send up a PLOGI
2992 	 * by proxy for the N_Port to get things going.
2993 	 *
2994 	 * If the N_Ports WWPN is smaller then the firmware has the
2995 	 * N_Port login initiative and does a FLOGI in order to obtain the
2996 	 * N_Ports WWNN and WWPN.  These names are required later
2997 	 * during Leadvilles FLOGI.  No PLOGI is done by the firmware in
2998 	 * anticipation of a PLOGI via the driver from the upper layers.
2999 	 * Upon reciept of said PLOGI the driver issues an ELS PLOGI
3000 	 * pass-through command and the firmware assumes the s_id
3001 	 * and the N_Port assumes the d_id and Bob's your uncle.
3002 	 */
3003 
3004 	/*
3005 	 * In N port 2 N port topology the FW provides a port database entry at
3006 	 * loop_id 0x7fe which allows us to acquire the Ports WWPN.
3007 	 */
3008 	tq->d_id.b.al_pa = 0;
3009 	tq->d_id.b.area = 0;
3010 	tq->d_id.b.domain = 0;
3011 	tq->loop_id = 0x7fe;
3012 
3013 	rval = ql_get_port_database(ha, tq, PDF_NONE);
3014 	if (rval == QL_SUCCESS || rval == QL_NOT_LOGGED_IN) {
3015 		ql_dev_id_list_t	*list;
3016 		uint32_t		list_size;
3017 		ql_mbx_data_t		mr;
3018 		port_id_t		d_id = {0, 0, 0, 0};
3019 		uint16_t		loop_id = 0;
3020 
3021 		cb_port_name = (uint8_t *)(CFG_IST(ha, CFG_CTRL_24258081) ?
3022 		    &ha->init_ctrl_blk.cb24.port_name[0] :
3023 		    &ha->init_ctrl_blk.cb.port_name[0]);
3024 
3025 		if ((ql_wwn_cmp(ha, (la_wwn_t *)&tq->port_name[0],
3026 		    (la_wwn_t *)cb_port_name) == 1)) {
3027 			EL(ha, "target port has N_Port login initiative\n");
3028 		} else {
3029 			EL(ha, "host port has N_Port login initiative\n");
3030 		}
3031 
3032 		/* Capture the N Ports WWPN */
3033 
3034 		bcopy((void *)&tq->port_name[0],
3035 		    (void *)&ha->n_port->port_name[0], 8);
3036 		bcopy((void *)&tq->node_name[0],
3037 		    (void *)&ha->n_port->node_name[0], 8);
3038 
3039 		/* Resolve an n_port_handle */
3040 		ha->n_port->n_port_handle = 0x7fe;
3041 
3042 		list_size = sizeof (ql_dev_id_list_t) * DEVICE_LIST_ENTRIES;
3043 		list = (ql_dev_id_list_t *)kmem_zalloc(list_size, KM_SLEEP);
3044 
3045 		if (list != NULL &&
3046 		    ql_get_id_list(ha, (caddr_t)list, list_size, &mr) ==
3047 		    QL_SUCCESS) {
3048 			if (mr.mb[1]) {
3049 				EL(ha, "id list entries = %d\n", mr.mb[1]);
3050 				for (index = 0; index < mr.mb[1]; index++) {
3051 					ql_dev_list(ha, list, index,
3052 					    &d_id, &loop_id);
3053 					ha->n_port->n_port_handle = loop_id;
3054 				}
3055 			} else {
3056 				for (index = 0; index <= LAST_LOCAL_LOOP_ID;
3057 				    index++) {
3058 					/* resuse tq */
3059 					tq->loop_id = (uint16_t)index;
3060 					rval = ql_get_port_database(ha, tq,
3061 					    PDF_NONE);
3062 					if (rval == QL_NOT_LOGGED_IN) {
3063 						if (tq->master_state ==
3064 						    PD_STATE_PLOGI_PENDING) {
3065 							ha->n_port->
3066 							    n_port_handle =
3067 							    tq->loop_id;
3068 							break;
3069 						}
3070 					} else {
3071 						ha->n_port->n_port_handle =
3072 						    tq->loop_id;
3073 						break;
3074