xref: /illumos-gate/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mbox.c (revision a3170057)

/*
 * CDDL HEADER START
 *
 * The contents of this file are subject to the terms of the
 * Common Development and Distribution License (the "License").
 * You may not use this file except in compliance with the License.
 *
 * You can obtain a copy of the license at
 * http://www.opensource.org/licenses/cddl1.txt.
 * See the License for the specific language governing permissions
 * and limitations under the License.
 *
 * When distributing Covered Code, include this CDDL HEADER in each
 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
 * If applicable, add the following below this CDDL HEADER, with the
 * fields enclosed by brackets "[]" replaced with your own identifying
 * information: Portions Copyright [yyyy] [name of copyright owner]
 *
 * CDDL HEADER END
 */

/*
 * Copyright (c) 2004-2012 Emulex. All rights reserved.
 * Use is subject to license terms.
 * Copyright 2020 RackTop Systems, Inc.
 */

#include <emlxs.h>

/* Required for EMLXS_CONTEXT in EMLXS_MSGF calls */
EMLXS_MSG_DEF(EMLXS_MBOX_C);


emlxs_table_t emlxs_mb_status_table[] = {
	{MBX_SUCCESS, "SUCCESS"},
	{MBX_FAILURE, "FAILURE"},
	{MBXERR_NUM_IOCBS, "NUM_IOCBS"},
	{MBXERR_IOCBS_EXCEEDED, "IOCBS_EXCEEDED"},
	{MBXERR_BAD_RING_NUMBER, "BAD_RING_NUMBER"},
	{MBXERR_MASK_ENTRIES_RANGE, "MASK_ENTRIES_RANGE"},
	{MBXERR_MASKS_EXCEEDED, "MASKS_EXCEEDED"},
	{MBXERR_BAD_PROFILE, "BAD_PROFILE"},
	{MBXERR_BAD_DEF_CLASS, "BAD_DEF_CLASS"},
	{MBXERR_BAD_MAX_RESPONDER, "BAD_MAX_RESPONDER"},
	{MBXERR_BAD_MAX_ORIGINATOR, "BAD_MAX_ORIGINATOR"},
	{MBXERR_RPI_REGISTERED, "RPI_REGISTERED"},
	{MBXERR_RPI_FULL, "RPI_FULL"},
	{MBXERR_NO_RESOURCES, "NO_RESOURCES"},
	{MBXERR_BAD_RCV_LENGTH, "BAD_RCV_LENGTH"},
	{MBXERR_DMA_ERROR, "DMA_ERROR"},
	{MBXERR_NOT_SUPPORTED, "NOT_SUPPORTED"},
	{MBXERR_UNSUPPORTED_FEATURE, "UNSUPPORTED_FEATURE"},
	{MBXERR_UNKNOWN_COMMAND, "UNKNOWN_COMMAND"},
	{MBXERR_BAD_IP_BIT, "BAD_IP_BIT"},
	{MBXERR_BAD_PCB_ALIGN, "BAD_PCB_ALIGN"},
	{MBXERR_BAD_HBQ_ID, "BAD_HBQ_ID"},
	{MBXERR_BAD_HBQ_STATE, "BAD_HBQ_STATE"},
	{MBXERR_BAD_HBQ_MASK_NUM, "BAD_HBQ_MASK_NUM"},
	{MBXERR_BAD_HBQ_MASK_SUBSET, "BAD_HBQ_MASK_SUBSET"},
	{MBXERR_HBQ_CREATE_FAIL, "HBQ_CREATE_FAIL"},
	{MBXERR_HBQ_EXISTING, "HBQ_EXISTING"},
	{MBXERR_HBQ_RSPRING_FULL, "HBQ_RSPRING_FULL"},
	{MBXERR_HBQ_DUP_MASK, "HBQ_DUP_MASK"},
	{MBXERR_HBQ_INVAL_GET_PTR, "HBQ_INVAL_GET_PTR"},
	{MBXERR_BAD_HBQ_SIZE, "BAD_HBQ_SIZE"},
	{MBXERR_BAD_HBQ_ORDER, "BAD_HBQ_ORDER"},
	{MBXERR_INVALID_ID, "INVALID_ID"},
	{MBXERR_INVALID_VFI, "INVALID_VFI"},
	{MBXERR_FLASH_WRITE_FAILED, "FLASH_WRITE_FAILED"},
	{MBXERR_INVALID_LINKSPEED, "INVALID_LINKSPEED"},
	{MBXERR_BAD_REDIRECT, "BAD_REDIRECT"},
	{MBXERR_RING_ALREADY_CONFIG, "RING_ALREADY_CONFIG"},
	{MBXERR_RING_INACTIVE, "RING_INACTIVE"},
	{MBXERR_RPI_INACTIVE, "RPI_INACTIVE"},
	{MBXERR_NO_ACTIVE_XRI, "NO_ACTIVE_XRI"},
	{MBXERR_XRI_NOT_ACTIVE, "XRI_NOT_ACTIVE"},
	{MBXERR_RPI_INUSE, "RPI_INUSE"},
	{MBXERR_NO_LINK_ATTENTION, "NO_LINK_ATTENTION"},
	{MBXERR_INVALID_SLI_MODE, "INVALID_SLI_MODE"},
	{MBXERR_INVALID_HOST_PTR, "INVALID_HOST_PTR"},
	{MBXERR_CANT_CFG_SLI_MODE, "CANT_CFG_SLI_MODE"},
	{MBXERR_BAD_OVERLAY, "BAD_OVERLAY"},
	{MBXERR_INVALID_FEAT_REQ, "INVALID_FEAT_REQ"},
	{MBXERR_CONFIG_CANT_COMPLETE, "CONFIG_CANT_COMPLETE"},
	{MBXERR_DID_ALREADY_REGISTERED, "DID_ALREADY_REGISTERED"},
	{MBXERR_DID_INCONSISTENT, "DID_INCONSISTENT"},
	{MBXERR_VPI_TOO_LARGE, "VPI_TOO_LARGE"},
	{MBXERR_STILL_ASSOCIATED, "STILL_ASSOCIATED"},
	{MBXERR_INVALID_VF_STATE, "INVALID_VF_STATE"},
	{MBXERR_VFI_ALREADY_REGISTERED, "VFI_ALREADY_REGISTERED"},
	{MBXERR_VFI_TOO_LARGE, "VFI_TOO_LARGE"},
	{MBXERR_LOAD_FW_FAILED, "LOAD_FW_FAILED"},
	{MBXERR_FIND_FW_FAILED, "FIND_FW_FAILED"},
};

emlxs_table_t emlxs_mb_cmd_table[] = {
	{MBX_SHUTDOWN, "SHUTDOWN"},
	{MBX_LOAD_SM, "LOAD_SM"},
	{MBX_READ_NV, "READ_NV"},
	{MBX_WRITE_NV, "WRITE_NV"},
	{MBX_RUN_BIU_DIAG, "RUN_BIU_DIAG"},
	{MBX_INIT_LINK, "INIT_LINK"},
	{MBX_DOWN_LINK, "DOWN_LINK"},
	{MBX_CONFIG_LINK, "CONFIG_LINK"},
	{MBX_PART_SLIM, "PART_SLIM"},
	{MBX_CONFIG_RING, "CONFIG_RING"},
	{MBX_RESET_RING, "RESET_RING"},
	{MBX_READ_CONFIG, "READ_CONFIG"},
	{MBX_READ_RCONFIG, "READ_RCONFIG"},
	{MBX_READ_SPARM, "READ_SPARM"},
	{MBX_READ_STATUS, "READ_STATUS"},
	{MBX_READ_RPI, "READ_RPI"},
	{MBX_READ_XRI, "READ_XRI"},
	{MBX_READ_REV, "READ_REV"},
	{MBX_READ_LNK_STAT, "READ_LNK_STAT"},
	{MBX_REG_LOGIN, "REG_LOGIN"},
	{MBX_UNREG_LOGIN, "UNREG_RPI"},
	{MBX_READ_LA, "READ_LA"},
	{MBX_CLEAR_LA, "CLEAR_LA"},
	{MBX_DUMP_MEMORY, "DUMP_MEMORY"},
	{MBX_DUMP_CONTEXT, "DUMP_CONTEXT"},
	{MBX_RUN_DIAGS, "RUN_DIAGS"},
	{MBX_RESTART, "RESTART"},
	{MBX_UPDATE_CFG, "UPDATE_CFG"},
	{MBX_DOWN_LOAD, "DOWN_LOAD"},
	{MBX_DEL_LD_ENTRY, "DEL_LD_ENTRY"},
	{MBX_RUN_PROGRAM, "RUN_PROGRAM"},
	{MBX_SET_MASK, "SET_MASK"},
	{MBX_SET_VARIABLE, "SET_VARIABLE"},
	{MBX_UNREG_D_ID, "UNREG_D_ID"},
	{MBX_KILL_BOARD, "KILL_BOARD"},
	{MBX_CONFIG_FARP, "CONFIG_FARP"},
	{MBX_LOAD_AREA, "LOAD_AREA"},
	{MBX_RUN_BIU_DIAG64, "RUN_BIU_DIAG64"},
	{MBX_CONFIG_PORT, "CONFIG_PORT"},
	{MBX_READ_SPARM64, "READ_SPARM64"},
	{MBX_READ_RPI64, "READ_RPI64"},
	{MBX_CONFIG_MSI, "CONFIG_MSI"},
	{MBX_CONFIG_MSIX, "CONFIG_MSIX"},
	{MBX_REG_LOGIN64, "REG_RPI"},
	{MBX_READ_LA64, "READ_LA64"},
	{MBX_FLASH_WR_ULA, "FLASH_WR_ULA"},
	{MBX_SET_DEBUG, "SET_DEBUG"},
	{MBX_GET_DEBUG, "GET_DEBUG"},
	{MBX_LOAD_EXP_ROM, "LOAD_EXP_ROM"},
	{MBX_BEACON, "BEACON"},
	{MBX_CONFIG_HBQ, "CONFIG_HBQ"},	/* SLI3 */
	{MBX_REG_VPI, "REG_VPI"},	/* NPIV */
	{MBX_UNREG_VPI, "UNREG_VPI"},	/* NPIV */
	{MBX_ASYNC_EVENT, "ASYNC_EVENT"},
	{MBX_HEARTBEAT, "HEARTBEAT"},
	{MBX_READ_EVENT_LOG_STATUS, "READ_EVENT_LOG_STATUS"},
	{MBX_READ_EVENT_LOG, "READ_EVENT_LOG"},
	{MBX_WRITE_EVENT_LOG, "WRITE_EVENT_LOG"},
	{MBX_NV_LOG, "NV_LOG"},
	{MBX_PORT_CAPABILITIES, "PORT_CAPABILITIES"},
	{MBX_IOV_CONTROL, "IOV_CONTROL"},
	{MBX_IOV_MBX, "IOV_MBX"},
	{MBX_SLI_CONFIG, "SLI_CONFIG"},
	{MBX_REQUEST_FEATURES, "REQUEST_FEATURES"},
	{MBX_RESUME_RPI, "RESUME_RPI"},
	{MBX_REG_VFI, "REG_VFI"},
	{MBX_REG_FCFI, "REG_FCFI"},
	{MBX_UNREG_VFI, "UNREG_VFI"},
	{MBX_UNREG_FCFI, "UNREG_FCFI"},
	{MBX_INIT_VFI, "INIT_VFI"},
	{MBX_INIT_VPI, "INIT_VPI"},
	{MBX_WRITE_VPARMS, "WRITE_VPARMS"},
	{MBX_ACCESS_VDATA, "ACCESS_VDATA"}
};	/* emlxs_mb_cmd_table */


emlxs_table_t emlxs_request_feature_table[] = {
	{SLI4_FEATURE_INHIBIT_AUTO_ABTS, "IAA "},	/* Bit 0 */
	{SLI4_FEATURE_NPIV, "NPIV "},			/* Bit 1 */
	{SLI4_FEATURE_DIF, "DIF "},			/* Bit 2 */
	{SLI4_FEATURE_VIRTUAL_FABRICS, "VF "},		/* Bit 3 */
	{SLI4_FEATURE_FCP_INITIATOR, "FCPI "},		/* Bit 4 */
	{SLI4_FEATURE_FCP_TARGET, "FCPT "},		/* Bit 5 */
	{SLI4_FEATURE_FCP_COMBO, "FCPC "},		/* Bit 6 */
	{SLI4_FEATURE_RSVD1, "RSVD1 "},			/* Bit 7 */
	{SLI4_FEATURE_RQD, "RQD "},			/* Bit 8 */
	{SLI4_FEATURE_INHIBIT_AUTO_ABTS_R, "IAAR "},	/* Bit 9 */
	{SLI4_FEATURE_HIGH_LOGIN_MODE, "HLM "},		/* Bit 10 */
	{SLI4_FEATURE_PERF_HINT, "PERFH "}		/* Bit 11 */
};	/* emlxs_request_feature_table */


extern char *
emlxs_mb_xlate_status(uint32_t status)
{
	static char	buffer[32];
	uint32_t	i;
	uint32_t	count;

	count = sizeof (emlxs_mb_status_table) / sizeof (emlxs_table_t);
	for (i = 0; i < count; i++) {
		if (status == emlxs_mb_status_table[i].code) {
			return (emlxs_mb_status_table[i].string);
		}
	}

	(void) snprintf(buffer, sizeof (buffer), "status=%x", status);
	return (buffer);

} /* emlxs_mb_xlate_status() */


/* SLI4 */
/*ARGSUSED*/
extern void
emlxs_mb_resetport(emlxs_hba_t *hba, MAILBOXQ *mbq)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
	mbq->nonembed = NULL;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	/*
	 * Signifies an embedded command
	 */
	mb4->un.varSLIConfig.be.embedded = 1;

	mb4->mbxCommand = MBX_SLI_CONFIG;
	mb4->mbxOwner = OWN_HOST;
	mb4->un.varSLIConfig.be.payload_length = IOCTL_HEADER_SZ;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
	    IOCTL_SUBSYSTEM_COMMON;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_RESET;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length = 0;

	return;

} /* emlxs_mb_resetport() */


/* SLI4 */
/*ARGSUSED*/
extern void
emlxs_mb_request_features(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t mask)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;

	hba->flag &= ~FC_NPIV_ENABLED;
	hba->sli.sli4.flag &= ~(EMLXS_SLI4_PHON | EMLXS_SLI4_PHWQ);

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
	mbq->nonembed = NULL;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	mb4->mbxCommand = MBX_REQUEST_FEATURES;
	mb4->mbxOwner = OWN_HOST;

	mb4->un.varReqFeatures.featuresRequested = mask;
	return;

} /* emlxs_mb_request_features() */


/* SLI4 */
/*ARGSUSED*/
extern void
emlxs_mb_noop(emlxs_hba_t *hba, MAILBOXQ *mbq)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
	IOCTL_COMMON_NOP *nop;

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
	mbq->nonembed = NULL;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	/*
	 * Signifies an embedded command
	 */
	mb4->un.varSLIConfig.be.embedded = 1;

	mb4->mbxCommand = MBX_SLI_CONFIG;
	mb4->mbxOwner = OWN_HOST;
	mb4->un.varSLIConfig.be.payload_length = sizeof (IOCTL_COMMON_NOP) +
	    IOCTL_HEADER_SZ;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
	    IOCTL_SUBSYSTEM_COMMON;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_NOP;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
	    sizeof (IOCTL_COMMON_NOP);
	nop = (IOCTL_COMMON_NOP *)&mb4->un.varSLIConfig.payload;
	nop->params.request.context = -1;

	return;

} /* emlxs_mb_noop() */


/* SLI4 */
/*ARGSUSED*/
extern int
emlxs_mbext_noop(emlxs_hba_t *hba, MAILBOXQ *mbq)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
	IOCTL_COMMON_NOP *nop;
	MATCHMAP *mp;
	mbox_req_hdr_t	*hdr_req;

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);

	if ((mp = (MATCHMAP *)emlxs_mem_get(hba, MEM_BUF)) == 0) {
		return (1);
	}
	/*
	 * Save address for completion
	 * Signifies a non-embedded command
	 */
	mb4->un.varSLIConfig.be.embedded = 0;
	mbq->nonembed = (void *)mp;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	mb4->mbxCommand = MBX_SLI_CONFIG;
	mb4->mbxOwner = OWN_HOST;

	hdr_req = (mbox_req_hdr_t *)mp->virt;
	hdr_req->subsystem = IOCTL_SUBSYSTEM_COMMON;
	hdr_req->opcode = COMMON_OPCODE_NOP;
	hdr_req->timeout = 0;
	hdr_req->req_length = sizeof (IOCTL_COMMON_NOP);
	nop = (IOCTL_COMMON_NOP *)(hdr_req + 1);
	nop->params.request.context = -1;

	return (0);

} /* emlxs_mbext_noop() */


/* SLI4 */
/*ARGSUSED*/
extern void
emlxs_mb_eq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
	IOCTL_COMMON_EQ_CREATE *qp;
	uint64_t	addr;

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
	mbq->nonembed = NULL;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	/*
	 * Signifies an embedded command
	 */
	mb4->un.varSLIConfig.be.embedded = 1;

	mb4->mbxCommand = MBX_SLI_CONFIG;
	mb4->mbxOwner = OWN_HOST;
	mb4->un.varSLIConfig.be.payload_length =
	    sizeof (IOCTL_COMMON_EQ_CREATE) + IOCTL_HEADER_SZ;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
	    IOCTL_SUBSYSTEM_COMMON;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = COMMON_OPCODE_EQ_CREATE;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
	    sizeof (IOCTL_COMMON_EQ_CREATE);
	mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;

	qp = (IOCTL_COMMON_EQ_CREATE *)&mb4->un.varSLIConfig.payload;

	/* 1024 * 4 bytes = 4K */
	qp->params.request.EQContext.Count = EQ_ELEMENT_COUNT_1024;
	qp->params.request.EQContext.Valid = 1;
	qp->params.request.EQContext.DelayMult = EQ_DELAY_MULT;

	addr = hba->sli.sli4.eq[num].addr.phys;
	qp->params.request.NumPages = 1;
	qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
	qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);

	return;

} /* emlxs_mb_eq_create() */


/* SLI4 */
/*ARGSUSED*/
extern void
emlxs_mb_cq_create(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t num)
{
	MAILBOX4 *mb4 = (MAILBOX4 *)mbq;
	IOCTL_COMMON_CQ_CREATE *qp;
	IOCTL_COMMON_CQ_CREATE_V2 *qp2;
	uint64_t	addr;
	uint32_t	i;

	bzero((void *) mb4, MAILBOX_CMD_SLI4_BSIZE);
	mbq->nonembed = NULL;
	mbq->mbox_cmpl = NULL; /* no cmpl needed */
	mbq->port = (void *)&PPORT;

	/*
	 * Signifies an embedded command
	 */
	mb4->un.varSLIConfig.be.embedded = 1;

	mb4->mbxCommand = MBX_SLI_CONFIG;
	mb4->mbxOwner = OWN_HOST;

	switch (hba->sli.sli4.param.CQV) {
	case 0:
		mb4->un.varSLIConfig.be.payload_length =
		    sizeof (IOCTL_COMMON_CQ_CREATE) + IOCTL_HEADER_SZ;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
		    IOCTL_SUBSYSTEM_COMMON;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
		    COMMON_OPCODE_CQ_CREATE;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
		    sizeof (IOCTL_COMMON_CQ_CREATE);
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.version = 0;

		qp = (IOCTL_COMMON_CQ_CREATE *)
		    &mb4->un.varSLIConfig.payload;

		/* 256 * 16 bytes = 4K */
		qp->params.request.CQContext.Count = CQ_ELEMENT_COUNT_256;
		qp->params.request.CQContext.EQId =
		    (uint8_t)hba->sli.sli4.cq[num].eqid;
		qp->params.request.CQContext.Valid = 1;
		qp->params.request.CQContext.Eventable = 1;
		qp->params.request.CQContext.NoDelay = 0;
		qp->params.request.CQContext.CoalesceWM = 0;

		addr = hba->sli.sli4.cq[num].addr.phys;
		qp->params.request.NumPages = 1;
		qp->params.request.Pages[0].addrLow = PADDR_LO(addr);
		qp->params.request.Pages[0].addrHigh = PADDR_HI(addr);

		break;

	case 2:
	default:
		mb4->un.varSLIConfig.be.payload_length =
		    sizeof (IOCTL_COMMON_CQ_CREATE_V2) + IOCTL_HEADER_SZ;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem =
		    IOCTL_SUBSYSTEM_COMMON;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode =
		    COMMON_OPCODE_CQ_CREATE;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.timeout = 0;
		mb4->un.varSLIConfig.be.un_hdr.hdr_req.req_length =
		    sizeof (IOCTL_COMMON_CQ_CREATE_V2);