16f443ebcSRyan Zezeski /* 26f443ebcSRyan Zezeski * This file and its contents are supplied under the terms of the 36f443ebcSRyan Zezeski * Common Development and Distribution License ("CDDL"), version 1.0. 46f443ebcSRyan Zezeski * You may only use this file in accordance with the terms of version 56f443ebcSRyan Zezeski * 1.0 of the CDDL. 66f443ebcSRyan Zezeski * 76f443ebcSRyan Zezeski * A full copy of the text of the CDDL should have accompanied this 86f443ebcSRyan Zezeski * source. A copy of the CDDL is also available via the Internet at 96f443ebcSRyan Zezeski * http://www.illumos.org/license/CDDL. 106f443ebcSRyan Zezeski */ 116f443ebcSRyan Zezeski 126f443ebcSRyan Zezeski /* 13eebd18daSAndy Fiddaman * Copyright 2024 Oxide Computer Company 146f443ebcSRyan Zezeski */ 156f443ebcSRyan Zezeski 166f443ebcSRyan Zezeski /* 176f443ebcSRyan Zezeski * This file declares all constants and structures dealing with the 186f443ebcSRyan Zezeski * physical ENA device. It is based on the ena_com code of the public 196f443ebcSRyan Zezeski * Linux and FreeBSD drivers. While this file is based on the common 206f443ebcSRyan Zezeski * code it doesn't share the same type names. Where it is useful, a 216f443ebcSRyan Zezeski * "common" reference is added to include the name of the type as 226f443ebcSRyan Zezeski * defined in the common code. 236f443ebcSRyan Zezeski * 246f443ebcSRyan Zezeski * The Linux driver defines enq_admin_aq_entry as the top-level type 256f443ebcSRyan Zezeski * for admin command descriptors. From this type you can access the 266f443ebcSRyan Zezeski * common bits shared by every descriptor (ena_admin_aq_common_desc) 276f443ebcSRyan Zezeski * as well as the control buffer (ena_admin_ctrl_buff_info) which is 286f443ebcSRyan Zezeski * present for _some_ commands. Other than that, this top-level type 296f443ebcSRyan Zezeski * treats the rest of the data as an opaque array of unsigned 32-bit 306f443ebcSRyan Zezeski * integers. Then, for each individual command, the Linux driver 316f443ebcSRyan Zezeski * defines a dedicated type, each of which contains the following: 326f443ebcSRyan Zezeski * 336f443ebcSRyan Zezeski * 1. The common descriptor: ena_admin_aq_common_desc. 346f443ebcSRyan Zezeski * 356f443ebcSRyan Zezeski * 2. The optional control buffer desc: ena_admin_ctrl_buff_info. 366f443ebcSRyan Zezeski * 376f443ebcSRyan Zezeski * 3. The command-specific data. 386f443ebcSRyan Zezeski * 396f443ebcSRyan Zezeski * 4. Optional padding to make sure all commands are 64 bytes in size. 406f443ebcSRyan Zezeski * 416f443ebcSRyan Zezeski * Furthermore, there may be further common types for commands which 426f443ebcSRyan Zezeski * are made up of several sub-commands, e.g. the get/set feature 436f443ebcSRyan Zezeski * commands. 446f443ebcSRyan Zezeski * 456f443ebcSRyan Zezeski * Finally, when a command is passed to the common function for 466f443ebcSRyan Zezeski * executing commands (ena_com_execute_admin_command()), it is cast as 476f443ebcSRyan Zezeski * a pointer to the top-level type: ena_admin_aq_entry. 486f443ebcSRyan Zezeski * 496f443ebcSRyan Zezeski * This works for the Linux driver just fine, but it causes lots of 506f443ebcSRyan Zezeski * repetition in the structure definitions and also means there is no 516f443ebcSRyan Zezeski * easy way to determine all valid commands. This ENA driver has 526f443ebcSRyan Zezeski * turned the Linux approach inside out -- the top-level type is a 536f443ebcSRyan Zezeski * union of all possible commands: enahw_cmd_desc_t. Each command may 546f443ebcSRyan Zezeski * then further sub-type via unions to represent its sub-commands. 556f443ebcSRyan Zezeski * This same treatment was given to the response descriptor: 566f443ebcSRyan Zezeski * enahw_resp_desc_t. 576f443ebcSRyan Zezeski * 586f443ebcSRyan Zezeski * What is the point of knowing all this? Well, when referencing the 596f443ebcSRyan Zezeski * common type in the comment above the enahw_ type, you need to keep 606f443ebcSRyan Zezeski * in mind that the Linux/common type will include all the common 616f443ebcSRyan Zezeski * descriptor bits, whereas these types do not. 626f443ebcSRyan Zezeski * 636f443ebcSRyan Zezeski * The common code DOES NOT pack any of these structures, and thus 646f443ebcSRyan Zezeski * neither do we. That means these structures all rely on natural 656f443ebcSRyan Zezeski * compiler alignment, just as the common code does. In ena.c you will 666f443ebcSRyan Zezeski * find CTASSERTs for many of these structures, to verify they are of 676f443ebcSRyan Zezeski * the expected size. 686f443ebcSRyan Zezeski */ 696f443ebcSRyan Zezeski 706f443ebcSRyan Zezeski #ifndef _ENA_HW_H 716f443ebcSRyan Zezeski #define _ENA_HW_H 726f443ebcSRyan Zezeski 736f443ebcSRyan Zezeski #include <sys/ddi.h> 746f443ebcSRyan Zezeski #include <sys/sunddi.h> 756f443ebcSRyan Zezeski #include <sys/types.h> 766f443ebcSRyan Zezeski #include <sys/debug.h> 776f443ebcSRyan Zezeski #include <sys/ethernet.h> 786f443ebcSRyan Zezeski 796f443ebcSRyan Zezeski /* 806f443ebcSRyan Zezeski * The common code sets the upper limit of I/O queues to 128. In this 816f443ebcSRyan Zezeski * case a "queue" is a SQ+CQ pair that forms a logical queue or ring 826f443ebcSRyan Zezeski * for sending or receiving packets. Thus, at maximum, we may expect 836f443ebcSRyan Zezeski * 128 Tx rings, and 128 Rx rings; though, practically speaking, the 846f443ebcSRyan Zezeski * number of rings will often be limited by number of CPUs or 856f443ebcSRyan Zezeski * available interrupts. 866f443ebcSRyan Zezeski * 876f443ebcSRyan Zezeski * common: ENA_MAX_NUM_IO_QUEUES 886f443ebcSRyan Zezeski */ 896f443ebcSRyan Zezeski #define ENAHW_MAX_NUM_IO_QUEUES 128 906f443ebcSRyan Zezeski 916f443ebcSRyan Zezeski /* 926f443ebcSRyan Zezeski * Generate a 32-bit bitmask where the bits between high (inclusive) 936f443ebcSRyan Zezeski * and low (inclusive) are set to 1. 946f443ebcSRyan Zezeski */ 956f443ebcSRyan Zezeski #define GENMASK(h, l) (((~0U) - (1U << (l)) + 1) & (~0U >> (32 - 1 - (h)))) 966f443ebcSRyan Zezeski 976f443ebcSRyan Zezeski /* 986f443ebcSRyan Zezeski * Generate a 64-bit bitmask where bit b is set to 1. 996f443ebcSRyan Zezeski */ 1006f443ebcSRyan Zezeski #define BIT(b) (1UL << (b)) 1016f443ebcSRyan Zezeski 1026f443ebcSRyan Zezeski #define ENAHW_DMA_ADMINQ_ALIGNMENT 8 1036f443ebcSRyan Zezeski 1046f443ebcSRyan Zezeski #define ENAHW_ADMIN_CQ_DESC_BUF_ALIGNMENT 8 1056f443ebcSRyan Zezeski #define ENAHW_ADMIN_SQ_DESC_BUF_ALIGNMENT 8 1066f443ebcSRyan Zezeski #define ENAHW_AENQ_DESC_BUF_ALIGNMENT 8 1076f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_ALIGNMENT 8 1086f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_ALLOC_SZ 4096 1096f443ebcSRyan Zezeski #define ENAHW_IO_CQ_DESC_BUF_ALIGNMENT 4096 1106f443ebcSRyan Zezeski #define ENAHW_IO_SQ_DESC_BUF_ALIGNMENT 8 1116f443ebcSRyan Zezeski 1126f443ebcSRyan Zezeski /* 1136f443ebcSRyan Zezeski * BAR0 register offsets. 1146f443ebcSRyan Zezeski * 1156f443ebcSRyan Zezeski * Any register not defined in the common code was marked as a gap, 116eebd18daSAndy Fiddaman * using the hex address of the register as suffix to make it clear 117eebd18daSAndy Fiddaman * where the gaps are. 1186f443ebcSRyan Zezeski */ 1196f443ebcSRyan Zezeski #define ENAHW_REG_VERSION 0x0 1206f443ebcSRyan Zezeski #define ENAHW_REG_CONTROLLER_VERSION 0x4 1216f443ebcSRyan Zezeski #define ENAHW_REG_CAPS 0x8 1226f443ebcSRyan Zezeski #define ENAHW_REG_CAPS_EXT 0xc 1236f443ebcSRyan Zezeski #define ENAHW_REG_ASQ_BASE_LO 0x10 1246f443ebcSRyan Zezeski #define ENAHW_REG_ASQ_BASE_HI 0x14 1256f443ebcSRyan Zezeski #define ENAHW_REG_ASQ_CAPS 0x18 1266f443ebcSRyan Zezeski #define ENAHW_REG_GAP_1C 0x1c 1276f443ebcSRyan Zezeski #define ENAHW_REG_ACQ_BASE_LO 0x20 1286f443ebcSRyan Zezeski #define ENAHW_REG_ACQ_BASE_HI 0x24 1296f443ebcSRyan Zezeski #define ENAHW_REG_ACQ_CAPS 0x28 1306f443ebcSRyan Zezeski #define ENAHW_REG_ASQ_DB 0x2c 1316f443ebcSRyan Zezeski #define ENAHW_REG_ACQ_TAIL 0x30 1326f443ebcSRyan Zezeski #define ENAHW_REG_AENQ_CAPS 0x34 1336f443ebcSRyan Zezeski #define ENAHW_REG_AENQ_BASE_LO 0x38 1346f443ebcSRyan Zezeski #define ENAHW_REG_AENQ_BASE_HI 0x3c 1356f443ebcSRyan Zezeski #define ENAHW_REG_AENQ_HEAD_DB 0x40 1366f443ebcSRyan Zezeski #define ENAHW_REG_AENQ_TAIL 0x44 1376f443ebcSRyan Zezeski #define ENAHW_REG_GAP_48 0x48 1386f443ebcSRyan Zezeski #define ENAHW_REG_INTERRUPT_MASK 0x4c 1396f443ebcSRyan Zezeski #define ENAHW_REG_GAP_50 0x50 1406f443ebcSRyan Zezeski #define ENAHW_REG_DEV_CTL 0x54 1416f443ebcSRyan Zezeski #define ENAHW_REG_DEV_STS 0x58 1426f443ebcSRyan Zezeski #define ENAHW_REG_MMIO_REG_READ 0x5c 1436f443ebcSRyan Zezeski #define ENAHW_REG_MMIO_RESP_LO 0x60 1446f443ebcSRyan Zezeski #define ENAHW_REG_MMIO_RESP_HI 0x64 1456f443ebcSRyan Zezeski #define ENAHW_REG_RSS_IND_ENTRY_UPDATE 0x68 1466f443ebcSRyan Zezeski #define ENAHW_NUM_REGS ((ENAHW_REG_RSS_IND_ENTRY_UPDATE / 4) + 1) 1476f443ebcSRyan Zezeski 1486f443ebcSRyan Zezeski /* 1496f443ebcSRyan Zezeski * Device Version (Register 0x0) 1506f443ebcSRyan Zezeski */ 1516f443ebcSRyan Zezeski #define ENAHW_DEV_MINOR_VSN_MASK 0xff 1526f443ebcSRyan Zezeski #define ENAHW_DEV_MAJOR_VSN_SHIFT 8 1536f443ebcSRyan Zezeski #define ENAHW_DEV_MAJOR_VSN_MASK 0xff00 1546f443ebcSRyan Zezeski 1556f443ebcSRyan Zezeski #define ENAHW_DEV_MAJOR_VSN(vsn) \ 1566f443ebcSRyan Zezeski (((vsn) & ENAHW_DEV_MAJOR_VSN_MASK) >> ENAHW_DEV_MAJOR_VSN_SHIFT) 1576f443ebcSRyan Zezeski #define ENAHW_DEV_MINOR_VSN(vsn) \ 1586f443ebcSRyan Zezeski ((vsn) & ENAHW_DEV_MINOR_VSN_MASK) 1596f443ebcSRyan Zezeski 1606f443ebcSRyan Zezeski /* 1616f443ebcSRyan Zezeski * Controller Version (Register 0x4) 1626f443ebcSRyan Zezeski */ 1636f443ebcSRyan Zezeski #define ENAHW_CTRL_SUBMINOR_VSN_MASK 0xff 1646f443ebcSRyan Zezeski #define ENAHW_CTRL_MINOR_VSN_SHIFT 8 1656f443ebcSRyan Zezeski #define ENAHW_CTRL_MINOR_VSN_MASK 0xff00 1666f443ebcSRyan Zezeski #define ENAHW_CTRL_MAJOR_VSN_SHIFT 16 1676f443ebcSRyan Zezeski #define ENAHW_CTRL_MAJOR_VSN_MASK 0xff0000 1686f443ebcSRyan Zezeski #define ENAHW_CTRL_IMPL_ID_SHIFT 24 1696f443ebcSRyan Zezeski #define ENAHW_CTRL_IMPL_ID_MASK 0xff000000 1706f443ebcSRyan Zezeski 1716f443ebcSRyan Zezeski #define ENAHW_CTRL_MAJOR_VSN(vsn) \ 1726f443ebcSRyan Zezeski (((vsn) & ENAHW_CTRL_MAJOR_VSN_MASK) >> ENAHW_CTRL_MAJOR_VSN_SHIFT) 1736f443ebcSRyan Zezeski #define ENAHW_CTRL_MINOR_VSN(vsn) \ 1746f443ebcSRyan Zezeski (((vsn) & ENAHW_CTRL_MINOR_VSN_MASK) >> ENAHW_CTRL_MINOR_VSN_SHIFT) 1756f443ebcSRyan Zezeski #define ENAHW_CTRL_SUBMINOR_VSN(vsn) \ 1766f443ebcSRyan Zezeski ((vsn) & ENAHW_CTRL_SUBMINOR_VSN_MASK) 1776f443ebcSRyan Zezeski #define ENAHW_CTRL_IMPL_ID(vsn) \ 1786f443ebcSRyan Zezeski (((vsn) & ENAHW_CTRL_IMPL_ID_MASK) >> ENAHW_CTRL_IMPL_ID_SHIFT) 1796f443ebcSRyan Zezeski 1806f443ebcSRyan Zezeski /* 1816f443ebcSRyan Zezeski * Device Caps (Register 0x8) 1826f443ebcSRyan Zezeski */ 1836f443ebcSRyan Zezeski #define ENAHW_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 1846f443ebcSRyan Zezeski #define ENAHW_CAPS_RESET_TIMEOUT_SHIFT 1 1856f443ebcSRyan Zezeski #define ENAHW_CAPS_RESET_TIMEOUT_MASK 0x3e 1866f443ebcSRyan Zezeski #define ENAHW_CAPS_RESET_TIMEOUT(v) \ 1876f443ebcSRyan Zezeski (((v) & ENAHW_CAPS_RESET_TIMEOUT_MASK) >> \ 1886f443ebcSRyan Zezeski ENAHW_CAPS_RESET_TIMEOUT_SHIFT) 1896f443ebcSRyan Zezeski #define ENAHW_CAPS_DMA_ADDR_WIDTH_SHIFT 8 1906f443ebcSRyan Zezeski #define ENAHW_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 1916f443ebcSRyan Zezeski #define ENAHW_CAPS_DMA_ADDR_WIDTH(v) \ 1926f443ebcSRyan Zezeski (((v) & ENAHW_CAPS_DMA_ADDR_WIDTH_MASK) >> \ 1936f443ebcSRyan Zezeski ENAHW_CAPS_DMA_ADDR_WIDTH_SHIFT) 1946f443ebcSRyan Zezeski #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT_SHIFT 16 1956f443ebcSRyan Zezeski #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT_MASK 0xf0000 1966f443ebcSRyan Zezeski #define ENAHW_CAPS_ADMIN_CMD_TIMEOUT(v) \ 1976f443ebcSRyan Zezeski (((v) & ENAHW_CAPS_ADMIN_CMD_TIMEOUT_MASK) >> \ 1986f443ebcSRyan Zezeski ENAHW_CAPS_ADMIN_CMD_TIMEOUT_SHIFT) 1996f443ebcSRyan Zezeski 200*c46e4de3SAndy Fiddaman typedef enum enahw_reset_reason_types { 2016f443ebcSRyan Zezeski ENAHW_RESET_NORMAL = 0, 2026f443ebcSRyan Zezeski ENAHW_RESET_KEEP_ALIVE_TO = 1, 2036f443ebcSRyan Zezeski ENAHW_RESET_ADMIN_TO = 2, 2046f443ebcSRyan Zezeski ENAHW_RESET_MISS_TX_CMPL = 3, 2056f443ebcSRyan Zezeski ENAHW_RESET_INV_RX_REQ_ID = 4, 2066f443ebcSRyan Zezeski ENAHW_RESET_INV_TX_REQ_ID = 5, 2076f443ebcSRyan Zezeski ENAHW_RESET_TOO_MANY_RX_DESCS = 6, 2086f443ebcSRyan Zezeski ENAHW_RESET_INIT_ERR = 7, 2096f443ebcSRyan Zezeski ENAHW_RESET_DRIVER_INVALID_STATE = 8, 2106f443ebcSRyan Zezeski ENAHW_RESET_OS_TRIGGER = 9, 2116f443ebcSRyan Zezeski ENAHW_RESET_OS_NETDEV_WD = 10, 2126f443ebcSRyan Zezeski ENAHW_RESET_SHUTDOWN = 11, 2136f443ebcSRyan Zezeski ENAHW_RESET_USER_TRIGGER = 12, 2146f443ebcSRyan Zezeski ENAHW_RESET_GENERIC = 13, 2156f443ebcSRyan Zezeski ENAHW_RESET_MISS_INTERRUPT = 14, 216*c46e4de3SAndy Fiddaman ENAHW_RESET_SUSPECTED_POLL_STARVATION = 15, 217*c46e4de3SAndy Fiddaman ENAHW_RESET_RX_DESCRIPTOR_MALFORMED = 16, 218*c46e4de3SAndy Fiddaman ENAHW_RESET_TX_DESCRIPTOR_MALFORMED = 17, 219*c46e4de3SAndy Fiddaman ENAHW_RESET_MISSING_ADMIN_INTERRUPT = 18, 220*c46e4de3SAndy Fiddaman ENAHW_RESET_DEVICE_REQUEST = 19, 2216f443ebcSRyan Zezeski ENAHW_RESET_LAST, 222*c46e4de3SAndy Fiddaman } enahw_reset_reason_t; 223*c46e4de3SAndy Fiddaman 224*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_LSB_SHIFT 0 225*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_LSB_MASK 0xf 226*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_MSB_SHIFT 4 227*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_MSB_MASK 0xf0 228*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_LSB(v) \ 229*c46e4de3SAndy Fiddaman (((v) & ENAHW_RESET_REASON_LSB_MASK) >> ENAHW_RESET_REASON_LSB_SHIFT) 230*c46e4de3SAndy Fiddaman #define ENAHW_RESET_REASON_MSB(v) \ 231*c46e4de3SAndy Fiddaman (((v) & ENAHW_RESET_REASON_MSB_MASK) >> ENAHW_RESET_REASON_MSB_SHIFT) 2326f443ebcSRyan Zezeski 2336f443ebcSRyan Zezeski /* 2346f443ebcSRyan Zezeski * Admin Submission Queue Caps (Register 0x18) 2356f443ebcSRyan Zezeski */ 2366f443ebcSRyan Zezeski #define ENAHW_ASQ_CAPS_DEPTH_MASK 0xffff 2376f443ebcSRyan Zezeski #define ENAHW_ASQ_CAPS_ENTRY_SIZE_SHIFT 16 2386f443ebcSRyan Zezeski #define ENAHW_ASQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 2396f443ebcSRyan Zezeski 2406f443ebcSRyan Zezeski #define ENAHW_ASQ_CAPS_DEPTH(x) ((x) & ENAHW_ASQ_CAPS_DEPTH_MASK) 2416f443ebcSRyan Zezeski 2426f443ebcSRyan Zezeski #define ENAHW_ASQ_CAPS_ENTRY_SIZE(x) \ 2436f443ebcSRyan Zezeski (((x) << ENAHW_ASQ_CAPS_ENTRY_SIZE_SHIFT) & \ 2446f443ebcSRyan Zezeski ENAHW_ASQ_CAPS_ENTRY_SIZE_MASK) 2456f443ebcSRyan Zezeski 2466f443ebcSRyan Zezeski /* 2476f443ebcSRyan Zezeski * Admin Completion Queue Caps (Register 0x28) 2486f443ebcSRyan Zezeski */ 2496f443ebcSRyan Zezeski #define ENAHW_ACQ_CAPS_DEPTH_MASK 0xffff 2506f443ebcSRyan Zezeski #define ENAHW_ACQ_CAPS_ENTRY_SIZE_SHIFT 16 2516f443ebcSRyan Zezeski #define ENAHW_ACQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 2526f443ebcSRyan Zezeski 2536f443ebcSRyan Zezeski #define ENAHW_ACQ_CAPS_DEPTH(x) ((x) & ENAHW_ACQ_CAPS_DEPTH_MASK) 2546f443ebcSRyan Zezeski 2556f443ebcSRyan Zezeski #define ENAHW_ACQ_CAPS_ENTRY_SIZE(x) \ 2566f443ebcSRyan Zezeski (((x) << ENAHW_ACQ_CAPS_ENTRY_SIZE_SHIFT) & \ 2576f443ebcSRyan Zezeski ENAHW_ACQ_CAPS_ENTRY_SIZE_MASK) 2586f443ebcSRyan Zezeski 2596f443ebcSRyan Zezeski /* 2606f443ebcSRyan Zezeski * Asynchronous Event Notification Queue Caps (Register 0x34) 2616f443ebcSRyan Zezeski */ 2626f443ebcSRyan Zezeski #define ENAHW_AENQ_CAPS_DEPTH_MASK 0xffff 2636f443ebcSRyan Zezeski #define ENAHW_AENQ_CAPS_ENTRY_SIZE_SHIFT 16 2646f443ebcSRyan Zezeski #define ENAHW_AENQ_CAPS_ENTRY_SIZE_MASK 0xffff0000 2656f443ebcSRyan Zezeski 2666f443ebcSRyan Zezeski #define ENAHW_AENQ_CAPS_DEPTH(x) ((x) & ENAHW_AENQ_CAPS_DEPTH_MASK) 2676f443ebcSRyan Zezeski 2686f443ebcSRyan Zezeski #define ENAHW_AENQ_CAPS_ENTRY_SIZE(x) \ 2696f443ebcSRyan Zezeski (((x) << ENAHW_AENQ_CAPS_ENTRY_SIZE_SHIFT) & \ 2706f443ebcSRyan Zezeski ENAHW_AENQ_CAPS_ENTRY_SIZE_MASK) 2716f443ebcSRyan Zezeski 2726f443ebcSRyan Zezeski /* 2736f443ebcSRyan Zezeski * Interrupt Mask (Register 0x4c) 2746f443ebcSRyan Zezeski */ 2756f443ebcSRyan Zezeski #define ENAHW_INTR_UNMASK 0x0 2766f443ebcSRyan Zezeski #define ENAHW_INTR_MASK 0x1 2776f443ebcSRyan Zezeski 2786f443ebcSRyan Zezeski /* 2796f443ebcSRyan Zezeski * Device Control (Register 0x54) 2806f443ebcSRyan Zezeski */ 2816f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_DEV_RESET_MASK 0x1 2826f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_AQ_RESTART_SHIFT 1 2836f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_AQ_RESTART_MASK 0x2 2846f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_QUIESCENT_SHIFT 2 2856f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_QUIESCENT_MASK 0x4 2866f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_IO_RESUME_SHIFT 3 2876f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_IO_RESUME_MASK 0x8 288*c46e4de3SAndy Fiddaman #define ENAHW_DEV_CTL_RESET_REASON_EXT_SHIFT 24 289*c46e4de3SAndy Fiddaman #define ENAHW_DEV_CTL_RESET_REASON_EXT_MASK 0xf000000 2906f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_RESET_REASON_SHIFT 28 2916f443ebcSRyan Zezeski #define ENAHW_DEV_CTL_RESET_REASON_MASK 0xf0000000 2926f443ebcSRyan Zezeski 2936f443ebcSRyan Zezeski /* 2946f443ebcSRyan Zezeski * Device Status (Register 0x58) 2956f443ebcSRyan Zezeski */ 2966f443ebcSRyan Zezeski #define ENAHW_DEV_STS_READY_MASK 0x1 2976f443ebcSRyan Zezeski #define ENAHW_DEV_STS_AQ_RESTART_IN_PROGRESS_SHIFT 1 2986f443ebcSRyan Zezeski #define ENAHW_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 2996f443ebcSRyan Zezeski #define ENAHW_DEV_STS_AQ_RESTART_FINISHED_SHIFT 2 3006f443ebcSRyan Zezeski #define ENAHW_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 3016f443ebcSRyan Zezeski #define ENAHW_DEV_STS_RESET_IN_PROGRESS_SHIFT 3 3026f443ebcSRyan Zezeski #define ENAHW_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 3036f443ebcSRyan Zezeski #define ENAHW_DEV_STS_RESET_FINISHED_SHIFT 4 3046f443ebcSRyan Zezeski #define ENAHW_DEV_STS_RESET_FINISHED_MASK 0x10 3056f443ebcSRyan Zezeski #define ENAHW_DEV_STS_FATAL_ERROR_SHIFT 5 3066f443ebcSRyan Zezeski #define ENAHW_DEV_STS_FATAL_ERROR_MASK 0x20 3076f443ebcSRyan Zezeski #define ENAHW_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_SHIFT 6 3086f443ebcSRyan Zezeski #define ENAHW_DEV_STS_QUIESCENT_STATE_IN_PROGRESS_MASK 0x40 3096f443ebcSRyan Zezeski #define ENAHW_DEV_STS_QUIESCENT_STATE_ACHIEVED_SHIFT 7 3106f443ebcSRyan Zezeski #define ENAHW_DEV_STS_QUIESCENT_STATE_ACHIEVED_MASK 0x80 3116f443ebcSRyan Zezeski 3126f443ebcSRyan Zezeski /* common: ena_admin_aenq_common_desc */ 3136f443ebcSRyan Zezeski typedef struct enahw_aenq_desc { 3146f443ebcSRyan Zezeski uint16_t ead_group; 3156f443ebcSRyan Zezeski uint16_t ead_syndrome; 3166f443ebcSRyan Zezeski uint8_t ead_flags; 3176f443ebcSRyan Zezeski uint8_t ead_rsvd1[3]; 3186f443ebcSRyan Zezeski uint32_t ead_ts_low; 3196f443ebcSRyan Zezeski uint32_t ead_ts_high; 3206f443ebcSRyan Zezeski 3216f443ebcSRyan Zezeski union { 3226f443ebcSRyan Zezeski uint32_t raw[12]; 3236f443ebcSRyan Zezeski 3246f443ebcSRyan Zezeski struct { 3256f443ebcSRyan Zezeski uint32_t flags; 3266f443ebcSRyan Zezeski } link_change; 3276f443ebcSRyan Zezeski 3286f443ebcSRyan Zezeski struct { 3296f443ebcSRyan Zezeski uint32_t rx_drops_low; 3306f443ebcSRyan Zezeski uint32_t rx_drops_high; 3316f443ebcSRyan Zezeski uint32_t tx_drops_low; 3326f443ebcSRyan Zezeski uint32_t tx_drops_high; 333*c46e4de3SAndy Fiddaman uint32_t rx_overruns_low; 334*c46e4de3SAndy Fiddaman uint32_t rx_overruns_high; 3356f443ebcSRyan Zezeski } keep_alive; 3366f443ebcSRyan Zezeski } ead_payload; 3376f443ebcSRyan Zezeski } enahw_aenq_desc_t; 3386f443ebcSRyan Zezeski 3396f443ebcSRyan Zezeski #define ENAHW_AENQ_DESC_PHASE_MASK BIT(0) 3406f443ebcSRyan Zezeski 3416f443ebcSRyan Zezeski #define ENAHW_AENQ_DESC_PHASE(desc) \ 3426f443ebcSRyan Zezeski ((desc)->ead_flags & ENAHW_AENQ_DESC_PHASE_MASK) 3436f443ebcSRyan Zezeski 3446f443ebcSRyan Zezeski #define ENAHW_AENQ_LINK_CHANGE_LINK_STATUS_MASK BIT(0) 3456f443ebcSRyan Zezeski 3466f443ebcSRyan Zezeski /* 3476f443ebcSRyan Zezeski * Asynchronous Event Notification Queue groups. 3486f443ebcSRyan Zezeski * 3496f443ebcSRyan Zezeski * Note: These values represent the bit position of each feature as 3506f443ebcSRyan Zezeski * returned by ENAHW_FEAT_AENQ_CONFIG. We encode them this way so that 3516f443ebcSRyan Zezeski * they can double as an index into the AENQ handlers array. 3526f443ebcSRyan Zezeski * 3536f443ebcSRyan Zezeski * common: ena_admin_aenq_group 3546f443ebcSRyan Zezeski */ 3556f443ebcSRyan Zezeski typedef enum enahw_aenq_groups { 3566f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_LINK_CHANGE = 0, 3576f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_FATAL_ERROR = 1, 3586f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_WARNING = 2, 3596f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_NOTIFICATION = 3, 3606f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_KEEP_ALIVE = 4, 3616f443ebcSRyan Zezeski ENAHW_AENQ_GROUP_REFRESH_CAPABILITIES = 5, 362*c46e4de3SAndy Fiddaman ENAHW_AENQ_GROUP_CONF_NOTIFICATIONS = 6, 363*c46e4de3SAndy Fiddaman ENAHW_AENQ_GROUP_DEVICE_REQUEST_RESET = 7, 364*c46e4de3SAndy Fiddaman ENAHW_AENQ_GROUPS_ARR_NUM = 8, 3656f443ebcSRyan Zezeski } enahw_aenq_groups_t; 3666f443ebcSRyan Zezeski 3676f443ebcSRyan Zezeski /* 3686f443ebcSRyan Zezeski * The reason for ENAHW_AENQ_GROUP_NOFIFICATION. 3696f443ebcSRyan Zezeski * 3706f443ebcSRyan Zezeski * common: ena_admin_aenq_notification_syndrome 3716f443ebcSRyan Zezeski */ 3726f443ebcSRyan Zezeski typedef enum enahw_aenq_syndrome { 3736f443ebcSRyan Zezeski ENAHW_AENQ_SYNDROME_UPDATE_HINTS = 2, 3746f443ebcSRyan Zezeski } enahw_aenq_syndrome_t; 3756f443ebcSRyan Zezeski 3766f443ebcSRyan Zezeski /* 3776f443ebcSRyan Zezeski * ENA devices use a 48-bit memory space. 3786f443ebcSRyan Zezeski * 3796f443ebcSRyan Zezeski * common: ena_common_mem_addr 3806f443ebcSRyan Zezeski */ 3816f443ebcSRyan Zezeski typedef struct enahw_addr { 3826f443ebcSRyan Zezeski uint32_t ea_low; 3836f443ebcSRyan Zezeski uint16_t ea_high; 3846f443ebcSRyan Zezeski uint16_t ea_rsvd; /* must be zero */ 3856f443ebcSRyan Zezeski } enahw_addr_t; 3866f443ebcSRyan Zezeski 3876f443ebcSRyan Zezeski /* common: ena_admin_ctrl_buff_info */ 3886f443ebcSRyan Zezeski struct enahw_ctrl_buff { 3896f443ebcSRyan Zezeski uint32_t ecb_length; 3906f443ebcSRyan Zezeski enahw_addr_t ecb_addr; 3916f443ebcSRyan Zezeski }; 3926f443ebcSRyan Zezeski 3936f443ebcSRyan Zezeski /* common: ena_admin_get_set_feature_common_desc */ 3946f443ebcSRyan Zezeski struct enahw_feat_common { 3956f443ebcSRyan Zezeski /* 3966f443ebcSRyan Zezeski * 1:0 Select which value you want. 3976f443ebcSRyan Zezeski * 3986f443ebcSRyan Zezeski * 0x1 = Current value. 3996f443ebcSRyan Zezeski * 0x3 = Default value. 4006f443ebcSRyan Zezeski * 4016f443ebcSRyan Zezeski * Note: Linux seems to set this to 0 to get the value, 4026f443ebcSRyan Zezeski * not sure if that's a bug or just another way to get the 4036f443ebcSRyan Zezeski * current value. 4046f443ebcSRyan Zezeski * 4056f443ebcSRyan Zezeski * 7:3 Reserved. 4066f443ebcSRyan Zezeski */ 4076f443ebcSRyan Zezeski uint8_t efc_flags; 4086f443ebcSRyan Zezeski 4096f443ebcSRyan Zezeski /* An id from enahw_feature_id_t. */ 4106f443ebcSRyan Zezeski uint8_t efc_id; 4116f443ebcSRyan Zezeski 4126f443ebcSRyan Zezeski /* 4136f443ebcSRyan Zezeski * Each feature is versioned, allowing upgrades to the feature 4146f443ebcSRyan Zezeski * set without breaking backwards compatibility. The driver 4156f443ebcSRyan Zezeski * uses this field to specify which version it supports 4166f443ebcSRyan Zezeski * (starting from zero). Linux doesn't document this very well 4176f443ebcSRyan Zezeski * and sets this value to 0 for most features. We define a set 4186f443ebcSRyan Zezeski * of macros, underneath the enahw_feature_id_t type, clearly 4196f443ebcSRyan Zezeski * documenting the version we support for each feature. 4206f443ebcSRyan Zezeski */ 4216f443ebcSRyan Zezeski uint8_t efc_version; 4226f443ebcSRyan Zezeski uint8_t efc_rsvd; 4236f443ebcSRyan Zezeski }; 4246f443ebcSRyan Zezeski 4256f443ebcSRyan Zezeski /* common: ena_admin_get_feat_cmd */ 4266f443ebcSRyan Zezeski typedef struct enahw_cmd_get_feat { 4276f443ebcSRyan Zezeski struct enahw_ctrl_buff ecgf_ctrl_buf; 4286f443ebcSRyan Zezeski struct enahw_feat_common ecgf_comm; 4296f443ebcSRyan Zezeski uint32_t egcf_unused[11]; 4306f443ebcSRyan Zezeski } enahw_cmd_get_feat_t; 4316f443ebcSRyan Zezeski 4326f443ebcSRyan Zezeski /* 4336f443ebcSRyan Zezeski * N.B. Linux sets efc_flags to 0 (via memset) when reading the 4346f443ebcSRyan Zezeski * current value, but the comments say it should be 0x1. We follow the 4356f443ebcSRyan Zezeski * comments. 4366f443ebcSRyan Zezeski */ 4376f443ebcSRyan Zezeski #define ENAHW_GET_FEAT_FLAGS_GET_CURR_VAL(desc) \ 4386f443ebcSRyan Zezeski ((desc)->ecgf_comm.efc_flags) |= 0x1 4396f443ebcSRyan Zezeski #define ENAHW_GET_FEAT_FLAGS_GET_DEF_VAL(desc) \ 4406f443ebcSRyan Zezeski ((desc)->ecgf_comm.efc_flags) |= 0x3 4416f443ebcSRyan Zezeski 4426f443ebcSRyan Zezeski /* 4436f443ebcSRyan Zezeski * Set the MTU of the device. This value does not include the L2 4446f443ebcSRyan Zezeski * headers or trailers, only the payload. 4456f443ebcSRyan Zezeski * 4466f443ebcSRyan Zezeski * common: ena_admin_set_feature_mtu_desc 4476f443ebcSRyan Zezeski */ 4486f443ebcSRyan Zezeski typedef struct enahw_feat_mtu { 4496f443ebcSRyan Zezeski uint32_t efm_mtu; 4506f443ebcSRyan Zezeski } enahw_feat_mtu_t; 4516f443ebcSRyan Zezeski 4526f443ebcSRyan Zezeski /* common: ena_admin_set_feature_host_attr_desc */ 4536f443ebcSRyan Zezeski typedef struct enahw_feat_host_attr { 4546f443ebcSRyan Zezeski enahw_addr_t efha_os_addr; 4556f443ebcSRyan Zezeski enahw_addr_t efha_debug_addr; 4566f443ebcSRyan Zezeski uint32_t efha_debug_sz; 4576f443ebcSRyan Zezeski } enahw_feat_host_attr_t; 4586f443ebcSRyan Zezeski 4596f443ebcSRyan Zezeski /* 4606f443ebcSRyan Zezeski * ENAHW_FEAT_AENQ_CONFIG 4616f443ebcSRyan Zezeski * 4626f443ebcSRyan Zezeski * common: ena_admin_feature_aenq_desc 4636f443ebcSRyan Zezeski */ 4646f443ebcSRyan Zezeski typedef struct enahw_feat_aenq { 4656f443ebcSRyan Zezeski /* Bitmask of AENQ groups this device supports. */ 4666f443ebcSRyan Zezeski uint32_t efa_supported_groups; 4676f443ebcSRyan Zezeski 4686f443ebcSRyan Zezeski /* Bitmask of AENQ groups currently enabled. */ 4696f443ebcSRyan Zezeski uint32_t efa_enabled_groups; 4706f443ebcSRyan Zezeski } enahw_feat_aenq_t; 4716f443ebcSRyan Zezeski 4726f443ebcSRyan Zezeski /* common: ena_admin_set_feat_cmd */ 4736f443ebcSRyan Zezeski typedef struct enahw_cmd_set_feat { 4746f443ebcSRyan Zezeski struct enahw_ctrl_buff ecsf_ctrl_buf; 4756f443ebcSRyan Zezeski struct enahw_feat_common ecsf_comm; 4766f443ebcSRyan Zezeski 4776f443ebcSRyan Zezeski union { 4786f443ebcSRyan Zezeski uint32_t ecsf_raw[11]; 4796f443ebcSRyan Zezeski enahw_feat_host_attr_t ecsf_host_attr; 4806f443ebcSRyan Zezeski enahw_feat_mtu_t ecsf_mtu; 4816f443ebcSRyan Zezeski enahw_feat_aenq_t ecsf_aenq; 4826f443ebcSRyan Zezeski } ecsf_feat; 4836f443ebcSRyan Zezeski } enahw_cmd_set_feat_t; 4846f443ebcSRyan Zezeski 4856f443ebcSRyan Zezeski /* 4866f443ebcSRyan Zezeski * Used to populate the host information buffer which the Nitro 4876f443ebcSRyan Zezeski * hypervisor supposedly uses for display, debugging, and possibly 4886f443ebcSRyan Zezeski * other purposes. 4896f443ebcSRyan Zezeski * 4906f443ebcSRyan Zezeski * common: ena_admin_host_info 4916f443ebcSRyan Zezeski */ 4926f443ebcSRyan Zezeski typedef struct enahw_host_info { 4936f443ebcSRyan Zezeski uint32_t ehi_os_type; 4946f443ebcSRyan Zezeski uint8_t ehi_os_dist_str[128]; 4956f443ebcSRyan Zezeski uint32_t ehi_os_dist; 4966f443ebcSRyan Zezeski uint8_t ehi_kernel_ver_str[32]; 4976f443ebcSRyan Zezeski uint32_t ehi_kernel_ver; 4986f443ebcSRyan Zezeski uint32_t ehi_driver_ver; 4996f443ebcSRyan Zezeski uint32_t ehi_supported_net_features[2]; 5006f443ebcSRyan Zezeski uint16_t ehi_ena_spec_version; 5016f443ebcSRyan Zezeski uint16_t ehi_bdf; 5026f443ebcSRyan Zezeski uint16_t ehi_num_cpus; 5036f443ebcSRyan Zezeski uint16_t ehi_rsvd; 5046f443ebcSRyan Zezeski uint32_t ehi_driver_supported_features; 5056f443ebcSRyan Zezeski } enahw_host_info_t; 5066f443ebcSRyan Zezeski 5076f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 5086f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_MINOR_SHIFT 8 5096f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_MINOR_MASK GENMASK(15, 8) 5106f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_SUB_MINOR_SHIFT 16 5116f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 5126f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_SPEC_MAJOR_SHIFT 8 5136f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_MODULE_TYPE_SHIFT 24 5146f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 5156f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 5166f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_DEVICE_SHIFT 3 5176f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 5186f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_BUS_SHIFT 8 5196f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_BUS_MASK GENMASK(15, 8) 5206f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RX_OFFSET_SHIFT 1 5216f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RX_OFFSET_MASK BIT(1) 5226f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 5236f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 5246f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 5256f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 5266f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 5276f443ebcSRyan Zezeski #define ENAHW_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 528*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 529*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) 530*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7 531*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7) 532*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_INFO_PHC_SHIFT 8 533*c46e4de3SAndy Fiddaman #define ENAHW_HOST_INFO_INFO_PHC_MASK BIT(8) 5346f443ebcSRyan Zezeski 5356f443ebcSRyan Zezeski /* common: ena_admin_os_type */ 5366f443ebcSRyan Zezeski enum enahw_os_type { 5376f443ebcSRyan Zezeski ENAHW_OS_LINUX = 1, 5386f443ebcSRyan Zezeski ENAHW_OS_WIN = 2, 5396f443ebcSRyan Zezeski ENAHW_OS_DPDK = 3, 5406f443ebcSRyan Zezeski ENAHW_OS_FREEBSD = 4, 5416f443ebcSRyan Zezeski ENAHW_OS_IPXE = 5, 5426f443ebcSRyan Zezeski ENAHW_OS_ESXI = 6, 5436f443ebcSRyan Zezeski ENAHW_OS_MACOS = 7, 5446f443ebcSRyan Zezeski ENAHW_OS_GROUPS_NUM = 7, 5456f443ebcSRyan Zezeski }; 5466f443ebcSRyan Zezeski 5476f443ebcSRyan Zezeski /* 5486f443ebcSRyan Zezeski * Create I/O Completion Queue 5496f443ebcSRyan Zezeski * 5506f443ebcSRyan Zezeski * A completion queue is where the device writes responses to I/O 5516f443ebcSRyan Zezeski * requests. The admin completion queue must be created before such a 5526f443ebcSRyan Zezeski * command can be issued, see ena_admin_cq_init(). 5536f443ebcSRyan Zezeski * 5546f443ebcSRyan Zezeski * common: ena_admin_aq_create_cq_cmd 5556f443ebcSRyan Zezeski */ 5566f443ebcSRyan Zezeski typedef struct enahw_cmd_create_cq { 5576f443ebcSRyan Zezeski /* 5586f443ebcSRyan Zezeski * 7-6 reserved 5596f443ebcSRyan Zezeski * 5606f443ebcSRyan Zezeski * 5 interrupt mode: when set the device sends an interrupt 5616f443ebcSRyan Zezeski * for each completion, otherwise the driver must poll 5626f443ebcSRyan Zezeski * the queue. 5636f443ebcSRyan Zezeski * 5646f443ebcSRyan Zezeski * 4-0 reserved 5656f443ebcSRyan Zezeski */ 5666f443ebcSRyan Zezeski uint8_t ecq_caps_1; 5676f443ebcSRyan Zezeski 5686f443ebcSRyan Zezeski /* 5696f443ebcSRyan Zezeski * 7-5 reserved 5706f443ebcSRyan Zezeski * 5716f443ebcSRyan Zezeski * 4-0 CQ entry size (in words): the size of a single CQ entry 5726f443ebcSRyan Zezeski * in multiples of 32-bit words. 5736f443ebcSRyan Zezeski * 5746f443ebcSRyan Zezeski * NOTE: According to the common code the "valid" values 5756f443ebcSRyan Zezeski * are 4 or 8 -- this is incorrect. The valid values are 5766f443ebcSRyan Zezeski * 2 and 4. The common code does have an "extended" Rx 5776f443ebcSRyan Zezeski * completion descriptor, ena_eth_io_rx_cdesc_ext, that 5786f443ebcSRyan Zezeski * is 32 bytes and thus would use a value of 8, but it is 5796f443ebcSRyan Zezeski * not used by the Linux or FreeBSD drivers, so we do not 5806f443ebcSRyan Zezeski * bother with it. 5816f443ebcSRyan Zezeski * 5826f443ebcSRyan Zezeski * Type Bytes Value 5836f443ebcSRyan Zezeski * enahw_tx_cdesc_t 8 2 5846f443ebcSRyan Zezeski * enahw_rx_cdesc_t 16 4 5856f443ebcSRyan Zezeski */ 5866f443ebcSRyan Zezeski uint8_t ecq_caps_2; 5876f443ebcSRyan Zezeski 5886f443ebcSRyan Zezeski /* The number of CQ entries, must be a power of 2. */ 5896f443ebcSRyan Zezeski uint16_t ecq_num_descs; 5906f443ebcSRyan Zezeski 5916f443ebcSRyan Zezeski /* The MSI-X vector assigned to this CQ. */ 5926f443ebcSRyan Zezeski uint32_t ecq_msix_vector; 5936f443ebcSRyan Zezeski 5946f443ebcSRyan Zezeski /* 5956f443ebcSRyan Zezeski * The CQ's physical base address. The CQ memory must be 5966f443ebcSRyan Zezeski * physically contiguous. 5976f443ebcSRyan Zezeski */ 5986f443ebcSRyan Zezeski enahw_addr_t ecq_addr; 5996f443ebcSRyan Zezeski } enahw_cmd_create_cq_t; 6006f443ebcSRyan Zezeski 6016f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_SHIFT 5 6026f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK (BIT(5)) 6036f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS_MASK (GENMASK(4, 0)) 6046f443ebcSRyan Zezeski 6056f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLE(cmd) \ 6066f443ebcSRyan Zezeski ((cmd)->ecq_caps_1 |= ENAHW_CMD_CREATE_CQ_INTERRUPT_MODE_ENABLED_MASK) 6076f443ebcSRyan Zezeski 6086f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS(cmd, val) \ 6096f443ebcSRyan Zezeski (((cmd)->ecq_caps_2) |= \ 6106f443ebcSRyan Zezeski ((val) & ENAHW_CMD_CREATE_CQ_DESC_SIZE_WORDS_MASK)) 6116f443ebcSRyan Zezeski 6126f443ebcSRyan Zezeski /* 6136f443ebcSRyan Zezeski * Destroy Completion Queue 6146f443ebcSRyan Zezeski * 6156f443ebcSRyan Zezeski * common: ena_admin_aq_destroy_cq_cmd 6166f443ebcSRyan Zezeski */ 6176f443ebcSRyan Zezeski typedef struct enahw_cmd_destroy_cq { 6186f443ebcSRyan Zezeski uint16_t edcq_idx; 6196f443ebcSRyan Zezeski uint16_t edcq_rsvd; 6206f443ebcSRyan Zezeski } enahw_cmd_destroy_cq_t; 6216f443ebcSRyan Zezeski 6226f443ebcSRyan Zezeski /* 6236f443ebcSRyan Zezeski * common: ena_admin_aq_create_sq_cmd 6246f443ebcSRyan Zezeski */ 6256f443ebcSRyan Zezeski typedef struct enahw_cmd_create_sq { 6266f443ebcSRyan Zezeski /* 6276f443ebcSRyan Zezeski * 7-5 direction: 0x1 = Tx, 0x2 = Rx 6286f443ebcSRyan Zezeski * 4-0 reserved 6296f443ebcSRyan Zezeski */ 6306f443ebcSRyan Zezeski uint8_t ecsq_dir; 6316f443ebcSRyan Zezeski uint8_t ecsq_rsvd1; 6326f443ebcSRyan Zezeski 6336f443ebcSRyan Zezeski /* 6346f443ebcSRyan Zezeski * 7 reserved 6356f443ebcSRyan Zezeski * 6366f443ebcSRyan Zezeski * 6-4 completion policy: How are completion events generated. 6376f443ebcSRyan Zezeski * 6386f443ebcSRyan Zezeski * See enahw_completion_policy_type_t for a description of 6396f443ebcSRyan Zezeski * the various values. 6406f443ebcSRyan Zezeski * 6416f443ebcSRyan Zezeski * 3-0 placement policy: Where the descriptor ring and 6426f443ebcSRyan Zezeski * headers reside. 6436f443ebcSRyan Zezeski * 6446f443ebcSRyan Zezeski * See enahw_placement_policy_t for a description of the 6456f443ebcSRyan Zezeski * various values. 6466f443ebcSRyan Zezeski */ 6476f443ebcSRyan Zezeski uint8_t ecsq_caps_2; 6486f443ebcSRyan Zezeski 6496f443ebcSRyan Zezeski /* 6506f443ebcSRyan Zezeski * 7-1 reserved 6516f443ebcSRyan Zezeski * 652eebd18daSAndy Fiddaman * 0 physically contiguous: When set indicates the descriptor 653eebd18daSAndy Fiddaman * ring memory is physically contiguous. 6546f443ebcSRyan Zezeski */ 6556f443ebcSRyan Zezeski uint8_t ecsq_caps_3; 6566f443ebcSRyan Zezeski 6576f443ebcSRyan Zezeski /* 6586f443ebcSRyan Zezeski * The index of the associated Completion Queue (CQ). The CQ 6596f443ebcSRyan Zezeski * must be created before the SQ. 6606f443ebcSRyan Zezeski */ 6616f443ebcSRyan Zezeski uint16_t ecsq_cq_idx; 6626f443ebcSRyan Zezeski 6636f443ebcSRyan Zezeski /* The number of descriptors in this SQ. */ 6646f443ebcSRyan Zezeski uint16_t ecsq_num_descs; 6656f443ebcSRyan Zezeski 6666f443ebcSRyan Zezeski /* 6676f443ebcSRyan Zezeski * The base physical address of the SQ. This should not be set 6686f443ebcSRyan Zezeski * for LLQ. Must be page aligned. 6696f443ebcSRyan Zezeski */ 6706f443ebcSRyan Zezeski enahw_addr_t ecsq_base; 6716f443ebcSRyan Zezeski 6726f443ebcSRyan Zezeski /* 6736f443ebcSRyan Zezeski * The physical address of the head write-back pointer. Valid 6746f443ebcSRyan Zezeski * only when the completion policy is set to one of the head 6756f443ebcSRyan Zezeski * write-back modes (0x2 or 0x3). Must be cacheline size 6766f443ebcSRyan Zezeski * aligned. 6776f443ebcSRyan Zezeski */ 6786f443ebcSRyan Zezeski enahw_addr_t ecsq_head_wb; 6796f443ebcSRyan Zezeski uint32_t ecsq_rsvdw2; 6806f443ebcSRyan Zezeski uint32_t ecsq_rsvdw3; 6816f443ebcSRyan Zezeski } enahw_cmd_create_sq_t; 6826f443ebcSRyan Zezeski 6836f443ebcSRyan Zezeski typedef enum enahw_sq_direction { 6846f443ebcSRyan Zezeski ENAHW_SQ_DIRECTION_TX = 1, 6856f443ebcSRyan Zezeski ENAHW_SQ_DIRECTION_RX = 2, 6866f443ebcSRyan Zezeski } enahw_sq_direction_t; 6876f443ebcSRyan Zezeski 6886f443ebcSRyan Zezeski typedef enum enahw_placement_policy { 6896f443ebcSRyan Zezeski /* Descriptors and headers are in host memory. */ 6906f443ebcSRyan Zezeski ENAHW_PLACEMENT_POLICY_HOST = 1, 6916f443ebcSRyan Zezeski 6926f443ebcSRyan Zezeski /* 6936f443ebcSRyan Zezeski * Descriptors and headers are in device memory (a.k.a Low 6946f443ebcSRyan Zezeski * Latency Queue). 6956f443ebcSRyan Zezeski */ 6966f443ebcSRyan Zezeski ENAHW_PLACEMENT_POLICY_DEV = 3, 6976f443ebcSRyan Zezeski } enahw_placement_policy_t; 6986f443ebcSRyan Zezeski 6996f443ebcSRyan Zezeski /* 7006f443ebcSRyan Zezeski * DESC: Write a CQ entry for each SQ descriptor. 7016f443ebcSRyan Zezeski * 7026f443ebcSRyan Zezeski * DESC_ON_DEMAND: Write a CQ entry when requested by the SQ descriptor. 7036f443ebcSRyan Zezeski * 7046f443ebcSRyan Zezeski * HEAD_ON_DEMAND: Update head pointer when requested by the SQ 7056f443ebcSRyan Zezeski * descriptor. 7066f443ebcSRyan Zezeski * 7076f443ebcSRyan Zezeski * HEAD: Update head pointer for each SQ descriptor. 7086f443ebcSRyan Zezeski * 7096f443ebcSRyan Zezeski */ 7106f443ebcSRyan Zezeski typedef enum enahw_completion_policy_type { 7116f443ebcSRyan Zezeski ENAHW_COMPLETION_POLICY_DESC = 0, 7126f443ebcSRyan Zezeski ENAHW_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 7136f443ebcSRyan Zezeski ENAHW_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 7146f443ebcSRyan Zezeski ENAHW_COMPLETION_POLICY_HEAD = 3, 7156f443ebcSRyan Zezeski } enahw_completion_policy_type_t; 7166f443ebcSRyan Zezeski 7176f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_DIR_SHIFT 5 7186f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_DIR_MASK GENMASK(7, 5) 7196f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY_MASK GENMASK(3, 0) 7206f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_SHIFT 4 7216f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_MASK GENMASK(6, 4) 7226f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK BIT(0) 7236f443ebcSRyan Zezeski 7246f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_DIR(cmd, val) \ 7256f443ebcSRyan Zezeski (((cmd)->ecsq_dir) |= (((val) << ENAHW_CMD_CREATE_SQ_DIR_SHIFT) & \ 7266f443ebcSRyan Zezeski ENAHW_CMD_CREATE_SQ_DIR_MASK)) 7276f443ebcSRyan Zezeski 7286f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY(cmd, val) \ 7296f443ebcSRyan Zezeski (((cmd)->ecsq_caps_2) |= \ 7306f443ebcSRyan Zezeski ((val) & ENAHW_CMD_CREATE_SQ_PLACEMENT_POLICY_MASK)) 7316f443ebcSRyan Zezeski 7326f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY(cmd, val) \ 7336f443ebcSRyan Zezeski (((cmd)->ecsq_caps_2) |= \ 7346f443ebcSRyan Zezeski (((val) << ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_SHIFT) & \ 7356f443ebcSRyan Zezeski ENAHW_CMD_CREATE_SQ_COMPLETION_POLICY_MASK)) 7366f443ebcSRyan Zezeski 7376f443ebcSRyan Zezeski #define ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG(cmd) \ 7386f443ebcSRyan Zezeski ((cmd)->ecsq_caps_3 |= ENAHW_CMD_CREATE_SQ_PHYSMEM_CONTIG_MASK) 7396f443ebcSRyan Zezeski 7406f443ebcSRyan Zezeski /* common: ena_admin_sq */ 7416f443ebcSRyan Zezeski typedef struct enahw_cmd_destroy_sq { 7426f443ebcSRyan Zezeski uint16_t edsq_idx; 7436f443ebcSRyan Zezeski uint8_t edsq_dir; /* Tx/Rx */ 7446f443ebcSRyan Zezeski uint8_t edsq_rsvd; 7456f443ebcSRyan Zezeski } enahw_cmd_destroy_sq_t; 7466f443ebcSRyan Zezeski 7476f443ebcSRyan Zezeski #define ENAHW_CMD_DESTROY_SQ_DIR_SHIFT 5 7486f443ebcSRyan Zezeski #define ENAHW_CMD_DESTROY_SQ_DIR_MASK GENMASK(7, 5) 7496f443ebcSRyan Zezeski 7506f443ebcSRyan Zezeski #define ENAHW_CMD_DESTROY_SQ_DIR(cmd, val) \ 7516f443ebcSRyan Zezeski (((cmd)->edsq_dir) |= (((val) << ENAHW_CMD_DESTROY_SQ_DIR_SHIFT) & \ 7526f443ebcSRyan Zezeski ENAHW_CMD_DESTROY_SQ_DIR_MASK)) 7536f443ebcSRyan Zezeski 7546f443ebcSRyan Zezeski /* common: ena_admin_aq_get_stats_cmd */ 7556f443ebcSRyan Zezeski typedef struct enahw_cmd_get_stats { 7566f443ebcSRyan Zezeski struct enahw_ctrl_buff ecgs_ctrl_buf; 7576f443ebcSRyan Zezeski uint8_t ecgs_type; 7586f443ebcSRyan Zezeski uint8_t ecgs_scope; 7596f443ebcSRyan Zezeski uint16_t ecgs_rsvd; 7606f443ebcSRyan Zezeski uint16_t ecgs_queue_idx; 7616f443ebcSRyan Zezeski 7626f443ebcSRyan Zezeski /* 7636f443ebcSRyan Zezeski * The device ID for which to query stats from. The sentinel 7646f443ebcSRyan Zezeski * value 0xFFFF indicates a query of the current device. 7656f443ebcSRyan Zezeski * According to the common docs, a "privileged device" may 7666f443ebcSRyan Zezeski * query stats for other ENA devices. However the definition 7676f443ebcSRyan Zezeski * of this "privilege device" is not expanded upon. 7686f443ebcSRyan Zezeski */ 7696f443ebcSRyan Zezeski uint16_t ecgs_device_id; 7706f443ebcSRyan Zezeski } enahw_cmd_get_stats_t; 7716f443ebcSRyan Zezeski 7726f443ebcSRyan Zezeski /* Query the stats for my device. */ 7736f443ebcSRyan Zezeski #define ENAHW_CMD_GET_STATS_MY_DEVICE_ID 0xFFFF 7746f443ebcSRyan Zezeski 7756f443ebcSRyan Zezeski /* 7766f443ebcSRyan Zezeski * BASIC: Returns enahw_resp_basic_stats. 7776f443ebcSRyan Zezeski * 7786f443ebcSRyan Zezeski * EXTENDED: According to the Linux documentation returns a buffer in 7796f443ebcSRyan Zezeski * "string format" with additional statistics per queue and per device ID. 7806f443ebcSRyan Zezeski * 7816f443ebcSRyan Zezeski * ENI: According to the Linux documentation it returns "extra HW 782*c46e4de3SAndy Fiddaman * stats for specific network interface". 7836f443ebcSRyan Zezeski * 7846f443ebcSRyan Zezeski * common: ena_admin_get_stats_type 7856f443ebcSRyan Zezeski */ 7866f443ebcSRyan Zezeski typedef enum enahw_get_stats_type { 7876f443ebcSRyan Zezeski ENAHW_GET_STATS_TYPE_BASIC = 0, 7886f443ebcSRyan Zezeski ENAHW_GET_STATS_TYPE_EXTENDED = 1, 7896f443ebcSRyan Zezeski ENAHW_GET_STATS_TYPE_ENI = 2, 7906f443ebcSRyan Zezeski } enahw_get_stats_type_t; 7916f443ebcSRyan Zezeski 7926f443ebcSRyan Zezeski /* common: ena_admin_get_stats_scope */ 7936f443ebcSRyan Zezeski typedef enum enahw_get_stats_scope { 7946f443ebcSRyan Zezeski ENAHW_GET_STATS_SCOPE_QUEUE = 0, 7956f443ebcSRyan Zezeski ENAHW_GET_STATS_SCOPE_ETH = 1, 7966f443ebcSRyan Zezeski } enahw_get_stats_scope_t; 7976f443ebcSRyan Zezeski 7986f443ebcSRyan Zezeski /* common: ena_admin_aq_entry */ 7996f443ebcSRyan Zezeski typedef struct enahw_cmd_desc { 8006f443ebcSRyan Zezeski uint16_t ecd_cmd_id; 8016f443ebcSRyan Zezeski uint8_t ecd_opcode; 8026f443ebcSRyan Zezeski uint8_t ecd_flags; 8036f443ebcSRyan Zezeski 8046f443ebcSRyan Zezeski union { 8056f443ebcSRyan Zezeski uint32_t ecd_raw[15]; 8066f443ebcSRyan Zezeski enahw_cmd_get_feat_t ecd_get_feat; 8076f443ebcSRyan Zezeski enahw_cmd_set_feat_t ecd_set_feat; 8086f443ebcSRyan Zezeski enahw_cmd_create_cq_t ecd_create_cq; 8096f443ebcSRyan Zezeski enahw_cmd_destroy_cq_t ecd_destroy_cq; 8106f443ebcSRyan Zezeski enahw_cmd_create_sq_t ecd_create_sq; 8116f443ebcSRyan Zezeski enahw_cmd_destroy_sq_t ecd_destroy_sq; 8126f443ebcSRyan Zezeski enahw_cmd_get_stats_t ecd_get_stats; 8136f443ebcSRyan Zezeski } ecd_cmd; 8146f443ebcSRyan Zezeski 8156f443ebcSRyan Zezeski } enahw_cmd_desc_t; 8166f443ebcSRyan Zezeski 8176f443ebcSRyan Zezeski /* 8186f443ebcSRyan Zezeski * top level commands that may be sent to the Admin Queue. 8196f443ebcSRyan Zezeski * 8206f443ebcSRyan Zezeski * common: ena_admin_aq_opcode 8216f443ebcSRyan Zezeski */ 8226f443ebcSRyan Zezeski typedef enum ena_cmd_opcode { 8236f443ebcSRyan Zezeski ENAHW_CMD_NONE = 0, 8246f443ebcSRyan Zezeski ENAHW_CMD_CREATE_SQ = 1, 8256f443ebcSRyan Zezeski ENAHW_CMD_DESTROY_SQ = 2, 8266f443ebcSRyan Zezeski ENAHW_CMD_CREATE_CQ = 3, 8276f443ebcSRyan Zezeski ENAHW_CMD_DESTROY_CQ = 4, 8286f443ebcSRyan Zezeski ENAHW_CMD_GET_FEATURE = 8, 8296f443ebcSRyan Zezeski ENAHW_CMD_SET_FEATURE = 9, 8306f443ebcSRyan Zezeski ENAHW_CMD_GET_STATS = 11, 8316f443ebcSRyan Zezeski } enahw_cmd_opcode_t; 8326f443ebcSRyan Zezeski 8336f443ebcSRyan Zezeski /* common: ENA_ADMIN_AQ_COMMON_DESC */ 8346f443ebcSRyan Zezeski #define ENAHW_CMD_ID_MASK GENMASK(11, 0) 8356f443ebcSRyan Zezeski #define ENAHW_CMD_PHASE_MASK BIT(0) 8366f443ebcSRyan Zezeski 8376f443ebcSRyan Zezeski #define ENAHW_CMD_ID(desc, id) \ 8386f443ebcSRyan Zezeski (((desc)->ecd_cmd_id) |= ((id) & ENAHW_CMD_ID_MASK)) 8396f443ebcSRyan Zezeski 8406f443ebcSRyan Zezeski /* 8416f443ebcSRyan Zezeski * Subcommands for ENA_ADMIN_{GET,SET}_FEATURE. 8426f443ebcSRyan Zezeski * 8436f443ebcSRyan Zezeski * common: ena_admin_aq_feature_id 8446f443ebcSRyan Zezeski */ 8456f443ebcSRyan Zezeski typedef enum enahw_feature_id { 8466f443ebcSRyan Zezeski ENAHW_FEAT_DEVICE_ATTRIBUTES = 1, 8476f443ebcSRyan Zezeski ENAHW_FEAT_MAX_QUEUES_NUM = 2, 8486f443ebcSRyan Zezeski ENAHW_FEAT_HW_HINTS = 3, 8496f443ebcSRyan Zezeski ENAHW_FEAT_LLQ = 4, 8506f443ebcSRyan Zezeski ENAHW_FEAT_EXTRA_PROPERTIES_STRINGS = 5, 8516f443ebcSRyan Zezeski ENAHW_FEAT_EXTRA_PROPERTIES_FLAGS = 6, 8526f443ebcSRyan Zezeski ENAHW_FEAT_MAX_QUEUES_EXT = 7, 8536f443ebcSRyan Zezeski ENAHW_FEAT_RSS_HASH_FUNCTION = 10, 8546f443ebcSRyan Zezeski ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG = 11, 8556f443ebcSRyan Zezeski ENAHW_FEAT_RSS_INDIRECTION_TABLE_CONFIG = 12, 8566f443ebcSRyan Zezeski ENAHW_FEAT_MTU = 14, 8576f443ebcSRyan Zezeski ENAHW_FEAT_RSS_HASH_INPUT = 18, 8586f443ebcSRyan Zezeski ENAHW_FEAT_INTERRUPT_MODERATION = 20, 8596f443ebcSRyan Zezeski ENAHW_FEAT_AENQ_CONFIG = 26, 8606f443ebcSRyan Zezeski ENAHW_FEAT_LINK_CONFIG = 27, 8616f443ebcSRyan Zezeski ENAHW_FEAT_HOST_ATTR_CONFIG = 28, 862*c46e4de3SAndy Fiddaman ENAHW_FEAT_PHC_CONFIG = 29, 8636f443ebcSRyan Zezeski ENAHW_FEAT_NUM = 32, 8646f443ebcSRyan Zezeski } enahw_feature_id_t; 8656f443ebcSRyan Zezeski 866eebd18daSAndy Fiddaman /* 867eebd18daSAndy Fiddaman * Device capabilities. 868eebd18daSAndy Fiddaman * 869eebd18daSAndy Fiddaman * common: ena_admin_aq_caps_id 870eebd18daSAndy Fiddaman */ 871eebd18daSAndy Fiddaman typedef enum enahw_capability_id { 872eebd18daSAndy Fiddaman ENAHW_CAP_ENI_STATS = 0, 873eebd18daSAndy Fiddaman ENAHW_CAP_ENA_SRD_INFO = 1, 874eebd18daSAndy Fiddaman ENAHW_CAP_CUSTOMER_METRICS = 2, 875*c46e4de3SAndy Fiddaman ENAHW_CAP_EXTENDED_RESET_REASONS = 3, 876eebd18daSAndy Fiddaman ENAHW_CAP_CDESC_MBZ = 4, 877*c46e4de3SAndy Fiddaman ENAHW_CAP_NUM 878eebd18daSAndy Fiddaman } enahw_capability_id_t; 879eebd18daSAndy Fiddaman 8806f443ebcSRyan Zezeski /* 8816f443ebcSRyan Zezeski * The following macros define the maximum version we support for each 8826f443ebcSRyan Zezeski * feature. These are the feature versions we use to communicate with 8836f443ebcSRyan Zezeski * the feature command. Linux has these values spread throughout the 8846f443ebcSRyan Zezeski * code at the various callsites of ena_com_get_feature(). We choose 8856f443ebcSRyan Zezeski * to centralize our feature versions to make it easier to audit. 8866f443ebcSRyan Zezeski */ 8876f443ebcSRyan Zezeski #define ENAHW_FEAT_DEVICE_ATTRIBUTES_VER 0 8886f443ebcSRyan Zezeski #define ENAHW_FEAT_MAX_QUEUES_NUM_VER 0 8896f443ebcSRyan Zezeski #define ENAHW_FEAT_HW_HINTS_VER 0 8906f443ebcSRyan Zezeski #define ENAHW_FEAT_LLQ_VER 0 8916f443ebcSRyan Zezeski #define ENAHW_FEAT_EXTRA_PROPERTIES_STRINGS_VER 0 8926f443ebcSRyan Zezeski #define ENAHW_FEAT_EXTRA_PROPERTIES_FLAGS_VER 0 8936f443ebcSRyan Zezeski #define ENAHW_FEAT_MAX_QUEUES_EXT_VER 1 8946f443ebcSRyan Zezeski #define ENAHW_FEAT_RSS_HASH_FUNCTION_VER 0 8956f443ebcSRyan Zezeski #define ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG_VER 0 8966f443ebcSRyan Zezeski #define ENAHW_FEAT_RSS_INDIRECTION_TABLE_CONFIG_VER 0 8976f443ebcSRyan Zezeski #define ENAHW_FEAT_MTU_VER 0 8986f443ebcSRyan Zezeski #define ENAHW_FEAT_RSS_HASH_INPUT_VER 0 8996f443ebcSRyan Zezeski #define ENAHW_FEAT_INTERRUPT_MODERATION_VER 0 9006f443ebcSRyan Zezeski #define ENAHW_FEAT_AENQ_CONFIG_VER 0 9016f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONFIG_VER 0 9026f443ebcSRyan Zezeski #define ENAHW_FEAT_HOST_ATTR_CONFIG_VER 0 9036f443ebcSRyan Zezeski 9046f443ebcSRyan Zezeski /* common: ena_admin_link_types */ 9056f443ebcSRyan Zezeski typedef enum enahw_link_speeds { 9066f443ebcSRyan Zezeski ENAHW_LINK_SPEED_1G = 0x1, 9076f443ebcSRyan Zezeski ENAHW_LINK_SPEED_2_HALF_G = 0x2, 9086f443ebcSRyan Zezeski ENAHW_LINK_SPEED_5G = 0x4, 9096f443ebcSRyan Zezeski ENAHW_LINK_SPEED_10G = 0x8, 9106f443ebcSRyan Zezeski ENAHW_LINK_SPEED_25G = 0x10, 9116f443ebcSRyan Zezeski ENAHW_LINK_SPEED_40G = 0x20, 9126f443ebcSRyan Zezeski ENAHW_LINK_SPEED_50G = 0x40, 9136f443ebcSRyan Zezeski ENAHW_LINK_SPEED_100G = 0x80, 9146f443ebcSRyan Zezeski ENAHW_LINK_SPEED_200G = 0x100, 9156f443ebcSRyan Zezeski ENAHW_LINK_SPEED_400G = 0x200, 9166f443ebcSRyan Zezeski } enahw_link_speeds_t; 9176f443ebcSRyan Zezeski 9186f443ebcSRyan Zezeski /* 9196f443ebcSRyan Zezeski * Response to ENAHW_FEAT_HW_HINTS. 9206f443ebcSRyan Zezeski * 9216f443ebcSRyan Zezeski * Hints from the device to the driver about what values to use for 9226f443ebcSRyan Zezeski * various communications between the two. A value of 0 indicates 9236f443ebcSRyan Zezeski * there is no hint and the driver should provide its own default. All 9246f443ebcSRyan Zezeski * timeout values are in milliseconds. 9256f443ebcSRyan Zezeski * 9266f443ebcSRyan Zezeski * common: ena_admin_ena_hw_hints 9276f443ebcSRyan Zezeski */ 928*c46e4de3SAndy Fiddaman 929*c46e4de3SAndy Fiddaman #define ENAHW_HINTS_NO_TIMEOUT 0xffff 930*c46e4de3SAndy Fiddaman 9316f443ebcSRyan Zezeski typedef struct enahw_device_hints { 9326f443ebcSRyan Zezeski /* 9336f443ebcSRyan Zezeski * The amount of time the driver should wait for an MMIO read 9346f443ebcSRyan Zezeski * reply before giving up and returning an error. 9356f443ebcSRyan Zezeski */ 9366f443ebcSRyan Zezeski uint16_t edh_mmio_read_timeout; 9376f443ebcSRyan Zezeski 9386f443ebcSRyan Zezeski /* 9396f443ebcSRyan Zezeski * If the driver has not seen an AENQ keep alive in this 9406f443ebcSRyan Zezeski * timeframe, then consider the device hung and perform a 9416f443ebcSRyan Zezeski * reset. 942*c46e4de3SAndy Fiddaman * common: driver_watchdog_timeout 9436f443ebcSRyan Zezeski */ 9446f443ebcSRyan Zezeski uint16_t edh_keep_alive_timeout; 9456f443ebcSRyan Zezeski 9466f443ebcSRyan Zezeski /* 9476f443ebcSRyan Zezeski * The timeperiod in which we expect a Tx to report 9486f443ebcSRyan Zezeski * completion, otherwise it is considered "missed". Initiate a 9496f443ebcSRyan Zezeski * device reset when the number of missed completions is 9506f443ebcSRyan Zezeski * greater than the threshold. 9516f443ebcSRyan Zezeski */ 9526f443ebcSRyan Zezeski uint16_t edh_tx_comp_timeout; 9536f443ebcSRyan Zezeski uint16_t edh_missed_tx_reset_threshold; 9546f443ebcSRyan Zezeski 9556f443ebcSRyan Zezeski /* 9566f443ebcSRyan Zezeski * The timeperiod in which we expect an admin command to 9576f443ebcSRyan Zezeski * report completion. 9586f443ebcSRyan Zezeski */ 9596f443ebcSRyan Zezeski uint16_t edh_admin_comp_timeout; 9606f443ebcSRyan Zezeski 9616f443ebcSRyan Zezeski /* 9626f443ebcSRyan Zezeski * Used by Linux to set the netdevice 'watchdog_timeo' value. 9636f443ebcSRyan Zezeski * This value is used by the networking stack to determine 9646f443ebcSRyan Zezeski * when a pending transmission has stalled. This is similar to 9656f443ebcSRyan Zezeski * the keep alive timeout, except its viewing progress from 966eebd18daSAndy Fiddaman * the perspective of the network stack itself. This difference 9676f443ebcSRyan Zezeski * is subtle but important: the device could be in a state 9686f443ebcSRyan Zezeski * where it has a functioning keep alive heartbeat, but has a 9696f443ebcSRyan Zezeski * stuck Tx queue impeding forward progress of the networking 9706f443ebcSRyan Zezeski * stack (which in many cases results in a scenario 971*c46e4de3SAndy Fiddaman * indistinguishable from a complete host hang). 9726f443ebcSRyan Zezeski * 9736f443ebcSRyan Zezeski * The mac layer does not currently provide such 9746f443ebcSRyan Zezeski * functionality, though it could and should be extended to 9756f443ebcSRyan Zezeski * support such a feature. 9766f443ebcSRyan Zezeski */ 9776f443ebcSRyan Zezeski uint16_t edh_net_wd_timeout; 9786f443ebcSRyan Zezeski 9796f443ebcSRyan Zezeski /* 9806f443ebcSRyan Zezeski * The maximum number of cookies/segments allowed in a DMA 9816f443ebcSRyan Zezeski * scatter-gather list. 9826f443ebcSRyan Zezeski */ 9836f443ebcSRyan Zezeski uint16_t edh_max_tx_sgl; 9846f443ebcSRyan Zezeski uint16_t edh_max_rx_sgl; 9856f443ebcSRyan Zezeski 9866f443ebcSRyan Zezeski uint16_t reserved[8]; 9876f443ebcSRyan Zezeski } enahw_device_hints_t; 9886f443ebcSRyan Zezeski 9896f443ebcSRyan Zezeski /* 9906f443ebcSRyan Zezeski * Response to ENAHW_FEAT_DEVICE_ATTRIBUTES. 9916f443ebcSRyan Zezeski * 9926f443ebcSRyan Zezeski * common: ena_admin_device_attr_feature_desc 9936f443ebcSRyan Zezeski */ 9946f443ebcSRyan Zezeski typedef struct enahw_feat_dev_attr { 9956f443ebcSRyan Zezeski uint32_t efda_impl_id; 9966f443ebcSRyan Zezeski uint32_t efda_device_version; 9976f443ebcSRyan Zezeski 9986f443ebcSRyan Zezeski /* 9996f443ebcSRyan Zezeski * Bitmap representing supported get/set feature subcommands 10006f443ebcSRyan Zezeski * (enahw_feature_id). 10016f443ebcSRyan Zezeski */ 10026f443ebcSRyan Zezeski uint32_t efda_supported_features; 10036f443ebcSRyan Zezeski 1004eebd18daSAndy Fiddaman /* 1005eebd18daSAndy Fiddaman * Bitmap representing device capabilities. 1006eebd18daSAndy Fiddaman * (enahw_capability_id) 1007eebd18daSAndy Fiddaman */ 1008eebd18daSAndy Fiddaman uint32_t efda_capabilities; 1009eebd18daSAndy Fiddaman 1010eebd18daSAndy Fiddaman /* Number of bits used for physical/virtual address. */ 10116f443ebcSRyan Zezeski uint32_t efda_phys_addr_width; 10126f443ebcSRyan Zezeski uint32_t efda_virt_addr_with; 10136f443ebcSRyan Zezeski 10146f443ebcSRyan Zezeski /* The unicast MAC address in network byte order. */ 10156f443ebcSRyan Zezeski uint8_t efda_mac_addr[6]; 10166f443ebcSRyan Zezeski uint8_t efda_rsvd2[2]; 10176f443ebcSRyan Zezeski uint32_t efda_max_mtu; 10186f443ebcSRyan Zezeski } enahw_feat_dev_attr_t; 10196f443ebcSRyan Zezeski 10206f443ebcSRyan Zezeski /* 10216f443ebcSRyan Zezeski * Response to ENAHW_FEAT_MAX_QUEUES_NUM. 10226f443ebcSRyan Zezeski * 10236f443ebcSRyan Zezeski * common: ena_admin_queue_feature_desc 10246f443ebcSRyan Zezeski */ 10256f443ebcSRyan Zezeski typedef struct enahw_feat_max_queue { 10266f443ebcSRyan Zezeski uint32_t efmq_max_sq_num; 10276f443ebcSRyan Zezeski uint32_t efmq_max_sq_depth; 10286f443ebcSRyan Zezeski uint32_t efmq_max_cq_num; 10296f443ebcSRyan Zezeski uint32_t efmq_max_cq_depth; 10306f443ebcSRyan Zezeski uint32_t efmq_max_legacy_llq_num; 10316f443ebcSRyan Zezeski uint32_t efmq_max_legacy_llq_depth; 10326f443ebcSRyan Zezeski uint32_t efmq_max_header_size; 10336f443ebcSRyan Zezeski 10346f443ebcSRyan Zezeski /* 10356f443ebcSRyan Zezeski * The maximum number of descriptors a single Tx packet may 10366f443ebcSRyan Zezeski * span. This includes the meta descriptor. 10376f443ebcSRyan Zezeski */ 10386f443ebcSRyan Zezeski uint16_t efmq_max_per_packet_tx_descs; 10396f443ebcSRyan Zezeski 10406f443ebcSRyan Zezeski /* 10416f443ebcSRyan Zezeski * The maximum number of descriptors a single Rx packet may span. 10426f443ebcSRyan Zezeski */ 10436f443ebcSRyan Zezeski uint16_t efmq_max_per_packet_rx_descs; 10446f443ebcSRyan Zezeski } enahw_feat_max_queue_t; 10456f443ebcSRyan Zezeski 10466f443ebcSRyan Zezeski /* 10476f443ebcSRyan Zezeski * Response to ENAHW_FEAT_MAX_QUEUES_EXT. 10486f443ebcSRyan Zezeski * 10496f443ebcSRyan Zezeski * common: ena_admin_queue_ext_feature_desc 10506f443ebcSRyan Zezeski */ 10516f443ebcSRyan Zezeski typedef struct enahw_feat_max_queue_ext { 10526f443ebcSRyan Zezeski uint8_t efmqe_version; 10536f443ebcSRyan Zezeski uint8_t efmqe_rsvd[3]; 10546f443ebcSRyan Zezeski 10556f443ebcSRyan Zezeski uint32_t efmqe_max_tx_sq_num; 10566f443ebcSRyan Zezeski uint32_t efmqe_max_tx_cq_num; 10576f443ebcSRyan Zezeski uint32_t efmqe_max_rx_sq_num; 10586f443ebcSRyan Zezeski uint32_t efmqe_max_rx_cq_num; 10596f443ebcSRyan Zezeski uint32_t efmqe_max_tx_sq_depth; 10606f443ebcSRyan Zezeski uint32_t efmqe_max_tx_cq_depth; 10616f443ebcSRyan Zezeski uint32_t efmqe_max_rx_sq_depth; 10626f443ebcSRyan Zezeski uint32_t efmqe_max_rx_cq_depth; 10636f443ebcSRyan Zezeski uint32_t efmqe_max_tx_header_size; 10646f443ebcSRyan Zezeski 10656f443ebcSRyan Zezeski /* 10666f443ebcSRyan Zezeski * The maximum number of descriptors a single Tx packet may 10676f443ebcSRyan Zezeski * span. This includes the meta descriptor. 10686f443ebcSRyan Zezeski */ 10696f443ebcSRyan Zezeski uint16_t efmqe_max_per_packet_tx_descs; 10706f443ebcSRyan Zezeski 10716f443ebcSRyan Zezeski /* 10726f443ebcSRyan Zezeski * The maximum number of descriptors a single Rx packet may span. 10736f443ebcSRyan Zezeski */ 10746f443ebcSRyan Zezeski uint16_t efmqe_max_per_packet_rx_descs; 10756f443ebcSRyan Zezeski } enahw_feat_max_queue_ext_t; 10766f443ebcSRyan Zezeski 10776f443ebcSRyan Zezeski /* 10786f443ebcSRyan Zezeski * Response to ENA_ADMIN_LINK_CONFIG. 10796f443ebcSRyan Zezeski * 10806f443ebcSRyan Zezeski * common: ena_admin_get_feature_link_desc 10816f443ebcSRyan Zezeski */ 10826f443ebcSRyan Zezeski typedef struct enahw_feat_link_conf { 10836f443ebcSRyan Zezeski /* Link speed in Mbit/s. */ 10846f443ebcSRyan Zezeski uint32_t eflc_speed; 10856f443ebcSRyan Zezeski 10866f443ebcSRyan Zezeski /* Bit field of enahw_link_speeds_t. */ 10876f443ebcSRyan Zezeski uint32_t eflc_supported; 10886f443ebcSRyan Zezeski 10896f443ebcSRyan Zezeski /* 10906f443ebcSRyan Zezeski * 31-2: reserved 10916f443ebcSRyan Zezeski * 1: duplex - Full Duplex 10926f443ebcSRyan Zezeski * 0: autoneg 10936f443ebcSRyan Zezeski */ 10946f443ebcSRyan Zezeski uint32_t eflc_flags; 10956f443ebcSRyan Zezeski } enahw_feat_link_conf_t; 10966f443ebcSRyan Zezeski 10976f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONF_AUTONEG_MASK BIT(0) 10986f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONF_DUPLEX_SHIFT 1 10996f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONF_DUPLEX_MASK BIT(1) 11006f443ebcSRyan Zezeski 11016f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONF_AUTONEG(f) \ 11026f443ebcSRyan Zezeski ((f)->eflc_flags & ENAHW_FEAT_LINK_CONF_AUTONEG_MASK) 11036f443ebcSRyan Zezeski 11046f443ebcSRyan Zezeski #define ENAHW_FEAT_LINK_CONF_FULL_DUPLEX(f) \ 11056f443ebcSRyan Zezeski ((((f)->eflc_flags & ENAHW_FEAT_LINK_CONF_DUPLEX_MASK) >> \ 11066f443ebcSRyan Zezeski ENAHW_FEAT_LINK_CONF_DUPLEX_SHIFT) == 1) 11076f443ebcSRyan Zezeski 11086f443ebcSRyan Zezeski /* 11096f443ebcSRyan Zezeski * Response to ENAHW_FEAT_STATELESS_OFFLOAD_CONFIG. 11106f443ebcSRyan Zezeski * 11116f443ebcSRyan Zezeski * common: ena_admin_feature_offload_desc 11126f443ebcSRyan Zezeski */ 11136f443ebcSRyan Zezeski typedef struct enahw_feat_offload { 11146f443ebcSRyan Zezeski /* 11156f443ebcSRyan Zezeski * 0 : Tx IPv4 Header Checksum 11166f443ebcSRyan Zezeski * 1 : Tx L4/IPv4 Partial Checksum 11176f443ebcSRyan Zezeski * 11186f443ebcSRyan Zezeski * The L4 checksum field should be initialized with pseudo 11196f443ebcSRyan Zezeski * header checksum. 11206f443ebcSRyan Zezeski * 11216f443ebcSRyan Zezeski * 2 : Tx L4/IPv4 Checksum Full 11226f443ebcSRyan Zezeski * 3 : Tx L4/IPv6 Partial Checksum 11236f443ebcSRyan Zezeski * 11246f443ebcSRyan Zezeski * The L4 checksum field should be initialized with pseudo 11256f443ebcSRyan Zezeski * header checksum. 11266f443ebcSRyan Zezeski * 11276f443ebcSRyan Zezeski * 4 : Tx L4/IPv6 Checksum Full 11286f443ebcSRyan Zezeski * 5 : TCP/IPv4 LSO (aka TSO) 11296f443ebcSRyan Zezeski * 6 : TCP/IPv6 LSO (aka TSO) 11306f443ebcSRyan Zezeski * 7 : LSO ECN 11316f443ebcSRyan Zezeski */ 11326f443ebcSRyan Zezeski uint32_t efo_tx; 11336f443ebcSRyan Zezeski 11346f443ebcSRyan Zezeski /* 11356f443ebcSRyan Zezeski * Receive side supported stateless offload. 11366f443ebcSRyan Zezeski * 11376f443ebcSRyan Zezeski * 0 : Rx IPv4 Header Checksum 11386f443ebcSRyan Zezeski * 1 : Rx TCP/UDP + IPv4 Full Checksum 11396f443ebcSRyan Zezeski * 2 : Rx TCP/UDP + IPv6 Full Checksum 11406f443ebcSRyan Zezeski * 3 : Rx hash calculation 11416f443ebcSRyan Zezeski */ 11426f443ebcSRyan Zezeski uint32_t efo_rx_supported; 11436f443ebcSRyan Zezeski 11446f443ebcSRyan Zezeski /* Linux seems to only check rx_supported. */ 11456f443ebcSRyan Zezeski uint32_t efo_rx_enabled; 11466f443ebcSRyan Zezeski } enahw_feat_offload_t; 11476f443ebcSRyan Zezeski 11486f443ebcSRyan Zezeski /* Feature Offloads */ 11496f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK BIT(0) 11506f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_SHIFT 1 11516f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 11526f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_SHIFT 2 11536f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 11546f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_SHIFT 3 11556f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 11566f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_SHIFT 4 11576f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 11586f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV4_SHIFT 5 11596f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK BIT(5) 11606f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV6_SHIFT 6 11616f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK BIT(6) 11626f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_ECN_SHIFT 7 11636f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_ECN_MASK BIT(7) 11646f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK BIT(0) 11656f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_SHIFT 1 11666f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK BIT(1) 11676f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_SHIFT 2 11686f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK BIT(2) 11696f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_HASH_SHIFT 3 11706f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_HASH_MASK BIT(3) 11716f443ebcSRyan Zezeski 11726f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM(f) \ 11736f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L3_IPV4_CSUM_MASK) != 0) 11746f443ebcSRyan Zezeski 11756f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART(f) \ 11766f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_PART_MASK) != 0) 11776f443ebcSRyan Zezeski 11786f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL(f) \ 11796f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV4_CSUM_FULL_MASK) != 0) 11806f443ebcSRyan Zezeski 11816f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV4(f) \ 11826f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TSO_IPV4_MASK) != 0) 11836f443ebcSRyan Zezeski 11846f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART(f) \ 11856f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_PART_MASK) != 0) 11866f443ebcSRyan Zezeski 11876f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL(f) \ 11886f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TX_L4_IPV6_CSUM_FULL_MASK) != 0) 11896f443ebcSRyan Zezeski 11906f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_TSO_IPV6(f) \ 11916f443ebcSRyan Zezeski (((f)->efo_tx & ENAHW_FEAT_OFFLOAD_TSO_IPV6_MASK) != 0) 11926f443ebcSRyan Zezeski 11936f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM(f) \ 11946f443ebcSRyan Zezeski (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L3_IPV4_CSUM_MASK) != 0) 11956f443ebcSRyan Zezeski 11966f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM(f) \ 11976f443ebcSRyan Zezeski (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L4_IPV4_CSUM_MASK) != 0) 11986f443ebcSRyan Zezeski 11996f443ebcSRyan Zezeski #define ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM(f) \ 12006f443ebcSRyan Zezeski (((f)->efo_rx_supported & ENAHW_FEAT_OFFLOAD_RX_L4_IPV6_CSUM_MASK) != 0) 12016f443ebcSRyan Zezeski 12026f443ebcSRyan Zezeski typedef union enahw_resp_get_feat { 12036f443ebcSRyan Zezeski uint32_t ergf_raw[14]; 12046f443ebcSRyan Zezeski enahw_feat_dev_attr_t ergf_dev_attr; 12056f443ebcSRyan Zezeski enahw_feat_max_queue_t ergf_max_queue; 12066f443ebcSRyan Zezeski enahw_feat_max_queue_ext_t ergf_max_queue_ext; 12076f443ebcSRyan Zezeski enahw_feat_aenq_t ergf_aenq; 12086f443ebcSRyan Zezeski enahw_feat_link_conf_t ergf_link_conf; 12096f443ebcSRyan Zezeski enahw_feat_offload_t ergf_offload; 1210*c46e4de3SAndy Fiddaman enahw_device_hints_t ergf_hints; 12116f443ebcSRyan Zezeski } enahw_resp_get_feat_u; 12126f443ebcSRyan Zezeski 12136f443ebcSRyan Zezeski /* 12146f443ebcSRyan Zezeski * common: ena_admin_acq_create_cq_resp_desc 12156f443ebcSRyan Zezeski */ 12166f443ebcSRyan Zezeski typedef struct enahw_resp_create_cq { 12176f443ebcSRyan Zezeski /* 12186f443ebcSRyan Zezeski * The hardware's index for this queue. 12196f443ebcSRyan Zezeski */ 12206f443ebcSRyan Zezeski uint16_t ercq_idx; 12216f443ebcSRyan Zezeski 12226f443ebcSRyan Zezeski /* 12236f443ebcSRyan Zezeski * Apparently the number of descriptors granted may be 12246f443ebcSRyan Zezeski * different than that requested. 12256f443ebcSRyan Zezeski */ 12266f443ebcSRyan Zezeski uint16_t ercq_actual_num_descs; 12276f443ebcSRyan Zezeski uint32_t ercq_numa_node_reg_offset; 122813776732SAndy Fiddaman /* CQ doorbell register - no longer supported by any ENA adapter */ 122913776732SAndy Fiddaman uint32_t ercq_head_db_reg_offset; 12306f443ebcSRyan Zezeski uint32_t ercq_interrupt_mask_reg_offset; /* stop intr */ 12316f443ebcSRyan Zezeski } enahw_resp_create_cq_t; 12326f443ebcSRyan Zezeski 12336f443ebcSRyan Zezeski /* common: ena_admin_acq_create_sq_resp_desc */ 12346f443ebcSRyan Zezeski typedef struct enahw_resp_create_sq { 12356f443ebcSRyan Zezeski uint16_t ersq_idx; 12366f443ebcSRyan Zezeski uint16_t ersq_rsvdw1; 12376f443ebcSRyan Zezeski uint32_t ersq_db_reg_offset; 12386f443ebcSRyan Zezeski uint32_t ersq_llq_descs_reg_offset; 12396f443ebcSRyan Zezeski uint32_t ersq_llq_headers_reg_offset; 12406f443ebcSRyan Zezeski } enahw_resp_create_sq_t; 12416f443ebcSRyan Zezeski 12426f443ebcSRyan Zezeski /* common: ena_admin_basic_stats */ 12436f443ebcSRyan Zezeski typedef struct enahw_resp_basic_stats { 12446f443ebcSRyan Zezeski uint32_t erbs_tx_bytes_low; 12456f443ebcSRyan Zezeski uint32_t erbs_tx_bytes_high; 12466f443ebcSRyan Zezeski uint32_t erbs_tx_pkts_low; 12476f443ebcSRyan Zezeski uint32_t erbs_tx_pkts_high; 12486f443ebcSRyan Zezeski uint32_t erbs_rx_bytes_low; 12496f443ebcSRyan Zezeski uint32_t erbs_rx_bytes_high; 12506f443ebcSRyan Zezeski uint32_t erbs_rx_pkts_low; 12516f443ebcSRyan Zezeski uint32_t erbs_rx_pkts_high; 12526f443ebcSRyan Zezeski uint32_t erbs_rx_drops_low; 12536f443ebcSRyan Zezeski uint32_t erbs_rx_drops_high; 12546f443ebcSRyan Zezeski uint32_t erbs_tx_drops_low; 12556f443ebcSRyan Zezeski uint32_t erbs_tx_drops_high; 1256*c46e4de3SAndy Fiddaman uint32_t erbs_rx_overruns_low; 1257*c46e4de3SAndy Fiddaman uint32_t erbs_rx_overruns_high; 12586f443ebcSRyan Zezeski } enahw_resp_basic_stats_t; 12596f443ebcSRyan Zezeski 12606f443ebcSRyan Zezeski /* common: ena_admin_eni_stats */ 12616f443ebcSRyan Zezeski typedef struct enahw_resp_eni_stats { 12626f443ebcSRyan Zezeski /* 12636f443ebcSRyan Zezeski * The number of inbound packets dropped due to aggregate 12646f443ebcSRyan Zezeski * inbound bandwidth allowance being exceeded. 12656f443ebcSRyan Zezeski */ 12666f443ebcSRyan Zezeski uint64_t eres_bw_in_exceeded; 12676f443ebcSRyan Zezeski 12686f443ebcSRyan Zezeski /* 12696f443ebcSRyan Zezeski * The number of outbound packets dropped due to aggregated outbound 12706f443ebcSRyan Zezeski * bandwidth allowance being exceeded. 12716f443ebcSRyan Zezeski */ 12726f443ebcSRyan Zezeski uint64_t eres_bw_out_exceeded; 12736f443ebcSRyan Zezeski 12746f443ebcSRyan Zezeski /* 12756f443ebcSRyan Zezeski * The number of packets dropped due to the Packets Per Second 12766f443ebcSRyan Zezeski * allowance being exceeded. 12776f443ebcSRyan Zezeski */ 12786f443ebcSRyan Zezeski uint64_t eres_pps_exceeded; 12796f443ebcSRyan Zezeski 12806f443ebcSRyan Zezeski /* 12816f443ebcSRyan Zezeski * The number of packets dropped due to connection tracking 12826f443ebcSRyan Zezeski * allowance being exceeded and leading to failure in 12836f443ebcSRyan Zezeski * establishment of new connections. 12846f443ebcSRyan Zezeski */ 12856f443ebcSRyan Zezeski uint64_t eres_conns_exceeded; 12866f443ebcSRyan Zezeski 12876f443ebcSRyan Zezeski /* 12886f443ebcSRyan Zezeski * The number of packets dropped due to linklocal packet rate 12896f443ebcSRyan Zezeski * allowance being exceeded. 12906f443ebcSRyan Zezeski */ 12916f443ebcSRyan Zezeski uint64_t eres_linklocal_exceeded; 12926f443ebcSRyan Zezeski } enahw_resp_eni_stats_t; 12936f443ebcSRyan Zezeski 12946f443ebcSRyan Zezeski /* 12956f443ebcSRyan Zezeski * common: ena_admin_acq_entry 12966f443ebcSRyan Zezeski */ 12976f443ebcSRyan Zezeski typedef struct enahw_resp_desc { 12986f443ebcSRyan Zezeski /* The index of the completed command. */ 12996f443ebcSRyan Zezeski uint16_t erd_cmd_id; 13006f443ebcSRyan Zezeski 13016f443ebcSRyan Zezeski /* The status of the command (enahw_resp_status_t). */ 13026f443ebcSRyan Zezeski uint8_t erd_status; 13036f443ebcSRyan Zezeski 13046f443ebcSRyan Zezeski /* 13056f443ebcSRyan Zezeski * 7-1 Reserved 13066f443ebcSRyan Zezeski * 0 Phase 13076f443ebcSRyan Zezeski */ 13086f443ebcSRyan Zezeski uint8_t erd_flags; 13096f443ebcSRyan Zezeski 13106f443ebcSRyan Zezeski /* Extended status. */ 13116f443ebcSRyan Zezeski uint16_t erd_ext_status; 13126f443ebcSRyan Zezeski 13136f443ebcSRyan Zezeski /* 13146f443ebcSRyan Zezeski * The AQ entry (enahw_cmd_desc) index which has been consumed 13156f443ebcSRyan Zezeski * by the device and can be reused. However, this field is not 13166f443ebcSRyan Zezeski * used in the other drivers, and it seems to be redundant 13176f443ebcSRyan Zezeski * with the erd_idx field. 13186f443ebcSRyan Zezeski */ 13196f443ebcSRyan Zezeski uint16_t erd_sq_head_idx; 13206f443ebcSRyan Zezeski 13216f443ebcSRyan Zezeski union { 13226f443ebcSRyan Zezeski uint32_t raw[14]; 13236f443ebcSRyan Zezeski enahw_resp_get_feat_u erd_get_feat; 13246f443ebcSRyan Zezeski enahw_resp_create_cq_t erd_create_cq; 13256f443ebcSRyan Zezeski /* destroy_cq: No command-specific response. */ 13266f443ebcSRyan Zezeski enahw_resp_create_sq_t erd_create_sq; 13276f443ebcSRyan Zezeski /* destroy_sq: No command-specific response. */ 13286f443ebcSRyan Zezeski enahw_resp_basic_stats_t erd_basic_stats; 13296f443ebcSRyan Zezeski enahw_resp_eni_stats_t erd_eni_stats; 13306f443ebcSRyan Zezeski } erd_resp; 13316f443ebcSRyan Zezeski } enahw_resp_desc_t; 13326f443ebcSRyan Zezeski 13336f443ebcSRyan Zezeski /* common: ENA_ADMIN_ACQ_COMMON_DESC */ 13346f443ebcSRyan Zezeski #define ENAHW_RESP_CMD_ID_MASK GENMASK(11, 0) 13356f443ebcSRyan Zezeski #define ENAHW_RESP_PHASE_MASK 0x1 13366f443ebcSRyan Zezeski 13376f443ebcSRyan Zezeski #define ENAHW_RESP_CMD_ID(desc) \ 13386f443ebcSRyan Zezeski (((desc)->erd_cmd_id) & ENAHW_RESP_CMD_ID_MASK) 13396f443ebcSRyan Zezeski 13406f443ebcSRyan Zezeski /* 13416f443ebcSRyan Zezeski * The response status of an Admin Queue command. 13426f443ebcSRyan Zezeski * 13436f443ebcSRyan Zezeski * common: ena_admin_aq_completion_status 13446f443ebcSRyan Zezeski */ 13456f443ebcSRyan Zezeski typedef enum enahw_resp_status { 13466f443ebcSRyan Zezeski ENAHW_RESP_SUCCESS = 0, 13476f443ebcSRyan Zezeski ENAHW_RESP_RESOURCE_ALLOCATION_FAILURE = 1, 13486f443ebcSRyan Zezeski ENAHW_RESP_BAD_OPCODE = 2, 13496f443ebcSRyan Zezeski ENAHW_RESP_UNSUPPORTED_OPCODE = 3, 13506f443ebcSRyan Zezeski ENAHW_RESP_MALFORMED_REQUEST = 4, 13516f443ebcSRyan Zezeski /* 13526f443ebcSRyan Zezeski * At this place in the common code it mentions that there is 1353eebd18daSAndy Fiddaman * "additional status" in the response descriptor's 13546f443ebcSRyan Zezeski * erd_ext_status field. As the common code never actually 13556f443ebcSRyan Zezeski * uses this field it's hard to know the exact meaning of the 13566f443ebcSRyan Zezeski * comment. My best guess is the illegal parameter error 13576f443ebcSRyan Zezeski * stores additional context in the erd_ext_status field. But 13586f443ebcSRyan Zezeski * how to interpret that additional context is anyone's guess. 13596f443ebcSRyan Zezeski */ 13606f443ebcSRyan Zezeski ENAHW_RESP_ILLEGAL_PARAMETER = 5, 13616f443ebcSRyan Zezeski ENAHW_RESP_UNKNOWN_ERROR = 6, 13626f443ebcSRyan Zezeski ENAHW_RESP_RESOURCE_BUSY = 7, 13636f443ebcSRyan Zezeski } enahw_resp_status_t; 13646f443ebcSRyan Zezeski 13656f443ebcSRyan Zezeski /* 1366eebd18daSAndy Fiddaman * I/O macros and structures. 13676f443ebcSRyan Zezeski * ------------------------- 13686f443ebcSRyan Zezeski */ 13696f443ebcSRyan Zezeski 13706f443ebcSRyan Zezeski /* 13716f443ebcSRyan Zezeski * The device's L3 and L4 protocol numbers. These are specific to the 13726f443ebcSRyan Zezeski * ENA device and not to be confused with IANA protocol numbers. 13736f443ebcSRyan Zezeski * 13746f443ebcSRyan Zezeski * common: ena_eth_io_l3_proto_index 13756f443ebcSRyan Zezeski */ 13766f443ebcSRyan Zezeski typedef enum enahw_io_l3_proto { 13776f443ebcSRyan Zezeski ENAHW_IO_L3_PROTO_UNKNOWN = 0, 13786f443ebcSRyan Zezeski ENAHW_IO_L3_PROTO_IPV4 = 8, 13796f443ebcSRyan Zezeski ENAHW_IO_L3_PROTO_IPV6 = 11, 13806f443ebcSRyan Zezeski ENAHW_IO_L3_PROTO_FCOE = 21, 13816f443ebcSRyan Zezeski ENAHW_IO_L3_PROTO_ROCE = 22, 13826f443ebcSRyan Zezeski } enahw_io_l3_proto_t; 13836f443ebcSRyan Zezeski 13846f443ebcSRyan Zezeski /* common: ena_eth_io_l4_proto_index */ 13856f443ebcSRyan Zezeski typedef enum enahw_io_l4_proto { 13866f443ebcSRyan Zezeski ENAHW_IO_L4_PROTO_UNKNOWN = 0, 13876f443ebcSRyan Zezeski ENAHW_IO_L4_PROTO_TCP = 12, 13886f443ebcSRyan Zezeski ENAHW_IO_L4_PROTO_UDP = 13, 13896f443ebcSRyan Zezeski ENAHW_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 13906f443ebcSRyan Zezeski } enahw_io_l4_proto_t; 13916f443ebcSRyan Zezeski 13926f443ebcSRyan Zezeski /* common: ena_eth_io_tx_desc */ 13936f443ebcSRyan Zezeski typedef struct enahw_tx_data_desc { 13946f443ebcSRyan Zezeski /* 13956f443ebcSRyan Zezeski * 15-0 Buffer Length (LENGTH) 13966f443ebcSRyan Zezeski * 13976f443ebcSRyan Zezeski * The buffer length in bytes. This should NOT include the 13986f443ebcSRyan Zezeski * Ethernet FCS bytes. 13996f443ebcSRyan Zezeski * 14006f443ebcSRyan Zezeski * 21-16 Request ID High Bits [15-10] (REQ_ID_HI) 14016f443ebcSRyan Zezeski * 22 Reserved Zero 14026f443ebcSRyan Zezeski * 23 Metadata Flag always zero (META_DESC) 14036f443ebcSRyan Zezeski * 14046f443ebcSRyan Zezeski * This flag indicates if the descriptor is a metadata 14056f443ebcSRyan Zezeski * descriptor or not. In this case we are defining the Tx 14066f443ebcSRyan Zezeski * descriptor, so it's always zero. 14076f443ebcSRyan Zezeski * 14086f443ebcSRyan Zezeski * 24 Phase bit (PHASE) 14096f443ebcSRyan Zezeski * 25 Reserved Zero 14106f443ebcSRyan Zezeski * 26 First Descriptor Bit (FIRST) 14116f443ebcSRyan Zezeski * 14126f443ebcSRyan Zezeski * Indicates this is the first descriptor for the frame. 14136f443ebcSRyan Zezeski * 14146f443ebcSRyan Zezeski * 27 Last Descriptor Bit (LAST) 14156f443ebcSRyan Zezeski * 14166f443ebcSRyan Zezeski * Indicates this is the last descriptor for the frame. 14176f443ebcSRyan Zezeski * 14186f443ebcSRyan Zezeski * 28 Completion Request Bit (COMP_REQ) 14196f443ebcSRyan Zezeski * 14206f443ebcSRyan Zezeski * Indicates if completion should be posted after the 14216f443ebcSRyan Zezeski * frame is transmitted. This bit is only valid on the 14226f443ebcSRyan Zezeski * first descriptor. 14236f443ebcSRyan Zezeski * 14246f443ebcSRyan Zezeski * 31-29 Reserved Zero 14256f443ebcSRyan Zezeski */ 14266f443ebcSRyan Zezeski uint32_t etd_len_ctrl; 14276f443ebcSRyan Zezeski 14286f443ebcSRyan Zezeski /* 14296f443ebcSRyan Zezeski * 3-0 L3 Protocol Number (L3_PROTO_IDX) 14306f443ebcSRyan Zezeski * 14316f443ebcSRyan Zezeski * The L3 protocol type, one of enahw_io_l3_proto_t. This 14326f443ebcSRyan Zezeski * field is required when L3_CSUM_EN or TSO_EN is set. 14336f443ebcSRyan Zezeski * 14346f443ebcSRyan Zezeski * 4 Don't Fragment Bit (DF) 14356f443ebcSRyan Zezeski * 14366f443ebcSRyan Zezeski * The value of IPv4 DF. This value must copy the value 14376f443ebcSRyan Zezeski * found in the packet's IPv4 header. 14386f443ebcSRyan Zezeski * 14396f443ebcSRyan Zezeski * 6-5 Reserved Zero 14406f443ebcSRyan Zezeski * 7 TSO Bit (TSO_EN) 14416f443ebcSRyan Zezeski * 14426f443ebcSRyan Zezeski * Enable TCP Segment Offload. 14436f443ebcSRyan Zezeski * 14446f443ebcSRyan Zezeski * 12-8 L4 Protocol Number (L4_PROTO_IDX) 14456f443ebcSRyan Zezeski * 14466f443ebcSRyan Zezeski * The L4 protocol type, one of enahw_io_l4_proto_t. This 14476f443ebcSRyan Zezeski * field is required when L4_CSUM_EN or TSO_EN are 14486f443ebcSRyan Zezeski * set. 14496f443ebcSRyan Zezeski * 14506f443ebcSRyan Zezeski * 13 L3 Checksum Offload (L3_CSUM_EN) 14516f443ebcSRyan Zezeski * 14526f443ebcSRyan Zezeski * Enable IPv4 header checksum offload. 14536f443ebcSRyan Zezeski * 14546f443ebcSRyan Zezeski * 14 L4 Checksum Offload (L4_CSUM_EN) 14556f443ebcSRyan Zezeski * 14566f443ebcSRyan Zezeski * Enable TCP/UDP checksum offload. 14576f443ebcSRyan Zezeski * 14586f443ebcSRyan Zezeski * 15 Ethernet FCS Disable (ETHERNET_FCS_DIS) 14596f443ebcSRyan Zezeski * 14606f443ebcSRyan Zezeski * Disable the device's Ethernet Frame Check sequence. 14616f443ebcSRyan Zezeski * 14626f443ebcSRyan Zezeski * 16 Reserved Zero 14636f443ebcSRyan Zezeski * 17 L4 Partial Checksum Present (L4_CSUM_PARTIAL) 14646f443ebcSRyan Zezeski * 14656f443ebcSRyan Zezeski * When set it indicates the host has already provided 14666f443ebcSRyan Zezeski * the pseudo-header checksum. Otherwise, it is up to the 14676f443ebcSRyan Zezeski * device to calculate it. 14686f443ebcSRyan Zezeski * 14696f443ebcSRyan Zezeski * When set and using TSO the host stack must remember 14706f443ebcSRyan Zezeski * not to include the TCP segment length in the supplied 14716f443ebcSRyan Zezeski * pseudo-header. 14726f443ebcSRyan Zezeski * 14736f443ebcSRyan Zezeski * The host stack should provide the pseudo-header 14746f443ebcSRyan Zezeski * checksum when using IPv6 with Routing Headers. 14756f443ebcSRyan Zezeski * 14766f443ebcSRyan Zezeski * 21-18 Reserved Zero 14776f443ebcSRyan Zezeski * 31-22 Request ID Low [9-0] (REQ_ID_LO) 14786f443ebcSRyan Zezeski */ 14796f443ebcSRyan Zezeski uint32_t etd_meta_ctrl; 14806f443ebcSRyan Zezeski 14816f443ebcSRyan Zezeski /* The low 32 bits of the buffer address. */ 14826f443ebcSRyan Zezeski uint32_t etd_buff_addr_lo; 14836f443ebcSRyan Zezeski 14846f443ebcSRyan Zezeski /* 14856f443ebcSRyan Zezeski * address high and header size 14866f443ebcSRyan Zezeski * 14876f443ebcSRyan Zezeski * 15-0 Buffer Address High [47-32] (ADDR_HI) 14886f443ebcSRyan Zezeski * 14896f443ebcSRyan Zezeski * The upper 15 bits of the buffer address. 14906f443ebcSRyan Zezeski * 14916f443ebcSRyan Zezeski * 23-16 Reserved Zero 14926f443ebcSRyan Zezeski * 31-24 Header Length (HEADER_LENGTH) 14936f443ebcSRyan Zezeski * 14946f443ebcSRyan Zezeski * This field has dubious documentation in the 14956f443ebcSRyan Zezeski * common/Linux driver code, even contradicting itself in 14966f443ebcSRyan Zezeski * the same sentence. Here's what it says, verbatim: 14976f443ebcSRyan Zezeski * 14986f443ebcSRyan Zezeski * > Header length. For Low Latency Queues, this fields 14996f443ebcSRyan Zezeski * > indicates the number of bytes written to the 15006f443ebcSRyan Zezeski * > headers' memory. For normal queues, if packet is TCP 15016f443ebcSRyan Zezeski * > or UDP, and longer than max_header_size, then this 15026f443ebcSRyan Zezeski * > field should be set to the sum of L4 header offset 15036f443ebcSRyan Zezeski * > and L4 header size(without options), otherwise, this 15046f443ebcSRyan Zezeski * > field should be set to 0. For both modes, this field 15056f443ebcSRyan Zezeski * > must not exceed the max_header_size. max_header_size 15066f443ebcSRyan Zezeski * > value is reported by the Max Queues Feature 15076f443ebcSRyan Zezeski * > descriptor 15086f443ebcSRyan Zezeski * 15096f443ebcSRyan Zezeski * Here's what one _might_ ascertain from the above. 15106f443ebcSRyan Zezeski * 15116f443ebcSRyan Zezeski * 1. This field should always be set in the case of 15126f443ebcSRyan Zezeski * LLQs/device placement. 15136f443ebcSRyan Zezeski * 15146f443ebcSRyan Zezeski * 2. This field must _never_ exceed the max header size 15156f443ebcSRyan Zezeski * as reported by feature detection. In our code this 15166f443ebcSRyan Zezeski * would be efmq_max_header_size for older ENA devices 15176f443ebcSRyan Zezeski * and efmqe_max_tx_header_size for newer ones. One 15186f443ebcSRyan Zezeski * empirical data point from a t3.small (with newer 15196f443ebcSRyan Zezeski * device) is a max Tx header size of 128 bytes. 15206f443ebcSRyan Zezeski * 15216f443ebcSRyan Zezeski * 3. If the packet is TCP or UDP, and the packet (or the 15226f443ebcSRyan Zezeski * headers?) is longer than the max header size, then 15236f443ebcSRyan Zezeski * this field should be set to the total header size 15246f443ebcSRyan Zezeski * with the exception of TCP header options. 15256f443ebcSRyan Zezeski * Otherwise, if the packet is not TCP or UDP, or if 15266f443ebcSRyan Zezeski * the packet (or header length?) _does not_ exceed 15276f443ebcSRyan Zezeski * the max header size, then set this value to 0. 15286f443ebcSRyan Zezeski * 15296f443ebcSRyan Zezeski * One might think, based on (3), that when the header 15306f443ebcSRyan Zezeski * size exceeds the max this field needs to be set, but 15316f443ebcSRyan Zezeski * that contradicts (2), which dictates that the total 15326f443ebcSRyan Zezeski * header size can never exceed the max. Sure enough, the 15336f443ebcSRyan Zezeski * Linux code drops all packets with headers that exceed 15346f443ebcSRyan Zezeski * the max. So in that case it would mean that "and 15356f443ebcSRyan Zezeski * longer than max_header_size" is referring to the total 15366f443ebcSRyan Zezeski * packet length. So for most workloads, the TCP/UDP 15376f443ebcSRyan Zezeski * packets should have this field set, to indicate their 15386f443ebcSRyan Zezeski * header length. This matches with Linux, which seems to 15396f443ebcSRyan Zezeski * set header length regardless of IP protocol. 15406f443ebcSRyan Zezeski * 15416f443ebcSRyan Zezeski * However, the FreeBSD code tells a different story. In 15426f443ebcSRyan Zezeski * it's non-LLQ Tx path it has the following comment, 15436f443ebcSRyan Zezeski * verbatim: 15446f443ebcSRyan Zezeski * 15456f443ebcSRyan Zezeski * > header_len is just a hint for the device. Because 15466f443ebcSRyan Zezeski * > FreeBSD is not giving us information about packet 15476f443ebcSRyan Zezeski * > header length and it is not guaranteed that all 15486f443ebcSRyan Zezeski * > packet headers will be in the 1st mbuf, setting 15496f443ebcSRyan Zezeski * > header_len to 0 is making the device ignore this 15506f443ebcSRyan Zezeski * > value and resolve header on it's own. 15516f443ebcSRyan Zezeski * 15526f443ebcSRyan Zezeski * According to this we can just set the value to zero 15536f443ebcSRyan Zezeski * and let the device figure it out. This maps better to 15546f443ebcSRyan Zezeski * illumos, where we also allow the header to potentially 15556f443ebcSRyan Zezeski * span multiple mblks (though we do have access to the 15566f443ebcSRyan Zezeski * header sizes via mac_ether_offload_info_t). 15576f443ebcSRyan Zezeski * 15586f443ebcSRyan Zezeski * The upshot: for now we take advantage of the device's 15596f443ebcSRyan Zezeski * ability to determine the header length on its own, at 15606f443ebcSRyan Zezeski * the potential cost of some performance (not measured). 15616f443ebcSRyan Zezeski */ 15626f443ebcSRyan Zezeski uint32_t etd_buff_addr_hi_hdr_sz; 15636f443ebcSRyan Zezeski } enahw_tx_data_desc_t; 15646f443ebcSRyan Zezeski 15656f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LENGTH_MASK GENMASK(15, 0) 15666f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQ_ID_HI_SHIFT 16 15676f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 15686f443ebcSRyan Zezeski #define ENAHW_TX_DESC_META_DESC_SHIFT 23 15696f443ebcSRyan Zezeski #define ENAHW_TX_DESC_META_DESC_MASK BIT(23) 15706f443ebcSRyan Zezeski #define ENAHW_TX_DESC_PHASE_SHIFT 24 15716f443ebcSRyan Zezeski #define ENAHW_TX_DESC_PHASE_MASK BIT(24) 15726f443ebcSRyan Zezeski #define ENAHW_TX_DESC_FIRST_SHIFT 26 15736f443ebcSRyan Zezeski #define ENAHW_TX_DESC_FIRST_MASK BIT(26) 15746f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LAST_SHIFT 27 15756f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LAST_MASK BIT(27) 15766f443ebcSRyan Zezeski #define ENAHW_TX_DESC_COMP_REQ_SHIFT 28 15776f443ebcSRyan Zezeski #define ENAHW_TX_DESC_COMP_REQ_MASK BIT(28) 15786f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 15796f443ebcSRyan Zezeski #define ENAHW_TX_DESC_DF_SHIFT 4 15806f443ebcSRyan Zezeski #define ENAHW_TX_DESC_DF_MASK BIT(4) 15816f443ebcSRyan Zezeski #define ENAHW_TX_DESC_TSO_EN_SHIFT 7 15826f443ebcSRyan Zezeski #define ENAHW_TX_DESC_TSO_EN_MASK BIT(7) 15836f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_PROTO_IDX_SHIFT 8 15846f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 15856f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L3_CSUM_EN_SHIFT 13 15866f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L3_CSUM_EN_MASK BIT(13) 15876f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_EN_SHIFT 14 15886f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_EN_MASK BIT(14) 15896f443ebcSRyan Zezeski #define ENAHW_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 15906f443ebcSRyan Zezeski #define ENAHW_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 15916f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 15926f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 15936f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQ_ID_LO_SHIFT 22 15946f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 15956f443ebcSRyan Zezeski #define ENAHW_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 15966f443ebcSRyan Zezeski #define ENAHW_TX_DESC_HEADER_LENGTH_SHIFT 24 15976f443ebcSRyan Zezeski #define ENAHW_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 15986f443ebcSRyan Zezeski 15996f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LENGTH(desc, len) \ 16006f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= ((len) & ENAHW_TX_DESC_LENGTH_MASK)) 16016f443ebcSRyan Zezeski 16026f443ebcSRyan Zezeski #define ENAHW_TX_DESC_FIRST_ON(desc) \ 16036f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_FIRST_MASK) 16046f443ebcSRyan Zezeski 16056f443ebcSRyan Zezeski #define ENAHW_TX_DESC_FIRST_OFF(desc) \ 16066f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_FIRST_MASK) 16076f443ebcSRyan Zezeski 16086f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQID_HI(desc, reqid) \ 16096f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= \ 16106f443ebcSRyan Zezeski ((((reqid) >> 10) << ENAHW_TX_DESC_REQ_ID_HI_SHIFT) & \ 16116f443ebcSRyan Zezeski ENAHW_TX_DESC_REQ_ID_HI_MASK)) 16126f443ebcSRyan Zezeski 16136f443ebcSRyan Zezeski #define ENAHW_TX_DESC_REQID_LO(desc, reqid) \ 16146f443ebcSRyan Zezeski (((desc)->etd_meta_ctrl) |= \ 16156f443ebcSRyan Zezeski (((reqid) << ENAHW_TX_DESC_REQ_ID_LO_SHIFT) & \ 16166f443ebcSRyan Zezeski ENAHW_TX_DESC_REQ_ID_LO_MASK)) 16176f443ebcSRyan Zezeski 16186f443ebcSRyan Zezeski #define ENAHW_TX_DESC_PHASE(desc, phase) \ 16196f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= (((phase) << ENAHW_TX_DESC_PHASE_SHIFT) & \ 16206f443ebcSRyan Zezeski ENAHW_TX_DESC_PHASE_MASK)) 16216f443ebcSRyan Zezeski 16226f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LAST_ON(desc) \ 16236f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_LAST_MASK) 16246f443ebcSRyan Zezeski 16256f443ebcSRyan Zezeski #define ENAHW_TX_DESC_LAST_OFF(desc) \ 16266f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_LAST_MASK) 16276f443ebcSRyan Zezeski 16286f443ebcSRyan Zezeski #define ENAHW_TX_DESC_COMP_REQ_ON(desc) \ 16296f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_COMP_REQ_MASK) 16306f443ebcSRyan Zezeski 16316f443ebcSRyan Zezeski #define ENAHW_TX_DESC_COMP_REQ_OFF(desc) \ 16326f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_COMP_REQ_MASK) 16336f443ebcSRyan Zezeski 16346f443ebcSRyan Zezeski #define ENAHW_TX_DESC_META_DESC_ON(desc) \ 16356f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) |= ENAHW_TX_DESC_META_DESC_MASK) 16366f443ebcSRyan Zezeski 16376f443ebcSRyan Zezeski #define ENAHW_TX_DESC_META_DESC_OFF(desc) \ 16386f443ebcSRyan Zezeski (((desc)->etd_len_ctrl) &= ~ENAHW_TX_DESC_META_DESC_MASK) 16396f443ebcSRyan Zezeski 16406f443ebcSRyan Zezeski #define ENAHW_TX_DESC_ADDR_LO(desc, addr) \ 16416f443ebcSRyan Zezeski (((desc)->etd_buff_addr_lo) = (addr)) 16426f443ebcSRyan Zezeski 16436f443ebcSRyan Zezeski #define ENAHW_TX_DESC_ADDR_HI(desc, addr) \ 16446f443ebcSRyan Zezeski (((desc)->etd_buff_addr_hi_hdr_sz) |= \ 16456f443ebcSRyan Zezeski (((addr) >> 32) & ENAHW_TX_DESC_ADDR_HI_MASK)) 16466f443ebcSRyan Zezeski 16476f443ebcSRyan Zezeski #define ENAHW_TX_DESC_HEADER_LENGTH(desc, len) \ 16486f443ebcSRyan Zezeski (((desc)->etd_buff_addr_hi_hdr_sz) |= \ 16496f443ebcSRyan Zezeski (((len) << ENAHW_TX_DESC_HEADER_LENGTH_SHIFT) & \ 16506f443ebcSRyan Zezeski ENAHW_TX_DESC_HEADER_LENGTH_MASK)) 16516f443ebcSRyan Zezeski 16526f443ebcSRyan Zezeski #define ENAHW_TX_DESC_DF_ON(desc) \ 16536f443ebcSRyan Zezeski ((desc)->etd_meta_ctrl |= ENAHW_TX_DESC_DF_MASK) 16546f443ebcSRyan Zezeski 16556f443ebcSRyan Zezeski #define ENAHW_TX_DESC_TSO_OFF(desc) \ 16566f443ebcSRyan Zezeski (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_TSO_EN_MASK) 16576f443ebcSRyan Zezeski 16586f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L3_CSUM_OFF(desc) \ 16596f443ebcSRyan Zezeski (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L3_CSUM_EN_MASK) 16606f443ebcSRyan Zezeski 16616f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_OFF(desc) \ 16626f443ebcSRyan Zezeski (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_EN_MASK) 16636f443ebcSRyan Zezeski 16646f443ebcSRyan Zezeski #define ENAHW_TX_DESC_L4_CSUM_PARTIAL_ON(desc) \ 16656f443ebcSRyan Zezeski (((desc)->etd_meta_ctrl) &= ~ENAHW_TX_DESC_L4_CSUM_PARTIAL_MASK) 16666f443ebcSRyan Zezeski 16676f443ebcSRyan Zezeski /* common: ena_eth_io_tx_meta_desc */ 16686f443ebcSRyan Zezeski typedef struct enahw_tx_meta_desc { 16696f443ebcSRyan Zezeski /* 16706f443ebcSRyan Zezeski * 9-0 Request ID Low [9-0] (REQ_ID_LO) 16716f443ebcSRyan Zezeski * 13-10 Reserved Zero 16726f443ebcSRyan Zezeski * 14 Extended Metadata Valid (EXT_VALID) 16736f443ebcSRyan Zezeski * 16746f443ebcSRyan Zezeski * When set this descriptor contains valid extended 16756f443ebcSRyan Zezeski * metadata. The extended metadata includes the L3/L4 16766f443ebcSRyan Zezeski * length and offset fields as well as the MSS bits. This 16776f443ebcSRyan Zezeski * is needed for TSO. 16786f443ebcSRyan Zezeski * 16796f443ebcSRyan Zezeski * 15 Reserved Zero 16806f443ebcSRyan Zezeski * 19-16 MSS High Bits (MSS_HI) 16816f443ebcSRyan Zezeski * 20 Meta Type (ETH_META_TYPE) 16826f443ebcSRyan Zezeski * 16836f443ebcSRyan Zezeski * If enabled this is an extended metadata descriptor. 16846f443ebcSRyan Zezeski * This seems redundant with EXT_VALID. 16856f443ebcSRyan Zezeski * 16866f443ebcSRyan Zezeski * 21 Meta Store (META_STORE) 16876f443ebcSRyan Zezeski * 16886f443ebcSRyan Zezeski * Store the extended metadata in the queue cache. 16896f443ebcSRyan Zezeski * 16906f443ebcSRyan Zezeski * 22 Reserved Zero 16916f443ebcSRyan Zezeski * 23 Metadata Flag (META_DESC) -- always one 16926f443ebcSRyan Zezeski * 24 Phase (PHASE) 16936f443ebcSRyan Zezeski * 25 Reserved Zero 16946f443ebcSRyan Zezeski * 26 First Descriptor Bit (FIRST) 16956f443ebcSRyan Zezeski * 27 Last Descriptor Bit (LAST) 16966f443ebcSRyan Zezeski * 28 Completion Request Bit (COMP_REQ) 16976f443ebcSRyan Zezeski * 31-29 Reserved Zero 16986f443ebcSRyan Zezeski */ 16996f443ebcSRyan Zezeski uint32_t etmd_len_ctrl; 17006f443ebcSRyan Zezeski 17016f443ebcSRyan Zezeski /* 17026f443ebcSRyan Zezeski * 5-0 Request ID High Bits [15-10] (REQ_ID_HI) 17036f443ebcSRyan Zezeski * 31-6 Reserved Zero 17046f443ebcSRyan Zezeski */ 17056f443ebcSRyan Zezeski uint32_t etmd_word1; 17066f443ebcSRyan Zezeski 17076f443ebcSRyan Zezeski /* 17086f443ebcSRyan Zezeski * 7-0 L3 Header Length (L3_HDR_LEN) 17096f443ebcSRyan Zezeski * 15:8 L3 Header Offset (L3_HDR_OFF) 17106f443ebcSRyan Zezeski * 21:16 L4 Header Length in Words (L4_HDR_LEN_IN_WORDS) 17116f443ebcSRyan Zezeski * 17126f443ebcSRyan Zezeski * Specifies the L4 header length in words. The device 17136f443ebcSRyan Zezeski * assumes the L4 header follows directly after the L3 17146f443ebcSRyan Zezeski * header and that the L4 offset is equal to L3_HDR_OFF + 17156f443ebcSRyan Zezeski * L3_HDR_LEN. 17166f443ebcSRyan Zezeski * 17176f443ebcSRyan Zezeski * 31-22 MSS Low Bits (MSS_LO) 17186f443ebcSRyan Zezeski */ 17196f443ebcSRyan Zezeski uint32_t etmd_word2; 17206f443ebcSRyan Zezeski uint32_t etmd_reserved; 17216f443ebcSRyan Zezeski } enahw_tx_meta_desc_t; 17226f443ebcSRyan Zezeski 17236f443ebcSRyan Zezeski /* common: N/A */ 17246f443ebcSRyan Zezeski typedef union enahw_tx_desc { 17256f443ebcSRyan Zezeski enahw_tx_data_desc_t etd_data; 17266f443ebcSRyan Zezeski enahw_tx_meta_desc_t etd_meta; 17276f443ebcSRyan Zezeski } enahw_tx_desc_t; 17286f443ebcSRyan Zezeski 17296f443ebcSRyan Zezeski /* common: ena_eth_io_tx_cdesc */ 17306f443ebcSRyan Zezeski typedef struct enahw_tx_cdesc { 17316f443ebcSRyan Zezeski /* 17326f443ebcSRyan Zezeski * 15-0 Request ID Bits 17336f443ebcSRyan Zezeski * 16 Reserved Zero 17346f443ebcSRyan Zezeski */ 17356f443ebcSRyan Zezeski uint16_t etc_req_id; 17366f443ebcSRyan Zezeski 17376f443ebcSRyan Zezeski /* 17386f443ebcSRyan Zezeski * Presumably the status of the Tx, though the Linux driver 17396f443ebcSRyan Zezeski * never checks this field. 17406f443ebcSRyan Zezeski */ 17416f443ebcSRyan Zezeski uint8_t etc_status; 17426f443ebcSRyan Zezeski 17436f443ebcSRyan Zezeski /* 17446f443ebcSRyan Zezeski * 0 Phase 17456f443ebcSRyan Zezeski * 7-1 Reserved Zero 17466f443ebcSRyan Zezeski */ 17476f443ebcSRyan Zezeski uint8_t etc_flags; 17486f443ebcSRyan Zezeski 17496f443ebcSRyan Zezeski /* 17506f443ebcSRyan Zezeski * This isn't documented or used in the Linux driver, but 17516f443ebcSRyan Zezeski * these probably store the submission queue ID and the 17526f443ebcSRyan Zezeski * submission queue head index. 17536f443ebcSRyan Zezeski */ 17546f443ebcSRyan Zezeski uint16_t etc_sub_qid; 17556f443ebcSRyan Zezeski uint16_t etc_sq_head_idx; 17566f443ebcSRyan Zezeski } enahw_tx_cdesc_t; 17576f443ebcSRyan Zezeski 17586f443ebcSRyan Zezeski #define ENAHW_TX_CDESC_PHASE_SHIFT 0 17596f443ebcSRyan Zezeski #define ENAHW_TX_CDESC_PHASE_MASK BIT(0) 17606f443ebcSRyan Zezeski 17616f443ebcSRyan Zezeski #define ENAHW_TX_CDESC_GET_PHASE(cdesc) \ 17626f443ebcSRyan Zezeski ((cdesc)->etc_flags & ENAHW_TX_CDESC_PHASE_MASK) 17636f443ebcSRyan Zezeski 17646f443ebcSRyan Zezeski /* common: ena_eth_io_rx_desc */ 17656f443ebcSRyan Zezeski typedef struct enahw_rx_desc { 17666f443ebcSRyan Zezeski /* 17676f443ebcSRyan Zezeski * The length of the buffer provided by the host, in bytes. 17686f443ebcSRyan Zezeski * Use the value of 0 to indicate 64K. 17696f443ebcSRyan Zezeski */ 17706f443ebcSRyan Zezeski uint16_t erd_length; 17716f443ebcSRyan Zezeski uint8_t erd_reserved1; 17726f443ebcSRyan Zezeski 17736f443ebcSRyan Zezeski /* 17746f443ebcSRyan Zezeski * 0 Phase (PHASE) 17756f443ebcSRyan Zezeski * 1 Reserved Zero 17766f443ebcSRyan Zezeski * 2 First (FIRST) 17776f443ebcSRyan Zezeski * 17786f443ebcSRyan Zezeski * Indicates this is the first descriptor for the frame. 17796f443ebcSRyan Zezeski * 17806f443ebcSRyan Zezeski * 3 Last (LAST) 17816f443ebcSRyan Zezeski * 17826f443ebcSRyan Zezeski * Indicates this is the last descriptor for the frame. 17836f443ebcSRyan Zezeski * 17846f443ebcSRyan Zezeski * 4 Completion Request (COMP_REQ) 17856f443ebcSRyan Zezeski * 17866f443ebcSRyan Zezeski * Indicates that a completion request should be generated 17876f443ebcSRyan Zezeski * for this descriptor. 17886f443ebcSRyan Zezeski * 17896f443ebcSRyan Zezeski * 7-5 Reserved Zero 17906f443ebcSRyan Zezeski */ 17916f443ebcSRyan Zezeski uint8_t erd_ctrl; 17926f443ebcSRyan Zezeski 17936f443ebcSRyan Zezeski /* 17946f443ebcSRyan Zezeski * 15-0 Request ID 17956f443ebcSRyan Zezeski * 16 Reserved 0 17966f443ebcSRyan Zezeski */ 17976f443ebcSRyan Zezeski uint16_t erd_req_id; 17986f443ebcSRyan Zezeski uint16_t erd_reserved2; 17996f443ebcSRyan Zezeski 18006f443ebcSRyan Zezeski /* The physical address of the buffer provided by the host. */ 18016f443ebcSRyan Zezeski uint32_t erd_buff_addr_lo; 18026f443ebcSRyan Zezeski uint16_t erd_buff_addr_hi; 18036f443ebcSRyan Zezeski uint16_t erd_reserved3; 18046f443ebcSRyan Zezeski } enahw_rx_desc_t; 18056f443ebcSRyan Zezeski 18066f443ebcSRyan Zezeski #define ENAHW_RX_DESC_PHASE_MASK BIT(0) 18076f443ebcSRyan Zezeski #define ENAHW_RX_DESC_FIRST_SHIFT 2 18086f443ebcSRyan Zezeski #define ENAHW_RX_DESC_FIRST_MASK BIT(2) 18096f443ebcSRyan Zezeski #define ENAHW_RX_DESC_LAST_SHIFT 3 18106f443ebcSRyan Zezeski #define ENAHW_RX_DESC_LAST_MASK BIT(3) 18116f443ebcSRyan Zezeski #define ENAHW_RX_DESC_COMP_REQ_SHIFT 4 18126f443ebcSRyan Zezeski #define ENAHW_RX_DESC_COMP_REQ_MASK BIT(4) 18136f443ebcSRyan Zezeski 1814eebd18daSAndy Fiddaman #define ENAHW_RX_DESC_CLEAR_CTRL(desc) ((desc)->erd_ctrl = 0) 18156f443ebcSRyan Zezeski #define ENAHW_RX_DESC_SET_PHASE(desc, val) \ 18166f443ebcSRyan Zezeski ((desc)->erd_ctrl |= ((val) & ENAHW_RX_DESC_PHASE_MASK)) 18176f443ebcSRyan Zezeski 18186f443ebcSRyan Zezeski #define ENAHW_RX_DESC_SET_FIRST(desc) \ 18196f443ebcSRyan Zezeski ((desc)->erd_ctrl |= ENAHW_RX_DESC_FIRST_MASK) 18206f443ebcSRyan Zezeski 18216f443ebcSRyan Zezeski #define ENAHW_RX_DESC_SET_LAST(desc) \ 18226f443ebcSRyan Zezeski ((desc)->erd_ctrl |= ENAHW_RX_DESC_LAST_MASK) 18236f443ebcSRyan Zezeski 18246f443ebcSRyan Zezeski #define ENAHW_RX_DESC_SET_COMP_REQ(desc) \ 18256f443ebcSRyan Zezeski ((desc)->erd_ctrl |= ENAHW_RX_DESC_COMP_REQ_MASK) 18266f443ebcSRyan Zezeski 18276f443ebcSRyan Zezeski /* 18286f443ebcSRyan Zezeski * Ethernet parsing information is only valid when last == 1. 18296f443ebcSRyan Zezeski * 18306f443ebcSRyan Zezeski * common: ena_eth_io_rx_cdesc_base 18316f443ebcSRyan Zezeski */ 18326f443ebcSRyan Zezeski typedef struct enahw_rx_cdesc { 18336f443ebcSRyan Zezeski /* 18346f443ebcSRyan Zezeski * 4-0 L3 Protocol Number (L3_PROTO) 18356f443ebcSRyan Zezeski * 18366f443ebcSRyan Zezeski * The L3 protocol type, one of enahw_io_l3_proto_t. 18376f443ebcSRyan Zezeski * 18386f443ebcSRyan Zezeski * 6-5 (SRC_VLAN_CNT) 18396f443ebcSRyan Zezeski * 7 Reserved Zero 18406f443ebcSRyan Zezeski * 12-8 L4 Protocol Number (L4_PROTO) 18416f443ebcSRyan Zezeski * 13 L3 Checksum Error (L3_CSUM_ERR) 18426f443ebcSRyan Zezeski * 18436f443ebcSRyan Zezeski * When set either the L3 checksum failed to match or the 18446f443ebcSRyan Zezeski * controller didn't attempt to validate the checksum. 18456f443ebcSRyan Zezeski * This bit is valid only when L3_PROTO indicates an IPv4 18466f443ebcSRyan Zezeski * packet. 18476f443ebcSRyan Zezeski * 18486f443ebcSRyan Zezeski * 14 L4 Checksum Error (L4_CSUM_ERR) 18496f443ebcSRyan Zezeski * 18506f443ebcSRyan Zezeski * When set either the L4 checksum failed to match or the 18516f443ebcSRyan Zezeski * controller didn't attempt to validate the checksum. 18526f443ebcSRyan Zezeski * This bit is valid only when L4_PROTO indicates a 18536f443ebcSRyan Zezeski * TCP/UDP packet, IPV4_FRAG is not set, and 18546f443ebcSRyan Zezeski * L4_CSUM_CHECKED is set. 18556f443ebcSRyan Zezeski * 18566f443ebcSRyan Zezeski * 15 IPv4 Fragmented (IPV4_FRAG) 18576f443ebcSRyan Zezeski * 16 L4 Checksum Validated (L4_CSUM_CHECKED) 18586f443ebcSRyan Zezeski * 18596f443ebcSRyan Zezeski * When set it indicates the device attempted to validate 18606f443ebcSRyan Zezeski * the L4 checksum. 18616f443ebcSRyan Zezeski * 18626f443ebcSRyan Zezeski * 23-17 Reserved Zero 18636f443ebcSRyan Zezeski * 24 Phase (PHASE) 18646f443ebcSRyan Zezeski * 25 (L3_CSUM2) 18656f443ebcSRyan Zezeski * 18666f443ebcSRyan Zezeski * According to the Linux source this is the "second 18676f443ebcSRyan Zezeski * checksum engine result". It's never checked. 18686f443ebcSRyan Zezeski * 18696f443ebcSRyan Zezeski * 26 First Descriptor Bit (FIRST) 18706f443ebcSRyan Zezeski * 18716f443ebcSRyan Zezeski * Indicates the first descriptor for the frame. 18726f443ebcSRyan Zezeski * 18736f443ebcSRyan Zezeski * 27 Last Descriptor Bit (LAST) 18746f443ebcSRyan Zezeski * 18756f443ebcSRyan Zezeski * Indicates the last descriptor for the frame. 18766f443ebcSRyan Zezeski * 18776f443ebcSRyan Zezeski * 29-28 Reserved Zero 18786f443ebcSRyan Zezeski * 30 Buffer Type (BUFFER) 18796f443ebcSRyan Zezeski * 18806f443ebcSRyan Zezeski * When enabled indicates this is a data descriptor. 18816f443ebcSRyan Zezeski * Otherwse, it is a metadata descriptor. 18826f443ebcSRyan Zezeski * 18836f443ebcSRyan Zezeski * 31 : reserved31 18846f443ebcSRyan Zezeski */ 18856f443ebcSRyan Zezeski uint32_t erc_status; 18866f443ebcSRyan Zezeski uint16_t erc_length; 18876f443ebcSRyan Zezeski uint16_t erc_req_id; 18886f443ebcSRyan Zezeski 18896f443ebcSRyan Zezeski /* 32-bit hash result */ 18906f443ebcSRyan Zezeski uint32_t erc_hash; 18916f443ebcSRyan Zezeski uint16_t erc_sub_qid; 18926f443ebcSRyan Zezeski 18936f443ebcSRyan Zezeski /* 18946f443ebcSRyan Zezeski * The device may choose to offset the start of the header 18956f443ebcSRyan Zezeski * data (which implies this value only applies to the first 18966f443ebcSRyan Zezeski * descriptor). When and why the device does this is not 18976f443ebcSRyan Zezeski * documented in the common code. The most likely case would 18986f443ebcSRyan Zezeski * be for IP header alignment. 18996f443ebcSRyan Zezeski */ 19006f443ebcSRyan Zezeski uint8_t erc_offset; 19016f443ebcSRyan Zezeski uint8_t erc_reserved; 19026f443ebcSRyan Zezeski } enahw_rx_cdesc_t; 19036f443ebcSRyan Zezeski 19046f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_PROTO_MASK GENMASK(4, 0) 19056f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_SRC_VLAN_CNT_SHIFT 5 19066f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_SRC_VLAN_CNT_MASK GENMASK(6, 5) 19076f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_PROTO_SHIFT 8 19086f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_PROTO_MASK GENMASK(12, 8) 19096f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_CSUM_ERR_SHIFT 13 19106f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_CSUM_ERR_MASK BIT(13) 19116f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_ERR_SHIFT 14 19126f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_ERR_MASK BIT(14) 19136f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_IPV4_FRAG_SHIFT 15 19146f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_IPV4_FRAG_MASK BIT(15) 19156f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_CHECKED_SHIFT 16 19166f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK BIT(16) 19176f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_PHASE_SHIFT 24 19186f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_PHASE_MASK BIT(24) 19196f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_CSUM2_SHIFT 25 19206f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_CSUM2_MASK BIT(25) 19216f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_FIRST_SHIFT 26 19226f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_FIRST_MASK BIT(26) 19236f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_LAST_SHIFT 27 19246f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_LAST_MASK BIT(27) 19256f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_BUFFER_SHIFT 30 19266f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_BUFFER_MASK BIT(30) 19276f443ebcSRyan Zezeski 19286f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_PROTO(desc) \ 19296f443ebcSRyan Zezeski ((desc)->erc_status & ENAHW_RX_CDESC_L3_PROTO_MASK) 19306f443ebcSRyan Zezeski 19316f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L3_CSUM_ERR(desc) \ 19326f443ebcSRyan Zezeski ((((desc)->erc_status & ENAHW_RX_CDESC_L3_CSUM_ERR_MASK) >> \ 19336f443ebcSRyan Zezeski ENAHW_RX_CDESC_L3_CSUM_ERR_SHIFT) != 0) 19346f443ebcSRyan Zezeski 19356f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_PROTO(desc) \ 19366f443ebcSRyan Zezeski (((desc)->erc_status & ENAHW_RX_CDESC_L4_PROTO_MASK) >> \ 19376f443ebcSRyan Zezeski ENAHW_RX_CDESC_L4_PROTO_SHIFT) 19386f443ebcSRyan Zezeski 19396f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_CHECKED(desc) \ 19406f443ebcSRyan Zezeski ((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_CHECKED_MASK) >> \ 19416f443ebcSRyan Zezeski ENAHW_RX_CDESC_L4_CSUM_CHECKED_SHIFT) != 0) 19426f443ebcSRyan Zezeski 19436f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_L4_CSUM_ERR(desc) \ 19446f443ebcSRyan Zezeski ((((desc)->erc_status & ENAHW_RX_CDESC_L4_CSUM_ERR_MASK) >> \ 19456f443ebcSRyan Zezeski ENAHW_RX_CDESC_L4_CSUM_ERR_SHIFT) != 0) 19466f443ebcSRyan Zezeski 19476f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_PHASE(desc) \ 19486f443ebcSRyan Zezeski (((desc)->erc_status & ENAHW_RX_CDESC_PHASE_MASK) >> \ 19496f443ebcSRyan Zezeski ENAHW_RX_CDESC_PHASE_SHIFT) 19506f443ebcSRyan Zezeski 19516f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_FIRST(desc) \ 19526f443ebcSRyan Zezeski ((((desc)->erc_status & ENAHW_RX_CDESC_FIRST_MASK) >> \ 19536f443ebcSRyan Zezeski ENAHW_RX_CDESC_FIRST_SHIFT) == 1) 19546f443ebcSRyan Zezeski 19556f443ebcSRyan Zezeski #define ENAHW_RX_CDESC_LAST(desc) \ 19566f443ebcSRyan Zezeski ((((desc)->erc_status & ENAHW_RX_CDESC_LAST_MASK) >> \ 19576f443ebcSRyan Zezeski ENAHW_RX_CDESC_LAST_SHIFT) == 1) 19586f443ebcSRyan Zezeski 19596f443ebcSRyan Zezeski /* 19606f443ebcSRyan Zezeski * Controls for the interrupt register mapped to each Rx/Tx CQ. 19616f443ebcSRyan Zezeski */ 19626f443ebcSRyan Zezeski #define ENAHW_REG_INTR_RX_DELAY_MASK GENMASK(14, 0) 19636f443ebcSRyan Zezeski #define ENAHW_REG_INTR_TX_DELAY_SHIFT 15 19646f443ebcSRyan Zezeski #define ENAHW_REG_INTR_TX_DELAY_MASK GENMASK(29, 15) 19656f443ebcSRyan Zezeski #define ENAHW_REG_INTR_UNMASK_SHIFT 30 19666f443ebcSRyan Zezeski #define ENAHW_REG_INTR_UNMASK_MASK BIT(30) 19676f443ebcSRyan Zezeski 19686f443ebcSRyan Zezeski #define ENAHW_REG_INTR_UNMASK(val) \ 19696f443ebcSRyan Zezeski ((val) |= ENAHW_REG_INTR_UNMASK_MASK) 19706f443ebcSRyan Zezeski 19716f443ebcSRyan Zezeski #define ENAHW_REG_INTR_MASK(val) \ 19726f443ebcSRyan Zezeski ((val) &= ~ENAHW_REG_INTR_UNMASK_MASK) 19736f443ebcSRyan Zezeski 19746f443ebcSRyan Zezeski #endif /* _ENA_HW_H */ 1975