108057504Sxy /* 208057504Sxy * This file is provided under a CDDLv1 license. When using or 308057504Sxy * redistributing this file, you may do so under this license. 408057504Sxy * In redistributing this file this license must be included 508057504Sxy * and no other modification of this header file is permitted. 608057504Sxy * 708057504Sxy * CDDL LICENSE SUMMARY 808057504Sxy * 908057504Sxy * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 1008057504Sxy * 1108057504Sxy * The contents of this file are subject to the terms of Version 1208057504Sxy * 1.0 of the Common Development and Distribution License (the "License"). 1308057504Sxy * 1408057504Sxy * You should have received a copy of the License with this software. 1508057504Sxy * You can obtain a copy of the License at 1608057504Sxy * http://www.opensolaris.org/os/licensing. 1708057504Sxy * See the License for the specific language governing permissions 1808057504Sxy * and limitations under the License. 1908057504Sxy */ 2008057504Sxy 2108057504Sxy /* 2208057504Sxy * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 2308057504Sxy * Use is subject to license terms of the CDDLv1. 2408057504Sxy */ 2508057504Sxy 2608057504Sxy #ifndef _E1000_OSDEP_H 2708057504Sxy #define _E1000_OSDEP_H 2808057504Sxy 2908057504Sxy #pragma ident "%Z%%M% %I% %E% SMI" 3008057504Sxy 3108057504Sxy #ifdef __cplusplus 3208057504Sxy extern "C" { 3308057504Sxy #endif 3408057504Sxy 3508057504Sxy #include <sys/types.h> 3608057504Sxy #include <sys/conf.h> 3708057504Sxy #include <sys/debug.h> 3808057504Sxy #include <sys/stropts.h> 3908057504Sxy #include <sys/stream.h> 4008057504Sxy #include <sys/strlog.h> 4108057504Sxy #include <sys/kmem.h> 4208057504Sxy #include <sys/stat.h> 4308057504Sxy #include <sys/kstat.h> 4408057504Sxy #include <sys/modctl.h> 4508057504Sxy #include <sys/errno.h> 4608057504Sxy #include <sys/ddi.h> 4708057504Sxy #include <sys/sunddi.h> 4808057504Sxy #include <sys/pci.h> 49*25f2d433Sxy #include <sys/atomic.h> 50*25f2d433Sxy #include "e1000g_debug.h" 5108057504Sxy 5208057504Sxy /* 5308057504Sxy * === BEGIN CONTENT FORMERLY IN FXHW.H === 5408057504Sxy */ 5508057504Sxy #define usec_delay(x) drv_usecwait(x) 5608057504Sxy #define msec_delay(x) drv_usecwait(x * 1000) 5708057504Sxy 58*25f2d433Sxy #ifdef E1000G_DEBUG 59*25f2d433Sxy #define DEBUGOUT(S) \ 60*25f2d433Sxy E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 61*25f2d433Sxy #define DEBUGOUT1(S, A) \ 62*25f2d433Sxy E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 63*25f2d433Sxy #define DEBUGOUT2(S, A, B) \ 64*25f2d433Sxy E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 65*25f2d433Sxy #define DEBUGOUT3(S, A, B, C) \ 66*25f2d433Sxy E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 67*25f2d433Sxy #define DEBUGFUNC(F) \ 68*25f2d433Sxy E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 6908057504Sxy #else 7008057504Sxy #define DEBUGOUT(S) 7108057504Sxy #define DEBUGOUT1(S, A) 7208057504Sxy #define DEBUGOUT2(S, A, B) 7308057504Sxy #define DEBUGOUT3(S, A, B, C) 74*25f2d433Sxy #define DEBUGFUNC(F) 7508057504Sxy #endif 7608057504Sxy 77*25f2d433Sxy #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 7808057504Sxy 7908057504Sxy #define FALSE 0 8008057504Sxy #define TRUE 1 8108057504Sxy #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 8208057504Sxy #define PCI_COMMAND_REGISTER 0x04 83*25f2d433Sxy #define PCI_EX_CONF_CAP 0xE0 84*25f2d433Sxy #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 85*25f2d433Sxy 86*25f2d433Sxy #define RECEIVE_BUFFER_ALIGN_SIZE 256 87*25f2d433Sxy #define E1000_MDALIGN 4096 88*25f2d433Sxy #define E1000_ERT_2048 0x100 89*25f2d433Sxy 90*25f2d433Sxy /* PHY Extended Status Register */ 91*25f2d433Sxy #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 92*25f2d433Sxy #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 93*25f2d433Sxy #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 94*25f2d433Sxy #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 95*25f2d433Sxy 96*25f2d433Sxy #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) 97*25f2d433Sxy 98*25f2d433Sxy #ifdef NO_82542_SUPPORT 99*25f2d433Sxy #define E1000_WRITE_REG(hw, reg, value) \ 100*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 101*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg), (value)) 10208057504Sxy 103*25f2d433Sxy #define E1000_READ_REG(hw, reg) \ 104*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 105*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg)) 10608057504Sxy 107*25f2d433Sxy #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 108*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 109*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2)), \ 110*25f2d433Sxy (value)) 111*25f2d433Sxy 112*25f2d433Sxy #define E1000_READ_REG_ARRAY(hw, reg, offset) \ 113*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 114*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2))) 115*25f2d433Sxy 116*25f2d433Sxy #else /* NO_82542_SUPPORT */ 117*25f2d433Sxy 118*25f2d433Sxy #define E1000_WRITE_REG(hw, reg, value) \ 11908057504Sxy {\ 120*25f2d433Sxy if ((hw)->mac.type != e1000_82542) \ 121*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 122*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg), \ 12308057504Sxy value); \ 12408057504Sxy else \ 125*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 126*25f2d433Sxy (uint32_t *)((hw)->hw_addr + \ 127*25f2d433Sxy e1000_translate_register_82542(reg)), \ 12808057504Sxy value); \ 12908057504Sxy } 13008057504Sxy 131*25f2d433Sxy #define E1000_READ_REG(hw, reg) (\ 132*25f2d433Sxy ((hw)->mac.type != e1000_82542) ? \ 133*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 134*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg)) : \ 135*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 136*25f2d433Sxy (uint32_t *)((hw)->hw_addr + \ 137*25f2d433Sxy e1000_translate_register_82542(reg)))) 13808057504Sxy 139*25f2d433Sxy #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 14008057504Sxy {\ 141*25f2d433Sxy if ((hw)->mac.type != e1000_82542) \ 142*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 143*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2)),\ 14408057504Sxy value); \ 14508057504Sxy else \ 146*25f2d433Sxy ddi_put32((OS_DEP(hw))->reg_handle, \ 147*25f2d433Sxy (uint32_t *)((hw)->hw_addr + \ 148*25f2d433Sxy e1000_translate_register_82542(reg) + \ 14908057504Sxy ((offset) << 2)), value); \ 15008057504Sxy } 15108057504Sxy 152*25f2d433Sxy #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 153*25f2d433Sxy ((hw)->mac.type != e1000_82542) ? \ 154*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 155*25f2d433Sxy (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2))) : \ 156*25f2d433Sxy ddi_get32((OS_DEP(hw))->reg_handle, \ 157*25f2d433Sxy (uint32_t *)((hw)->hw_addr + \ 158*25f2d433Sxy e1000_translate_register_82542(reg) + \ 15908057504Sxy ((offset) << 2)))) 160*25f2d433Sxy #endif /* NO_82542_SUPPORT */ 16108057504Sxy 16208057504Sxy 16308057504Sxy #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) NULL 16408057504Sxy #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) NULL 16508057504Sxy #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) NULL 16608057504Sxy #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) NULL 16708057504Sxy #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) NULL 16808057504Sxy #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) NULL 16908057504Sxy 17008057504Sxy 171*25f2d433Sxy #define E1000_READ_FLASH_REG(hw, reg) \ 17208057504Sxy ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 173*25f2d433Sxy (uint32_t *)((hw)->flash_address + (reg))) 17408057504Sxy 175*25f2d433Sxy #define E1000_READ_FLASH_REG16(hw, reg) \ 17608057504Sxy ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 177*25f2d433Sxy (uint16_t *)((hw)->flash_address + (reg))) 17808057504Sxy 179*25f2d433Sxy #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 18008057504Sxy ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 181*25f2d433Sxy (uint32_t *)((hw)->flash_address + (reg)), (value)) 18208057504Sxy 183*25f2d433Sxy #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 18408057504Sxy ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 185*25f2d433Sxy (uint16_t *)((hw)->flash_address + (reg)), (value)) 18608057504Sxy 18708057504Sxy /* 18808057504Sxy * === END CONTENT FORMERLY IN FXHW.H === 18908057504Sxy */ 19008057504Sxy 19108057504Sxy #define msec_delay_irq msec_delay 19208057504Sxy 193*25f2d433Sxy typedef int8_t s8; 194*25f2d433Sxy typedef int16_t s16; 195*25f2d433Sxy typedef int32_t s32; 196*25f2d433Sxy typedef int64_t s64; 197*25f2d433Sxy typedef uint8_t u8; 198*25f2d433Sxy typedef uint16_t u16; 199*25f2d433Sxy typedef uint32_t u32; 200*25f2d433Sxy typedef uint64_t u64; 201*25f2d433Sxy 20208057504Sxy typedef uint8_t UCHAR; /* 8-bit unsigned */ 20308057504Sxy typedef UCHAR UINT8; /* 8-bit unsigned */ 20408057504Sxy typedef uint16_t USHORT; /* 16-bit unsigned */ 20508057504Sxy typedef uint16_t UINT16; /* 16-bit unsigned */ 20608057504Sxy typedef uint32_t ULONG; /* 32-bit unsigned */ 20708057504Sxy typedef uint32_t UINT32; 20808057504Sxy typedef uint32_t UINT; /* 32-bit unsigned */ 20908057504Sxy typedef UCHAR BOOLEAN; 21008057504Sxy typedef UCHAR *PUCHAR; 21108057504Sxy typedef UINT *PUINT; 21208057504Sxy typedef ULONG *PLONG; 21308057504Sxy typedef ULONG NDIS_STATUS; 21408057504Sxy typedef USHORT *PUSHORT; 21508057504Sxy typedef PUSHORT PUINT16; /* 16-bit unsigned pointer */ 21608057504Sxy typedef ULONG E1000_32_BIT_PHYSICAL_ADDRESS, 21708057504Sxy *PFX_32_BIT_PHYSICAL_ADDRESS; 21808057504Sxy typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS, 21908057504Sxy *PFX_64_BIT_PHYSICAL_ADDRESS; 22008057504Sxy 22108057504Sxy struct e1000g_osdep { 222*25f2d433Sxy ddi_acc_handle_t reg_handle; 223*25f2d433Sxy ddi_acc_handle_t cfg_handle; 22408057504Sxy ddi_acc_handle_t ich_flash_handle; 225*25f2d433Sxy struct e1000g *adapter; 22608057504Sxy }; 22708057504Sxy 22808057504Sxy #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 22908057504Sxy #define E1000_WRITE_REG_IO E1000_WRITE_REG 23008057504Sxy #else /* on x86, use port io routines */ 231*25f2d433Sxy #define E1000_WRITE_REG_IO(a, reg, val) { \ 232*25f2d433Sxy outl(((a)->io_base), reg); \ 233*25f2d433Sxy outl(((a)->io_base + 4), val); } 23408057504Sxy #endif /* __sparc */ 23508057504Sxy 23608057504Sxy #ifdef __cplusplus 23708057504Sxy } 23808057504Sxy #endif 23908057504Sxy 24008057504Sxy #endif /* _E1000_OSDEP_H */ 241