1*08057504Sxy /* 2*08057504Sxy * This file is provided under a CDDLv1 license. When using or 3*08057504Sxy * redistributing this file, you may do so under this license. 4*08057504Sxy * In redistributing this file this license must be included 5*08057504Sxy * and no other modification of this header file is permitted. 6*08057504Sxy * 7*08057504Sxy * CDDL LICENSE SUMMARY 8*08057504Sxy * 9*08057504Sxy * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10*08057504Sxy * 11*08057504Sxy * The contents of this file are subject to the terms of Version 12*08057504Sxy * 1.0 of the Common Development and Distribution License (the "License"). 13*08057504Sxy * 14*08057504Sxy * You should have received a copy of the License with this software. 15*08057504Sxy * You can obtain a copy of the License at 16*08057504Sxy * http://www.opensolaris.org/os/licensing. 17*08057504Sxy * See the License for the specific language governing permissions 18*08057504Sxy * and limitations under the License. 19*08057504Sxy */ 20*08057504Sxy 21*08057504Sxy /* 22*08057504Sxy * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23*08057504Sxy * Use is subject to license terms of the CDDLv1. 24*08057504Sxy */ 25*08057504Sxy 26*08057504Sxy #ifndef _E1000_OSDEP_H 27*08057504Sxy #define _E1000_OSDEP_H 28*08057504Sxy 29*08057504Sxy #pragma ident "%Z%%M% %I% %E% SMI" 30*08057504Sxy 31*08057504Sxy #ifdef __cplusplus 32*08057504Sxy extern "C" { 33*08057504Sxy #endif 34*08057504Sxy 35*08057504Sxy #include <sys/types.h> 36*08057504Sxy #include <sys/conf.h> 37*08057504Sxy #include <sys/debug.h> 38*08057504Sxy #include <sys/stropts.h> 39*08057504Sxy #include <sys/stream.h> 40*08057504Sxy #include <sys/strlog.h> 41*08057504Sxy #include <sys/kmem.h> 42*08057504Sxy #include <sys/stat.h> 43*08057504Sxy #include <sys/kstat.h> 44*08057504Sxy #include <sys/modctl.h> 45*08057504Sxy #include <sys/errno.h> 46*08057504Sxy #include <sys/ddi.h> 47*08057504Sxy #include <sys/sunddi.h> 48*08057504Sxy #include <sys/pci.h> 49*08057504Sxy 50*08057504Sxy /* 51*08057504Sxy * === BEGIN CONTENT FORMERLY IN FXHW.H === 52*08057504Sxy */ 53*08057504Sxy #define DelayInMicroseconds(x) drv_usecwait(x) 54*08057504Sxy #define DelayInMilliseconds(x) drv_usecwait(x * 1000) 55*08057504Sxy #define usec_delay(x) drv_usecwait(x) 56*08057504Sxy #define msec_delay(x) drv_usecwait(x * 1000) 57*08057504Sxy 58*08057504Sxy #ifdef e1000g_DEBUG 59*08057504Sxy #define DEBUGOUT(S) cmn_err(CE_CONT, S) 60*08057504Sxy #define DEBUGOUT1(S, A) cmn_err(CE_CONT, S, A) 61*08057504Sxy #define DEBUGOUT2(S, A, B) cmn_err(CE_CONT, S, A, B) 62*08057504Sxy #define DEBUGOUT3(S, A, B, C) cmn_err(CE_CONT, S, A, B, C) 63*08057504Sxy #define DEBUGOUT7(S, A, B, C, D, E, F, G) \ 64*08057504Sxy cmn_err(CE_CONT, S, A, B, C, D, E, F, G) 65*08057504Sxy #else 66*08057504Sxy #define DEBUGOUT(S) 67*08057504Sxy #define DEBUGOUT1(S, A) 68*08057504Sxy #define DEBUGOUT2(S, A, B) 69*08057504Sxy #define DEBUGOUT3(S, A, B, C) 70*08057504Sxy #define DEBUGOUT7(S, A, B, C, D, E, F, G) 71*08057504Sxy #endif 72*08057504Sxy 73*08057504Sxy #define DEBUGFUNC(F) DEBUGOUT(F) 74*08057504Sxy 75*08057504Sxy #define IN 76*08057504Sxy #define OUT 77*08057504Sxy #define FALSE 0 78*08057504Sxy #define TRUE 1 79*08057504Sxy #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 80*08057504Sxy #define PCI_COMMAND_REGISTER 0x04 81*08057504Sxy 82*08057504Sxy #define E1000_WRITE_FLUSH(a) /* NOOP */ 83*08057504Sxy 84*08057504Sxy #define E1000_WRITE_REG(a, reg, value) \ 85*08057504Sxy {\ 86*08057504Sxy if ((a)->mac_type >= e1000_82543) \ 87*08057504Sxy ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 88*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_##reg), \ 89*08057504Sxy value); \ 90*08057504Sxy else \ 91*08057504Sxy ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 92*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_82542_##reg), \ 93*08057504Sxy value); \ 94*08057504Sxy } 95*08057504Sxy 96*08057504Sxy #define E1000_READ_REG(a, reg) (\ 97*08057504Sxy ((a)->mac_type >= e1000_82543) ? \ 98*08057504Sxy ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 99*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_##reg)) : \ 100*08057504Sxy ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 101*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_82542_##reg))) 102*08057504Sxy 103*08057504Sxy #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 104*08057504Sxy {\ 105*08057504Sxy if ((a)->mac_type >= e1000_82543) \ 106*08057504Sxy ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 107*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2)),\ 108*08057504Sxy value); \ 109*08057504Sxy else \ 110*08057504Sxy ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 111*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ 112*08057504Sxy ((offset) << 2)), value); \ 113*08057504Sxy } 114*08057504Sxy 115*08057504Sxy #define E1000_READ_REG_ARRAY(a, reg, offset) (\ 116*08057504Sxy ((a)->mac_type >= e1000_82543) ? \ 117*08057504Sxy ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 118*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \ 119*08057504Sxy ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 120*08057504Sxy (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ 121*08057504Sxy ((offset) << 2)))) 122*08057504Sxy 123*08057504Sxy 124*08057504Sxy #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) NULL 125*08057504Sxy #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) NULL 126*08057504Sxy #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) NULL 127*08057504Sxy #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) NULL 128*08057504Sxy #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) NULL 129*08057504Sxy #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) NULL 130*08057504Sxy 131*08057504Sxy 132*08057504Sxy #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 133*08057504Sxy #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 134*08057504Sxy 135*08057504Sxy #define E1000_READ_ICH_FLASH_REG(hw, reg) \ 136*08057504Sxy ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 137*08057504Sxy (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg))) 138*08057504Sxy 139*08057504Sxy #define E1000_READ_ICH_FLASH_REG16(hw, reg) \ 140*08057504Sxy ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 141*08057504Sxy (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg))) 142*08057504Sxy 143*08057504Sxy #define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \ 144*08057504Sxy ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 145*08057504Sxy (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) 146*08057504Sxy 147*08057504Sxy #define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \ 148*08057504Sxy ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 149*08057504Sxy (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) 150*08057504Sxy 151*08057504Sxy /* 152*08057504Sxy * The size of the receive buffers we allocate, 153*08057504Sxy */ 154*08057504Sxy #define E1000_SIZE_OF_RECEIVE_BUFFERS (2048) 155*08057504Sxy 156*08057504Sxy /* 157*08057504Sxy * Use this define refer to the size of a recieve buffer plus its 158*08057504Sxy * align size 159*08057504Sxy */ 160*08057504Sxy #define E1000_SIZE_OF_UNALIGNED_RECEIVE_BUFFERS \ 161*08057504Sxy E1000_SIZE_OF_RECEIVE_BUFFERS + RECEIVE_BUFFER_ALIGN_SIZE 162*08057504Sxy 163*08057504Sxy /* 164*08057504Sxy * === END CONTENT FORMERLY IN FXHW.H === 165*08057504Sxy */ 166*08057504Sxy 167*08057504Sxy #define msec_delay_irq msec_delay 168*08057504Sxy 169*08057504Sxy typedef uint8_t UCHAR; /* 8-bit unsigned */ 170*08057504Sxy typedef UCHAR UINT8; /* 8-bit unsigned */ 171*08057504Sxy typedef uint16_t USHORT; /* 16-bit unsigned */ 172*08057504Sxy typedef uint16_t UINT16; /* 16-bit unsigned */ 173*08057504Sxy typedef uint32_t ULONG; /* 32-bit unsigned */ 174*08057504Sxy typedef uint32_t UINT32; 175*08057504Sxy typedef uint32_t UINT; /* 32-bit unsigned */ 176*08057504Sxy typedef UCHAR BOOLEAN; 177*08057504Sxy typedef UCHAR *PUCHAR; 178*08057504Sxy typedef UINT *PUINT; 179*08057504Sxy typedef ULONG *PLONG; 180*08057504Sxy typedef ULONG NDIS_STATUS; 181*08057504Sxy typedef USHORT *PUSHORT; 182*08057504Sxy typedef PUSHORT PUINT16; /* 16-bit unsigned pointer */ 183*08057504Sxy typedef ULONG E1000_32_BIT_PHYSICAL_ADDRESS, 184*08057504Sxy *PFX_32_BIT_PHYSICAL_ADDRESS; 185*08057504Sxy typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS, 186*08057504Sxy *PFX_64_BIT_PHYSICAL_ADDRESS; 187*08057504Sxy 188*08057504Sxy struct e1000g_osdep { 189*08057504Sxy ddi_acc_handle_t E1000_handle; 190*08057504Sxy ddi_acc_handle_t handle; 191*08057504Sxy /* flash access */ 192*08057504Sxy ddi_acc_handle_t ich_flash_handle; 193*08057504Sxy caddr_t ich_flash_base; 194*08057504Sxy off_t ich_flash_size; 195*08057504Sxy }; 196*08057504Sxy 197*08057504Sxy #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 198*08057504Sxy 199*08057504Sxy #define E1000_READ_REG_IO E1000_READ_REG 200*08057504Sxy #define E1000_WRITE_REG_IO E1000_WRITE_REG 201*08057504Sxy 202*08057504Sxy #else /* on x86, use port io routines */ 203*08057504Sxy 204*08057504Sxy #define E1000_READ_REG_IO(a, reg) \ 205*08057504Sxy e1000_read_reg_io((a), E1000_##reg) 206*08057504Sxy #define E1000_WRITE_REG_IO(a, reg, val) \ 207*08057504Sxy e1000_write_reg_io((a), E1000_##reg, val) 208*08057504Sxy 209*08057504Sxy #endif /* __sparc */ 210*08057504Sxy 211*08057504Sxy #ifdef __cplusplus 212*08057504Sxy } 213*08057504Sxy #endif 214*08057504Sxy 215*08057504Sxy #endif /* _E1000_OSDEP_H */ 216