1*75eba5b6SRobert Mustacchi /****************************************************************************** 2*75eba5b6SRobert Mustacchi 3*75eba5b6SRobert Mustacchi Copyright (c) 2001-2013, Intel Corporation 4*75eba5b6SRobert Mustacchi All rights reserved. 5*75eba5b6SRobert Mustacchi 6*75eba5b6SRobert Mustacchi Redistribution and use in source and binary forms, with or without 7*75eba5b6SRobert Mustacchi modification, are permitted provided that the following conditions are met: 8*75eba5b6SRobert Mustacchi 9*75eba5b6SRobert Mustacchi 1. Redistributions of source code must retain the above copyright notice, 10*75eba5b6SRobert Mustacchi this list of conditions and the following disclaimer. 11*75eba5b6SRobert Mustacchi 12*75eba5b6SRobert Mustacchi 2. Redistributions in binary form must reproduce the above copyright 13*75eba5b6SRobert Mustacchi notice, this list of conditions and the following disclaimer in the 14*75eba5b6SRobert Mustacchi documentation and/or other materials provided with the distribution. 15*75eba5b6SRobert Mustacchi 16*75eba5b6SRobert Mustacchi 3. Neither the name of the Intel Corporation nor the names of its 17*75eba5b6SRobert Mustacchi contributors may be used to endorse or promote products derived from 18*75eba5b6SRobert Mustacchi this software without specific prior written permission. 19*75eba5b6SRobert Mustacchi 20*75eba5b6SRobert Mustacchi THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21*75eba5b6SRobert Mustacchi AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22*75eba5b6SRobert Mustacchi IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23*75eba5b6SRobert Mustacchi ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24*75eba5b6SRobert Mustacchi LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25*75eba5b6SRobert Mustacchi CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26*75eba5b6SRobert Mustacchi SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27*75eba5b6SRobert Mustacchi INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28*75eba5b6SRobert Mustacchi CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29*75eba5b6SRobert Mustacchi ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30*75eba5b6SRobert Mustacchi POSSIBILITY OF SUCH DAMAGE. 31*75eba5b6SRobert Mustacchi 32*75eba5b6SRobert Mustacchi ******************************************************************************/ 33*75eba5b6SRobert Mustacchi /*$FreeBSD$*/ 34*75eba5b6SRobert Mustacchi 35*75eba5b6SRobert Mustacchi #ifndef _E1000_DEFINES_H_ 36*75eba5b6SRobert Mustacchi #define _E1000_DEFINES_H_ 37*75eba5b6SRobert Mustacchi 38*75eba5b6SRobert Mustacchi /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 39*75eba5b6SRobert Mustacchi #define REQ_TX_DESCRIPTOR_MULTIPLE 8 40*75eba5b6SRobert Mustacchi #define REQ_RX_DESCRIPTOR_MULTIPLE 8 41*75eba5b6SRobert Mustacchi 42*75eba5b6SRobert Mustacchi /* Definitions for power management and wakeup registers */ 43*75eba5b6SRobert Mustacchi /* Wake Up Control */ 44*75eba5b6SRobert Mustacchi #define E1000_WUC_APME 0x00000001 /* APM Enable */ 45*75eba5b6SRobert Mustacchi #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 46*75eba5b6SRobert Mustacchi #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 47*75eba5b6SRobert Mustacchi 48*75eba5b6SRobert Mustacchi /* Wake Up Filter Control */ 49*75eba5b6SRobert Mustacchi #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 50*75eba5b6SRobert Mustacchi #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 51*75eba5b6SRobert Mustacchi #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 52*75eba5b6SRobert Mustacchi #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 53*75eba5b6SRobert Mustacchi #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 54*75eba5b6SRobert Mustacchi #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 55*75eba5b6SRobert Mustacchi #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 56*75eba5b6SRobert Mustacchi #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 57*75eba5b6SRobert Mustacchi 58*75eba5b6SRobert Mustacchi /* Wake Up Status */ 59*75eba5b6SRobert Mustacchi #define E1000_WUS_LNKC E1000_WUFC_LNKC 60*75eba5b6SRobert Mustacchi #define E1000_WUS_MAG E1000_WUFC_MAG 61*75eba5b6SRobert Mustacchi #define E1000_WUS_EX E1000_WUFC_EX 62*75eba5b6SRobert Mustacchi #define E1000_WUS_MC E1000_WUFC_MC 63*75eba5b6SRobert Mustacchi #define E1000_WUS_BC E1000_WUFC_BC 64*75eba5b6SRobert Mustacchi 65*75eba5b6SRobert Mustacchi /* Extended Device Control */ 66*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 67*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */ 68*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */ 69*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */ 70*75eba5b6SRobert Mustacchi /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */ 71*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 72*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 73*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* Direction of SDP3 0=in 1=out */ 74*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 75*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 76*75eba5b6SRobert Mustacchi /* Physical Func Reset Done Indication */ 77*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PFRSTD 0x00004000 78*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 79*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 80*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ 81*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 82*75eba5b6SRobert Mustacchi /* Offset of the link mode field in Ctrl Ext register */ 83*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_OFFSET 22 84*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 85*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 86*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 87*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 88*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_EIAME 0x01000000 89*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_IRCA 0x00000001 90*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */ 91*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 92*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 93*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_LSECCK 0x00001000 94*75eba5b6SRobert Mustacchi #define E1000_CTRL_EXT_PHYPDEN 0x00100000 95*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_REG_ADDR_SHIFT 16 96*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 97*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_OPCODE_READ 0x08000000 98*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 99*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_READY 0x20000000 100*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_ERROR 0x80000000 101*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 102*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 103*75eba5b6SRobert Mustacchi #define E1000_MAX_SGMII_PHY_REG_ADDR 255 104*75eba5b6SRobert Mustacchi #define E1000_I2CCMD_PHY_TIMEOUT 200 105*75eba5b6SRobert Mustacchi #define E1000_IVAR_VALID 0x80 106*75eba5b6SRobert Mustacchi #define E1000_GPIE_NSICR 0x00000001 107*75eba5b6SRobert Mustacchi #define E1000_GPIE_MSIX_MODE 0x00000010 108*75eba5b6SRobert Mustacchi #define E1000_GPIE_EIAME 0x40000000 109*75eba5b6SRobert Mustacchi #define E1000_GPIE_PBA 0x80000000 110*75eba5b6SRobert Mustacchi 111*75eba5b6SRobert Mustacchi /* Receive Descriptor bit definitions */ 112*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 113*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 114*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 115*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 116*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 117*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 118*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 119*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 120*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 121*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 122*75eba5b6SRobert Mustacchi #define E1000_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 123*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 124*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 125*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 126*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 127*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 128*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 129*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 130*75eba5b6SRobert Mustacchi #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 131*75eba5b6SRobert Mustacchi 132*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 133*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_LB 0x00040000 134*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_CE 0x01000000 135*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_SE 0x02000000 136*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_SEQ 0x04000000 137*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_CXE 0x10000000 138*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_TCPE 0x20000000 139*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_IPE 0x40000000 140*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_STATERR_RXE 0x80000000 141*75eba5b6SRobert Mustacchi 142*75eba5b6SRobert Mustacchi /* mask to determine if packets should be dropped due to frame errors */ 143*75eba5b6SRobert Mustacchi #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 144*75eba5b6SRobert Mustacchi E1000_RXD_ERR_CE | \ 145*75eba5b6SRobert Mustacchi E1000_RXD_ERR_SE | \ 146*75eba5b6SRobert Mustacchi E1000_RXD_ERR_SEQ | \ 147*75eba5b6SRobert Mustacchi E1000_RXD_ERR_CXE | \ 148*75eba5b6SRobert Mustacchi E1000_RXD_ERR_RXE) 149*75eba5b6SRobert Mustacchi 150*75eba5b6SRobert Mustacchi /* Same mask, but for extended and packet split descriptors */ 151*75eba5b6SRobert Mustacchi #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 152*75eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_CE | \ 153*75eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_SE | \ 154*75eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_SEQ | \ 155*75eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_CXE | \ 156*75eba5b6SRobert Mustacchi E1000_RXDEXT_STATERR_RXE) 157*75eba5b6SRobert Mustacchi 158*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 159*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 160*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 161*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 162*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 163*75eba5b6SRobert Mustacchi #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 164*75eba5b6SRobert Mustacchi 165*75eba5b6SRobert Mustacchi #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 166*75eba5b6SRobert Mustacchi 167*75eba5b6SRobert Mustacchi /* Management Control */ 168*75eba5b6SRobert Mustacchi #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 169*75eba5b6SRobert Mustacchi #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 170*75eba5b6SRobert Mustacchi #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 171*75eba5b6SRobert Mustacchi #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 172*75eba5b6SRobert Mustacchi #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 173*75eba5b6SRobert Mustacchi /* Enable MAC address filtering */ 174*75eba5b6SRobert Mustacchi #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 175*75eba5b6SRobert Mustacchi /* Enable MNG packets to host memory */ 176*75eba5b6SRobert Mustacchi #define E1000_MANC_EN_MNG2HOST 0x00200000 177*75eba5b6SRobert Mustacchi 178*75eba5b6SRobert Mustacchi #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 179*75eba5b6SRobert Mustacchi #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 180*75eba5b6SRobert Mustacchi #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 181*75eba5b6SRobert Mustacchi #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 182*75eba5b6SRobert Mustacchi 183*75eba5b6SRobert Mustacchi /* Receive Control */ 184*75eba5b6SRobert Mustacchi #define E1000_RCTL_RST 0x00000001 /* Software reset */ 185*75eba5b6SRobert Mustacchi #define E1000_RCTL_EN 0x00000002 /* enable */ 186*75eba5b6SRobert Mustacchi #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 187*75eba5b6SRobert Mustacchi #define E1000_RCTL_UPE 0x00000008 /* unicast promisc enable */ 188*75eba5b6SRobert Mustacchi #define E1000_RCTL_MPE 0x00000010 /* multicast promisc enable */ 189*75eba5b6SRobert Mustacchi #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 190*75eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 191*75eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 192*75eba5b6SRobert Mustacchi #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 193*75eba5b6SRobert Mustacchi #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 194*75eba5b6SRobert Mustacchi #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 195*75eba5b6SRobert Mustacchi #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 196*75eba5b6SRobert Mustacchi #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 197*75eba5b6SRobert Mustacchi #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 198*75eba5b6SRobert Mustacchi /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 199*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 200*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 201*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 202*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 203*75eba5b6SRobert Mustacchi /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 204*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 205*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 206*75eba5b6SRobert Mustacchi #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 207*75eba5b6SRobert Mustacchi #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 208*75eba5b6SRobert Mustacchi #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 209*75eba5b6SRobert Mustacchi #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 210*75eba5b6SRobert Mustacchi #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 211*75eba5b6SRobert Mustacchi #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 212*75eba5b6SRobert Mustacchi #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 213*75eba5b6SRobert Mustacchi #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 214*75eba5b6SRobert Mustacchi 215*75eba5b6SRobert Mustacchi /* Use byte values for the following shift parameters 216*75eba5b6SRobert Mustacchi * Usage: 217*75eba5b6SRobert Mustacchi * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 218*75eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE0_MASK) | 219*75eba5b6SRobert Mustacchi * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 220*75eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE1_MASK) | 221*75eba5b6SRobert Mustacchi * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 222*75eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE2_MASK) | 223*75eba5b6SRobert Mustacchi * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 224*75eba5b6SRobert Mustacchi * E1000_PSRCTL_BSIZE3_MASK)) 225*75eba5b6SRobert Mustacchi * where value0 = [128..16256], default=256 226*75eba5b6SRobert Mustacchi * value1 = [1024..64512], default=4096 227*75eba5b6SRobert Mustacchi * value2 = [0..64512], default=4096 228*75eba5b6SRobert Mustacchi * value3 = [0..64512], default=0 229*75eba5b6SRobert Mustacchi */ 230*75eba5b6SRobert Mustacchi 231*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 232*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 233*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 234*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 235*75eba5b6SRobert Mustacchi 236*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 237*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 238*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 239*75eba5b6SRobert Mustacchi #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 240*75eba5b6SRobert Mustacchi 241*75eba5b6SRobert Mustacchi /* SWFW_SYNC Definitions */ 242*75eba5b6SRobert Mustacchi #define E1000_SWFW_EEP_SM 0x01 243*75eba5b6SRobert Mustacchi #define E1000_SWFW_PHY0_SM 0x02 244*75eba5b6SRobert Mustacchi #define E1000_SWFW_PHY1_SM 0x04 245*75eba5b6SRobert Mustacchi #define E1000_SWFW_CSR_SM 0x08 246*75eba5b6SRobert Mustacchi #define E1000_SWFW_PHY2_SM 0x20 247*75eba5b6SRobert Mustacchi #define E1000_SWFW_PHY3_SM 0x40 248*75eba5b6SRobert Mustacchi #define E1000_SWFW_SW_MNG_SM 0x400 249*75eba5b6SRobert Mustacchi 250*75eba5b6SRobert Mustacchi /* Device Control */ 251*75eba5b6SRobert Mustacchi #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 252*75eba5b6SRobert Mustacchi #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 253*75eba5b6SRobert Mustacchi #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */ 254*75eba5b6SRobert Mustacchi #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 255*75eba5b6SRobert Mustacchi #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 256*75eba5b6SRobert Mustacchi #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 257*75eba5b6SRobert Mustacchi #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 258*75eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 259*75eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 260*75eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 261*75eba5b6SRobert Mustacchi #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 262*75eba5b6SRobert Mustacchi #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 263*75eba5b6SRobert Mustacchi #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 264*75eba5b6SRobert Mustacchi #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 265*75eba5b6SRobert Mustacchi #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 266*75eba5b6SRobert Mustacchi #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 267*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 268*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 269*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 270*75eba5b6SRobert Mustacchi #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 271*75eba5b6SRobert Mustacchi #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 272*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 273*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 274*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 275*75eba5b6SRobert Mustacchi #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 276*75eba5b6SRobert Mustacchi #define E1000_CTRL_RST 0x04000000 /* Global reset */ 277*75eba5b6SRobert Mustacchi #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 278*75eba5b6SRobert Mustacchi #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 279*75eba5b6SRobert Mustacchi #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 280*75eba5b6SRobert Mustacchi #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 281*75eba5b6SRobert Mustacchi #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 282*75eba5b6SRobert Mustacchi 283*75eba5b6SRobert Mustacchi #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 284*75eba5b6SRobert Mustacchi #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 285*75eba5b6SRobert Mustacchi #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 286*75eba5b6SRobert Mustacchi #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 287*75eba5b6SRobert Mustacchi 288*75eba5b6SRobert Mustacchi #define E1000_CONNSW_ENRGSRC 0x4 289*75eba5b6SRobert Mustacchi #define E1000_CONNSW_PHYSD 0x400 290*75eba5b6SRobert Mustacchi #define E1000_CONNSW_SERDESD 0x200 291*75eba5b6SRobert Mustacchi #define E1000_PCS_CFG_PCS_EN 8 292*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FLV_LINK_UP 1 293*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_10 0 294*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_100 2 295*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSV_1000 4 296*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FDV_FULL 8 297*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FSD 0x10 298*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FORCE_LINK 0x20 299*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 300*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_ENABLE 0x10000 301*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_RESTART 0x20000 302*75eba5b6SRobert Mustacchi #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 303*75eba5b6SRobert Mustacchi #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 304*75eba5b6SRobert Mustacchi 305*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_LINK_OK 1 306*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SPEED_100 2 307*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SPEED_1000 4 308*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_DUPLEX_FULL 8 309*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_SYNK_OK 0x10 310*75eba5b6SRobert Mustacchi #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 311*75eba5b6SRobert Mustacchi 312*75eba5b6SRobert Mustacchi /* Device Status */ 313*75eba5b6SRobert Mustacchi #define E1000_STATUS_FD 0x00000001 /* Duplex 0=half 1=full */ 314*75eba5b6SRobert Mustacchi #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 315*75eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 316*75eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_SHIFT 2 317*75eba5b6SRobert Mustacchi #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 318*75eba5b6SRobert Mustacchi #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 319*75eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_MASK 0x000000C0 320*75eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 321*75eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 322*75eba5b6SRobert Mustacchi #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 323*75eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ 324*75eba5b6SRobert Mustacchi #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 325*75eba5b6SRobert Mustacchi #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ 326*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */ 327*75eba5b6SRobert Mustacchi #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 328*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 329*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 330*75eba5b6SRobert Mustacchi 331*75eba5b6SRobert Mustacchi /* Constants used to interpret the masked PCI-X bus speed. */ 332*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */ 333*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */ 334*75eba5b6SRobert Mustacchi #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/ 335*75eba5b6SRobert Mustacchi 336*75eba5b6SRobert Mustacchi #define SPEED_10 10 337*75eba5b6SRobert Mustacchi #define SPEED_100 100 338*75eba5b6SRobert Mustacchi #define SPEED_1000 1000 339*75eba5b6SRobert Mustacchi #define HALF_DUPLEX 1 340*75eba5b6SRobert Mustacchi #define FULL_DUPLEX 2 341*75eba5b6SRobert Mustacchi 342*75eba5b6SRobert Mustacchi #define PHY_FORCE_TIME 20 343*75eba5b6SRobert Mustacchi 344*75eba5b6SRobert Mustacchi #define ADVERTISE_10_HALF 0x0001 345*75eba5b6SRobert Mustacchi #define ADVERTISE_10_FULL 0x0002 346*75eba5b6SRobert Mustacchi #define ADVERTISE_100_HALF 0x0004 347*75eba5b6SRobert Mustacchi #define ADVERTISE_100_FULL 0x0008 348*75eba5b6SRobert Mustacchi #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 349*75eba5b6SRobert Mustacchi #define ADVERTISE_1000_FULL 0x0020 350*75eba5b6SRobert Mustacchi 351*75eba5b6SRobert Mustacchi /* 1000/H is not supported, nor spec-compliant. */ 352*75eba5b6SRobert Mustacchi #define E1000_ALL_SPEED_DUPLEX ( \ 353*75eba5b6SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 354*75eba5b6SRobert Mustacchi ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 355*75eba5b6SRobert Mustacchi #define E1000_ALL_NOT_GIG ( \ 356*75eba5b6SRobert Mustacchi ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 357*75eba5b6SRobert Mustacchi ADVERTISE_100_FULL) 358*75eba5b6SRobert Mustacchi #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 359*75eba5b6SRobert Mustacchi #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 360*75eba5b6SRobert Mustacchi #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 361*75eba5b6SRobert Mustacchi 362*75eba5b6SRobert Mustacchi #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 363*75eba5b6SRobert Mustacchi 364*75eba5b6SRobert Mustacchi /* LED Control */ 365*75eba5b6SRobert Mustacchi #define E1000_PHY_LED0_MODE_MASK 0x00000007 366*75eba5b6SRobert Mustacchi #define E1000_PHY_LED0_IVRT 0x00000008 367*75eba5b6SRobert Mustacchi #define E1000_PHY_LED0_MASK 0x0000001F 368*75eba5b6SRobert Mustacchi 369*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 370*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_MODE_SHIFT 0 371*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_IVRT 0x00000040 372*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_LED0_BLINK 0x00000080 373*75eba5b6SRobert Mustacchi 374*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LINK_UP 0x2 375*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LED_ON 0xE 376*75eba5b6SRobert Mustacchi #define E1000_LEDCTL_MODE_LED_OFF 0xF 377*75eba5b6SRobert Mustacchi 378*75eba5b6SRobert Mustacchi /* Transmit Descriptor bit definitions */ 379*75eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 380*75eba5b6SRobert Mustacchi #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 381*75eba5b6SRobert Mustacchi #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 382*75eba5b6SRobert Mustacchi #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 383*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 384*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 385*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 386*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 387*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 388*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 389*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 390*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 391*75eba5b6SRobert Mustacchi #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 392*75eba5b6SRobert Mustacchi #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 393*75eba5b6SRobert Mustacchi #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 394*75eba5b6SRobert Mustacchi #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 395*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 396*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 397*75eba5b6SRobert Mustacchi #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 398*75eba5b6SRobert Mustacchi #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 399*75eba5b6SRobert Mustacchi #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 400*75eba5b6SRobert Mustacchi 401*75eba5b6SRobert Mustacchi /* Transmit Control */ 402*75eba5b6SRobert Mustacchi #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 403*75eba5b6SRobert Mustacchi #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 404*75eba5b6SRobert Mustacchi #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 405*75eba5b6SRobert Mustacchi #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 406*75eba5b6SRobert Mustacchi #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 407*75eba5b6SRobert Mustacchi #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 408*75eba5b6SRobert Mustacchi 409*75eba5b6SRobert Mustacchi /* Transmit Arbitration Count */ 410*75eba5b6SRobert Mustacchi #define E1000_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */ 411*75eba5b6SRobert Mustacchi 412*75eba5b6SRobert Mustacchi /* SerDes Control */ 413*75eba5b6SRobert Mustacchi #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 414*75eba5b6SRobert Mustacchi #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 415*75eba5b6SRobert Mustacchi 416*75eba5b6SRobert Mustacchi /* Receive Checksum Control */ 417*75eba5b6SRobert Mustacchi #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 418*75eba5b6SRobert Mustacchi #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 419*75eba5b6SRobert Mustacchi #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 420*75eba5b6SRobert Mustacchi #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 421*75eba5b6SRobert Mustacchi #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 422*75eba5b6SRobert Mustacchi 423*75eba5b6SRobert Mustacchi /* Header split receive */ 424*75eba5b6SRobert Mustacchi #define E1000_RFCTL_NFSW_DIS 0x00000040 425*75eba5b6SRobert Mustacchi #define E1000_RFCTL_NFSR_DIS 0x00000080 426*75eba5b6SRobert Mustacchi #define E1000_RFCTL_ACK_DIS 0x00001000 427*75eba5b6SRobert Mustacchi #define E1000_RFCTL_EXTEN 0x00008000 428*75eba5b6SRobert Mustacchi #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 429*75eba5b6SRobert Mustacchi #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 430*75eba5b6SRobert Mustacchi #define E1000_RFCTL_LEF 0x00040000 431*75eba5b6SRobert Mustacchi 432*75eba5b6SRobert Mustacchi /* Collision related configuration parameters */ 433*75eba5b6SRobert Mustacchi #define E1000_COLLISION_THRESHOLD 15 434*75eba5b6SRobert Mustacchi #define E1000_CT_SHIFT 4 435*75eba5b6SRobert Mustacchi #define E1000_COLLISION_DISTANCE 63 436*75eba5b6SRobert Mustacchi #define E1000_COLD_SHIFT 12 437*75eba5b6SRobert Mustacchi 438*75eba5b6SRobert Mustacchi /* Default values for the transmit IPG register */ 439*75eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGT 10 440*75eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_FIBER 9 441*75eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGT_COPPER 8 442*75eba5b6SRobert Mustacchi 443*75eba5b6SRobert Mustacchi #define E1000_TIPG_IPGT_MASK 0x000003FF 444*75eba5b6SRobert Mustacchi 445*75eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGR1 2 446*75eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR1 8 447*75eba5b6SRobert Mustacchi #define E1000_TIPG_IPGR1_SHIFT 10 448*75eba5b6SRobert Mustacchi 449*75eba5b6SRobert Mustacchi #define DEFAULT_82542_TIPG_IPGR2 10 450*75eba5b6SRobert Mustacchi #define DEFAULT_82543_TIPG_IPGR2 6 451*75eba5b6SRobert Mustacchi #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 452*75eba5b6SRobert Mustacchi #define E1000_TIPG_IPGR2_SHIFT 20 453*75eba5b6SRobert Mustacchi 454*75eba5b6SRobert Mustacchi /* Ethertype field values */ 455*75eba5b6SRobert Mustacchi #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 456*75eba5b6SRobert Mustacchi 457*75eba5b6SRobert Mustacchi #define ETHERNET_FCS_SIZE 4 458*75eba5b6SRobert Mustacchi #define MAX_JUMBO_FRAME_SIZE 0x3F00 459*75eba5b6SRobert Mustacchi 460*75eba5b6SRobert Mustacchi /* Extended Configuration Control and Size */ 461*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 462*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 463*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 464*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 465*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 466*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 467*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 468*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 469*75eba5b6SRobert Mustacchi #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 470*75eba5b6SRobert Mustacchi 471*75eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 472*75eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 473*75eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 474*75eba5b6SRobert Mustacchi #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 475*75eba5b6SRobert Mustacchi 476*75eba5b6SRobert Mustacchi #define E1000_KABGTXD_BGSQLBIAS 0x00050000 477*75eba5b6SRobert Mustacchi 478*75eba5b6SRobert Mustacchi /* Low Power IDLE Control */ 479*75eba5b6SRobert Mustacchi #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 480*75eba5b6SRobert Mustacchi 481*75eba5b6SRobert Mustacchi /* PBA constants */ 482*75eba5b6SRobert Mustacchi #define E1000_PBA_8K 0x0008 /* 8KB */ 483*75eba5b6SRobert Mustacchi #define E1000_PBA_10K 0x000A /* 10KB */ 484*75eba5b6SRobert Mustacchi #define E1000_PBA_12K 0x000C /* 12KB */ 485*75eba5b6SRobert Mustacchi #define E1000_PBA_14K 0x000E /* 14KB */ 486*75eba5b6SRobert Mustacchi #define E1000_PBA_16K 0x0010 /* 16KB */ 487*75eba5b6SRobert Mustacchi #define E1000_PBA_18K 0x0012 488*75eba5b6SRobert Mustacchi #define E1000_PBA_20K 0x0014 489*75eba5b6SRobert Mustacchi #define E1000_PBA_22K 0x0016 490*75eba5b6SRobert Mustacchi #define E1000_PBA_24K 0x0018 491*75eba5b6SRobert Mustacchi #define E1000_PBA_26K 0x001A 492*75eba5b6SRobert Mustacchi #define E1000_PBA_30K 0x001E 493*75eba5b6SRobert Mustacchi #define E1000_PBA_32K 0x0020 494*75eba5b6SRobert Mustacchi #define E1000_PBA_34K 0x0022 495*75eba5b6SRobert Mustacchi #define E1000_PBA_35K 0x0023 496*75eba5b6SRobert Mustacchi #define E1000_PBA_38K 0x0026 497*75eba5b6SRobert Mustacchi #define E1000_PBA_40K 0x0028 498*75eba5b6SRobert Mustacchi #define E1000_PBA_48K 0x0030 /* 48KB */ 499*75eba5b6SRobert Mustacchi #define E1000_PBA_64K 0x0040 /* 64KB */ 500*75eba5b6SRobert Mustacchi 501*75eba5b6SRobert Mustacchi #define E1000_PBA_RXA_MASK 0xFFFF 502*75eba5b6SRobert Mustacchi 503*75eba5b6SRobert Mustacchi #define E1000_PBS_16K E1000_PBA_16K 504*75eba5b6SRobert Mustacchi 505*75eba5b6SRobert Mustacchi /* Uncorrectable/correctable ECC Error counts and enable bits */ 506*75eba5b6SRobert Mustacchi #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 507*75eba5b6SRobert Mustacchi #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 508*75eba5b6SRobert Mustacchi #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 509*75eba5b6SRobert Mustacchi #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 510*75eba5b6SRobert Mustacchi 511*75eba5b6SRobert Mustacchi #define IFS_MAX 80 512*75eba5b6SRobert Mustacchi #define IFS_MIN 40 513*75eba5b6SRobert Mustacchi #define IFS_RATIO 4 514*75eba5b6SRobert Mustacchi #define IFS_STEP 10 515*75eba5b6SRobert Mustacchi #define MIN_NUM_XMITS 1000 516*75eba5b6SRobert Mustacchi 517*75eba5b6SRobert Mustacchi /* SW Semaphore Register */ 518*75eba5b6SRobert Mustacchi #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 519*75eba5b6SRobert Mustacchi #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 520*75eba5b6SRobert Mustacchi #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 521*75eba5b6SRobert Mustacchi 522*75eba5b6SRobert Mustacchi #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 523*75eba5b6SRobert Mustacchi 524*75eba5b6SRobert Mustacchi /* Interrupt Cause Read */ 525*75eba5b6SRobert Mustacchi #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 526*75eba5b6SRobert Mustacchi #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 527*75eba5b6SRobert Mustacchi #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 528*75eba5b6SRobert Mustacchi #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 529*75eba5b6SRobert Mustacchi #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 530*75eba5b6SRobert Mustacchi #define E1000_ICR_RXO 0x00000040 /* Rx overrun */ 531*75eba5b6SRobert Mustacchi #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 532*75eba5b6SRobert Mustacchi #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 533*75eba5b6SRobert Mustacchi #define E1000_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */ 534*75eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 535*75eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 536*75eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 537*75eba5b6SRobert Mustacchi #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 538*75eba5b6SRobert Mustacchi #define E1000_ICR_TXD_LOW 0x00008000 539*75eba5b6SRobert Mustacchi #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 540*75eba5b6SRobert Mustacchi #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 541*75eba5b6SRobert Mustacchi #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 542*75eba5b6SRobert Mustacchi #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 543*75eba5b6SRobert Mustacchi /* If this bit asserted, the driver should claim the interrupt */ 544*75eba5b6SRobert Mustacchi #define E1000_ICR_INT_ASSERTED 0x80000000 545*75eba5b6SRobert Mustacchi #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 546*75eba5b6SRobert Mustacchi #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 547*75eba5b6SRobert Mustacchi #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 548*75eba5b6SRobert Mustacchi #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 549*75eba5b6SRobert Mustacchi #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 550*75eba5b6SRobert Mustacchi #define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 551*75eba5b6SRobert Mustacchi #define E1000_ICR_FER 0x00400000 /* Fatal Error */ 552*75eba5b6SRobert Mustacchi 553*75eba5b6SRobert Mustacchi #define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/ 554*75eba5b6SRobert Mustacchi #define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */ 555*75eba5b6SRobert Mustacchi 556*75eba5b6SRobert Mustacchi #define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */ 557*75eba5b6SRobert Mustacchi #define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */ 558*75eba5b6SRobert Mustacchi 559*75eba5b6SRobert Mustacchi /* PBA ECC Register */ 560*75eba5b6SRobert Mustacchi #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 561*75eba5b6SRobert Mustacchi #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 562*75eba5b6SRobert Mustacchi #define E1000_PBA_ECC_CORR_EN 0x00000001 /* Enable ECC error correction */ 563*75eba5b6SRobert Mustacchi #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 564*75eba5b6SRobert Mustacchi #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 on ECC error */ 565*75eba5b6SRobert Mustacchi 566*75eba5b6SRobert Mustacchi /* Extended Interrupt Cause Read */ 567*75eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 568*75eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 569*75eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 570*75eba5b6SRobert Mustacchi #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 571*75eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 572*75eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 573*75eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 574*75eba5b6SRobert Mustacchi #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 575*75eba5b6SRobert Mustacchi #define E1000_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 576*75eba5b6SRobert Mustacchi #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 577*75eba5b6SRobert Mustacchi /* TCP Timer */ 578*75eba5b6SRobert Mustacchi #define E1000_TCPTIMER_KS 0x00000100 /* KickStart */ 579*75eba5b6SRobert Mustacchi #define E1000_TCPTIMER_COUNT_ENABLE 0x00000200 /* Count Enable */ 580*75eba5b6SRobert Mustacchi #define E1000_TCPTIMER_COUNT_FINISH 0x00000400 /* Count finish */ 581*75eba5b6SRobert Mustacchi #define E1000_TCPTIMER_LOOP 0x00000800 /* Loop */ 582*75eba5b6SRobert Mustacchi 583*75eba5b6SRobert Mustacchi /* This defines the bits that are set in the Interrupt Mask 584*75eba5b6SRobert Mustacchi * Set/Read Register. Each bit is documented below: 585*75eba5b6SRobert Mustacchi * o RXT0 = Receiver Timer Interrupt (ring 0) 586*75eba5b6SRobert Mustacchi * o TXDW = Transmit Descriptor Written Back 587*75eba5b6SRobert Mustacchi * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 588*75eba5b6SRobert Mustacchi * o RXSEQ = Receive Sequence Error 589*75eba5b6SRobert Mustacchi * o LSC = Link Status Change 590*75eba5b6SRobert Mustacchi */ 591*75eba5b6SRobert Mustacchi #define IMS_ENABLE_MASK ( \ 592*75eba5b6SRobert Mustacchi E1000_IMS_RXT0 | \ 593*75eba5b6SRobert Mustacchi E1000_IMS_TXDW | \ 594*75eba5b6SRobert Mustacchi E1000_IMS_RXDMT0 | \ 595*75eba5b6SRobert Mustacchi E1000_IMS_RXSEQ | \ 596*75eba5b6SRobert Mustacchi E1000_IMS_LSC) 597*75eba5b6SRobert Mustacchi 598*75eba5b6SRobert Mustacchi /* Interrupt Mask Set */ 599*75eba5b6SRobert Mustacchi #define E1000_IMS_TXDW E1000_ICR_TXDW /* Tx desc written back */ 600*75eba5b6SRobert Mustacchi #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 601*75eba5b6SRobert Mustacchi #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 602*75eba5b6SRobert Mustacchi #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 603*75eba5b6SRobert Mustacchi #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 604*75eba5b6SRobert Mustacchi #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 605*75eba5b6SRobert Mustacchi #define E1000_IMS_RXO E1000_ICR_RXO /* Rx overrun */ 606*75eba5b6SRobert Mustacchi #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 607*75eba5b6SRobert Mustacchi #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 608*75eba5b6SRobert Mustacchi #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 609*75eba5b6SRobert Mustacchi #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 610*75eba5b6SRobert Mustacchi #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 611*75eba5b6SRobert Mustacchi #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 612*75eba5b6SRobert Mustacchi #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 613*75eba5b6SRobert Mustacchi #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 614*75eba5b6SRobert Mustacchi #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 615*75eba5b6SRobert Mustacchi #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 616*75eba5b6SRobert Mustacchi #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 617*75eba5b6SRobert Mustacchi #define E1000_IMS_FER E1000_ICR_FER /* Fatal Error */ 618*75eba5b6SRobert Mustacchi 619*75eba5b6SRobert Mustacchi #define E1000_IMS_THS E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/ 620*75eba5b6SRobert Mustacchi #define E1000_IMS_MDDET E1000_ICR_MDDET /* Malicious Driver Detect */ 621*75eba5b6SRobert Mustacchi /* Extended Interrupt Mask Set */ 622*75eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 623*75eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 624*75eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 625*75eba5b6SRobert Mustacchi #define E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 626*75eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 627*75eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 628*75eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 629*75eba5b6SRobert Mustacchi #define E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 630*75eba5b6SRobert Mustacchi #define E1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 631*75eba5b6SRobert Mustacchi #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 632*75eba5b6SRobert Mustacchi 633*75eba5b6SRobert Mustacchi /* Interrupt Cause Set */ 634*75eba5b6SRobert Mustacchi #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 635*75eba5b6SRobert Mustacchi #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 636*75eba5b6SRobert Mustacchi #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 637*75eba5b6SRobert Mustacchi 638*75eba5b6SRobert Mustacchi /* Extended Interrupt Cause Set */ 639*75eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */ 640*75eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */ 641*75eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */ 642*75eba5b6SRobert Mustacchi #define E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */ 643*75eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */ 644*75eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */ 645*75eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */ 646*75eba5b6SRobert Mustacchi #define E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */ 647*75eba5b6SRobert Mustacchi #define E1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER /* TCP Timer */ 648*75eba5b6SRobert Mustacchi #define E1000_EICS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 649*75eba5b6SRobert Mustacchi 650*75eba5b6SRobert Mustacchi #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 651*75eba5b6SRobert Mustacchi /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 652*75eba5b6SRobert Mustacchi #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 653*75eba5b6SRobert Mustacchi 654*75eba5b6SRobert Mustacchi /* Transmit Descriptor Control */ 655*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 656*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 657*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 658*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 659*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 660*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 661*75eba5b6SRobert Mustacchi /* Enable the counting of descriptors still to be processed. */ 662*75eba5b6SRobert Mustacchi #define E1000_TXDCTL_COUNT_DESC 0x00400000 663*75eba5b6SRobert Mustacchi 664*75eba5b6SRobert Mustacchi /* Flow Control Constants */ 665*75eba5b6SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 666*75eba5b6SRobert Mustacchi #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 667*75eba5b6SRobert Mustacchi #define FLOW_CONTROL_TYPE 0x8808 668*75eba5b6SRobert Mustacchi 669*75eba5b6SRobert Mustacchi /* 802.1q VLAN Packet Size */ 670*75eba5b6SRobert Mustacchi #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 671*75eba5b6SRobert Mustacchi #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 672*75eba5b6SRobert Mustacchi 673*75eba5b6SRobert Mustacchi /* Receive Address 674*75eba5b6SRobert Mustacchi * Number of high/low register pairs in the RAR. The RAR (Receive Address 675*75eba5b6SRobert Mustacchi * Registers) holds the directed and multicast addresses that we monitor. 676*75eba5b6SRobert Mustacchi * Technically, we have 16 spots. However, we reserve one of these spots 677*75eba5b6SRobert Mustacchi * (RAR[15]) for our directed address used by controllers with 678*75eba5b6SRobert Mustacchi * manageability enabled, allowing us room for 15 multicast addresses. 679*75eba5b6SRobert Mustacchi */ 680*75eba5b6SRobert Mustacchi #define E1000_RAR_ENTRIES 15 681*75eba5b6SRobert Mustacchi #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 682*75eba5b6SRobert Mustacchi #define E1000_RAL_MAC_ADDR_LEN 4 683*75eba5b6SRobert Mustacchi #define E1000_RAH_MAC_ADDR_LEN 2 684*75eba5b6SRobert Mustacchi #define E1000_RAH_QUEUE_MASK_82575 0x000C0000 685*75eba5b6SRobert Mustacchi #define E1000_RAH_POOL_1 0x00040000 686*75eba5b6SRobert Mustacchi 687*75eba5b6SRobert Mustacchi /* Error Codes */ 688*75eba5b6SRobert Mustacchi #define E1000_SUCCESS 0 689*75eba5b6SRobert Mustacchi #define E1000_ERR_NVM 1 690*75eba5b6SRobert Mustacchi #define E1000_ERR_PHY 2 691*75eba5b6SRobert Mustacchi #define E1000_ERR_CONFIG 3 692*75eba5b6SRobert Mustacchi #define E1000_ERR_PARAM 4 693*75eba5b6SRobert Mustacchi #define E1000_ERR_MAC_INIT 5 694*75eba5b6SRobert Mustacchi #define E1000_ERR_PHY_TYPE 6 695*75eba5b6SRobert Mustacchi #define E1000_ERR_RESET 9 696*75eba5b6SRobert Mustacchi #define E1000_ERR_MASTER_REQUESTS_PENDING 10 697*75eba5b6SRobert Mustacchi #define E1000_ERR_HOST_INTERFACE_COMMAND 11 698*75eba5b6SRobert Mustacchi #define E1000_BLK_PHY_RESET 12 699*75eba5b6SRobert Mustacchi #define E1000_ERR_SWFW_SYNC 13 700*75eba5b6SRobert Mustacchi #define E1000_NOT_IMPLEMENTED 14 701*75eba5b6SRobert Mustacchi #define E1000_ERR_MBX 15 702*75eba5b6SRobert Mustacchi #define E1000_ERR_INVALID_ARGUMENT 16 703*75eba5b6SRobert Mustacchi #define E1000_ERR_NO_SPACE 17 704*75eba5b6SRobert Mustacchi #define E1000_ERR_NVM_PBA_SECTION 18 705*75eba5b6SRobert Mustacchi #define E1000_ERR_I2C 19 706*75eba5b6SRobert Mustacchi #define E1000_ERR_INVM_VALUE_NOT_FOUND 20 707*75eba5b6SRobert Mustacchi 708*75eba5b6SRobert Mustacchi /* Loop limit on how long we wait for auto-negotiation to complete */ 709*75eba5b6SRobert Mustacchi #define FIBER_LINK_UP_LIMIT 50 710*75eba5b6SRobert Mustacchi #define COPPER_LINK_UP_LIMIT 10 711*75eba5b6SRobert Mustacchi #define PHY_AUTO_NEG_LIMIT 45 712*75eba5b6SRobert Mustacchi #define PHY_FORCE_LIMIT 20 713*75eba5b6SRobert Mustacchi /* Number of 100 microseconds we wait for PCI Express master disable */ 714*75eba5b6SRobert Mustacchi #define MASTER_DISABLE_TIMEOUT 800 715*75eba5b6SRobert Mustacchi /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 716*75eba5b6SRobert Mustacchi #define PHY_CFG_TIMEOUT 100 717*75eba5b6SRobert Mustacchi /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 718*75eba5b6SRobert Mustacchi #define MDIO_OWNERSHIP_TIMEOUT 10 719*75eba5b6SRobert Mustacchi /* Number of milliseconds for NVM auto read done after MAC reset. */ 720*75eba5b6SRobert Mustacchi #define AUTO_READ_DONE_TIMEOUT 10 721*75eba5b6SRobert Mustacchi 722*75eba5b6SRobert Mustacchi /* Flow Control */ 723*75eba5b6SRobert Mustacchi #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 724*75eba5b6SRobert Mustacchi #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 725*75eba5b6SRobert Mustacchi #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 726*75eba5b6SRobert Mustacchi 727*75eba5b6SRobert Mustacchi /* Transmit Configuration Word */ 728*75eba5b6SRobert Mustacchi #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 729*75eba5b6SRobert Mustacchi #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 730*75eba5b6SRobert Mustacchi #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 731*75eba5b6SRobert Mustacchi #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 732*75eba5b6SRobert Mustacchi #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 733*75eba5b6SRobert Mustacchi 734*75eba5b6SRobert Mustacchi /* Receive Configuration Word */ 735*75eba5b6SRobert Mustacchi #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 736*75eba5b6SRobert Mustacchi #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 737*75eba5b6SRobert Mustacchi #define E1000_RXCW_C 0x20000000 /* Receive config */ 738*75eba5b6SRobert Mustacchi #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 739*75eba5b6SRobert Mustacchi 740*75eba5b6SRobert Mustacchi #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 741*75eba5b6SRobert Mustacchi #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 742*75eba5b6SRobert Mustacchi 743*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 744*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 745*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 746*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 747*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 748*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 749*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 750*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 751*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 752*75eba5b6SRobert Mustacchi 753*75eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 754*75eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 755*75eba5b6SRobert Mustacchi 756*75eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 757*75eba5b6SRobert Mustacchi #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 758*75eba5b6SRobert Mustacchi 759*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 760*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 761*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 762*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 763*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 764*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 765*75eba5b6SRobert Mustacchi 766*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 767*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 768*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 769*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 770*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 771*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 772*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 773*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 774*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 775*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 776*75eba5b6SRobert Mustacchi #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 777*75eba5b6SRobert Mustacchi 778*75eba5b6SRobert Mustacchi #define E1000_TIMINCA_16NS_SHIFT 24 779*75eba5b6SRobert Mustacchi #define E1000_TIMINCA_INCPERIOD_SHIFT 24 780*75eba5b6SRobert Mustacchi #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 781*75eba5b6SRobert Mustacchi 782*75eba5b6SRobert Mustacchi #define E1000_TSICR_TXTS 0x00000002 783*75eba5b6SRobert Mustacchi #define E1000_TSIM_TXTS 0x00000002 784*75eba5b6SRobert Mustacchi /* TUPLE Filtering Configuration */ 785*75eba5b6SRobert Mustacchi #define E1000_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */ 786*75eba5b6SRobert Mustacchi #define E1000_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */ 787*75eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */ 788*75eba5b6SRobert Mustacchi /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */ 789*75eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_TCP 0x0 790*75eba5b6SRobert Mustacchi /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 791*75eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_UDP 0x1 792*75eba5b6SRobert Mustacchi /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */ 793*75eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_SCTP 0x2 794*75eba5b6SRobert Mustacchi #define E1000_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */ 795*75eba5b6SRobert Mustacchi #define E1000_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */ 796*75eba5b6SRobert Mustacchi #define E1000_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */ 797*75eba5b6SRobert Mustacchi #define E1000_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */ 798*75eba5b6SRobert Mustacchi #define E1000_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */ 799*75eba5b6SRobert Mustacchi #define E1000_IMIR_PORT_BYPASS 0x20000 /* IMIR Port Bypass Bit */ 800*75eba5b6SRobert Mustacchi #define E1000_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */ 801*75eba5b6SRobert Mustacchi #define E1000_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */ 802*75eba5b6SRobert Mustacchi 803*75eba5b6SRobert Mustacchi #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 804*75eba5b6SRobert Mustacchi #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 805*75eba5b6SRobert Mustacchi #define E1000_MDICNFG_PHY_MASK 0x03E00000 806*75eba5b6SRobert Mustacchi #define E1000_MDICNFG_PHY_SHIFT 21 807*75eba5b6SRobert Mustacchi 808*75eba5b6SRobert Mustacchi #define E1000_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */ 809*75eba5b6SRobert Mustacchi #define E1000_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */ 810*75eba5b6SRobert Mustacchi #define E1000_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */ 811*75eba5b6SRobert Mustacchi #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 812*75eba5b6SRobert Mustacchi #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Spd Throttle Event */ 813*75eba5b6SRobert Mustacchi 814*75eba5b6SRobert Mustacchi /* I350 EEE defines */ 815*75eba5b6SRobert Mustacchi #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 816*75eba5b6SRobert Mustacchi #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 817*75eba5b6SRobert Mustacchi #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 818*75eba5b6SRobert Mustacchi #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 819*75eba5b6SRobert Mustacchi #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 820*75eba5b6SRobert Mustacchi /* EEE status */ 821*75eba5b6SRobert Mustacchi #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 822*75eba5b6SRobert Mustacchi #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 823*75eba5b6SRobert Mustacchi #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 824*75eba5b6SRobert Mustacchi #define E1000_EEE_SU_LPI_CLK_STP 0x00800000 /* EEE LPI Clock Stop */ 825*75eba5b6SRobert Mustacchi /* PCI Express Control */ 826*75eba5b6SRobert Mustacchi #define E1000_GCR_RXD_NO_SNOOP 0x00000001 827*75eba5b6SRobert Mustacchi #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 828*75eba5b6SRobert Mustacchi #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 829*75eba5b6SRobert Mustacchi #define E1000_GCR_TXD_NO_SNOOP 0x00000008 830*75eba5b6SRobert Mustacchi #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 831*75eba5b6SRobert Mustacchi #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 832*75eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 833*75eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 834*75eba5b6SRobert Mustacchi #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 835*75eba5b6SRobert Mustacchi #define E1000_GCR_CAP_VER2 0x00040000 836*75eba5b6SRobert Mustacchi 837*75eba5b6SRobert Mustacchi #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 838*75eba5b6SRobert Mustacchi E1000_GCR_RXDSCW_NO_SNOOP | \ 839*75eba5b6SRobert Mustacchi E1000_GCR_RXDSCR_NO_SNOOP | \ 840*75eba5b6SRobert Mustacchi E1000_GCR_TXD_NO_SNOOP | \ 841*75eba5b6SRobert Mustacchi E1000_GCR_TXDSCW_NO_SNOOP | \ 842*75eba5b6SRobert Mustacchi E1000_GCR_TXDSCR_NO_SNOOP) 843*75eba5b6SRobert Mustacchi 844*75eba5b6SRobert Mustacchi /* mPHY address control and data registers */ 845*75eba5b6SRobert Mustacchi #define E1000_MPHY_ADDR_CTL 0x0024 /* Address Control Reg */ 846*75eba5b6SRobert Mustacchi #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 847*75eba5b6SRobert Mustacchi #define E1000_MPHY_DATA 0x0E10 /* Data Register */ 848*75eba5b6SRobert Mustacchi 849*75eba5b6SRobert Mustacchi /* AFE CSR Offset for PCS CLK */ 850*75eba5b6SRobert Mustacchi #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 851*75eba5b6SRobert Mustacchi /* Override for near end digital loopback. */ 852*75eba5b6SRobert Mustacchi #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 853*75eba5b6SRobert Mustacchi 854*75eba5b6SRobert Mustacchi /* PHY Control Register */ 855*75eba5b6SRobert Mustacchi #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 856*75eba5b6SRobert Mustacchi #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 857*75eba5b6SRobert Mustacchi #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 858*75eba5b6SRobert Mustacchi #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 859*75eba5b6SRobert Mustacchi #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 860*75eba5b6SRobert Mustacchi #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 861*75eba5b6SRobert Mustacchi #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 862*75eba5b6SRobert Mustacchi #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 863*75eba5b6SRobert Mustacchi #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 864*75eba5b6SRobert Mustacchi #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 865*75eba5b6SRobert Mustacchi #define MII_CR_SPEED_1000 0x0040 866*75eba5b6SRobert Mustacchi #define MII_CR_SPEED_100 0x2000 867*75eba5b6SRobert Mustacchi #define MII_CR_SPEED_10 0x0000 868*75eba5b6SRobert Mustacchi 869*75eba5b6SRobert Mustacchi /* PHY Status Register */ 870*75eba5b6SRobert Mustacchi #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 871*75eba5b6SRobert Mustacchi #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 872*75eba5b6SRobert Mustacchi #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 873*75eba5b6SRobert Mustacchi #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 874*75eba5b6SRobert Mustacchi #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 875*75eba5b6SRobert Mustacchi #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 876*75eba5b6SRobert Mustacchi #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 877*75eba5b6SRobert Mustacchi #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 878*75eba5b6SRobert Mustacchi #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 879*75eba5b6SRobert Mustacchi #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 880*75eba5b6SRobert Mustacchi #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 881*75eba5b6SRobert Mustacchi #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 882*75eba5b6SRobert Mustacchi #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 883*75eba5b6SRobert Mustacchi #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 884*75eba5b6SRobert Mustacchi #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 885*75eba5b6SRobert Mustacchi 886*75eba5b6SRobert Mustacchi /* Autoneg Advertisement Register */ 887*75eba5b6SRobert Mustacchi #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 888*75eba5b6SRobert Mustacchi #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 889*75eba5b6SRobert Mustacchi #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 890*75eba5b6SRobert Mustacchi #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 891*75eba5b6SRobert Mustacchi #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 892*75eba5b6SRobert Mustacchi #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 893*75eba5b6SRobert Mustacchi #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 894*75eba5b6SRobert Mustacchi #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 895*75eba5b6SRobert Mustacchi #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 896*75eba5b6SRobert Mustacchi #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 897*75eba5b6SRobert Mustacchi 898*75eba5b6SRobert Mustacchi /* Link Partner Ability Register (Base Page) */ 899*75eba5b6SRobert Mustacchi #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 900*75eba5b6SRobert Mustacchi #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */ 901*75eba5b6SRobert Mustacchi #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */ 902*75eba5b6SRobert Mustacchi #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */ 903*75eba5b6SRobert Mustacchi #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 904*75eba5b6SRobert Mustacchi #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 905*75eba5b6SRobert Mustacchi #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 906*75eba5b6SRobert Mustacchi #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */ 907*75eba5b6SRobert Mustacchi #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */ 908*75eba5b6SRobert Mustacchi #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */ 909*75eba5b6SRobert Mustacchi #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 910*75eba5b6SRobert Mustacchi 911*75eba5b6SRobert Mustacchi /* Autoneg Expansion Register */ 912*75eba5b6SRobert Mustacchi #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 913*75eba5b6SRobert Mustacchi #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */ 914*75eba5b6SRobert Mustacchi #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */ 915*75eba5b6SRobert Mustacchi #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */ 916*75eba5b6SRobert Mustacchi #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */ 917*75eba5b6SRobert Mustacchi 918*75eba5b6SRobert Mustacchi /* 1000BASE-T Control Register */ 919*75eba5b6SRobert Mustacchi #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 920*75eba5b6SRobert Mustacchi #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 921*75eba5b6SRobert Mustacchi #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 922*75eba5b6SRobert Mustacchi /* 1=Repeater/switch device port 0=DTE device */ 923*75eba5b6SRobert Mustacchi #define CR_1000T_REPEATER_DTE 0x0400 924*75eba5b6SRobert Mustacchi /* 1=Configure PHY as Master 0=Configure PHY as Slave */ 925*75eba5b6SRobert Mustacchi #define CR_1000T_MS_VALUE 0x0800 926*75eba5b6SRobert Mustacchi /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */ 927*75eba5b6SRobert Mustacchi #define CR_1000T_MS_ENABLE 0x1000 928*75eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 929*75eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 930*75eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 931*75eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 932*75eba5b6SRobert Mustacchi #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 933*75eba5b6SRobert Mustacchi 934*75eba5b6SRobert Mustacchi /* 1000BASE-T Status Register */ 935*75eba5b6SRobert Mustacchi #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle err since last rd */ 936*75eba5b6SRobert Mustacchi #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */ 937*75eba5b6SRobert Mustacchi #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 938*75eba5b6SRobert Mustacchi #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 939*75eba5b6SRobert Mustacchi #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 940*75eba5b6SRobert Mustacchi #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 941*75eba5b6SRobert Mustacchi #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local Tx Master, 0=Slave */ 942*75eba5b6SRobert Mustacchi #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 943*75eba5b6SRobert Mustacchi 944*75eba5b6SRobert Mustacchi #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 945*75eba5b6SRobert Mustacchi 946*75eba5b6SRobert Mustacchi /* PHY 1000 MII Register/Bit Definitions */ 947*75eba5b6SRobert Mustacchi /* PHY Registers defined by IEEE */ 948*75eba5b6SRobert Mustacchi #define PHY_CONTROL 0x00 /* Control Register */ 949*75eba5b6SRobert Mustacchi #define PHY_STATUS 0x01 /* Status Register */ 950*75eba5b6SRobert Mustacchi #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 951*75eba5b6SRobert Mustacchi #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 952*75eba5b6SRobert Mustacchi #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 953*75eba5b6SRobert Mustacchi #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 954*75eba5b6SRobert Mustacchi #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 955*75eba5b6SRobert Mustacchi #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */ 956*75eba5b6SRobert Mustacchi #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 957*75eba5b6SRobert Mustacchi #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 958*75eba5b6SRobert Mustacchi #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 959*75eba5b6SRobert Mustacchi #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 960*75eba5b6SRobert Mustacchi 961*75eba5b6SRobert Mustacchi #define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 962*75eba5b6SRobert Mustacchi 963*75eba5b6SRobert Mustacchi /* NVM Control */ 964*75eba5b6SRobert Mustacchi #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 965*75eba5b6SRobert Mustacchi #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 966*75eba5b6SRobert Mustacchi #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 967*75eba5b6SRobert Mustacchi #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 968*75eba5b6SRobert Mustacchi #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 969*75eba5b6SRobert Mustacchi #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 970*75eba5b6SRobert Mustacchi #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 971*75eba5b6SRobert Mustacchi #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 972*75eba5b6SRobert Mustacchi #define E1000_EECD_BLOCKED 0x00008000 /* Bit banging access blocked flag */ 973*75eba5b6SRobert Mustacchi #define E1000_EECD_ABORT 0x00010000 /* NVM operation aborted flag */ 974*75eba5b6SRobert Mustacchi #define E1000_EECD_TIMEOUT 0x00020000 /* NVM read operation timeout flag */ 975*75eba5b6SRobert Mustacchi #define E1000_EECD_ERROR_CLR 0x00040000 /* NVM error status clear bit */ 976*75eba5b6SRobert Mustacchi /* NVM Addressing bits based on type 0=small, 1=large */ 977*75eba5b6SRobert Mustacchi #define E1000_EECD_ADDR_BITS 0x00000400 978*75eba5b6SRobert Mustacchi #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */ 979*75eba5b6SRobert Mustacchi #ifndef E1000_NVM_GRANT_ATTEMPTS 980*75eba5b6SRobert Mustacchi #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 981*75eba5b6SRobert Mustacchi #endif 982*75eba5b6SRobert Mustacchi #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 983*75eba5b6SRobert Mustacchi #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 984*75eba5b6SRobert Mustacchi #define E1000_EECD_SIZE_EX_SHIFT 11 985*75eba5b6SRobert Mustacchi #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 986*75eba5b6SRobert Mustacchi #define E1000_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */ 987*75eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 988*75eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 989*75eba5b6SRobert Mustacchi #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 990*75eba5b6SRobert Mustacchi #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done */ 991*75eba5b6SRobert Mustacchi #define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 992*75eba5b6SRobert Mustacchi #define E1000_EECD_SEC1VAL_I210 0x02000000 /* Sector One Valid */ 993*75eba5b6SRobert Mustacchi #define E1000_FLUDONE_ATTEMPTS 20000 994*75eba5b6SRobert Mustacchi #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 995*75eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_RX 0x00 996*75eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 997*75eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 998*75eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 999*75eba5b6SRobert Mustacchi #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 1000*75eba5b6SRobert Mustacchi 1001*75eba5b6SRobert Mustacchi #define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 1002*75eba5b6SRobert Mustacchi /* Secure FLASH mode requires removing MSb */ 1003*75eba5b6SRobert Mustacchi #define E1000_I210_FW_PTR_MASK 0x7FFF 1004*75eba5b6SRobert Mustacchi /* Firmware code revision field word offset*/ 1005*75eba5b6SRobert Mustacchi #define E1000_I210_FW_VER_OFFSET 328 1006*75eba5b6SRobert Mustacchi 1007*75eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write regs */ 1008*75eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1009*75eba5b6SRobert Mustacchi #define E1000_NVM_RW_REG_START 1 /* Start operation */ 1010*75eba5b6SRobert Mustacchi #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1011*75eba5b6SRobert Mustacchi #define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 1012*75eba5b6SRobert Mustacchi #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 1013*75eba5b6SRobert Mustacchi #define E1000_FLASH_UPDATES 2000 1014*75eba5b6SRobert Mustacchi 1015*75eba5b6SRobert Mustacchi /* NVM Word Offsets */ 1016*75eba5b6SRobert Mustacchi #define NVM_COMPAT 0x0003 1017*75eba5b6SRobert Mustacchi #define NVM_ID_LED_SETTINGS 0x0004 1018*75eba5b6SRobert Mustacchi #define NVM_VERSION 0x0005 1019*75eba5b6SRobert Mustacchi #define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */ 1020*75eba5b6SRobert Mustacchi #define NVM_PHY_CLASS_WORD 0x0007 1021*75eba5b6SRobert Mustacchi #define E1000_I210_NVM_FW_MODULE_PTR 0x0010 1022*75eba5b6SRobert Mustacchi #define E1000_I350_NVM_FW_MODULE_PTR 0x0051 1023*75eba5b6SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1 0x0019 1024*75eba5b6SRobert Mustacchi #define NVM_MAC_ADDR 0x0000 1025*75eba5b6SRobert Mustacchi #define NVM_SUB_DEV_ID 0x000B 1026*75eba5b6SRobert Mustacchi #define NVM_SUB_VEN_ID 0x000C 1027*75eba5b6SRobert Mustacchi #define NVM_DEV_ID 0x000D 1028*75eba5b6SRobert Mustacchi #define NVM_VEN_ID 0x000E 1029*75eba5b6SRobert Mustacchi #define NVM_INIT_CTRL_2 0x000F 1030*75eba5b6SRobert Mustacchi #define NVM_INIT_CTRL_4 0x0013 1031*75eba5b6SRobert Mustacchi #define NVM_LED_1_CFG 0x001C 1032*75eba5b6SRobert Mustacchi #define NVM_LED_0_2_CFG 0x001F 1033*75eba5b6SRobert Mustacchi 1034*75eba5b6SRobert Mustacchi #define NVM_COMPAT_VALID_CSUM 0x0001 1035*75eba5b6SRobert Mustacchi #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 1036*75eba5b6SRobert Mustacchi 1037*75eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL2_REG 0x000F 1038*75eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_B 0x0014 1039*75eba5b6SRobert Mustacchi #define NVM_INIT_3GIO_3 0x001A 1040*75eba5b6SRobert Mustacchi #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 1041*75eba5b6SRobert Mustacchi #define NVM_INIT_CONTROL3_PORT_A 0x0024 1042*75eba5b6SRobert Mustacchi #define NVM_CFG 0x0012 1043*75eba5b6SRobert Mustacchi #define NVM_ALT_MAC_ADDR_PTR 0x0037 1044*75eba5b6SRobert Mustacchi #define NVM_CHECKSUM_REG 0x003F 1045*75eba5b6SRobert Mustacchi #define NVM_COMPATIBILITY_REG_3 0x0003 1046*75eba5b6SRobert Mustacchi #define NVM_COMPATIBILITY_BIT_MASK 0x8000 1047*75eba5b6SRobert Mustacchi 1048*75eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 1049*75eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 1050*75eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 1051*75eba5b6SRobert Mustacchi #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 1052*75eba5b6SRobert Mustacchi 1053*75eba5b6SRobert Mustacchi #define NVM_82580_LAN_FUNC_OFFSET(a) ((a) ? (0x40 + (0x40 * (a))) : 0) 1054*75eba5b6SRobert Mustacchi 1055*75eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x24 of the NVM */ 1056*75eba5b6SRobert Mustacchi #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 1057*75eba5b6SRobert Mustacchi #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed extrnl */ 1058*75eba5b6SRobert Mustacchi /* Offset of Link Mode bits for 82575/82576 */ 1059*75eba5b6SRobert Mustacchi #define NVM_WORD24_LNK_MODE_OFFSET 8 1060*75eba5b6SRobert Mustacchi /* Offset of Link Mode bits for 82580 up */ 1061*75eba5b6SRobert Mustacchi #define NVM_WORD24_82580_LNK_MODE_OFFSET 4 1062*75eba5b6SRobert Mustacchi 1063*75eba5b6SRobert Mustacchi 1064*75eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x0f of the NVM */ 1065*75eba5b6SRobert Mustacchi #define NVM_WORD0F_PAUSE_MASK 0x3000 1066*75eba5b6SRobert Mustacchi #define NVM_WORD0F_PAUSE 0x1000 1067*75eba5b6SRobert Mustacchi #define NVM_WORD0F_ASM_DIR 0x2000 1068*75eba5b6SRobert Mustacchi #define NVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 1069*75eba5b6SRobert Mustacchi 1070*75eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x1a of the NVM */ 1071*75eba5b6SRobert Mustacchi #define NVM_WORD1A_ASPM_MASK 0x000C 1072*75eba5b6SRobert Mustacchi 1073*75eba5b6SRobert Mustacchi /* Mask bits for fields in Word 0x03 of the EEPROM */ 1074*75eba5b6SRobert Mustacchi #define NVM_COMPAT_LOM 0x0800 1075*75eba5b6SRobert Mustacchi 1076*75eba5b6SRobert Mustacchi /* length of string needed to store PBA number */ 1077*75eba5b6SRobert Mustacchi #define E1000_PBANUM_LENGTH 11 1078*75eba5b6SRobert Mustacchi 1079*75eba5b6SRobert Mustacchi /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 1080*75eba5b6SRobert Mustacchi #define NVM_SUM 0xBABA 1081*75eba5b6SRobert Mustacchi 1082*75eba5b6SRobert Mustacchi /* OEM NVM Offsets */ 1083*75eba5b6SRobert Mustacchi #define NVM_OEM_OFFSET_0 6 1084*75eba5b6SRobert Mustacchi #define NVM_OEM_OFFSET_1 7 1085*75eba5b6SRobert Mustacchi 1086*75eba5b6SRobert Mustacchi /* PBA (printed board assembly) number words */ 1087*75eba5b6SRobert Mustacchi #define NVM_PBA_OFFSET_0 8 1088*75eba5b6SRobert Mustacchi #define NVM_PBA_OFFSET_1 9 1089*75eba5b6SRobert Mustacchi #define NVM_PBA_PTR_GUARD 0xFAFA 1090*75eba5b6SRobert Mustacchi #define NVM_RESERVED_WORD 0xFFFF 1091*75eba5b6SRobert Mustacchi #define NVM_PHY_CLASS_A 0x8000 1092*75eba5b6SRobert Mustacchi #define NVM_SERDES_AMPLITUDE_MASK 0x000F 1093*75eba5b6SRobert Mustacchi #define NVM_SIZE_MASK 0x1C00 1094*75eba5b6SRobert Mustacchi #define NVM_SIZE_SHIFT 10 1095*75eba5b6SRobert Mustacchi #define NVM_WORD_SIZE_BASE_SHIFT 6 1096*75eba5b6SRobert Mustacchi #define NVM_SWDPIO_EXT_SHIFT 4 1097*75eba5b6SRobert Mustacchi 1098*75eba5b6SRobert Mustacchi /* NVM Commands - Microwire */ 1099*75eba5b6SRobert Mustacchi #define NVM_READ_OPCODE_MICROWIRE 0x6 /* NVM read opcode */ 1100*75eba5b6SRobert Mustacchi #define NVM_WRITE_OPCODE_MICROWIRE 0x5 /* NVM write opcode */ 1101*75eba5b6SRobert Mustacchi #define NVM_ERASE_OPCODE_MICROWIRE 0x7 /* NVM erase opcode */ 1102*75eba5b6SRobert Mustacchi #define NVM_EWEN_OPCODE_MICROWIRE 0x13 /* NVM erase/write enable */ 1103*75eba5b6SRobert Mustacchi #define NVM_EWDS_OPCODE_MICROWIRE 0x10 /* NVM erase/write disable */ 1104*75eba5b6SRobert Mustacchi 1105*75eba5b6SRobert Mustacchi /* NVM Commands - SPI */ 1106*75eba5b6SRobert Mustacchi #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 1107*75eba5b6SRobert Mustacchi #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 1108*75eba5b6SRobert Mustacchi #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 1109*75eba5b6SRobert Mustacchi #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 1110*75eba5b6SRobert Mustacchi #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 1111*75eba5b6SRobert Mustacchi #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 1112*75eba5b6SRobert Mustacchi 1113*75eba5b6SRobert Mustacchi /* SPI NVM Status Register */ 1114*75eba5b6SRobert Mustacchi #define NVM_STATUS_RDY_SPI 0x01 1115*75eba5b6SRobert Mustacchi 1116*75eba5b6SRobert Mustacchi /* Word definitions for ID LED Settings */ 1117*75eba5b6SRobert Mustacchi #define ID_LED_RESERVED_0000 0x0000 1118*75eba5b6SRobert Mustacchi #define ID_LED_RESERVED_FFFF 0xFFFF 1119*75eba5b6SRobert Mustacchi #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 1120*75eba5b6SRobert Mustacchi (ID_LED_OFF1_OFF2 << 8) | \ 1121*75eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2 << 4) | \ 1122*75eba5b6SRobert Mustacchi (ID_LED_DEF1_DEF2)) 1123*75eba5b6SRobert Mustacchi #define ID_LED_DEF1_DEF2 0x1 1124*75eba5b6SRobert Mustacchi #define ID_LED_DEF1_ON2 0x2 1125*75eba5b6SRobert Mustacchi #define ID_LED_DEF1_OFF2 0x3 1126*75eba5b6SRobert Mustacchi #define ID_LED_ON1_DEF2 0x4 1127*75eba5b6SRobert Mustacchi #define ID_LED_ON1_ON2 0x5 1128*75eba5b6SRobert Mustacchi #define ID_LED_ON1_OFF2 0x6 1129*75eba5b6SRobert Mustacchi #define ID_LED_OFF1_DEF2 0x7 1130*75eba5b6SRobert Mustacchi #define ID_LED_OFF1_ON2 0x8 1131*75eba5b6SRobert Mustacchi #define ID_LED_OFF1_OFF2 0x9 1132*75eba5b6SRobert Mustacchi 1133*75eba5b6SRobert Mustacchi #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 1134*75eba5b6SRobert Mustacchi #define IGP_ACTIVITY_LED_ENABLE 0x0300 1135*75eba5b6SRobert Mustacchi #define IGP_LED3_MODE 0x07000000 1136*75eba5b6SRobert Mustacchi 1137*75eba5b6SRobert Mustacchi /* PCI/PCI-X/PCI-EX Config space */ 1138*75eba5b6SRobert Mustacchi #define PCIX_COMMAND_REGISTER 0xE6 1139*75eba5b6SRobert Mustacchi #define PCIX_STATUS_REGISTER_LO 0xE8 1140*75eba5b6SRobert Mustacchi #define PCIX_STATUS_REGISTER_HI 0xEA 1141*75eba5b6SRobert Mustacchi #define PCI_HEADER_TYPE_REGISTER 0x0E 1142*75eba5b6SRobert Mustacchi #define PCIE_LINK_STATUS 0x12 1143*75eba5b6SRobert Mustacchi #define PCIE_DEVICE_CONTROL2 0x28 1144*75eba5b6SRobert Mustacchi 1145*75eba5b6SRobert Mustacchi #define PCIX_COMMAND_MMRBC_MASK 0x000C 1146*75eba5b6SRobert Mustacchi #define PCIX_COMMAND_MMRBC_SHIFT 0x2 1147*75eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 1148*75eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 1149*75eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_4K 0x3 1150*75eba5b6SRobert Mustacchi #define PCIX_STATUS_HI_MMRBC_2K 0x2 1151*75eba5b6SRobert Mustacchi #define PCIX_STATUS_LO_FUNC_MASK 0x7 1152*75eba5b6SRobert Mustacchi #define PCI_HEADER_TYPE_MULTIFUNC 0x80 1153*75eba5b6SRobert Mustacchi #define PCIE_LINK_WIDTH_MASK 0x3F0 1154*75eba5b6SRobert Mustacchi #define PCIE_LINK_WIDTH_SHIFT 4 1155*75eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_MASK 0x0F 1156*75eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_2500 0x01 1157*75eba5b6SRobert Mustacchi #define PCIE_LINK_SPEED_5000 0x02 1158*75eba5b6SRobert Mustacchi #define PCIE_DEVICE_CONTROL2_16ms 0x0005 1159*75eba5b6SRobert Mustacchi 1160*75eba5b6SRobert Mustacchi #ifndef ETH_ADDR_LEN 1161*75eba5b6SRobert Mustacchi #define ETH_ADDR_LEN 6 1162*75eba5b6SRobert Mustacchi #endif 1163*75eba5b6SRobert Mustacchi 1164*75eba5b6SRobert Mustacchi #define PHY_REVISION_MASK 0xFFFFFFF0 1165*75eba5b6SRobert Mustacchi #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 1166*75eba5b6SRobert Mustacchi #define MAX_PHY_MULTI_PAGE_REG 0xF 1167*75eba5b6SRobert Mustacchi 1168*75eba5b6SRobert Mustacchi /* Bit definitions for valid PHY IDs. 1169*75eba5b6SRobert Mustacchi * I = Integrated 1170*75eba5b6SRobert Mustacchi * E = External 1171*75eba5b6SRobert Mustacchi */ 1172*75eba5b6SRobert Mustacchi #define M88E1000_E_PHY_ID 0x01410C50 1173*75eba5b6SRobert Mustacchi #define M88E1000_I_PHY_ID 0x01410C30 1174*75eba5b6SRobert Mustacchi #define M88E1011_I_PHY_ID 0x01410C20 1175*75eba5b6SRobert Mustacchi #define IGP01E1000_I_PHY_ID 0x02A80380 1176*75eba5b6SRobert Mustacchi #define M88E1111_I_PHY_ID 0x01410CC0 1177*75eba5b6SRobert Mustacchi #define M88E1112_E_PHY_ID 0x01410C90 1178*75eba5b6SRobert Mustacchi #define I347AT4_E_PHY_ID 0x01410DC0 1179*75eba5b6SRobert Mustacchi #define M88E1340M_E_PHY_ID 0x01410DF0 1180*75eba5b6SRobert Mustacchi #define GG82563_E_PHY_ID 0x01410CA0 1181*75eba5b6SRobert Mustacchi #define IGP03E1000_E_PHY_ID 0x02A80390 1182*75eba5b6SRobert Mustacchi #define IFE_E_PHY_ID 0x02A80330 1183*75eba5b6SRobert Mustacchi #define IFE_PLUS_E_PHY_ID 0x02A80320 1184*75eba5b6SRobert Mustacchi #define IFE_C_E_PHY_ID 0x02A80310 1185*75eba5b6SRobert Mustacchi #define BME1000_E_PHY_ID 0x01410CB0 1186*75eba5b6SRobert Mustacchi #define BME1000_E_PHY_ID_R2 0x01410CB1 1187*75eba5b6SRobert Mustacchi #define I82577_E_PHY_ID 0x01540050 1188*75eba5b6SRobert Mustacchi #define I82578_E_PHY_ID 0x004DD040 1189*75eba5b6SRobert Mustacchi #define I82579_E_PHY_ID 0x01540090 1190*75eba5b6SRobert Mustacchi #define I217_E_PHY_ID 0x015400A0 1191*75eba5b6SRobert Mustacchi #define I82580_I_PHY_ID 0x015403A0 1192*75eba5b6SRobert Mustacchi #define I350_I_PHY_ID 0x015403B0 1193*75eba5b6SRobert Mustacchi #define I210_I_PHY_ID 0x01410C00 1194*75eba5b6SRobert Mustacchi #define IGP04E1000_E_PHY_ID 0x02A80391 1195*75eba5b6SRobert Mustacchi #define M88_VENDOR 0x0141 1196*75eba5b6SRobert Mustacchi 1197*75eba5b6SRobert Mustacchi /* M88E1000 Specific Registers */ 1198*75eba5b6SRobert Mustacchi #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Reg */ 1199*75eba5b6SRobert Mustacchi #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Reg */ 1200*75eba5b6SRobert Mustacchi #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Cntrl */ 1201*75eba5b6SRobert Mustacchi #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 1202*75eba5b6SRobert Mustacchi 1203*75eba5b6SRobert Mustacchi #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 1204*75eba5b6SRobert Mustacchi #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */ 1205*75eba5b6SRobert Mustacchi #define M88E1000_PHY_GEN_CONTROL 0x1E /* meaning depends on reg 29 */ 1206*75eba5b6SRobert Mustacchi #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 1207*75eba5b6SRobert Mustacchi #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 1208*75eba5b6SRobert Mustacchi 1209*75eba5b6SRobert Mustacchi /* M88E1000 PHY Specific Control Register */ 1210*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */ 1211*75eba5b6SRobert Mustacchi /* MDI Crossover Mode bits 6:5 Manual MDI configuration */ 1212*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 1213*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 1214*75eba5b6SRobert Mustacchi /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 1215*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_AUTO_X_1000T 0x0040 1216*75eba5b6SRobert Mustacchi /* Auto crossover enabled all speeds */ 1217*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_AUTO_X_MODE 0x0060 1218*75eba5b6SRobert Mustacchi #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Tx */ 1219*75eba5b6SRobert Mustacchi 1220*75eba5b6SRobert Mustacchi /* M88E1000 PHY Specific Status Register */ 1221*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 1222*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 1223*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 1224*75eba5b6SRobert Mustacchi /* 0 = <50M 1225*75eba5b6SRobert Mustacchi * 1 = 50-80M 1226*75eba5b6SRobert Mustacchi * 2 = 80-110M 1227*75eba5b6SRobert Mustacchi * 3 = 110-140M 1228*75eba5b6SRobert Mustacchi * 4 = >140M 1229*75eba5b6SRobert Mustacchi */ 1230*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_CABLE_LENGTH 0x0380 1231*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 1232*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 1233*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 1234*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 1235*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 1236*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 1237*75eba5b6SRobert Mustacchi 1238*75eba5b6SRobert Mustacchi #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 1239*75eba5b6SRobert Mustacchi 1240*75eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 1241*75eba5b6SRobert Mustacchi * are the master 1242*75eba5b6SRobert Mustacchi */ 1243*75eba5b6SRobert Mustacchi #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 1244*75eba5b6SRobert Mustacchi #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 1245*75eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 1246*75eba5b6SRobert Mustacchi * are the slave 1247*75eba5b6SRobert Mustacchi */ 1248*75eba5b6SRobert Mustacchi #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 1249*75eba5b6SRobert Mustacchi #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 1250*75eba5b6SRobert Mustacchi #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 1251*75eba5b6SRobert Mustacchi 1252*75eba5b6SRobert Mustacchi /* Intel I347AT4 Registers */ 1253*75eba5b6SRobert Mustacchi #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 1254*75eba5b6SRobert Mustacchi #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 1255*75eba5b6SRobert Mustacchi #define I347AT4_PAGE_SELECT 0x16 1256*75eba5b6SRobert Mustacchi 1257*75eba5b6SRobert Mustacchi /* I347AT4 Extended PHY Specific Control Register */ 1258*75eba5b6SRobert Mustacchi 1259*75eba5b6SRobert Mustacchi /* Number of times we will attempt to autonegotiate before downshifting if we 1260*75eba5b6SRobert Mustacchi * are the master 1261*75eba5b6SRobert Mustacchi */ 1262*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 1263*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 1264*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 1265*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 1266*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 1267*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 1268*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 1269*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 1270*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 1271*75eba5b6SRobert Mustacchi #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 1272*75eba5b6SRobert Mustacchi 1273*75eba5b6SRobert Mustacchi /* I347AT4 PHY Cable Diagnostics Control */ 1274*75eba5b6SRobert Mustacchi #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 1275*75eba5b6SRobert Mustacchi 1276*75eba5b6SRobert Mustacchi /* M88E1112 only registers */ 1277*75eba5b6SRobert Mustacchi #define M88E1112_VCT_DSP_DISTANCE 0x001A 1278*75eba5b6SRobert Mustacchi 1279*75eba5b6SRobert Mustacchi /* M88EC018 Rev 2 specific DownShift settings */ 1280*75eba5b6SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 1281*75eba5b6SRobert Mustacchi #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 1282*75eba5b6SRobert Mustacchi 1283*75eba5b6SRobert Mustacchi #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 1284*75eba5b6SRobert Mustacchi #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 1285*75eba5b6SRobert Mustacchi 1286*75eba5b6SRobert Mustacchi /* BME1000 PHY Specific Control Register */ 1287*75eba5b6SRobert Mustacchi #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 1288*75eba5b6SRobert Mustacchi 1289*75eba5b6SRobert Mustacchi /* Bits... 1290*75eba5b6SRobert Mustacchi * 15-5: page 1291*75eba5b6SRobert Mustacchi * 4-0: register offset 1292*75eba5b6SRobert Mustacchi */ 1293*75eba5b6SRobert Mustacchi #define GG82563_PAGE_SHIFT 5 1294*75eba5b6SRobert Mustacchi #define GG82563_REG(page, reg) \ 1295*75eba5b6SRobert Mustacchi (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 1296*75eba5b6SRobert Mustacchi #define GG82563_MIN_ALT_REG 30 1297*75eba5b6SRobert Mustacchi 1298*75eba5b6SRobert Mustacchi /* GG82563 Specific Registers */ 1299*75eba5b6SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) /* PHY Spec Cntrl */ 1300*75eba5b6SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */ 1301*75eba5b6SRobert Mustacchi #define GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) /* PHY Spec Cntrl2 */ 1302*75eba5b6SRobert Mustacchi #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */ 1303*75eba5b6SRobert Mustacchi 1304*75eba5b6SRobert Mustacchi /* MAC Specific Control Register */ 1305*75eba5b6SRobert Mustacchi #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) 1306*75eba5b6SRobert Mustacchi 1307*75eba5b6SRobert Mustacchi #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */ 1308*75eba5b6SRobert Mustacchi 1309*75eba5b6SRobert Mustacchi /* Page 193 - Port Control Registers */ 1310*75eba5b6SRobert Mustacchi /* Kumeran Mode Control */ 1311*75eba5b6SRobert Mustacchi #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) 1312*75eba5b6SRobert Mustacchi #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Pwr Mgt Ctrl */ 1313*75eba5b6SRobert Mustacchi 1314*75eba5b6SRobert Mustacchi /* Page 194 - KMRN Registers */ 1315*75eba5b6SRobert Mustacchi #define GG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) /* Inband Ctrl */ 1316*75eba5b6SRobert Mustacchi 1317*75eba5b6SRobert Mustacchi /* MDI Control */ 1318*75eba5b6SRobert Mustacchi #define E1000_MDIC_REG_MASK 0x001F0000 1319*75eba5b6SRobert Mustacchi #define E1000_MDIC_REG_SHIFT 16 1320*75eba5b6SRobert Mustacchi #define E1000_MDIC_PHY_MASK 0x03E00000 1321*75eba5b6SRobert Mustacchi #define E1000_MDIC_PHY_SHIFT 21 1322*75eba5b6SRobert Mustacchi #define E1000_MDIC_OP_WRITE 0x04000000 1323*75eba5b6SRobert Mustacchi #define E1000_MDIC_OP_READ 0x08000000 1324*75eba5b6SRobert Mustacchi #define E1000_MDIC_READY 0x10000000 1325*75eba5b6SRobert Mustacchi #define E1000_MDIC_ERROR 0x40000000 1326*75eba5b6SRobert Mustacchi #define E1000_MDIC_DEST 0x80000000 1327*75eba5b6SRobert Mustacchi 1328*75eba5b6SRobert Mustacchi /* SerDes Control */ 1329*75eba5b6SRobert Mustacchi #define E1000_GEN_CTL_READY 0x80000000 1330*75eba5b6SRobert Mustacchi #define E1000_GEN_CTL_ADDRESS_SHIFT 8 1331*75eba5b6SRobert Mustacchi #define E1000_GEN_POLL_TIMEOUT 640 1332*75eba5b6SRobert Mustacchi 1333*75eba5b6SRobert Mustacchi /* LinkSec register fields */ 1334*75eba5b6SRobert Mustacchi #define E1000_LSECTXCAP_SUM_MASK 0x00FF0000 1335*75eba5b6SRobert Mustacchi #define E1000_LSECTXCAP_SUM_SHIFT 16 1336*75eba5b6SRobert Mustacchi #define E1000_LSECRXCAP_SUM_MASK 0x00FF0000 1337*75eba5b6SRobert Mustacchi #define E1000_LSECRXCAP_SUM_SHIFT 16 1338*75eba5b6SRobert Mustacchi 1339*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_EN_MASK 0x00000003 1340*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_DISABLE 0x0 1341*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AUTH 0x1 1342*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 1343*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_AISCI 0x00000020 1344*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 1345*75eba5b6SRobert Mustacchi #define E1000_LSECTXCTRL_RSV_MASK 0x000000D8 1346*75eba5b6SRobert Mustacchi 1347*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_EN_MASK 0x0000000C 1348*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_EN_SHIFT 2 1349*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_DISABLE 0x0 1350*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_CHECK 0x1 1351*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_STRICT 0x2 1352*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_DROP 0x3 1353*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_PLSH 0x00000040 1354*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_RP 0x00000080 1355*75eba5b6SRobert Mustacchi #define E1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 1356*75eba5b6SRobert Mustacchi 1357*75eba5b6SRobert Mustacchi /* Tx Rate-Scheduler Config fields */ 1358*75eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RS_ENA 0x80000000 1359*75eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1360*75eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_INT_SHIFT 14 1361*75eba5b6SRobert Mustacchi #define E1000_RTTBCNRC_RF_INT_MASK \ 1362*75eba5b6SRobert Mustacchi (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1363*75eba5b6SRobert Mustacchi 1364*75eba5b6SRobert Mustacchi /* DMA Coalescing register fields */ 1365*75eba5b6SRobert Mustacchi /* DMA Coalescing Watchdog Timer */ 1366*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMACWT_MASK 0x00003FFF 1367*75eba5b6SRobert Mustacchi /* DMA Coalescing Rx Threshold */ 1368*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 1369*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMACTHR_SHIFT 16 1370*75eba5b6SRobert Mustacchi /* Lx when no PCIe transactions */ 1371*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_LX_MASK 0x30000000 1372*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_LX_SHIFT 28 1373*75eba5b6SRobert Mustacchi #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 1374*75eba5b6SRobert Mustacchi /* DMA Coalescing BMC-to-OS Watchdog Enable */ 1375*75eba5b6SRobert Mustacchi #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 1376*75eba5b6SRobert Mustacchi 1377*75eba5b6SRobert Mustacchi /* DMA Coalescing Transmit Threshold */ 1378*75eba5b6SRobert Mustacchi #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF 1379*75eba5b6SRobert Mustacchi 1380*75eba5b6SRobert Mustacchi #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 1381*75eba5b6SRobert Mustacchi 1382*75eba5b6SRobert Mustacchi /* Rx Traffic Rate Threshold */ 1383*75eba5b6SRobert Mustacchi #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF 1384*75eba5b6SRobert Mustacchi /* Rx packet rate in current window */ 1385*75eba5b6SRobert Mustacchi #define E1000_DMCRTRH_LRPRCW 0x80000000 1386*75eba5b6SRobert Mustacchi 1387*75eba5b6SRobert Mustacchi /* DMA Coal Rx Traffic Current Count */ 1388*75eba5b6SRobert Mustacchi #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF 1389*75eba5b6SRobert Mustacchi 1390*75eba5b6SRobert Mustacchi /* Flow ctrl Rx Threshold High val */ 1391*75eba5b6SRobert Mustacchi #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 1392*75eba5b6SRobert Mustacchi #define E1000_FCRTC_RTH_COAL_SHIFT 4 1393*75eba5b6SRobert Mustacchi /* Lx power decision based on DMA coal */ 1394*75eba5b6SRobert Mustacchi #define E1000_PCIEMISC_LX_DECISION 0x00000080 1395*75eba5b6SRobert Mustacchi 1396*75eba5b6SRobert Mustacchi #define E1000_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */ 1397*75eba5b6SRobert Mustacchi #define E1000_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */ 1398*75eba5b6SRobert Mustacchi #define E1000_TXPB0S_SIZE_I210_MASK 0x0000003F /* Tx packet buffer 0 size */ 1399*75eba5b6SRobert Mustacchi #define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */ 1400*75eba5b6SRobert Mustacchi #define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */ 1401*75eba5b6SRobert Mustacchi 1402*75eba5b6SRobert Mustacchi /* Proxy Filter Control */ 1403*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */ 1404*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_EX 0x00000004 /* Directed exact proxy */ 1405*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_MC 0x00000008 /* Directed MC Proxy */ 1406*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_BC 0x00000010 /* Broadcast Proxy Enable */ 1407*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */ 1408*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */ 1409*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */ 1410*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 1411*75eba5b6SRobert Mustacchi #define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */ 1412*75eba5b6SRobert Mustacchi /* Proxy Status */ 1413*75eba5b6SRobert Mustacchi #define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */ 1414*75eba5b6SRobert Mustacchi 1415*75eba5b6SRobert Mustacchi /* Firmware Status */ 1416*75eba5b6SRobert Mustacchi #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */ 1417*75eba5b6SRobert Mustacchi /* VF Control */ 1418*75eba5b6SRobert Mustacchi #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */ 1419*75eba5b6SRobert Mustacchi 1420*75eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */ 1421*75eba5b6SRobert Mustacchi /* Lan ID bit field offset in status register */ 1422*75eba5b6SRobert Mustacchi #define E1000_STATUS_LAN_ID_OFFSET 2 1423*75eba5b6SRobert Mustacchi #define E1000_VFTA_ENTRIES 128 1424*75eba5b6SRobert Mustacchi #endif /* _E1000_DEFINES_H_ */ 1425