1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * This file is part of the Chelsio T4 support code.
14  *
15  * Copyright (C) 2011-2013 Chelsio Communications.  All rights reserved.
16  *
17  * This program is distributed in the hope that it will be useful, but WITHOUT
18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20  * release for licensing terms and conditions.
21  */
22 
23 #ifndef __CXGBE_ADAPTER_H
24 #define	__CXGBE_ADAPTER_H
25 
26 #include <sys/ddi.h>
27 #include <sys/mac_provider.h>
28 #include <sys/ethernet.h>
29 #include <sys/queue.h>
30 #include <sys/containerof.h>
31 #include <sys/ddi_ufm.h>
32 
33 #include "offload.h"
34 #include "firmware/t4fw_interface.h"
35 #include "shared.h"
36 
37 struct adapter;
38 typedef struct adapter adapter_t;
39 
40 enum {
41 	FW_IQ_QSIZE = 256,
42 	FW_IQ_ESIZE = 64,	/* At least 64 mandated by the firmware spec */
43 
44 	RX_IQ_QSIZE = 1024,
45 	RX_IQ_ESIZE = 64,	/* At least 64 so CPL_RX_PKT will fit */
46 
47 	EQ_ESIZE = 64,		/* All egres queues use this entry size */
48 
49 	RX_FL_ESIZE = 64,	/* 8 64bit addresses */
50 
51 	FL_BUF_SIZES = 4,
52 
53 	CTRL_EQ_QSIZE = 128,
54 
55 	TX_EQ_QSIZE = 1024,
56 	TX_SGL_SEGS = 36,
57 	TX_WR_FLITS = SGE_MAX_WR_LEN / 8
58 };
59 
60 enum {
61 	/* adapter flags */
62 	FULL_INIT_DONE	= (1 << 0),
63 	FW_OK		= (1 << 1),
64 	INTR_FWD	= (1 << 2),
65 	INTR_ALLOCATED	= (1 << 3),
66 	MASTER_PF	= (1 << 4),
67 
68 	CXGBE_BUSY	= (1 << 9),
69 
70 	/* port flags */
71 	DOOMED		= (1 << 0),
72 	PORT_INIT_DONE	= (1 << 1),
73 };
74 
75 enum {
76 	/* Features */
77 	CXGBE_HW_LSO	= (1 << 0),
78 	CXGBE_HW_CSUM	= (1 << 1),
79 };
80 
81 enum {
82 	UDBS_SEG_SHIFT	= 7,	/* log2(UDBS_SEG_SIZE) */
83 	UDBS_DB_OFFSET	= 8,	/* offset of the 4B doorbell in a segment */
84 	UDBS_WR_OFFSET	= 64,	/* offset of the work request in a segment */
85 };
86 
87 #define	IS_DOOMED(pi)	(pi->flags & DOOMED)
88 #define	SET_DOOMED(pi)	do { pi->flags |= DOOMED; } while (0)
89 #define	IS_BUSY(sc)	(sc->flags & CXGBE_BUSY)
90 #define	SET_BUSY(sc)	do { sc->flags |= CXGBE_BUSY; } while (0)
91 #define	CLR_BUSY(sc)	do { sc->flags &= ~CXGBE_BUSY; } while (0)
92 
93 struct port_info {
94 	PORT_INFO_HDR;
95 
96 	kmutex_t lock;
97 	struct adapter *adapter;
98 
99 #ifdef TCP_OFFLOAD_ENABLE
100 	void *tdev;
101 #endif
102 
103 	unsigned int flags;
104 
105 	uint16_t viid;
106 	int16_t  xact_addr_filt; /* index of exact MAC address filter */
107 	uint16_t rss_size;	/* size of VI's RSS table slice */
108 	uint16_t ntxq;		/* # of tx queues */
109 	uint16_t first_txq;	/* index of first tx queue */
110 	uint16_t nrxq;		/* # of rx queues */
111 	uint16_t first_rxq;	/* index of first rx queue */
112 #ifdef TCP_OFFLOAD_ENABLE
113 	uint16_t nofldtxq;		/* # of offload tx queues */
114 	uint16_t first_ofld_txq;	/* index of first offload tx queue */
115 	uint16_t nofldrxq;		/* # of offload rx queues */
116 	uint16_t first_ofld_rxq;	/* index of first offload rx queue */
117 #endif
118 	uint8_t  lport;		/* associated offload logical port */
119 	int8_t   mdio_addr;
120 	uint8_t  port_type;
121 	uint8_t  mod_type;
122 	uint8_t  port_id;
123 	uint8_t  tx_chan;
124 	uint8_t  rx_chan;
125 	uint8_t  rx_cchan;
126 	uint8_t instance; /* Associated adapter instance */
127 	uint8_t child_inst; /* Associated child instance */
128 	uint8_t	tmr_idx;
129 	int8_t	pktc_idx;
130 	struct link_config link_cfg;
131 	struct port_stats stats;
132 	uint32_t features;
133 	uint8_t macaddr_cnt;
134 	u8 rss_mode;
135 	u16 viid_mirror;
136 	kstat_t *ksp_config;
137 	kstat_t *ksp_info;
138 
139 	u8 vivld;
140 	u8 vin;
141 	u8 smt_idx;
142 
143 	u8 vivld_mirror;
144 	u8 vin_mirror;
145 	u8 smt_idx_mirror;
146 };
147 
148 struct fl_sdesc {
149 	struct rxbuf *rxb;
150 };
151 
152 struct tx_desc {
153 	__be64 flit[8];
154 };
155 
156 /* DMA maps used for tx */
157 struct tx_maps {
158 	ddi_dma_handle_t *map;
159 	uint32_t map_total;	/* # of DMA maps */
160 	uint32_t map_pidx;	/* next map to be used */
161 	uint32_t map_cidx;	/* reclaimed up to this index */
162 	uint32_t map_avail;	/* # of available maps */
163 };
164 
165 struct tx_sdesc {
166 	mblk_t *m;
167 	uint32_t txb_used;	/* # of bytes of tx copy buffer used */
168 	uint16_t hdls_used;	/* # of dma handles used */
169 	uint16_t desc_used;	/* # of hardware descriptors used */
170 };
171 
172 enum {
173 	/* iq flags */
174 	IQ_ALLOCATED	= (1 << 0),	/* firmware resources allocated */
175 	IQ_INTR		= (1 << 1),	/* iq takes direct interrupt */
176 	IQ_HAS_FL	= (1 << 2),	/* iq has fl */
177 
178 	/* iq state */
179 	IQS_DISABLED	= 0,
180 	IQS_BUSY	= 1,
181 	IQS_IDLE	= 2,
182 };
183 
184 /*
185  * Ingress Queue: T4 is producer, driver is consumer.
186  */
187 struct sge_iq {
188 	unsigned int flags;
189 	ddi_dma_handle_t dhdl;
190 	ddi_acc_handle_t ahdl;
191 
192 	volatile uint_t state;
193 	__be64 *desc;		/* KVA of descriptor ring */
194 	uint64_t ba;		/* bus address of descriptor ring */
195 	const __be64 *cdesc;	/* current descriptor */
196 	struct adapter *adapter; /* associated  adapter */
197 	uint8_t  gen;		/* generation bit */
198 	uint8_t  intr_params;	/* interrupt holdoff parameters */
199 	int8_t   intr_pktc_idx;	/* packet count threshold index */
200 	uint8_t  intr_next;	/* holdoff for next interrupt */
201 	uint8_t  esize;		/* size (bytes) of each entry in the queue */
202 	uint16_t qsize;		/* size (# of entries) of the queue */
203 	uint16_t cidx;		/* consumer index */
204 	uint16_t pending;	/* # of descs processed since last doorbell */
205 	uint16_t cntxt_id;	/* SGE context id  for the iq */
206 	uint16_t abs_id;	/* absolute SGE id for the iq */
207 	kmutex_t lock;		/* Rx access lock */
208 	uint8_t polling;
209 
210 	STAILQ_ENTRY(sge_iq) link;
211 };
212 
213 enum {
214 	EQ_CTRL		= 1,
215 	EQ_ETH		= 2,
216 #ifdef TCP_OFFLOAD_ENABLE
217 	EQ_OFLD		= 3,
218 #endif
219 
220 	/* eq flags */
221 	EQ_TYPEMASK	= 7,		/* 3 lsbits hold the type */
222 	EQ_ALLOCATED	= (1 << 3),	/* firmware resources allocated */
223 	EQ_DOOMED	= (1 << 4),	/* about to be destroyed */
224 	EQ_CRFLUSHED	= (1 << 5),	/* expecting an update from SGE */
225 	EQ_STALLED	= (1 << 6),	/* out of hw descriptors or dmamaps */
226 	EQ_MTX		= (1 << 7),	/* mutex has been initialized */
227 	EQ_STARTED	= (1 << 8),	/* started */
228 };
229 
230 /* Listed in order of preference.  Update t4_sysctls too if you change these */
231 enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8};
232 
233 /*
234  * Egress Queue: driver is producer, T4 is consumer.
235  *
236  * Note: A free list is an egress queue (driver produces the buffers and T4
237  * consumes them) but it's special enough to have its own struct (see sge_fl).
238  */
239 struct sge_eq {
240 	ddi_dma_handle_t desc_dhdl;
241 	ddi_acc_handle_t desc_ahdl;
242 	unsigned int flags;
243 	kmutex_t lock;
244 
245 	struct tx_desc *desc;	/* KVA of descriptor ring */
246 	uint64_t ba;		/* bus address of descriptor ring */
247 	struct sge_qstat *spg;	/* status page, for convenience */
248 	int doorbells;
249 	volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
250 	u_int udb_qid;		/* relative qid within the doorbell page */
251 	uint16_t cap;		/* max # of desc, for convenience */
252 	uint16_t avail;		/* available descriptors, for convenience */
253 	uint16_t qsize;		/* size (# of entries) of the queue */
254 	uint16_t cidx;		/* consumer idx (desc idx) */
255 	uint16_t pidx;		/* producer idx (desc idx) */
256 	uint16_t pending;	/* # of descriptors used since last doorbell */
257 	uint16_t iqid;		/* iq that gets egr_update for the eq */
258 	uint8_t tx_chan;	/* tx channel used by the eq */
259 	uint32_t cntxt_id;	/* SGE context id for the eq */
260 };
261 
262 enum {
263 	/* fl flags */
264 	FL_MTX		= (1 << 0),	/* mutex has been initialized */
265 	FL_STARVING	= (1 << 1),	/* on the list of starving fl's */
266 	FL_DOOMED	= (1 << 2),	/* about to be destroyed */
267 };
268 
269 #define	FL_RUNNING_LOW(fl)	(fl->cap - fl->needed <= fl->lowat)
270 #define	FL_NOT_RUNNING_LOW(fl)	(fl->cap - fl->needed >= 2 * fl->lowat)
271 
272 struct sge_fl {
273 	unsigned int flags;
274 	kmutex_t lock;
275 	ddi_dma_handle_t dhdl;
276 	ddi_acc_handle_t ahdl;
277 
278 	__be64 *desc;		/* KVA of descriptor ring, ptr to addresses */
279 	uint64_t ba;		/* bus address of descriptor ring */
280 	struct fl_sdesc *sdesc;	/* KVA of software descriptor ring */
281 	uint32_t cap;		/* max # of buffers, for convenience */
282 	uint16_t qsize;		/* size (# of entries) of the queue */
283 	uint16_t cntxt_id;	/* SGE context id for the freelist */
284 	uint32_t cidx;		/* consumer idx (buffer idx, NOT hw desc idx) */
285 	uint32_t pidx;		/* producer idx (buffer idx, NOT hw desc idx) */
286 	uint32_t needed;	/* # of buffers needed to fill up fl. */
287 	uint32_t lowat;		/* # of buffers <= this means fl needs help */
288 	uint32_t pending;	/* # of bufs allocated since last doorbell */
289 	uint32_t offset;	/* current packet within the larger buffer */
290 	uint16_t copy_threshold; /* anything this size or less is copied up */
291 
292 	uint64_t copied_up;	/* # of frames copied into mblk and handed up */
293 	uint64_t passed_up;	/* # of frames wrapped in mblk and handed up */
294 	uint64_t allocb_fail;	/* # of mblk allocation failures */
295 
296 	TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
297 };
298 
299 /* txq: SGE egress queue + miscellaneous items */
300 struct sge_txq {
301 	struct sge_eq eq;	/* MUST be first */
302 
303 	struct port_info *port;	/* the port this txq belongs to */
304 	struct tx_sdesc *sdesc;	/* KVA of software descriptor ring */
305 	mac_ring_handle_t ring_handle;
306 
307 	/* DMA handles used for tx */
308 	ddi_dma_handle_t *tx_dhdl;
309 	uint32_t tx_dhdl_total;	/* Total # of handles */
310 	uint32_t tx_dhdl_pidx;	/* next handle to be used */
311 	uint32_t tx_dhdl_cidx;	/* reclaimed up to this index */
312 	uint32_t tx_dhdl_avail;	/* # of available handles */
313 
314 	/* Copy buffers for tx */
315 	ddi_dma_handle_t txb_dhdl;
316 	ddi_acc_handle_t txb_ahdl;
317 	caddr_t txb_va;		/* KVA of copy buffers area */
318 	uint64_t txb_ba;	/* bus address of copy buffers area */
319 	uint32_t txb_size;	/* total size */
320 	uint32_t txb_next;	/* offset of next useable area in the buffer */
321 	uint32_t txb_avail;	/* # of bytes available */
322 	uint16_t copy_threshold; /* anything this size or less is copied up */
323 
324 	uint64_t txpkts;	/* # of ethernet packets */
325 	uint64_t txbytes;	/* # of ethernet bytes */
326 	kstat_t *ksp;
327 
328 	/* stats for common events first */
329 
330 	uint64_t txcsum;	/* # of times hardware assisted with checksum */
331 	uint64_t tso_wrs;	/* # of IPv4 TSO work requests */
332 	uint64_t imm_wrs;	/* # of work requests with immediate data */
333 	uint64_t sgl_wrs;	/* # of work requests with direct SGL */
334 	uint64_t txpkt_wrs;	/* # of txpkt work requests (not coalesced) */
335 	uint64_t txpkts_wrs;	/* # of coalesced tx work requests */
336 	uint64_t txpkts_pkts;	/* # of frames in coalesced tx work requests */
337 	uint64_t txb_used;	/* # of tx copy buffers used (64 byte each) */
338 	uint64_t hdl_used;	/* # of DMA handles used */
339 
340 	/* stats for not-that-common events */
341 
342 	uint32_t txb_full;	/* txb ran out of space */
343 	uint32_t dma_hdl_failed; /* couldn't obtain DMA handle */
344 	uint32_t dma_map_failed; /* couldn't obtain DMA mapping */
345 	uint32_t qfull;		/* out of hardware descriptors */
346 	uint32_t qflush;	/* # of SGE_EGR_UPDATE notifications for txq */
347 	uint32_t pullup_early;	/* # of pullups before starting frame's SGL */
348 	uint32_t pullup_late;	/* # of pullups while building frame's SGL */
349 	uint32_t pullup_failed;	/* # of failed pullups */
350 };
351 
352 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
353 struct sge_rxq {
354 	struct sge_iq iq;	/* MUST be first */
355 	struct sge_fl fl;
356 
357 	struct port_info *port;	/* the port this rxq belongs to */
358 	kstat_t *ksp;
359 
360 	mac_ring_handle_t ring_handle;
361 	uint64_t ring_gen_num;
362 
363 	/* stats for common events first */
364 
365 	uint64_t rxcsum;	/* # of times hardware assisted with checksum */
366 	uint64_t rxpkts;	/* # of ethernet packets */
367 	uint64_t rxbytes;	/* # of ethernet bytes */
368 
369 	/* stats for not-that-common events */
370 
371 	uint32_t nomem;		/* mblk allocation during rx failed */
372 };
373 
374 #ifdef TCP_OFFLOAD_ENABLE
375 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
376 struct sge_ofld_rxq {
377 	struct sge_iq iq;	/* MUST be first */
378 	struct sge_fl fl;
379 };
380 
381 /*
382  * wrq: SGE egress queue that is given prebuilt work requests.  Both the control
383  * and offload tx queues are of this type.
384  */
385 struct sge_wrq {
386 	struct sge_eq eq;	/* MUST be first */
387 
388 	struct adapter *adapter;
389 
390 	/* List of WRs held up due to lack of tx descriptors */
391 	struct mblk_pair wr_list;
392 
393 	/* stats for common events first */
394 
395 	uint64_t tx_wrs;	/* # of tx work requests */
396 
397 	/* stats for not-that-common events */
398 
399 	uint32_t no_desc;	/* out of hardware descriptors */
400 };
401 #endif
402 
403 struct sge {
404 	int fl_starve_threshold;
405 	int s_qpp;
406 
407 	int nrxq;	/* total rx queues (all ports and the rest) */
408 	int ntxq;	/* total tx queues (all ports and the rest) */
409 #ifdef TCP_OFFLOAD_ENABLE
410 	int nofldrxq;	/* total # of TOE rx queues */
411 	int nofldtxq;	/* total # of TOE tx queues */
412 #endif
413 	int niq;	/* total ingress queues */
414 	int neq;	/* total egress queues */
415 	int stat_len;	/* length of status page at ring end */
416 	int pktshift;	/* padding between CPL & packet data */
417 	int fl_align;	/* response queue message alignment */
418 
419 	struct sge_iq fwq;	/* Firmware event queue */
420 #ifdef TCP_OFFLOAD_ENABLE
421 	struct sge_wrq mgmtq;	/* Management queue (Control queue) */
422 #endif
423 	struct sge_txq *txq;	/* NIC tx queues */
424 	struct sge_rxq *rxq;	/* NIC rx queues */
425 #ifdef TCP_OFFLOAD_ENABLE
426 	struct sge_wrq *ctrlq;	/* Control queues */
427 	struct sge_wrq *ofld_txq;	/* TOE tx queues */
428 	struct sge_ofld_rxq *ofld_rxq;	/* TOE rx queues */
429 #endif
430 
431 	int iq_start; /* iq context id map start index */
432 	int eq_start; /* eq context id map start index */
433 	int iqmap_sz; /* size of iq context id map */
434 	int eqmap_sz; /* size of eq context id map */
435 	struct sge_iq **iqmap;	/* iq->cntxt_id to iq mapping */
436 	struct sge_eq **eqmap;	/* eq->cntxt_id to eq mapping */
437 
438 	/* Device access and DMA attributes for all the descriptor rings */
439 	ddi_device_acc_attr_t acc_attr_desc;
440 	ddi_dma_attr_t	dma_attr_desc;
441 
442 	/* Device access and DMA attributes for tx buffers */
443 	ddi_device_acc_attr_t acc_attr_tx;
444 	ddi_dma_attr_t	dma_attr_tx;
445 
446 	/* Device access and DMA attributes for rx buffers are in rxb_params */
447 	kmem_cache_t *rxbuf_cache;
448 	struct rxbuf_cache_params rxb_params;
449 };
450 
451 struct driver_properties {
452 	/* There is a driver.conf variable for each of these */
453 	int max_ntxq_10g;
454 	int max_nrxq_10g;
455 	int max_ntxq_1g;
456 	int max_nrxq_1g;
457 #ifdef TCP_OFFLOAD_ENABLE
458 	int max_nofldtxq_10g;
459 	int max_nofldrxq_10g;
460 	int max_nofldtxq_1g;
461 	int max_nofldrxq_1g;
462 #endif
463 	int intr_types;
464 	int tmr_idx_10g;
465 	int pktc_idx_10g;
466 	int tmr_idx_1g;
467 	int pktc_idx_1g;
468 	int qsize_txq;
469 	int qsize_rxq;
470 
471 	int timer_val[SGE_NTIMERS];
472 	int counter_val[SGE_NCOUNTERS];
473 
474 	int wc;
475 
476 	int multi_rings;
477 	int t4_fw_install;
478 };
479 
480 struct rss_header;
481 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
482     mblk_t *);
483 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
484 
485 struct t4_mbox_list {
486 	STAILQ_ENTRY(t4_mbox_list) link;
487 };
488 
489 struct adapter {
490 	SLIST_ENTRY(adapter) link;
491 	dev_info_t *dip;
492 	dev_t dev;
493 
494 	unsigned int pf;
495 	unsigned int mbox;
496 
497 	unsigned int vpd_busy;
498 	unsigned int vpd_flag;
499 
500 	u32 t4_bar0;
501 
502 	uint_t open;	/* character device is open */
503 
504 	/* PCI config space access handle */
505 	ddi_acc_handle_t pci_regh;
506 
507 	/* MMIO register access handle */
508 	ddi_acc_handle_t regh;
509 	caddr_t regp;
510 	/* BAR1 register access handle */
511 	ddi_acc_handle_t reg1h;
512 	caddr_t reg1p;
513 
514 	/* Interrupt information */
515 	int intr_type;
516 	int intr_count;
517 	int intr_cap;
518 	uint_t intr_pri;
519 	ddi_intr_handle_t *intr_handle;
520 
521 	struct driver_properties props;
522 	kstat_t *ksp;
523 	kstat_t *ksp_stat;
524 
525 	struct sge sge;
526 
527 	struct port_info *port[MAX_NPORTS];
528 	ddi_taskq_t *tq[NCHAN];
529 	uint8_t chan_map[NCHAN];
530 	uint32_t filter_mode;
531 
532 	struct l2t_data *l2t;	/* L2 table */
533 	struct tid_info tids;
534 
535 	int doorbells;
536 	int registered_device_map;
537 	int open_device_map;
538 	int flags;
539 
540 	unsigned int cfcsum;
541 	struct adapter_params params;
542 	struct t4_virt_res vres;
543 
544 #ifdef TCP_OFFLOAD_ENABLE
545 	struct uld_softc tom;
546 	struct tom_tunables tt;
547 #endif
548 
549 #ifdef TCP_OFFLOAD_ENABLE
550 	int offload_map;
551 #endif
552 	uint16_t linkcaps;
553 	uint16_t niccaps;
554 	uint16_t toecaps;
555 	uint16_t rdmacaps;
556 	uint16_t iscsicaps;
557 	uint16_t fcoecaps;
558 
559 	fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
560 	cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
561 
562 	kmutex_t lock;
563 	kcondvar_t cv;
564 
565 	/* Starving free lists */
566 	kmutex_t sfl_lock;	/* same cache-line as sc_lock? but that's ok */
567 	TAILQ_HEAD(, sge_fl) sfl;
568 	timeout_id_t sfl_timer;
569 
570 	/* Sensors */
571 	id_t temp_sensor;
572 	id_t volt_sensor;
573 
574 	ddi_ufm_handle_t *ufm_hdl;
575 
576 	/* support for single-threading access to adapter mailbox registers */
577 	kmutex_t mbox_lock;
578 	STAILQ_HEAD(, t4_mbox_list) mbox_list;
579 };
580 
581 enum {
582 	NIC_H = 0,
583 	TOM_H,
584 	IW_H,
585 	ISCSI_H
586 };
587 
588 struct memwin {
589 	uint32_t base;
590 	uint32_t aperture;
591 };
592 
593 #define	ADAPTER_LOCK(sc)		mutex_enter(&(sc)->lock)
594 #define	ADAPTER_UNLOCK(sc)		mutex_exit(&(sc)->lock)
595 #define	ADAPTER_LOCK_ASSERT_OWNED(sc)	ASSERT(mutex_owned(&(sc)->lock))
596 #define	ADAPTER_LOCK_ASSERT_NOTOWNED(sc) ASSERT(!mutex_owned(&(sc)->lock))
597 
598 #define	PORT_LOCK(pi)			mutex_enter(&(pi)->lock)
599 #define	PORT_UNLOCK(pi)			mutex_exit(&(pi)->lock)
600 #define	PORT_LOCK_ASSERT_OWNED(pi)	ASSERT(mutex_owned(&(pi)->lock))
601 #define	PORT_LOCK_ASSERT_NOTOWNED(pi)	ASSERT(!mutex_owned(&(pi)->lock))
602 
603 #define	IQ_LOCK(iq)			mutex_enter(&(iq)->lock)
604 #define	IQ_UNLOCK(iq)			mutex_exit(&(iq)->lock)
605 #define	IQ_LOCK_ASSERT_OWNED(iq)	ASSERT(mutex_owned(&(iq)->lock))
606 #define	IQ_LOCK_ASSERT_NOTOWNED(iq)	ASSERT(!mutex_owned(&(iq)->lock))
607 
608 #define	FL_LOCK(fl)			mutex_enter(&(fl)->lock)
609 #define	FL_UNLOCK(fl)			mutex_exit(&(fl)->lock)
610 #define	FL_LOCK_ASSERT_OWNED(fl)	ASSERT(mutex_owned(&(fl)->lock))
611 #define	FL_LOCK_ASSERT_NOTOWNED(fl)	ASSERT(!mutex_owned(&(fl)->lock))
612 
613 #define	RXQ_LOCK(rxq)			IQ_LOCK(&(rxq)->iq)
614 #define	RXQ_UNLOCK(rxq)			IQ_UNLOCK(&(rxq)->iq)
615 #define	RXQ_LOCK_ASSERT_OWNED(rxq)	IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
616 #define	RXQ_LOCK_ASSERT_NOTOWNED(rxq)	IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
617 
618 #define	RXQ_FL_LOCK(rxq)		FL_LOCK(&(rxq)->fl)
619 #define	RXQ_FL_UNLOCK(rxq)		FL_UNLOCK(&(rxq)->fl)
620 #define	RXQ_FL_LOCK_ASSERT_OWNED(rxq)	FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
621 #define	RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
622 
623 #define	EQ_LOCK(eq)			mutex_enter(&(eq)->lock)
624 #define	EQ_UNLOCK(eq)			mutex_exit(&(eq)->lock)
625 #define	EQ_LOCK_ASSERT_OWNED(eq)	ASSERT(mutex_owned(&(eq)->lock))
626 #define	EQ_LOCK_ASSERT_NOTOWNED(eq)	ASSERT(!mutex_owned(&(eq)->lock))
627 
628 #define	TXQ_LOCK(txq)			EQ_LOCK(&(txq)->eq)
629 #define	TXQ_UNLOCK(txq)			EQ_UNLOCK(&(txq)->eq)
630 #define	TXQ_LOCK_ASSERT_OWNED(txq)	EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
631 #define	TXQ_LOCK_ASSERT_NOTOWNED(txq)	EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
632 
633 #define	for_each_txq(pi, iter, txq) \
634 	txq = &pi->adapter->sge.txq[pi->first_txq]; \
635 	for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
636 #define	for_each_rxq(pi, iter, rxq) \
637 	rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
638 	for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
639 #define	for_each_ofld_txq(pi, iter, ofld_txq) \
640 	ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
641 	for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
642 #define	for_each_ofld_rxq(pi, iter, ofld_rxq) \
643 	ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
644 	for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
645 
646 #define	NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
647 
648 /* One for errors, one for firmware events */
649 #define	T4_EXTRA_INTR 2
650 
651 typedef kmutex_t t4_os_lock_t;
652 
t4_os_lock(t4_os_lock_t * lock)653 static inline void t4_os_lock(t4_os_lock_t *lock)
654 {
655 	mutex_enter(lock);
656 }
657 
t4_os_unlock(t4_os_lock_t * lock)658 static inline void t4_os_unlock(t4_os_lock_t *lock)
659 {
660 	mutex_exit(lock);
661 }
662 
t4_mbox_list_add(struct adapter * adap,struct t4_mbox_list * entry)663 static inline void t4_mbox_list_add(struct adapter *adap,
664 				    struct t4_mbox_list *entry)
665 {
666 	t4_os_lock(&adap->mbox_lock);
667 	STAILQ_INSERT_TAIL(&adap->mbox_list, entry, link);
668 	t4_os_unlock(&adap->mbox_lock);
669 }
670 
t4_mbox_list_del(struct adapter * adap,struct t4_mbox_list * entry)671 static inline void t4_mbox_list_del(struct adapter *adap,
672 				    struct t4_mbox_list *entry)
673 {
674 	t4_os_lock(&adap->mbox_lock);
675 	STAILQ_REMOVE(&adap->mbox_list, entry, t4_mbox_list, link);
676 	t4_os_unlock(&adap->mbox_lock);
677 }
678 
679 static inline struct t4_mbox_list *
t4_mbox_list_first_entry(struct adapter * adap)680 t4_mbox_list_first_entry(struct adapter *adap)
681 {
682 	return STAILQ_FIRST(&adap->mbox_list);
683 }
684 
685 static inline uint32_t
t4_read_reg(struct adapter * sc,uint32_t reg)686 t4_read_reg(struct adapter *sc, uint32_t reg)
687 {
688 	/* LINTED: E_BAD_PTR_CAST_ALIGN */
689 	return (ddi_get32(sc->regh, (uint32_t *)(sc->regp + reg)));
690 }
691 
692 static inline void
t4_write_reg(struct adapter * sc,uint32_t reg,uint32_t val)693 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
694 {
695 	/* LINTED: E_BAD_PTR_CAST_ALIGN */
696 	ddi_put32(sc->regh, (uint32_t *)(sc->regp + reg), val);
697 }
698 
699 static inline void
t4_os_pci_read_cfg1(struct adapter * sc,int reg,uint8_t * val)700 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
701 {
702 	*val = pci_config_get8(sc->pci_regh, reg);
703 }
704 
705 static inline void
t4_os_pci_write_cfg1(struct adapter * sc,int reg,uint8_t val)706 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
707 {
708 	pci_config_put8(sc->pci_regh, reg, val);
709 }
710 
711 static inline void
t4_os_pci_read_cfg2(struct adapter * sc,int reg,uint16_t * val)712 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
713 {
714 	*val = pci_config_get16(sc->pci_regh, reg);
715 }
716 
717 static inline void
t4_os_pci_write_cfg2(struct adapter * sc,int reg,uint16_t val)718 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
719 {
720 	pci_config_put16(sc->pci_regh, reg, val);
721 }
722 
723 static inline void
t4_os_pci_read_cfg4(struct adapter * sc,int reg,uint32_t * val)724 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
725 {
726 	*val = pci_config_get32(sc->pci_regh, reg);
727 }
728 
729 static inline void
t4_os_pci_write_cfg4(struct adapter * sc,int reg,uint32_t val)730 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
731 {
732 	pci_config_put32(sc->pci_regh, reg, val);
733 }
734 
735 static inline uint64_t
t4_read_reg64(struct adapter * sc,uint32_t reg)736 t4_read_reg64(struct adapter *sc, uint32_t reg)
737 {
738 	/* LINTED: E_BAD_PTR_CAST_ALIGN */
739 	return (ddi_get64(sc->regh, (uint64_t *)(sc->regp + reg)));
740 }
741 
742 static inline void
t4_write_reg64(struct adapter * sc,uint32_t reg,uint64_t val)743 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
744 {
745 	/* LINTED: E_BAD_PTR_CAST_ALIGN */
746 	ddi_put64(sc->regh, (uint64_t *)(sc->regp + reg), val);
747 }
748 
749 static inline struct port_info *
adap2pinfo(struct adapter * sc,int idx)750 adap2pinfo(struct adapter *sc, int idx)
751 {
752 	return (sc->port[idx]);
753 }
754 
755 static inline void
t4_os_set_hw_addr(struct adapter * sc,int idx,uint8_t hw_addr[])756 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
757 {
758 	bcopy(hw_addr, sc->port[idx]->hw_addr, ETHERADDRL);
759 }
760 
761 static inline bool
is_10G_port(const struct port_info * pi)762 is_10G_port(const struct port_info *pi)
763 {
764 	return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) != 0);
765 }
766 
767 static inline struct sge_rxq *
iq_to_rxq(struct sge_iq * iq)768 iq_to_rxq(struct sge_iq *iq)
769 {
770 	return (__containerof(iq, struct sge_rxq, iq));
771 }
772 
773 static inline bool
is_25G_port(const struct port_info * pi)774 is_25G_port(const struct port_info *pi)
775 {
776 	return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) != 0);
777 }
778 
779 static inline bool
is_40G_port(const struct port_info * pi)780 is_40G_port(const struct port_info *pi)
781 {
782 	return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) != 0);
783 }
784 
785 static inline bool
is_50G_port(const struct port_info * pi)786 is_50G_port(const struct port_info *pi)
787 {
788 	return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) != 0);
789 }
790 
791 static inline bool
is_100G_port(const struct port_info * pi)792 is_100G_port(const struct port_info *pi)
793 {
794 	return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) != 0);
795 }
796 
797 static inline bool
is_10XG_port(const struct port_info * pi)798 is_10XG_port(const struct port_info *pi)
799 {
800 	return (is_10G_port(pi) || is_40G_port(pi) ||
801 		is_25G_port(pi) || is_50G_port(pi) ||
802 		is_100G_port(pi));
803 }
804 
805 #ifdef TCP_OFFLOAD_ENABLE
806 int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0);
807 
808 static inline int
t4_wrq_tx(struct adapter * sc,struct sge_wrq * wrq,mblk_t * m)809 t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m)
810 {
811 	int rc;
812 
813 	TXQ_LOCK(wrq);
814 	rc = t4_wrq_tx_locked(sc, wrq, m);
815 	TXQ_UNLOCK(wrq);
816 	return (rc);
817 }
818 #endif
819 
820 /**
821  * t4_os_pci_read_seeprom - read four bytes of SEEPROM/VPD contents
822  * @adapter: the adapter
823  * @addr: SEEPROM/VPD Address to read
824  * @valp: where to store the value read
825  *
826  * Read a 32-bit value from the given address in the SEEPROM/VPD.  The address
827  * must be four-byte aligned.  Returns 0 on success, a negative erro number
828  * on failure.
829  */
t4_os_pci_read_seeprom(adapter_t * adapter,int addr,u32 * valp)830 static inline int t4_os_pci_read_seeprom(adapter_t *adapter,
831 					 int addr, u32 *valp)
832 {
833 	int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
834 	int ret;
835 
836 	ret = t4_seeprom_read(adapter, addr, valp);
837 
838 	return ret >= 0 ? 0 : ret;
839 }
840 
841 /**
842  * t4_os_pci_write_seeprom - write four bytes of SEEPROM/VPD contents
843  * @adapter: the adapter
844  * @addr: SEEPROM/VPD Address to write
845  * @val: the value write
846  *
847  * Write a 32-bit value to the given address in the SEEPROM/VPD.  The address
848  * must be four-byte aligned.  Returns 0 on success, a negative erro number
849  * on failure.
850  */
t4_os_pci_write_seeprom(adapter_t * adapter,int addr,u32 val)851 static inline int t4_os_pci_write_seeprom(adapter_t *adapter,
852 					  int addr, u32 val)
853 {
854 	int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
855 	int ret;
856 
857 	ret = t4_seeprom_write(adapter, addr, val);
858 
859 	return ret >= 0 ? 0 : ret;
860 }
861 
t4_os_pci_set_vpd_size(struct adapter * adapter,size_t len)862 static inline int t4_os_pci_set_vpd_size(struct adapter *adapter, size_t len)
863 {
864 	return 0;
865 }
866 
t4_use_ldst(struct adapter * adap)867 static inline unsigned int t4_use_ldst(struct adapter *adap)
868 {
869 	return (adap->flags & FW_OK);
870 }
871 #define t4_os_alloc(_size)	kmem_alloc(_size, KM_SLEEP)
872 
t4_db_full(struct adapter * adap)873 static inline void t4_db_full(struct adapter *adap) {}
t4_db_dropped(struct adapter * adap)874 static inline void t4_db_dropped(struct adapter *adap) {}
875 
876 /* t4_nexus.c */
877 int t4_os_find_pci_capability(struct adapter *sc, int cap);
878 void t4_os_portmod_changed(struct adapter *sc, int idx);
879 int adapter_full_init(struct adapter *sc);
880 int adapter_full_uninit(struct adapter *sc);
881 int port_full_init(struct port_info *pi);
882 int port_full_uninit(struct port_info *pi);
883 void enable_port_queues(struct port_info *pi);
884 void disable_port_queues(struct port_info *pi);
885 int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h);
886 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
887 void t4_iterate(void (*func)(int, void *), void *arg);
888 
889 /* t4_sge.c */
890 void t4_sge_init(struct adapter *sc);
891 int t4_setup_adapter_queues(struct adapter *sc);
892 int t4_teardown_adapter_queues(struct adapter *sc);
893 int t4_setup_port_queues(struct port_info *pi);
894 int t4_teardown_port_queues(struct port_info *pi);
895 uint_t t4_intr_all(caddr_t arg1, caddr_t arg2);
896 uint_t t4_intr(caddr_t arg1, caddr_t arg2);
897 uint_t t4_intr_err(caddr_t arg1, caddr_t arg2);
898 int t4_mgmt_tx(struct adapter *sc, mblk_t *m);
899 void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
900 uint32_t position_memwin(struct adapter *, int, uint32_t);
901 
902 mblk_t *t4_eth_tx(void *, mblk_t *);
903 mblk_t *t4_mc_tx(void *arg, mblk_t *m);
904 mblk_t *t4_ring_rx(struct sge_rxq *rxq, int poll_bytes);
905 int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps,  int count,
906     int flags);
907 
908 /* t4_mac.c */
909 void t4_mc_init(struct port_info *pi);
910 void t4_mc_cb_init(struct port_info *);
911 void t4_os_link_changed(struct adapter *sc, int idx, int link_stat);
912 void t4_mac_rx(struct port_info *pi, struct sge_rxq *rxq, mblk_t *m);
913 void t4_mac_tx_update(struct port_info *pi, struct sge_txq *txq);
914 int t4_addmac(void *arg, const uint8_t *ucaddr);
915 
916 /* t4_ioctl.c */
917 int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
918 
919 struct l2t_data *t4_init_l2t(struct adapter *sc);
920 int begin_synchronized_op(struct port_info *pi, int hold, int waitok);
921 void end_synchronized_op(struct port_info *pi, int held);
922 #endif /* __CXGBE_ADAPTER_H */
923