1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Chelsio Terminator 4 (T4) Firmware interface header file.
14  *
15  * Copyright (C) 2009-2013 Chelsio Communications.  All rights reserved.
16  *
17  * Written by felix marti (felix@chelsio.com)
18  *
19  * This program is distributed in the hope that it will be useful, but WITHOUT
20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
22  * release for licensing terms and conditions.
23  */
24 #ifndef _T4FW_INTERFACE_H_
25 #define	_T4FW_INTERFACE_H_
26 
27 /*
28  *	******************************
29  *	   R E T U R N   V A L U E S
30  *	******************************
31  */
32 
33 enum fw_retval {
34 	FW_SUCCESS		= 0,	/* completed sucessfully */
35 	FW_EPERM		= 1,	/* operation not permitted */
36 	FW_ENOENT		= 2,	/* no such file or directory */
37 	FW_EIO			= 5,	/* input/output error; hw bad */
38 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
39 	FW_EAGAIN		= 11,	/* try again */
40 	FW_ENOMEM		= 12,	/* out of memory */
41 	FW_EFAULT		= 14,	/* bad address; fw bad */
42 	FW_EBUSY		= 16,	/* resource busy */
43 	FW_EEXIST		= 17,	/* file exists */
44 	FW_ENODEV		= 19,	/* no such device */
45 	FW_EINVAL		= 22,	/* invalid argument */
46 	FW_ENOSPC		= 28,	/* no space left on device */
47 	FW_ENOSYS		= 38,	/* functionality not implemented */
48 	FW_ENODATA		= 61,	/* no data available */
49 	FW_EPROTO		= 71,	/* protocol error */
50 	FW_EADDRINUSE		= 98,	/* address already in use */
51 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
52 	FW_ENETDOWN		= 100,	/* network is down */
53 	FW_ENETUNREACH		= 101,	/* network is unreachable */
54 	FW_ENOBUFS		= 105,	/* no buffer space available */
55 	FW_ETIMEDOUT		= 110,	/* timeout */
56 	FW_EINPROGRESS		= 115,	/* fw internal */
57 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
58 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
59 	FW_SCSI_ABORTED		= 130,	/* */
60 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
61 	FW_ERR_LINK_DOWN	= 132,	/* */
62 	FW_RDEV_NOT_READY	= 133,	/* */
63 	FW_ERR_RDEV_LOST	= 134,	/* */
64 	FW_ERR_RDEV_LOGO	= 135,	/* */
65 	FW_FCOE_NO_XCHG		= 136,	/* */
66 	FW_SCSI_RSP_ERR		= 137,	/* */
67 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
68 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
69 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
70 	FW_SCSI_DDP_ERR		= 141,	/* DDP error */
71 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
72 };
73 
74 /*
75  *	******************************
76  *	   W O R K   R E Q U E S T s
77  *	******************************
78  */
79 
80 enum fw_wr_opcodes {
81 	FW_FRAG_WR		= 0x1d,
82 	FW_FILTER_WR		= 0x02,
83 	FW_ULPTX_WR		= 0x04,
84 	FW_TP_WR		= 0x05,
85 	FW_ETH_TX_PKT_WR	= 0x08,
86 	FW_ETH_TX_PKT2_WR	= 0x44,
87 	FW_ETH_TX_PKTS_WR	= 0x09,
88 	FW_ETH_TX_UO_WR		= 0x1c,
89 	FW_EQ_FLUSH_WR		= 0x1b,
90 	FW_OFLD_CONNECTION_WR	= 0x2f,
91 	FW_FLOWC_WR		= 0x0a,
92 	FW_OFLD_TX_DATA_WR	= 0x0b,
93 	FW_CMD_WR		= 0x10,
94 	FW_ETH_TX_PKT_VM_WR	= 0x11,
95 	FW_RI_RES_WR		= 0x0c,
96 	FW_RI_RDMA_WRITE_WR	= 0x14,
97 	FW_RI_SEND_WR		= 0x15,
98 	FW_RI_RDMA_READ_WR	= 0x16,
99 	FW_RI_RECV_WR		= 0x17,
100 	FW_RI_BIND_MW_WR	= 0x18,
101 	FW_RI_FR_NSMR_WR	= 0x19,
102 	FW_RI_INV_LSTAG_WR	= 0x1a,
103 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
104 	FW_RI_ATOMIC_WR		= 0x16,
105 	FW_RI_WR		= 0x0d,
106 	FW_CHNET_IFCONF_WR	= 0x6b,
107 	FW_RDEV_WR		= 0x38,
108 	FW_FOISCSI_NODE_WR	= 0x60,
109 	FW_FOISCSI_CTRL_WR	= 0x6a,
110 	FW_FOISCSI_CHAP_WR	= 0x6c,
111 	FW_FCOE_ELS_CT_WR	= 0x30,
112 	FW_SCSI_WRITE_WR	= 0x31,
113 	FW_SCSI_READ_WR		= 0x32,
114 	FW_SCSI_CMD_WR		= 0x33,
115 	FW_SCSI_ABRT_CLS_WR	= 0x34,
116 	FW_SCSI_TGT_ACC_WR	= 0x35,
117 	FW_SCSI_TGT_XMIT_WR	= 0x36,
118 	FW_SCSI_TGT_RSP_WR	= 0x37,
119 	FW_POFCOE_TCB_WR	= 0x42,
120 	FW_POFCOE_ULPTX_WR	= 0x43,
121 	FW_LASTC2E_WR		= 0x70
122 };
123 
124 /*
125  * Generic work request header flit0
126  */
127 struct fw_wr_hdr {
128 	__be32 hi;
129 	__be32 lo;
130 };
131 
132 /* work request opcode (hi) */
133 #define	S_FW_WR_OP		24
134 #define	M_FW_WR_OP		0xff
135 #define	V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
136 #define	G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
137 
138 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
139 #define	S_FW_WR_ATOMIC		23
140 #define	M_FW_WR_ATOMIC		0x1
141 #define	V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
142 #define	G_FW_WR_ATOMIC(x)	\
143 	(((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
144 #define	F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
145 
146 /*
147  *	flush flag (hi) - firmware flushes flushable work request buffered
148  *	in the flow context.
149  */
150 #define	S_FW_WR_FLUSH	22
151 #define	M_FW_WR_FLUSH	0x1
152 #define	V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
153 #define	G_FW_WR_FLUSH(x)  \
154 	(((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
155 #define	F_FW_WR_FLUSH	V_FW_WR_FLUSH(1U)
156 
157 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
158 #define	S_FW_WR_COMPL	21
159 #define	M_FW_WR_COMPL	0x1
160 #define	V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
161 #define	G_FW_WR_COMPL(x)  \
162 	(((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
163 #define	F_FW_WR_COMPL	V_FW_WR_COMPL(1U)
164 
165 /* work request immediate data lengh (hi) */
166 #define	S_FW_WR_IMMDLEN	0
167 #define	M_FW_WR_IMMDLEN	0xff
168 #define	V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
169 #define	G_FW_WR_IMMDLEN(x)	\
170 	(((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
171 
172 /* egress queue status update to associated ingress queue entry (lo) */
173 #define	S_FW_WR_EQUIQ		31
174 #define	M_FW_WR_EQUIQ		0x1
175 #define	V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
176 #define	G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
177 #define	F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
178 
179 /* egress queue status update to egress queue status entry (lo) */
180 #define	S_FW_WR_EQUEQ		30
181 #define	M_FW_WR_EQUEQ		0x1
182 #define	V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
183 #define	G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
184 #define	F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
185 
186 /* flow context identifier (lo) */
187 #define	S_FW_WR_FLOWID		8
188 #define	M_FW_WR_FLOWID		0xfffff
189 #define	V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
190 #define	G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
191 
192 /* length in units of 16-bytes (lo) */
193 #define	S_FW_WR_LEN16		0
194 #define	M_FW_WR_LEN16		0xff
195 #define	V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
196 #define	G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
197 
198 struct fw_frag_wr {
199 	__be32 op_to_fragoff16;
200 	__be32 flowid_len16;
201 	__be64 r4;
202 };
203 
204 #define S_FW_FRAG_WR_EOF	15
205 #define M_FW_FRAG_WR_EOF	0x1
206 #define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
207 #define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
208 #define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
209 
210 #define S_FW_FRAG_WR_FRAGOFF16		8
211 #define M_FW_FRAG_WR_FRAGOFF16		0x7f
212 #define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
213 #define G_FW_FRAG_WR_FRAGOFF16(x)	\
214     (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
215 
216 /*
217  * valid filter configurations for compressed tuple
218  * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
219  * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
220  * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
221  * OV - Outer VLAN/VNIC_ID,
222  */
223 #define	HW_TPL_FR_MT_M_E_P_FC		0x3C3
224 #define	HW_TPL_FR_MT_M_PR_T_FC		0x3B3
225 #define	HW_TPL_FR_MT_M_IV_P_FC		0x38B
226 #define	HW_TPL_FR_MT_M_OV_P_FC		0x387
227 #define	HW_TPL_FR_MT_E_PR_T		0x370
228 #define	HW_TPL_FR_MT_E_PR_P_FC		0X363
229 #define	HW_TPL_FR_MT_E_T_P_FC		0X353
230 #define	HW_TPL_FR_MT_PR_IV_P_FC		0X32B
231 #define	HW_TPL_FR_MT_PR_OV_P_FC		0X327
232 #define	HW_TPL_FR_MT_T_IV_P_FC		0X31B
233 #define	HW_TPL_FR_MT_T_OV_P_FC		0X317
234 #define	HW_TPL_FR_M_E_PR_FC		0X2E1
235 #define	HW_TPL_FR_M_E_T_FC		0X2D1
236 #define	HW_TPL_FR_M_PR_IV_FC		0X2A9
237 #define	HW_TPL_FR_M_PR_OV_FC		0X2A5
238 #define	HW_TPL_FR_M_T_IV_FC		0X299
239 #define	HW_TPL_FR_M_T_OV_FC		0X295
240 #define	HW_TPL_FR_E_PR_T_P		0X272
241 #define	HW_TPL_FR_E_PR_T_FC		0X271
242 #define	HW_TPL_FR_E_IV_FC		0X249
243 #define	HW_TPL_FR_E_OV_FC		0X245
244 #define	HW_TPL_FR_PR_T_IV_FC		0X239
245 #define	HW_TPL_FR_PR_T_OV_FC		0X235
246 #define	HW_TPL_FR_IV_OV_FC		0X20D
247 #define	HW_TPL_MT_M_E_PR		0X1E0
248 #define	HW_TPL_MT_M_E_T			0X1D0
249 #define	HW_TPL_MT_E_PR_T_FC		0X171
250 #define	HW_TPL_MT_E_IV			0X148
251 #define	HW_TPL_MT_E_OV			0X144
252 #define	HW_TPL_MT_PR_T_IV		0X138
253 #define	HW_TPL_MT_PR_T_OV		0X134
254 #define	HW_TPL_M_E_PR_P			0X0E2
255 #define	HW_TPL_M_E_T_P			0X0D2
256 #define	HW_TPL_E_PR_T_P_FC		0X073
257 #define	HW_TPL_E_IV_P			0X04A
258 #define	HW_TPL_E_OV_P			0X046
259 #define	HW_TPL_PR_T_IV_P		0X03A
260 #define	HW_TPL_PR_T_OV_P		0X036
261 
262 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
263 enum fw_filter_wr_cookie {
264 	FW_FILTER_WR_SUCCESS,
265 	FW_FILTER_WR_FLT_ADDED,
266 	FW_FILTER_WR_FLT_DELETED,
267 	FW_FILTER_WR_SMT_TBL_FULL,
268 	FW_FILTER_WR_EINVAL,
269 };
270 
271 struct fw_filter_wr {
272 	__be32 op_pkd;
273 	__be32 len16_pkd;
274 	__be64 r3;
275 	__be32 tid_to_iq;
276 	__be32 del_filter_to_l2tix;
277 	__be16 ethtype;
278 	__be16 ethtypem;
279 	__u8   frag_to_ovlan_vldm;
280 	__u8   smac_sel;
281 	__be16 rx_chan_rx_rpl_iq;
282 	__be32 maci_to_matchtypem;
283 	__u8   ptcl;
284 	__u8   ptclm;
285 	__u8   ttyp;
286 	__u8   ttypm;
287 	__be16 ivlan;
288 	__be16 ivlanm;
289 	__be16 ovlan;
290 	__be16 ovlanm;
291 	__u8   lip[16];
292 	__u8   lipm[16];
293 	__u8   fip[16];
294 	__u8   fipm[16];
295 	__be16 lp;
296 	__be16 lpm;
297 	__be16 fp;
298 	__be16 fpm;
299 	__be16 r7;
300 	__u8   sma[6];
301 };
302 
303 #define	S_FW_FILTER_WR_TID	12
304 #define	M_FW_FILTER_WR_TID	0xfffff
305 #define	V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
306 #define	G_FW_FILTER_WR_TID(x)	\
307 	(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
308 
309 #define	S_FW_FILTER_WR_RQTYPE		11
310 #define	M_FW_FILTER_WR_RQTYPE		0x1
311 #define	V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
312 #define	G_FW_FILTER_WR_RQTYPE(x)	\
313 	(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
314 #define	F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
315 
316 #define	S_FW_FILTER_WR_NOREPLY		10
317 #define	M_FW_FILTER_WR_NOREPLY		0x1
318 #define	V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
319 #define	G_FW_FILTER_WR_NOREPLY(x)	\
320 	(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
321 #define	F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
322 
323 #define	S_FW_FILTER_WR_IQ	0
324 #define	M_FW_FILTER_WR_IQ	0x3ff
325 #define	V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
326 #define	G_FW_FILTER_WR_IQ(x)	\
327 	(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
328 
329 #define	S_FW_FILTER_WR_DEL_FILTER	31
330 #define	M_FW_FILTER_WR_DEL_FILTER	0x1
331 #define	V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
332 #define	G_FW_FILTER_WR_DEL_FILTER(x)	\
333 	(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
334 #define	F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
335 
336 #define	S_FW_FILTER_WR_RPTTID		25
337 #define	M_FW_FILTER_WR_RPTTID		0x1
338 #define	V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
339 #define	G_FW_FILTER_WR_RPTTID(x)	\
340 	(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
341 #define	F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
342 
343 #define	S_FW_FILTER_WR_DROP	24
344 #define	M_FW_FILTER_WR_DROP	0x1
345 #define	V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
346 #define	G_FW_FILTER_WR_DROP(x)	\
347 	(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
348 #define	F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
349 
350 #define	S_FW_FILTER_WR_DIRSTEER		23
351 #define	M_FW_FILTER_WR_DIRSTEER		0x1
352 #define	V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
353 #define	G_FW_FILTER_WR_DIRSTEER(x)	\
354 	(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
355 #define	F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
356 
357 #define	S_FW_FILTER_WR_MASKHASH		22
358 #define	M_FW_FILTER_WR_MASKHASH		0x1
359 #define	V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
360 #define	G_FW_FILTER_WR_MASKHASH(x)	\
361 	(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
362 #define	F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
363 
364 #define	S_FW_FILTER_WR_DIRSTEERHASH	21
365 #define	M_FW_FILTER_WR_DIRSTEERHASH	0x1
366 #define	V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
367 #define	G_FW_FILTER_WR_DIRSTEERHASH(x)	\
368 	(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
369 #define	F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
370 
371 #define	S_FW_FILTER_WR_LPBK	20
372 #define	M_FW_FILTER_WR_LPBK	0x1
373 #define	V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
374 #define	G_FW_FILTER_WR_LPBK(x)	\
375 	(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
376 #define	F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
377 
378 #define	S_FW_FILTER_WR_DMAC	19
379 #define	M_FW_FILTER_WR_DMAC	0x1
380 #define	V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
381 #define	G_FW_FILTER_WR_DMAC(x)	\
382 	(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
383 #define	F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
384 
385 #define	S_FW_FILTER_WR_SMAC	18
386 #define	M_FW_FILTER_WR_SMAC	0x1
387 #define	V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
388 #define	G_FW_FILTER_WR_SMAC(x)	\
389 	(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
390 #define	F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
391 
392 #define	S_FW_FILTER_WR_INSVLAN		17
393 #define	M_FW_FILTER_WR_INSVLAN		0x1
394 #define	V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
395 #define	G_FW_FILTER_WR_INSVLAN(x)	\
396 	(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
397 #define	F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
398 
399 #define	S_FW_FILTER_WR_RMVLAN		16
400 #define	M_FW_FILTER_WR_RMVLAN		0x1
401 #define	V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
402 #define	G_FW_FILTER_WR_RMVLAN(x)	\
403 	(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
404 #define	F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
405 
406 #define	S_FW_FILTER_WR_HITCNTS		15
407 #define	M_FW_FILTER_WR_HITCNTS		0x1
408 #define	V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
409 #define	G_FW_FILTER_WR_HITCNTS(x)	\
410 	(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
411 #define	F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
412 
413 #define	S_FW_FILTER_WR_TXCHAN		13
414 #define	M_FW_FILTER_WR_TXCHAN		0x3
415 #define	V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
416 #define	G_FW_FILTER_WR_TXCHAN(x)	\
417 	(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
418 
419 #define	S_FW_FILTER_WR_PRIO	12
420 #define	M_FW_FILTER_WR_PRIO	0x1
421 #define	V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
422 #define	G_FW_FILTER_WR_PRIO(x)	\
423 	(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
424 #define	F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
425 
426 #define	S_FW_FILTER_WR_L2TIX	0
427 #define	M_FW_FILTER_WR_L2TIX	0xfff
428 #define	V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
429 #define	G_FW_FILTER_WR_L2TIX(x)	\
430 	(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
431 
432 #define	S_FW_FILTER_WR_FRAG	7
433 #define	M_FW_FILTER_WR_FRAG	0x1
434 #define	V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
435 #define	G_FW_FILTER_WR_FRAG(x)	\
436 	(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
437 #define	F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
438 
439 #define	S_FW_FILTER_WR_FRAGM	6
440 #define	M_FW_FILTER_WR_FRAGM	0x1
441 #define	V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
442 #define	G_FW_FILTER_WR_FRAGM(x)	\
443 	(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
444 #define	F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
445 
446 #define	S_FW_FILTER_WR_IVLAN_VLD	5
447 #define	M_FW_FILTER_WR_IVLAN_VLD	0x1
448 #define	V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
449 #define	G_FW_FILTER_WR_IVLAN_VLD(x)	\
450 	(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
451 #define	F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
452 
453 #define	S_FW_FILTER_WR_OVLAN_VLD	4
454 #define	M_FW_FILTER_WR_OVLAN_VLD	0x1
455 #define	V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
456 #define	G_FW_FILTER_WR_OVLAN_VLD(x)	\
457 	(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
458 #define	F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
459 
460 #define	S_FW_FILTER_WR_IVLAN_VLDM	3
461 #define	M_FW_FILTER_WR_IVLAN_VLDM	0x1
462 #define	V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
463 #define	G_FW_FILTER_WR_IVLAN_VLDM(x)	\
464 	(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
465 #define	F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
466 
467 #define	S_FW_FILTER_WR_OVLAN_VLDM	2
468 #define	M_FW_FILTER_WR_OVLAN_VLDM	0x1
469 #define	V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
470 #define	G_FW_FILTER_WR_OVLAN_VLDM(x)	\
471 	(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
472 #define	F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
473 
474 #define	S_FW_FILTER_WR_RX_CHAN		15
475 #define	M_FW_FILTER_WR_RX_CHAN		0x1
476 #define	V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
477 #define	G_FW_FILTER_WR_RX_CHAN(x)	\
478 	(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
479 #define	F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
480 
481 #define	S_FW_FILTER_WR_RX_RPL_IQ	0
482 #define	M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
483 #define	V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
484 #define	G_FW_FILTER_WR_RX_RPL_IQ(x)	\
485 	(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
486 
487 #define	S_FW_FILTER_WR_MACI	23
488 #define	M_FW_FILTER_WR_MACI	0x1ff
489 #define	V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
490 #define	G_FW_FILTER_WR_MACI(x)	\
491 	(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
492 
493 #define	S_FW_FILTER_WR_MACIM	14
494 #define	M_FW_FILTER_WR_MACIM	0x1ff
495 #define	V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
496 #define	G_FW_FILTER_WR_MACIM(x)	\
497 	(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
498 
499 #define	S_FW_FILTER_WR_FCOE	13
500 #define	M_FW_FILTER_WR_FCOE	0x1
501 #define	V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
502 #define	G_FW_FILTER_WR_FCOE(x)	\
503 	(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
504 #define	F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
505 
506 #define	S_FW_FILTER_WR_FCOEM	12
507 #define	M_FW_FILTER_WR_FCOEM	0x1
508 #define	V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
509 #define	G_FW_FILTER_WR_FCOEM(x)	\
510 	(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
511 #define	F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
512 
513 #define	S_FW_FILTER_WR_PORT	9
514 #define	M_FW_FILTER_WR_PORT	0x7
515 #define	V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
516 #define	G_FW_FILTER_WR_PORT(x)	\
517 	(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
518 
519 #define	S_FW_FILTER_WR_PORTM	6
520 #define	M_FW_FILTER_WR_PORTM	0x7
521 #define	V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
522 #define	G_FW_FILTER_WR_PORTM(x)	\
523 	(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
524 
525 #define	S_FW_FILTER_WR_MATCHTYPE	3
526 #define	M_FW_FILTER_WR_MATCHTYPE	0x7
527 #define	V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
528 #define	G_FW_FILTER_WR_MATCHTYPE(x)	\
529 	(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
530 
531 #define	S_FW_FILTER_WR_MATCHTYPEM	0
532 #define	M_FW_FILTER_WR_MATCHTYPEM	0x7
533 #define	V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
534 #define	G_FW_FILTER_WR_MATCHTYPEM(x)	\
535 	(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
536 
537 struct fw_ulptx_wr {
538 	__be32 op_to_compl;
539 	__be32 flowid_len16;
540 	__u64  cookie;
541 };
542 
543 struct fw_tp_wr {
544 	__be32 op_to_immdlen;
545 	__be32 flowid_len16;
546 	__u64  cookie;
547 };
548 
549 struct fw_eth_tx_pkt_wr {
550 	__be32 op_immdlen;
551 	__be32 equiq_to_len16;
552 	__be64 r3;
553 };
554 
555 #define	S_FW_ETH_TX_PKT_WR_IMMDLEN	0
556 #define	M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
557 #define	V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
558 #define	G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
559 	(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
560 
561 struct fw_eth_tx_pkt2_wr {
562 	__be32 op_immdlen;
563 	__be32 equiq_to_len16;
564 	__be32 r3;
565 	__be32 L4ChkDisable_to_IpHdrLen;
566 };
567 
568 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
569 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
570 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
571 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
572     (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
573 
574 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
575 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
576 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
577     ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
578 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
579     (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
580      M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
581 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
582     V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
583 
584 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
585 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
586 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
587     ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
588 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
589     (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
590      M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
591 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
592     V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
593 
594 #define S_FW_ETH_TX_PKT2_WR_IVLAN	28
595 #define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
596 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
597 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
598     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
599 #define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
600 
601 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
602 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
603 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
604 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
605     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
606 
607 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
608 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
609 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
610 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
611     (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
612 
613 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
614 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
615 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
616 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
617     (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
618 
619 struct fw_eth_tx_pkts_wr {
620 	__be32 op_pkd;
621 	__be32 equiq_to_len16;
622 	__be32 r3;
623 	__be16 plen;
624 	__u8   npkt;
625 	__u8   type;
626 };
627 
628 struct fw_eth_tx_uo_wr {
629 	__be32 op_immdlen;
630 	__be32 equiq_to_len16;
631 	__be64 r3;
632 	__u8   r4;
633 	__u8   ethlen;
634 	__be16 iplen;
635 	__u8   udplen;
636 	__u8   rtplen;
637 	__be16 r5;
638 	__be16 mss;
639 	__be16 schedpktsize;
640 	__be32 length;
641 };
642 
643 struct fw_eq_flush_wr {
644 	__u8   opcode;
645 	__u8   r1[3];
646 	__be32 equiq_to_len16;
647 	__be64 r3;
648 };
649 
650 struct fw_ofld_connection_wr {
651 	__be32 op_compl;
652 	__be32 len16_pkd;
653 	__u64  cookie;
654 	__be64 r2;
655 	__be64 r3;
656 	struct fw_ofld_connection_le {
657 		__be32 version_cpl;
658 		__be32 filter;
659 		__be32 r1;
660 		__be16 lport;
661 		__be16 pport;
662 		union fw_ofld_connection_leip {
663 			struct fw_ofld_connection_le_ipv4 {
664 				__be32 pip;
665 				__be32 lip;
666 				__be64 r0;
667 				__be64 r1;
668 				__be64 r2;
669 			} ipv4;
670 			struct fw_ofld_connection_le_ipv6 {
671 				__be64 pip_hi;
672 				__be64 pip_lo;
673 				__be64 lip_hi;
674 				__be64 lip_lo;
675 			} ipv6;
676 		} u;
677 	} le;
678 	struct fw_ofld_connection_tcb {
679 		__be32 t_state_to_astid;
680 		__be16 cplrxdataack_cplpassacceptrpl;
681 		__be16 rcv_adv;
682 		__be32 rcv_nxt;
683 		__be32 tx_max;
684 		__be64 opt0;
685 		__be32 opt2;
686 		__be32 r1;
687 		__be64 r2;
688 		__be64 r3;
689 	} tcb;
690 };
691 
692 #define	S_FW_OFLD_CONNECTION_WR_VERSION		31
693 #define	M_FW_OFLD_CONNECTION_WR_VERSION		0x1
694 #define	V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
695 	((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
696 #define	G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
697 	(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
698 	M_FW_OFLD_CONNECTION_WR_VERSION)
699 #define	F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
700 
701 #define	S_FW_OFLD_CONNECTION_WR_CPL	30
702 #define	M_FW_OFLD_CONNECTION_WR_CPL	0x1
703 #define	V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
704 #define	G_FW_OFLD_CONNECTION_WR_CPL(x)	\
705 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
706 #define	F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
707 
708 #define	S_FW_OFLD_CONNECTION_WR_T_STATE		28
709 #define	M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
710 #define	V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
711 	((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
712 #define	G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
713 	(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
714 	M_FW_OFLD_CONNECTION_WR_T_STATE)
715 
716 #define	S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
717 #define	M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
718 #define	V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
719 	((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
720 #define	G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
721 	(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
722 	M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
723 
724 #define	S_FW_OFLD_CONNECTION_WR_ASTID		0
725 #define	M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
726 #define	V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
727 	((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
728 #define	G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
729 	(((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
730 
731 #define	S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
732 #define	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
733 #define	V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
734 	((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
735 #define	G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
736 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
737 	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
738 #define	F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
739     V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
740 
741 #define	S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
742 #define	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
743 #define	V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
744 	((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
745 #define	G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
746 	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
747 	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
748 #define	F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
749     V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
750 
751 enum fw_flowc_mnem_tcpstate {
752 	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0,	/* illegal */
753 	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1,	/* illegal */
754 	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2,	/* illegal */
755 	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3,	/* illegal */
756 	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4,	/* default */
757 	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5,	/* got peer close already */
758 	/* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */
759 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6,
760 	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
761 	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7,
762 	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
763 	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8,
764 	/* sent FIN and got FIN + ACK, waiting for FIN */
765 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9,
766 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10,	/* not expected */
767 };
768 
769 enum fw_flowc_mnem_uostate {
770 	FW_FLOWC_MNEM_UOSTATE_CLOSED	= 0,	/* illegal */
771 	FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1,	/* default */
772 	/* graceful close, after sending outstanding payload */
773 	FW_FLOWC_MNEM_UOSTATE_CLOSING	= 2,
774 	/* immediate close, after discarding outstanding payload */
775 	FW_FLOWC_MNEM_UOSTATE_ABORTING	= 3,
776 };
777 
778 enum fw_flowc_mnem {
779 	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
780 	FW_FLOWC_MNEM_CH		= 1,
781 	FW_FLOWC_MNEM_PORT		= 2,
782 	FW_FLOWC_MNEM_IQID		= 3,
783 	FW_FLOWC_MNEM_SNDNXT		= 4,
784 	FW_FLOWC_MNEM_RCVNXT		= 5,
785 	FW_FLOWC_MNEM_SNDBUF		= 6,
786 	FW_FLOWC_MNEM_MSS		= 7,
787 	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
788 	FW_FLOWC_MNEM_TCPSTATE		= 9,
789 	FW_FLOWC_MNEM_UOSTATE		= 10,
790 	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
791 	FW_FLOWC_MNEM_DCBPRIO		= 12,
792 };
793 
794 struct fw_flowc_mnemval {
795 	__u8   mnemonic;
796 	__u8   r4[3];
797 	__be32 val;
798 };
799 
800 struct fw_flowc_wr {
801 	__be32 op_to_nparams;
802 	__be32 flowid_len16;
803 #ifndef C99_NOT_SUPPORTED
804 	struct fw_flowc_mnemval mnemval[];
805 #endif
806 };
807 
808 #define	S_FW_FLOWC_WR_NPARAMS		0
809 #define	M_FW_FLOWC_WR_NPARAMS		0xff
810 #define	V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
811 #define	G_FW_FLOWC_WR_NPARAMS(x)	\
812 	(((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
813 
814 struct fw_ofld_tx_data_wr {
815 	__be32 op_to_immdlen;
816 	__be32 flowid_len16;
817 	__be32 plen;
818 	__be32 tunnel_to_proxy;
819 };
820 
821 #define	S_FW_OFLD_TX_DATA_WR_TUNNEL	19
822 #define	M_FW_OFLD_TX_DATA_WR_TUNNEL	0x1
823 #define	V_FW_OFLD_TX_DATA_WR_TUNNEL(x)	((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
824 #define	G_FW_OFLD_TX_DATA_WR_TUNNEL(x)	\
825 	(((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
826 #define	F_FW_OFLD_TX_DATA_WR_TUNNEL	V_FW_OFLD_TX_DATA_WR_TUNNEL(1U)
827 
828 #define	S_FW_OFLD_TX_DATA_WR_SAVE	18
829 #define	M_FW_OFLD_TX_DATA_WR_SAVE	0x1
830 #define	V_FW_OFLD_TX_DATA_WR_SAVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SAVE)
831 #define	G_FW_OFLD_TX_DATA_WR_SAVE(x)	\
832 	(((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
833 #define	F_FW_OFLD_TX_DATA_WR_SAVE	V_FW_OFLD_TX_DATA_WR_SAVE(1U)
834 
835 #define	S_FW_OFLD_TX_DATA_WR_FLUSH	17
836 #define	M_FW_OFLD_TX_DATA_WR_FLUSH	0x1
837 #define	V_FW_OFLD_TX_DATA_WR_FLUSH(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLUSH)
838 #define	G_FW_OFLD_TX_DATA_WR_FLUSH(x)	\
839 	(((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
840 #define	F_FW_OFLD_TX_DATA_WR_FLUSH	V_FW_OFLD_TX_DATA_WR_FLUSH(1U)
841 
842 #define	S_FW_OFLD_TX_DATA_WR_URGENT	16
843 #define	M_FW_OFLD_TX_DATA_WR_URGENT	0x1
844 #define	V_FW_OFLD_TX_DATA_WR_URGENT(x)	((x) << S_FW_OFLD_TX_DATA_WR_URGENT)
845 #define	G_FW_OFLD_TX_DATA_WR_URGENT(x)	\
846 	(((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
847 #define	F_FW_OFLD_TX_DATA_WR_URGENT	V_FW_OFLD_TX_DATA_WR_URGENT(1U)
848 
849 #define	S_FW_OFLD_TX_DATA_WR_MORE	15
850 #define	M_FW_OFLD_TX_DATA_WR_MORE	0x1
851 #define	V_FW_OFLD_TX_DATA_WR_MORE(x)	((x) << S_FW_OFLD_TX_DATA_WR_MORE)
852 #define	G_FW_OFLD_TX_DATA_WR_MORE(x)	\
853 	(((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
854 #define	F_FW_OFLD_TX_DATA_WR_MORE	V_FW_OFLD_TX_DATA_WR_MORE(1U)
855 
856 #define	S_FW_OFLD_TX_DATA_WR_SHOVE	14
857 #define	M_FW_OFLD_TX_DATA_WR_SHOVE	0x1
858 #define	V_FW_OFLD_TX_DATA_WR_SHOVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SHOVE)
859 #define	G_FW_OFLD_TX_DATA_WR_SHOVE(x)	\
860 	(((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
861 #define	F_FW_OFLD_TX_DATA_WR_SHOVE	V_FW_OFLD_TX_DATA_WR_SHOVE(1U)
862 
863 #define	S_FW_OFLD_TX_DATA_WR_ULPMODE	10
864 #define	M_FW_OFLD_TX_DATA_WR_ULPMODE	0xf
865 #define	V_FW_OFLD_TX_DATA_WR_ULPMODE(x)	((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE)
866 #define	G_FW_OFLD_TX_DATA_WR_ULPMODE(x)	\
867 	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)
868 
869 #define	S_FW_OFLD_TX_DATA_WR_ULPSUBMODE		6
870 #define	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE		0xf
871 #define	V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
872 	((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
873 #define	G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
874 	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
875 	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
876 
877 #define	S_FW_OFLD_TX_DATA_WR_PROXY	5
878 #define	M_FW_OFLD_TX_DATA_WR_PROXY	0x1
879 #define	V_FW_OFLD_TX_DATA_WR_PROXY(x)	((x) << S_FW_OFLD_TX_DATA_WR_PROXY)
880 #define	G_FW_OFLD_TX_DATA_WR_PROXY(x)	\
881 	(((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
882 #define	F_FW_OFLD_TX_DATA_WR_PROXY	V_FW_OFLD_TX_DATA_WR_PROXY(1U)
883 
884 struct fw_cmd_wr {
885 	__be32 op_dma;
886 	__be32 len16_pkd;
887 	__be64 cookie_daddr;
888 };
889 
890 #define	S_FW_CMD_WR_DMA		17
891 #define	M_FW_CMD_WR_DMA		0x1
892 #define	V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
893 #define	G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
894 #define	F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
895 
896 struct fw_eth_tx_pkt_vm_wr {
897 	__be32 op_immdlen;
898 	__be32 equiq_to_len16;
899 	__be32 r3[2];
900 	__u8   ethmacdst[6];
901 	__u8   ethmacsrc[6];
902 	__be16 ethtype;
903 	__be16 vlantci;
904 };
905 
906 /*
907  *	************************************
908  *	   R I   W O R K   R E Q U E S T s
909  *	************************************
910  */
911 
912 enum fw_ri_wr_opcode {
913 	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
914 	FW_RI_READ_REQ			= 0x1,
915 	FW_RI_READ_RESP			= 0x2,
916 	FW_RI_SEND			= 0x3,
917 	FW_RI_SEND_WITH_INV		= 0x4,
918 	FW_RI_SEND_WITH_SE		= 0x5,
919 	FW_RI_SEND_WITH_SE_INV		= 0x6,
920 	FW_RI_TERMINATE			= 0x7,
921 	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
922 	FW_RI_BIND_MW			= 0x9,
923 	FW_RI_FAST_REGISTER		= 0xa,
924 	FW_RI_LOCAL_INV			= 0xb,
925 	FW_RI_QP_MODIFY			= 0xc,
926 	FW_RI_BYPASS			= 0xd,
927 	FW_RI_RECEIVE			= 0xe,
928 	FW_RI_SGE_EC_CR_RETURN		= 0xf
929 
930 };
931 
932 enum fw_ri_wr_flags {
933 	FW_RI_COMPLETION_FLAG		= 0x01,
934 	FW_RI_NOTIFICATION_FLAG		= 0x02,
935 	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
936 	FW_RI_READ_FENCE_FLAG		= 0x08,
937 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
938 	FW_RI_RDMA_READ_INVALIDATE	= 0x20
939 };
940 
941 enum fw_ri_mpa_attrs {
942 	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
943 	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
944 	FW_RI_MPA_CRC_ENABLE		= 0x04,
945 	FW_RI_MPA_IETF_ENABLE		= 0x08
946 };
947 
948 enum fw_ri_qp_caps {
949 	FW_RI_QP_RDMA_READ_ENABLE	 = 0x01,
950 	FW_RI_QP_RDMA_WRITE_ENABLE	 = 0x02,
951 	FW_RI_QP_BIND_ENABLE		 = 0x04,
952 	FW_RI_QP_FAST_REGISTER_ENABLE	 = 0x08,
953 	FW_RI_QP_STAG0_ENABLE		 = 0x10,
954 	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80,
955 };
956 
957 enum fw_ri_addr_type {
958 	FW_RI_ZERO_BASED_TO		= 0x00,
959 	FW_RI_VA_BASED_TO		= 0x01
960 };
961 
962 enum fw_ri_mem_perms {
963 	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
964 	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
965 	FW_RI_MEM_ACCESS_REM		= 0x03,
966 	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
967 	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
968 	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
969 };
970 
971 enum fw_ri_stag_type {
972 	FW_RI_STAG_NSMR			= 0x00,
973 	FW_RI_STAG_SMR			= 0x01,
974 	FW_RI_STAG_MW			= 0x02,
975 	FW_RI_STAG_MW_RELAXED		= 0x03
976 };
977 
978 enum fw_ri_data_op {
979 	FW_RI_DATA_IMMD			= 0x81,
980 	FW_RI_DATA_DSGL			= 0x82,
981 	FW_RI_DATA_ISGL			= 0x83
982 };
983 
984 enum fw_ri_sgl_depth {
985 	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
986 	FW_RI_SGL_DEPTH_MAX_RQ		= 4
987 };
988 
989 enum fw_ri_cqe_err {
990 	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
991 	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
992 	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
993 	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
994 	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
995 	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
996 	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
997 	/* attempt to invalidate a SMR */
998 	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07,
999 	/* attempt to invalidate a MR w MW */
1000 	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08,
1001 	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
1002 	/* ECC error detected when reading the PSTAG for a MW Invalidate */
1003 	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A,
1004 	/* pbl address out of bound : software error */
1005 	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B,
1006 	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
1007 	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
1008 	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
1009 	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
1010 	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
1011 	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
1012 	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
1013 	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
1014 	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
1015 	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
1016 	/* MO not zero for TERMINATE or READ_REQ */
1017 	FW_RI_CQE_ERR_MO		= 0x1A,
1018 	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
1019 	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
1020 	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
1021 	/* RQE address out of bound : software error */
1022 	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E,
1023 	/* internel error (opcode mismatch) */
1024 	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F
1025 
1026 };
1027 
1028 struct fw_ri_dsge_pair {
1029 	__be32	len[2];
1030 	__be64	addr[2];
1031 };
1032 
1033 struct fw_ri_dsgl {
1034 	__u8	op;
1035 	__u8	r1;
1036 	__be16	nsge;
1037 	__be32	len0;
1038 	__be64	addr0;
1039 #ifndef C99_NOT_SUPPORTED
1040 	struct fw_ri_dsge_pair sge[];
1041 #endif
1042 };
1043 
1044 struct fw_ri_sge {
1045 	__be32 stag;
1046 	__be32 len;
1047 	__be64 to;
1048 };
1049 
1050 struct fw_ri_isgl {
1051 	__u8	op;
1052 	__u8	r1;
1053 	__be16	nsge;
1054 	__be32	r2;
1055 #ifndef C99_NOT_SUPPORTED
1056 	struct fw_ri_sge sge[];
1057 #endif
1058 };
1059 
1060 struct fw_ri_immd {
1061 	__u8	op;
1062 	__u8	r1;
1063 	__be16	r2;
1064 	__be32	immdlen;
1065 #ifndef C99_NOT_SUPPORTED
1066 	__u8	data[];
1067 #endif
1068 };
1069 
1070 struct fw_ri_tpte {
1071 	__be32 valid_to_pdid;
1072 	__be32 locread_to_qpid;
1073 	__be32 nosnoop_pbladdr;
1074 	__be32 len_lo;
1075 	__be32 va_hi;
1076 	__be32 va_lo_fbo;
1077 	__be32 dca_mwbcnt_pstag;
1078 	__be32 len_hi;
1079 };
1080 
1081 #define	S_FW_RI_TPTE_VALID		31
1082 #define	M_FW_RI_TPTE_VALID		0x1
1083 #define	V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
1084 #define	G_FW_RI_TPTE_VALID(x)		\
1085 	(((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1086 #define	F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1087 
1088 #define	S_FW_RI_TPTE_STAGKEY		23
1089 #define	M_FW_RI_TPTE_STAGKEY		0xff
1090 #define	V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1091 #define	G_FW_RI_TPTE_STAGKEY(x)		\
1092 	(((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1093 
1094 #define	S_FW_RI_TPTE_STAGSTATE		22
1095 #define	M_FW_RI_TPTE_STAGSTATE		0x1
1096 #define	V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1097 #define	G_FW_RI_TPTE_STAGSTATE(x)	\
1098 	(((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1099 #define	F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1100 
1101 #define	S_FW_RI_TPTE_STAGTYPE		20
1102 #define	M_FW_RI_TPTE_STAGTYPE		0x3
1103 #define	V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1104 #define	G_FW_RI_TPTE_STAGTYPE(x)	\
1105 	(((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1106 
1107 #define	S_FW_RI_TPTE_PDID		0
1108 #define	M_FW_RI_TPTE_PDID		0xfffff
1109 #define	V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1110 #define	G_FW_RI_TPTE_PDID(x)		\
1111 	(((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1112 
1113 #define	S_FW_RI_TPTE_PERM		28
1114 #define	M_FW_RI_TPTE_PERM		0xf
1115 #define	V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1116 #define	G_FW_RI_TPTE_PERM(x)		\
1117 	(((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1118 
1119 #define	S_FW_RI_TPTE_REMINVDIS		27
1120 #define	M_FW_RI_TPTE_REMINVDIS		0x1
1121 #define	V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1122 #define	G_FW_RI_TPTE_REMINVDIS(x)	\
1123 	(((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1124 #define	F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1125 
1126 #define	S_FW_RI_TPTE_ADDRTYPE		26
1127 #define	M_FW_RI_TPTE_ADDRTYPE		1
1128 #define	V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1129 #define	G_FW_RI_TPTE_ADDRTYPE(x)	\
1130 	(((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1131 #define	F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1132 
1133 #define	S_FW_RI_TPTE_MWBINDEN		25
1134 #define	M_FW_RI_TPTE_MWBINDEN		0x1
1135 #define	V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1136 #define	G_FW_RI_TPTE_MWBINDEN(x)	\
1137 	(((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1138 #define	F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1139 
1140 #define	S_FW_RI_TPTE_PS			20
1141 #define	M_FW_RI_TPTE_PS			0x1f
1142 #define	V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1143 #define	G_FW_RI_TPTE_PS(x)		\
1144 	(((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1145 
1146 #define	S_FW_RI_TPTE_QPID		0
1147 #define	M_FW_RI_TPTE_QPID		0xfffff
1148 #define	V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1149 #define	G_FW_RI_TPTE_QPID(x)		\
1150 	(((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1151 
1152 #define	S_FW_RI_TPTE_NOSNOOP		31
1153 #define	M_FW_RI_TPTE_NOSNOOP		0x1
1154 #define	V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1155 #define	G_FW_RI_TPTE_NOSNOOP(x)		\
1156 	(((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1157 #define	F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1158 
1159 #define	S_FW_RI_TPTE_PBLADDR		0
1160 #define	M_FW_RI_TPTE_PBLADDR		0x1fffffff
1161 #define	V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1162 #define	G_FW_RI_TPTE_PBLADDR(x)		\
1163 	(((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1164 
1165 #define	S_FW_RI_TPTE_DCA		24
1166 #define	M_FW_RI_TPTE_DCA		0x1f
1167 #define	V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1168 #define	G_FW_RI_TPTE_DCA(x)		\
1169 	(((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1170 
1171 #define	S_FW_RI_TPTE_MWBCNT_PSTAG	0
1172 #define	M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
1173 #define	V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1174 	((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1175 #define	G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1176 	(((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1177 
1178 enum fw_ri_cqe_rxtx {
1179 	FW_RI_CQE_RXTX_RX = 0x0,
1180 	FW_RI_CQE_RXTX_TX = 0x1,
1181 };
1182 
1183 struct fw_ri_cqe {
1184 	union fw_ri_rxtx {
1185 		struct fw_ri_scqe {
1186 		__be32	qpid_n_stat_rxtx_type;
1187 		__be32	plen;
1188 		__be32	reserved;
1189 		__be32	wrid;
1190 		} scqe;
1191 		struct fw_ri_rcqe {
1192 		__be32	qpid_n_stat_rxtx_type;
1193 		__be32	plen;
1194 		__be32	stag;
1195 		__be32	msn;
1196 		} rcqe;
1197 	} u;
1198 };
1199 
1200 #define	S_FW_RI_CQE_QPID	12
1201 #define	M_FW_RI_CQE_QPID	0xfffff
1202 #define	V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1203 #define	G_FW_RI_CQE_QPID(x)   \
1204 	(((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1205 
1206 #define	S_FW_RI_CQE_NOTIFY    10
1207 #define	M_FW_RI_CQE_NOTIFY    0x1
1208 #define	V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1209 #define	G_FW_RI_CQE_NOTIFY(x) \
1210 	(((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1211 
1212 #define	S_FW_RI_CQE_STATUS    5
1213 #define	M_FW_RI_CQE_STATUS    0x1f
1214 #define	V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1215 #define	G_FW_RI_CQE_STATUS(x) \
1216 	(((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1217 
1218 #define	S_FW_RI_CQE_RXTX	4
1219 #define	M_FW_RI_CQE_RXTX	0x1
1220 #define	V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1221 #define	G_FW_RI_CQE_RXTX(x)   \
1222 	(((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1223 
1224 #define	S_FW_RI_CQE_TYPE	0
1225 #define	M_FW_RI_CQE_TYPE	0xf
1226 #define	V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1227 #define	G_FW_RI_CQE_TYPE(x)   \
1228 	(((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1229 
1230 enum fw_ri_res_type {
1231 	FW_RI_RES_TYPE_SQ,
1232 	FW_RI_RES_TYPE_RQ,
1233 	FW_RI_RES_TYPE_CQ,
1234 };
1235 
1236 enum fw_ri_res_op {
1237 	FW_RI_RES_OP_WRITE,
1238 	FW_RI_RES_OP_RESET,
1239 };
1240 
1241 struct fw_ri_res {
1242 	union fw_ri_restype {
1243 		struct fw_ri_res_sqrq {
1244 			__u8   restype;
1245 			__u8   op;
1246 			__be16 r3;
1247 			__be32 eqid;
1248 			__be32 r4[2];
1249 			__be32 fetchszm_to_iqid;
1250 			__be32 dcaen_to_eqsize;
1251 			__be64 eqaddr;
1252 		} sqrq;
1253 		struct fw_ri_res_cq {
1254 			__u8   restype;
1255 			__u8   op;
1256 			__be16 r3;
1257 			__be32 iqid;
1258 			__be32 r4[2];
1259 			__be32 iqandst_to_iqandstindex;
1260 			__be16 iqdroprss_to_iqesize;
1261 			__be16 iqsize;
1262 			__be64 iqaddr;
1263 			__be32 iqns_iqro;
1264 			__be32 r6_lo;
1265 			__be64 r7;
1266 		} cq;
1267 	} u;
1268 };
1269 
1270 struct fw_ri_res_wr {
1271 	__be32 op_nres;
1272 	__be32 len16_pkd;
1273 	__u64  cookie;
1274 #ifndef C99_NOT_SUPPORTED
1275 	struct fw_ri_res res[];
1276 #endif
1277 };
1278 
1279 #define	S_FW_RI_RES_WR_NRES	0
1280 #define	M_FW_RI_RES_WR_NRES	0xff
1281 #define	V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1282 #define	G_FW_RI_RES_WR_NRES(x)	\
1283 	(((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1284 
1285 #define	S_FW_RI_RES_WR_FETCHSZM		26
1286 #define	M_FW_RI_RES_WR_FETCHSZM		0x1
1287 #define	V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1288 #define	G_FW_RI_RES_WR_FETCHSZM(x)	\
1289 	(((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1290 #define	F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1291 
1292 #define	S_FW_RI_RES_WR_STATUSPGNS	25
1293 #define	M_FW_RI_RES_WR_STATUSPGNS	0x1
1294 #define	V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1295 #define	G_FW_RI_RES_WR_STATUSPGNS(x)	\
1296 	(((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1297 #define	F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1298 
1299 #define	S_FW_RI_RES_WR_STATUSPGRO	24
1300 #define	M_FW_RI_RES_WR_STATUSPGRO	0x1
1301 #define	V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1302 #define	G_FW_RI_RES_WR_STATUSPGRO(x)	\
1303 	(((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1304 #define	F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
1305 
1306 #define	S_FW_RI_RES_WR_FETCHNS		23
1307 #define	M_FW_RI_RES_WR_FETCHNS		0x1
1308 #define	V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
1309 #define	G_FW_RI_RES_WR_FETCHNS(x)	\
1310 	(((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1311 #define	F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
1312 
1313 #define	S_FW_RI_RES_WR_FETCHRO		22
1314 #define	M_FW_RI_RES_WR_FETCHRO		0x1
1315 #define	V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
1316 #define	G_FW_RI_RES_WR_FETCHRO(x)	\
1317 	(((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1318 #define	F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
1319 
1320 #define	S_FW_RI_RES_WR_HOSTFCMODE	20
1321 #define	M_FW_RI_RES_WR_HOSTFCMODE	0x3
1322 #define	V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1323 #define	G_FW_RI_RES_WR_HOSTFCMODE(x)	\
1324 	(((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1325 
1326 #define	S_FW_RI_RES_WR_CPRIO	19
1327 #define	M_FW_RI_RES_WR_CPRIO	0x1
1328 #define	V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
1329 #define	G_FW_RI_RES_WR_CPRIO(x)	\
1330 	(((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1331 #define	F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
1332 
1333 #define	S_FW_RI_RES_WR_ONCHIP		18
1334 #define	M_FW_RI_RES_WR_ONCHIP		0x1
1335 #define	V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
1336 #define	G_FW_RI_RES_WR_ONCHIP(x)	\
1337 	(((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1338 #define	F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
1339 
1340 #define	S_FW_RI_RES_WR_PCIECHN		16
1341 #define	M_FW_RI_RES_WR_PCIECHN		0x3
1342 #define	V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
1343 #define	G_FW_RI_RES_WR_PCIECHN(x)	\
1344 	(((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1345 
1346 #define	S_FW_RI_RES_WR_IQID	0
1347 #define	M_FW_RI_RES_WR_IQID	0xffff
1348 #define	V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
1349 #define	G_FW_RI_RES_WR_IQID(x)	\
1350 	(((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1351 
1352 #define	S_FW_RI_RES_WR_DCAEN	31
1353 #define	M_FW_RI_RES_WR_DCAEN	0x1
1354 #define	V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
1355 #define	G_FW_RI_RES_WR_DCAEN(x)	\
1356 	(((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1357 #define	F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
1358 
1359 #define	S_FW_RI_RES_WR_DCACPU		26
1360 #define	M_FW_RI_RES_WR_DCACPU		0x1f
1361 #define	V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
1362 #define	G_FW_RI_RES_WR_DCACPU(x)	\
1363 	(((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1364 
1365 #define	S_FW_RI_RES_WR_FBMIN	23
1366 #define	M_FW_RI_RES_WR_FBMIN	0x7
1367 #define	V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
1368 #define	G_FW_RI_RES_WR_FBMIN(x)	\
1369 	(((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1370 
1371 #define	S_FW_RI_RES_WR_FBMAX	20
1372 #define	M_FW_RI_RES_WR_FBMAX	0x7
1373 #define	V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
1374 #define	G_FW_RI_RES_WR_FBMAX(x)	\
1375 	(((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1376 
1377 #define	S_FW_RI_RES_WR_CIDXFTHRESHO	19
1378 #define	M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
1379 #define	V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1380 #define	G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
1381 	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1382 #define	F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1383 
1384 #define	S_FW_RI_RES_WR_CIDXFTHRESH	16
1385 #define	M_FW_RI_RES_WR_CIDXFTHRESH	0x7
1386 #define	V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1387 #define	G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
1388 	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1389 
1390 #define	S_FW_RI_RES_WR_EQSIZE		0
1391 #define	M_FW_RI_RES_WR_EQSIZE		0xffff
1392 #define	V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
1393 #define	G_FW_RI_RES_WR_EQSIZE(x)	\
1394 	(((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1395 
1396 #define	S_FW_RI_RES_WR_IQANDST		15
1397 #define	M_FW_RI_RES_WR_IQANDST		0x1
1398 #define	V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
1399 #define	G_FW_RI_RES_WR_IQANDST(x)	\
1400 	(((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1401 #define	F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
1402 
1403 #define	S_FW_RI_RES_WR_IQANUS		14
1404 #define	M_FW_RI_RES_WR_IQANUS		0x1
1405 #define	V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
1406 #define	G_FW_RI_RES_WR_IQANUS(x)	\
1407 	(((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1408 #define	F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
1409 
1410 #define	S_FW_RI_RES_WR_IQANUD		12
1411 #define	M_FW_RI_RES_WR_IQANUD		0x3
1412 #define	V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
1413 #define	G_FW_RI_RES_WR_IQANUD(x)	\
1414 	(((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1415 
1416 #define	S_FW_RI_RES_WR_IQANDSTINDEX	0
1417 #define	M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
1418 #define	V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1419 #define	G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
1420 	(((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1421 
1422 #define	S_FW_RI_RES_WR_IQDROPRSS	15
1423 #define	M_FW_RI_RES_WR_IQDROPRSS	0x1
1424 #define	V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
1425 #define	G_FW_RI_RES_WR_IQDROPRSS(x)	\
1426 	(((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1427 #define	F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
1428 
1429 #define	S_FW_RI_RES_WR_IQGTSMODE	14
1430 #define	M_FW_RI_RES_WR_IQGTSMODE	0x1
1431 #define	V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
1432 #define	G_FW_RI_RES_WR_IQGTSMODE(x)	\
1433 	(((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1434 #define	F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
1435 
1436 #define	S_FW_RI_RES_WR_IQPCIECH		12
1437 #define	M_FW_RI_RES_WR_IQPCIECH		0x3
1438 #define	V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
1439 #define	G_FW_RI_RES_WR_IQPCIECH(x)	\
1440 	(((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1441 
1442 #define	S_FW_RI_RES_WR_IQDCAEN		11
1443 #define	M_FW_RI_RES_WR_IQDCAEN		0x1
1444 #define	V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
1445 #define	G_FW_RI_RES_WR_IQDCAEN(x)	\
1446 	(((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1447 #define	F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
1448 
1449 #define	S_FW_RI_RES_WR_IQDCACPU		6
1450 #define	M_FW_RI_RES_WR_IQDCACPU		0x1f
1451 #define	V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
1452 #define	G_FW_RI_RES_WR_IQDCACPU(x)	\
1453 	(((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1454 
1455 #define	S_FW_RI_RES_WR_IQINTCNTTHRESH		4
1456 #define	M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
1457 #define	V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1458 	((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1459 #define	G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1460 	(((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1461 
1462 #define	S_FW_RI_RES_WR_IQO	3
1463 #define	M_FW_RI_RES_WR_IQO	0x1
1464 #define	V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
1465 #define	G_FW_RI_RES_WR_IQO(x)	\
1466 	(((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1467 #define	F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
1468 
1469 #define	S_FW_RI_RES_WR_IQCPRIO		2
1470 #define	M_FW_RI_RES_WR_IQCPRIO		0x1
1471 #define	V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
1472 #define	G_FW_RI_RES_WR_IQCPRIO(x)	\
1473 	(((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1474 #define	F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
1475 
1476 #define	S_FW_RI_RES_WR_IQESIZE		0
1477 #define	M_FW_RI_RES_WR_IQESIZE		0x3
1478 #define	V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
1479 #define	G_FW_RI_RES_WR_IQESIZE(x)	\
1480 	(((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1481 
1482 #define	S_FW_RI_RES_WR_IQNS	31
1483 #define	M_FW_RI_RES_WR_IQNS	0x1
1484 #define	V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
1485 #define	G_FW_RI_RES_WR_IQNS(x)	\
1486 	(((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1487 #define	F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
1488 
1489 #define	S_FW_RI_RES_WR_IQRO	30
1490 #define	M_FW_RI_RES_WR_IQRO	0x1
1491 #define	V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
1492 #define	G_FW_RI_RES_WR_IQRO(x)	\
1493 	(((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1494 #define	F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
1495 
1496 struct fw_ri_rdma_write_wr {
1497 	__u8   opcode;
1498 	__u8   flags;
1499 	__u16  wrid;
1500 	__u8   r1[3];
1501 	__u8   len16;
1502 	__be64 r2;
1503 	__be32 plen;
1504 	__be32 stag_sink;
1505 	__be64 to_sink;
1506 };
1507 
1508 struct fw_ri_send_wr {
1509 	__u8   opcode;
1510 	__u8   flags;
1511 	__u16  wrid;
1512 	__u8   r1[3];
1513 	__u8   len16;
1514 	__be32 sendop_pkd;
1515 	__be32 stag_inv;
1516 	__be32 plen;
1517 	__be32 r3;
1518 	__be64 r4;
1519 };
1520 
1521 #define	S_FW_RI_SEND_WR_SENDOP		0
1522 #define	M_FW_RI_SEND_WR_SENDOP		0xf
1523 #define	V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
1524 #define	G_FW_RI_SEND_WR_SENDOP(x)	\
1525 	(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1526 
1527 struct fw_ri_rdma_read_wr {
1528 	__u8   opcode;
1529 	__u8   flags;
1530 	__u16  wrid;
1531 	__u8   r1[3];
1532 	__u8   len16;
1533 	__be64 r2;
1534 	__be32 stag_sink;
1535 	__be32 to_sink_hi;
1536 	__be32 to_sink_lo;
1537 	__be32 plen;
1538 	__be32 stag_src;
1539 	__be32 to_src_hi;
1540 	__be32 to_src_lo;
1541 	__be32 r5;
1542 };
1543 
1544 struct fw_ri_recv_wr {
1545 	__u8   opcode;
1546 	__u8   r1;
1547 	__u16  wrid;
1548 	__u8   r2[3];
1549 	__u8   len16;
1550 };
1551 
1552 struct fw_ri_bind_mw_wr {
1553 	__u8   opcode;
1554 	__u8   flags;
1555 	__u16  wrid;
1556 	__u8   r1[3];
1557 	__u8   len16;
1558 	__u8   qpbinde_to_dcacpu;
1559 	__u8   pgsz_shift;
1560 	__u8   addr_type;
1561 	__u8   mem_perms;
1562 	__be32 stag_mr;
1563 	__be32 stag_mw;
1564 	__be32 r3;
1565 	__be64 len_mw;
1566 	__be64 va_fbo;
1567 	__be64 r4;
1568 };
1569 
1570 #define	S_FW_RI_BIND_MW_WR_QPBINDE	6
1571 #define	M_FW_RI_BIND_MW_WR_QPBINDE	0x1
1572 #define	V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1573 #define	G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
1574 	(((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1575 #define	F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1576 
1577 #define	S_FW_RI_BIND_MW_WR_NS		5
1578 #define	M_FW_RI_BIND_MW_WR_NS		0x1
1579 #define	V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
1580 #define	G_FW_RI_BIND_MW_WR_NS(x)	\
1581 	(((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1582 #define	F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
1583 
1584 #define	S_FW_RI_BIND_MW_WR_DCACPU	0
1585 #define	M_FW_RI_BIND_MW_WR_DCACPU	0x1f
1586 #define	V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1587 #define	G_FW_RI_BIND_MW_WR_DCACPU(x)	\
1588 	(((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1589 
1590 struct fw_ri_fr_nsmr_wr {
1591 	__u8   opcode;
1592 	__u8   flags;
1593 	__u16  wrid;
1594 	__u8   r1[3];
1595 	__u8   len16;
1596 	__u8   qpbinde_to_dcacpu;
1597 	__u8   pgsz_shift;
1598 	__u8   addr_type;
1599 	__u8   mem_perms;
1600 	__be32 stag;
1601 	__be32 len_hi;
1602 	__be32 len_lo;
1603 	__be32 va_hi;
1604 	__be32 va_lo_fbo;
1605 };
1606 
1607 #define	S_FW_RI_FR_NSMR_WR_QPBINDE	6
1608 #define	M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
1609 #define	V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1610 #define	G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
1611 	(((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1612 #define	F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1613 
1614 #define	S_FW_RI_FR_NSMR_WR_NS		5
1615 #define	M_FW_RI_FR_NSMR_WR_NS		0x1
1616 #define	V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
1617 #define	G_FW_RI_FR_NSMR_WR_NS(x)	\
1618 	(((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1619 #define	F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
1620 
1621 #define	S_FW_RI_FR_NSMR_WR_DCACPU	0
1622 #define	M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
1623 #define	V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1624 #define	G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
1625 	(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1626 
1627 struct fw_ri_inv_lstag_wr {
1628 	__u8   opcode;
1629 	__u8   flags;
1630 	__u16  wrid;
1631 	__u8   r1[3];
1632 	__u8   len16;
1633 	__be32 r2;
1634 	__be32 stag_inv;
1635 };
1636 
1637 struct fw_ri_send_immediate_wr {
1638 	__u8   opcode;
1639 	__u8   flags;
1640 	__u16  wrid;
1641 	__u8   r1[3];
1642 	__u8   len16;
1643 	__be32 sendimmop_pkd;
1644 	__be32 r3;
1645 	__be32 plen;
1646 	__be32 r4;
1647 	__be64 r5;
1648 };
1649 
1650 #define	S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
1651 #define	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
1652 #define	V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1653 	((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1654 #define	G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1655 	(((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1656 	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1657 
1658 enum fw_ri_atomic_op {
1659 	FW_RI_ATOMIC_OP_FETCHADD,
1660 	FW_RI_ATOMIC_OP_SWAP,
1661 	FW_RI_ATOMIC_OP_CMDSWAP,
1662 };
1663 
1664 struct fw_ri_atomic_wr {
1665 	__u8   opcode;
1666 	__u8   flags;
1667 	__u16  wrid;
1668 	__u8   r1[3];
1669 	__u8   len16;
1670 	__be32 atomicop_pkd;
1671 	__be64 r3;
1672 	__be32 aopcode_pkd;
1673 	__be32 reqid;
1674 	__be32 stag;
1675 	__be32 to_hi;
1676 	__be32 to_lo;
1677 	__be32 addswap_data_hi;
1678 	__be32 addswap_data_lo;
1679 	__be32 addswap_mask_hi;
1680 	__be32 addswap_mask_lo;
1681 	__be32 compare_data_hi;
1682 	__be32 compare_data_lo;
1683 	__be32 compare_mask_hi;
1684 	__be32 compare_mask_lo;
1685 	__be32 r5;
1686 };
1687 
1688 #define	S_FW_RI_ATOMIC_WR_ATOMICOP	0
1689 #define	M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
1690 #define	V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1691 #define	G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
1692 	(((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1693 
1694 #define	S_FW_RI_ATOMIC_WR_AOPCODE	0
1695 #define	M_FW_RI_ATOMIC_WR_AOPCODE	0xf
1696 #define	V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1697 #define	G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
1698 	(((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1699 
1700 enum fw_ri_type {
1701 	FW_RI_TYPE_INIT,
1702 	FW_RI_TYPE_FINI,
1703 	FW_RI_TYPE_TERMINATE
1704 };
1705 
1706 enum fw_ri_init_p2ptype {
1707 	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
1708 	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
1709 	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
1710 	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
1711 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
1712 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
1713 	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
1714 };
1715 
1716 struct fw_ri_wr {
1717 	__be32 op_compl;
1718 	__be32 flowid_len16;
1719 	__u64  cookie;
1720 	union fw_ri {
1721 		struct fw_ri_init {
1722 			__u8   type;
1723 			__u8   mpareqbit_p2ptype;
1724 			__u8   r4[2];
1725 			__u8   mpa_attrs;
1726 			__u8   qp_caps;
1727 			__be16 nrqe;
1728 			__be32 pdid;
1729 			__be32 qpid;
1730 			__be32 sq_eqid;
1731 			__be32 rq_eqid;
1732 			__be32 scqid;
1733 			__be32 rcqid;
1734 			__be32 ord_max;
1735 			__be32 ird_max;
1736 			__be32 iss;
1737 			__be32 irs;
1738 			__be32 hwrqsize;
1739 			__be32 hwrqaddr;
1740 			__be64 r5;
1741 			union fw_ri_init_p2p {
1742 				struct fw_ri_rdma_write_wr write;
1743 				struct fw_ri_rdma_read_wr read;
1744 				struct fw_ri_send_wr send;
1745 			} u;
1746 		} init;
1747 		struct fw_ri_fini {
1748 			__u8   type;
1749 			__u8   r3[7];
1750 			__be64 r4;
1751 		} fini;
1752 		struct fw_ri_terminate {
1753 			__u8   type;
1754 			__u8   r3[3];
1755 			__be32 immdlen;
1756 			__u8   termmsg[40];
1757 		} terminate;
1758 	} u;
1759 };
1760 
1761 #define	S_FW_RI_WR_MPAREQBIT	7
1762 #define	M_FW_RI_WR_MPAREQBIT	0x1
1763 #define	V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
1764 #define	G_FW_RI_WR_MPAREQBIT(x)	\
1765 	(((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
1766 #define	F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
1767 
1768 #define	S_FW_RI_WR_0BRRBIT	6
1769 #define	M_FW_RI_WR_0BRRBIT	0x1
1770 #define	V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
1771 #define	G_FW_RI_WR_0BRRBIT(x)	\
1772 	(((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
1773 #define	F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
1774 
1775 #define	S_FW_RI_WR_P2PTYPE	0
1776 #define	M_FW_RI_WR_P2PTYPE	0xf
1777 #define	V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
1778 #define	G_FW_RI_WR_P2PTYPE(x)	\
1779 	(((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
1780 
1781 /*
1782  *	*******************************************
1783  *	  F O i S C S I   W O R K R E Q U E S T s
1784  *	*******************************************
1785  */
1786 
1787 #define	FW_FOISCSI_NAME_MAX_LEN		224
1788 #define	FW_FOISCSI_ALIAS_MAX_LEN	224
1789 #define	FW_FOISCSI_CHAP_SEC_MAX_LEN	128
1790 #define	FW_FOISCSI_INIT_NODE_MAX	8
1791 
1792 enum fw_chnet_ifconf_wr_subop {
1793 	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
1794 
1795 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
1796 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
1797 
1798 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
1799 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
1800 
1801 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
1802 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
1803 
1804 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
1805 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
1806 
1807 	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
1808 	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
1809 
1810 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
1811 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
1812 
1813 	FW_CHNET_IFCONF_WR_SUBOP_MAX,
1814 };
1815 
1816 struct fw_chnet_ifconf_wr {
1817 	__be32 op_compl;
1818 	__be32 flowid_len16;
1819 	__be64 cookie;
1820 	__be32 if_flowid;
1821 	__u8   idx;
1822 	__u8   subop;
1823 	__u8   retval;
1824 	__u8   r2;
1825 	__be64 r3;
1826 	struct fw_chnet_ifconf_params {
1827 		__be32 r0;
1828 		__be16 vlanid;
1829 		__be16 mtu;
1830 		union fw_chnet_ifconf_addr_type {
1831 			struct fw_chnet_ifconf_ipv4 {
1832 				__be32 addr;
1833 				__be32 mask;
1834 				__be32 router;
1835 				__be32 r0;
1836 				__be64 r1;
1837 			} ipv4;
1838 			struct fw_chnet_ifconf_ipv6 {
1839 				__be64 linklocal_lo;
1840 				__be64 linklocal_hi;
1841 				__be64 router_hi;
1842 				__be64 router_lo;
1843 				__be64 aconf_hi;
1844 				__be64 aconf_lo;
1845 				__be64 linklocal_aconf_hi;
1846 				__be64 linklocal_aconf_lo;
1847 				__be64 router_aconf_hi;
1848 				__be64 router_aconf_lo;
1849 				__be64 r0;
1850 			} ipv6;
1851 		} in_attr;
1852 	} param;
1853 };
1854 
1855 enum fw_foiscsi_node_type {
1856 	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
1857 	FW_FOISCSI_NODE_TYPE_TARGET,
1858 };
1859 
1860 enum fw_foiscsi_session_type {
1861 	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
1862 	FW_FOISCSI_SESSION_TYPE_NORMAL,
1863 };
1864 
1865 enum fw_foiscsi_auth_policy {
1866 	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
1867 	FW_FOISCSI_AUTH_POLICY_MUTUAL,
1868 };
1869 
1870 enum fw_foiscsi_auth_method {
1871 	FW_FOISCSI_AUTH_METHOD_NONE = 0,
1872 	FW_FOISCSI_AUTH_METHOD_CHAP,
1873 	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
1874 	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
1875 };
1876 
1877 enum fw_foiscsi_digest_type {
1878 	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
1879 	FW_FOISCSI_DIGEST_TYPE_CRC32,
1880 	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
1881 	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
1882 };
1883 
1884 enum fw_foiscsi_wr_subop {
1885 	FW_FOISCSI_WR_SUBOP_ADD = 1,
1886 	FW_FOISCSI_WR_SUBOP_DEL = 2,
1887 	FW_FOISCSI_WR_SUBOP_MOD = 4,
1888 };
1889 
1890 enum fw_foiscsi_ctrl_state {
1891 	FW_FOISCSI_CTRL_STATE_FREE = 0,
1892 	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
1893 	FW_FOISCSI_CTRL_STATE_FAILED,
1894 	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
1895 	FW_FOISCSI_CTRL_STATE_REDIRECT,
1896 };
1897 
1898 struct fw_rdev_wr {
1899 	__be32 op_to_immdlen;
1900 	__be32 alloc_to_len16;
1901 	__be64 cookie;
1902 	__u8   protocol;
1903 	__u8   event_cause;
1904 	__u8   cur_state;
1905 	__u8   prev_state;
1906 	__be32 flags_to_assoc_flowid;
1907 	union rdev_entry {
1908 		struct fcoe_rdev_entry {
1909 			__be32 flowid;
1910 			__u8   protocol;
1911 			__u8   event_cause;
1912 			__u8   flags;
1913 			__u8   rjt_reason;
1914 			__u8   cur_login_st;
1915 			__u8   prev_login_st;
1916 			__be16 rcv_fr_sz;
1917 			__u8   rd_xfer_rdy_to_rport_type;
1918 			__u8   vft_to_qos;
1919 			__u8   org_proc_assoc_to_acc_rsp_code;
1920 			__u8   enh_disc_to_tgt;
1921 			__u8   wwnn[8];
1922 			__u8   wwpn[8];
1923 			__be16 iqid;
1924 			__u8   fc_oui[3];
1925 			__u8   r_id[3];
1926 		} fcoe_rdev;
1927 		struct iscsi_rdev_entry {
1928 			__be32 flowid;
1929 			__u8   protocol;
1930 			__u8   event_cause;
1931 			__u8   flags;
1932 			__u8   r3;
1933 			__be16 iscsi_opts;
1934 			__be16 tcp_opts;
1935 			__be16 ip_opts;
1936 			__be16 max_rcv_len;
1937 			__be16 max_snd_len;
1938 			__be16 first_brst_len;
1939 			__be16 max_brst_len;
1940 			__be16 r4;
1941 			__be16 def_time2wait;
1942 			__be16 def_time2ret;
1943 			__be16 nop_out_intrvl;
1944 			__be16 non_scsi_to;
1945 			__be16 isid;
1946 			__be16 tsid;
1947 			__be16 port;
1948 			__be16 tpgt;
1949 			__u8   r5[6];
1950 			__be16 iqid;
1951 		} iscsi_rdev;
1952 	} u;
1953 };
1954 
1955 #define	S_FW_RDEV_WR_IMMDLEN	0
1956 #define	M_FW_RDEV_WR_IMMDLEN	0xff
1957 #define	V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
1958 #define	G_FW_RDEV_WR_IMMDLEN(x)	\
1959 	(((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
1960 
1961 #define	S_FW_RDEV_WR_ALLOC	31
1962 #define	M_FW_RDEV_WR_ALLOC	0x1
1963 #define	V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
1964 #define	G_FW_RDEV_WR_ALLOC(x)	\
1965 	(((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
1966 #define	F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
1967 
1968 #define	S_FW_RDEV_WR_FREE	30
1969 #define	M_FW_RDEV_WR_FREE	0x1
1970 #define	V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
1971 #define	G_FW_RDEV_WR_FREE(x)	\
1972 	(((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
1973 #define	F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
1974 
1975 #define	S_FW_RDEV_WR_MODIFY	29
1976 #define	M_FW_RDEV_WR_MODIFY	0x1
1977 #define	V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
1978 #define	G_FW_RDEV_WR_MODIFY(x)	\
1979 	(((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
1980 #define	F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
1981 
1982 #define	S_FW_RDEV_WR_FLOWID	8
1983 #define	M_FW_RDEV_WR_FLOWID	0xfffff
1984 #define	V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
1985 #define	G_FW_RDEV_WR_FLOWID(x)	\
1986 	(((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
1987 
1988 #define	S_FW_RDEV_WR_LEN16	0
1989 #define	M_FW_RDEV_WR_LEN16	0xff
1990 #define	V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
1991 #define	G_FW_RDEV_WR_LEN16(x)	\
1992 	(((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
1993 
1994 #define	S_FW_RDEV_WR_FLAGS	24
1995 #define	M_FW_RDEV_WR_FLAGS	0xff
1996 #define	V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
1997 #define	G_FW_RDEV_WR_FLAGS(x)	\
1998 	(((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
1999 
2000 #define	S_FW_RDEV_WR_GET_NEXT		20
2001 #define	M_FW_RDEV_WR_GET_NEXT		0xf
2002 #define	V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
2003 #define	G_FW_RDEV_WR_GET_NEXT(x)	\
2004 	(((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2005 
2006 #define	S_FW_RDEV_WR_ASSOC_FLOWID	0
2007 #define	M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
2008 #define	V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2009 #define	G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
2010 	(((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2011 
2012 #define	S_FW_RDEV_WR_RJT	7
2013 #define	M_FW_RDEV_WR_RJT	0x1
2014 #define	V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
2015 #define	G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2016 #define	F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
2017 
2018 #define	S_FW_RDEV_WR_REASON	0
2019 #define	M_FW_RDEV_WR_REASON	0x7f
2020 #define	V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
2021 #define	G_FW_RDEV_WR_REASON(x)	\
2022 	(((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2023 
2024 #define	S_FW_RDEV_WR_RD_XFER_RDY	7
2025 #define	M_FW_RDEV_WR_RD_XFER_RDY	0x1
2026 #define	V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2027 #define	G_FW_RDEV_WR_RD_XFER_RDY(x)	\
2028 	(((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2029 #define	F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
2030 
2031 #define	S_FW_RDEV_WR_WR_XFER_RDY	6
2032 #define	M_FW_RDEV_WR_WR_XFER_RDY	0x1
2033 #define	V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2034 #define	G_FW_RDEV_WR_WR_XFER_RDY(x)	\
2035 	(((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2036 #define	F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
2037 
2038 #define	S_FW_RDEV_WR_FC_SP	5
2039 #define	M_FW_RDEV_WR_FC_SP	0x1
2040 #define	V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
2041 #define	G_FW_RDEV_WR_FC_SP(x)	\
2042 	(((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2043 #define	F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
2044 
2045 #define	S_FW_RDEV_WR_RPORT_TYPE		0
2046 #define	M_FW_RDEV_WR_RPORT_TYPE		0x1f
2047 #define	V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
2048 #define	G_FW_RDEV_WR_RPORT_TYPE(x)	\
2049 	(((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2050 
2051 #define	S_FW_RDEV_WR_VFT	7
2052 #define	M_FW_RDEV_WR_VFT	0x1
2053 #define	V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
2054 #define	G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2055 #define	F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
2056 
2057 #define	S_FW_RDEV_WR_NPIV	6
2058 #define	M_FW_RDEV_WR_NPIV	0x1
2059 #define	V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
2060 #define	G_FW_RDEV_WR_NPIV(x)	\
2061 	(((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2062 #define	F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
2063 
2064 #define	S_FW_RDEV_WR_CLASS	4
2065 #define	M_FW_RDEV_WR_CLASS	0x3
2066 #define	V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
2067 #define	G_FW_RDEV_WR_CLASS(x)	\
2068 	(((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2069 
2070 #define	S_FW_RDEV_WR_SEQ_DEL	3
2071 #define	M_FW_RDEV_WR_SEQ_DEL	0x1
2072 #define	V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
2073 #define	G_FW_RDEV_WR_SEQ_DEL(x)	\
2074 	(((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2075 #define	F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
2076 
2077 #define	S_FW_RDEV_WR_PRIO_PREEMP	2
2078 #define	M_FW_RDEV_WR_PRIO_PREEMP	0x1
2079 #define	V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2080 #define	G_FW_RDEV_WR_PRIO_PREEMP(x)	\
2081 	(((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2082 #define	F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
2083 
2084 #define	S_FW_RDEV_WR_PREF	1
2085 #define	M_FW_RDEV_WR_PREF	0x1
2086 #define	V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
2087 #define	G_FW_RDEV_WR_PREF(x)	\
2088 	(((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2089 #define	F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
2090 
2091 #define	S_FW_RDEV_WR_QOS	0
2092 #define	M_FW_RDEV_WR_QOS	0x1
2093 #define	V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
2094 #define	G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2095 #define	F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
2096 
2097 #define	S_FW_RDEV_WR_ORG_PROC_ASSOC	7
2098 #define	M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
2099 #define	V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2100 #define	G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
2101 	(((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2102 #define	F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2103 
2104 #define	S_FW_RDEV_WR_RSP_PROC_ASSOC	6
2105 #define	M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
2106 #define	V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2107 #define	G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
2108 	(((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2109 #define	F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2110 
2111 #define	S_FW_RDEV_WR_IMAGE_PAIR		5
2112 #define	M_FW_RDEV_WR_IMAGE_PAIR		0x1
2113 #define	V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2114 #define	G_FW_RDEV_WR_IMAGE_PAIR(x)	\
2115 	(((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2116 #define	F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
2117 
2118 #define	S_FW_RDEV_WR_ACC_RSP_CODE	0
2119 #define	M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
2120 #define	V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2121 #define	G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
2122 	(((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2123 
2124 #define	S_FW_RDEV_WR_ENH_DISC		7
2125 #define	M_FW_RDEV_WR_ENH_DISC		0x1
2126 #define	V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
2127 #define	G_FW_RDEV_WR_ENH_DISC(x)	\
2128 	(((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2129 #define	F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
2130 
2131 #define	S_FW_RDEV_WR_REC	6
2132 #define	M_FW_RDEV_WR_REC	0x1
2133 #define	V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
2134 #define	G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2135 #define	F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
2136 
2137 #define	S_FW_RDEV_WR_TASK_RETRY_ID	5
2138 #define	M_FW_RDEV_WR_TASK_RETRY_ID	0x1
2139 #define	V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2140 #define	G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
2141 	(((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2142 #define	F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2143 
2144 #define	S_FW_RDEV_WR_RETRY	4
2145 #define	M_FW_RDEV_WR_RETRY	0x1
2146 #define	V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
2147 #define	G_FW_RDEV_WR_RETRY(x)	\
2148 	(((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2149 #define	F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
2150 
2151 #define	S_FW_RDEV_WR_CONF_CMPL		3
2152 #define	M_FW_RDEV_WR_CONF_CMPL		0x1
2153 #define	V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
2154 #define	G_FW_RDEV_WR_CONF_CMPL(x)	\
2155 	(((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2156 #define	F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
2157 
2158 #define	S_FW_RDEV_WR_DATA_OVLY		2
2159 #define	M_FW_RDEV_WR_DATA_OVLY		0x1
2160 #define	V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
2161 #define	G_FW_RDEV_WR_DATA_OVLY(x)	\
2162 	(((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2163 #define	F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
2164 
2165 #define	S_FW_RDEV_WR_INI	1
2166 #define	M_FW_RDEV_WR_INI	0x1
2167 #define	V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
2168 #define	G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2169 #define	F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
2170 
2171 #define	S_FW_RDEV_WR_TGT	0
2172 #define	M_FW_RDEV_WR_TGT	0x1
2173 #define	V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
2174 #define	G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2175 #define	F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
2176 
2177 struct fw_foiscsi_node_wr {
2178 	__be32 op_to_immdlen;
2179 	__be32 flowid_len16;
2180 	__u64  cookie;
2181 	__u8   subop;
2182 	__u8   status;
2183 	__u8   alias_len;
2184 	__u8   iqn_len;
2185 	__be32 node_flowid;
2186 	__be16 nodeid;
2187 	__be16 login_retry;
2188 	__be16 retry_timeout;
2189 	__be16 r3;
2190 	__u8   iqn[224];
2191 	__u8   alias[224];
2192 };
2193 
2194 #define	S_FW_FOISCSI_NODE_WR_IMMDLEN	0
2195 #define	M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
2196 #define	V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2197 #define	G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
2198 	(((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2199 
2200 struct fw_foiscsi_ctrl_wr {
2201 	__be32 op_compl;
2202 	__be32 flowid_len16;
2203 	__u64  cookie;
2204 	__u8   subop;
2205 	__u8   status;
2206 	__u8   ctrl_state;
2207 	__u8   io_state;
2208 	__be32 node_id;
2209 	__be32 ctrl_id;
2210 	__be32 io_id;
2211 	struct fw_foiscsi_sess_attr {
2212 		__be32 sess_type_to_erl;
2213 		__be16 max_conn;
2214 		__be16 max_r2t;
2215 		__be16 time2wait;
2216 		__be16 time2retain;
2217 		__be32 max_burst;
2218 		__be32 first_burst;
2219 		__be32 r1;
2220 	} sess_attr;
2221 	struct fw_foiscsi_conn_attr {
2222 		__be32 hdigest_to_ddp_pgsz;
2223 		__be32 max_rcv_dsl;
2224 		__be32 ping_tmo;
2225 		__be16 dst_port;
2226 		__be16 src_port;
2227 		union fw_foiscsi_conn_attr_addr {
2228 			struct fw_foiscsi_conn_attr_ipv6 {
2229 				__be64 dst_addr[2];
2230 				__be64 src_addr[2];
2231 			} ipv6_addr;
2232 			struct fw_foiscsi_conn_attr_ipv4 {
2233 				__be32 dst_addr;
2234 				__be32 src_addr;
2235 			} ipv4_addr;
2236 		} u;
2237 	} conn_attr;
2238 	__u8   tgt_name_len;
2239 	__u8   r3[7];
2240 	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2241 };
2242 
2243 #define	S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
2244 #define	M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
2245 #define	V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2246 	((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2247 #define	G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2248 	(((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \
2249 	M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2250 
2251 #define	S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
2252 #define	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
2253 #define	V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2254 	((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2255 #define	G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2256 	(((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2257 	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2258 #define	F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
2259     V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2260 
2261 #define	S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
2262 #define	M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
2263 #define	V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2264 	((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2265 #define	G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2266 	(((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2267 	M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2268 #define	F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
2269     V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2270 
2271 #define	S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
2272 #define	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
2273 #define	V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2274 	((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2275 #define	G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2276 	(((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2277 	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2278 #define	F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
2279     V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2280 
2281 #define	S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
2282 #define	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
2283 #define	V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2284 	((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2285 #define	G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2286 	(((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2287 	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2288 #define	F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
2289     V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2290 
2291 #define	S_FW_FOISCSI_CTRL_WR_ERL	24
2292 #define	M_FW_FOISCSI_CTRL_WR_ERL	0x3
2293 #define	V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2294 #define	G_FW_FOISCSI_CTRL_WR_ERL(x)	\
2295 	(((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2296 
2297 #define	S_FW_FOISCSI_CTRL_WR_HDIGEST	30
2298 #define	M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
2299 #define	V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2300 #define	G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
2301 	(((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2302 
2303 #define	S_FW_FOISCSI_CTRL_WR_DDIGEST	28
2304 #define	M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
2305 #define	V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2306 #define	G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
2307 	(((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2308 
2309 #define	S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
2310 #define	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
2311 #define	V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2312 	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2313 #define	G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2314 	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2315 	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2316 
2317 #define	S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
2318 #define	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
2319 #define	V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2320 	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2321 #define	G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2322 	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2323 	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2324 
2325 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
2326 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
2327 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2328     ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2329 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2330     (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2331 
2332 struct fw_foiscsi_chap_wr {
2333 	__be32 op_compl;
2334 	__be32 flowid_len16;
2335 	__u64  cookie;
2336 	__u8   status;
2337 	__u8   id_len;
2338 	__u8   sec_len;
2339 	__u8   node_type;
2340 	__be16 node_id;
2341 	__u8   r3[2];
2342 	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
2343 	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2344 };
2345 
2346 /*
2347  *	*****************************************
2348  *	  F O F C O E   W O R K R E Q U E S T s
2349  *	*****************************************
2350  */
2351 
2352 struct fw_fcoe_els_ct_wr {
2353 	__be32 op_immdlen;
2354 	__be32 flowid_len16;
2355 	__be64 cookie;
2356 	__be16 iqid;
2357 	__u8   tmo_val;
2358 	__u8   els_ct_type;
2359 	__u8   ctl_pri;
2360 	__u8   cp_en_class;
2361 	__be16 xfer_cnt;
2362 	__u8   fl_to_sp;
2363 	__u8   l_id[3];
2364 	__u8   r5;
2365 	__u8   r_id[3];
2366 	__be64 rsp_dmaaddr;
2367 	__be32 rsp_dmalen;
2368 	__be32 r6;
2369 };
2370 
2371 #define	S_FW_FCOE_ELS_CT_WR_OPCODE	24
2372 #define	M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
2373 #define	V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2374 #define	G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
2375 	(((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2376 
2377 #define	S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
2378 #define	M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
2379 #define	V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2380 #define	G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
2381 	(((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2382 
2383 #define	S_FW_FCOE_ELS_CT_WR_FLOWID	8
2384 #define	M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
2385 #define	V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2386 #define	G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
2387 	(((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2388 
2389 #define	S_FW_FCOE_ELS_CT_WR_LEN16	0
2390 #define	M_FW_FCOE_ELS_CT_WR_LEN16	0xff
2391 #define	V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2392 #define	G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
2393 	(((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2394 
2395 #define	S_FW_FCOE_ELS_CT_WR_CP_EN	6
2396 #define	M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
2397 #define	V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2398 #define	G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
2399 	(((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2400 
2401 #define	S_FW_FCOE_ELS_CT_WR_CLASS	4
2402 #define	M_FW_FCOE_ELS_CT_WR_CLASS	0x3
2403 #define	V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2404 #define	G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
2405 	(((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2406 
2407 #define	S_FW_FCOE_ELS_CT_WR_FL		2
2408 #define	M_FW_FCOE_ELS_CT_WR_FL		0x1
2409 #define	V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
2410 #define	G_FW_FCOE_ELS_CT_WR_FL(x)	\
2411 	(((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2412 #define	F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
2413 
2414 #define	S_FW_FCOE_ELS_CT_WR_NPIV	1
2415 #define	M_FW_FCOE_ELS_CT_WR_NPIV	0x1
2416 #define	V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2417 #define	G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
2418 	(((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2419 #define	F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2420 
2421 #define	S_FW_FCOE_ELS_CT_WR_SP		0
2422 #define	M_FW_FCOE_ELS_CT_WR_SP		0x1
2423 #define	V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
2424 #define	G_FW_FCOE_ELS_CT_WR_SP(x)	\
2425 	(((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2426 #define	F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
2427 
2428 /*
2429  *	****************************************
2430  *	  S C S I   W O R K R E Q U E S T s
2431  *	  (FOiSCSI and FCOE unified data path)
2432  *	****************************************
2433  */
2434 
2435 struct fw_scsi_write_wr {
2436 	__be32 op_immdlen;
2437 	__be32 flowid_len16;
2438 	__be64 cookie;
2439 	__be16 iqid;
2440 	__u8   tmo_val;
2441 	__u8   use_xfer_cnt;
2442 	union fw_scsi_write_priv {
2443 		struct fcoe_write_priv {
2444 			__u8   ctl_pri;
2445 			__u8   cp_en_class;
2446 			__u8   r3_lo[2];
2447 		} fcoe;
2448 		struct iscsi_write_priv {
2449 			__u8   r3[4];
2450 		} iscsi;
2451 	} u;
2452 	__be32 xfer_cnt;
2453 	__be32 ini_xfer_cnt;
2454 	__be64 rsp_dmaaddr;
2455 	__be32 rsp_dmalen;
2456 	__be32 r4;
2457 };
2458 
2459 #define	S_FW_SCSI_WRITE_WR_OPCODE	24
2460 #define	M_FW_SCSI_WRITE_WR_OPCODE	0xff
2461 #define	V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2462 #define	G_FW_SCSI_WRITE_WR_OPCODE(x)	\
2463 	(((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2464 
2465 #define	S_FW_SCSI_WRITE_WR_IMMDLEN	0
2466 #define	M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
2467 #define	V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2468 #define	G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
2469 	(((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2470 
2471 #define	S_FW_SCSI_WRITE_WR_FLOWID	8
2472 #define	M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
2473 #define	V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2474 #define	G_FW_SCSI_WRITE_WR_FLOWID(x)	\
2475 	(((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2476 
2477 #define	S_FW_SCSI_WRITE_WR_LEN16	0
2478 #define	M_FW_SCSI_WRITE_WR_LEN16	0xff
2479 #define	V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
2480 #define	G_FW_SCSI_WRITE_WR_LEN16(x)	\
2481 	(((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2482 
2483 #define	S_FW_SCSI_WRITE_WR_CP_EN	6
2484 #define	M_FW_SCSI_WRITE_WR_CP_EN	0x3
2485 #define	V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2486 #define	G_FW_SCSI_WRITE_WR_CP_EN(x)	\
2487 	(((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2488 
2489 #define	S_FW_SCSI_WRITE_WR_CLASS	4
2490 #define	M_FW_SCSI_WRITE_WR_CLASS	0x3
2491 #define	V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
2492 #define	G_FW_SCSI_WRITE_WR_CLASS(x)	\
2493 	(((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2494 
2495 struct fw_scsi_read_wr {
2496 	__be32 op_immdlen;
2497 	__be32 flowid_len16;
2498 	__be64 cookie;
2499 	__be16 iqid;
2500 	__u8   tmo_val;
2501 	__u8   use_xfer_cnt;
2502 	union fw_scsi_read_priv {
2503 		struct fcoe_read_priv {
2504 			__u8   ctl_pri;
2505 			__u8   cp_en_class;
2506 			__u8   r3_lo[2];
2507 		} fcoe;
2508 		struct iscsi_read_priv {
2509 			__u8   r3[4];
2510 		} iscsi;
2511 	} u;
2512 	__be32 xfer_cnt;
2513 	__be32 ini_xfer_cnt;
2514 	__be64 rsp_dmaaddr;
2515 	__be32 rsp_dmalen;
2516 	__be32 r4;
2517 };
2518 
2519 #define	S_FW_SCSI_READ_WR_OPCODE	24
2520 #define	M_FW_SCSI_READ_WR_OPCODE	0xff
2521 #define	V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
2522 #define	G_FW_SCSI_READ_WR_OPCODE(x)	\
2523 	(((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2524 
2525 #define	S_FW_SCSI_READ_WR_IMMDLEN	0
2526 #define	M_FW_SCSI_READ_WR_IMMDLEN	0xff
2527 #define	V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2528 #define	G_FW_SCSI_READ_WR_IMMDLEN(x)	\
2529 	(((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2530 
2531 #define	S_FW_SCSI_READ_WR_FLOWID	8
2532 #define	M_FW_SCSI_READ_WR_FLOWID	0xfffff
2533 #define	V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
2534 #define	G_FW_SCSI_READ_WR_FLOWID(x)	\
2535 	(((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2536 
2537 #define	S_FW_SCSI_READ_WR_LEN16		0
2538 #define	M_FW_SCSI_READ_WR_LEN16		0xff
2539 #define	V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
2540 #define	G_FW_SCSI_READ_WR_LEN16(x)	\
2541 	(((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2542 
2543 #define	S_FW_SCSI_READ_WR_CP_EN		6
2544 #define	M_FW_SCSI_READ_WR_CP_EN		0x3
2545 #define	V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
2546 #define	G_FW_SCSI_READ_WR_CP_EN(x)	\
2547 	(((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
2548 
2549 #define	S_FW_SCSI_READ_WR_CLASS		4
2550 #define	M_FW_SCSI_READ_WR_CLASS		0x3
2551 #define	V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
2552 #define	G_FW_SCSI_READ_WR_CLASS(x)	\
2553 	(((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
2554 
2555 struct fw_scsi_cmd_wr {
2556 	__be32 op_immdlen;
2557 	__be32 flowid_len16;
2558 	__be64 cookie;
2559 	__be16 iqid;
2560 	__u8   tmo_val;
2561 	__u8   r3;
2562 	union fw_scsi_cmd_priv {
2563 		struct fcoe_cmd_priv {
2564 			__u8   ctl_pri;
2565 			__u8   cp_en_class;
2566 			__u8   r4_lo[2];
2567 		} fcoe;
2568 		struct iscsi_cmd_priv {
2569 			__u8   r4[4];
2570 		} iscsi;
2571 	} u;
2572 	__u8   r5[8];
2573 	__be64 rsp_dmaaddr;
2574 	__be32 rsp_dmalen;
2575 	__be32 r6;
2576 };
2577 
2578 #define	S_FW_SCSI_CMD_WR_OPCODE		24
2579 #define	M_FW_SCSI_CMD_WR_OPCODE		0xff
2580 #define	V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
2581 #define	G_FW_SCSI_CMD_WR_OPCODE(x)	\
2582 	(((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
2583 
2584 #define	S_FW_SCSI_CMD_WR_IMMDLEN	0
2585 #define	M_FW_SCSI_CMD_WR_IMMDLEN	0xff
2586 #define	V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
2587 #define	G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
2588 	(((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
2589 
2590 #define	S_FW_SCSI_CMD_WR_FLOWID		8
2591 #define	M_FW_SCSI_CMD_WR_FLOWID		0xfffff
2592 #define	V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
2593 #define	G_FW_SCSI_CMD_WR_FLOWID(x)	\
2594 	(((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
2595 
2596 #define	S_FW_SCSI_CMD_WR_LEN16		0
2597 #define	M_FW_SCSI_CMD_WR_LEN16		0xff
2598 #define	V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
2599 #define	G_FW_SCSI_CMD_WR_LEN16(x)	\
2600 	(((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
2601 
2602 #define	S_FW_SCSI_CMD_WR_CP_EN		6
2603 #define	M_FW_SCSI_CMD_WR_CP_EN		0x3
2604 #define	V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
2605 #define	G_FW_SCSI_CMD_WR_CP_EN(x)	\
2606 	(((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
2607 
2608 #define	S_FW_SCSI_CMD_WR_CLASS		4
2609 #define	M_FW_SCSI_CMD_WR_CLASS		0x3
2610 #define	V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
2611 #define	G_FW_SCSI_CMD_WR_CLASS(x)	\
2612 	(((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
2613 
2614 struct fw_scsi_abrt_cls_wr {
2615 	__be32 op_immdlen;
2616 	__be32 flowid_len16;
2617 	__be64 cookie;
2618 	__be16 iqid;
2619 	__u8   tmo_val;
2620 	__u8   sub_opcode_to_chk_all_io;
2621 	__u8   r3[4];
2622 	__be64 t_cookie;
2623 };
2624 
2625 #define	S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
2626 #define	M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
2627 #define	V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
2628 #define	G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
2629 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
2630 
2631 #define	S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
2632 #define	M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
2633 #define	V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
2634 	((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2635 #define	G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
2636 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
2637 
2638 #define	S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
2639 #define	M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
2640 #define	V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
2641 #define	G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
2642 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
2643 
2644 #define	S_FW_SCSI_ABRT_CLS_WR_LEN16	0
2645 #define	M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
2646 #define	V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
2647 #define	G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
2648 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
2649 
2650 #define	S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
2651 #define	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
2652 #define	V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
2653 	((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2654 #define	G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
2655 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
2656 	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
2657 
2658 #define	S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
2659 #define	M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
2660 #define	V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
2661 #define	G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
2662 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
2663 #define	F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
2664 
2665 #define	S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
2666 #define	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
2667 #define	V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
2668 	((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2669 #define	G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
2670 	(((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
2671 	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
2672 #define	F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
2673     V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
2674 
2675 struct fw_scsi_tgt_acc_wr {
2676 	__be32 op_immdlen;
2677 	__be32 flowid_len16;
2678 	__be64 cookie;
2679 	__be16 iqid;
2680 	__u8   r3;
2681 	__u8   use_burst_len;
2682 	union fw_scsi_tgt_acc_priv {
2683 		struct fcoe_tgt_acc_priv {
2684 			__u8   ctl_pri;
2685 			__u8   cp_en_class;
2686 			__u8   r4_lo[2];
2687 		} fcoe;
2688 		struct iscsi_tgt_acc_priv {
2689 			__u8   r4[4];
2690 		} iscsi;
2691 	} u;
2692 	__be32 burst_len;
2693 	__be32 rel_off;
2694 	__be64 r5;
2695 	__be32 r6;
2696 	__be32 tot_xfer_len;
2697 };
2698 
2699 #define	S_FW_SCSI_TGT_ACC_WR_OPCODE	24
2700 #define	M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
2701 #define	V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
2702 #define	G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
2703 	(((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
2704 
2705 #define	S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
2706 #define	M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
2707 #define	V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2708 #define	G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
2709 	(((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
2710 
2711 #define	S_FW_SCSI_TGT_ACC_WR_FLOWID	8
2712 #define	M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
2713 #define	V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
2714 #define	G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
2715 	(((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
2716 
2717 #define	S_FW_SCSI_TGT_ACC_WR_LEN16	0
2718 #define	M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
2719 #define	V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
2720 #define	G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
2721 	(((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
2722 
2723 #define	S_FW_SCSI_TGT_ACC_WR_CP_EN	6
2724 #define	M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
2725 #define	V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
2726 #define	G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
2727 	(((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
2728 
2729 #define	S_FW_SCSI_TGT_ACC_WR_CLASS	4
2730 #define	M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
2731 #define	V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
2732 #define	G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
2733 	(((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
2734 
2735 struct fw_scsi_tgt_xmit_wr {
2736 	__be32 op_immdlen;
2737 	__be32 flowid_len16;
2738 	__be64 cookie;
2739 	__be16 iqid;
2740 	__u8   auto_rsp;
2741 	__u8   use_xfer_cnt;
2742 	union fw_scsi_tgt_xmit_priv {
2743 		struct fcoe_tgt_xmit_priv {
2744 			__u8   ctl_pri;
2745 			__u8   cp_en_class;
2746 			__u8   r3_lo[2];
2747 		} fcoe;
2748 		struct iscsi_tgt_xmit_priv {
2749 			__u8   r3[4];
2750 		} iscsi;
2751 	} u;
2752 	__be32 xfer_cnt;
2753 	__be32 r4;
2754 	__be64 r5;
2755 	__be32 r6;
2756 	__be32 tot_xfer_len;
2757 };
2758 
2759 #define	S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
2760 #define	M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
2761 #define	V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
2762 #define	G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
2763 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
2764 
2765 #define	S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
2766 #define	M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
2767 #define	V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2768 	((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2769 #define	G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2770 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
2771 
2772 #define	S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
2773 #define	M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
2774 #define	V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
2775 #define	G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
2776 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
2777 
2778 #define	S_FW_SCSI_TGT_XMIT_WR_LEN16	0
2779 #define	M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
2780 #define	V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
2781 #define	G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
2782 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
2783 
2784 #define	S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
2785 #define	M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
2786 #define	V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
2787 #define	G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
2788 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
2789 
2790 #define	S_FW_SCSI_TGT_XMIT_WR_CLASS	4
2791 #define	M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
2792 #define	V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
2793 #define	G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
2794 	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
2795 
2796 struct fw_scsi_tgt_rsp_wr {
2797 	__be32 op_immdlen;
2798 	__be32 flowid_len16;
2799 	__be64 cookie;
2800 	__be16 iqid;
2801 	__u8   r3[2];
2802 	union fw_scsi_tgt_rsp_priv {
2803 		struct fcoe_tgt_rsp_priv {
2804 			__u8   ctl_pri;
2805 			__u8   cp_en_class;
2806 			__u8   r4_lo[2];
2807 		} fcoe;
2808 		struct iscsi_tgt_rsp_priv {
2809 			__u8   r4[4];
2810 		} iscsi;
2811 	} u;
2812 	__u8   r5[8];
2813 };
2814 
2815 #define	S_FW_SCSI_TGT_RSP_WR_OPCODE	24
2816 #define	M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
2817 #define	V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
2818 #define	G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
2819 	(((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
2820 
2821 #define	S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
2822 #define	M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
2823 #define	V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2824 #define	G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
2825 	(((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
2826 
2827 #define	S_FW_SCSI_TGT_RSP_WR_FLOWID	8
2828 #define	M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
2829 #define	V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
2830 #define	G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
2831 	(((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
2832 
2833 #define	S_FW_SCSI_TGT_RSP_WR_LEN16	0
2834 #define	M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
2835 #define	V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
2836 #define	G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
2837 	(((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
2838 
2839 #define	S_FW_SCSI_TGT_RSP_WR_CP_EN	6
2840 #define	M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
2841 #define	V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
2842 #define	G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
2843 	(((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
2844 
2845 #define	S_FW_SCSI_TGT_RSP_WR_CLASS	4
2846 #define	M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
2847 #define	V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
2848 #define	G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
2849 	(((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
2850 
2851 struct fw_pofcoe_tcb_wr {
2852 	__be32 op_compl;
2853 	__be32 equiq_to_len16;
2854 	__be64 cookie;
2855 	__be32 tid_to_port;
2856 	__be16 x_id;
2857 	__be16 vlan_id;
2858 	__be32 s_id;
2859 	__be32 d_id;
2860 	__be32 tag;
2861 	__be32 xfer_len;
2862 	__be32 r4;
2863 	__be16 r5;
2864 	__be16 iqid;
2865 };
2866 
2867 #define S_FW_POFCOE_TCB_WR_TID		12
2868 #define M_FW_POFCOE_TCB_WR_TID		0xfffff
2869 #define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
2870 #define G_FW_POFCOE_TCB_WR_TID(x)	\
2871     (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
2872 
2873 #define S_FW_POFCOE_TCB_WR_ALLO		4
2874 #define M_FW_POFCOE_TCB_WR_ALLOC	0x1
2875 #define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
2876 #define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
2877     (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
2878 #define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
2879 
2880 #define S_FW_POFCOE_TCB_WR_FREE		3
2881 #define M_FW_POFCOE_TCB_WR_FREE		0x1
2882 #define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
2883 #define G_FW_POFCOE_TCB_WR_FREE(x)	\
2884     (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
2885 #define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
2886 
2887 #define S_FW_POFCOE_TCB_WR_PORT		0
2888 #define M_FW_POFCOE_TCB_WR_PORT		0x7
2889 #define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
2890 #define G_FW_POFCOE_TCB_WR_PORT(x)	\
2891     (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
2892 
2893 struct fw_pofcoe_ulptx_wr {
2894 	__be32 op_pkd;
2895 	__be32 equiq_to_len16;
2896 	__u64  cookie;
2897 };
2898 
2899 
2900 /*
2901  *	*******************
2902  *	  C O M M A N D s
2903  *	*******************
2904  */
2905 
2906 /*
2907  * The maximum length of time, in miliseconds, that we expect any firmware
2908  * command to take to execute and return a reply to the host.  The RESET
2909  * and INITIALIZE commands can take a fair amount of time to execute but
2910  * most execute in far less time than this maximum.  This constant is used
2911  * by host software to determine how long to wait for a firmware command
2912  * reply before declaring the firmware as dead/unreachable ...
2913  */
2914 #define	FW_CMD_MAX_TIMEOUT	10000
2915 
2916 /*
2917  * If a host driver does a HELLO and discovers that there's already a MASTER
2918  * selected, we may have to wait for that MASTER to finish issuing RESET,
2919  * configuration and INITIALIZE commands.  Also, there's a possibility that
2920  * our own HELLO may get lost if it happens right as the MASTER is issuign a
2921  * RESET command, so we need to be willing to make a few retries of our HELLO.
2922  */
2923 #define	FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
2924 #define	FW_CMD_HELLO_RETRIES	3
2925 
2926 enum fw_cmd_opcodes {
2927 	FW_LDST_CMD		= 0x01,
2928 	FW_RESET_CMD		= 0x03,
2929 	FW_HELLO_CMD		= 0x04,
2930 	FW_BYE_CMD		= 0x05,
2931 	FW_INITIALIZE_CMD	= 0x06,
2932 	FW_CAPS_CONFIG_CMD	= 0x07,
2933 	FW_PARAMS_CMD		= 0x08,
2934 	FW_PFVF_CMD		= 0x09,
2935 	FW_IQ_CMD		= 0x10,
2936 	FW_EQ_MNGT_CMD		= 0x11,
2937 	FW_EQ_ETH_CMD		= 0x12,
2938 	FW_EQ_CTRL_CMD		= 0x13,
2939 	FW_EQ_OFLD_CMD		= 0x21,
2940 	FW_VI_CMD		= 0x14,
2941 	FW_VI_MAC_CMD		= 0x15,
2942 	FW_VI_RXMODE_CMD	= 0x16,
2943 	FW_VI_ENABLE_CMD	= 0x17,
2944 	FW_VI_STATS_CMD		= 0x1a,
2945 	FW_ACL_MAC_CMD		= 0x18,
2946 	FW_ACL_VLAN_CMD		= 0x19,
2947 	FW_PORT_CMD		= 0x1b,
2948 	FW_PORT_STATS_CMD	= 0x1c,
2949 	FW_PORT_LB_STATS_CMD	= 0x1d,
2950 	FW_PORT_TRACE_CMD	= 0x1e,
2951 	FW_PORT_TRACE_MMAP_CMD	= 0x1f,
2952 	FW_RSS_IND_TBL_CMD	= 0x20,
2953 	FW_RSS_GLB_CONFIG_CMD	= 0x22,
2954 	FW_RSS_VI_CONFIG_CMD	= 0x23,
2955 	FW_SCHED_CMD		= 0x24,
2956 	FW_DEVLOG_CMD		= 0x25,
2957 	FW_WATCHDOG_CMD		= 0x27,
2958 	FW_CLIP_CMD		= 0x28,
2959 	FW_CHNET_IFACE_CMD	= 0x26,
2960 	FW_FCOE_RES_INFO_CMD	= 0x31,
2961 	FW_FCOE_LINK_CMD	= 0x32,
2962 	FW_FCOE_VNP_CMD		= 0x33,
2963 	FW_FCOE_SPARAMS_CMD	= 0x35,
2964 	FW_FCOE_STATS_CMD	= 0x37,
2965 	FW_FCOE_FCF_CMD		= 0x38,
2966 	FW_LASTC2E_CMD		= 0x40,
2967 	FW_ERROR_CMD		= 0x80,
2968 	FW_DEBUG_CMD		= 0x81,
2969 };
2970 
2971 enum fw_cmd_cap {
2972 	FW_CMD_CAP_PF		= 0x01,
2973 	FW_CMD_CAP_DMAQ		= 0x02,
2974 	FW_CMD_CAP_PORT		= 0x04,
2975 	FW_CMD_CAP_PORTPROMISC	= 0x08,
2976 	FW_CMD_CAP_PORTSTATS	= 0x10,
2977 	FW_CMD_CAP_VF		= 0x80,
2978 };
2979 
2980 /*
2981  * Generic command header flit0
2982  */
2983 struct fw_cmd_hdr {
2984 	__be32 hi;
2985 	__be32 lo;
2986 };
2987 
2988 #define	S_FW_CMD_OP		24
2989 #define	M_FW_CMD_OP		0xff
2990 #define	V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
2991 #define	G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
2992 
2993 #define	S_FW_CMD_REQUEST	23
2994 #define	M_FW_CMD_REQUEST	0x1
2995 #define	V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
2996 #define	G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
2997 #define	F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
2998 
2999 #define	S_FW_CMD_READ		22
3000 #define	M_FW_CMD_READ		0x1
3001 #define	V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
3002 #define	G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
3003 #define	F_FW_CMD_READ		V_FW_CMD_READ(1U)
3004 
3005 #define	S_FW_CMD_WRITE		21
3006 #define	M_FW_CMD_WRITE		0x1
3007 #define	V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
3008 #define	G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
3009 #define	F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
3010 
3011 #define	S_FW_CMD_EXEC		20
3012 #define	M_FW_CMD_EXEC		0x1
3013 #define	V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
3014 #define	G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
3015 #define	F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
3016 
3017 #define	S_FW_CMD_RAMASK		20
3018 #define	M_FW_CMD_RAMASK		0xf
3019 #define	V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
3020 #define	G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
3021 
3022 #define	S_FW_CMD_RETVAL		8
3023 #define	M_FW_CMD_RETVAL		0xff
3024 #define	V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
3025 #define	G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
3026 
3027 #define	S_FW_CMD_LEN16		0
3028 #define	M_FW_CMD_LEN16		0xff
3029 #define	V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
3030 #define	G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
3031 
3032 #define	FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16)
3033 
3034 /*
3035  *	address spaces
3036  */
3037 enum fw_ldst_addrspc {
3038 	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
3039 	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
3040 	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
3041 	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
3042 	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
3043 	FW_LDST_ADDRSPC_TP_PIO	  = 0x0010,
3044 	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
3045 	FW_LDST_ADDRSPC_TP_MIB	  = 0x0012,
3046 	FW_LDST_ADDRSPC_MDIO	  = 0x0018,
3047 	FW_LDST_ADDRSPC_MPS	  = 0x0020,
3048 	FW_LDST_ADDRSPC_FUNC	  = 0x0028,
3049 	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
3050 	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
3051 	FW_LDST_ADDRSPC_LE	  = 0x0030,
3052 	FW_LDST_ADDRSPC_I2C       = 0x0038,
3053 	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
3054 	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
3055 	FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,
3056 };
3057 
3058 /*
3059  *	MDIO VSC8634 register access control field
3060  */
3061 enum fw_ldst_mdio_vsc8634_aid {
3062 	FW_LDST_MDIO_VS_STANDARD,
3063 	FW_LDST_MDIO_VS_EXTENDED,
3064 	FW_LDST_MDIO_VS_GPIO
3065 };
3066 
3067 enum fw_ldst_mps_fid {
3068 	FW_LDST_MPS_ATRB,
3069 	FW_LDST_MPS_RPLC
3070 };
3071 
3072