xref: /illumos-gate/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h (revision de483253)

/*
 * This file and its contents are supplied under the terms of the
 * Common Development and Distribution License ("CDDL"), version 1.0.
 * You may only use this file in accordance with the terms of version
 * 1.0 of the CDDL.
 *
 * A full copy of the text of the CDDL should have accompanied this
 * source. A copy of the CDDL is also available via the Internet at
 * http://www.illumos.org/license/CDDL.
 */

/*
 * Chelsio Terminator 4 (T4) Firmware interface header file.
 *
 * Copyright (C) 2009-2013 Chelsio Communications.  All rights reserved.
 *
 * Written by felix marti (felix@chelsio.com)
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
 * release for licensing terms and conditions.
 */
#ifndef _T4FW_INTERFACE_H_
#define	_T4FW_INTERFACE_H_

/*
 *	******************************
 *	   R E T U R N   V A L U E S
 *	******************************
 */

enum fw_retval {
	FW_SUCCESS		= 0,	/* completed sucessfully */
	FW_EPERM		= 1,	/* operation not permitted */
	FW_ENOENT		= 2,	/* no such file or directory */
	FW_EIO			= 5,	/* input/output error; hw bad */
	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
	FW_EAGAIN		= 11,	/* try again */
	FW_ENOMEM		= 12,	/* out of memory */
	FW_EFAULT		= 14,	/* bad address; fw bad */
	FW_EBUSY		= 16,	/* resource busy */
	FW_EEXIST		= 17,	/* file exists */
	FW_ENODEV		= 19,	/* no such device */
	FW_EINVAL		= 22,	/* invalid argument */
	FW_ENOSPC		= 28,	/* no space left on device */
	FW_ENOSYS		= 38,	/* functionality not implemented */
	FW_ENODATA		= 61,	/* no data available */
	FW_EPROTO		= 71,	/* protocol error */
	FW_EADDRINUSE		= 98,	/* address already in use */
	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
	FW_ENETDOWN		= 100,	/* network is down */
	FW_ENETUNREACH		= 101,	/* network is unreachable */
	FW_ENOBUFS		= 105,	/* no buffer space available */
	FW_ETIMEDOUT		= 110,	/* timeout */
	FW_EINPROGRESS		= 115,	/* fw internal */
	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
	FW_SCSI_ABORTED		= 130,	/* */
	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
	FW_ERR_LINK_DOWN	= 132,	/* */
	FW_RDEV_NOT_READY	= 133,	/* */
	FW_ERR_RDEV_LOST	= 134,	/* */
	FW_ERR_RDEV_LOGO	= 135,	/* */
	FW_FCOE_NO_XCHG		= 136,	/* */
	FW_SCSI_RSP_ERR		= 137,	/* */
	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
	FW_SCSI_DDP_ERR		= 141,	/* DDP error */
	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
};

/*
 *	******************************
 *	   W O R K   R E Q U E S T s
 *	******************************
 */

enum fw_wr_opcodes {
	FW_FRAG_WR		= 0x1d,
	FW_FILTER_WR		= 0x02,
	FW_ULPTX_WR		= 0x04,
	FW_TP_WR		= 0x05,
	FW_ETH_TX_PKT_WR	= 0x08,
	FW_ETH_TX_PKT2_WR	= 0x44,
	FW_ETH_TX_PKTS_WR	= 0x09,
	FW_ETH_TX_UO_WR		= 0x1c,
	FW_EQ_FLUSH_WR		= 0x1b,
	FW_OFLD_CONNECTION_WR	= 0x2f,
	FW_FLOWC_WR		= 0x0a,
	FW_OFLD_TX_DATA_WR	= 0x0b,
	FW_CMD_WR		= 0x10,
	FW_ETH_TX_PKT_VM_WR	= 0x11,
	FW_RI_RES_WR		= 0x0c,
	FW_RI_RDMA_WRITE_WR	= 0x14,
	FW_RI_SEND_WR		= 0x15,
	FW_RI_RDMA_READ_WR	= 0x16,
	FW_RI_RECV_WR		= 0x17,
	FW_RI_BIND_MW_WR	= 0x18,
	FW_RI_FR_NSMR_WR	= 0x19,
	FW_RI_INV_LSTAG_WR	= 0x1a,
	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
	FW_RI_ATOMIC_WR		= 0x16,
	FW_RI_WR		= 0x0d,
	FW_CHNET_IFCONF_WR	= 0x6b,
	FW_RDEV_WR		= 0x38,
	FW_FOISCSI_NODE_WR	= 0x60,
	FW_FOISCSI_CTRL_WR	= 0x6a,
	FW_FOISCSI_CHAP_WR	= 0x6c,
	FW_FCOE_ELS_CT_WR	= 0x30,
	FW_SCSI_WRITE_WR	= 0x31,
	FW_SCSI_READ_WR		= 0x32,
	FW_SCSI_CMD_WR		= 0x33,
	FW_SCSI_ABRT_CLS_WR	= 0x34,
	FW_SCSI_TGT_ACC_WR	= 0x35,
	FW_SCSI_TGT_XMIT_WR	= 0x36,
	FW_SCSI_TGT_RSP_WR	= 0x37,
	FW_POFCOE_TCB_WR	= 0x42,
	FW_POFCOE_ULPTX_WR	= 0x43,
	FW_LASTC2E_WR		= 0x70
};

/*
 * Generic work request header flit0
 */
struct fw_wr_hdr {
	__be32 hi;
	__be32 lo;
};

/* work request opcode (hi) */
#define	S_FW_WR_OP		24
#define	M_FW_WR_OP		0xff
#define	V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
#define	G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)

/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
#define	S_FW_WR_ATOMIC		23
#define	M_FW_WR_ATOMIC		0x1
#define	V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
#define	G_FW_WR_ATOMIC(x)	\
	(((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
#define	F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)

/*
 *	flush flag (hi) - firmware flushes flushable work request buffered
 *	in the flow context.
 */
#define	S_FW_WR_FLUSH	22
#define	M_FW_WR_FLUSH	0x1
#define	V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
#define	G_FW_WR_FLUSH(x)  \
	(((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
#define	F_FW_WR_FLUSH	V_FW_WR_FLUSH(1U)

/* completion flag (hi) - firmware generates a cpl_fw6_ack */
#define	S_FW_WR_COMPL	21
#define	M_FW_WR_COMPL	0x1
#define	V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
#define	G_FW_WR_COMPL(x)  \
	(((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
#define	F_FW_WR_COMPL	V_FW_WR_COMPL(1U)

/* work request immediate data lengh (hi) */
#define	S_FW_WR_IMMDLEN	0
#define	M_FW_WR_IMMDLEN	0xff
#define	V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
#define	G_FW_WR_IMMDLEN(x)	\
	(((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)

/* egress queue status update to associated ingress queue entry (lo) */
#define	S_FW_WR_EQUIQ		31
#define	M_FW_WR_EQUIQ		0x1
#define	V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
#define	G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
#define	F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)

/* egress queue status update to egress queue status entry (lo) */
#define	S_FW_WR_EQUEQ		30
#define	M_FW_WR_EQUEQ		0x1
#define	V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
#define	G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
#define	F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)

/* flow context identifier (lo) */
#define	S_FW_WR_FLOWID		8
#define	M_FW_WR_FLOWID		0xfffff
#define	V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
#define	G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)

/* length in units of 16-bytes (lo) */
#define	S_FW_WR_LEN16		0
#define	M_FW_WR_LEN16		0xff
#define	V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
#define	G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)

struct fw_frag_wr {
	__be32 op_to_fragoff16;
	__be32 flowid_len16;
	__be64 r4;
};

#define S_FW_FRAG_WR_EOF	15
#define M_FW_FRAG_WR_EOF	0x1
#define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
#define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
#define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)

#define S_FW_FRAG_WR_FRAGOFF16		8
#define M_FW_FRAG_WR_FRAGOFF16		0x7f
#define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
#define G_FW_FRAG_WR_FRAGOFF16(x)	\
    (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)

/*
 * valid filter configurations for compressed tuple
 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
 * OV - Outer VLAN/VNIC_ID,
 */
#define	HW_TPL_FR_MT_M_E_P_FC		0x3C3
#define	HW_TPL_FR_MT_M_PR_T_FC		0x3B3
#define	HW_TPL_FR_MT_M_IV_P_FC		0x38B
#define	HW_TPL_FR_MT_M_OV_P_FC		0x387
#define	HW_TPL_FR_MT_E_PR_T		0x370
#define	HW_TPL_FR_MT_E_PR_P_FC		0X363
#define	HW_TPL_FR_MT_E_T_P_FC		0X353
#define	HW_TPL_FR_MT_PR_IV_P_FC		0X32B
#define	HW_TPL_FR_MT_PR_OV_P_FC		0X327
#define	HW_TPL_FR_MT_T_IV_P_FC		0X31B
#define	HW_TPL_FR_MT_T_OV_P_FC		0X317
#define	HW_TPL_FR_M_E_PR_FC		0X2E1
#define	HW_TPL_FR_M_E_T_FC		0X2D1
#define	HW_TPL_FR_M_PR_IV_FC		0X2A9
#define	HW_TPL_FR_M_PR_OV_FC		0X2A5
#define	HW_TPL_FR_M_T_IV_FC		0X299
#define	HW_TPL_FR_M_T_OV_FC		0X295
#define	HW_TPL_FR_E_PR_T_P		0X272
#define	HW_TPL_FR_E_PR_T_FC		0X271
#define	HW_TPL_FR_E_IV_FC		0X249
#define	HW_TPL_FR_E_OV_FC		0X245
#define	HW_TPL_FR_PR_T_IV_FC		0X239
#define	HW_TPL_FR_PR_T_OV_FC		0X235
#define	HW_TPL_FR_IV_OV_FC		0X20D
#define	HW_TPL_MT_M_E_PR		0X1E0
#define	HW_TPL_MT_M_E_T			0X1D0
#define	HW_TPL_MT_E_PR_T_FC		0X171
#define	HW_TPL_MT_E_IV			0X148
#define	HW_TPL_MT_E_OV			0X144
#define	HW_TPL_MT_PR_T_IV		0X138
#define	HW_TPL_MT_PR_T_OV		0X134
#define	HW_TPL_M_E_PR_P			0X0E2
#define	HW_TPL_M_E_T_P			0X0D2
#define	HW_TPL_E_PR_T_P_FC		0X073
#define	HW_TPL_E_IV_P			0X04A
#define	HW_TPL_E_OV_P			0X046
#define	HW_TPL_PR_T_IV_P		0X03A
#define	HW_TPL_PR_T_OV_P		0X036

/* filter wr reply code in cookie in CPL_SET_TCB_RPL */
enum fw_filter_wr_cookie {
	FW_FILTER_WR_SUCCESS,
	FW_FILTER_WR_FLT_ADDED,
	FW_FILTER_WR_FLT_DELETED,
	FW_FILTER_WR_SMT_TBL_FULL,
	FW_FILTER_WR_EINVAL,
};

struct fw_filter_wr {
	__be32 op_pkd;
	__be32 len16_pkd;
	__be64 r3;
	__be32 tid_to_iq;
	__be32 del_filter_to_l2tix;
	__be16 ethtype;
	__be16 ethtypem;
	__u8   frag_to_ovlan_vldm;
	__u8   smac_sel;
	__be16 rx_chan_rx_rpl_iq;
	__be32 maci_to_matchtypem;
	__u8   ptcl;
	__u8   ptclm;
	__u8   ttyp;
	__u8   ttypm;
	__be16 ivlan;
	__be16 ivlanm;
	__be16 ovlan;
	__be16 ovlanm;
	__u8   lip[16];
	__u8   lipm[16];
	__u8   fip[16];
	__u8   fipm[16];
	__be16 lp;
	__be16 lpm;
	__be16 fp;
	__be16 fpm;
	__be16 r7;
	__u8   sma[6];
};

#define	S_FW_FILTER_WR_TID	12
#define	M_FW_FILTER_WR_TID	0xfffff
#define	V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
#define	G_FW_FILTER_WR_TID(x)	\
	(((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)

#define	S_FW_FILTER_WR_RQTYPE		11
#define	M_FW_FILTER_WR_RQTYPE		0x1
#define	V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
#define	G_FW_FILTER_WR_RQTYPE(x)	\
	(((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
#define	F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)

#define	S_FW_FILTER_WR_NOREPLY		10
#define	M_FW_FILTER_WR_NOREPLY		0x1
#define	V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
#define	G_FW_FILTER_WR_NOREPLY(x)	\
	(((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
#define	F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)

#define	S_FW_FILTER_WR_IQ	0
#define	M_FW_FILTER_WR_IQ	0x3ff
#define	V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
#define	G_FW_FILTER_WR_IQ(x)	\
	(((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)

#define	S_FW_FILTER_WR_DEL_FILTER	31
#define	M_FW_FILTER_WR_DEL_FILTER	0x1
#define	V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
#define	G_FW_FILTER_WR_DEL_FILTER(x)	\
	(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
#define	F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)

#define	S_FW_FILTER_WR_RPTTID		25
#define	M_FW_FILTER_WR_RPTTID		0x1
#define	V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
#define	G_FW_FILTER_WR_RPTTID(x)	\
	(((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
#define	F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)

#define	S_FW_FILTER_WR_DROP	24
#define	M_FW_FILTER_WR_DROP	0x1
#define	V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
#define	G_FW_FILTER_WR_DROP(x)	\
	(((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
#define	F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)

#define	S_FW_FILTER_WR_DIRSTEER		23
#define	M_FW_FILTER_WR_DIRSTEER		0x1
#define	V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
#define	G_FW_FILTER_WR_DIRSTEER(x)	\
	(((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
#define	F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)

#define	S_FW_FILTER_WR_MASKHASH		22
#define	M_FW_FILTER_WR_MASKHASH		0x1
#define	V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
#define	G_FW_FILTER_WR_MASKHASH(x)	\
	(((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
#define	F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)

#define	S_FW_FILTER_WR_DIRSTEERHASH	21
#define	M_FW_FILTER_WR_DIRSTEERHASH	0x1
#define	V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
#define	G_FW_FILTER_WR_DIRSTEERHASH(x)	\
	(((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
#define	F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)

#define	S_FW_FILTER_WR_LPBK	20
#define	M_FW_FILTER_WR_LPBK	0x1
#define	V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
#define	G_FW_FILTER_WR_LPBK(x)	\
	(((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
#define	F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)

#define	S_FW_FILTER_WR_DMAC	19
#define	M_FW_FILTER_WR_DMAC	0x1
#define	V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
#define	G_FW_FILTER_WR_DMAC(x)	\
	(((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
#define	F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)

#define	S_FW_FILTER_WR_SMAC	18
#define	M_FW_FILTER_WR_SMAC	0x1
#define	V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
#define	G_FW_FILTER_WR_SMAC(x)	\
	(((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
#define	F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)

#define	S_FW_FILTER_WR_INSVLAN		17
#define	M_FW_FILTER_WR_INSVLAN		0x1
#define	V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
#define	G_FW_FILTER_WR_INSVLAN(x)	\
	(((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
#define	F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)

#define	S_FW_FILTER_WR_RMVLAN		16
#define	M_FW_FILTER_WR_RMVLAN		0x1
#define	V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
#define	G_FW_FILTER_WR_RMVLAN(x)	\
	(((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
#define	F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)

#define	S_FW_FILTER_WR_HITCNTS		15
#define	M_FW_FILTER_WR_HITCNTS		0x1
#define	V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
#define	G_FW_FILTER_WR_HITCNTS(x)	\
	(((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
#define	F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)

#define	S_FW_FILTER_WR_TXCHAN		13
#define	M_FW_FILTER_WR_TXCHAN		0x3
#define	V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
#define	G_FW_FILTER_WR_TXCHAN(x)	\
	(((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)

#define	S_FW_FILTER_WR_PRIO	12
#define	M_FW_FILTER_WR_PRIO	0x1
#define	V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
#define	G_FW_FILTER_WR_PRIO(x)	\
	(((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
#define	F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)

#define	S_FW_FILTER_WR_L2TIX	0
#define	M_FW_FILTER_WR_L2TIX	0xfff
#define	V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
#define	G_FW_FILTER_WR_L2TIX(x)	\
	(((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)

#define	S_FW_FILTER_WR_FRAG	7
#define	M_FW_FILTER_WR_FRAG	0x1
#define	V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
#define	G_FW_FILTER_WR_FRAG(x)	\
	(((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
#define	F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)

#define	S_FW_FILTER_WR_FRAGM	6
#define	M_FW_FILTER_WR_FRAGM	0x1
#define	V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
#define	G_FW_FILTER_WR_FRAGM(x)	\
	(((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
#define	F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)

#define	S_FW_FILTER_WR_IVLAN_VLD	5
#define	M_FW_FILTER_WR_IVLAN_VLD	0x1
#define	V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
#define	G_FW_FILTER_WR_IVLAN_VLD(x)	\
	(((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
#define	F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)

#define	S_FW_FILTER_WR_OVLAN_VLD	4
#define	M_FW_FILTER_WR_OVLAN_VLD	0x1
#define	V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
#define	G_FW_FILTER_WR_OVLAN_VLD(x)	\
	(((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
#define	F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)

#define	S_FW_FILTER_WR_IVLAN_VLDM	3
#define	M_FW_FILTER_WR_IVLAN_VLDM	0x1
#define	V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
#define	G_FW_FILTER_WR_IVLAN_VLDM(x)	\
	(((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
#define	F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)

#define	S_FW_FILTER_WR_OVLAN_VLDM	2
#define	M_FW_FILTER_WR_OVLAN_VLDM	0x1
#define	V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
#define	G_FW_FILTER_WR_OVLAN_VLDM(x)	\
	(((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
#define	F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)

#define	S_FW_FILTER_WR_RX_CHAN		15
#define	M_FW_FILTER_WR_RX_CHAN		0x1
#define	V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
#define	G_FW_FILTER_WR_RX_CHAN(x)	\
	(((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
#define	F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)

#define	S_FW_FILTER_WR_RX_RPL_IQ	0
#define	M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
#define	V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
#define	G_FW_FILTER_WR_RX_RPL_IQ(x)	\
	(((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)

#define	S_FW_FILTER_WR_MACI	23
#define	M_FW_FILTER_WR_MACI	0x1ff
#define	V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
#define	G_FW_FILTER_WR_MACI(x)	\
	(((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)

#define	S_FW_FILTER_WR_MACIM	14
#define	M_FW_FILTER_WR_MACIM	0x1ff
#define	V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
#define	G_FW_FILTER_WR_MACIM(x)	\
	(((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)

#define	S_FW_FILTER_WR_FCOE	13
#define	M_FW_FILTER_WR_FCOE	0x1
#define	V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
#define	G_FW_FILTER_WR_FCOE(x)	\
	(((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
#define	F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)

#define	S_FW_FILTER_WR_FCOEM	12
#define	M_FW_FILTER_WR_FCOEM	0x1
#define	V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
#define	G_FW_FILTER_WR_FCOEM(x)	\
	(((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
#define	F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)

#define	S_FW_FILTER_WR_PORT	9
#define	M_FW_FILTER_WR_PORT	0x7
#define	V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
#define	G_FW_FILTER_WR_PORT(x)	\
	(((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)

#define	S_FW_FILTER_WR_PORTM	6
#define	M_FW_FILTER_WR_PORTM	0x7
#define	V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
#define	G_FW_FILTER_WR_PORTM(x)	\
	(((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)

#define	S_FW_FILTER_WR_MATCHTYPE	3
#define	M_FW_FILTER_WR_MATCHTYPE	0x7
#define	V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
#define	G_FW_FILTER_WR_MATCHTYPE(x)	\
	(((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)

#define	S_FW_FILTER_WR_MATCHTYPEM	0
#define	M_FW_FILTER_WR_MATCHTYPEM	0x7
#define	V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
#define	G_FW_FILTER_WR_MATCHTYPEM(x)	\
	(((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)

struct fw_ulptx_wr {
	__be32 op_to_compl;
	__be32 flowid_len16;
	__u64  cookie;
};

struct fw_tp_wr {
	__be32 op_to_immdlen;
	__be32 flowid_len16;
	__u64  cookie;
};

struct fw_eth_tx_pkt_wr {
	__be32 op_immdlen;
	__be32 equiq_to_len16;
	__be64 r3;
};

#define	S_FW_ETH_TX_PKT_WR_IMMDLEN	0
#define	M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
#define	V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
#define	G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
	(((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)

struct fw_eth_tx_pkt2_wr {
	__be32 op_immdlen;
	__be32 equiq_to_len16;
	__be32 r3;
	__be32 L4ChkDisable_to_IpHdrLen;
};

#define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
#define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)

#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
    ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
     M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
    V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)

#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
    ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
     M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
    V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)

#define S_FW_ETH_TX_PKT2_WR_IVLAN	28
#define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
#define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
#define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
#define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)

#define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
#define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)

#define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
#define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)

#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
    (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)

struct fw_eth_tx_pkts_wr {
	__be32 op_pkd;
	__be32 equiq_to_len16;
	__be32 r3;
	__be16 plen;
	__u8   npkt;
	__u8   type;
};

struct fw_eth_tx_uo_wr {
	__be32 op_immdlen;
	__be32 equiq_to_len16;
	__be64 r3;
	__u8   r4;
	__u8   ethlen;
	__be16 iplen;
	__u8   udplen;
	__u8   rtplen;
	__be16 r5;
	__be16 mss;
	__be16 schedpktsize;
	__be32 length;
};

struct fw_eq_flush_wr {
	__u8   opcode;
	__u8   r1[3];
	__be32 equiq_to_len16;
	__be64 r3;
};

struct fw_ofld_connection_wr {
	__be32 op_compl;
	__be32 len16_pkd;
	__u64  cookie;
	__be64 r2;
	__be64 r3;
	struct fw_ofld_connection_le {
		__be32 version_cpl;
		__be32 filter;
		__be32 r1;
		__be16 lport;
		__be16 pport;
		union fw_ofld_connection_leip {
			struct fw_ofld_connection_le_ipv4 {
				__be32 pip;
				__be32 lip;
				__be64 r0;
				__be64 r1;
				__be64 r2;
			} ipv4;
			struct fw_ofld_connection_le_ipv6 {
				__be64 pip_hi;
				__be64 pip_lo;
				__be64 lip_hi;
				__be64 lip_lo;
			} ipv6;
		} u;
	} le;
	struct fw_ofld_connection_tcb {
		__be32 t_state_to_astid;
		__be16 cplrxdataack_cplpassacceptrpl;
		__be16 rcv_adv;
		__be32 rcv_nxt;
		__be32 tx_max;
		__be64 opt0;
		__be32 opt2;
		__be32 r1;
		__be64 r2;
		__be64 r3;
	} tcb;
};

#define	S_FW_OFLD_CONNECTION_WR_VERSION		31
#define	M_FW_OFLD_CONNECTION_WR_VERSION		0x1
#define	V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
#define	G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
	M_FW_OFLD_CONNECTION_WR_VERSION)
#define	F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)

#define	S_FW_OFLD_CONNECTION_WR_CPL	30
#define	M_FW_OFLD_CONNECTION_WR_CPL	0x1
#define	V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
#define	G_FW_OFLD_CONNECTION_WR_CPL(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
#define	F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)

#define	S_FW_OFLD_CONNECTION_WR_T_STATE		28
#define	M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
#define	V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
#define	G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
	M_FW_OFLD_CONNECTION_WR_T_STATE)

#define	S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
#define	M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
#define	V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
#define	G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
	M_FW_OFLD_CONNECTION_WR_RCV_SCALE)

#define	S_FW_OFLD_CONNECTION_WR_ASTID		0
#define	M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
#define	V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
#define	G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)

#define	S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
#define	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
#define	V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
#define	G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
	M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
#define	F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
    V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)

#define	S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
#define	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
#define	V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
	((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
#define	G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
	(((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
	M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
#define	F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
    V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)

enum fw_flowc_mnem_tcpstate {
	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0,	/* illegal */
	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1,	/* illegal */
	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2,	/* illegal */
	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3,	/* illegal */
	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4,	/* default */
	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5,	/* got peer close already */
	/* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */
	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6,
	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7,
	/* haven't gotten ACK for FIN & will resend FIN but have received FIN */
	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8,
	/* sent FIN and got FIN + ACK, waiting for FIN */
	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9,
	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10,	/* not expected */
};

enum fw_flowc_mnem_uostate {
	FW_FLOWC_MNEM_UOSTATE_CLOSED	= 0,	/* illegal */
	FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1,	/* default */
	/* graceful close, after sending outstanding payload */
	FW_FLOWC_MNEM_UOSTATE_CLOSING	= 2,
	/* immediate close, after discarding outstanding payload */
	FW_FLOWC_MNEM_UOSTATE_ABORTING	= 3,
};

enum fw_flowc_mnem {
	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
	FW_FLOWC_MNEM_CH		= 1,
	FW_FLOWC_MNEM_PORT		= 2,
	FW_FLOWC_MNEM_IQID		= 3,
	FW_FLOWC_MNEM_SNDNXT		= 4,
	FW_FLOWC_MNEM_RCVNXT		= 5,
	FW_FLOWC_MNEM_SNDBUF		= 6,
	FW_FLOWC_MNEM_MSS		= 7,
	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
	FW_FLOWC_MNEM_TCPSTATE		= 9,
	FW_FLOWC_MNEM_UOSTATE		= 10,
	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
	FW_FLOWC_MNEM_DCBPRIO		= 12,
};

struct fw_flowc_mnemval {
	__u8   mnemonic;
	__u8   r4[3];
	__be32 val;
};

struct fw_flowc_wr {
	__be32 op_to_nparams;
	__be32 flowid_len16;
#ifndef C99_NOT_SUPPORTED
	struct fw_flowc_mnemval mnemval[];
#endif
};

#define	S_FW_FLOWC_WR_NPARAMS		0
#define	M_FW_FLOWC_WR_NPARAMS		0xff
#define	V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
#define	G_FW_FLOWC_WR_NPARAMS(x)	\
	(((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)

struct fw_ofld_tx_data_wr {
	__be32 op_to_immdlen;
	__be32 flowid_len16;
	__be32 plen;
	__be32 tunnel_to_proxy;
};

#define	S_FW_OFLD_TX_DATA_WR_TUNNEL	19
#define	M_FW_OFLD_TX_DATA_WR_TUNNEL	0x1
#define	V_FW_OFLD_TX_DATA_WR_TUNNEL(x)	((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
#define	G_FW_OFLD_TX_DATA_WR_TUNNEL(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
#define	F_FW_OFLD_TX_DATA_WR_TUNNEL	V_FW_OFLD_TX_DATA_WR_TUNNEL(1U)

#define	S_FW_OFLD_TX_DATA_WR_SAVE	18
#define	M_FW_OFLD_TX_DATA_WR_SAVE	0x1
#define	V_FW_OFLD_TX_DATA_WR_SAVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SAVE)
#define	G_FW_OFLD_TX_DATA_WR_SAVE(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
#define	F_FW_OFLD_TX_DATA_WR_SAVE	V_FW_OFLD_TX_DATA_WR_SAVE(1U)

#define	S_FW_OFLD_TX_DATA_WR_FLUSH	17
#define	M_FW_OFLD_TX_DATA_WR_FLUSH	0x1
#define	V_FW_OFLD_TX_DATA_WR_FLUSH(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLUSH)
#define	G_FW_OFLD_TX_DATA_WR_FLUSH(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
#define	F_FW_OFLD_TX_DATA_WR_FLUSH	V_FW_OFLD_TX_DATA_WR_FLUSH(1U)

#define	S_FW_OFLD_TX_DATA_WR_URGENT	16
#define	M_FW_OFLD_TX_DATA_WR_URGENT	0x1
#define	V_FW_OFLD_TX_DATA_WR_URGENT(x)	((x) << S_FW_OFLD_TX_DATA_WR_URGENT)
#define	G_FW_OFLD_TX_DATA_WR_URGENT(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
#define	F_FW_OFLD_TX_DATA_WR_URGENT	V_FW_OFLD_TX_DATA_WR_URGENT(1U)

#define	S_FW_OFLD_TX_DATA_WR_MORE	15
#define	M_FW_OFLD_TX_DATA_WR_MORE	0x1
#define	V_FW_OFLD_TX_DATA_WR_MORE(x)	((x) << S_FW_OFLD_TX_DATA_WR_MORE)
#define	G_FW_OFLD_TX_DATA_WR_MORE(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
#define	F_FW_OFLD_TX_DATA_WR_MORE	V_FW_OFLD_TX_DATA_WR_MORE(1U)

#define	S_FW_OFLD_TX_DATA_WR_SHOVE	14
#define	M_FW_OFLD_TX_DATA_WR_SHOVE	0x1
#define	V_FW_OFLD_TX_DATA_WR_SHOVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SHOVE)
#define	G_FW_OFLD_TX_DATA_WR_SHOVE(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
#define	F_FW_OFLD_TX_DATA_WR_SHOVE	V_FW_OFLD_TX_DATA_WR_SHOVE(1U)

#define	S_FW_OFLD_TX_DATA_WR_ULPMODE	10
#define	M_FW_OFLD_TX_DATA_WR_ULPMODE	0xf
#define	V_FW_OFLD_TX_DATA_WR_ULPMODE(x)	((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE)
#define	G_FW_OFLD_TX_DATA_WR_ULPMODE(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)

#define	S_FW_OFLD_TX_DATA_WR_ULPSUBMODE		6
#define	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE		0xf
#define	V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
	((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
#define	G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
	M_FW_OFLD_TX_DATA_WR_ULPSUBMODE)

#define	S_FW_OFLD_TX_DATA_WR_PROXY	5
#define	M_FW_OFLD_TX_DATA_WR_PROXY	0x1
#define	V_FW_OFLD_TX_DATA_WR_PROXY(x)	((x) << S_FW_OFLD_TX_DATA_WR_PROXY)
#define	G_FW_OFLD_TX_DATA_WR_PROXY(x)	\
	(((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
#define	F_FW_OFLD_TX_DATA_WR_PROXY	V_FW_OFLD_TX_DATA_WR_PROXY(1U)

struct fw_cmd_wr {
	__be32 op_dma;
	__be32 len16_pkd;
	__be64 cookie_daddr;
};

#define	S_FW_CMD_WR_DMA		17
#define	M_FW_CMD_WR_DMA		0x1
#define	V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
#define	G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
#define	F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)

struct fw_eth_tx_pkt_vm_wr {
	__be32 op_immdlen;
	__be32 equiq_to_len16;
	__be32 r3[2];
	__u8   ethmacdst[6];
	__u8   ethmacsrc[6];
	__be16 ethtype;
	__be16 vlantci;
};

/*
 *	************************************
 *	   R I   W O R K   R E Q U E S T s
 *	************************************
 */

enum fw_ri_wr_opcode {
	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
	FW_RI_READ_REQ			= 0x1,
	FW_RI_READ_RESP			= 0x2,
	FW_RI_SEND			= 0x3,
	FW_RI_SEND_WITH_INV		= 0x4,
	FW_RI_SEND_WITH_SE		= 0x5,
	FW_RI_SEND_WITH_SE_INV		= 0x6,
	FW_RI_TERMINATE			= 0x7,
	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
	FW_RI_BIND_MW			= 0x9,
	FW_RI_FAST_REGISTER		= 0xa,
	FW_RI_LOCAL_INV			= 0xb,
	FW_RI_QP_MODIFY			= 0xc,
	FW_RI_BYPASS			= 0xd,
	FW_RI_RECEIVE			= 0xe,
	FW_RI_SGE_EC_CR_RETURN		= 0xf

};

enum fw_ri_wr_flags {
	FW_RI_COMPLETION_FLAG		= 0x01,
	FW_RI_NOTIFICATION_FLAG		= 0x02,
	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
	FW_RI_READ_FENCE_FLAG		= 0x08,
	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
	FW_RI_RDMA_READ_INVALIDATE	= 0x20
};

enum fw_ri_mpa_attrs {
	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
	FW_RI_MPA_CRC_ENABLE		= 0x04,
	FW_RI_MPA_IETF_ENABLE		= 0x08
};

enum fw_ri_qp_caps {
	FW_RI_QP_RDMA_READ_ENABLE	 = 0x01,
	FW_RI_QP_RDMA_WRITE_ENABLE	 = 0x02,
	FW_RI_QP_BIND_ENABLE		 = 0x04,
	FW_RI_QP_FAST_REGISTER_ENABLE	 = 0x08,
	FW_RI_QP_STAG0_ENABLE		 = 0x10,
	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80,
};

enum fw_ri_addr_type {
	FW_RI_ZERO_BASED_TO		= 0x00,
	FW_RI_VA_BASED_TO		= 0x01
};

enum fw_ri_mem_perms {
	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
	FW_RI_MEM_ACCESS_REM		= 0x03,
	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
};

enum fw_ri_stag_type {
	FW_RI_STAG_NSMR			= 0x00,
	FW_RI_STAG_SMR			= 0x01,
	FW_RI_STAG_MW			= 0x02,
	FW_RI_STAG_MW_RELAXED		= 0x03
};

enum fw_ri_data_op {
	FW_RI_DATA_IMMD			= 0x81,
	FW_RI_DATA_DSGL			= 0x82,
	FW_RI_DATA_ISGL			= 0x83
};

enum fw_ri_sgl_depth {
	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
	FW_RI_SGL_DEPTH_MAX_RQ		= 4
};

enum fw_ri_cqe_err {
	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
	/* attempt to invalidate a SMR */
	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07,
	/* attempt to invalidate a MR w MW */
	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08,
	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
	/* ECC error detected when reading the PSTAG for a MW Invalidate */
	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A,
	/* pbl address out of bound : software error */
	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B,
	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
	/* MO not zero for TERMINATE or READ_REQ */
	FW_RI_CQE_ERR_MO		= 0x1A,
	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
	/* RQE address out of bound : software error */
	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E,
	/* internel error (opcode mismatch) */
	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F

};

struct fw_ri_dsge_pair {
	__be32	len[2];
	__be64	addr[2];
};

struct fw_ri_dsgl {
	__u8	op;
	__u8	r1;
	__be16	nsge;
	__be32	len0;
	__be64	addr0;
#ifndef C99_NOT_SUPPORTED
	struct fw_ri_dsge_pair sge[];
#endif
};

struct fw_ri_sge {
	__be32 stag;
	__be32 len;
	__be64 to;
};

struct fw_ri_isgl {
	__u8	op;
	__u8	r1;
	__be16	nsge;
	__be32	r2;
#ifndef C99_NOT_SUPPORTED
	struct fw_ri_sge sge[];
#endif
};

struct fw_ri_immd {
	__u8	op;
	__u8	r1;
	__be16	r2;
	__be32	immdlen;
#ifndef C99_NOT_SUPPORTED
	__u8	data[];
#endif
};

struct fw_ri_tpte {
	__be32 valid_to_pdid;
	__be32 locread_to_qpid;
	__be32 nosnoop_pbladdr;
	__be32 len_lo;
	__be32 va_hi;
	__be32 va_lo_fbo;
	__be32 dca_mwbcnt_pstag;
	__be32 len_hi;
};

#define	S_FW_RI_TPTE_VALID		31
#define	M_FW_RI_TPTE_VALID		0x1
#define	V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
#define	G_FW_RI_TPTE_VALID(x)		\
	(((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
#define	F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)

#define	S_FW_RI_TPTE_STAGKEY		23
#define	M_FW_RI_TPTE_STAGKEY		0xff
#define	V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
#define	G_FW_RI_TPTE_STAGKEY(x)		\
	(((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)

#define	S_FW_RI_TPTE_STAGSTATE		22
#define	M_FW_RI_TPTE_STAGSTATE		0x1
#define	V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
#define	G_FW_RI_TPTE_STAGSTATE(x)	\
	(((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
#define	F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)

#define	S_FW_RI_TPTE_STAGTYPE		20
#define	M_FW_RI_TPTE_STAGTYPE		0x3
#define	V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
#define	G_FW_RI_TPTE_STAGTYPE(x)	\
	(((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)

#define	S_FW_RI_TPTE_PDID		0
#define	M_FW_RI_TPTE_PDID		0xfffff
#define	V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
#define	G_FW_RI_TPTE_PDID(x)		\
	(((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)

#define	S_FW_RI_TPTE_PERM		28
#define	M_FW_RI_TPTE_PERM		0xf
#define	V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
#define	G_FW_RI_TPTE_PERM(x)		\
	(((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)

#define	S_FW_RI_TPTE_REMINVDIS		27
#define	M_FW_RI_TPTE_REMINVDIS		0x1
#define	V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
#define	G_FW_RI_TPTE_REMINVDIS(x)	\
	(((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
#define	F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)

#define	S_FW_RI_TPTE_ADDRTYPE		26
#define	M_FW_RI_TPTE_ADDRTYPE		1
#define	V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
#define	G_FW_RI_TPTE_ADDRTYPE(x)	\
	(((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
#define	F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)

#define	S_FW_RI_TPTE_MWBINDEN		25
#define	M_FW_RI_TPTE_MWBINDEN		0x1
#define	V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
#define	G_FW_RI_TPTE_MWBINDEN(x)	\
	(((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
#define	F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)

#define	S_FW_RI_TPTE_PS			20
#define	M_FW_RI_TPTE_PS			0x1f
#define	V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
#define	G_FW_RI_TPTE_PS(x)		\
	(((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)

#define	S_FW_RI_TPTE_QPID		0
#define	M_FW_RI_TPTE_QPID		0xfffff
#define	V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
#define	G_FW_RI_TPTE_QPID(x)		\
	(((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)

#define	S_FW_RI_TPTE_NOSNOOP		31
#define	M_FW_RI_TPTE_NOSNOOP		0x1
#define	V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
#define	G_FW_RI_TPTE_NOSNOOP(x)		\
	(((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
#define	F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)

#define	S_FW_RI_TPTE_PBLADDR		0
#define	M_FW_RI_TPTE_PBLADDR		0x1fffffff
#define	V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
#define	G_FW_RI_TPTE_PBLADDR(x)		\
	(((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)

#define	S_FW_RI_TPTE_DCA		24
#define	M_FW_RI_TPTE_DCA		0x1f
#define	V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
#define	G_FW_RI_TPTE_DCA(x)		\
	(((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)

#define	S_FW_RI_TPTE_MWBCNT_PSTAG	0
#define	M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
#define	V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
	((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
#define	G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
	(((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)

enum fw_ri_cqe_rxtx {
	FW_RI_CQE_RXTX_RX = 0x0,
	FW_RI_CQE_RXTX_TX = 0x1,
};

struct fw_ri_cqe {
	union fw_ri_rxtx {
		struct fw_ri_scqe {
		__be32	qpid_n_stat_rxtx_type;
		__be32	plen;
		__be32	reserved;
		__be32	wrid;
		} scqe;
		struct fw_ri_rcqe {
		__be32	qpid_n_stat_rxtx_type;
		__be32	plen;
		__be32	stag;
		__be32	msn;
		} rcqe;
	} u;
};

#define	S_FW_RI_CQE_QPID	12
#define	M_FW_RI_CQE_QPID	0xfffff
#define	V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
#define	G_FW_RI_CQE_QPID(x)   \
	(((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)

#define	S_FW_RI_CQE_NOTIFY    10
#define	M_FW_RI_CQE_NOTIFY    0x1
#define	V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
#define	G_FW_RI_CQE_NOTIFY(x) \
	(((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)

#define	S_FW_RI_CQE_STATUS    5
#define	M_FW_RI_CQE_STATUS    0x1f
#define	V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
#define	G_FW_RI_CQE_STATUS(x) \
	(((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)

#define	S_FW_RI_CQE_RXTX	4
#define	M_FW_RI_CQE_RXTX	0x1
#define	V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
#define	G_FW_RI_CQE_RXTX(x)   \
	(((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)

#define	S_FW_RI_CQE_TYPE	0
#define	M_FW_RI_CQE_TYPE	0xf
#define	V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
#define	G_FW_RI_CQE_TYPE(x)   \
	(((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)

enum fw_ri_res_type {
	FW_RI_RES_TYPE_SQ,
	FW_RI_RES_TYPE_RQ,
	FW_RI_RES_TYPE_CQ,
};

enum fw_ri_res_op {
	FW_RI_RES_OP_WRITE,
	FW_RI_RES_OP_RESET,
};

struct fw_ri_res {
	union fw_ri_restype {
		struct fw_ri_res_sqrq {
			__u8   restype;
			__u8   op;
			__be16 r3;
			__be32 eqid;
			__be32 r4[2];
			__be32 fetchszm_to_iqid;
			__be32 dcaen_to_eqsize;
			__be64 eqaddr;
		} sqrq;
		struct fw_ri_res_cq {
			__u8   restype;
			__u8   op;
			__be16 r3;
			__be32 iqid;
			__be32 r4[2];
			__be32 iqandst_to_iqandstindex;
			__be16 iqdroprss_to_iqesize;
			__be16 iqsize;
			__be64 iqaddr;
			__be32 iqns_iqro;
			__be32 r6_lo;
			__be64 r7;
		} cq;
	} u;
};

struct fw_ri_res_wr {
	__be32 op_nres;
	__be32 len16_pkd;
	__u64  cookie;
#ifndef C99_NOT_SUPPORTED
	struct fw_ri_res res[];
#endif
};

#define	S_FW_RI_RES_WR_NRES	0
#define	M_FW_RI_RES_WR_NRES	0xff
#define	V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
#define	G_FW_RI_RES_WR_NRES(x)	\
	(((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)

#define	S_FW_RI_RES_WR_FETCHSZM		26
#define	M_FW_RI_RES_WR_FETCHSZM		0x1
#define	V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
#define	G_FW_RI_RES_WR_FETCHSZM(x)	\
	(((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
#define	F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)

#define	S_FW_RI_RES_WR_STATUSPGNS	25
#define	M_FW_RI_RES_WR_STATUSPGNS	0x1
#define	V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
#define	G_FW_RI_RES_WR_STATUSPGNS(x)	\
	(((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
#define	F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)

#define	S_FW_RI_RES_WR_STATUSPGRO	24
#define	M_FW_RI_RES_WR_STATUSPGRO	0x1
#define	V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
#define	G_FW_RI_RES_WR_STATUSPGRO(x)	\
	(((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
#define	F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)

#define	S_FW_RI_RES_WR_FETCHNS		23
#define	M_FW_RI_RES_WR_FETCHNS		0x1
#define	V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
#define	G_FW_RI_RES_WR_FETCHNS(x)	\
	(((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
#define	F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)

#define	S_FW_RI_RES_WR_FETCHRO		22
#define	M_FW_RI_RES_WR_FETCHRO		0x1
#define	V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
#define	G_FW_RI_RES_WR_FETCHRO(x)	\
	(((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
#define	F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)

#define	S_FW_RI_RES_WR_HOSTFCMODE	20
#define	M_FW_RI_RES_WR_HOSTFCMODE	0x3
#define	V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
#define	G_FW_RI_RES_WR_HOSTFCMODE(x)	\
	(((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)

#define	S_FW_RI_RES_WR_CPRIO	19
#define	M_FW_RI_RES_WR_CPRIO	0x1
#define	V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
#define	G_FW_RI_RES_WR_CPRIO(x)	\
	(((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
#define	F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)

#define	S_FW_RI_RES_WR_ONCHIP		18
#define	M_FW_RI_RES_WR_ONCHIP		0x1
#define	V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
#define	G_FW_RI_RES_WR_ONCHIP(x)	\
	(((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
#define	F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)

#define	S_FW_RI_RES_WR_PCIECHN		16
#define	M_FW_RI_RES_WR_PCIECHN		0x3
#define	V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
#define	G_FW_RI_RES_WR_PCIECHN(x)	\
	(((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)

#define	S_FW_RI_RES_WR_IQID	0
#define	M_FW_RI_RES_WR_IQID	0xffff
#define	V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
#define	G_FW_RI_RES_WR_IQID(x)	\
	(((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)

#define	S_FW_RI_RES_WR_DCAEN	31
#define	M_FW_RI_RES_WR_DCAEN	0x1
#define	V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
#define	G_FW_RI_RES_WR_DCAEN(x)	\
	(((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
#define	F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)

#define	S_FW_RI_RES_WR_DCACPU		26
#define	M_FW_RI_RES_WR_DCACPU		0x1f
#define	V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
#define	G_FW_RI_RES_WR_DCACPU(x)	\
	(((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)

#define	S_FW_RI_RES_WR_FBMIN	23
#define	M_FW_RI_RES_WR_FBMIN	0x7
#define	V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
#define	G_FW_RI_RES_WR_FBMIN(x)	\
	(((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)

#define	S_FW_RI_RES_WR_FBMAX	20
#define	M_FW_RI_RES_WR_FBMAX	0x7
#define	V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
#define	G_FW_RI_RES_WR_FBMAX(x)	\
	(((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)

#define	S_FW_RI_RES_WR_CIDXFTHRESHO	19
#define	M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
#define	V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
#define	G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
#define	F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)

#define	S_FW_RI_RES_WR_CIDXFTHRESH	16
#define	M_FW_RI_RES_WR_CIDXFTHRESH	0x7
#define	V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
#define	G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
	(((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)

#define	S_FW_RI_RES_WR_EQSIZE		0
#define	M_FW_RI_RES_WR_EQSIZE		0xffff
#define	V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
#define	G_FW_RI_RES_WR_EQSIZE(x)	\
	(((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)

#define	S_FW_RI_RES_WR_IQANDST		15
#define	M_FW_RI_RES_WR_IQANDST		0x1
#define	V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
#define	G_FW_RI_RES_WR_IQANDST(x)	\
	(((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
#define	F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)

#define	S_FW_RI_RES_WR_IQANUS		14
#define	M_FW_RI_RES_WR_IQANUS		0x1
#define	V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
#define	G_FW_RI_RES_WR_IQANUS(x)	\
	(((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
#define	F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)

#define	S_FW_RI_RES_WR_IQANUD		12
#define	M_FW_RI_RES_WR_IQANUD		0x3
#define	V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
#define	G_FW_RI_RES_WR_IQANUD(x)	\
	(((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)

#define	S_FW_RI_RES_WR_IQANDSTINDEX	0
#define	M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
#define	V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
#define	G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
	(((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)

#define	S_FW_RI_RES_WR_IQDROPRSS	15
#define	M_FW_RI_RES_WR_IQDROPRSS	0x1
#define	V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
#define	G_FW_RI_RES_WR_IQDROPRSS(x)	\
	(((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
#define	F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)

#define	S_FW_RI_RES_WR_IQGTSMODE	14
#define	M_FW_RI_RES_WR_IQGTSMODE	0x1
#define	V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
#define	G_FW_RI_RES_WR_IQGTSMODE(x)	\
	(((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
#define	F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)

#define	S_FW_RI_RES_WR_IQPCIECH		12
#define	M_FW_RI_RES_WR_IQPCIECH		0x3
#define	V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
#define	G_FW_RI_RES_WR_IQPCIECH(x)	\
	(((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)

#define	S_FW_RI_RES_WR_IQDCAEN		11
#define	M_FW_RI_RES_WR_IQDCAEN		0x1
#define	V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
#define	G_FW_RI_RES_WR_IQDCAEN(x)	\
	(((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
#define	F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)

#define	S_FW_RI_RES_WR_IQDCACPU		6
#define	M_FW_RI_RES_WR_IQDCACPU		0x1f
#define	V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
#define	G_FW_RI_RES_WR_IQDCACPU(x)	\
	(((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)

#define	S_FW_RI_RES_WR_IQINTCNTTHRESH		4
#define	M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
#define	V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
	((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
#define	G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
	(((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)

#define	S_FW_RI_RES_WR_IQO	3
#define	M_FW_RI_RES_WR_IQO	0x1
#define	V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
#define	G_FW_RI_RES_WR_IQO(x)	\
	(((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
#define	F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)

#define	S_FW_RI_RES_WR_IQCPRIO		2
#define	M_FW_RI_RES_WR_IQCPRIO		0x1
#define	V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
#define	G_FW_RI_RES_WR_IQCPRIO(x)	\
	(((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
#define	F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)

#define	S_FW_RI_RES_WR_IQESIZE		0
#define	M_FW_RI_RES_WR_IQESIZE		0x3
#define	V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
#define	G_FW_RI_RES_WR_IQESIZE(x)	\
	(((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)

#define	S_FW_RI_RES_WR_IQNS	31
#define	M_FW_RI_RES_WR_IQNS	0x1
#define	V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
#define	G_FW_RI_RES_WR_IQNS(x)	\
	(((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
#define	F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)

#define	S_FW_RI_RES_WR_IQRO	30
#define	M_FW_RI_RES_WR_IQRO	0x1
#define	V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
#define	G_FW_RI_RES_WR_IQRO(x)	\
	(((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
#define	F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)

struct fw_ri_rdma_write_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be64 r2;
	__be32 plen;
	__be32 stag_sink;
	__be64 to_sink;
};

struct fw_ri_send_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be32 sendop_pkd;
	__be32 stag_inv;
	__be32 plen;
	__be32 r3;
	__be64 r4;
};

#define	S_FW_RI_SEND_WR_SENDOP		0
#define	M_FW_RI_SEND_WR_SENDOP		0xf
#define	V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
#define	G_FW_RI_SEND_WR_SENDOP(x)	\
	(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)

struct fw_ri_rdma_read_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be64 r2;
	__be32 stag_sink;
	__be32 to_sink_hi;
	__be32 to_sink_lo;
	__be32 plen;
	__be32 stag_src;
	__be32 to_src_hi;
	__be32 to_src_lo;
	__be32 r5;
};

struct fw_ri_recv_wr {
	__u8   opcode;
	__u8   r1;
	__u16  wrid;
	__u8   r2[3];
	__u8   len16;
};

struct fw_ri_bind_mw_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__u8   qpbinde_to_dcacpu;
	__u8   pgsz_shift;
	__u8   addr_type;
	__u8   mem_perms;
	__be32 stag_mr;
	__be32 stag_mw;
	__be32 r3;
	__be64 len_mw;
	__be64 va_fbo;
	__be64 r4;
};

#define	S_FW_RI_BIND_MW_WR_QPBINDE	6
#define	M_FW_RI_BIND_MW_WR_QPBINDE	0x1
#define	V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
#define	G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
	(((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
#define	F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)

#define	S_FW_RI_BIND_MW_WR_NS		5
#define	M_FW_RI_BIND_MW_WR_NS		0x1
#define	V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
#define	G_FW_RI_BIND_MW_WR_NS(x)	\
	(((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
#define	F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)

#define	S_FW_RI_BIND_MW_WR_DCACPU	0
#define	M_FW_RI_BIND_MW_WR_DCACPU	0x1f
#define	V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
#define	G_FW_RI_BIND_MW_WR_DCACPU(x)	\
	(((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)

struct fw_ri_fr_nsmr_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__u8   qpbinde_to_dcacpu;
	__u8   pgsz_shift;
	__u8   addr_type;
	__u8   mem_perms;
	__be32 stag;
	__be32 len_hi;
	__be32 len_lo;
	__be32 va_hi;
	__be32 va_lo_fbo;
};

#define	S_FW_RI_FR_NSMR_WR_QPBINDE	6
#define	M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
#define	V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
#define	G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
	(((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
#define	F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)

#define	S_FW_RI_FR_NSMR_WR_NS		5
#define	M_FW_RI_FR_NSMR_WR_NS		0x1
#define	V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
#define	G_FW_RI_FR_NSMR_WR_NS(x)	\
	(((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
#define	F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)

#define	S_FW_RI_FR_NSMR_WR_DCACPU	0
#define	M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
#define	V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
#define	G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
	(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)

struct fw_ri_inv_lstag_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be32 r2;
	__be32 stag_inv;
};

struct fw_ri_send_immediate_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be32 sendimmop_pkd;
	__be32 r3;
	__be32 plen;
	__be32 r4;
	__be64 r5;
};

#define	S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
#define	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
#define	V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
	((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
#define	G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
	(((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
	M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)

enum fw_ri_atomic_op {
	FW_RI_ATOMIC_OP_FETCHADD,
	FW_RI_ATOMIC_OP_SWAP,
	FW_RI_ATOMIC_OP_CMDSWAP,
};

struct fw_ri_atomic_wr {
	__u8   opcode;
	__u8   flags;
	__u16  wrid;
	__u8   r1[3];
	__u8   len16;
	__be32 atomicop_pkd;
	__be64 r3;
	__be32 aopcode_pkd;
	__be32 reqid;
	__be32 stag;
	__be32 to_hi;
	__be32 to_lo;
	__be32 addswap_data_hi;
	__be32 addswap_data_lo;
	__be32 addswap_mask_hi;
	__be32 addswap_mask_lo;
	__be32 compare_data_hi;
	__be32 compare_data_lo;
	__be32 compare_mask_hi;
	__be32 compare_mask_lo;
	__be32 r5;
};

#define	S_FW_RI_ATOMIC_WR_ATOMICOP	0
#define	M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
#define	V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
#define	G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
	(((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)

#define	S_FW_RI_ATOMIC_WR_AOPCODE	0
#define	M_FW_RI_ATOMIC_WR_AOPCODE	0xf
#define	V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
#define	G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
	(((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)

enum fw_ri_type {
	FW_RI_TYPE_INIT,
	FW_RI_TYPE_FINI,
	FW_RI_TYPE_TERMINATE
};

enum fw_ri_init_p2ptype {
	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
};

struct fw_ri_wr {
	__be32 op_compl;
	__be32 flowid_len16;
	__u64  cookie;
	union fw_ri {
		struct fw_ri_init {
			__u8   type;
			__u8   mpareqbit_p2ptype;
			__u8   r4[2];
			__u8   mpa_attrs;
			__u8   qp_caps;
			__be16 nrqe;
			__be32 pdid;
			__be32 qpid;
			__be32 sq_eqid;
			__be32 rq_eqid;
			__be32 scqid;
			__be32 rcqid;
			__be32 ord_max;
			__be32 ird_max;
			__be32 iss;
			__be32 irs;
			__be32 hwrqsize;
			__be32 hwrqaddr;
			__be64 r5;
			union fw_ri_init_p2p {
				struct fw_ri_rdma_write_wr write;
				struct fw_ri_rdma_read_wr read;
				struct fw_ri_send_wr send;
			} u;
		} init;
		struct fw_ri_fini {
			__u8   type;
			__u8   r3[7];
			__be64 r4;
		} fini;
		struct fw_ri_terminate {
			__u8   type;
			__u8   r3[3];
			__be32 immdlen;
			__u8   termmsg[40];
		} terminate;
	} u;
};

#define	S_FW_RI_WR_MPAREQBIT	7
#define	M_FW_RI_WR_MPAREQBIT	0x1
#define	V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
#define	G_FW_RI_WR_MPAREQBIT(x)	\
	(((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
#define	F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)

#define	S_FW_RI_WR_0BRRBIT	6
#define	M_FW_RI_WR_0BRRBIT	0x1
#define	V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
#define	G_FW_RI_WR_0BRRBIT(x)	\
	(((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
#define	F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)

#define	S_FW_RI_WR_P2PTYPE	0
#define	M_FW_RI_WR_P2PTYPE	0xf
#define	V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
#define	G_FW_RI_WR_P2PTYPE(x)	\
	(((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)

/*
 *	*******************************************
 *	  F O i S C S I   W O R K R E Q U E S T s
 *	*******************************************
 */

#define	FW_FOISCSI_NAME_MAX_LEN		224
#define	FW_FOISCSI_ALIAS_MAX_LEN	224
#define	FW_FOISCSI_CHAP_SEC_MAX_LEN	128
#define	FW_FOISCSI_INIT_NODE_MAX	8

enum fw_chnet_ifconf_wr_subop {
	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,

	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,

	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,

	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,

	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,

	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,

	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,

	FW_CHNET_IFCONF_WR_SUBOP_MAX,
};

struct fw_chnet_ifconf_wr {
	__be32 op_compl;
	__be32 flowid_len16;
	__be64 cookie;
	__be32 if_flowid;
	__u8   idx;
	__u8   subop;
	__u8   retval;
	__u8   r2;
	__be64 r3;
	struct fw_chnet_ifconf_params {
		__be32 r0;
		__be16 vlanid;
		__be16 mtu;
		union fw_chnet_ifconf_addr_type {
			struct fw_chnet_ifconf_ipv4 {
				__be32 addr;
				__be32 mask;
				__be32 router;
				__be32 r0;
				__be64 r1;
			} ipv4;
			struct fw_chnet_ifconf_ipv6 {
				__be64 linklocal_lo;
				__be64 linklocal_hi;
				__be64 router_hi;
				__be64 router_lo;
				__be64 aconf_hi;
				__be64 aconf_lo;
				__be64 linklocal_aconf_hi;
				__be64 linklocal_aconf_lo;
				__be64 router_aconf_hi;
				__be64 router_aconf_lo;
				__be64 r0;
			} ipv6;
		} in_attr;
	} param;
};

enum fw_foiscsi_node_type {
	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
	FW_FOISCSI_NODE_TYPE_TARGET,
};

enum fw_foiscsi_session_type {
	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
	FW_FOISCSI_SESSION_TYPE_NORMAL,
};

enum fw_foiscsi_auth_policy {
	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
	FW_FOISCSI_AUTH_POLICY_MUTUAL,
};

enum fw_foiscsi_auth_method {
	FW_FOISCSI_AUTH_METHOD_NONE = 0,
	FW_FOISCSI_AUTH_METHOD_CHAP,
	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
};

enum fw_foiscsi_digest_type {
	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
	FW_FOISCSI_DIGEST_TYPE_CRC32,
	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
};

enum fw_foiscsi_wr_subop {
	FW_FOISCSI_WR_SUBOP_ADD = 1,
	FW_FOISCSI_WR_SUBOP_DEL = 2,
	FW_FOISCSI_WR_SUBOP_MOD = 4,
};

enum fw_foiscsi_ctrl_state {
	FW_FOISCSI_CTRL_STATE_FREE = 0,
	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
	FW_FOISCSI_CTRL_STATE_FAILED,
	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
	FW_FOISCSI_CTRL_STATE_REDIRECT,
};

struct fw_rdev_wr {
	__be32 op_to_immdlen;
	__be32 alloc_to_len16;
	__be64 cookie;
	__u8   protocol;
	__u8   event_cause;
	__u8   cur_state;
	__u8   prev_state;
	__be32 flags_to_assoc_flowid;
	union rdev_entry {
		struct fcoe_rdev_entry {
			__be32 flowid;
			__u8   protocol;
			__u8   event_cause;
			__u8   flags;
			__u8   rjt_reason;
			__u8   cur_login_st;
			__u8   prev_login_st;
			__be16 rcv_fr_sz;
			__u8   rd_xfer_rdy_to_rport_type;
			__u8   vft_to_qos;
			__u8   org_proc_assoc_to_acc_rsp_code;
			__u8   enh_disc_to_tgt;
			__u8   wwnn[8];
			__u8   wwpn[8];
			__be16 iqid;
			__u8   fc_oui[3];
			__u8   r_id[3];
		} fcoe_rdev;
		struct iscsi_rdev_entry {
			__be32 flowid;
			__u8   protocol;
			__u8   event_cause;
			__u8   flags;
			__u8   r3;
			__be16 iscsi_opts;
			__be16 tcp_opts;
			__be16 ip_opts;
			__be16 max_rcv_len;
			__be16 max_snd_len;
			__be16 first_brst_len;
			__be16 max_brst_len;
			__be16 r4;
			__be16 def_time2wait;
			__be16 def_time2ret;
			__be16 nop_out_intrvl;
			__be16 non_scsi_to;
			__be16 isid;
			__be16 tsid;
			__be16 port;
			__be16 tpgt;
			__u8   r5[6];
			__be16 iqid;
		} iscsi_rdev;
	} u;
};

#define	S_FW_RDEV_WR_IMMDLEN	0
#define	M_FW_RDEV_WR_IMMDLEN	0xff
#define	V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
#define	G_FW_RDEV_WR_IMMDLEN(x)	\
	(((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)

#define	S_FW_RDEV_WR_ALLOC	31
#define	M_FW_RDEV_WR_ALLOC	0x1
#define	V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
#define	G_FW_RDEV_WR_ALLOC(x)	\
	(((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
#define	F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)

#define	S_FW_RDEV_WR_FREE	30
#define	M_FW_RDEV_WR_FREE	0x1
#define	V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
#define	G_FW_RDEV_WR_FREE(x)	\
	(((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
#define	F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)

#define	S_FW_RDEV_WR_MODIFY	29
#define	M_FW_RDEV_WR_MODIFY	0x1
#define	V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
#define	G_FW_RDEV_WR_MODIFY(x)	\
	(((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
#define	F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)

#define	S_FW_RDEV_WR_FLOWID	8
#define	M_FW_RDEV_WR_FLOWID	0xfffff
#define	V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
#define	G_FW_RDEV_WR_FLOWID(x)	\
	(((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)

#define	S_FW_RDEV_WR_LEN16	0
#define	M_FW_RDEV_WR_LEN16	0xff
#define	V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
#define	G_FW_RDEV_WR_LEN16(x)	\
	(((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)

#define	S_FW_RDEV_WR_FLAGS	24
#define	M_FW_RDEV_WR_FLAGS	0xff
#define	V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
#define	G_FW_RDEV_WR_FLAGS(x)	\
	(((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)

#define	S_FW_RDEV_WR_GET_NEXT		20
#define	M_FW_RDEV_WR_GET_NEXT		0xf
#define	V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
#define	G_FW_RDEV_WR_GET_NEXT(x)	\
	(((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)

#define	S_FW_RDEV_WR_ASSOC_FLOWID	0
#define	M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
#define	V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
#define	G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
	(((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)

#define	S_FW_RDEV_WR_RJT	7
#define	M_FW_RDEV_WR_RJT	0x1
#define	V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
#define	G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
#define	F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)

#define	S_FW_RDEV_WR_REASON	0
#define	M_FW_RDEV_WR_REASON	0x7f
#define	V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
#define	G_FW_RDEV_WR_REASON(x)	\
	(((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)

#define	S_FW_RDEV_WR_RD_XFER_RDY	7
#define	M_FW_RDEV_WR_RD_XFER_RDY	0x1
#define	V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
#define	G_FW_RDEV_WR_RD_XFER_RDY(x)	\
	(((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
#define	F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)

#define	S_FW_RDEV_WR_WR_XFER_RDY	6
#define	M_FW_RDEV_WR_WR_XFER_RDY	0x1
#define	V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
#define	G_FW_RDEV_WR_WR_XFER_RDY(x)	\
	(((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
#define	F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)

#define	S_FW_RDEV_WR_FC_SP	5
#define	M_FW_RDEV_WR_FC_SP	0x1
#define	V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
#define	G_FW_RDEV_WR_FC_SP(x)	\
	(((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
#define	F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)

#define	S_FW_RDEV_WR_RPORT_TYPE		0
#define	M_FW_RDEV_WR_RPORT_TYPE		0x1f
#define	V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
#define	G_FW_RDEV_WR_RPORT_TYPE(x)	\
	(((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)

#define	S_FW_RDEV_WR_VFT	7
#define	M_FW_RDEV_WR_VFT	0x1
#define	V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
#define	G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
#define	F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)

#define	S_FW_RDEV_WR_NPIV	6
#define	M_FW_RDEV_WR_NPIV	0x1
#define	V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
#define	G_FW_RDEV_WR_NPIV(x)	\
	(((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
#define	F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)

#define	S_FW_RDEV_WR_CLASS	4
#define	M_FW_RDEV_WR_CLASS	0x3
#define	V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
#define	G_FW_RDEV_WR_CLASS(x)	\
	(((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)

#define	S_FW_RDEV_WR_SEQ_DEL	3
#define	M_FW_RDEV_WR_SEQ_DEL	0x1
#define	V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
#define	G_FW_RDEV_WR_SEQ_DEL(x)	\
	(((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
#define	F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)

#define	S_FW_RDEV_WR_PRIO_PREEMP	2
#define	M_FW_RDEV_WR_PRIO_PREEMP	0x1
#define	V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
#define	G_FW_RDEV_WR_PRIO_PREEMP(x)	\
	(((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
#define	F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)

#define	S_FW_RDEV_WR_PREF	1
#define	M_FW_RDEV_WR_PREF	0x1
#define	V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
#define	G_FW_RDEV_WR_PREF(x)	\
	(((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
#define	F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)

#define	S_FW_RDEV_WR_QOS	0
#define	M_FW_RDEV_WR_QOS	0x1
#define	V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
#define	G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
#define	F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)

#define	S_FW_RDEV_WR_ORG_PROC_ASSOC	7
#define	M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
#define	V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
#define	G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
	(((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
#define	F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)

#define	S_FW_RDEV_WR_RSP_PROC_ASSOC	6
#define	M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
#define	V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
#define	G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
	(((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
#define	F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)

#define	S_FW_RDEV_WR_IMAGE_PAIR		5
#define	M_FW_RDEV_WR_IMAGE_PAIR		0x1
#define	V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
#define	G_FW_RDEV_WR_IMAGE_PAIR(x)	\
	(((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
#define	F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)

#define	S_FW_RDEV_WR_ACC_RSP_CODE	0
#define	M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
#define	V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
#define	G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
	(((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)

#define	S_FW_RDEV_WR_ENH_DISC		7
#define	M_FW_RDEV_WR_ENH_DISC		0x1
#define	V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
#define	G_FW_RDEV_WR_ENH_DISC(x)	\
	(((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
#define	F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)

#define	S_FW_RDEV_WR_REC	6
#define	M_FW_RDEV_WR_REC	0x1
#define	V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
#define	G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
#define	F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)

#define	S_FW_RDEV_WR_TASK_RETRY_ID	5
#define	M_FW_RDEV_WR_TASK_RETRY_ID	0x1
#define	V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
#define	G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
	(((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
#define	F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)

#define	S_FW_RDEV_WR_RETRY	4
#define	M_FW_RDEV_WR_RETRY	0x1
#define	V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
#define	G_FW_RDEV_WR_RETRY(x)	\
	(((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
#define	F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)

#define	S_FW_RDEV_WR_CONF_CMPL		3
#define	M_FW_RDEV_WR_CONF_CMPL		0x1
#define	V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
#define	G_FW_RDEV_WR_CONF_CMPL(x)	\
	(((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
#define	F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)

#define	S_FW_RDEV_WR_DATA_OVLY		2
#define	M_FW_RDEV_WR_DATA_OVLY		0x1
#define	V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
#define	G_FW_RDEV_WR_DATA_OVLY(x)	\
	(((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
#define	F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)

#define	S_FW_RDEV_WR_INI	1
#define	M_FW_RDEV_WR_INI	0x1
#define	V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
#define	G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
#define	F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)

#define	S_FW_RDEV_WR_TGT	0
#define	M_FW_RDEV_WR_TGT	0x1
#define	V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
#define	G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
#define	F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)

struct fw_foiscsi_node_wr {
	__be32 op_to_immdlen;
	__be32 flowid_len16;
	__u64  cookie;
	__u8   subop;
	__u8   status;
	__u8   alias_len;
	__u8   iqn_len;
	__be32 node_flowid;
	__be16 nodeid;
	__be16 login_retry;
	__be16 retry_timeout;
	__be16 r3;
	__u8   iqn[224];
	__u8   alias[224];
};

#define	S_FW_FOISCSI_NODE_WR_IMMDLEN	0
#define	M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
#define	V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
#define	G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
	(((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)

struct fw_foiscsi_ctrl_wr {
	__be32 op_compl;
	__be32 flowid_len16;
	__u64  cookie;
	__u8   subop;
	__u8   status;
	__u8   ctrl_state;
	__u8   io_state;
	__be32 node_id;
	__be32 ctrl_id;
	__be32 io_id;
	struct fw_foiscsi_sess_attr {
		__be32 sess_type_to_erl;
		__be16 max_conn;
		__be16 max_r2t;
		__be16 time2wait;
		__be16 time2retain;
		__be32 max_burst;
		__be32 first_burst;
		__be32 r1;
	} sess_attr;
	struct fw_foiscsi_conn_attr {
		__be32 hdigest_to_ddp_pgsz;
		__be32 max_rcv_dsl;
		__be32 ping_tmo;
		__be16 dst_port;
		__be16 src_port;
		union fw_foiscsi_conn_attr_addr {
			struct fw_foiscsi_conn_attr_ipv6 {
				__be64 dst_addr[2];
				__be64 src_addr[2];
			} ipv6_addr;
			struct fw_foiscsi_conn_attr_ipv4 {
				__be32 dst_addr;
				__be32 src_addr;
			} ipv4_addr;
		} u;
	} conn_attr;
	__u8   tgt_name_len;
	__u8   r3[7];
	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
};

#define	S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
#define	M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
#define	V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
#define	G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \
	M_FW_FOISCSI_CTRL_WR_SESS_TYPE)

#define	S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
#define	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
#define	V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
#define	G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
	M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
#define	F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
    V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)

#define	S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
#define	M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
#define	V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
#define	G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
	M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
#define	F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
    V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)

#define	S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
#define	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
#define	V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
#define	G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
	M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
#define	F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
    V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)

#define	S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
#define	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
#define	V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
#define	G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
	M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
#define	F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
    V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)

#define	S_FW_FOISCSI_CTRL_WR_ERL	24
#define	M_FW_FOISCSI_CTRL_WR_ERL	0x3
#define	V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
#define	G_FW_FOISCSI_CTRL_WR_ERL(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)

#define	S_FW_FOISCSI_CTRL_WR_HDIGEST	30
#define	M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
#define	V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
#define	G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)

#define	S_FW_FOISCSI_CTRL_WR_DDIGEST	28
#define	M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
#define	V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
#define	G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)

#define	S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
#define	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
#define	V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
#define	G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
	M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)

#define	S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
#define	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
#define	V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
	((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
#define	G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
	(((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
	M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)

#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
    ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
    (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)

struct fw_foiscsi_chap_wr {
	__be32 op_compl;
	__be32 flowid_len16;
	__u64  cookie;
	__u8   status;
	__u8   id_len;
	__u8   sec_len;
	__u8   node_type;
	__be16 node_id;
	__u8   r3[2];
	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
};

/*
 *	*****************************************
 *	  F O F C O E   W O R K R E Q U E S T s
 *	*****************************************
 */

struct fw_fcoe_els_ct_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   tmo_val;
	__u8   els_ct_type;
	__u8   ctl_pri;
	__u8   cp_en_class;
	__be16 xfer_cnt;
	__u8   fl_to_sp;
	__u8   l_id[3];
	__u8   r5;
	__u8   r_id[3];
	__be64 rsp_dmaaddr;
	__be32 rsp_dmalen;
	__be32 r6;
};

#define	S_FW_FCOE_ELS_CT_WR_OPCODE	24
#define	M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
#define	V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
#define	G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)

#define	S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
#define	M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
#define	V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
#define	G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)

#define	S_FW_FCOE_ELS_CT_WR_FLOWID	8
#define	M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
#define	V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
#define	G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)

#define	S_FW_FCOE_ELS_CT_WR_LEN16	0
#define	M_FW_FCOE_ELS_CT_WR_LEN16	0xff
#define	V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
#define	G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)

#define	S_FW_FCOE_ELS_CT_WR_CP_EN	6
#define	M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
#define	V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
#define	G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)

#define	S_FW_FCOE_ELS_CT_WR_CLASS	4
#define	M_FW_FCOE_ELS_CT_WR_CLASS	0x3
#define	V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
#define	G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)

#define	S_FW_FCOE_ELS_CT_WR_FL		2
#define	M_FW_FCOE_ELS_CT_WR_FL		0x1
#define	V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
#define	G_FW_FCOE_ELS_CT_WR_FL(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
#define	F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)

#define	S_FW_FCOE_ELS_CT_WR_NPIV	1
#define	M_FW_FCOE_ELS_CT_WR_NPIV	0x1
#define	V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
#define	G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
#define	F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)

#define	S_FW_FCOE_ELS_CT_WR_SP		0
#define	M_FW_FCOE_ELS_CT_WR_SP		0x1
#define	V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
#define	G_FW_FCOE_ELS_CT_WR_SP(x)	\
	(((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
#define	F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)

/*
 *	****************************************
 *	  S C S I   W O R K R E Q U E S T s
 *	  (FOiSCSI and FCOE unified data path)
 *	****************************************
 */

struct fw_scsi_write_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   tmo_val;
	__u8   use_xfer_cnt;
	union fw_scsi_write_priv {
		struct fcoe_write_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r3_lo[2];
		} fcoe;
		struct iscsi_write_priv {
			__u8   r3[4];
		} iscsi;
	} u;
	__be32 xfer_cnt;
	__be32 ini_xfer_cnt;
	__be64 rsp_dmaaddr;
	__be32 rsp_dmalen;
	__be32 r4;
};

#define	S_FW_SCSI_WRITE_WR_OPCODE	24
#define	M_FW_SCSI_WRITE_WR_OPCODE	0xff
#define	V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
#define	G_FW_SCSI_WRITE_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)

#define	S_FW_SCSI_WRITE_WR_IMMDLEN	0
#define	M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
#define	V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
#define	G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)

#define	S_FW_SCSI_WRITE_WR_FLOWID	8
#define	M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
#define	V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
#define	G_FW_SCSI_WRITE_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)

#define	S_FW_SCSI_WRITE_WR_LEN16	0
#define	M_FW_SCSI_WRITE_WR_LEN16	0xff
#define	V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
#define	G_FW_SCSI_WRITE_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)

#define	S_FW_SCSI_WRITE_WR_CP_EN	6
#define	M_FW_SCSI_WRITE_WR_CP_EN	0x3
#define	V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
#define	G_FW_SCSI_WRITE_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)

#define	S_FW_SCSI_WRITE_WR_CLASS	4
#define	M_FW_SCSI_WRITE_WR_CLASS	0x3
#define	V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
#define	G_FW_SCSI_WRITE_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)

struct fw_scsi_read_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   tmo_val;
	__u8   use_xfer_cnt;
	union fw_scsi_read_priv {
		struct fcoe_read_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r3_lo[2];
		} fcoe;
		struct iscsi_read_priv {
			__u8   r3[4];
		} iscsi;
	} u;
	__be32 xfer_cnt;
	__be32 ini_xfer_cnt;
	__be64 rsp_dmaaddr;
	__be32 rsp_dmalen;
	__be32 r4;
};

#define	S_FW_SCSI_READ_WR_OPCODE	24
#define	M_FW_SCSI_READ_WR_OPCODE	0xff
#define	V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
#define	G_FW_SCSI_READ_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)

#define	S_FW_SCSI_READ_WR_IMMDLEN	0
#define	M_FW_SCSI_READ_WR_IMMDLEN	0xff
#define	V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
#define	G_FW_SCSI_READ_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)

#define	S_FW_SCSI_READ_WR_FLOWID	8
#define	M_FW_SCSI_READ_WR_FLOWID	0xfffff
#define	V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
#define	G_FW_SCSI_READ_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)

#define	S_FW_SCSI_READ_WR_LEN16		0
#define	M_FW_SCSI_READ_WR_LEN16		0xff
#define	V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
#define	G_FW_SCSI_READ_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)

#define	S_FW_SCSI_READ_WR_CP_EN		6
#define	M_FW_SCSI_READ_WR_CP_EN		0x3
#define	V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
#define	G_FW_SCSI_READ_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)

#define	S_FW_SCSI_READ_WR_CLASS		4
#define	M_FW_SCSI_READ_WR_CLASS		0x3
#define	V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
#define	G_FW_SCSI_READ_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)

struct fw_scsi_cmd_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   tmo_val;
	__u8   r3;
	union fw_scsi_cmd_priv {
		struct fcoe_cmd_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r4_lo[2];
		} fcoe;
		struct iscsi_cmd_priv {
			__u8   r4[4];
		} iscsi;
	} u;
	__u8   r5[8];
	__be64 rsp_dmaaddr;
	__be32 rsp_dmalen;
	__be32 r6;
};

#define	S_FW_SCSI_CMD_WR_OPCODE		24
#define	M_FW_SCSI_CMD_WR_OPCODE		0xff
#define	V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
#define	G_FW_SCSI_CMD_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)

#define	S_FW_SCSI_CMD_WR_IMMDLEN	0
#define	M_FW_SCSI_CMD_WR_IMMDLEN	0xff
#define	V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
#define	G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)

#define	S_FW_SCSI_CMD_WR_FLOWID		8
#define	M_FW_SCSI_CMD_WR_FLOWID		0xfffff
#define	V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
#define	G_FW_SCSI_CMD_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)

#define	S_FW_SCSI_CMD_WR_LEN16		0
#define	M_FW_SCSI_CMD_WR_LEN16		0xff
#define	V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
#define	G_FW_SCSI_CMD_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)

#define	S_FW_SCSI_CMD_WR_CP_EN		6
#define	M_FW_SCSI_CMD_WR_CP_EN		0x3
#define	V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
#define	G_FW_SCSI_CMD_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)

#define	S_FW_SCSI_CMD_WR_CLASS		4
#define	M_FW_SCSI_CMD_WR_CLASS		0x3
#define	V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
#define	G_FW_SCSI_CMD_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)

struct fw_scsi_abrt_cls_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   tmo_val;
	__u8   sub_opcode_to_chk_all_io;
	__u8   r3[4];
	__be64 t_cookie;
};

#define	S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
#define	M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
#define	V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
#define	G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)

#define	S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
#define	M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
#define	V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
	((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
#define	G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)

#define	S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
#define	M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
#define	V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
#define	G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)

#define	S_FW_SCSI_ABRT_CLS_WR_LEN16	0
#define	M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
#define	V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
#define	G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)

#define	S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
#define	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
#define	V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
	((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
#define	G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
	M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)

#define	S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
#define	M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
#define	V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
#define	G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
#define	F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)

#define	S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
#define	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
#define	V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
	((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
#define	G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
	(((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
	M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
#define	F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
    V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)

struct fw_scsi_tgt_acc_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   r3;
	__u8   use_burst_len;
	union fw_scsi_tgt_acc_priv {
		struct fcoe_tgt_acc_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r4_lo[2];
		} fcoe;
		struct iscsi_tgt_acc_priv {
			__u8   r4[4];
		} iscsi;
	} u;
	__be32 burst_len;
	__be32 rel_off;
	__be64 r5;
	__be32 r6;
	__be32 tot_xfer_len;
};

#define	S_FW_SCSI_TGT_ACC_WR_OPCODE	24
#define	M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
#define	V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
#define	G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)

#define	S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
#define	M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
#define	V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
#define	G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)

#define	S_FW_SCSI_TGT_ACC_WR_FLOWID	8
#define	M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
#define	V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
#define	G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)

#define	S_FW_SCSI_TGT_ACC_WR_LEN16	0
#define	M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
#define	V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
#define	G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)

#define	S_FW_SCSI_TGT_ACC_WR_CP_EN	6
#define	M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
#define	V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
#define	G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)

#define	S_FW_SCSI_TGT_ACC_WR_CLASS	4
#define	M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
#define	V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
#define	G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)

struct fw_scsi_tgt_xmit_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   auto_rsp;
	__u8   use_xfer_cnt;
	union fw_scsi_tgt_xmit_priv {
		struct fcoe_tgt_xmit_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r3_lo[2];
		} fcoe;
		struct iscsi_tgt_xmit_priv {
			__u8   r3[4];
		} iscsi;
	} u;
	__be32 xfer_cnt;
	__be32 r4;
	__be64 r5;
	__be32 r6;
	__be32 tot_xfer_len;
};

#define	S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
#define	M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
#define	V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
#define	G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)

#define	S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
#define	M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
#define	V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
	((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
#define	G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)

#define	S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
#define	M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
#define	V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
#define	G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)

#define	S_FW_SCSI_TGT_XMIT_WR_LEN16	0
#define	M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
#define	V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
#define	G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)

#define	S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
#define	M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
#define	V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
#define	G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)

#define	S_FW_SCSI_TGT_XMIT_WR_CLASS	4
#define	M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
#define	V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
#define	G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)

struct fw_scsi_tgt_rsp_wr {
	__be32 op_immdlen;
	__be32 flowid_len16;
	__be64 cookie;
	__be16 iqid;
	__u8   r3[2];
	union fw_scsi_tgt_rsp_priv {
		struct fcoe_tgt_rsp_priv {
			__u8   ctl_pri;
			__u8   cp_en_class;
			__u8   r4_lo[2];
		} fcoe;
		struct iscsi_tgt_rsp_priv {
			__u8   r4[4];
		} iscsi;
	} u;
	__u8   r5[8];
};

#define	S_FW_SCSI_TGT_RSP_WR_OPCODE	24
#define	M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
#define	V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
#define	G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)

#define	S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
#define	M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
#define	V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
#define	G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)

#define	S_FW_SCSI_TGT_RSP_WR_FLOWID	8
#define	M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
#define	V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
#define	G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)

#define	S_FW_SCSI_TGT_RSP_WR_LEN16	0
#define	M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
#define	V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
#define	G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)

#define	S_FW_SCSI_TGT_RSP_WR_CP_EN	6
#define	M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
#define	V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
#define	G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)

#define	S_FW_SCSI_TGT_RSP_WR_CLASS	4
#define	M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
#define	V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
#define	G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
	(((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)

struct fw_pofcoe_tcb_wr {
	__be32 op_compl;
	__be32 equiq_to_len16;
	__be64 cookie;
	__be32 tid_to_port;
	__be16 x_id;
	__be16 vlan_id;
	__be32 s_id;
	__be32 d_id;
	__be32 tag;
	__be32 xfer_len;
	__be32 r4;
	__be16 r5;
	__be16 iqid;
};

#define S_FW_POFCOE_TCB_WR_TID		12
#define M_FW_POFCOE_TCB_WR_TID		0xfffff
#define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
#define G_FW_POFCOE_TCB_WR_TID(x)	\
    (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)

#define S_FW_POFCOE_TCB_WR_ALLO		4
#define M_FW_POFCOE_TCB_WR_ALLOC	0x1
#define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
#define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
    (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
#define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)

#define S_FW_POFCOE_TCB_WR_FREE		3
#define M_FW_POFCOE_TCB_WR_FREE		0x1
#define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
#define G_FW_POFCOE_TCB_WR_FREE(x)	\
    (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
#define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)

#define S_FW_POFCOE_TCB_WR_PORT		0
#define M_FW_POFCOE_TCB_WR_PORT		0x7
#define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
#define G_FW_POFCOE_TCB_WR_PORT(x)	\
    (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)

struct fw_pofcoe_ulptx_wr {
	__be32 op_pkd;
	__be32 equiq_to_len16;
	__u64  cookie;
};


/*
 *	*******************
 *	  C O M M A N D s
 *	*******************
 */

/*
 * The maximum length of time, in miliseconds, that we expect any firmware
 * command to take to execute and return a reply to the host.  The RESET
 * and INITIALIZE commands can take a fair amount of time to execute but
 * most execute in far less time than this maximum.  This constant is used
 * by host software to determine how long to wait for a firmware command
 * reply before declaring the firmware as dead/unreachable ...
 */
#define	FW_CMD_MAX_TIMEOUT	10000

/*
 * If a host driver does a HELLO and discovers that there's already a MASTER
 * selected, we may have to wait for that MASTER to finish issuing RESET,
 * configuration and INITIALIZE commands.  Also, there's a possibility that
 * our own HELLO may get lost if it happens right as the MASTER is issuign a
 * RESET command, so we need to be willing to make a few retries of our HELLO.
 */
#define	FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
#define	FW_CMD_HELLO_RETRIES	3

enum fw_cmd_opcodes {
	FW_LDST_CMD		= 0x01,
	FW_RESET_CMD		= 0x03,
	FW_HELLO_CMD		= 0x04,
	FW_BYE_CMD		= 0x05,
	FW_INITIALIZE_CMD	= 0x06,
	FW_CAPS_CONFIG_CMD	= 0x07,
	FW_PARAMS_CMD		= 0x08,
	FW_PFVF_CMD		= 0x09,
	FW_IQ_CMD		= 0x10,
	FW_EQ_MNGT_CMD		= 0x11,
	FW_EQ_ETH_CMD		= 0x12,
	FW_EQ_CTRL_CMD		= 0x13,
	FW_EQ_OFLD_CMD		= 0x21,
	FW_VI_CMD		= 0x14,
	FW_VI_MAC_CMD		= 0x15,
	FW_VI_RXMODE_CMD	= 0x16,
	FW_VI_ENABLE_CMD	= 0x17,
	FW_VI_STATS_CMD		= 0x1a,
	FW_ACL_MAC_CMD		= 0x18,
	FW_ACL_VLAN_CMD		= 0x19,
	FW_PORT_CMD		= 0x1b,
	FW_PORT_STATS_CMD	= 0x1c,
	FW_PORT_LB_STATS_CMD	= 0x1d,
	FW_PORT_TRACE_CMD	= 0x1e,
	FW_PORT_TRACE_MMAP_CMD	= 0x1f,
	FW_RSS_IND_TBL_CMD	= 0x20,
	FW_RSS_GLB_CONFIG_CMD	= 0x22,
	FW_RSS_VI_CONFIG_CMD	= 0x23,
	FW_SCHED_CMD		= 0x24,
	FW_DEVLOG_CMD		= 0x25,
	FW_WATCHDOG_CMD		= 0x27,
	FW_CLIP_CMD		= 0x28,
	FW_CHNET_IFACE_CMD	= 0x26,
	FW_FCOE_RES_INFO_CMD	= 0x31,
	FW_FCOE_LINK_CMD	= 0x32,
	FW_FCOE_VNP_CMD		= 0x33,
	FW_FCOE_SPARAMS_CMD	= 0x35,
	FW_FCOE_STATS_CMD	= 0x37,
	FW_FCOE_FCF_CMD		= 0x38,
	FW_LASTC2E_CMD		= 0x40,
	FW_ERROR_CMD		= 0x80,
	FW_DEBUG_CMD		= 0x81,
};

enum fw_cmd_cap {
	FW_CMD_CAP_PF		= 0x01,
	FW_CMD_CAP_DMAQ		= 0x02,
	FW_CMD_CAP_PORT		= 0x04,
	FW_CMD_CAP_PORTPROMISC	= 0x08,
	FW_CMD_CAP_PORTSTATS	= 0x10,
	FW_CMD_CAP_VF		= 0x80,
};

/*
 * Generic command header flit0
 */
struct fw_cmd_hdr {
	__be32 hi;
	__be32 lo;
};

#define	S_FW_CMD_OP		24
#define	M_FW_CMD_OP		0xff
#define	V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
#define	G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)

#define	S_FW_CMD_REQUEST	23
#define	M_FW_CMD_REQUEST	0x1
#define	V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
#define	G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
#define	F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)

#define	S_FW_CMD_READ		22
#define	M_FW_CMD_READ		0x1
#define	V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
#define	G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
#define	F_FW_CMD_READ		V_FW_CMD_READ(1U)

#define	S_FW_CMD_WRITE		21
#define	M_FW_CMD_WRITE		0x1
#define	V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
#define	G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
#define	F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)

#define	S_FW_CMD_EXEC		20
#define	M_FW_CMD_EXEC		0x1
#define	V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
#define	G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
#define	F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)

#define	S_FW_CMD_RAMASK		20
#define	M_FW_CMD_RAMASK		0xf
#define	V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
#define	G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)

#define	S_FW_CMD_RETVAL		8
#define	M_FW_CMD_RETVAL		0xff
#define	V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
#define	G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)

#define	S_FW_CMD_LEN16		0
#define	M_FW_CMD_LEN16		0xff
#define	V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
#define	G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)

#define	FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16)

/*
 *	address spaces
 */
enum fw_ldst_addrspc {
	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
	FW_LDST_ADDRSPC_TP_PIO	  = 0x0010,
	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
	FW_LDST_ADDRSPC_TP_MIB	  = 0x0012,
	FW_LDST_ADDRSPC_MDIO	  = 0x0018,
	FW_LDST_ADDRSPC_MPS	  = 0x0020,
	FW_LDST_ADDRSPC_FUNC	  = 0x0028,
	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
	FW_LDST_ADDRSPC_LE	  = 0x0030,
	FW_LDST_ADDRSPC_I2C       = 0x0038,
	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
	FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,
};

/*
 *	MDIO VSC8634 register access control field
 */
enum fw_ldst_mdio_vsc8634_aid {
	FW_LDST_MDIO_VS_STANDARD,
	FW_LDST_MDIO_VS_EXTENDED,
	FW_LDST_MDIO_VS_GPIO
};

enum fw_ldst_mps_fid {
	FW_LDST_MPS_ATRB,
	FW_LDST_MPS_RPLC
};