1 /* 2 * Chelsio Terminator 4 (T4) Firmware interface header file. 3 * 4 * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 5 * 6 * Written by felix marti (felix@chelsio.com) 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 11 * release for licensing terms and conditions. 12 */ 13 14 #ifndef _T4FW_INTERFACE_H_ 15 #define _T4FW_INTERFACE_H_ 16 17 /****************************************************************************** 18 * R E T U R N V A L U E S 19 ********************************/ 20 21 enum fw_retval { 22 FW_SUCCESS = 0, /* completed sucessfully */ 23 FW_EPERM = 1, /* operation not permitted */ 24 FW_ENOENT = 2, /* no such file or directory */ 25 FW_EIO = 5, /* input/output error; hw bad */ 26 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 27 FW_EAGAIN = 11, /* try again */ 28 FW_ENOMEM = 12, /* out of memory */ 29 FW_EFAULT = 14, /* bad address; fw bad */ 30 FW_EBUSY = 16, /* resource busy */ 31 FW_EEXIST = 17, /* file exists */ 32 FW_ENODEV = 19, /* no such device */ 33 FW_EINVAL = 22, /* invalid argument */ 34 FW_ENOSPC = 28, /* no space left on device */ 35 FW_ENOSYS = 38, /* functionality not implemented */ 36 FW_ENODATA = 61, /* no data available */ 37 FW_EPROTO = 71, /* protocol error */ 38 FW_EADDRINUSE = 98, /* address already in use */ 39 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 40 FW_ENETDOWN = 100, /* network is down */ 41 FW_ENETUNREACH = 101, /* network is unreachable */ 42 FW_ENOBUFS = 105, /* no buffer space available */ 43 FW_ETIMEDOUT = 110, /* timeout */ 44 FW_EINPROGRESS = 115, /* fw internal */ 45 FW_SCSI_ABORT_REQUESTED = 128, /* */ 46 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 47 FW_SCSI_ABORTED = 130, /* */ 48 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 49 FW_ERR_LINK_DOWN = 132, /* */ 50 FW_RDEV_NOT_READY = 133, /* */ 51 FW_ERR_RDEV_LOST = 134, /* */ 52 FW_ERR_RDEV_LOGO = 135, /* */ 53 FW_FCOE_NO_XCHG = 136, /* */ 54 FW_SCSI_RSP_ERR = 137, /* */ 55 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 56 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 57 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 58 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 59 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 60 }; 61 62 /****************************************************************************** 63 * M E M O R Y T Y P E s 64 ******************************/ 65 66 enum fw_memtype { 67 FW_MEMTYPE_EDC0 = 0x0, 68 FW_MEMTYPE_EDC1 = 0x1, 69 FW_MEMTYPE_EXTMEM = 0x2, 70 FW_MEMTYPE_FLASH = 0x4, 71 FW_MEMTYPE_INTERNAL = 0x5, 72 FW_MEMTYPE_EXTMEM1 = 0x6, 73 FW_MEMTYPE_HMA = 0x7, 74 }; 75 76 /****************************************************************************** 77 * W O R K R E Q U E S T s 78 ********************************/ 79 80 enum fw_wr_opcodes { 81 FW_FRAG_WR = 0x1d, 82 FW_FILTER_WR = 0x02, 83 FW_ULPTX_WR = 0x04, 84 FW_TP_WR = 0x05, 85 FW_ETH_TX_PKT_WR = 0x08, 86 FW_ETH_TX_PKT2_WR = 0x44, 87 FW_ETH_TX_PKTS_WR = 0x09, 88 FW_ETH_TX_PKTS2_WR = 0x78, 89 FW_ETH_TX_EO_WR = 0x1c, 90 FW_EQ_FLUSH_WR = 0x1b, 91 FW_OFLD_CONNECTION_WR = 0x2f, 92 FW_FLOWC_WR = 0x0a, 93 FW_OFLD_TX_DATA_WR = 0x0b, 94 FW_CMD_WR = 0x10, 95 FW_ETH_TX_PKT_VM_WR = 0x11, 96 FW_ETH_TX_PKTS_VM_WR = 0x12, 97 FW_RI_RES_WR = 0x0c, 98 FW_RI_RDMA_WRITE_WR = 0x14, 99 FW_RI_SEND_WR = 0x15, 100 FW_RI_RDMA_READ_WR = 0x16, 101 FW_RI_RECV_WR = 0x17, 102 FW_RI_BIND_MW_WR = 0x18, 103 FW_RI_FR_NSMR_WR = 0x19, 104 FW_RI_FR_NSMR_TPTE_WR = 0x20, 105 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 106 FW_RI_INV_LSTAG_WR = 0x1a, 107 FW_RI_SEND_IMMEDIATE_WR = 0x15, 108 FW_RI_ATOMIC_WR = 0x16, 109 FW_RI_WR = 0x0d, 110 FW_CHNET_IFCONF_WR = 0x6b, 111 FW_RDEV_WR = 0x38, 112 FW_FOISCSI_NODE_WR = 0x60, 113 FW_FOISCSI_CTRL_WR = 0x6a, 114 FW_FOISCSI_CHAP_WR = 0x6c, 115 FW_FCOE_ELS_CT_WR = 0x30, 116 FW_SCSI_WRITE_WR = 0x31, 117 FW_SCSI_READ_WR = 0x32, 118 FW_SCSI_CMD_WR = 0x33, 119 FW_SCSI_ABRT_CLS_WR = 0x34, 120 FW_SCSI_TGT_ACC_WR = 0x35, 121 FW_SCSI_TGT_XMIT_WR = 0x36, 122 FW_SCSI_TGT_RSP_WR = 0x37, 123 FW_POFCOE_TCB_WR = 0x42, 124 FW_POFCOE_ULPTX_WR = 0x43, 125 FW_ISCSI_TX_DATA_WR = 0x45, 126 FW_PTP_TX_PKT_WR = 0x46, 127 FW_TLSTX_DATA_WR = 0x68, 128 FW_TLS_KEYCTX_TX_WR = 0x69, 129 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 130 FW_COiSCSI_TGT_WR = 0x70, 131 FW_COiSCSI_TGT_CONN_WR = 0x71, 132 FW_COiSCSI_TGT_XMIT_WR = 0x72, 133 FW_ISNS_WR = 0x75, 134 FW_ISNS_XMIT_WR = 0x76, 135 FW_FILTER2_WR = 0x77, 136 FW_LASTC2E_WR = 0x80 137 }; 138 139 /* 140 * Generic work request header flit0 141 */ 142 struct fw_wr_hdr { 143 __be32 hi; 144 __be32 lo; 145 }; 146 147 /* work request opcode (hi) 148 */ 149 #define S_FW_WR_OP 24 150 #define M_FW_WR_OP 0xff 151 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 152 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 153 154 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 155 */ 156 #define S_FW_WR_ATOMIC 23 157 #define M_FW_WR_ATOMIC 0x1 158 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 159 #define G_FW_WR_ATOMIC(x) \ 160 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 161 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 162 163 /* flush flag (hi) - firmware flushes flushable work request buffered 164 * in the flow context. 165 */ 166 #define S_FW_WR_FLUSH 22 167 #define M_FW_WR_FLUSH 0x1 168 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 169 #define G_FW_WR_FLUSH(x) \ 170 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 171 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 172 173 /* completion flag (hi) - firmware generates a cpl_fw6_ack 174 */ 175 #define S_FW_WR_COMPL 21 176 #define M_FW_WR_COMPL 0x1 177 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 178 #define G_FW_WR_COMPL(x) \ 179 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 180 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 181 182 183 /* work request immediate data lengh (hi) 184 */ 185 #define S_FW_WR_IMMDLEN 0 186 #define M_FW_WR_IMMDLEN 0xff 187 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 188 #define G_FW_WR_IMMDLEN(x) \ 189 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 190 191 /* egress queue status update to associated ingress queue entry (lo) 192 */ 193 #define S_FW_WR_EQUIQ 31 194 #define M_FW_WR_EQUIQ 0x1 195 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 196 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 197 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 198 199 /* egress queue status update to egress queue status entry (lo) 200 */ 201 #define S_FW_WR_EQUEQ 30 202 #define M_FW_WR_EQUEQ 0x1 203 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 204 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 205 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 206 207 /* flow context identifier (lo) 208 */ 209 #define S_FW_WR_FLOWID 8 210 #define M_FW_WR_FLOWID 0xfffff 211 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 212 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 213 214 /* length in units of 16-bytes (lo) 215 */ 216 #define S_FW_WR_LEN16 0 217 #define M_FW_WR_LEN16 0xff 218 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 219 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 220 221 struct fw_frag_wr { 222 __be32 op_to_fragoff16; 223 __be32 flowid_len16; 224 __be64 r4; 225 }; 226 227 #define S_FW_FRAG_WR_EOF 15 228 #define M_FW_FRAG_WR_EOF 0x1 229 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 230 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 231 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 232 233 #define S_FW_FRAG_WR_FRAGOFF16 8 234 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 235 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 236 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 237 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 238 239 /* valid filter configurations for compressed tuple 240 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 241 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 242 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 243 * OV - Outer VLAN/VNIC_ID, 244 */ 245 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 246 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 247 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 248 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 249 #define HW_TPL_FR_MT_E_PR_T 0x370 250 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 251 #define HW_TPL_FR_MT_E_T_P_FC 0X353 252 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 253 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 254 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 255 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 256 #define HW_TPL_FR_M_E_PR_FC 0X2E1 257 #define HW_TPL_FR_M_E_T_FC 0X2D1 258 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 259 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 260 #define HW_TPL_FR_M_T_IV_FC 0X299 261 #define HW_TPL_FR_M_T_OV_FC 0X295 262 #define HW_TPL_FR_E_PR_T_P 0X272 263 #define HW_TPL_FR_E_PR_T_FC 0X271 264 #define HW_TPL_FR_E_IV_FC 0X249 265 #define HW_TPL_FR_E_OV_FC 0X245 266 #define HW_TPL_FR_PR_T_IV_FC 0X239 267 #define HW_TPL_FR_PR_T_OV_FC 0X235 268 #define HW_TPL_FR_IV_OV_FC 0X20D 269 #define HW_TPL_MT_M_E_PR 0X1E0 270 #define HW_TPL_MT_M_E_T 0X1D0 271 #define HW_TPL_MT_E_PR_T_FC 0X171 272 #define HW_TPL_MT_E_IV 0X148 273 #define HW_TPL_MT_E_OV 0X144 274 #define HW_TPL_MT_PR_T_IV 0X138 275 #define HW_TPL_MT_PR_T_OV 0X134 276 #define HW_TPL_M_E_PR_P 0X0E2 277 #define HW_TPL_M_E_T_P 0X0D2 278 #define HW_TPL_E_PR_T_P_FC 0X073 279 #define HW_TPL_E_IV_P 0X04A 280 #define HW_TPL_E_OV_P 0X046 281 #define HW_TPL_PR_T_IV_P 0X03A 282 #define HW_TPL_PR_T_OV_P 0X036 283 284 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 285 enum fw_filter_wr_cookie { 286 FW_FILTER_WR_SUCCESS, 287 FW_FILTER_WR_FLT_ADDED, 288 FW_FILTER_WR_FLT_DELETED, 289 FW_FILTER_WR_SMT_TBL_FULL, 290 FW_FILTER_WR_EINVAL, 291 }; 292 293 enum fw_filter_wr_nat_mode { 294 FW_FILTER_WR_NATMODE_NONE = 0, 295 FW_FILTER_WR_NATMODE_DIP , 296 FW_FILTER_WR_NATMODE_DIPDP, 297 FW_FILTER_WR_NATMODE_DIPDPSIP, 298 FW_FILTER_WR_NATMODE_DIPDPSP, 299 FW_FILTER_WR_NATMODE_SIPSP, 300 FW_FILTER_WR_NATMODE_DIPSIPSP, 301 FW_FILTER_WR_NATMODE_FOURTUPLE, 302 }; 303 304 struct fw_filter_wr { 305 __be32 op_pkd; 306 __be32 len16_pkd; 307 __be64 r3; 308 __be32 tid_to_iq; 309 __be32 del_filter_to_l2tix; 310 __be16 ethtype; 311 __be16 ethtypem; 312 __u8 frag_to_ovlan_vldm; 313 __u8 smac_sel; 314 __be16 rx_chan_rx_rpl_iq; 315 __be32 maci_to_matchtypem; 316 __u8 ptcl; 317 __u8 ptclm; 318 __u8 ttyp; 319 __u8 ttypm; 320 __be16 ivlan; 321 __be16 ivlanm; 322 __be16 ovlan; 323 __be16 ovlanm; 324 __u8 lip[16]; 325 __u8 lipm[16]; 326 __u8 fip[16]; 327 __u8 fipm[16]; 328 __be16 lp; 329 __be16 lpm; 330 __be16 fp; 331 __be16 fpm; 332 __be16 r7; 333 __u8 sma[6]; 334 }; 335 336 struct fw_filter2_wr { 337 __be32 op_pkd; 338 __be32 len16_pkd; 339 __be64 r3; 340 __be32 tid_to_iq; 341 __be32 del_filter_to_l2tix; 342 __be16 ethtype; 343 __be16 ethtypem; 344 __u8 frag_to_ovlan_vldm; 345 __u8 smac_sel; 346 __be16 rx_chan_rx_rpl_iq; 347 __be32 maci_to_matchtypem; 348 __u8 ptcl; 349 __u8 ptclm; 350 __u8 ttyp; 351 __u8 ttypm; 352 __be16 ivlan; 353 __be16 ivlanm; 354 __be16 ovlan; 355 __be16 ovlanm; 356 __u8 lip[16]; 357 __u8 lipm[16]; 358 __u8 fip[16]; 359 __u8 fipm[16]; 360 __be16 lp; 361 __be16 lpm; 362 __be16 fp; 363 __be16 fpm; 364 __be16 r7; 365 __u8 sma[6]; 366 __be16 r8; 367 __u8 filter_type_swapmac; 368 __u8 natmode_to_ulp_type; 369 __be16 newlport; 370 __be16 newfport; 371 __u8 newlip[16]; 372 __u8 newfip[16]; 373 __be32 natseqcheck; 374 __be32 r9; 375 __be64 r10; 376 __be64 r11; 377 __be64 r12; 378 __be64 r13; 379 }; 380 381 #define S_FW_FILTER_WR_TID 12 382 #define M_FW_FILTER_WR_TID 0xfffff 383 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 384 #define G_FW_FILTER_WR_TID(x) \ 385 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 386 387 #define S_FW_FILTER_WR_RQTYPE 11 388 #define M_FW_FILTER_WR_RQTYPE 0x1 389 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 390 #define G_FW_FILTER_WR_RQTYPE(x) \ 391 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 392 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 393 394 #define S_FW_FILTER_WR_NOREPLY 10 395 #define M_FW_FILTER_WR_NOREPLY 0x1 396 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 397 #define G_FW_FILTER_WR_NOREPLY(x) \ 398 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 399 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 400 401 #define S_FW_FILTER_WR_IQ 0 402 #define M_FW_FILTER_WR_IQ 0x3ff 403 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 404 #define G_FW_FILTER_WR_IQ(x) \ 405 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 406 407 #define S_FW_FILTER_WR_DEL_FILTER 31 408 #define M_FW_FILTER_WR_DEL_FILTER 0x1 409 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 410 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 411 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 412 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 413 414 #define S_FW_FILTER2_WR_DROP_ENCAP 30 415 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 416 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 417 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 418 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 419 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 420 421 #define S_FW_FILTER2_WR_TX_LOOP 29 422 #define M_FW_FILTER2_WR_TX_LOOP 0x1 423 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 424 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 425 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 426 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 427 428 #define S_FW_FILTER_WR_RPTTID 25 429 #define M_FW_FILTER_WR_RPTTID 0x1 430 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 431 #define G_FW_FILTER_WR_RPTTID(x) \ 432 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 433 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 434 435 #define S_FW_FILTER_WR_DROP 24 436 #define M_FW_FILTER_WR_DROP 0x1 437 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 438 #define G_FW_FILTER_WR_DROP(x) \ 439 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 440 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 441 442 #define S_FW_FILTER_WR_DIRSTEER 23 443 #define M_FW_FILTER_WR_DIRSTEER 0x1 444 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 445 #define G_FW_FILTER_WR_DIRSTEER(x) \ 446 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 447 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 448 449 #define S_FW_FILTER_WR_MASKHASH 22 450 #define M_FW_FILTER_WR_MASKHASH 0x1 451 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 452 #define G_FW_FILTER_WR_MASKHASH(x) \ 453 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 454 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 455 456 #define S_FW_FILTER_WR_DIRSTEERHASH 21 457 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 458 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 459 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 460 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 461 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 462 463 #define S_FW_FILTER_WR_LPBK 20 464 #define M_FW_FILTER_WR_LPBK 0x1 465 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 466 #define G_FW_FILTER_WR_LPBK(x) \ 467 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 468 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 469 470 #define S_FW_FILTER_WR_DMAC 19 471 #define M_FW_FILTER_WR_DMAC 0x1 472 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 473 #define G_FW_FILTER_WR_DMAC(x) \ 474 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 475 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 476 477 #define S_FW_FILTER_WR_SMAC 18 478 #define M_FW_FILTER_WR_SMAC 0x1 479 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 480 #define G_FW_FILTER_WR_SMAC(x) \ 481 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 482 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 483 484 #define S_FW_FILTER_WR_INSVLAN 17 485 #define M_FW_FILTER_WR_INSVLAN 0x1 486 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 487 #define G_FW_FILTER_WR_INSVLAN(x) \ 488 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 489 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 490 491 #define S_FW_FILTER_WR_RMVLAN 16 492 #define M_FW_FILTER_WR_RMVLAN 0x1 493 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 494 #define G_FW_FILTER_WR_RMVLAN(x) \ 495 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 496 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 497 498 #define S_FW_FILTER_WR_HITCNTS 15 499 #define M_FW_FILTER_WR_HITCNTS 0x1 500 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 501 #define G_FW_FILTER_WR_HITCNTS(x) \ 502 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 503 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 504 505 #define S_FW_FILTER_WR_TXCHAN 13 506 #define M_FW_FILTER_WR_TXCHAN 0x3 507 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 508 #define G_FW_FILTER_WR_TXCHAN(x) \ 509 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 510 511 #define S_FW_FILTER_WR_PRIO 12 512 #define M_FW_FILTER_WR_PRIO 0x1 513 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 514 #define G_FW_FILTER_WR_PRIO(x) \ 515 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 516 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 517 518 #define S_FW_FILTER_WR_L2TIX 0 519 #define M_FW_FILTER_WR_L2TIX 0xfff 520 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 521 #define G_FW_FILTER_WR_L2TIX(x) \ 522 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 523 524 #define S_FW_FILTER_WR_FRAG 7 525 #define M_FW_FILTER_WR_FRAG 0x1 526 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 527 #define G_FW_FILTER_WR_FRAG(x) \ 528 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 529 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 530 531 #define S_FW_FILTER_WR_FRAGM 6 532 #define M_FW_FILTER_WR_FRAGM 0x1 533 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 534 #define G_FW_FILTER_WR_FRAGM(x) \ 535 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 536 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 537 538 #define S_FW_FILTER_WR_IVLAN_VLD 5 539 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 540 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 541 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 542 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 543 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 544 545 #define S_FW_FILTER_WR_OVLAN_VLD 4 546 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 547 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 548 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 549 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 550 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 551 552 #define S_FW_FILTER_WR_IVLAN_VLDM 3 553 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 554 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 555 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 556 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 557 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 558 559 #define S_FW_FILTER_WR_OVLAN_VLDM 2 560 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 561 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 562 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 563 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 564 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 565 566 #define S_FW_FILTER_WR_RX_CHAN 15 567 #define M_FW_FILTER_WR_RX_CHAN 0x1 568 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 569 #define G_FW_FILTER_WR_RX_CHAN(x) \ 570 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 571 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 572 573 #define S_FW_FILTER_WR_RX_RPL_IQ 0 574 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 575 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 576 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 577 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 578 579 #define S_FW_FILTER2_WR_FILTER_TYPE 1 580 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 581 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 582 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 583 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 584 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 585 586 #define S_FW_FILTER2_WR_SWAPMAC 0 587 #define M_FW_FILTER2_WR_SWAPMAC 0x1 588 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 589 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 590 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 591 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 592 593 #define S_FW_FILTER2_WR_NATMODE 5 594 #define M_FW_FILTER2_WR_NATMODE 0x7 595 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 596 #define G_FW_FILTER2_WR_NATMODE(x) \ 597 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 598 599 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 600 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 601 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 602 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 603 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 604 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 605 606 #define S_FW_FILTER2_WR_ULP_TYPE 0 607 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 608 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 609 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 610 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 611 612 #define S_FW_FILTER_WR_MACI 23 613 #define M_FW_FILTER_WR_MACI 0x1ff 614 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 615 #define G_FW_FILTER_WR_MACI(x) \ 616 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 617 618 #define S_FW_FILTER_WR_MACIM 14 619 #define M_FW_FILTER_WR_MACIM 0x1ff 620 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 621 #define G_FW_FILTER_WR_MACIM(x) \ 622 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 623 624 #define S_FW_FILTER_WR_FCOE 13 625 #define M_FW_FILTER_WR_FCOE 0x1 626 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 627 #define G_FW_FILTER_WR_FCOE(x) \ 628 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 629 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 630 631 #define S_FW_FILTER_WR_FCOEM 12 632 #define M_FW_FILTER_WR_FCOEM 0x1 633 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 634 #define G_FW_FILTER_WR_FCOEM(x) \ 635 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 636 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 637 638 #define S_FW_FILTER_WR_PORT 9 639 #define M_FW_FILTER_WR_PORT 0x7 640 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 641 #define G_FW_FILTER_WR_PORT(x) \ 642 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 643 644 #define S_FW_FILTER_WR_PORTM 6 645 #define M_FW_FILTER_WR_PORTM 0x7 646 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 647 #define G_FW_FILTER_WR_PORTM(x) \ 648 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 649 650 #define S_FW_FILTER_WR_MATCHTYPE 3 651 #define M_FW_FILTER_WR_MATCHTYPE 0x7 652 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 653 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 654 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 655 656 #define S_FW_FILTER_WR_MATCHTYPEM 0 657 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 658 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 659 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 660 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 661 662 struct fw_ulptx_wr { 663 __be32 op_to_compl; 664 __be32 flowid_len16; 665 __u64 cookie; 666 }; 667 668 /* flag for packet type - control packet (0), data packet (1) 669 */ 670 #define S_FW_ULPTX_WR_DATA 28 671 #define M_FW_ULPTX_WR_DATA 0x1 672 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 673 #define G_FW_ULPTX_WR_DATA(x) \ 674 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 675 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 676 677 struct fw_tp_wr { 678 __be32 op_to_immdlen; 679 __be32 flowid_len16; 680 __u64 cookie; 681 }; 682 683 struct fw_eth_tx_pkt_wr { 684 __be32 op_immdlen; 685 __be32 equiq_to_len16; 686 __be64 r3; 687 }; 688 689 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 690 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 691 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 692 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 693 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 694 695 struct fw_eth_tx_pkt2_wr { 696 __be32 op_immdlen; 697 __be32 equiq_to_len16; 698 __be32 r3; 699 __be32 L4ChkDisable_to_IpHdrLen; 700 }; 701 702 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 703 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 704 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 705 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 706 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 707 708 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 709 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 710 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 711 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 712 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 713 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 714 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 715 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 716 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 717 718 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 719 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 720 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 721 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 722 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 723 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 724 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 725 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 726 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 727 728 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 729 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 730 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 731 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 732 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 733 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 734 735 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 736 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 737 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 738 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 739 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 740 741 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 742 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 743 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 744 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 745 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 746 747 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 748 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 749 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 750 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 751 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 752 753 struct fw_eth_tx_pkts_wr { 754 __be32 op_pkd; 755 __be32 equiq_to_len16; 756 __be32 r3; 757 __be16 plen; 758 __u8 npkt; 759 __u8 type; 760 }; 761 762 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 763 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 764 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 765 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 766 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 767 768 struct fw_eth_tx_pkt_ptp_wr { 769 __be32 op_immdlen; 770 __be32 equiq_to_len16; 771 __be64 r3; 772 }; 773 774 enum fw_eth_tx_eo_type { 775 FW_ETH_TX_EO_TYPE_UDPSEG, 776 FW_ETH_TX_EO_TYPE_TCPSEG, 777 FW_ETH_TX_EO_TYPE_NVGRESEG, 778 FW_ETH_TX_EO_TYPE_VXLANSEG, 779 FW_ETH_TX_EO_TYPE_GENEVESEG, 780 }; 781 782 struct fw_eth_tx_eo_wr { 783 __be32 op_immdlen; 784 __be32 equiq_to_len16; 785 __be64 r3; 786 union fw_eth_tx_eo { 787 struct fw_eth_tx_eo_udpseg { 788 __u8 type; 789 __u8 ethlen; 790 __be16 iplen; 791 __u8 udplen; 792 __u8 rtplen; 793 __be16 r4; 794 __be16 mss; 795 __be16 schedpktsize; 796 __be32 plen; 797 } udpseg; 798 struct fw_eth_tx_eo_tcpseg { 799 __u8 type; 800 __u8 ethlen; 801 __be16 iplen; 802 __u8 tcplen; 803 __u8 tsclk_tsoff; 804 __be16 r4; 805 __be16 mss; 806 __be16 r5; 807 __be32 plen; 808 } tcpseg; 809 struct fw_eth_tx_eo_nvgreseg { 810 __u8 type; 811 __u8 iphdroffout; 812 __be16 grehdroff; 813 __be16 iphdroffin; 814 __be16 tcphdroffin; 815 __be16 mss; 816 __be16 r4; 817 __be32 plen; 818 } nvgreseg; 819 struct fw_eth_tx_eo_vxlanseg { 820 __u8 type; 821 __u8 iphdroffout; 822 __be16 vxlanhdroff; 823 __be16 iphdroffin; 824 __be16 tcphdroffin; 825 __be16 mss; 826 __be16 r4; 827 __be32 plen; 828 829 } vxlanseg; 830 struct fw_eth_tx_eo_geneveseg { 831 __u8 type; 832 __u8 iphdroffout; 833 __be16 genevehdroff; 834 __be16 iphdroffin; 835 __be16 tcphdroffin; 836 __be16 mss; 837 __be16 r4; 838 __be32 plen; 839 } geneveseg; 840 } u; 841 }; 842 843 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 844 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 845 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 846 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 847 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 848 849 #define S_FW_ETH_TX_EO_WR_TSCLK 6 850 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 851 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 852 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 853 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 854 855 #define S_FW_ETH_TX_EO_WR_TSOFF 0 856 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 857 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 858 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 859 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 860 861 struct fw_eq_flush_wr { 862 __u8 opcode; 863 __u8 r1[3]; 864 __be32 equiq_to_len16; 865 __be64 r3; 866 }; 867 868 struct fw_ofld_connection_wr { 869 __be32 op_compl; 870 __be32 len16_pkd; 871 __u64 cookie; 872 __be64 r2; 873 __be64 r3; 874 struct fw_ofld_connection_le { 875 __be32 version_cpl; 876 __be32 filter; 877 __be32 r1; 878 __be16 lport; 879 __be16 pport; 880 union fw_ofld_connection_leip { 881 struct fw_ofld_connection_le_ipv4 { 882 __be32 pip; 883 __be32 lip; 884 __be64 r0; 885 __be64 r1; 886 __be64 r2; 887 } ipv4; 888 struct fw_ofld_connection_le_ipv6 { 889 __be64 pip_hi; 890 __be64 pip_lo; 891 __be64 lip_hi; 892 __be64 lip_lo; 893 } ipv6; 894 } u; 895 } le; 896 struct fw_ofld_connection_tcb { 897 __be32 t_state_to_astid; 898 __be16 cplrxdataack_cplpassacceptrpl; 899 __be16 rcv_adv; 900 __be32 rcv_nxt; 901 __be32 tx_max; 902 __be64 opt0; 903 __be32 opt2; 904 __be32 r1; 905 __be64 r2; 906 __be64 r3; 907 } tcb; 908 }; 909 910 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 911 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 912 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 913 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 914 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 915 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 916 M_FW_OFLD_CONNECTION_WR_VERSION) 917 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 918 919 #define S_FW_OFLD_CONNECTION_WR_CPL 30 920 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 921 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 922 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 923 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 924 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 925 926 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 927 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 928 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 929 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 930 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 931 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 932 M_FW_OFLD_CONNECTION_WR_T_STATE) 933 934 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 935 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 936 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 937 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 938 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 939 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 940 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 941 942 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 943 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 944 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 945 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 946 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 947 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 948 949 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 950 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 951 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 952 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 953 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 954 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 955 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 956 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 957 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 958 959 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 960 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 961 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 962 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 963 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 964 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 965 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 966 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 967 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 968 969 enum fw_flowc_mnem_tcpstate { 970 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 971 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 972 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 973 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 974 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 975 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 976 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 977 * will resend FIN - equiv ESTAB 978 */ 979 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 980 * will resend FIN but have 981 * received FIN 982 */ 983 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 984 * will resend FIN but have 985 * received FIN 986 */ 987 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 988 * waiting for FIN 989 */ 990 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 991 }; 992 993 enum fw_flowc_mnem_eostate { 994 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 995 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 996 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 997 * outstanding payload 998 */ 999 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1000 * discarding outstanding payload 1001 */ 1002 }; 1003 1004 enum fw_flowc_mnem { 1005 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1006 FW_FLOWC_MNEM_CH = 1, 1007 FW_FLOWC_MNEM_PORT = 2, 1008 FW_FLOWC_MNEM_IQID = 3, 1009 FW_FLOWC_MNEM_SNDNXT = 4, 1010 FW_FLOWC_MNEM_RCVNXT = 5, 1011 FW_FLOWC_MNEM_SNDBUF = 6, 1012 FW_FLOWC_MNEM_MSS = 7, 1013 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1014 FW_FLOWC_MNEM_TCPSTATE = 9, 1015 FW_FLOWC_MNEM_EOSTATE = 10, 1016 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1017 FW_FLOWC_MNEM_DCBPRIO = 12, 1018 FW_FLOWC_MNEM_SND_SCALE = 13, 1019 FW_FLOWC_MNEM_RCV_SCALE = 14, 1020 FW_FLOWC_MNEM_ULP_MODE = 15, 1021 FW_FLOWC_MNEM_MAX = 16, 1022 }; 1023 1024 struct fw_flowc_mnemval { 1025 __u8 mnemonic; 1026 __u8 r4[3]; 1027 __be32 val; 1028 }; 1029 1030 struct fw_flowc_wr { 1031 __be32 op_to_nparams; 1032 __be32 flowid_len16; 1033 #ifndef C99_NOT_SUPPORTED 1034 struct fw_flowc_mnemval mnemval[0]; 1035 #endif 1036 }; 1037 1038 #define S_FW_FLOWC_WR_NPARAMS 0 1039 #define M_FW_FLOWC_WR_NPARAMS 0xff 1040 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1041 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1042 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1043 1044 struct fw_ofld_tx_data_wr { 1045 __be32 op_to_immdlen; 1046 __be32 flowid_len16; 1047 __be32 plen; 1048 __be32 lsodisable_to_flags; 1049 }; 1050 1051 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1052 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1053 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1054 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1055 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1056 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1057 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1058 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1059 1060 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1061 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1062 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1063 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1064 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1065 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1066 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1067 1068 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1069 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1070 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1071 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1072 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1073 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1074 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1075 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1076 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1077 1078 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1079 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1080 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1081 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1082 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1083 1084 1085 /* Use fw_ofld_tx_data_wr structure */ 1086 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1087 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1088 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1089 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1090 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1091 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1092 1093 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1094 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1095 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1096 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1097 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1098 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1099 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1100 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1101 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1102 1103 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1104 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1105 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1106 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1107 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1108 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1109 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1110 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1111 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1112 1113 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1114 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1115 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1116 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1117 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1118 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1119 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1120 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1121 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1122 1123 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1124 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1125 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1126 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1127 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1128 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1129 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1130 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1131 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1132 1133 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1134 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1135 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1136 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1137 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1138 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1139 1140 struct fw_cmd_wr { 1141 __be32 op_dma; 1142 __be32 len16_pkd; 1143 __be64 cookie_daddr; 1144 }; 1145 1146 #define S_FW_CMD_WR_DMA 17 1147 #define M_FW_CMD_WR_DMA 0x1 1148 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1149 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1150 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1151 1152 struct fw_eth_tx_pkt_vm_wr { 1153 __be32 op_immdlen; 1154 __be32 equiq_to_len16; 1155 __be32 r3[2]; 1156 __u8 ethmacdst[6]; 1157 __u8 ethmacsrc[6]; 1158 __be16 ethtype; 1159 __be16 vlantci; 1160 }; 1161 1162 struct fw_eth_tx_pkts_vm_wr { 1163 __be32 op_pkd; 1164 __be32 equiq_to_len16; 1165 __be32 r3; 1166 __be16 plen; 1167 __u8 npkt; 1168 __u8 r4; 1169 __u8 ethmacdst[6]; 1170 __u8 ethmacsrc[6]; 1171 __be16 ethtype; 1172 __be16 vlantci; 1173 }; 1174 1175 /****************************************************************************** 1176 * R I W O R K R E Q U E S T s 1177 **************************************/ 1178 1179 enum fw_ri_wr_opcode { 1180 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1181 FW_RI_READ_REQ = 0x1, 1182 FW_RI_READ_RESP = 0x2, 1183 FW_RI_SEND = 0x3, 1184 FW_RI_SEND_WITH_INV = 0x4, 1185 FW_RI_SEND_WITH_SE = 0x5, 1186 FW_RI_SEND_WITH_SE_INV = 0x6, 1187 FW_RI_TERMINATE = 0x7, 1188 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1189 FW_RI_BIND_MW = 0x9, 1190 FW_RI_FAST_REGISTER = 0xa, 1191 FW_RI_LOCAL_INV = 0xb, 1192 FW_RI_QP_MODIFY = 0xc, 1193 FW_RI_BYPASS = 0xd, 1194 FW_RI_RECEIVE = 0xe, 1195 #if 0 1196 FW_RI_SEND_IMMEDIATE = 0x8, 1197 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1198 FW_RI_ATOMIC_REQUEST = 0xa, 1199 FW_RI_ATOMIC_RESPONSE = 0xb, 1200 1201 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1202 FW_RI_FAST_REGISTER = 0xd, 1203 FW_RI_LOCAL_INV = 0xe, 1204 #endif 1205 FW_RI_SGE_EC_CR_RETURN = 0xf, 1206 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1207 }; 1208 1209 enum fw_ri_wr_flags { 1210 FW_RI_COMPLETION_FLAG = 0x01, 1211 FW_RI_NOTIFICATION_FLAG = 0x02, 1212 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1213 FW_RI_READ_FENCE_FLAG = 0x08, 1214 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1215 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1216 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1217 }; 1218 1219 enum fw_ri_mpa_attrs { 1220 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1221 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1222 FW_RI_MPA_CRC_ENABLE = 0x04, 1223 FW_RI_MPA_IETF_ENABLE = 0x08 1224 }; 1225 1226 enum fw_ri_qp_caps { 1227 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1228 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1229 FW_RI_QP_BIND_ENABLE = 0x04, 1230 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1231 FW_RI_QP_STAG0_ENABLE = 0x10, 1232 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1233 }; 1234 1235 enum fw_ri_addr_type { 1236 FW_RI_ZERO_BASED_TO = 0x00, 1237 FW_RI_VA_BASED_TO = 0x01 1238 }; 1239 1240 enum fw_ri_mem_perms { 1241 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1242 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1243 FW_RI_MEM_ACCESS_REM = 0x03, 1244 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1245 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1246 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1247 }; 1248 1249 enum fw_ri_stag_type { 1250 FW_RI_STAG_NSMR = 0x00, 1251 FW_RI_STAG_SMR = 0x01, 1252 FW_RI_STAG_MW = 0x02, 1253 FW_RI_STAG_MW_RELAXED = 0x03 1254 }; 1255 1256 enum fw_ri_data_op { 1257 FW_RI_DATA_IMMD = 0x81, 1258 FW_RI_DATA_DSGL = 0x82, 1259 FW_RI_DATA_ISGL = 0x83 1260 }; 1261 1262 enum fw_ri_sgl_depth { 1263 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1264 FW_RI_SGL_DEPTH_MAX_RQ = 4 1265 }; 1266 1267 enum fw_ri_cqe_err { 1268 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1269 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1270 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1271 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1272 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1273 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1274 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1275 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1276 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1277 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1278 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1279 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1280 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1281 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1282 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1283 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1284 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1285 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1286 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1287 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1288 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1289 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1290 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1291 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1292 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1293 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1294 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1295 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1296 1297 }; 1298 1299 struct fw_ri_dsge_pair { 1300 __be32 len[2]; 1301 __be64 addr[2]; 1302 }; 1303 1304 struct fw_ri_dsgl { 1305 __u8 op; 1306 __u8 r1; 1307 __be16 nsge; 1308 __be32 len0; 1309 __be64 addr0; 1310 #ifndef C99_NOT_SUPPORTED 1311 struct fw_ri_dsge_pair sge[0]; 1312 #endif 1313 }; 1314 1315 struct fw_ri_sge { 1316 __be32 stag; 1317 __be32 len; 1318 __be64 to; 1319 }; 1320 1321 struct fw_ri_isgl { 1322 __u8 op; 1323 __u8 r1; 1324 __be16 nsge; 1325 __be32 r2; 1326 #ifndef C99_NOT_SUPPORTED 1327 struct fw_ri_sge sge[0]; 1328 #endif 1329 }; 1330 1331 struct fw_ri_immd { 1332 __u8 op; 1333 __u8 r1; 1334 __be16 r2; 1335 __be32 immdlen; 1336 #ifndef C99_NOT_SUPPORTED 1337 __u8 data[0]; 1338 #endif 1339 }; 1340 1341 struct fw_ri_tpte { 1342 __be32 valid_to_pdid; 1343 __be32 locread_to_qpid; 1344 __be32 nosnoop_pbladdr; 1345 __be32 len_lo; 1346 __be32 va_hi; 1347 __be32 va_lo_fbo; 1348 __be32 dca_mwbcnt_pstag; 1349 __be32 len_hi; 1350 }; 1351 1352 #define S_FW_RI_TPTE_VALID 31 1353 #define M_FW_RI_TPTE_VALID 0x1 1354 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1355 #define G_FW_RI_TPTE_VALID(x) \ 1356 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1357 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1358 1359 #define S_FW_RI_TPTE_STAGKEY 23 1360 #define M_FW_RI_TPTE_STAGKEY 0xff 1361 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1362 #define G_FW_RI_TPTE_STAGKEY(x) \ 1363 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1364 1365 #define S_FW_RI_TPTE_STAGSTATE 22 1366 #define M_FW_RI_TPTE_STAGSTATE 0x1 1367 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1368 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1369 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1370 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1371 1372 #define S_FW_RI_TPTE_STAGTYPE 20 1373 #define M_FW_RI_TPTE_STAGTYPE 0x3 1374 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1375 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1376 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1377 1378 #define S_FW_RI_TPTE_PDID 0 1379 #define M_FW_RI_TPTE_PDID 0xfffff 1380 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1381 #define G_FW_RI_TPTE_PDID(x) \ 1382 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1383 1384 #define S_FW_RI_TPTE_PERM 28 1385 #define M_FW_RI_TPTE_PERM 0xf 1386 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1387 #define G_FW_RI_TPTE_PERM(x) \ 1388 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1389 1390 #define S_FW_RI_TPTE_REMINVDIS 27 1391 #define M_FW_RI_TPTE_REMINVDIS 0x1 1392 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1393 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1394 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1395 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1396 1397 #define S_FW_RI_TPTE_ADDRTYPE 26 1398 #define M_FW_RI_TPTE_ADDRTYPE 1 1399 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1400 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1401 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1402 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1403 1404 #define S_FW_RI_TPTE_MWBINDEN 25 1405 #define M_FW_RI_TPTE_MWBINDEN 0x1 1406 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1407 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1408 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1409 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1410 1411 #define S_FW_RI_TPTE_PS 20 1412 #define M_FW_RI_TPTE_PS 0x1f 1413 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1414 #define G_FW_RI_TPTE_PS(x) \ 1415 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1416 1417 #define S_FW_RI_TPTE_QPID 0 1418 #define M_FW_RI_TPTE_QPID 0xfffff 1419 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1420 #define G_FW_RI_TPTE_QPID(x) \ 1421 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1422 1423 #define S_FW_RI_TPTE_NOSNOOP 31 1424 #define M_FW_RI_TPTE_NOSNOOP 0x1 1425 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1426 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1427 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1428 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1429 1430 #define S_FW_RI_TPTE_PBLADDR 0 1431 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1432 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1433 #define G_FW_RI_TPTE_PBLADDR(x) \ 1434 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1435 1436 #define S_FW_RI_TPTE_DCA 24 1437 #define M_FW_RI_TPTE_DCA 0x1f 1438 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1439 #define G_FW_RI_TPTE_DCA(x) \ 1440 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1441 1442 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1443 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1444 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1445 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1446 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1447 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1448 1449 enum fw_ri_cqe_rxtx { 1450 FW_RI_CQE_RXTX_RX = 0x0, 1451 FW_RI_CQE_RXTX_TX = 0x1, 1452 }; 1453 1454 struct fw_ri_cqe { 1455 union fw_ri_rxtx { 1456 struct fw_ri_scqe { 1457 __be32 qpid_n_stat_rxtx_type; 1458 __be32 plen; 1459 __be32 stag; 1460 __be32 wrid; 1461 } scqe; 1462 struct fw_ri_rcqe { 1463 __be32 qpid_n_stat_rxtx_type; 1464 __be32 plen; 1465 __be32 stag; 1466 __be32 msn; 1467 } rcqe; 1468 struct fw_ri_rcqe_imm { 1469 __be32 qpid_n_stat_rxtx_type; 1470 __be32 plen; 1471 __be32 mo; 1472 __be32 msn; 1473 __u64 imm_data; 1474 } imm_data_rcqe; 1475 } u; 1476 }; 1477 1478 #define S_FW_RI_CQE_QPID 12 1479 #define M_FW_RI_CQE_QPID 0xfffff 1480 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1481 #define G_FW_RI_CQE_QPID(x) \ 1482 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1483 1484 #define S_FW_RI_CQE_NOTIFY 10 1485 #define M_FW_RI_CQE_NOTIFY 0x1 1486 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1487 #define G_FW_RI_CQE_NOTIFY(x) \ 1488 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1489 1490 #define S_FW_RI_CQE_STATUS 5 1491 #define M_FW_RI_CQE_STATUS 0x1f 1492 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1493 #define G_FW_RI_CQE_STATUS(x) \ 1494 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1495 1496 1497 #define S_FW_RI_CQE_RXTX 4 1498 #define M_FW_RI_CQE_RXTX 0x1 1499 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1500 #define G_FW_RI_CQE_RXTX(x) \ 1501 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1502 1503 #define S_FW_RI_CQE_TYPE 0 1504 #define M_FW_RI_CQE_TYPE 0xf 1505 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1506 #define G_FW_RI_CQE_TYPE(x) \ 1507 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1508 1509 enum fw_ri_res_type { 1510 FW_RI_RES_TYPE_SQ, 1511 FW_RI_RES_TYPE_RQ, 1512 FW_RI_RES_TYPE_CQ, 1513 FW_RI_RES_TYPE_SRQ, 1514 }; 1515 1516 enum fw_ri_res_op { 1517 FW_RI_RES_OP_WRITE, 1518 FW_RI_RES_OP_RESET, 1519 }; 1520 1521 struct fw_ri_res { 1522 union fw_ri_restype { 1523 struct fw_ri_res_sqrq { 1524 __u8 restype; 1525 __u8 op; 1526 __be16 r3; 1527 __be32 eqid; 1528 __be32 r4[2]; 1529 __be32 fetchszm_to_iqid; 1530 __be32 dcaen_to_eqsize; 1531 __be64 eqaddr; 1532 } sqrq; 1533 struct fw_ri_res_cq { 1534 __u8 restype; 1535 __u8 op; 1536 __be16 r3; 1537 __be32 iqid; 1538 __be32 r4[2]; 1539 __be32 iqandst_to_iqandstindex; 1540 __be16 iqdroprss_to_iqesize; 1541 __be16 iqsize; 1542 __be64 iqaddr; 1543 __be32 iqns_iqro; 1544 __be32 r6_lo; 1545 __be64 r7; 1546 } cq; 1547 struct fw_ri_res_srq { 1548 __u8 restype; 1549 __u8 op; 1550 __be16 r3; 1551 __be32 eqid; 1552 __be32 r4[2]; 1553 __be32 fetchszm_to_iqid; 1554 __be32 dcaen_to_eqsize; 1555 __be64 eqaddr; 1556 __be32 srqid; 1557 __be32 pdid; 1558 __be32 hwsrqsize; 1559 __be32 hwsrqaddr; 1560 } srq; 1561 } u; 1562 }; 1563 1564 struct fw_ri_res_wr { 1565 __be32 op_nres; 1566 __be32 len16_pkd; 1567 __u64 cookie; 1568 #ifndef C99_NOT_SUPPORTED 1569 struct fw_ri_res res[0]; 1570 #endif 1571 }; 1572 1573 #define S_FW_RI_RES_WR_VFN 8 1574 #define M_FW_RI_RES_WR_VFN 0xff 1575 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1576 #define G_FW_RI_RES_WR_VFN(x) \ 1577 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1578 1579 #define S_FW_RI_RES_WR_NRES 0 1580 #define M_FW_RI_RES_WR_NRES 0xff 1581 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1582 #define G_FW_RI_RES_WR_NRES(x) \ 1583 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1584 1585 #define S_FW_RI_RES_WR_FETCHSZM 26 1586 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1587 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1588 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1589 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1590 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1591 1592 #define S_FW_RI_RES_WR_STATUSPGNS 25 1593 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1594 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1595 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1596 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1597 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1598 1599 #define S_FW_RI_RES_WR_STATUSPGRO 24 1600 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1601 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1602 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1603 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1604 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1605 1606 #define S_FW_RI_RES_WR_FETCHNS 23 1607 #define M_FW_RI_RES_WR_FETCHNS 0x1 1608 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1609 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1610 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1611 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1612 1613 #define S_FW_RI_RES_WR_FETCHRO 22 1614 #define M_FW_RI_RES_WR_FETCHRO 0x1 1615 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1616 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1617 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1618 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1619 1620 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1621 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1622 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1623 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1624 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1625 1626 #define S_FW_RI_RES_WR_CPRIO 19 1627 #define M_FW_RI_RES_WR_CPRIO 0x1 1628 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1629 #define G_FW_RI_RES_WR_CPRIO(x) \ 1630 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1631 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1632 1633 #define S_FW_RI_RES_WR_ONCHIP 18 1634 #define M_FW_RI_RES_WR_ONCHIP 0x1 1635 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1636 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1637 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1638 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1639 1640 #define S_FW_RI_RES_WR_PCIECHN 16 1641 #define M_FW_RI_RES_WR_PCIECHN 0x3 1642 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1643 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1644 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1645 1646 #define S_FW_RI_RES_WR_IQID 0 1647 #define M_FW_RI_RES_WR_IQID 0xffff 1648 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1649 #define G_FW_RI_RES_WR_IQID(x) \ 1650 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1651 1652 #define S_FW_RI_RES_WR_DCAEN 31 1653 #define M_FW_RI_RES_WR_DCAEN 0x1 1654 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1655 #define G_FW_RI_RES_WR_DCAEN(x) \ 1656 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1657 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1658 1659 #define S_FW_RI_RES_WR_DCACPU 26 1660 #define M_FW_RI_RES_WR_DCACPU 0x1f 1661 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1662 #define G_FW_RI_RES_WR_DCACPU(x) \ 1663 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1664 1665 #define S_FW_RI_RES_WR_FBMIN 23 1666 #define M_FW_RI_RES_WR_FBMIN 0x7 1667 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1668 #define G_FW_RI_RES_WR_FBMIN(x) \ 1669 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1670 1671 #define S_FW_RI_RES_WR_FBMAX 20 1672 #define M_FW_RI_RES_WR_FBMAX 0x7 1673 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1674 #define G_FW_RI_RES_WR_FBMAX(x) \ 1675 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1676 1677 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1678 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1679 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1680 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1681 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1682 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1683 1684 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1685 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1686 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1687 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1688 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1689 1690 #define S_FW_RI_RES_WR_EQSIZE 0 1691 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1692 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1693 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1694 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1695 1696 #define S_FW_RI_RES_WR_IQANDST 15 1697 #define M_FW_RI_RES_WR_IQANDST 0x1 1698 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1699 #define G_FW_RI_RES_WR_IQANDST(x) \ 1700 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1701 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1702 1703 #define S_FW_RI_RES_WR_IQANUS 14 1704 #define M_FW_RI_RES_WR_IQANUS 0x1 1705 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1706 #define G_FW_RI_RES_WR_IQANUS(x) \ 1707 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1708 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1709 1710 #define S_FW_RI_RES_WR_IQANUD 12 1711 #define M_FW_RI_RES_WR_IQANUD 0x3 1712 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1713 #define G_FW_RI_RES_WR_IQANUD(x) \ 1714 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1715 1716 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1717 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1718 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1719 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1720 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1721 1722 #define S_FW_RI_RES_WR_IQDROPRSS 15 1723 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1724 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1725 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1726 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1727 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1728 1729 #define S_FW_RI_RES_WR_IQGTSMODE 14 1730 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1731 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1732 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1733 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1734 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1735 1736 #define S_FW_RI_RES_WR_IQPCIECH 12 1737 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1738 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1739 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1740 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1741 1742 #define S_FW_RI_RES_WR_IQDCAEN 11 1743 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1744 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1745 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1746 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1747 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1748 1749 #define S_FW_RI_RES_WR_IQDCACPU 6 1750 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1751 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1752 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1753 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1754 1755 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1756 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1757 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1758 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1759 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1760 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1761 1762 #define S_FW_RI_RES_WR_IQO 3 1763 #define M_FW_RI_RES_WR_IQO 0x1 1764 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1765 #define G_FW_RI_RES_WR_IQO(x) \ 1766 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1767 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1768 1769 #define S_FW_RI_RES_WR_IQCPRIO 2 1770 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1771 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1772 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1773 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1774 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1775 1776 #define S_FW_RI_RES_WR_IQESIZE 0 1777 #define M_FW_RI_RES_WR_IQESIZE 0x3 1778 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1779 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1780 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1781 1782 #define S_FW_RI_RES_WR_IQNS 31 1783 #define M_FW_RI_RES_WR_IQNS 0x1 1784 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1785 #define G_FW_RI_RES_WR_IQNS(x) \ 1786 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1787 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1788 1789 #define S_FW_RI_RES_WR_IQRO 30 1790 #define M_FW_RI_RES_WR_IQRO 0x1 1791 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1792 #define G_FW_RI_RES_WR_IQRO(x) \ 1793 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1794 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1795 1796 struct fw_ri_rdma_write_wr { 1797 __u8 opcode; 1798 __u8 flags; 1799 __u16 wrid; 1800 __u8 r1[3]; 1801 __u8 len16; 1802 __u64 immd_data; 1803 __be32 plen; 1804 __be32 stag_sink; 1805 __be64 to_sink; 1806 #ifndef C99_NOT_SUPPORTED 1807 union { 1808 struct fw_ri_immd immd_src[0]; 1809 struct fw_ri_isgl isgl_src[0]; 1810 } u; 1811 #endif 1812 }; 1813 1814 struct fw_ri_send_wr { 1815 __u8 opcode; 1816 __u8 flags; 1817 __u16 wrid; 1818 __u8 r1[3]; 1819 __u8 len16; 1820 __be32 sendop_pkd; 1821 __be32 stag_inv; 1822 __be32 plen; 1823 __be32 r3; 1824 __be64 r4; 1825 #ifndef C99_NOT_SUPPORTED 1826 union { 1827 struct fw_ri_immd immd_src[0]; 1828 struct fw_ri_isgl isgl_src[0]; 1829 } u; 1830 #endif 1831 }; 1832 1833 #define S_FW_RI_SEND_WR_SENDOP 0 1834 #define M_FW_RI_SEND_WR_SENDOP 0xf 1835 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1836 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1837 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1838 1839 struct fw_ri_rdma_write_cmpl_wr { 1840 __u8 opcode; 1841 __u8 flags; 1842 __u16 wrid; 1843 __u8 r1[3]; 1844 __u8 len16; 1845 __u8 r2; 1846 __u8 flags_send; 1847 __u16 wrid_send; 1848 __be32 stag_inv; 1849 __be32 plen; 1850 __be32 stag_sink; 1851 __be64 to_sink; 1852 union fw_ri_cmpl { 1853 struct fw_ri_immd_cmpl { 1854 __u8 op; 1855 __u8 r1[6]; 1856 __u8 immdlen; 1857 __u8 data[16]; 1858 } immd_src; 1859 struct fw_ri_isgl isgl_src; 1860 } u_cmpl; 1861 __be64 r3; 1862 #ifndef C99_NOT_SUPPORTED 1863 union fw_ri_write { 1864 struct fw_ri_immd immd_src[0]; 1865 struct fw_ri_isgl isgl_src[0]; 1866 } u; 1867 #endif 1868 }; 1869 1870 struct fw_ri_rdma_read_wr { 1871 __u8 opcode; 1872 __u8 flags; 1873 __u16 wrid; 1874 __u8 r1[3]; 1875 __u8 len16; 1876 __be64 r2; 1877 __be32 stag_sink; 1878 __be32 to_sink_hi; 1879 __be32 to_sink_lo; 1880 __be32 plen; 1881 __be32 stag_src; 1882 __be32 to_src_hi; 1883 __be32 to_src_lo; 1884 __be32 r5; 1885 }; 1886 1887 struct fw_ri_recv_wr { 1888 __u8 opcode; 1889 __u8 r1; 1890 __u16 wrid; 1891 __u8 r2[3]; 1892 __u8 len16; 1893 struct fw_ri_isgl isgl; 1894 }; 1895 1896 struct fw_ri_bind_mw_wr { 1897 __u8 opcode; 1898 __u8 flags; 1899 __u16 wrid; 1900 __u8 r1[3]; 1901 __u8 len16; 1902 __u8 qpbinde_to_dcacpu; 1903 __u8 pgsz_shift; 1904 __u8 addr_type; 1905 __u8 mem_perms; 1906 __be32 stag_mr; 1907 __be32 stag_mw; 1908 __be32 r3; 1909 __be64 len_mw; 1910 __be64 va_fbo; 1911 __be64 r4; 1912 }; 1913 1914 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1915 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1916 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1917 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1918 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1919 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1920 1921 #define S_FW_RI_BIND_MW_WR_NS 5 1922 #define M_FW_RI_BIND_MW_WR_NS 0x1 1923 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1924 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1925 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1926 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1927 1928 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1929 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1930 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1931 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1932 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1933 1934 struct fw_ri_fr_nsmr_wr { 1935 __u8 opcode; 1936 __u8 flags; 1937 __u16 wrid; 1938 __u8 r1[3]; 1939 __u8 len16; 1940 __u8 qpbinde_to_dcacpu; 1941 __u8 pgsz_shift; 1942 __u8 addr_type; 1943 __u8 mem_perms; 1944 __be32 stag; 1945 __be32 len_hi; 1946 __be32 len_lo; 1947 __be32 va_hi; 1948 __be32 va_lo_fbo; 1949 }; 1950 1951 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1952 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1953 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1954 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1955 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1956 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1957 1958 #define S_FW_RI_FR_NSMR_WR_NS 5 1959 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1960 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1961 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1962 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1963 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1964 1965 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1966 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1967 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1968 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1969 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1970 1971 struct fw_ri_fr_nsmr_tpte_wr { 1972 __u8 opcode; 1973 __u8 flags; 1974 __u16 wrid; 1975 __u8 r1[3]; 1976 __u8 len16; 1977 __be32 r2; 1978 __be32 stag; 1979 struct fw_ri_tpte tpte; 1980 __be64 pbl[2]; 1981 }; 1982 1983 struct fw_ri_inv_lstag_wr { 1984 __u8 opcode; 1985 __u8 flags; 1986 __u16 wrid; 1987 __u8 r1[3]; 1988 __u8 len16; 1989 __be32 r2; 1990 __be32 stag_inv; 1991 }; 1992 1993 struct fw_ri_send_immediate_wr { 1994 __u8 opcode; 1995 __u8 flags; 1996 __u16 wrid; 1997 __u8 r1[3]; 1998 __u8 len16; 1999 __be32 sendimmop_pkd; 2000 __be32 r3; 2001 __be32 plen; 2002 __be32 r4; 2003 __be64 r5; 2004 #ifndef C99_NOT_SUPPORTED 2005 struct fw_ri_immd immd_src[0]; 2006 #endif 2007 }; 2008 2009 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2010 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2011 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2012 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2013 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2014 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2015 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2016 2017 enum fw_ri_atomic_op { 2018 FW_RI_ATOMIC_OP_FETCHADD, 2019 FW_RI_ATOMIC_OP_SWAP, 2020 FW_RI_ATOMIC_OP_CMDSWAP, 2021 }; 2022 2023 struct fw_ri_atomic_wr { 2024 __u8 opcode; 2025 __u8 flags; 2026 __u16 wrid; 2027 __u8 r1[3]; 2028 __u8 len16; 2029 __be32 atomicop_pkd; 2030 __be64 r3; 2031 __be32 aopcode_pkd; 2032 __be32 reqid; 2033 __be32 stag; 2034 __be32 to_hi; 2035 __be32 to_lo; 2036 __be32 addswap_data_hi; 2037 __be32 addswap_data_lo; 2038 __be32 addswap_mask_hi; 2039 __be32 addswap_mask_lo; 2040 __be32 compare_data_hi; 2041 __be32 compare_data_lo; 2042 __be32 compare_mask_hi; 2043 __be32 compare_mask_lo; 2044 __be32 r5; 2045 }; 2046 2047 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2048 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2049 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2050 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2051 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2052 2053 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2054 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2055 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2056 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2057 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2058 2059 enum fw_ri_type { 2060 FW_RI_TYPE_INIT, 2061 FW_RI_TYPE_FINI, 2062 FW_RI_TYPE_TERMINATE 2063 }; 2064 2065 enum fw_ri_init_p2ptype { 2066 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2067 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2068 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2069 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2070 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2071 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2072 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2073 }; 2074 2075 enum fw_ri_init_rqeqid_srq { 2076 FW_RI_INIT_RQEQID_SRQ = 1U << 31, 2077 }; 2078 2079 struct fw_ri_wr { 2080 __be32 op_compl; 2081 __be32 flowid_len16; 2082 __u64 cookie; 2083 union fw_ri { 2084 struct fw_ri_init { 2085 __u8 type; 2086 __u8 mpareqbit_p2ptype; 2087 __u8 r4[2]; 2088 __u8 mpa_attrs; 2089 __u8 qp_caps; 2090 __be16 nrqe; 2091 __be32 pdid; 2092 __be32 qpid; 2093 __be32 sq_eqid; 2094 __be32 rq_eqid; 2095 __be32 scqid; 2096 __be32 rcqid; 2097 __be32 ord_max; 2098 __be32 ird_max; 2099 __be32 iss; 2100 __be32 irs; 2101 __be32 hwrqsize; 2102 __be32 hwrqaddr; 2103 __be64 r5; 2104 union fw_ri_init_p2p { 2105 struct fw_ri_rdma_write_wr write; 2106 struct fw_ri_rdma_read_wr read; 2107 struct fw_ri_send_wr send; 2108 } u; 2109 } init; 2110 struct fw_ri_fini { 2111 __u8 type; 2112 __u8 r3[7]; 2113 __be64 r4; 2114 } fini; 2115 struct fw_ri_terminate { 2116 __u8 type; 2117 __u8 r3[3]; 2118 __be32 immdlen; 2119 __u8 termmsg[40]; 2120 } terminate; 2121 } u; 2122 }; 2123 2124 #define S_FW_RI_WR_MPAREQBIT 7 2125 #define M_FW_RI_WR_MPAREQBIT 0x1 2126 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2127 #define G_FW_RI_WR_MPAREQBIT(x) \ 2128 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2129 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2130 2131 #define S_FW_RI_WR_0BRRBIT 6 2132 #define M_FW_RI_WR_0BRRBIT 0x1 2133 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2134 #define G_FW_RI_WR_0BRRBIT(x) \ 2135 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2136 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2137 2138 #define S_FW_RI_WR_P2PTYPE 0 2139 #define M_FW_RI_WR_P2PTYPE 0xf 2140 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2141 #define G_FW_RI_WR_P2PTYPE(x) \ 2142 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2143 2144 /****************************************************************************** 2145 * F O i S C S I W O R K R E Q U E S T s 2146 *********************************************/ 2147 2148 #define FW_FOISCSI_NAME_MAX_LEN 224 2149 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2150 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2151 #define FW_FOISCSI_INIT_NODE_MAX 8 2152 2153 enum fw_chnet_ifconf_wr_subop { 2154 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2155 2156 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2157 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2158 2159 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2160 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2161 2162 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2163 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2164 2165 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2166 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2167 2168 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2169 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2170 2171 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2172 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2173 2174 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2175 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2176 2177 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2178 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2179 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2180 2181 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2182 }; 2183 2184 struct fw_chnet_ifconf_wr { 2185 __be32 op_compl; 2186 __be32 flowid_len16; 2187 __be64 cookie; 2188 __be32 if_flowid; 2189 __u8 idx; 2190 __u8 subop; 2191 __u8 retval; 2192 __u8 r2; 2193 __be64 r3; 2194 struct fw_chnet_ifconf_params { 2195 __be32 r0; 2196 __be16 vlanid; 2197 __be16 mtu; 2198 union fw_chnet_ifconf_addr_type { 2199 struct fw_chnet_ifconf_ipv4 { 2200 __be32 addr; 2201 __be32 mask; 2202 __be32 router; 2203 __be32 r0; 2204 __be64 r1; 2205 } ipv4; 2206 struct fw_chnet_ifconf_ipv6 { 2207 __u8 prefix_len; 2208 __u8 r0; 2209 __be16 r1; 2210 __be32 r2; 2211 __be64 addr_hi; 2212 __be64 addr_lo; 2213 __be64 router_hi; 2214 __be64 router_lo; 2215 } ipv6; 2216 } in_attr; 2217 } param; 2218 }; 2219 2220 enum fw_foiscsi_node_type { 2221 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2222 FW_FOISCSI_NODE_TYPE_TARGET, 2223 }; 2224 2225 enum fw_foiscsi_session_type { 2226 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2227 FW_FOISCSI_SESSION_TYPE_NORMAL, 2228 }; 2229 2230 enum fw_foiscsi_auth_policy { 2231 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2232 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2233 }; 2234 2235 enum fw_foiscsi_auth_method { 2236 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2237 FW_FOISCSI_AUTH_METHOD_CHAP, 2238 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2239 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2240 }; 2241 2242 enum fw_foiscsi_digest_type { 2243 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2244 FW_FOISCSI_DIGEST_TYPE_CRC32, 2245 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2246 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2247 }; 2248 2249 enum fw_foiscsi_wr_subop { 2250 FW_FOISCSI_WR_SUBOP_ADD = 1, 2251 FW_FOISCSI_WR_SUBOP_DEL = 2, 2252 FW_FOISCSI_WR_SUBOP_MOD = 4, 2253 }; 2254 2255 enum fw_foiscsi_ctrl_state { 2256 FW_FOISCSI_CTRL_STATE_FREE = 0, 2257 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2258 FW_FOISCSI_CTRL_STATE_FAILED, 2259 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2260 FW_FOISCSI_CTRL_STATE_REDIRECT, 2261 }; 2262 2263 struct fw_rdev_wr { 2264 __be32 op_to_immdlen; 2265 __be32 alloc_to_len16; 2266 __be64 cookie; 2267 __u8 protocol; 2268 __u8 event_cause; 2269 __u8 cur_state; 2270 __u8 prev_state; 2271 __be32 flags_to_assoc_flowid; 2272 union rdev_entry { 2273 struct fcoe_rdev_entry { 2274 __be32 flowid; 2275 __u8 protocol; 2276 __u8 event_cause; 2277 __u8 flags; 2278 __u8 rjt_reason; 2279 __u8 cur_login_st; 2280 __u8 prev_login_st; 2281 __be16 rcv_fr_sz; 2282 __u8 rd_xfer_rdy_to_rport_type; 2283 __u8 vft_to_qos; 2284 __u8 org_proc_assoc_to_acc_rsp_code; 2285 __u8 enh_disc_to_tgt; 2286 __u8 wwnn[8]; 2287 __u8 wwpn[8]; 2288 __be16 iqid; 2289 __u8 fc_oui[3]; 2290 __u8 r_id[3]; 2291 } fcoe_rdev; 2292 struct iscsi_rdev_entry { 2293 __be32 flowid; 2294 __u8 protocol; 2295 __u8 event_cause; 2296 __u8 flags; 2297 __u8 r3; 2298 __be16 iscsi_opts; 2299 __be16 tcp_opts; 2300 __be16 ip_opts; 2301 __be16 max_rcv_len; 2302 __be16 max_snd_len; 2303 __be16 first_brst_len; 2304 __be16 max_brst_len; 2305 __be16 r4; 2306 __be16 def_time2wait; 2307 __be16 def_time2ret; 2308 __be16 nop_out_intrvl; 2309 __be16 non_scsi_to; 2310 __be16 isid; 2311 __be16 tsid; 2312 __be16 port; 2313 __be16 tpgt; 2314 __u8 r5[6]; 2315 __be16 iqid; 2316 } iscsi_rdev; 2317 } u; 2318 }; 2319 2320 #define S_FW_RDEV_WR_IMMDLEN 0 2321 #define M_FW_RDEV_WR_IMMDLEN 0xff 2322 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2323 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2324 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2325 2326 #define S_FW_RDEV_WR_ALLOC 31 2327 #define M_FW_RDEV_WR_ALLOC 0x1 2328 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2329 #define G_FW_RDEV_WR_ALLOC(x) \ 2330 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2331 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2332 2333 #define S_FW_RDEV_WR_FREE 30 2334 #define M_FW_RDEV_WR_FREE 0x1 2335 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2336 #define G_FW_RDEV_WR_FREE(x) \ 2337 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2338 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2339 2340 #define S_FW_RDEV_WR_MODIFY 29 2341 #define M_FW_RDEV_WR_MODIFY 0x1 2342 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2343 #define G_FW_RDEV_WR_MODIFY(x) \ 2344 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2345 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2346 2347 #define S_FW_RDEV_WR_FLOWID 8 2348 #define M_FW_RDEV_WR_FLOWID 0xfffff 2349 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2350 #define G_FW_RDEV_WR_FLOWID(x) \ 2351 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2352 2353 #define S_FW_RDEV_WR_LEN16 0 2354 #define M_FW_RDEV_WR_LEN16 0xff 2355 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2356 #define G_FW_RDEV_WR_LEN16(x) \ 2357 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2358 2359 #define S_FW_RDEV_WR_FLAGS 24 2360 #define M_FW_RDEV_WR_FLAGS 0xff 2361 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2362 #define G_FW_RDEV_WR_FLAGS(x) \ 2363 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2364 2365 #define S_FW_RDEV_WR_GET_NEXT 20 2366 #define M_FW_RDEV_WR_GET_NEXT 0xf 2367 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2368 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2369 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2370 2371 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2372 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2373 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2374 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2375 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2376 2377 #define S_FW_RDEV_WR_RJT 7 2378 #define M_FW_RDEV_WR_RJT 0x1 2379 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2380 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2381 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2382 2383 #define S_FW_RDEV_WR_REASON 0 2384 #define M_FW_RDEV_WR_REASON 0x7f 2385 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2386 #define G_FW_RDEV_WR_REASON(x) \ 2387 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2388 2389 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2390 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2391 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2392 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2393 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2394 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2395 2396 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2397 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2398 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2399 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2400 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2401 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2402 2403 #define S_FW_RDEV_WR_FC_SP 5 2404 #define M_FW_RDEV_WR_FC_SP 0x1 2405 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2406 #define G_FW_RDEV_WR_FC_SP(x) \ 2407 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2408 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2409 2410 #define S_FW_RDEV_WR_RPORT_TYPE 0 2411 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2412 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2413 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2414 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2415 2416 #define S_FW_RDEV_WR_VFT 7 2417 #define M_FW_RDEV_WR_VFT 0x1 2418 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2419 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2420 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2421 2422 #define S_FW_RDEV_WR_NPIV 6 2423 #define M_FW_RDEV_WR_NPIV 0x1 2424 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2425 #define G_FW_RDEV_WR_NPIV(x) \ 2426 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2427 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2428 2429 #define S_FW_RDEV_WR_CLASS 4 2430 #define M_FW_RDEV_WR_CLASS 0x3 2431 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2432 #define G_FW_RDEV_WR_CLASS(x) \ 2433 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2434 2435 #define S_FW_RDEV_WR_SEQ_DEL 3 2436 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2437 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2438 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2439 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2440 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2441 2442 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2443 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2444 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2445 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2446 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2447 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2448 2449 #define S_FW_RDEV_WR_PREF 1 2450 #define M_FW_RDEV_WR_PREF 0x1 2451 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2452 #define G_FW_RDEV_WR_PREF(x) \ 2453 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2454 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2455 2456 #define S_FW_RDEV_WR_QOS 0 2457 #define M_FW_RDEV_WR_QOS 0x1 2458 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2459 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2460 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2461 2462 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2463 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2464 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2465 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2466 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2467 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2468 2469 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2470 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2471 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2472 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2473 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2474 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2475 2476 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2477 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2478 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2479 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2480 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2481 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2482 2483 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2484 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2485 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2486 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2487 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2488 2489 #define S_FW_RDEV_WR_ENH_DISC 7 2490 #define M_FW_RDEV_WR_ENH_DISC 0x1 2491 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2492 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2493 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2494 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2495 2496 #define S_FW_RDEV_WR_REC 6 2497 #define M_FW_RDEV_WR_REC 0x1 2498 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2499 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2500 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2501 2502 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2503 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2504 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2505 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2506 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2507 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2508 2509 #define S_FW_RDEV_WR_RETRY 4 2510 #define M_FW_RDEV_WR_RETRY 0x1 2511 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2512 #define G_FW_RDEV_WR_RETRY(x) \ 2513 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2514 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2515 2516 #define S_FW_RDEV_WR_CONF_CMPL 3 2517 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2518 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2519 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2520 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2521 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2522 2523 #define S_FW_RDEV_WR_DATA_OVLY 2 2524 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2525 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2526 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2527 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2528 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2529 2530 #define S_FW_RDEV_WR_INI 1 2531 #define M_FW_RDEV_WR_INI 0x1 2532 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2533 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2534 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2535 2536 #define S_FW_RDEV_WR_TGT 0 2537 #define M_FW_RDEV_WR_TGT 0x1 2538 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2539 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2540 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2541 2542 struct fw_foiscsi_node_wr { 2543 __be32 op_to_immdlen; 2544 __be32 flowid_len16; 2545 __u64 cookie; 2546 __u8 subop; 2547 __u8 status; 2548 __u8 alias_len; 2549 __u8 iqn_len; 2550 __be32 node_flowid; 2551 __be16 nodeid; 2552 __be16 login_retry; 2553 __be16 retry_timeout; 2554 __be16 r3; 2555 __u8 iqn[224]; 2556 __u8 alias[224]; 2557 }; 2558 2559 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2560 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2561 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2562 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2563 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2564 2565 struct fw_foiscsi_ctrl_wr { 2566 __be32 op_compl; 2567 __be32 flowid_len16; 2568 __u64 cookie; 2569 __u8 subop; 2570 __u8 status; 2571 __u8 ctrl_state; 2572 __u8 io_state; 2573 __be32 node_id; 2574 __be32 ctrl_id; 2575 __be32 io_id; 2576 struct fw_foiscsi_sess_attr { 2577 __be32 sess_type_to_erl; 2578 __be16 max_conn; 2579 __be16 max_r2t; 2580 __be16 time2wait; 2581 __be16 time2retain; 2582 __be32 max_burst; 2583 __be32 first_burst; 2584 __be32 r1; 2585 } sess_attr; 2586 struct fw_foiscsi_conn_attr { 2587 __be32 hdigest_to_ddp_pgsz; 2588 __be32 max_rcv_dsl; 2589 __be32 ping_tmo; 2590 __be16 dst_port; 2591 __be16 src_port; 2592 union fw_foiscsi_conn_attr_addr { 2593 struct fw_foiscsi_conn_attr_ipv6 { 2594 __be64 dst_addr[2]; 2595 __be64 src_addr[2]; 2596 } ipv6_addr; 2597 struct fw_foiscsi_conn_attr_ipv4 { 2598 __be32 dst_addr; 2599 __be32 src_addr; 2600 } ipv4_addr; 2601 } u; 2602 } conn_attr; 2603 __u8 tgt_name_len; 2604 __u8 r3[7]; 2605 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2606 }; 2607 2608 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2609 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2610 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2611 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2612 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2613 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2614 2615 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2616 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2617 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2618 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2619 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2620 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2621 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2622 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2623 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2624 2625 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2626 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2627 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2628 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2629 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2630 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2631 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2632 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2633 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2634 2635 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2636 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2637 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2638 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2639 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2640 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2641 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2642 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2643 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2644 2645 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2646 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2647 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2648 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2649 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2650 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2651 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2652 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2653 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2654 2655 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2656 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2657 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2658 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2659 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2660 2661 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2662 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2663 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2664 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2665 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2666 2667 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2668 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2669 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2670 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2671 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2672 2673 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2674 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2675 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2676 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2677 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2678 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2679 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2680 2681 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2682 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2683 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2684 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2685 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2686 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2687 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2688 2689 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2690 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2691 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2692 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2693 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2694 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2695 2696 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2697 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2698 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2699 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2700 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2701 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2702 2703 struct fw_foiscsi_chap_wr { 2704 __be32 op_compl; 2705 __be32 flowid_len16; 2706 __u64 cookie; 2707 __u8 status; 2708 __u8 id_len; 2709 __u8 sec_len; 2710 __u8 node_type; 2711 __be16 node_id; 2712 __u8 r3[2]; 2713 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2714 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2715 }; 2716 2717 /****************************************************************************** 2718 * C O i S C S I W O R K R E Q U E S T S 2719 ********************************************/ 2720 2721 enum fw_chnet_addr_type { 2722 FW_CHNET_ADDD_TYPE_NONE = 0, 2723 FW_CHNET_ADDR_TYPE_IPV4, 2724 FW_CHNET_ADDR_TYPE_IPV6, 2725 }; 2726 2727 enum fw_msg_wr_type { 2728 FW_MSG_WR_TYPE_RPL = 0, 2729 FW_MSG_WR_TYPE_ERR, 2730 FW_MSG_WR_TYPE_PLD, 2731 }; 2732 2733 struct fw_coiscsi_tgt_wr { 2734 __be32 op_compl; 2735 __be32 flowid_len16; 2736 __u64 cookie; 2737 __u8 subop; 2738 __u8 status; 2739 __be16 r4; 2740 __be32 flags; 2741 struct fw_coiscsi_tgt_conn_attr { 2742 __be32 in_tid; 2743 __be16 in_port; 2744 __u8 in_type; 2745 __u8 r6; 2746 union fw_coiscsi_tgt_conn_attr_addr { 2747 struct fw_coiscsi_tgt_conn_attr_in_addr { 2748 __be32 addr; 2749 __be32 r7; 2750 __be32 r8[2]; 2751 } in_addr; 2752 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2753 __be64 addr[2]; 2754 } in_addr6; 2755 } u; 2756 } conn_attr; 2757 }; 2758 2759 struct fw_coiscsi_tgt_xmit_wr { 2760 __be32 op_to_immdlen; 2761 __be32 flowid_len16; 2762 __be64 cookie; 2763 __be16 iq_id; 2764 __be16 r4; 2765 __be32 datasn; 2766 __be32 t_xfer_len; 2767 __be32 flags; 2768 __be32 tag; 2769 __be32 tidx; 2770 __be32 r5[2]; 2771 }; 2772 2773 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2774 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2775 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2776 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2777 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2778 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2779 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2780 2781 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2782 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2783 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2784 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2785 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2786 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2787 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2788 2789 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2790 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2791 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2792 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2793 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2794 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2795 2796 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2797 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2798 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2799 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2800 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2801 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2802 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2803 2804 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2805 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2806 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2807 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2808 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2809 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2810 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2811 2812 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2813 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2814 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2815 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2816 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2817 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2818 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2819 2820 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2821 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2822 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2823 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2824 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2825 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2826 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2827 2828 struct fw_isns_wr { 2829 __be32 op_compl; 2830 __be32 flowid_len16; 2831 __u64 cookie; 2832 __u8 subop; 2833 __u8 status; 2834 __be16 iq_id; 2835 __be32 r4; 2836 struct fw_tcp_conn_attr { 2837 __be32 in_tid; 2838 __be16 in_port; 2839 __u8 in_type; 2840 __u8 r6; 2841 union fw_tcp_conn_attr_addr { 2842 struct fw_tcp_conn_attr_in_addr { 2843 __be32 addr; 2844 __be32 r7; 2845 __be32 r8[2]; 2846 } in_addr; 2847 struct fw_tcp_conn_attr_in_addr6 { 2848 __be64 addr[2]; 2849 } in_addr6; 2850 } u; 2851 } conn_attr; 2852 }; 2853 2854 struct fw_isns_xmit_wr { 2855 __be32 op_to_immdlen; 2856 __be32 flowid_len16; 2857 __be64 cookie; 2858 __be16 iq_id; 2859 __be16 r4; 2860 __be32 xfer_len; 2861 __be64 r5; 2862 }; 2863 2864 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2865 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2866 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2867 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2868 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2869 2870 /****************************************************************************** 2871 * F O F C O E W O R K R E Q U E S T s 2872 *******************************************/ 2873 2874 struct fw_fcoe_els_ct_wr { 2875 __be32 op_immdlen; 2876 __be32 flowid_len16; 2877 __be64 cookie; 2878 __be16 iqid; 2879 __u8 tmo_val; 2880 __u8 els_ct_type; 2881 __u8 ctl_pri; 2882 __u8 cp_en_class; 2883 __be16 xfer_cnt; 2884 __u8 fl_to_sp; 2885 __u8 l_id[3]; 2886 __u8 r5; 2887 __u8 r_id[3]; 2888 __be64 rsp_dmaaddr; 2889 __be32 rsp_dmalen; 2890 __be32 r6; 2891 }; 2892 2893 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2894 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2895 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2896 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2897 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2898 2899 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2900 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2901 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2902 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2903 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2904 2905 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2906 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2907 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2908 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2909 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2910 2911 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2912 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2913 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2914 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2915 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2916 2917 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2918 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2919 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2920 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2921 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2922 2923 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2924 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2925 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2926 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2927 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2928 2929 #define S_FW_FCOE_ELS_CT_WR_FL 2 2930 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2931 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2932 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2933 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2934 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2935 2936 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2937 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2938 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2939 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2940 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2941 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2942 2943 #define S_FW_FCOE_ELS_CT_WR_SP 0 2944 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2945 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2946 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2947 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2948 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2949 2950 /****************************************************************************** 2951 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2952 *****************************************************************************/ 2953 2954 struct fw_scsi_write_wr { 2955 __be32 op_immdlen; 2956 __be32 flowid_len16; 2957 __be64 cookie; 2958 __be16 iqid; 2959 __u8 tmo_val; 2960 __u8 use_xfer_cnt; 2961 union fw_scsi_write_priv { 2962 struct fcoe_write_priv { 2963 __u8 ctl_pri; 2964 __u8 cp_en_class; 2965 __u8 r3_lo[2]; 2966 } fcoe; 2967 struct iscsi_write_priv { 2968 __u8 r3[4]; 2969 } iscsi; 2970 } u; 2971 __be32 xfer_cnt; 2972 __be32 ini_xfer_cnt; 2973 __be64 rsp_dmaaddr; 2974 __be32 rsp_dmalen; 2975 __be32 r4; 2976 }; 2977 2978 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2979 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2980 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2981 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2982 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2983 2984 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2985 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2986 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2987 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2988 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2989 2990 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2991 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2992 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2993 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2994 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2995 2996 #define S_FW_SCSI_WRITE_WR_LEN16 0 2997 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2998 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2999 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 3000 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 3001 3002 #define S_FW_SCSI_WRITE_WR_CP_EN 6 3003 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 3004 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 3005 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 3006 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 3007 3008 #define S_FW_SCSI_WRITE_WR_CLASS 4 3009 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 3010 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 3011 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 3012 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 3013 3014 struct fw_scsi_read_wr { 3015 __be32 op_immdlen; 3016 __be32 flowid_len16; 3017 __be64 cookie; 3018 __be16 iqid; 3019 __u8 tmo_val; 3020 __u8 use_xfer_cnt; 3021 union fw_scsi_read_priv { 3022 struct fcoe_read_priv { 3023 __u8 ctl_pri; 3024 __u8 cp_en_class; 3025 __u8 r3_lo[2]; 3026 } fcoe; 3027 struct iscsi_read_priv { 3028 __u8 r3[4]; 3029 } iscsi; 3030 } u; 3031 __be32 xfer_cnt; 3032 __be32 ini_xfer_cnt; 3033 __be64 rsp_dmaaddr; 3034 __be32 rsp_dmalen; 3035 __be32 r4; 3036 }; 3037 3038 #define S_FW_SCSI_READ_WR_OPCODE 24 3039 #define M_FW_SCSI_READ_WR_OPCODE 0xff 3040 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 3041 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 3042 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 3043 3044 #define S_FW_SCSI_READ_WR_IMMDLEN 0 3045 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 3046 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 3047 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 3048 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 3049 3050 #define S_FW_SCSI_READ_WR_FLOWID 8 3051 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 3052 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 3053 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 3054 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 3055 3056 #define S_FW_SCSI_READ_WR_LEN16 0 3057 #define M_FW_SCSI_READ_WR_LEN16 0xff 3058 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 3059 #define G_FW_SCSI_READ_WR_LEN16(x) \ 3060 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 3061 3062 #define S_FW_SCSI_READ_WR_CP_EN 6 3063 #define M_FW_SCSI_READ_WR_CP_EN 0x3 3064 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 3065 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 3066 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 3067 3068 #define S_FW_SCSI_READ_WR_CLASS 4 3069 #define M_FW_SCSI_READ_WR_CLASS 0x3 3070 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 3071 #define G_FW_SCSI_READ_WR_CLASS(x) \ 3072 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 3073 3074 struct fw_scsi_cmd_wr { 3075 __be32 op_immdlen; 3076 __be32 flowid_len16; 3077 __be64 cookie; 3078 __be16 iqid; 3079 __u8 tmo_val; 3080 __u8 r3; 3081 union fw_scsi_cmd_priv { 3082 struct fcoe_cmd_priv { 3083