1 /* 2 * Chelsio Terminator 4 (T4) Firmware interface header file. 3 * 4 * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved. 5 * 6 * Written by felix marti (felix@chelsio.com) 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 11 * release for licensing terms and conditions. 12 */ 13 14 /* 15 * Copyright 2020 RackTop Systems, Inc. 16 */ 17 18 #ifndef _T4FW_INTERFACE_H_ 19 #define _T4FW_INTERFACE_H_ 20 21 /****************************************************************************** 22 * R E T U R N V A L U E S 23 ********************************/ 24 25 enum fw_retval { 26 FW_SUCCESS = 0, /* completed sucessfully */ 27 FW_EPERM = 1, /* operation not permitted */ 28 FW_ENOENT = 2, /* no such file or directory */ 29 FW_EIO = 5, /* input/output error; hw bad */ 30 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 31 FW_EAGAIN = 11, /* try again */ 32 FW_ENOMEM = 12, /* out of memory */ 33 FW_EFAULT = 14, /* bad address; fw bad */ 34 FW_EBUSY = 16, /* resource busy */ 35 FW_EEXIST = 17, /* file exists */ 36 FW_ENODEV = 19, /* no such device */ 37 FW_EINVAL = 22, /* invalid argument */ 38 FW_ENOSPC = 28, /* no space left on device */ 39 FW_ENOSYS = 38, /* functionality not implemented */ 40 FW_ENODATA = 61, /* no data available */ 41 FW_EPROTO = 71, /* protocol error */ 42 FW_EADDRINUSE = 98, /* address already in use */ 43 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 44 FW_ENETDOWN = 100, /* network is down */ 45 FW_ENETUNREACH = 101, /* network is unreachable */ 46 FW_ENOBUFS = 105, /* no buffer space available */ 47 FW_ETIMEDOUT = 110, /* timeout */ 48 FW_EINPROGRESS = 115, /* fw internal */ 49 FW_SCSI_ABORT_REQUESTED = 128, /* */ 50 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 51 FW_SCSI_ABORTED = 130, /* */ 52 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 53 FW_ERR_LINK_DOWN = 132, /* */ 54 FW_RDEV_NOT_READY = 133, /* */ 55 FW_ERR_RDEV_LOST = 134, /* */ 56 FW_ERR_RDEV_LOGO = 135, /* */ 57 FW_FCOE_NO_XCHG = 136, /* */ 58 FW_SCSI_RSP_ERR = 137, /* */ 59 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 60 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 61 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 62 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 63 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 64 }; 65 66 /****************************************************************************** 67 * M E M O R Y T Y P E s 68 ******************************/ 69 70 enum fw_memtype { 71 FW_MEMTYPE_EDC0 = 0x0, 72 FW_MEMTYPE_EDC1 = 0x1, 73 FW_MEMTYPE_EXTMEM = 0x2, 74 FW_MEMTYPE_FLASH = 0x4, 75 FW_MEMTYPE_INTERNAL = 0x5, 76 FW_MEMTYPE_EXTMEM1 = 0x6, 77 FW_MEMTYPE_HMA = 0x7, 78 }; 79 80 /****************************************************************************** 81 * W O R K R E Q U E S T s 82 ********************************/ 83 84 enum fw_wr_opcodes { 85 FW_FRAG_WR = 0x1d, 86 FW_FILTER_WR = 0x02, 87 FW_ULPTX_WR = 0x04, 88 FW_TP_WR = 0x05, 89 FW_ETH_TX_PKT_WR = 0x08, 90 FW_ETH_TX_PKT2_WR = 0x44, 91 FW_ETH_TX_PKTS_WR = 0x09, 92 FW_ETH_TX_PKTS2_WR = 0x78, 93 FW_ETH_TX_EO_WR = 0x1c, 94 FW_EQ_FLUSH_WR = 0x1b, 95 FW_OFLD_CONNECTION_WR = 0x2f, 96 FW_FLOWC_WR = 0x0a, 97 FW_OFLD_TX_DATA_WR = 0x0b, 98 FW_CMD_WR = 0x10, 99 FW_ETH_TX_PKT_VM_WR = 0x11, 100 FW_ETH_TX_PKTS_VM_WR = 0x12, 101 FW_RI_RES_WR = 0x0c, 102 FW_RI_RDMA_WRITE_WR = 0x14, 103 FW_RI_SEND_WR = 0x15, 104 FW_RI_RDMA_READ_WR = 0x16, 105 FW_RI_RECV_WR = 0x17, 106 FW_RI_BIND_MW_WR = 0x18, 107 FW_RI_FR_NSMR_WR = 0x19, 108 FW_RI_FR_NSMR_TPTE_WR = 0x20, 109 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 110 FW_RI_INV_LSTAG_WR = 0x1a, 111 FW_RI_SEND_IMMEDIATE_WR = 0x15, 112 FW_RI_ATOMIC_WR = 0x16, 113 FW_RI_WR = 0x0d, 114 FW_CHNET_IFCONF_WR = 0x6b, 115 FW_RDEV_WR = 0x38, 116 FW_FOISCSI_NODE_WR = 0x60, 117 FW_FOISCSI_CTRL_WR = 0x6a, 118 FW_FOISCSI_CHAP_WR = 0x6c, 119 FW_FCOE_ELS_CT_WR = 0x30, 120 FW_SCSI_WRITE_WR = 0x31, 121 FW_SCSI_READ_WR = 0x32, 122 FW_SCSI_CMD_WR = 0x33, 123 FW_SCSI_ABRT_CLS_WR = 0x34, 124 FW_SCSI_TGT_ACC_WR = 0x35, 125 FW_SCSI_TGT_XMIT_WR = 0x36, 126 FW_SCSI_TGT_RSP_WR = 0x37, 127 FW_POFCOE_TCB_WR = 0x42, 128 FW_POFCOE_ULPTX_WR = 0x43, 129 FW_ISCSI_TX_DATA_WR = 0x45, 130 FW_PTP_TX_PKT_WR = 0x46, 131 FW_TLSTX_DATA_WR = 0x68, 132 FW_TLS_KEYCTX_TX_WR = 0x69, 133 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 134 FW_COiSCSI_TGT_WR = 0x70, 135 FW_COiSCSI_TGT_CONN_WR = 0x71, 136 FW_COiSCSI_TGT_XMIT_WR = 0x72, 137 FW_ISNS_WR = 0x75, 138 FW_ISNS_XMIT_WR = 0x76, 139 FW_FILTER2_WR = 0x77, 140 FW_LASTC2E_WR = 0x80 141 }; 142 143 /* 144 * Generic work request header flit0 145 */ 146 struct fw_wr_hdr { 147 __be32 hi; 148 __be32 lo; 149 }; 150 151 /* work request opcode (hi) 152 */ 153 #define S_FW_WR_OP 24 154 #define M_FW_WR_OP 0xff 155 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 156 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 157 158 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 159 */ 160 #define S_FW_WR_ATOMIC 23 161 #define M_FW_WR_ATOMIC 0x1 162 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 163 #define G_FW_WR_ATOMIC(x) \ 164 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 165 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 166 167 /* flush flag (hi) - firmware flushes flushable work request buffered 168 * in the flow context. 169 */ 170 #define S_FW_WR_FLUSH 22 171 #define M_FW_WR_FLUSH 0x1 172 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 173 #define G_FW_WR_FLUSH(x) \ 174 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 175 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 176 177 /* completion flag (hi) - firmware generates a cpl_fw6_ack 178 */ 179 #define S_FW_WR_COMPL 21 180 #define M_FW_WR_COMPL 0x1 181 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 182 #define G_FW_WR_COMPL(x) \ 183 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 184 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 185 186 187 /* work request immediate data lengh (hi) 188 */ 189 #define S_FW_WR_IMMDLEN 0 190 #define M_FW_WR_IMMDLEN 0xff 191 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 192 #define G_FW_WR_IMMDLEN(x) \ 193 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 194 195 /* egress queue status update to associated ingress queue entry (lo) 196 */ 197 #define S_FW_WR_EQUIQ 31 198 #define M_FW_WR_EQUIQ 0x1 199 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 200 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 201 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 202 203 /* egress queue status update to egress queue status entry (lo) 204 */ 205 #define S_FW_WR_EQUEQ 30 206 #define M_FW_WR_EQUEQ 0x1 207 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 208 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 209 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 210 211 /* flow context identifier (lo) 212 */ 213 #define S_FW_WR_FLOWID 8 214 #define M_FW_WR_FLOWID 0xfffff 215 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 216 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 217 218 /* length in units of 16-bytes (lo) 219 */ 220 #define S_FW_WR_LEN16 0 221 #define M_FW_WR_LEN16 0xff 222 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 223 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 224 225 struct fw_frag_wr { 226 __be32 op_to_fragoff16; 227 __be32 flowid_len16; 228 __be64 r4; 229 }; 230 231 #define S_FW_FRAG_WR_EOF 15 232 #define M_FW_FRAG_WR_EOF 0x1 233 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 234 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 235 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 236 237 #define S_FW_FRAG_WR_FRAGOFF16 8 238 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 239 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 240 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 241 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 242 243 /* valid filter configurations for compressed tuple 244 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 245 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 246 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 247 * OV - Outer VLAN/VNIC_ID, 248 */ 249 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 250 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 251 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 252 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 253 #define HW_TPL_FR_MT_E_PR_T 0x370 254 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 255 #define HW_TPL_FR_MT_E_T_P_FC 0X353 256 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 257 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 258 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 259 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 260 #define HW_TPL_FR_M_E_PR_FC 0X2E1 261 #define HW_TPL_FR_M_E_T_FC 0X2D1 262 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 263 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 264 #define HW_TPL_FR_M_T_IV_FC 0X299 265 #define HW_TPL_FR_M_T_OV_FC 0X295 266 #define HW_TPL_FR_E_PR_T_P 0X272 267 #define HW_TPL_FR_E_PR_T_FC 0X271 268 #define HW_TPL_FR_E_IV_FC 0X249 269 #define HW_TPL_FR_E_OV_FC 0X245 270 #define HW_TPL_FR_PR_T_IV_FC 0X239 271 #define HW_TPL_FR_PR_T_OV_FC 0X235 272 #define HW_TPL_FR_IV_OV_FC 0X20D 273 #define HW_TPL_MT_M_E_PR 0X1E0 274 #define HW_TPL_MT_M_E_T 0X1D0 275 #define HW_TPL_MT_E_PR_T_FC 0X171 276 #define HW_TPL_MT_E_IV 0X148 277 #define HW_TPL_MT_E_OV 0X144 278 #define HW_TPL_MT_PR_T_IV 0X138 279 #define HW_TPL_MT_PR_T_OV 0X134 280 #define HW_TPL_M_E_PR_P 0X0E2 281 #define HW_TPL_M_E_T_P 0X0D2 282 #define HW_TPL_E_PR_T_P_FC 0X073 283 #define HW_TPL_E_IV_P 0X04A 284 #define HW_TPL_E_OV_P 0X046 285 #define HW_TPL_PR_T_IV_P 0X03A 286 #define HW_TPL_PR_T_OV_P 0X036 287 288 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 289 enum fw_filter_wr_cookie { 290 FW_FILTER_WR_SUCCESS, 291 FW_FILTER_WR_FLT_ADDED, 292 FW_FILTER_WR_FLT_DELETED, 293 FW_FILTER_WR_SMT_TBL_FULL, 294 FW_FILTER_WR_EINVAL, 295 }; 296 297 enum fw_filter_wr_nat_mode { 298 FW_FILTER_WR_NATMODE_NONE = 0, 299 FW_FILTER_WR_NATMODE_DIP , 300 FW_FILTER_WR_NATMODE_DIPDP, 301 FW_FILTER_WR_NATMODE_DIPDPSIP, 302 FW_FILTER_WR_NATMODE_DIPDPSP, 303 FW_FILTER_WR_NATMODE_SIPSP, 304 FW_FILTER_WR_NATMODE_DIPSIPSP, 305 FW_FILTER_WR_NATMODE_FOURTUPLE, 306 }; 307 308 struct fw_filter_wr { 309 __be32 op_pkd; 310 __be32 len16_pkd; 311 __be64 r3; 312 __be32 tid_to_iq; 313 __be32 del_filter_to_l2tix; 314 __be16 ethtype; 315 __be16 ethtypem; 316 __u8 frag_to_ovlan_vldm; 317 __u8 smac_sel; 318 __be16 rx_chan_rx_rpl_iq; 319 __be32 maci_to_matchtypem; 320 __u8 ptcl; 321 __u8 ptclm; 322 __u8 ttyp; 323 __u8 ttypm; 324 __be16 ivlan; 325 __be16 ivlanm; 326 __be16 ovlan; 327 __be16 ovlanm; 328 __u8 lip[16]; 329 __u8 lipm[16]; 330 __u8 fip[16]; 331 __u8 fipm[16]; 332 __be16 lp; 333 __be16 lpm; 334 __be16 fp; 335 __be16 fpm; 336 __be16 r7; 337 __u8 sma[6]; 338 }; 339 340 struct fw_filter2_wr { 341 __be32 op_pkd; 342 __be32 len16_pkd; 343 __be64 r3; 344 __be32 tid_to_iq; 345 __be32 del_filter_to_l2tix; 346 __be16 ethtype; 347 __be16 ethtypem; 348 __u8 frag_to_ovlan_vldm; 349 __u8 smac_sel; 350 __be16 rx_chan_rx_rpl_iq; 351 __be32 maci_to_matchtypem; 352 __u8 ptcl; 353 __u8 ptclm; 354 __u8 ttyp; 355 __u8 ttypm; 356 __be16 ivlan; 357 __be16 ivlanm; 358 __be16 ovlan; 359 __be16 ovlanm; 360 __u8 lip[16]; 361 __u8 lipm[16]; 362 __u8 fip[16]; 363 __u8 fipm[16]; 364 __be16 lp; 365 __be16 lpm; 366 __be16 fp; 367 __be16 fpm; 368 __be16 r7; 369 __u8 sma[6]; 370 __be16 r8; 371 __u8 filter_type_swapmac; 372 __u8 natmode_to_ulp_type; 373 __be16 newlport; 374 __be16 newfport; 375 __u8 newlip[16]; 376 __u8 newfip[16]; 377 __be32 natseqcheck; 378 __be32 r9; 379 __be64 r10; 380 __be64 r11; 381 __be64 r12; 382 __be64 r13; 383 }; 384 385 #define S_FW_FILTER_WR_TID 12 386 #define M_FW_FILTER_WR_TID 0xfffff 387 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 388 #define G_FW_FILTER_WR_TID(x) \ 389 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 390 391 #define S_FW_FILTER_WR_RQTYPE 11 392 #define M_FW_FILTER_WR_RQTYPE 0x1 393 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 394 #define G_FW_FILTER_WR_RQTYPE(x) \ 395 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 396 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 397 398 #define S_FW_FILTER_WR_NOREPLY 10 399 #define M_FW_FILTER_WR_NOREPLY 0x1 400 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 401 #define G_FW_FILTER_WR_NOREPLY(x) \ 402 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 403 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 404 405 #define S_FW_FILTER_WR_IQ 0 406 #define M_FW_FILTER_WR_IQ 0x3ff 407 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 408 #define G_FW_FILTER_WR_IQ(x) \ 409 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 410 411 #define S_FW_FILTER_WR_DEL_FILTER 31 412 #define M_FW_FILTER_WR_DEL_FILTER 0x1 413 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 414 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 415 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 416 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 417 418 #define S_FW_FILTER2_WR_DROP_ENCAP 30 419 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 420 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 421 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 422 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 423 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 424 425 #define S_FW_FILTER2_WR_TX_LOOP 29 426 #define M_FW_FILTER2_WR_TX_LOOP 0x1 427 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 428 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 429 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 430 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 431 432 #define S_FW_FILTER_WR_RPTTID 25 433 #define M_FW_FILTER_WR_RPTTID 0x1 434 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 435 #define G_FW_FILTER_WR_RPTTID(x) \ 436 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 437 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 438 439 #define S_FW_FILTER_WR_DROP 24 440 #define M_FW_FILTER_WR_DROP 0x1 441 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 442 #define G_FW_FILTER_WR_DROP(x) \ 443 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 444 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 445 446 #define S_FW_FILTER_WR_DIRSTEER 23 447 #define M_FW_FILTER_WR_DIRSTEER 0x1 448 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 449 #define G_FW_FILTER_WR_DIRSTEER(x) \ 450 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 451 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 452 453 #define S_FW_FILTER_WR_MASKHASH 22 454 #define M_FW_FILTER_WR_MASKHASH 0x1 455 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 456 #define G_FW_FILTER_WR_MASKHASH(x) \ 457 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 458 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 459 460 #define S_FW_FILTER_WR_DIRSTEERHASH 21 461 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 462 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 463 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 464 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 465 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 466 467 #define S_FW_FILTER_WR_LPBK 20 468 #define M_FW_FILTER_WR_LPBK 0x1 469 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 470 #define G_FW_FILTER_WR_LPBK(x) \ 471 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 472 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 473 474 #define S_FW_FILTER_WR_DMAC 19 475 #define M_FW_FILTER_WR_DMAC 0x1 476 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 477 #define G_FW_FILTER_WR_DMAC(x) \ 478 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 479 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 480 481 #define S_FW_FILTER_WR_SMAC 18 482 #define M_FW_FILTER_WR_SMAC 0x1 483 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 484 #define G_FW_FILTER_WR_SMAC(x) \ 485 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 486 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 487 488 #define S_FW_FILTER_WR_INSVLAN 17 489 #define M_FW_FILTER_WR_INSVLAN 0x1 490 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 491 #define G_FW_FILTER_WR_INSVLAN(x) \ 492 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 493 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 494 495 #define S_FW_FILTER_WR_RMVLAN 16 496 #define M_FW_FILTER_WR_RMVLAN 0x1 497 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 498 #define G_FW_FILTER_WR_RMVLAN(x) \ 499 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 500 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 501 502 #define S_FW_FILTER_WR_HITCNTS 15 503 #define M_FW_FILTER_WR_HITCNTS 0x1 504 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 505 #define G_FW_FILTER_WR_HITCNTS(x) \ 506 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 507 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 508 509 #define S_FW_FILTER_WR_TXCHAN 13 510 #define M_FW_FILTER_WR_TXCHAN 0x3 511 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 512 #define G_FW_FILTER_WR_TXCHAN(x) \ 513 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 514 515 #define S_FW_FILTER_WR_PRIO 12 516 #define M_FW_FILTER_WR_PRIO 0x1 517 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 518 #define G_FW_FILTER_WR_PRIO(x) \ 519 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 520 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 521 522 #define S_FW_FILTER_WR_L2TIX 0 523 #define M_FW_FILTER_WR_L2TIX 0xfff 524 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 525 #define G_FW_FILTER_WR_L2TIX(x) \ 526 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 527 528 #define S_FW_FILTER_WR_FRAG 7 529 #define M_FW_FILTER_WR_FRAG 0x1 530 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 531 #define G_FW_FILTER_WR_FRAG(x) \ 532 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 533 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 534 535 #define S_FW_FILTER_WR_FRAGM 6 536 #define M_FW_FILTER_WR_FRAGM 0x1 537 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 538 #define G_FW_FILTER_WR_FRAGM(x) \ 539 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 540 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 541 542 #define S_FW_FILTER_WR_IVLAN_VLD 5 543 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 544 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 545 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 546 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 547 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 548 549 #define S_FW_FILTER_WR_OVLAN_VLD 4 550 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 551 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 552 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 553 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 554 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 555 556 #define S_FW_FILTER_WR_IVLAN_VLDM 3 557 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 558 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 559 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 560 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 561 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 562 563 #define S_FW_FILTER_WR_OVLAN_VLDM 2 564 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 565 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 566 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 567 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 568 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 569 570 #define S_FW_FILTER_WR_RX_CHAN 15 571 #define M_FW_FILTER_WR_RX_CHAN 0x1 572 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 573 #define G_FW_FILTER_WR_RX_CHAN(x) \ 574 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 575 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 576 577 #define S_FW_FILTER_WR_RX_RPL_IQ 0 578 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 579 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 580 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 581 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 582 583 #define S_FW_FILTER2_WR_FILTER_TYPE 1 584 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 585 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 586 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 587 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 588 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 589 590 #define S_FW_FILTER2_WR_SWAPMAC 0 591 #define M_FW_FILTER2_WR_SWAPMAC 0x1 592 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 593 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 594 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 595 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 596 597 #define S_FW_FILTER2_WR_NATMODE 5 598 #define M_FW_FILTER2_WR_NATMODE 0x7 599 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 600 #define G_FW_FILTER2_WR_NATMODE(x) \ 601 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 602 603 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 604 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 605 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 606 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 607 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 608 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 609 610 #define S_FW_FILTER2_WR_ULP_TYPE 0 611 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 612 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 613 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 614 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 615 616 #define S_FW_FILTER_WR_MACI 23 617 #define M_FW_FILTER_WR_MACI 0x1ff 618 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 619 #define G_FW_FILTER_WR_MACI(x) \ 620 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 621 622 #define S_FW_FILTER_WR_MACIM 14 623 #define M_FW_FILTER_WR_MACIM 0x1ff 624 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 625 #define G_FW_FILTER_WR_MACIM(x) \ 626 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 627 628 #define S_FW_FILTER_WR_FCOE 13 629 #define M_FW_FILTER_WR_FCOE 0x1 630 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 631 #define G_FW_FILTER_WR_FCOE(x) \ 632 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 633 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 634 635 #define S_FW_FILTER_WR_FCOEM 12 636 #define M_FW_FILTER_WR_FCOEM 0x1 637 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 638 #define G_FW_FILTER_WR_FCOEM(x) \ 639 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 640 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 641 642 #define S_FW_FILTER_WR_PORT 9 643 #define M_FW_FILTER_WR_PORT 0x7 644 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 645 #define G_FW_FILTER_WR_PORT(x) \ 646 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 647 648 #define S_FW_FILTER_WR_PORTM 6 649 #define M_FW_FILTER_WR_PORTM 0x7 650 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 651 #define G_FW_FILTER_WR_PORTM(x) \ 652 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 653 654 #define S_FW_FILTER_WR_MATCHTYPE 3 655 #define M_FW_FILTER_WR_MATCHTYPE 0x7 656 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 657 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 658 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 659 660 #define S_FW_FILTER_WR_MATCHTYPEM 0 661 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 662 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 663 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 664 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 665 666 struct fw_ulptx_wr { 667 __be32 op_to_compl; 668 __be32 flowid_len16; 669 __u64 cookie; 670 }; 671 672 /* flag for packet type - control packet (0), data packet (1) 673 */ 674 #define S_FW_ULPTX_WR_DATA 28 675 #define M_FW_ULPTX_WR_DATA 0x1 676 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 677 #define G_FW_ULPTX_WR_DATA(x) \ 678 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 679 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 680 681 struct fw_tp_wr { 682 __be32 op_to_immdlen; 683 __be32 flowid_len16; 684 __u64 cookie; 685 }; 686 687 struct fw_eth_tx_pkt_wr { 688 __be32 op_immdlen; 689 __be32 equiq_to_len16; 690 __be64 r3; 691 }; 692 693 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 694 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 695 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 696 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 697 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 698 699 struct fw_eth_tx_pkt2_wr { 700 __be32 op_immdlen; 701 __be32 equiq_to_len16; 702 __be32 r3; 703 __be32 L4ChkDisable_to_IpHdrLen; 704 }; 705 706 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 707 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 708 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 709 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 710 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 711 712 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 713 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 714 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 715 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 716 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 717 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 718 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 719 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 720 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 721 722 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 723 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 724 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 725 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 726 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 727 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 728 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 729 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 730 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 731 732 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 733 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 734 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 735 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 736 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 737 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 738 739 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 740 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 741 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 742 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 743 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 744 745 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 746 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 747 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 748 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 750 751 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 752 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 753 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 754 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 755 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 756 757 struct fw_eth_tx_pkts_wr { 758 __be32 op_pkd; 759 __be32 equiq_to_len16; 760 __be32 r3; 761 __be16 plen; 762 __u8 npkt; 763 __u8 type; 764 }; 765 766 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 767 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 768 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 769 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 770 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 771 772 struct fw_eth_tx_pkt_ptp_wr { 773 __be32 op_immdlen; 774 __be32 equiq_to_len16; 775 __be64 r3; 776 }; 777 778 enum fw_eth_tx_eo_type { 779 FW_ETH_TX_EO_TYPE_UDPSEG, 780 FW_ETH_TX_EO_TYPE_TCPSEG, 781 FW_ETH_TX_EO_TYPE_NVGRESEG, 782 FW_ETH_TX_EO_TYPE_VXLANSEG, 783 FW_ETH_TX_EO_TYPE_GENEVESEG, 784 }; 785 786 struct fw_eth_tx_eo_wr { 787 __be32 op_immdlen; 788 __be32 equiq_to_len16; 789 __be64 r3; 790 union fw_eth_tx_eo { 791 struct fw_eth_tx_eo_udpseg { 792 __u8 type; 793 __u8 ethlen; 794 __be16 iplen; 795 __u8 udplen; 796 __u8 rtplen; 797 __be16 r4; 798 __be16 mss; 799 __be16 schedpktsize; 800 __be32 plen; 801 } udpseg; 802 struct fw_eth_tx_eo_tcpseg { 803 __u8 type; 804 __u8 ethlen; 805 __be16 iplen; 806 __u8 tcplen; 807 __u8 tsclk_tsoff; 808 __be16 r4; 809 __be16 mss; 810 __be16 r5; 811 __be32 plen; 812 } tcpseg; 813 struct fw_eth_tx_eo_nvgreseg { 814 __u8 type; 815 __u8 iphdroffout; 816 __be16 grehdroff; 817 __be16 iphdroffin; 818 __be16 tcphdroffin; 819 __be16 mss; 820 __be16 r4; 821 __be32 plen; 822 } nvgreseg; 823 struct fw_eth_tx_eo_vxlanseg { 824 __u8 type; 825 __u8 iphdroffout; 826 __be16 vxlanhdroff; 827 __be16 iphdroffin; 828 __be16 tcphdroffin; 829 __be16 mss; 830 __be16 r4; 831 __be32 plen; 832 833 } vxlanseg; 834 struct fw_eth_tx_eo_geneveseg { 835 __u8 type; 836 __u8 iphdroffout; 837 __be16 genevehdroff; 838 __be16 iphdroffin; 839 __be16 tcphdroffin; 840 __be16 mss; 841 __be16 r4; 842 __be32 plen; 843 } geneveseg; 844 } u; 845 }; 846 847 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 848 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 849 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 850 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 851 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 852 853 #define S_FW_ETH_TX_EO_WR_TSCLK 6 854 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 855 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 856 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 857 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 858 859 #define S_FW_ETH_TX_EO_WR_TSOFF 0 860 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 861 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 862 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 863 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 864 865 struct fw_eq_flush_wr { 866 __u8 opcode; 867 __u8 r1[3]; 868 __be32 equiq_to_len16; 869 __be64 r3; 870 }; 871 872 struct fw_ofld_connection_wr { 873 __be32 op_compl; 874 __be32 len16_pkd; 875 __u64 cookie; 876 __be64 r2; 877 __be64 r3; 878 struct fw_ofld_connection_le { 879 __be32 version_cpl; 880 __be32 filter; 881 __be32 r1; 882 __be16 lport; 883 __be16 pport; 884 union fw_ofld_connection_leip { 885 struct fw_ofld_connection_le_ipv4 { 886 __be32 pip; 887 __be32 lip; 888 __be64 r0; 889 __be64 r1; 890 __be64 r2; 891 } ipv4; 892 struct fw_ofld_connection_le_ipv6 { 893 __be64 pip_hi; 894 __be64 pip_lo; 895 __be64 lip_hi; 896 __be64 lip_lo; 897 } ipv6; 898 } u; 899 } le; 900 struct fw_ofld_connection_tcb { 901 __be32 t_state_to_astid; 902 __be16 cplrxdataack_cplpassacceptrpl; 903 __be16 rcv_adv; 904 __be32 rcv_nxt; 905 __be32 tx_max; 906 __be64 opt0; 907 __be32 opt2; 908 __be32 r1; 909 __be64 r2; 910 __be64 r3; 911 } tcb; 912 }; 913 914 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 915 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 916 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 917 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 918 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 919 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 920 M_FW_OFLD_CONNECTION_WR_VERSION) 921 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 922 923 #define S_FW_OFLD_CONNECTION_WR_CPL 30 924 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 925 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 926 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 927 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 928 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 929 930 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 931 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 932 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 933 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 934 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 935 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 936 M_FW_OFLD_CONNECTION_WR_T_STATE) 937 938 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 939 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 940 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 941 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 942 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 943 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 944 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 945 946 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 947 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 948 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 949 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 950 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 951 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 952 953 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 954 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 955 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 956 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 957 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 958 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 959 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 960 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 961 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 962 963 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 964 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 965 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 966 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 967 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 968 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 969 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 970 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 971 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 972 973 enum fw_flowc_mnem_tcpstate { 974 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 975 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 976 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 977 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 978 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 979 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 980 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 981 * will resend FIN - equiv ESTAB 982 */ 983 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 984 * will resend FIN but have 985 * received FIN 986 */ 987 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 988 * will resend FIN but have 989 * received FIN 990 */ 991 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 992 * waiting for FIN 993 */ 994 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 995 }; 996 997 enum fw_flowc_mnem_eostate { 998 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 999 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1000 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1001 * outstanding payload 1002 */ 1003 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1004 * discarding outstanding payload 1005 */ 1006 }; 1007 1008 enum fw_flowc_mnem { 1009 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1010 FW_FLOWC_MNEM_CH = 1, 1011 FW_FLOWC_MNEM_PORT = 2, 1012 FW_FLOWC_MNEM_IQID = 3, 1013 FW_FLOWC_MNEM_SNDNXT = 4, 1014 FW_FLOWC_MNEM_RCVNXT = 5, 1015 FW_FLOWC_MNEM_SNDBUF = 6, 1016 FW_FLOWC_MNEM_MSS = 7, 1017 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1018 FW_FLOWC_MNEM_TCPSTATE = 9, 1019 FW_FLOWC_MNEM_EOSTATE = 10, 1020 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1021 FW_FLOWC_MNEM_DCBPRIO = 12, 1022 FW_FLOWC_MNEM_SND_SCALE = 13, 1023 FW_FLOWC_MNEM_RCV_SCALE = 14, 1024 FW_FLOWC_MNEM_ULP_MODE = 15, 1025 FW_FLOWC_MNEM_MAX = 16, 1026 }; 1027 1028 struct fw_flowc_mnemval { 1029 __u8 mnemonic; 1030 __u8 r4[3]; 1031 __be32 val; 1032 }; 1033 1034 struct fw_flowc_wr { 1035 __be32 op_to_nparams; 1036 __be32 flowid_len16; 1037 #ifndef C99_NOT_SUPPORTED 1038 struct fw_flowc_mnemval mnemval[0]; 1039 #endif 1040 }; 1041 1042 #define S_FW_FLOWC_WR_NPARAMS 0 1043 #define M_FW_FLOWC_WR_NPARAMS 0xff 1044 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1045 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1046 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1047 1048 struct fw_ofld_tx_data_wr { 1049 __be32 op_to_immdlen; 1050 __be32 flowid_len16; 1051 __be32 plen; 1052 __be32 lsodisable_to_flags; 1053 }; 1054 1055 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1056 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1057 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1058 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1059 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1060 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1061 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1062 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1063 1064 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1065 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1066 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1067 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1068 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1069 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1070 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1071 1072 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1073 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1074 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1075 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1076 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1077 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1078 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1079 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1080 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1081 1082 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1083 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1084 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1085 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1086 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1087 1088 1089 /* Use fw_ofld_tx_data_wr structure */ 1090 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1091 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1092 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1093 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1094 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1095 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1096 1097 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1098 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1099 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1100 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1101 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1102 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1103 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1104 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1105 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1106 1107 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1108 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1109 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1110 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1111 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1112 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1113 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1114 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1115 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1116 1117 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1118 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1119 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1120 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1121 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1122 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1123 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1124 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1125 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1126 1127 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1128 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1129 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1130 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1131 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1132 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1133 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1134 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1135 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1136 1137 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1138 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1139 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1140 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1141 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1142 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1143 1144 struct fw_cmd_wr { 1145 __be32 op_dma; 1146 __be32 len16_pkd; 1147 __be64 cookie_daddr; 1148 }; 1149 1150 #define S_FW_CMD_WR_DMA 17 1151 #define M_FW_CMD_WR_DMA 0x1 1152 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1153 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1154 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1155 1156 struct fw_eth_tx_pkt_vm_wr { 1157 __be32 op_immdlen; 1158 __be32 equiq_to_len16; 1159 __be32 r3[2]; 1160 __u8 ethmacdst[6]; 1161 __u8 ethmacsrc[6]; 1162 __be16 ethtype; 1163 __be16 vlantci; 1164 }; 1165 1166 struct fw_eth_tx_pkts_vm_wr { 1167 __be32 op_pkd; 1168 __be32 equiq_to_len16; 1169 __be32 r3; 1170 __be16 plen; 1171 __u8 npkt; 1172 __u8 r4; 1173 __u8 ethmacdst[6]; 1174 __u8 ethmacsrc[6]; 1175 __be16 ethtype; 1176 __be16 vlantci; 1177 }; 1178 1179 /****************************************************************************** 1180 * R I W O R K R E Q U E S T s 1181 **************************************/ 1182 1183 enum fw_ri_wr_opcode { 1184 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1185 FW_RI_READ_REQ = 0x1, 1186 FW_RI_READ_RESP = 0x2, 1187 FW_RI_SEND = 0x3, 1188 FW_RI_SEND_WITH_INV = 0x4, 1189 FW_RI_SEND_WITH_SE = 0x5, 1190 FW_RI_SEND_WITH_SE_INV = 0x6, 1191 FW_RI_TERMINATE = 0x7, 1192 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1193 FW_RI_BIND_MW = 0x9, 1194 FW_RI_FAST_REGISTER = 0xa, 1195 FW_RI_LOCAL_INV = 0xb, 1196 FW_RI_QP_MODIFY = 0xc, 1197 FW_RI_BYPASS = 0xd, 1198 FW_RI_RECEIVE = 0xe, 1199 #if 0 1200 FW_RI_SEND_IMMEDIATE = 0x8, 1201 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1202 FW_RI_ATOMIC_REQUEST = 0xa, 1203 FW_RI_ATOMIC_RESPONSE = 0xb, 1204 1205 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1206 FW_RI_FAST_REGISTER = 0xd, 1207 FW_RI_LOCAL_INV = 0xe, 1208 #endif 1209 FW_RI_SGE_EC_CR_RETURN = 0xf, 1210 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1211 }; 1212 1213 enum fw_ri_wr_flags { 1214 FW_RI_COMPLETION_FLAG = 0x01, 1215 FW_RI_NOTIFICATION_FLAG = 0x02, 1216 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1217 FW_RI_READ_FENCE_FLAG = 0x08, 1218 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1219 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1220 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40 1221 }; 1222 1223 enum fw_ri_mpa_attrs { 1224 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1225 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1226 FW_RI_MPA_CRC_ENABLE = 0x04, 1227 FW_RI_MPA_IETF_ENABLE = 0x08 1228 }; 1229 1230 enum fw_ri_qp_caps { 1231 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1232 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1233 FW_RI_QP_BIND_ENABLE = 0x04, 1234 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1235 FW_RI_QP_STAG0_ENABLE = 0x10, 1236 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1237 }; 1238 1239 enum fw_ri_addr_type { 1240 FW_RI_ZERO_BASED_TO = 0x00, 1241 FW_RI_VA_BASED_TO = 0x01 1242 }; 1243 1244 enum fw_ri_mem_perms { 1245 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1246 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1247 FW_RI_MEM_ACCESS_REM = 0x03, 1248 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1249 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1250 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1251 }; 1252 1253 enum fw_ri_stag_type { 1254 FW_RI_STAG_NSMR = 0x00, 1255 FW_RI_STAG_SMR = 0x01, 1256 FW_RI_STAG_MW = 0x02, 1257 FW_RI_STAG_MW_RELAXED = 0x03 1258 }; 1259 1260 enum fw_ri_data_op { 1261 FW_RI_DATA_IMMD = 0x81, 1262 FW_RI_DATA_DSGL = 0x82, 1263 FW_RI_DATA_ISGL = 0x83 1264 }; 1265 1266 enum fw_ri_sgl_depth { 1267 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1268 FW_RI_SGL_DEPTH_MAX_RQ = 4 1269 }; 1270 1271 enum fw_ri_cqe_err { 1272 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1273 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1274 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1275 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1276 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1277 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1278 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1279 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1280 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1281 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1282 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1283 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1284 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1285 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1286 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1287 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1288 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1289 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1290 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1291 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1292 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1293 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1294 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1295 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1296 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1297 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1298 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1299 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1300 1301 }; 1302 1303 struct fw_ri_dsge_pair { 1304 __be32 len[2]; 1305 __be64 addr[2]; 1306 }; 1307 1308 struct fw_ri_dsgl { 1309 __u8 op; 1310 __u8 r1; 1311 __be16 nsge; 1312 __be32 len0; 1313 __be64 addr0; 1314 #ifndef C99_NOT_SUPPORTED 1315 struct fw_ri_dsge_pair sge[0]; 1316 #endif 1317 }; 1318 1319 struct fw_ri_sge { 1320 __be32 stag; 1321 __be32 len; 1322 __be64 to; 1323 }; 1324 1325 struct fw_ri_isgl { 1326 __u8 op; 1327 __u8 r1; 1328 __be16 nsge; 1329 __be32 r2; 1330 #ifndef C99_NOT_SUPPORTED 1331 struct fw_ri_sge sge[0]; 1332 #endif 1333 }; 1334 1335 struct fw_ri_immd { 1336 __u8 op; 1337 __u8 r1; 1338 __be16 r2; 1339 __be32 immdlen; 1340 #ifndef C99_NOT_SUPPORTED 1341 __u8 data[0]; 1342 #endif 1343 }; 1344 1345 struct fw_ri_tpte { 1346 __be32 valid_to_pdid; 1347 __be32 locread_to_qpid; 1348 __be32 nosnoop_pbladdr; 1349 __be32 len_lo; 1350 __be32 va_hi; 1351 __be32 va_lo_fbo; 1352 __be32 dca_mwbcnt_pstag; 1353 __be32 len_hi; 1354 }; 1355 1356 #define S_FW_RI_TPTE_VALID 31 1357 #define M_FW_RI_TPTE_VALID 0x1 1358 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1359 #define G_FW_RI_TPTE_VALID(x) \ 1360 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1361 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1362 1363 #define S_FW_RI_TPTE_STAGKEY 23 1364 #define M_FW_RI_TPTE_STAGKEY 0xff 1365 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1366 #define G_FW_RI_TPTE_STAGKEY(x) \ 1367 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1368 1369 #define S_FW_RI_TPTE_STAGSTATE 22 1370 #define M_FW_RI_TPTE_STAGSTATE 0x1 1371 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1372 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1373 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1374 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1375 1376 #define S_FW_RI_TPTE_STAGTYPE 20 1377 #define M_FW_RI_TPTE_STAGTYPE 0x3 1378 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1379 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1380 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1381 1382 #define S_FW_RI_TPTE_PDID 0 1383 #define M_FW_RI_TPTE_PDID 0xfffff 1384 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1385 #define G_FW_RI_TPTE_PDID(x) \ 1386 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1387 1388 #define S_FW_RI_TPTE_PERM 28 1389 #define M_FW_RI_TPTE_PERM 0xf 1390 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1391 #define G_FW_RI_TPTE_PERM(x) \ 1392 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1393 1394 #define S_FW_RI_TPTE_REMINVDIS 27 1395 #define M_FW_RI_TPTE_REMINVDIS 0x1 1396 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1397 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1398 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1399 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1400 1401 #define S_FW_RI_TPTE_ADDRTYPE 26 1402 #define M_FW_RI_TPTE_ADDRTYPE 1 1403 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1404 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1405 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1406 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1407 1408 #define S_FW_RI_TPTE_MWBINDEN 25 1409 #define M_FW_RI_TPTE_MWBINDEN 0x1 1410 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1411 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1412 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1413 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1414 1415 #define S_FW_RI_TPTE_PS 20 1416 #define M_FW_RI_TPTE_PS 0x1f 1417 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1418 #define G_FW_RI_TPTE_PS(x) \ 1419 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1420 1421 #define S_FW_RI_TPTE_QPID 0 1422 #define M_FW_RI_TPTE_QPID 0xfffff 1423 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1424 #define G_FW_RI_TPTE_QPID(x) \ 1425 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1426 1427 #define S_FW_RI_TPTE_NOSNOOP 31 1428 #define M_FW_RI_TPTE_NOSNOOP 0x1 1429 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1430 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1431 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1432 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1433 1434 #define S_FW_RI_TPTE_PBLADDR 0 1435 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1436 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1437 #define G_FW_RI_TPTE_PBLADDR(x) \ 1438 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1439 1440 #define S_FW_RI_TPTE_DCA 24 1441 #define M_FW_RI_TPTE_DCA 0x1f 1442 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1443 #define G_FW_RI_TPTE_DCA(x) \ 1444 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1445 1446 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1447 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1448 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1449 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1450 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1451 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1452 1453 enum fw_ri_cqe_rxtx { 1454 FW_RI_CQE_RXTX_RX = 0x0, 1455 FW_RI_CQE_RXTX_TX = 0x1, 1456 }; 1457 1458 struct fw_ri_cqe { 1459 union fw_ri_rxtx { 1460 struct fw_ri_scqe { 1461 __be32 qpid_n_stat_rxtx_type; 1462 __be32 plen; 1463 __be32 stag; 1464 __be32 wrid; 1465 } scqe; 1466 struct fw_ri_rcqe { 1467 __be32 qpid_n_stat_rxtx_type; 1468 __be32 plen; 1469 __be32 stag; 1470 __be32 msn; 1471 } rcqe; 1472 struct fw_ri_rcqe_imm { 1473 __be32 qpid_n_stat_rxtx_type; 1474 __be32 plen; 1475 __be32 mo; 1476 __be32 msn; 1477 __u64 imm_data; 1478 } imm_data_rcqe; 1479 } u; 1480 }; 1481 1482 #define S_FW_RI_CQE_QPID 12 1483 #define M_FW_RI_CQE_QPID 0xfffff 1484 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1485 #define G_FW_RI_CQE_QPID(x) \ 1486 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1487 1488 #define S_FW_RI_CQE_NOTIFY 10 1489 #define M_FW_RI_CQE_NOTIFY 0x1 1490 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1491 #define G_FW_RI_CQE_NOTIFY(x) \ 1492 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1493 1494 #define S_FW_RI_CQE_STATUS 5 1495 #define M_FW_RI_CQE_STATUS 0x1f 1496 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1497 #define G_FW_RI_CQE_STATUS(x) \ 1498 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1499 1500 1501 #define S_FW_RI_CQE_RXTX 4 1502 #define M_FW_RI_CQE_RXTX 0x1 1503 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1504 #define G_FW_RI_CQE_RXTX(x) \ 1505 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1506 1507 #define S_FW_RI_CQE_TYPE 0 1508 #define M_FW_RI_CQE_TYPE 0xf 1509 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1510 #define G_FW_RI_CQE_TYPE(x) \ 1511 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1512 1513 enum fw_ri_res_type { 1514 FW_RI_RES_TYPE_SQ, 1515 FW_RI_RES_TYPE_RQ, 1516 FW_RI_RES_TYPE_CQ, 1517 FW_RI_RES_TYPE_SRQ, 1518 }; 1519 1520 enum fw_ri_res_op { 1521 FW_RI_RES_OP_WRITE, 1522 FW_RI_RES_OP_RESET, 1523 }; 1524 1525 struct fw_ri_res { 1526 union fw_ri_restype { 1527 struct fw_ri_res_sqrq { 1528 __u8 restype; 1529 __u8 op; 1530 __be16 r3; 1531 __be32 eqid; 1532 __be32 r4[2]; 1533 __be32 fetchszm_to_iqid; 1534 __be32 dcaen_to_eqsize; 1535 __be64 eqaddr; 1536 } sqrq; 1537 struct fw_ri_res_cq { 1538 __u8 restype; 1539 __u8 op; 1540 __be16 r3; 1541 __be32 iqid; 1542 __be32 r4[2]; 1543 __be32 iqandst_to_iqandstindex; 1544 __be16 iqdroprss_to_iqesize; 1545 __be16 iqsize; 1546 __be64 iqaddr; 1547 __be32 iqns_iqro; 1548 __be32 r6_lo; 1549 __be64 r7; 1550 } cq; 1551 struct fw_ri_res_srq { 1552 __u8 restype; 1553 __u8 op; 1554 __be16 r3; 1555 __be32 eqid; 1556 __be32 r4[2]; 1557 __be32 fetchszm_to_iqid; 1558 __be32 dcaen_to_eqsize; 1559 __be64 eqaddr; 1560 __be32 srqid; 1561 __be32 pdid; 1562 __be32 hwsrqsize; 1563 __be32 hwsrqaddr; 1564 } srq; 1565 } u; 1566 }; 1567 1568 struct fw_ri_res_wr { 1569 __be32 op_nres; 1570 __be32 len16_pkd; 1571 __u64 cookie; 1572 #ifndef C99_NOT_SUPPORTED 1573 struct fw_ri_res res[0]; 1574 #endif 1575 }; 1576 1577 #define S_FW_RI_RES_WR_VFN 8 1578 #define M_FW_RI_RES_WR_VFN 0xff 1579 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1580 #define G_FW_RI_RES_WR_VFN(x) \ 1581 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1582 1583 #define S_FW_RI_RES_WR_NRES 0 1584 #define M_FW_RI_RES_WR_NRES 0xff 1585 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1586 #define G_FW_RI_RES_WR_NRES(x) \ 1587 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1588 1589 #define S_FW_RI_RES_WR_FETCHSZM 26 1590 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1591 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1592 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1593 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1594 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1595 1596 #define S_FW_RI_RES_WR_STATUSPGNS 25 1597 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1598 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1599 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1600 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1601 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1602 1603 #define S_FW_RI_RES_WR_STATUSPGRO 24 1604 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1605 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1606 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1607 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1608 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1609 1610 #define S_FW_RI_RES_WR_FETCHNS 23 1611 #define M_FW_RI_RES_WR_FETCHNS 0x1 1612 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1613 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1614 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1615 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1616 1617 #define S_FW_RI_RES_WR_FETCHRO 22 1618 #define M_FW_RI_RES_WR_FETCHRO 0x1 1619 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1620 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1621 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1622 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1623 1624 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1625 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1626 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1627 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1628 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1629 1630 #define S_FW_RI_RES_WR_CPRIO 19 1631 #define M_FW_RI_RES_WR_CPRIO 0x1 1632 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1633 #define G_FW_RI_RES_WR_CPRIO(x) \ 1634 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1635 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1636 1637 #define S_FW_RI_RES_WR_ONCHIP 18 1638 #define M_FW_RI_RES_WR_ONCHIP 0x1 1639 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1640 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1641 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1642 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1643 1644 #define S_FW_RI_RES_WR_PCIECHN 16 1645 #define M_FW_RI_RES_WR_PCIECHN 0x3 1646 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1647 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1648 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1649 1650 #define S_FW_RI_RES_WR_IQID 0 1651 #define M_FW_RI_RES_WR_IQID 0xffff 1652 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1653 #define G_FW_RI_RES_WR_IQID(x) \ 1654 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1655 1656 #define S_FW_RI_RES_WR_DCAEN 31 1657 #define M_FW_RI_RES_WR_DCAEN 0x1 1658 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1659 #define G_FW_RI_RES_WR_DCAEN(x) \ 1660 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1661 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1662 1663 #define S_FW_RI_RES_WR_DCACPU 26 1664 #define M_FW_RI_RES_WR_DCACPU 0x1f 1665 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1666 #define G_FW_RI_RES_WR_DCACPU(x) \ 1667 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1668 1669 #define S_FW_RI_RES_WR_FBMIN 23 1670 #define M_FW_RI_RES_WR_FBMIN 0x7 1671 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1672 #define G_FW_RI_RES_WR_FBMIN(x) \ 1673 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1674 1675 #define S_FW_RI_RES_WR_FBMAX 20 1676 #define M_FW_RI_RES_WR_FBMAX 0x7 1677 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1678 #define G_FW_RI_RES_WR_FBMAX(x) \ 1679 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1680 1681 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1682 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1683 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1684 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1685 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1686 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1687 1688 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1689 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1690 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1691 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1692 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1693 1694 #define S_FW_RI_RES_WR_EQSIZE 0 1695 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1696 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1697 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1698 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1699 1700 #define S_FW_RI_RES_WR_IQANDST 15 1701 #define M_FW_RI_RES_WR_IQANDST 0x1 1702 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1703 #define G_FW_RI_RES_WR_IQANDST(x) \ 1704 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1705 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1706 1707 #define S_FW_RI_RES_WR_IQANUS 14 1708 #define M_FW_RI_RES_WR_IQANUS 0x1 1709 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1710 #define G_FW_RI_RES_WR_IQANUS(x) \ 1711 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1712 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1713 1714 #define S_FW_RI_RES_WR_IQANUD 12 1715 #define M_FW_RI_RES_WR_IQANUD 0x3 1716 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1717 #define G_FW_RI_RES_WR_IQANUD(x) \ 1718 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1719 1720 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1721 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1722 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1723 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1724 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1725 1726 #define S_FW_RI_RES_WR_IQDROPRSS 15 1727 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1728 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1729 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1730 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1731 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1732 1733 #define S_FW_RI_RES_WR_IQGTSMODE 14 1734 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1735 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1736 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1737 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1738 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1739 1740 #define S_FW_RI_RES_WR_IQPCIECH 12 1741 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1742 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1743 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1744 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1745 1746 #define S_FW_RI_RES_WR_IQDCAEN 11 1747 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1748 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1749 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1750 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1751 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1752 1753 #define S_FW_RI_RES_WR_IQDCACPU 6 1754 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1755 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1756 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1757 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1758 1759 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1760 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1761 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1762 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1763 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1764 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1765 1766 #define S_FW_RI_RES_WR_IQO 3 1767 #define M_FW_RI_RES_WR_IQO 0x1 1768 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1769 #define G_FW_RI_RES_WR_IQO(x) \ 1770 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1771 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1772 1773 #define S_FW_RI_RES_WR_IQCPRIO 2 1774 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1775 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1776 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1777 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1778 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1779 1780 #define S_FW_RI_RES_WR_IQESIZE 0 1781 #define M_FW_RI_RES_WR_IQESIZE 0x3 1782 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1783 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1784 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1785 1786 #define S_FW_RI_RES_WR_IQNS 31 1787 #define M_FW_RI_RES_WR_IQNS 0x1 1788 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1789 #define G_FW_RI_RES_WR_IQNS(x) \ 1790 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1791 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1792 1793 #define S_FW_RI_RES_WR_IQRO 30 1794 #define M_FW_RI_RES_WR_IQRO 0x1 1795 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1796 #define G_FW_RI_RES_WR_IQRO(x) \ 1797 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1798 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1799 1800 struct fw_ri_rdma_write_wr { 1801 __u8 opcode; 1802 __u8 flags; 1803 __u16 wrid; 1804 __u8 r1[3]; 1805 __u8 len16; 1806 __u64 immd_data; 1807 __be32 plen; 1808 __be32 stag_sink; 1809 __be64 to_sink; 1810 #ifndef C99_NOT_SUPPORTED 1811 union { 1812 struct fw_ri_immd immd_src[0]; 1813 struct fw_ri_isgl isgl_src[0]; 1814 } u; 1815 #endif 1816 }; 1817 1818 struct fw_ri_send_wr { 1819 __u8 opcode; 1820 __u8 flags; 1821 __u16 wrid; 1822 __u8 r1[3]; 1823 __u8 len16; 1824 __be32 sendop_pkd; 1825 __be32 stag_inv; 1826 __be32 plen; 1827 __be32 r3; 1828 __be64 r4; 1829 #ifndef C99_NOT_SUPPORTED 1830 union { 1831 struct fw_ri_immd immd_src[0]; 1832 struct fw_ri_isgl isgl_src[0]; 1833 } u; 1834 #endif 1835 }; 1836 1837 #define S_FW_RI_SEND_WR_SENDOP 0 1838 #define M_FW_RI_SEND_WR_SENDOP 0xf 1839 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1840 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1841 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1842 1843 struct fw_ri_rdma_write_cmpl_wr { 1844 __u8 opcode; 1845 __u8 flags; 1846 __u16 wrid; 1847 __u8 r1[3]; 1848 __u8 len16; 1849 __u8 r2; 1850 __u8 flags_send; 1851 __u16 wrid_send; 1852 __be32 stag_inv; 1853 __be32 plen; 1854 __be32 stag_sink; 1855 __be64 to_sink; 1856 union fw_ri_cmpl { 1857 struct fw_ri_immd_cmpl { 1858 __u8 op; 1859 __u8 r1[6]; 1860 __u8 immdlen; 1861 __u8 data[16]; 1862 } immd_src; 1863 struct fw_ri_isgl isgl_src; 1864 } u_cmpl; 1865 __be64 r3; 1866 #ifndef C99_NOT_SUPPORTED 1867 union fw_ri_write { 1868 struct fw_ri_immd immd_src[0]; 1869 struct fw_ri_isgl isgl_src[0]; 1870 } u; 1871 #endif 1872 }; 1873 1874 struct fw_ri_rdma_read_wr { 1875 __u8 opcode; 1876 __u8 flags; 1877 __u16 wrid; 1878 __u8 r1[3]; 1879 __u8 len16; 1880 __be64 r2; 1881 __be32 stag_sink; 1882 __be32 to_sink_hi; 1883 __be32 to_sink_lo; 1884 __be32 plen; 1885 __be32 stag_src; 1886 __be32 to_src_hi; 1887 __be32 to_src_lo; 1888 __be32 r5; 1889 }; 1890 1891 struct fw_ri_recv_wr { 1892 __u8 opcode; 1893 __u8 r1; 1894 __u16 wrid; 1895 __u8 r2[3]; 1896 __u8 len16; 1897 struct fw_ri_isgl isgl; 1898 }; 1899 1900 struct fw_ri_bind_mw_wr { 1901 __u8 opcode; 1902 __u8 flags; 1903 __u16 wrid; 1904 __u8 r1[3]; 1905 __u8 len16; 1906 __u8 qpbinde_to_dcacpu; 1907 __u8 pgsz_shift; 1908 __u8 addr_type; 1909 __u8 mem_perms; 1910 __be32 stag_mr; 1911 __be32 stag_mw; 1912 __be32 r3; 1913 __be64 len_mw; 1914 __be64 va_fbo; 1915 __be64 r4; 1916 }; 1917 1918 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1919 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1920 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1921 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1922 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1923 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1924 1925 #define S_FW_RI_BIND_MW_WR_NS 5 1926 #define M_FW_RI_BIND_MW_WR_NS 0x1 1927 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1928 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1929 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1930 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1931 1932 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1933 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1934 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1935 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1936 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1937 1938 struct fw_ri_fr_nsmr_wr { 1939 __u8 opcode; 1940 __u8 flags; 1941 __u16 wrid; 1942 __u8 r1[3]; 1943 __u8 len16; 1944 __u8 qpbinde_to_dcacpu; 1945 __u8 pgsz_shift; 1946 __u8 addr_type; 1947 __u8 mem_perms; 1948 __be32 stag; 1949 __be32 len_hi; 1950 __be32 len_lo; 1951 __be32 va_hi; 1952 __be32 va_lo_fbo; 1953 }; 1954 1955 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1956 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1957 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1958 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1959 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1960 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1961 1962 #define S_FW_RI_FR_NSMR_WR_NS 5 1963 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1964 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1965 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1966 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1967 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1968 1969 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1970 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1971 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1972 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1973 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1974 1975 struct fw_ri_fr_nsmr_tpte_wr { 1976 __u8 opcode; 1977 __u8 flags; 1978 __u16 wrid; 1979 __u8 r1[3]; 1980 __u8 len16; 1981 __be32 r2; 1982 __be32 stag; 1983 struct fw_ri_tpte tpte; 1984 __be64 pbl[2]; 1985 }; 1986 1987 struct fw_ri_inv_lstag_wr { 1988 __u8 opcode; 1989 __u8 flags; 1990 __u16 wrid; 1991 __u8 r1[3]; 1992 __u8 len16; 1993 __be32 r2; 1994 __be32 stag_inv; 1995 }; 1996 1997 struct fw_ri_send_immediate_wr { 1998 __u8 opcode; 1999 __u8 flags; 2000 __u16 wrid; 2001 __u8 r1[3]; 2002 __u8 len16; 2003 __be32 sendimmop_pkd; 2004 __be32 r3; 2005 __be32 plen; 2006 __be32 r4; 2007 __be64 r5; 2008 #ifndef C99_NOT_SUPPORTED 2009 struct fw_ri_immd immd_src[0]; 2010 #endif 2011 }; 2012 2013 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2014 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2015 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2016 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2017 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2018 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2019 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2020 2021 enum fw_ri_atomic_op { 2022 FW_RI_ATOMIC_OP_FETCHADD, 2023 FW_RI_ATOMIC_OP_SWAP, 2024 FW_RI_ATOMIC_OP_CMDSWAP, 2025 }; 2026 2027 struct fw_ri_atomic_wr { 2028 __u8 opcode; 2029 __u8 flags; 2030 __u16 wrid; 2031 __u8 r1[3]; 2032 __u8 len16; 2033 __be32 atomicop_pkd; 2034 __be64 r3; 2035 __be32 aopcode_pkd; 2036 __be32 reqid; 2037 __be32 stag; 2038 __be32 to_hi; 2039 __be32 to_lo; 2040 __be32 addswap_data_hi; 2041 __be32 addswap_data_lo; 2042 __be32 addswap_mask_hi; 2043 __be32 addswap_mask_lo; 2044 __be32 compare_data_hi; 2045 __be32 compare_data_lo; 2046 __be32 compare_mask_hi; 2047 __be32 compare_mask_lo; 2048 __be32 r5; 2049 }; 2050 2051 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2052 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2053 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2054 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2055 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2056 2057 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2058 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2059 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2060 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2061 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2062 2063 enum fw_ri_type { 2064 FW_RI_TYPE_INIT, 2065 FW_RI_TYPE_FINI, 2066 FW_RI_TYPE_TERMINATE 2067 }; 2068 2069 enum fw_ri_init_p2ptype { 2070 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2071 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2072 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2073 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2074 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2075 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2076 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2077 }; 2078 2079 enum fw_ri_init_rqeqid_srq { 2080 FW_RI_INIT_RQEQID_SRQ = 1U << 31, 2081 }; 2082 2083 struct fw_ri_wr { 2084 __be32 op_compl; 2085 __be32 flowid_len16; 2086 __u64 cookie; 2087 union fw_ri { 2088 struct fw_ri_init { 2089 __u8 type; 2090 __u8 mpareqbit_p2ptype; 2091 __u8 r4[2]; 2092 __u8 mpa_attrs; 2093 __u8 qp_caps; 2094 __be16 nrqe; 2095 __be32 pdid; 2096 __be32 qpid; 2097 __be32 sq_eqid; 2098 __be32 rq_eqid; 2099 __be32 scqid; 2100 __be32 rcqid; 2101 __be32 ord_max; 2102 __be32 ird_max; 2103 __be32 iss; 2104 __be32 irs; 2105 __be32 hwrqsize; 2106 __be32 hwrqaddr; 2107 __be64 r5; 2108 union fw_ri_init_p2p { 2109 struct fw_ri_rdma_write_wr write; 2110 struct fw_ri_rdma_read_wr read; 2111 struct fw_ri_send_wr send; 2112 } u; 2113 } init; 2114 struct fw_ri_fini { 2115 __u8 type; 2116 __u8 r3[7]; 2117 __be64 r4; 2118 } fini; 2119 struct fw_ri_terminate { 2120 __u8 type; 2121 __u8 r3[3]; 2122 __be32 immdlen; 2123 __u8 termmsg[40]; 2124 } terminate; 2125 } u; 2126 }; 2127 2128 #define S_FW_RI_WR_MPAREQBIT 7 2129 #define M_FW_RI_WR_MPAREQBIT 0x1 2130 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2131 #define G_FW_RI_WR_MPAREQBIT(x) \ 2132 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2133 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2134 2135 #define S_FW_RI_WR_0BRRBIT 6 2136 #define M_FW_RI_WR_0BRRBIT 0x1 2137 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2138 #define G_FW_RI_WR_0BRRBIT(x) \ 2139 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2140 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2141 2142 #define S_FW_RI_WR_P2PTYPE 0 2143 #define M_FW_RI_WR_P2PTYPE 0xf 2144 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2145 #define G_FW_RI_WR_P2PTYPE(x) \ 2146 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2147 2148 /****************************************************************************** 2149 * F O i S C S I W O R K R E Q U E S T s 2150 *********************************************/ 2151 2152 #define FW_FOISCSI_NAME_MAX_LEN 224 2153 #define FW_FOISCSI_ALIAS_MAX_LEN 224 2154 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 2155 #define FW_FOISCSI_INIT_NODE_MAX 8 2156 2157 enum fw_chnet_ifconf_wr_subop { 2158 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 2159 2160 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 2161 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 2162 2163 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 2164 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 2165 2166 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 2167 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 2168 2169 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 2170 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 2171 2172 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 2173 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 2174 2175 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 2176 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 2177 2178 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2179 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2180 2181 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2182 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2183 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2184 2185 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2186 }; 2187 2188 struct fw_chnet_ifconf_wr { 2189 __be32 op_compl; 2190 __be32 flowid_len16; 2191 __be64 cookie; 2192 __be32 if_flowid; 2193 __u8 idx; 2194 __u8 subop; 2195 __u8 retval; 2196 __u8 r2; 2197 __be64 r3; 2198 struct fw_chnet_ifconf_params { 2199 __be32 r0; 2200 __be16 vlanid; 2201 __be16 mtu; 2202 union fw_chnet_ifconf_addr_type { 2203 struct fw_chnet_ifconf_ipv4 { 2204 __be32 addr; 2205 __be32 mask; 2206 __be32 router; 2207 __be32 r0; 2208 __be64 r1; 2209 } ipv4; 2210 struct fw_chnet_ifconf_ipv6 { 2211 __u8 prefix_len; 2212 __u8 r0; 2213 __be16 r1; 2214 __be32 r2; 2215 __be64 addr_hi; 2216 __be64 addr_lo; 2217 __be64 router_hi; 2218 __be64 router_lo; 2219 } ipv6; 2220 } in_attr; 2221 } param; 2222 }; 2223 2224 enum fw_foiscsi_node_type { 2225 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2226 FW_FOISCSI_NODE_TYPE_TARGET, 2227 }; 2228 2229 enum fw_foiscsi_session_type { 2230 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2231 FW_FOISCSI_SESSION_TYPE_NORMAL, 2232 }; 2233 2234 enum fw_foiscsi_auth_policy { 2235 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2236 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2237 }; 2238 2239 enum fw_foiscsi_auth_method { 2240 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2241 FW_FOISCSI_AUTH_METHOD_CHAP, 2242 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2243 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2244 }; 2245 2246 enum fw_foiscsi_digest_type { 2247 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2248 FW_FOISCSI_DIGEST_TYPE_CRC32, 2249 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2250 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2251 }; 2252 2253 enum fw_foiscsi_wr_subop { 2254 FW_FOISCSI_WR_SUBOP_ADD = 1, 2255 FW_FOISCSI_WR_SUBOP_DEL = 2, 2256 FW_FOISCSI_WR_SUBOP_MOD = 4, 2257 }; 2258 2259 enum fw_foiscsi_ctrl_state { 2260 FW_FOISCSI_CTRL_STATE_FREE = 0, 2261 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2262 FW_FOISCSI_CTRL_STATE_FAILED, 2263 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2264 FW_FOISCSI_CTRL_STATE_REDIRECT, 2265 }; 2266 2267 struct fw_rdev_wr { 2268 __be32 op_to_immdlen; 2269 __be32 alloc_to_len16; 2270 __be64 cookie; 2271 __u8 protocol; 2272 __u8 event_cause; 2273 __u8 cur_state; 2274 __u8 prev_state; 2275 __be32 flags_to_assoc_flowid; 2276 union rdev_entry { 2277 struct fcoe_rdev_entry { 2278 __be32 flowid; 2279 __u8 protocol; 2280 __u8 event_cause; 2281 __u8 flags; 2282 __u8 rjt_reason; 2283 __u8 cur_login_st; 2284 __u8 prev_login_st; 2285 __be16 rcv_fr_sz; 2286 __u8 rd_xfer_rdy_to_rport_type; 2287 __u8 vft_to_qos; 2288 __u8 org_proc_assoc_to_acc_rsp_code; 2289 __u8 enh_disc_to_tgt; 2290 __u8 wwnn[8]; 2291 __u8 wwpn[8]; 2292 __be16 iqid; 2293 __u8 fc_oui[3]; 2294 __u8 r_id[3]; 2295 } fcoe_rdev; 2296 struct iscsi_rdev_entry { 2297 __be32 flowid; 2298 __u8 protocol; 2299 __u8 event_cause; 2300 __u8 flags; 2301 __u8 r3; 2302 __be16 iscsi_opts; 2303 __be16 tcp_opts; 2304 __be16 ip_opts; 2305 __be16 max_rcv_len; 2306 __be16 max_snd_len; 2307 __be16 first_brst_len; 2308 __be16 max_brst_len; 2309 __be16 r4; 2310 __be16 def_time2wait; 2311 __be16 def_time2ret; 2312 __be16 nop_out_intrvl; 2313 __be16 non_scsi_to; 2314 __be16 isid; 2315 __be16 tsid; 2316 __be16 port; 2317 __be16 tpgt; 2318 __u8 r5[6]; 2319 __be16 iqid; 2320 } iscsi_rdev; 2321 } u; 2322 }; 2323 2324 #define S_FW_RDEV_WR_IMMDLEN 0 2325 #define M_FW_RDEV_WR_IMMDLEN 0xff 2326 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2327 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2328 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2329 2330 #define S_FW_RDEV_WR_ALLOC 31 2331 #define M_FW_RDEV_WR_ALLOC 0x1 2332 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2333 #define G_FW_RDEV_WR_ALLOC(x) \ 2334 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2335 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2336 2337 #define S_FW_RDEV_WR_FREE 30 2338 #define M_FW_RDEV_WR_FREE 0x1 2339 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2340 #define G_FW_RDEV_WR_FREE(x) \ 2341 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2342 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2343 2344 #define S_FW_RDEV_WR_MODIFY 29 2345 #define M_FW_RDEV_WR_MODIFY 0x1 2346 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2347 #define G_FW_RDEV_WR_MODIFY(x) \ 2348 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2349 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2350 2351 #define S_FW_RDEV_WR_FLOWID 8 2352 #define M_FW_RDEV_WR_FLOWID 0xfffff 2353 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2354 #define G_FW_RDEV_WR_FLOWID(x) \ 2355 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2356 2357 #define S_FW_RDEV_WR_LEN16 0 2358 #define M_FW_RDEV_WR_LEN16 0xff 2359 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2360 #define G_FW_RDEV_WR_LEN16(x) \ 2361 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2362 2363 #define S_FW_RDEV_WR_FLAGS 24 2364 #define M_FW_RDEV_WR_FLAGS 0xff 2365 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2366 #define G_FW_RDEV_WR_FLAGS(x) \ 2367 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2368 2369 #define S_FW_RDEV_WR_GET_NEXT 20 2370 #define M_FW_RDEV_WR_GET_NEXT 0xf 2371 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2372 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2373 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2374 2375 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2376 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2377 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2378 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2379 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2380 2381 #define S_FW_RDEV_WR_RJT 7 2382 #define M_FW_RDEV_WR_RJT 0x1 2383 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2384 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2385 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2386 2387 #define S_FW_RDEV_WR_REASON 0 2388 #define M_FW_RDEV_WR_REASON 0x7f 2389 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2390 #define G_FW_RDEV_WR_REASON(x) \ 2391 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2392 2393 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2394 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2395 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2396 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2397 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2398 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2399 2400 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2401 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2402 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2403 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2404 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2405 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2406 2407 #define S_FW_RDEV_WR_FC_SP 5 2408 #define M_FW_RDEV_WR_FC_SP 0x1 2409 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2410 #define G_FW_RDEV_WR_FC_SP(x) \ 2411 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2412 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2413 2414 #define S_FW_RDEV_WR_RPORT_TYPE 0 2415 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2416 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2417 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2418 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2419 2420 #define S_FW_RDEV_WR_VFT 7 2421 #define M_FW_RDEV_WR_VFT 0x1 2422 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2423 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2424 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2425 2426 #define S_FW_RDEV_WR_NPIV 6 2427 #define M_FW_RDEV_WR_NPIV 0x1 2428 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2429 #define G_FW_RDEV_WR_NPIV(x) \ 2430 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2431 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2432 2433 #define S_FW_RDEV_WR_CLASS 4 2434 #define M_FW_RDEV_WR_CLASS 0x3 2435 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2436 #define G_FW_RDEV_WR_CLASS(x) \ 2437 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2438 2439 #define S_FW_RDEV_WR_SEQ_DEL 3 2440 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2441 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2442 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2443 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2444 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2445 2446 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2447 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2448 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2449 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2450 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2451 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2452 2453 #define S_FW_RDEV_WR_PREF 1 2454 #define M_FW_RDEV_WR_PREF 0x1 2455 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2456 #define G_FW_RDEV_WR_PREF(x) \ 2457 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2458 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2459 2460 #define S_FW_RDEV_WR_QOS 0 2461 #define M_FW_RDEV_WR_QOS 0x1 2462 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2463 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2464 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2465 2466 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2467 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2468 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2469 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2470 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2471 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2472 2473 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2474 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2475 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2476 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2477 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2478 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2479 2480 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2481 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2482 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2483 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2484 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2485 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2486 2487 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2488 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2489 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2490 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2491 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2492 2493 #define S_FW_RDEV_WR_ENH_DISC 7 2494 #define M_FW_RDEV_WR_ENH_DISC 0x1 2495 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2496 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2497 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2498 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2499 2500 #define S_FW_RDEV_WR_REC 6 2501 #define M_FW_RDEV_WR_REC 0x1 2502 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2503 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2504 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2505 2506 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2507 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2508 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2509 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2510 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2511 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2512 2513 #define S_FW_RDEV_WR_RETRY 4 2514 #define M_FW_RDEV_WR_RETRY 0x1 2515 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2516 #define G_FW_RDEV_WR_RETRY(x) \ 2517 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2518 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2519 2520 #define S_FW_RDEV_WR_CONF_CMPL 3 2521 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2522 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2523 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2524 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2525 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2526 2527 #define S_FW_RDEV_WR_DATA_OVLY 2 2528 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2529 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2530 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2531 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2532 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2533 2534 #define S_FW_RDEV_WR_INI 1 2535 #define M_FW_RDEV_WR_INI 0x1 2536 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2537 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2538 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2539 2540 #define S_FW_RDEV_WR_TGT 0 2541 #define M_FW_RDEV_WR_TGT 0x1 2542 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2543 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2544 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2545 2546 struct fw_foiscsi_node_wr { 2547 __be32 op_to_immdlen; 2548 __be32 flowid_len16; 2549 __u64 cookie; 2550 __u8 subop; 2551 __u8 status; 2552 __u8 alias_len; 2553 __u8 iqn_len; 2554 __be32 node_flowid; 2555 __be16 nodeid; 2556 __be16 login_retry; 2557 __be16 retry_timeout; 2558 __be16 r3; 2559 __u8 iqn[224]; 2560 __u8 alias[224]; 2561 }; 2562 2563 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2564 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2565 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2566 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2567 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2568 2569 struct fw_foiscsi_ctrl_wr { 2570 __be32 op_compl; 2571 __be32 flowid_len16; 2572 __u64 cookie; 2573 __u8 subop; 2574 __u8 sta