1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Chelsio Terminator 4 (T4) Firmware interface header file. 14 * 15 * Copyright (C) 2009-2013 Chelsio Communications. All rights reserved. 16 * 17 * Written by felix marti (felix@chelsio.com) 18 * 19 * This program is distributed in the hope that it will be useful, but WITHOUT 20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 21 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 22 * release for licensing terms and conditions. 23 */ 24 #ifndef _T4FW_INTERFACE_H_ 25 #define _T4FW_INTERFACE_H_ 26 27 /* 28 * ****************************** 29 * R E T U R N V A L U E S 30 * ****************************** 31 */ 32 33 enum fw_retval { 34 FW_SUCCESS = 0, /* completed sucessfully */ 35 FW_EPERM = 1, /* operation not permitted */ 36 FW_ENOENT = 2, /* no such file or directory */ 37 FW_EIO = 5, /* input/output error; hw bad */ 38 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 39 FW_EAGAIN = 11, /* try again */ 40 FW_ENOMEM = 12, /* out of memory */ 41 FW_EFAULT = 14, /* bad address; fw bad */ 42 FW_EBUSY = 16, /* resource busy */ 43 FW_EEXIST = 17, /* file exists */ 44 FW_EINVAL = 22, /* invalid argument */ 45 FW_ENOSPC = 28, /* no space left on device */ 46 FW_ENOSYS = 38, /* functionality not implemented */ 47 FW_EPROTO = 71, /* protocol error */ 48 FW_EADDRINUSE = 98, /* address already in use */ 49 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 50 FW_ENETDOWN = 100, /* network is down */ 51 FW_ENETUNREACH = 101, /* network is unreachable */ 52 FW_ENOBUFS = 105, /* no buffer space available */ 53 FW_ETIMEDOUT = 110, /* timeout */ 54 FW_EINPROGRESS = 115, /* fw internal */ 55 FW_SCSI_ABORT_REQUESTED = 128, /* */ 56 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 57 FW_SCSI_ABORTED = 130, /* */ 58 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 59 FW_ERR_LINK_DOWN = 132, /* */ 60 FW_RDEV_NOT_READY = 133, /* */ 61 FW_ERR_RDEV_LOST = 134, /* */ 62 FW_ERR_RDEV_LOGO = 135, /* */ 63 FW_FCOE_NO_XCHG = 136, /* */ 64 FW_SCSI_RSP_ERR = 137, /* */ 65 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 66 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 67 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 68 FW_SCSI_DDP_ERR = 141, /* DDP error */ 69 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 70 }; 71 72 /* 73 * ****************************** 74 * W O R K R E Q U E S T s 75 * ****************************** 76 */ 77 78 enum fw_wr_opcodes { 79 FW_FILTER_WR = 0x02, 80 FW_ULPTX_WR = 0x04, 81 FW_TP_WR = 0x05, 82 FW_ETH_TX_PKT_WR = 0x08, 83 FW_ETH_TX_PKTS_WR = 0x09, 84 FW_ETH_TX_UO_WR = 0x1c, 85 FW_EQ_FLUSH_WR = 0x1b, 86 FW_OFLD_CONNECTION_WR = 0x2f, 87 FW_FLOWC_WR = 0x0a, 88 FW_OFLD_TX_DATA_WR = 0x0b, 89 FW_CMD_WR = 0x10, 90 FW_ETH_TX_PKT_VM_WR = 0x11, 91 FW_RI_RES_WR = 0x0c, 92 FW_RI_RDMA_WRITE_WR = 0x14, 93 FW_RI_SEND_WR = 0x15, 94 FW_RI_RDMA_READ_WR = 0x16, 95 FW_RI_RECV_WR = 0x17, 96 FW_RI_BIND_MW_WR = 0x18, 97 FW_RI_FR_NSMR_WR = 0x19, 98 FW_RI_INV_LSTAG_WR = 0x1a, 99 FW_RI_SEND_IMMEDIATE_WR = 0x15, 100 FW_RI_ATOMIC_WR = 0x16, 101 FW_RI_WR = 0x0d, 102 FW_CHNET_IFCONF_WR = 0x6b, 103 FW_RDEV_WR = 0x38, 104 FW_FOISCSI_NODE_WR = 0x60, 105 FW_FOISCSI_CTRL_WR = 0x6a, 106 FW_FOISCSI_CHAP_WR = 0x6c, 107 FW_FCOE_ELS_CT_WR = 0x30, 108 FW_SCSI_WRITE_WR = 0x31, 109 FW_SCSI_READ_WR = 0x32, 110 FW_SCSI_CMD_WR = 0x33, 111 FW_SCSI_ABRT_CLS_WR = 0x34, 112 FW_SCSI_TGT_ACC_WR = 0x35, 113 FW_SCSI_TGT_XMIT_WR = 0x36, 114 FW_SCSI_TGT_RSP_WR = 0x37, 115 FW_LASTC2E_WR = 0x70 116 }; 117 118 /* 119 * Generic work request header flit0 120 */ 121 struct fw_wr_hdr { 122 __be32 hi; 123 __be32 lo; 124 }; 125 126 /* work request opcode (hi) */ 127 #define S_FW_WR_OP 24 128 #define M_FW_WR_OP 0xff 129 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 130 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 131 132 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 133 #define S_FW_WR_ATOMIC 23 134 #define M_FW_WR_ATOMIC 0x1 135 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 136 #define G_FW_WR_ATOMIC(x) \ 137 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 138 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 139 140 /* 141 * flush flag (hi) - firmware flushes flushable work request buffered 142 * in the flow context. 143 */ 144 #define S_FW_WR_FLUSH 22 145 #define M_FW_WR_FLUSH 0x1 146 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 147 #define G_FW_WR_FLUSH(x) \ 148 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 149 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 150 151 /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 152 #define S_FW_WR_COMPL 21 153 #define M_FW_WR_COMPL 0x1 154 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 155 #define G_FW_WR_COMPL(x) \ 156 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 157 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 158 159 /* work request immediate data lengh (hi) */ 160 #define S_FW_WR_IMMDLEN 0 161 #define M_FW_WR_IMMDLEN 0xff 162 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 163 #define G_FW_WR_IMMDLEN(x) \ 164 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 165 166 /* egress queue status update to associated ingress queue entry (lo) */ 167 #define S_FW_WR_EQUIQ 31 168 #define M_FW_WR_EQUIQ 0x1 169 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 170 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 171 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 172 173 /* egress queue status update to egress queue status entry (lo) */ 174 #define S_FW_WR_EQUEQ 30 175 #define M_FW_WR_EQUEQ 0x1 176 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 177 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 178 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 179 180 /* flow context identifier (lo) */ 181 #define S_FW_WR_FLOWID 8 182 #define M_FW_WR_FLOWID 0xfffff 183 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 184 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 185 186 /* length in units of 16-bytes (lo) */ 187 #define S_FW_WR_LEN16 0 188 #define M_FW_WR_LEN16 0xff 189 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 190 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 191 192 /* 193 * valid filter configurations for compressed tuple 194 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 195 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 196 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 197 * OV - Outer VLAN/VNIC_ID, 198 */ 199 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 200 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 201 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 202 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 203 #define HW_TPL_FR_MT_E_PR_T 0x370 204 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 205 #define HW_TPL_FR_MT_E_T_P_FC 0X353 206 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 207 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 208 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 209 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 210 #define HW_TPL_FR_M_E_PR_FC 0X2E1 211 #define HW_TPL_FR_M_E_T_FC 0X2D1 212 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 213 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 214 #define HW_TPL_FR_M_T_IV_FC 0X299 215 #define HW_TPL_FR_M_T_OV_FC 0X295 216 #define HW_TPL_FR_E_PR_T_P 0X272 217 #define HW_TPL_FR_E_PR_T_FC 0X271 218 #define HW_TPL_FR_E_IV_FC 0X249 219 #define HW_TPL_FR_E_OV_FC 0X245 220 #define HW_TPL_FR_PR_T_IV_FC 0X239 221 #define HW_TPL_FR_PR_T_OV_FC 0X235 222 #define HW_TPL_FR_IV_OV_FC 0X20D 223 #define HW_TPL_MT_M_E_PR 0X1E0 224 #define HW_TPL_MT_M_E_T 0X1D0 225 #define HW_TPL_MT_E_PR_T_FC 0X171 226 #define HW_TPL_MT_E_IV 0X148 227 #define HW_TPL_MT_E_OV 0X144 228 #define HW_TPL_MT_PR_T_IV 0X138 229 #define HW_TPL_MT_PR_T_OV 0X134 230 #define HW_TPL_M_E_PR_P 0X0E2 231 #define HW_TPL_M_E_T_P 0X0D2 232 #define HW_TPL_E_PR_T_P_FC 0X073 233 #define HW_TPL_E_IV_P 0X04A 234 #define HW_TPL_E_OV_P 0X046 235 #define HW_TPL_PR_T_IV_P 0X03A 236 #define HW_TPL_PR_T_OV_P 0X036 237 238 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 239 enum fw_filter_wr_cookie { 240 FW_FILTER_WR_SUCCESS, 241 FW_FILTER_WR_FLT_ADDED, 242 FW_FILTER_WR_FLT_DELETED, 243 FW_FILTER_WR_SMT_TBL_FULL, 244 FW_FILTER_WR_EINVAL, 245 }; 246 247 struct fw_filter_wr { 248 __be32 op_pkd; 249 __be32 len16_pkd; 250 __be64 r3; 251 __be32 tid_to_iq; 252 __be32 del_filter_to_l2tix; 253 __be16 ethtype; 254 __be16 ethtypem; 255 __u8 frag_to_ovlan_vldm; 256 __u8 smac_sel; 257 __be16 rx_chan_rx_rpl_iq; 258 __be32 maci_to_matchtypem; 259 __u8 ptcl; 260 __u8 ptclm; 261 __u8 ttyp; 262 __u8 ttypm; 263 __be16 ivlan; 264 __be16 ivlanm; 265 __be16 ovlan; 266 __be16 ovlanm; 267 __u8 lip[16]; 268 __u8 lipm[16]; 269 __u8 fip[16]; 270 __u8 fipm[16]; 271 __be16 lp; 272 __be16 lpm; 273 __be16 fp; 274 __be16 fpm; 275 __be16 r7; 276 __u8 sma[6]; 277 }; 278 279 #define S_FW_FILTER_WR_TID 12 280 #define M_FW_FILTER_WR_TID 0xfffff 281 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 282 #define G_FW_FILTER_WR_TID(x) \ 283 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 284 285 #define S_FW_FILTER_WR_RQTYPE 11 286 #define M_FW_FILTER_WR_RQTYPE 0x1 287 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 288 #define G_FW_FILTER_WR_RQTYPE(x) \ 289 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 290 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 291 292 #define S_FW_FILTER_WR_NOREPLY 10 293 #define M_FW_FILTER_WR_NOREPLY 0x1 294 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 295 #define G_FW_FILTER_WR_NOREPLY(x) \ 296 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 297 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 298 299 #define S_FW_FILTER_WR_IQ 0 300 #define M_FW_FILTER_WR_IQ 0x3ff 301 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 302 #define G_FW_FILTER_WR_IQ(x) \ 303 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 304 305 #define S_FW_FILTER_WR_DEL_FILTER 31 306 #define M_FW_FILTER_WR_DEL_FILTER 0x1 307 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 308 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 309 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 310 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 311 312 #define S_FW_FILTER_WR_RPTTID 25 313 #define M_FW_FILTER_WR_RPTTID 0x1 314 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 315 #define G_FW_FILTER_WR_RPTTID(x) \ 316 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 317 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 318 319 #define S_FW_FILTER_WR_DROP 24 320 #define M_FW_FILTER_WR_DROP 0x1 321 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 322 #define G_FW_FILTER_WR_DROP(x) \ 323 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 324 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 325 326 #define S_FW_FILTER_WR_DIRSTEER 23 327 #define M_FW_FILTER_WR_DIRSTEER 0x1 328 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 329 #define G_FW_FILTER_WR_DIRSTEER(x) \ 330 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 331 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 332 333 #define S_FW_FILTER_WR_MASKHASH 22 334 #define M_FW_FILTER_WR_MASKHASH 0x1 335 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 336 #define G_FW_FILTER_WR_MASKHASH(x) \ 337 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 338 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 339 340 #define S_FW_FILTER_WR_DIRSTEERHASH 21 341 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 342 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 343 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 344 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 345 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 346 347 #define S_FW_FILTER_WR_LPBK 20 348 #define M_FW_FILTER_WR_LPBK 0x1 349 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 350 #define G_FW_FILTER_WR_LPBK(x) \ 351 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 352 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 353 354 #define S_FW_FILTER_WR_DMAC 19 355 #define M_FW_FILTER_WR_DMAC 0x1 356 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 357 #define G_FW_FILTER_WR_DMAC(x) \ 358 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 359 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 360 361 #define S_FW_FILTER_WR_SMAC 18 362 #define M_FW_FILTER_WR_SMAC 0x1 363 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 364 #define G_FW_FILTER_WR_SMAC(x) \ 365 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 366 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 367 368 #define S_FW_FILTER_WR_INSVLAN 17 369 #define M_FW_FILTER_WR_INSVLAN 0x1 370 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 371 #define G_FW_FILTER_WR_INSVLAN(x) \ 372 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 373 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 374 375 #define S_FW_FILTER_WR_RMVLAN 16 376 #define M_FW_FILTER_WR_RMVLAN 0x1 377 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 378 #define G_FW_FILTER_WR_RMVLAN(x) \ 379 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 380 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 381 382 #define S_FW_FILTER_WR_HITCNTS 15 383 #define M_FW_FILTER_WR_HITCNTS 0x1 384 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 385 #define G_FW_FILTER_WR_HITCNTS(x) \ 386 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 387 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 388 389 #define S_FW_FILTER_WR_TXCHAN 13 390 #define M_FW_FILTER_WR_TXCHAN 0x3 391 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 392 #define G_FW_FILTER_WR_TXCHAN(x) \ 393 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 394 395 #define S_FW_FILTER_WR_PRIO 12 396 #define M_FW_FILTER_WR_PRIO 0x1 397 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 398 #define G_FW_FILTER_WR_PRIO(x) \ 399 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 400 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 401 402 #define S_FW_FILTER_WR_L2TIX 0 403 #define M_FW_FILTER_WR_L2TIX 0xfff 404 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 405 #define G_FW_FILTER_WR_L2TIX(x) \ 406 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 407 408 #define S_FW_FILTER_WR_FRAG 7 409 #define M_FW_FILTER_WR_FRAG 0x1 410 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 411 #define G_FW_FILTER_WR_FRAG(x) \ 412 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 413 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 414 415 #define S_FW_FILTER_WR_FRAGM 6 416 #define M_FW_FILTER_WR_FRAGM 0x1 417 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 418 #define G_FW_FILTER_WR_FRAGM(x) \ 419 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 420 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 421 422 #define S_FW_FILTER_WR_IVLAN_VLD 5 423 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 424 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 425 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 426 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 427 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 428 429 #define S_FW_FILTER_WR_OVLAN_VLD 4 430 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 431 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 432 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 433 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 434 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 435 436 #define S_FW_FILTER_WR_IVLAN_VLDM 3 437 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 438 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 439 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 440 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 441 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 442 443 #define S_FW_FILTER_WR_OVLAN_VLDM 2 444 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 445 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 446 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 447 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 448 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 449 450 #define S_FW_FILTER_WR_RX_CHAN 15 451 #define M_FW_FILTER_WR_RX_CHAN 0x1 452 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 453 #define G_FW_FILTER_WR_RX_CHAN(x) \ 454 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 455 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 456 457 #define S_FW_FILTER_WR_RX_RPL_IQ 0 458 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 459 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 460 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 461 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 462 463 #define S_FW_FILTER_WR_MACI 23 464 #define M_FW_FILTER_WR_MACI 0x1ff 465 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 466 #define G_FW_FILTER_WR_MACI(x) \ 467 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 468 469 #define S_FW_FILTER_WR_MACIM 14 470 #define M_FW_FILTER_WR_MACIM 0x1ff 471 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 472 #define G_FW_FILTER_WR_MACIM(x) \ 473 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 474 475 #define S_FW_FILTER_WR_FCOE 13 476 #define M_FW_FILTER_WR_FCOE 0x1 477 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 478 #define G_FW_FILTER_WR_FCOE(x) \ 479 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 480 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 481 482 #define S_FW_FILTER_WR_FCOEM 12 483 #define M_FW_FILTER_WR_FCOEM 0x1 484 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 485 #define G_FW_FILTER_WR_FCOEM(x) \ 486 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 487 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 488 489 #define S_FW_FILTER_WR_PORT 9 490 #define M_FW_FILTER_WR_PORT 0x7 491 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 492 #define G_FW_FILTER_WR_PORT(x) \ 493 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 494 495 #define S_FW_FILTER_WR_PORTM 6 496 #define M_FW_FILTER_WR_PORTM 0x7 497 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 498 #define G_FW_FILTER_WR_PORTM(x) \ 499 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 500 501 #define S_FW_FILTER_WR_MATCHTYPE 3 502 #define M_FW_FILTER_WR_MATCHTYPE 0x7 503 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 504 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 505 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 506 507 #define S_FW_FILTER_WR_MATCHTYPEM 0 508 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 509 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 510 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 511 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 512 513 struct fw_ulptx_wr { 514 __be32 op_to_compl; 515 __be32 flowid_len16; 516 __u64 cookie; 517 }; 518 519 struct fw_tp_wr { 520 __be32 op_to_immdlen; 521 __be32 flowid_len16; 522 __u64 cookie; 523 }; 524 525 struct fw_eth_tx_pkt_wr { 526 __be32 op_immdlen; 527 __be32 equiq_to_len16; 528 __be64 r3; 529 }; 530 531 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 532 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 533 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 534 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 535 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 536 537 struct fw_eth_tx_pkts_wr { 538 __be32 op_pkd; 539 __be32 equiq_to_len16; 540 __be32 r3; 541 __be16 plen; 542 __u8 npkt; 543 __u8 type; 544 }; 545 546 struct fw_eth_tx_uo_wr { 547 __be32 op_immdlen; 548 __be32 equiq_to_len16; 549 __be64 r3; 550 __be16 ethlen; 551 __be16 iplen; 552 __be16 udplen; 553 __be16 mss; 554 __be32 length; 555 __be32 r4; 556 }; 557 558 struct fw_eq_flush_wr { 559 __u8 opcode; 560 __u8 r1[3]; 561 __be32 equiq_to_len16; 562 __be64 r3; 563 }; 564 565 struct fw_ofld_connection_wr { 566 __be32 op_compl; 567 __be32 len16_pkd; 568 __u64 cookie; 569 __be64 r2; 570 __be64 r3; 571 struct fw_ofld_connection_le { 572 __be32 version_cpl; 573 __be32 filter; 574 __be32 r1; 575 __be16 lport; 576 __be16 pport; 577 union fw_ofld_connection_leip { 578 struct fw_ofld_connection_le_ipv4 { 579 __be32 pip; 580 __be32 lip; 581 __be64 r0; 582 __be64 r1; 583 __be64 r2; 584 } ipv4; 585 struct fw_ofld_connection_le_ipv6 { 586 __be64 pip_hi; 587 __be64 pip_lo; 588 __be64 lip_hi; 589 __be64 lip_lo; 590 } ipv6; 591 } u; 592 } le; 593 struct fw_ofld_connection_tcb { 594 __be32 t_state_to_astid; 595 __be16 cplrxdataack_cplpassacceptrpl; 596 __be16 rcv_adv; 597 __be32 rcv_nxt; 598 __be32 tx_max; 599 __be64 opt0; 600 __be32 opt2; 601 __be32 r1; 602 __be64 r2; 603 __be64 r3; 604 } tcb; 605 }; 606 607 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 608 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 609 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 610 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 611 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 612 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 613 M_FW_OFLD_CONNECTION_WR_VERSION) 614 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 615 616 #define S_FW_OFLD_CONNECTION_WR_CPL 30 617 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 618 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 619 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 620 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 621 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 622 623 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 624 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 625 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 626 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 627 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 628 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 629 M_FW_OFLD_CONNECTION_WR_T_STATE) 630 631 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 632 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 633 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 634 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 635 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 636 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 637 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 638 639 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 640 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 641 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 642 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 643 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 644 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 645 646 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 647 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 648 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 649 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 650 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 651 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 652 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 653 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 654 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 655 656 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 657 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 658 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 659 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 660 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 661 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 662 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 663 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 664 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 665 666 enum fw_flowc_mnem_tcpstate { 667 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 668 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 669 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 670 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 671 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 672 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 673 /* haven't gotten ACK for FIN and will resend FIN - equiv ESTAB */ 674 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, 675 /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 676 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, 677 /* haven't gotten ACK for FIN & will resend FIN but have received FIN */ 678 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, 679 /* sent FIN and got FIN + ACK, waiting for FIN */ 680 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, 681 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 682 }; 683 684 enum fw_flowc_mnem_uostate { 685 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 686 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 687 /* graceful close, after sending outstanding payload */ 688 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, 689 /* immediate close, after discarding outstanding payload */ 690 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, 691 }; 692 693 enum fw_flowc_mnem { 694 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 695 FW_FLOWC_MNEM_CH, 696 FW_FLOWC_MNEM_PORT, 697 FW_FLOWC_MNEM_IQID, 698 FW_FLOWC_MNEM_SNDNXT, 699 FW_FLOWC_MNEM_RCVNXT, 700 FW_FLOWC_MNEM_SNDBUF, 701 FW_FLOWC_MNEM_MSS, 702 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 703 FW_FLOWC_MNEM_TCPSTATE, 704 FW_FLOWC_MNEM_UOSTATE, 705 FW_FLOWC_MNEM_SCHEDCLASS, 706 }; 707 708 struct fw_flowc_mnemval { 709 __u8 mnemonic; 710 __u8 r4[3]; 711 __be32 val; 712 }; 713 714 struct fw_flowc_wr { 715 __be32 op_to_nparams; 716 __be32 flowid_len16; 717 #ifndef C99_NOT_SUPPORTED 718 struct fw_flowc_mnemval mnemval[]; 719 #endif 720 }; 721 722 #define S_FW_FLOWC_WR_NPARAMS 0 723 #define M_FW_FLOWC_WR_NPARAMS 0xff 724 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 725 #define G_FW_FLOWC_WR_NPARAMS(x) \ 726 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 727 728 struct fw_ofld_tx_data_wr { 729 __be32 op_to_immdlen; 730 __be32 flowid_len16; 731 __be32 plen; 732 __be32 tunnel_to_proxy; 733 }; 734 735 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 736 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 737 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 738 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 739 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 740 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 741 742 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 743 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 744 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 745 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 746 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 747 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 748 749 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 750 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 751 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 752 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 753 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 754 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 755 756 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 757 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 758 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 759 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 760 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 761 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 762 763 #define S_FW_OFLD_TX_DATA_WR_MORE 15 764 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 765 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 766 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 767 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 768 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 769 770 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 771 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 772 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 773 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 774 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 775 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 776 777 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 778 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 779 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 780 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 781 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 782 783 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 784 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 785 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 786 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 787 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 788 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 789 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 790 791 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 792 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 793 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 794 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 795 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 796 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 797 798 struct fw_cmd_wr { 799 __be32 op_dma; 800 __be32 len16_pkd; 801 __be64 cookie_daddr; 802 }; 803 804 #define S_FW_CMD_WR_DMA 17 805 #define M_FW_CMD_WR_DMA 0x1 806 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 807 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 808 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 809 810 struct fw_eth_tx_pkt_vm_wr { 811 __be32 op_immdlen; 812 __be32 equiq_to_len16; 813 __be32 r3[2]; 814 __u8 ethmacdst[6]; 815 __u8 ethmacsrc[6]; 816 __be16 ethtype; 817 __be16 vlantci; 818 }; 819 820 /* 821 * ************************************ 822 * R I W O R K R E Q U E S T s 823 * ************************************ 824 */ 825 826 enum fw_ri_wr_opcode { 827 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 828 FW_RI_READ_REQ = 0x1, 829 FW_RI_READ_RESP = 0x2, 830 FW_RI_SEND = 0x3, 831 FW_RI_SEND_WITH_INV = 0x4, 832 FW_RI_SEND_WITH_SE = 0x5, 833 FW_RI_SEND_WITH_SE_INV = 0x6, 834 FW_RI_TERMINATE = 0x7, 835 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 836 FW_RI_BIND_MW = 0x9, 837 FW_RI_FAST_REGISTER = 0xa, 838 FW_RI_LOCAL_INV = 0xb, 839 FW_RI_QP_MODIFY = 0xc, 840 FW_RI_BYPASS = 0xd, 841 FW_RI_RECEIVE = 0xe, 842 FW_RI_SGE_EC_CR_RETURN = 0xf 843 844 }; 845 846 enum fw_ri_wr_flags { 847 FW_RI_COMPLETION_FLAG = 0x01, 848 FW_RI_NOTIFICATION_FLAG = 0x02, 849 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 850 FW_RI_READ_FENCE_FLAG = 0x08, 851 FW_RI_LOCAL_FENCE_FLAG = 0x10, 852 FW_RI_RDMA_READ_INVALIDATE = 0x20 853 }; 854 855 enum fw_ri_mpa_attrs { 856 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 857 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 858 FW_RI_MPA_CRC_ENABLE = 0x04, 859 FW_RI_MPA_IETF_ENABLE = 0x08 860 }; 861 862 enum fw_ri_qp_caps { 863 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 864 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 865 FW_RI_QP_BIND_ENABLE = 0x04, 866 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 867 FW_RI_QP_STAG0_ENABLE = 0x10, 868 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE = 0x80, 869 }; 870 871 enum fw_ri_addr_type { 872 FW_RI_ZERO_BASED_TO = 0x00, 873 FW_RI_VA_BASED_TO = 0x01 874 }; 875 876 enum fw_ri_mem_perms { 877 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 878 FW_RI_MEM_ACCESS_REM_READ = 0x02, 879 FW_RI_MEM_ACCESS_REM = 0x03, 880 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 881 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 882 FW_RI_MEM_ACCESS_LOCAL = 0x0C 883 }; 884 885 enum fw_ri_stag_type { 886 FW_RI_STAG_NSMR = 0x00, 887 FW_RI_STAG_SMR = 0x01, 888 FW_RI_STAG_MW = 0x02, 889 FW_RI_STAG_MW_RELAXED = 0x03 890 }; 891 892 enum fw_ri_data_op { 893 FW_RI_DATA_IMMD = 0x81, 894 FW_RI_DATA_DSGL = 0x82, 895 FW_RI_DATA_ISGL = 0x83 896 }; 897 898 enum fw_ri_sgl_depth { 899 FW_RI_SGL_DEPTH_MAX_SQ = 16, 900 FW_RI_SGL_DEPTH_MAX_RQ = 4 901 }; 902 903 enum fw_ri_cqe_err { 904 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 905 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 906 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 907 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 908 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 909 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 910 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 911 /* attempt to invalidate a SMR */ 912 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, 913 /* attempt to invalidate a MR w MW */ 914 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, 915 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 916 /* ECC error detected when reading the PSTAG for a MW Invalidate */ 917 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, 918 /* pbl address out of bound : software error */ 919 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, 920 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 921 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 922 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 923 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 924 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 925 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 926 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 927 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 928 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 929 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 930 /* MO not zero for TERMINATE or READ_REQ */ 931 FW_RI_CQE_ERR_MO = 0x1A, 932 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 933 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 934 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 935 /* RQE address out of bound : software error */ 936 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, 937 /* internel error (opcode mismatch) */ 938 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F 939 940 }; 941 942 struct fw_ri_dsge_pair { 943 __be32 len[2]; 944 __be64 addr[2]; 945 }; 946 947 struct fw_ri_dsgl { 948 __u8 op; 949 __u8 r1; 950 __be16 nsge; 951 __be32 len0; 952 __be64 addr0; 953 #ifndef C99_NOT_SUPPORTED 954 struct fw_ri_dsge_pair sge[]; 955 #endif 956 }; 957 958 struct fw_ri_sge { 959 __be32 stag; 960 __be32 len; 961 __be64 to; 962 }; 963 964 struct fw_ri_isgl { 965 __u8 op; 966 __u8 r1; 967 __be16 nsge; 968 __be32 r2; 969 #ifndef C99_NOT_SUPPORTED 970 struct fw_ri_sge sge[]; 971 #endif 972 }; 973 974 struct fw_ri_immd { 975 __u8 op; 976 __u8 r1; 977 __be16 r2; 978 __be32 immdlen; 979 #ifndef C99_NOT_SUPPORTED 980 __u8 data[]; 981 #endif 982 }; 983 984 struct fw_ri_tpte { 985 __be32 valid_to_pdid; 986 __be32 locread_to_qpid; 987 __be32 nosnoop_pbladdr; 988 __be32 len_lo; 989 __be32 va_hi; 990 __be32 va_lo_fbo; 991 __be32 dca_mwbcnt_pstag; 992 __be32 len_hi; 993 }; 994 995 #define S_FW_RI_TPTE_VALID 31 996 #define M_FW_RI_TPTE_VALID 0x1 997 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 998 #define G_FW_RI_TPTE_VALID(x) \ 999 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1000 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1001 1002 #define S_FW_RI_TPTE_STAGKEY 23 1003 #define M_FW_RI_TPTE_STAGKEY 0xff 1004 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1005 #define G_FW_RI_TPTE_STAGKEY(x) \ 1006 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1007 1008 #define S_FW_RI_TPTE_STAGSTATE 22 1009 #define M_FW_RI_TPTE_STAGSTATE 0x1 1010 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1011 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1012 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1013 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1014 1015 #define S_FW_RI_TPTE_STAGTYPE 20 1016 #define M_FW_RI_TPTE_STAGTYPE 0x3 1017 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1018 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1019 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1020 1021 #define S_FW_RI_TPTE_PDID 0 1022 #define M_FW_RI_TPTE_PDID 0xfffff 1023 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1024 #define G_FW_RI_TPTE_PDID(x) \ 1025 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1026 1027 #define S_FW_RI_TPTE_PERM 28 1028 #define M_FW_RI_TPTE_PERM 0xf 1029 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1030 #define G_FW_RI_TPTE_PERM(x) \ 1031 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1032 1033 #define S_FW_RI_TPTE_REMINVDIS 27 1034 #define M_FW_RI_TPTE_REMINVDIS 0x1 1035 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1036 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1037 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1038 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1039 1040 #define S_FW_RI_TPTE_ADDRTYPE 26 1041 #define M_FW_RI_TPTE_ADDRTYPE 1 1042 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1043 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1044 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1045 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1046 1047 #define S_FW_RI_TPTE_MWBINDEN 25 1048 #define M_FW_RI_TPTE_MWBINDEN 0x1 1049 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1050 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1051 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1052 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1053 1054 #define S_FW_RI_TPTE_PS 20 1055 #define M_FW_RI_TPTE_PS 0x1f 1056 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1057 #define G_FW_RI_TPTE_PS(x) \ 1058 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1059 1060 #define S_FW_RI_TPTE_QPID 0 1061 #define M_FW_RI_TPTE_QPID 0xfffff 1062 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1063 #define G_FW_RI_TPTE_QPID(x) \ 1064 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1065 1066 #define S_FW_RI_TPTE_NOSNOOP 31 1067 #define M_FW_RI_TPTE_NOSNOOP 0x1 1068 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1069 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1070 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1071 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1072 1073 #define S_FW_RI_TPTE_PBLADDR 0 1074 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1075 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1076 #define G_FW_RI_TPTE_PBLADDR(x) \ 1077 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1078 1079 #define S_FW_RI_TPTE_DCA 24 1080 #define M_FW_RI_TPTE_DCA 0x1f 1081 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1082 #define G_FW_RI_TPTE_DCA(x) \ 1083 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1084 1085 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1086 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1087 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1088 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1089 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1090 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1091 1092 enum fw_ri_cqe_rxtx { 1093 FW_RI_CQE_RXTX_RX = 0x0, 1094 FW_RI_CQE_RXTX_TX = 0x1, 1095 }; 1096 1097 struct fw_ri_cqe { 1098 union fw_ri_rxtx { 1099 struct fw_ri_scqe { 1100 __be32 qpid_n_stat_rxtx_type; 1101 __be32 plen; 1102 __be32 reserved; 1103 __be32 wrid; 1104 } scqe; 1105 struct fw_ri_rcqe { 1106 __be32 qpid_n_stat_rxtx_type; 1107 __be32 plen; 1108 __be32 stag; 1109 __be32 msn; 1110 } rcqe; 1111 } u; 1112 }; 1113 1114 #define S_FW_RI_CQE_QPID 12 1115 #define M_FW_RI_CQE_QPID 0xfffff 1116 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1117 #define G_FW_RI_CQE_QPID(x) \ 1118 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1119 1120 #define S_FW_RI_CQE_NOTIFY 10 1121 #define M_FW_RI_CQE_NOTIFY 0x1 1122 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1123 #define G_FW_RI_CQE_NOTIFY(x) \ 1124 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1125 1126 #define S_FW_RI_CQE_STATUS 5 1127 #define M_FW_RI_CQE_STATUS 0x1f 1128 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1129 #define G_FW_RI_CQE_STATUS(x) \ 1130 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1131 1132 #define S_FW_RI_CQE_RXTX 4 1133 #define M_FW_RI_CQE_RXTX 0x1 1134 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1135 #define G_FW_RI_CQE_RXTX(x) \ 1136 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1137 1138 #define S_FW_RI_CQE_TYPE 0 1139 #define M_FW_RI_CQE_TYPE 0xf 1140 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1141 #define G_FW_RI_CQE_TYPE(x) \ 1142 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1143 1144 enum fw_ri_res_type { 1145 FW_RI_RES_TYPE_SQ, 1146 FW_RI_RES_TYPE_RQ, 1147 FW_RI_RES_TYPE_CQ, 1148 }; 1149 1150 enum fw_ri_res_op { 1151 FW_RI_RES_OP_WRITE, 1152 FW_RI_RES_OP_RESET, 1153 }; 1154 1155 struct fw_ri_res { 1156 union fw_ri_restype { 1157 struct fw_ri_res_sqrq { 1158 __u8 restype; 1159 __u8 op; 1160 __be16 r3; 1161 __be32 eqid; 1162 __be32 r4[2]; 1163 __be32 fetchszm_to_iqid; 1164 __be32 dcaen_to_eqsize; 1165 __be64 eqaddr; 1166 } sqrq; 1167 struct fw_ri_res_cq { 1168 __u8 restype; 1169 __u8 op; 1170 __be16 r3; 1171 __be32 iqid; 1172 __be32 r4[2]; 1173 __be32 iqandst_to_iqandstindex; 1174 __be16 iqdroprss_to_iqesize; 1175 __be16 iqsize; 1176 __be64 iqaddr; 1177 __be32 iqns_iqro; 1178 __be32 r6_lo; 1179 __be64 r7; 1180 } cq; 1181 } u; 1182 }; 1183 1184 struct fw_ri_res_wr { 1185 __be32 op_nres; 1186 __be32 len16_pkd; 1187 __u64 cookie; 1188 #ifndef C99_NOT_SUPPORTED 1189 struct fw_ri_res res[]; 1190 #endif 1191 }; 1192 1193 #define S_FW_RI_RES_WR_NRES 0 1194 #define M_FW_RI_RES_WR_NRES 0xff 1195 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1196 #define G_FW_RI_RES_WR_NRES(x) \ 1197 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1198 1199 #define S_FW_RI_RES_WR_FETCHSZM 26 1200 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1201 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1202 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1203 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1204 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1205 1206 #define S_FW_RI_RES_WR_STATUSPGNS 25 1207 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1208 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1209 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1210 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1211 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1212 1213 #define S_FW_RI_RES_WR_STATUSPGRO 24 1214 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1215 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1216 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1217 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1218 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1219 1220 #define S_FW_RI_RES_WR_FETCHNS 23 1221 #define M_FW_RI_RES_WR_FETCHNS 0x1 1222 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1223 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1224 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1225 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1226 1227 #define S_FW_RI_RES_WR_FETCHRO 22 1228 #define M_FW_RI_RES_WR_FETCHRO 0x1 1229 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1230 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1231 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1232 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1233 1234 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1235 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1236 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1237 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1238 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1239 1240 #define S_FW_RI_RES_WR_CPRIO 19 1241 #define M_FW_RI_RES_WR_CPRIO 0x1 1242 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1243 #define G_FW_RI_RES_WR_CPRIO(x) \ 1244 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1245 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1246 1247 #define S_FW_RI_RES_WR_ONCHIP 18 1248 #define M_FW_RI_RES_WR_ONCHIP 0x1 1249 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1250 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1251 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1252 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1253 1254 #define S_FW_RI_RES_WR_PCIECHN 16 1255 #define M_FW_RI_RES_WR_PCIECHN 0x3 1256 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1257 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1258 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1259 1260 #define S_FW_RI_RES_WR_IQID 0 1261 #define M_FW_RI_RES_WR_IQID 0xffff 1262 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1263 #define G_FW_RI_RES_WR_IQID(x) \ 1264 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1265 1266 #define S_FW_RI_RES_WR_DCAEN 31 1267 #define M_FW_RI_RES_WR_DCAEN 0x1 1268 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1269 #define G_FW_RI_RES_WR_DCAEN(x) \ 1270 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1271 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1272 1273 #define S_FW_RI_RES_WR_DCACPU 26 1274 #define M_FW_RI_RES_WR_DCACPU 0x1f 1275 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1276 #define G_FW_RI_RES_WR_DCACPU(x) \ 1277 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1278 1279 #define S_FW_RI_RES_WR_FBMIN 23 1280 #define M_FW_RI_RES_WR_FBMIN 0x7 1281 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1282 #define G_FW_RI_RES_WR_FBMIN(x) \ 1283 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1284 1285 #define S_FW_RI_RES_WR_FBMAX 20 1286 #define M_FW_RI_RES_WR_FBMAX 0x7 1287 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1288 #define G_FW_RI_RES_WR_FBMAX(x) \ 1289 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1290 1291 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1292 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1293 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1294 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1295 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1296 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1297 1298 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1299 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1300 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1301 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1302 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1303 1304 #define S_FW_RI_RES_WR_EQSIZE 0 1305 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1306 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1307 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1308 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1309 1310 #define S_FW_RI_RES_WR_IQANDST 15 1311 #define M_FW_RI_RES_WR_IQANDST 0x1 1312 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1313 #define G_FW_RI_RES_WR_IQANDST(x) \ 1314 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1315 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1316 1317 #define S_FW_RI_RES_WR_IQANUS 14 1318 #define M_FW_RI_RES_WR_IQANUS 0x1 1319 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1320 #define G_FW_RI_RES_WR_IQANUS(x) \ 1321 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1322 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1323 1324 #define S_FW_RI_RES_WR_IQANUD 12 1325 #define M_FW_RI_RES_WR_IQANUD 0x3 1326 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1327 #define G_FW_RI_RES_WR_IQANUD(x) \ 1328 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1329 1330 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1331 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1332 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1333 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1334 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1335 1336 #define S_FW_RI_RES_WR_IQDROPRSS 15 1337 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1338 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1339 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1340 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1341 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1342 1343 #define S_FW_RI_RES_WR_IQGTSMODE 14 1344 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1345 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1346 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1347 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1348 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1349 1350 #define S_FW_RI_RES_WR_IQPCIECH 12 1351 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1352 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1353 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1354 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1355 1356 #define S_FW_RI_RES_WR_IQDCAEN 11 1357 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1358 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1359 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1360 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1361 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1362 1363 #define S_FW_RI_RES_WR_IQDCACPU 6 1364 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1365 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1366 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1367 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1368 1369 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1370 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1371 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1372 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1373 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1374 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1375 1376 #define S_FW_RI_RES_WR_IQO 3 1377 #define M_FW_RI_RES_WR_IQO 0x1 1378 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1379 #define G_FW_RI_RES_WR_IQO(x) \ 1380 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1381 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1382 1383 #define S_FW_RI_RES_WR_IQCPRIO 2 1384 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1385 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1386 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1387 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1388 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1389 1390 #define S_FW_RI_RES_WR_IQESIZE 0 1391 #define M_FW_RI_RES_WR_IQESIZE 0x3 1392 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1393 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1394 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1395 1396 #define S_FW_RI_RES_WR_IQNS 31 1397 #define M_FW_RI_RES_WR_IQNS 0x1 1398 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1399 #define G_FW_RI_RES_WR_IQNS(x) \ 1400 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1401 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1402 1403 #define S_FW_RI_RES_WR_IQRO 30 1404 #define M_FW_RI_RES_WR_IQRO 0x1 1405 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1406 #define G_FW_RI_RES_WR_IQRO(x) \ 1407 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1408 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1409 1410 struct fw_ri_rdma_write_wr { 1411 __u8 opcode; 1412 __u8 flags; 1413 __u16 wrid; 1414 __u8 r1[3]; 1415 __u8 len16; 1416 __be64 r2; 1417 __be32 plen; 1418 __be32 stag_sink; 1419 __be64 to_sink; 1420 }; 1421 1422 struct fw_ri_send_wr { 1423 __u8 opcode; 1424 __u8 flags; 1425 __u16 wrid; 1426 __u8 r1[3]; 1427 __u8 len16; 1428 __be32 sendop_pkd; 1429 __be32 stag_inv; 1430 __be32 plen; 1431 __be32 r3; 1432 __be64 r4; 1433 }; 1434 1435 #define S_FW_RI_SEND_WR_SENDOP 0 1436 #define M_FW_RI_SEND_WR_SENDOP 0xf 1437 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1438 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1439 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1440 1441 struct fw_ri_rdma_read_wr { 1442 __u8 opcode; 1443 __u8 flags; 1444 __u16 wrid; 1445 __u8 r1[3]; 1446 __u8 len16; 1447 __be64 r2; 1448 __be32 stag_sink; 1449 __be32 to_sink_hi; 1450 __be32 to_sink_lo; 1451 __be32 plen; 1452 __be32 stag_src; 1453 __be32 to_src_hi; 1454 __be32 to_src_lo; 1455 __be32 r5; 1456 }; 1457 1458 struct fw_ri_recv_wr { 1459 __u8 opcode; 1460 __u8 r1; 1461 __u16 wrid; 1462 __u8 r2[3]; 1463 __u8 len16; 1464 }; 1465 1466 struct fw_ri_bind_mw_wr { 1467 __u8 opcode; 1468 __u8 flags; 1469 __u16 wrid; 1470 __u8 r1[3]; 1471 __u8 len16; 1472 __u8 qpbinde_to_dcacpu; 1473 __u8 pgsz_shift; 1474 __u8 addr_type; 1475 __u8 mem_perms; 1476 __be32 stag_mr; 1477 __be32 stag_mw; 1478 __be32 r3; 1479 __be64 len_mw; 1480 __be64 va_fbo; 1481 __be64 r4; 1482 }; 1483 1484 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1485 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1486 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1487 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1488 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1489 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1490 1491 #define S_FW_RI_BIND_MW_WR_NS 5 1492 #define M_FW_RI_BIND_MW_WR_NS 0x1 1493 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1494 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1495 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1496 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1497 1498 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1499 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1500 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1501 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1502 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1503 1504 struct fw_ri_fr_nsmr_wr { 1505 __u8 opcode; 1506 __u8 flags; 1507 __u16 wrid; 1508 __u8 r1[3]; 1509 __u8 len16; 1510 __u8 qpbinde_to_dcacpu; 1511 __u8 pgsz_shift; 1512 __u8 addr_type; 1513 __u8 mem_perms; 1514 __be32 stag; 1515 __be32 len_hi; 1516 __be32 len_lo; 1517 __be32 va_hi; 1518 __be32 va_lo_fbo; 1519 }; 1520 1521 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1522 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1523 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1524 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1525 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1526 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1527 1528 #define S_FW_RI_FR_NSMR_WR_NS 5 1529 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1530 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1531 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1532 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1533 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1534 1535 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1536 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1537 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1538 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1539 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1540 1541 struct fw_ri_inv_lstag_wr { 1542 __u8 opcode; 1543 __u8 flags; 1544 __u16 wrid; 1545 __u8 r1[3]; 1546 __u8 len16; 1547 __be32 r2; 1548 __be32 stag_inv; 1549 }; 1550 1551 struct fw_ri_send_immediate_wr { 1552 __u8 opcode; 1553 __u8 flags; 1554 __u16 wrid; 1555 __u8 r1[3]; 1556 __u8 len16; 1557 __be32 sendimmop_pkd; 1558 __be32 r3; 1559 __be32 plen; 1560 __be32 r4; 1561 __be64 r5; 1562 }; 1563 1564 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1565 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1566 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1567 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1568 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1569 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1570 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1571 1572 enum fw_ri_atomic_op { 1573 FW_RI_ATOMIC_OP_FETCHADD, 1574 FW_RI_ATOMIC_OP_SWAP, 1575 FW_RI_ATOMIC_OP_CMDSWAP, 1576 }; 1577 1578 struct fw_ri_atomic_wr { 1579 __u8 opcode; 1580 __u8 flags; 1581 __u16 wrid; 1582 __u8 r1[3]; 1583 __u8 len16; 1584 __be32 atomicop_pkd; 1585 __be64 r3; 1586 __be32 aopcode_pkd; 1587 __be32 reqid; 1588 __be32 stag; 1589 __be32 to_hi; 1590 __be32 to_lo; 1591 __be32 addswap_data_hi; 1592 __be32 addswap_data_lo; 1593 __be32 addswap_mask_hi; 1594 __be32 addswap_mask_lo; 1595 __be32 compare_data_hi; 1596 __be32 compare_data_lo; 1597 __be32 compare_mask_hi; 1598 __be32 compare_mask_lo; 1599 __be32 r5; 1600 }; 1601 1602 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1603 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1604 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1605 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1606 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1607 1608 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1609 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1610 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1611 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1612 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1613 1614 enum fw_ri_type { 1615 FW_RI_TYPE_INIT, 1616 FW_RI_TYPE_FINI, 1617 FW_RI_TYPE_TERMINATE 1618 }; 1619 1620 enum fw_ri_init_p2ptype { 1621 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1622 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1623 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1624 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1625 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1626 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1627 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1628 }; 1629 1630 struct fw_ri_wr { 1631 __be32 op_compl; 1632 __be32 flowid_len16; 1633 __u64 cookie; 1634 union fw_ri { 1635 struct fw_ri_init { 1636 __u8 type; 1637 __u8 mpareqbit_p2ptype; 1638 __u8 r4[2]; 1639 __u8 mpa_attrs; 1640 __u8 qp_caps; 1641 __be16 nrqe; 1642 __be32 pdid; 1643 __be32 qpid; 1644 __be32 sq_eqid; 1645 __be32 rq_eqid; 1646 __be32 scqid; 1647 __be32 rcqid; 1648 __be32 ord_max; 1649 __be32 ird_max; 1650 __be32 iss; 1651 __be32 irs; 1652 __be32 hwrqsize; 1653 __be32 hwrqaddr; 1654 __be64 r5; 1655 union fw_ri_init_p2p { 1656 struct fw_ri_rdma_write_wr write; 1657 struct fw_ri_rdma_read_wr read; 1658 struct fw_ri_send_wr send; 1659 } u; 1660 } init; 1661 struct fw_ri_fini { 1662 __u8 type; 1663 __u8 r3[7]; 1664 __be64 r4; 1665 } fini; 1666 struct fw_ri_terminate { 1667 __u8 type; 1668 __u8 r3[3]; 1669 __be32 immdlen; 1670 __u8 termmsg[40]; 1671 } terminate; 1672 } u; 1673 }; 1674 1675 #define S_FW_RI_WR_MPAREQBIT 7 1676 #define M_FW_RI_WR_MPAREQBIT 0x1 1677 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1678 #define G_FW_RI_WR_MPAREQBIT(x) \ 1679 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1680 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1681 1682 #define S_FW_RI_WR_0BRRBIT 6 1683 #define M_FW_RI_WR_0BRRBIT 0x1 1684 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1685 #define G_FW_RI_WR_0BRRBIT(x) \ 1686 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1687 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1688 1689 #define S_FW_RI_WR_P2PTYPE 0 1690 #define M_FW_RI_WR_P2PTYPE 0xf 1691 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1692 #define G_FW_RI_WR_P2PTYPE(x) \ 1693 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1694 1695 /* 1696 * ******************************************* 1697 * F O i S C S I W O R K R E Q U E S T s 1698 * ******************************************* 1699 */ 1700 1701 #define FW_FOISCSI_NAME_MAX_LEN 224 1702 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1703 #define FW_FOISCSI_MAX_CHAP_NAME_LEN 64 1704 #define FW_FOISCSI_INIT_NODE_MAX 8 1705 1706 enum fw_chnet_ifconf_wr_subop { 1707 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1708 1709 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1710 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1711 1712 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1713 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1714 1715 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1716 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1717 1718 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1719 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1720 1721 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1722 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1723 1724 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1725 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1726 1727 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1728 }; 1729 1730 struct fw_chnet_ifconf_wr { 1731 __be32 op_compl; 1732 __be32 flowid_len16; 1733 __be64 cookie; 1734 __be32 if_flowid; 1735 __u8 idx; 1736 __u8 subop; 1737 __u8 retval; 1738 __u8 r2; 1739 __be64 r3; 1740 struct fw_chnet_ifconf_params { 1741 __be32 r0; 1742 __be16 vlanid; 1743 __be16 mtu; 1744 union fw_chnet_ifconf_addr_type { 1745 struct fw_chnet_ifconf_ipv4 { 1746 __be32 addr; 1747 __be32 mask; 1748 __be32 router; 1749 __be32 r0; 1750 __be64 r1; 1751 } ipv4; 1752 struct fw_chnet_ifconf_ipv6 { 1753 __be64 linklocal_lo; 1754 __be64 linklocal_hi; 1755 __be64 router_hi; 1756 __be64 router_lo; 1757 __be64 aconf_hi; 1758 __be64 aconf_lo; 1759 __be64 linklocal_aconf_hi; 1760 __be64 linklocal_aconf_lo; 1761 __be64 router_aconf_hi; 1762 __be64 router_aconf_lo; 1763 __be64 r0; 1764 } ipv6; 1765 } in_attr; 1766 } param; 1767 }; 1768 1769 enum fw_foiscsi_session_type { 1770 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1771 FW_FOISCSI_SESSION_TYPE_NORMAL, 1772 }; 1773 1774 enum fw_foiscsi_auth_policy { 1775 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1776 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1777 }; 1778 1779 enum fw_foiscsi_auth_method { 1780 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1781 FW_FOISCSI_AUTH_METHOD_CHAP, 1782 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1783 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1784 }; 1785 1786 enum fw_foiscsi_digest_type { 1787 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1788 FW_FOISCSI_DIGEST_TYPE_CRC32, 1789 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1790 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1791 }; 1792 1793 enum fw_foiscsi_wr_subop { 1794 FW_FOISCSI_WR_SUBOP_ADD = 1, 1795 FW_FOISCSI_WR_SUBOP_DEL = 2, 1796 FW_FOISCSI_WR_SUBOP_MOD = 4, 1797 }; 1798 1799 enum fw_foiscsi_ctrl_state { 1800 FW_FOISCSI_CTRL_STATE_FREE = 0, 1801 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1802 FW_FOISCSI_CTRL_STATE_FAILED, 1803 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1804 FW_FOISCSI_CTRL_STATE_REDIRECT, 1805 }; 1806 1807 struct fw_rdev_wr { 1808 __be32 op_to_immdlen; 1809 __be32 alloc_to_len16; 1810 __be64 cookie; 1811 __u8 protocol; 1812 __u8 event_cause; 1813 __u8 cur_state; 1814 __u8 prev_state; 1815 __be32 flags_to_assoc_flowid; 1816 union rdev_entry { 1817 struct fcoe_rdev_entry { 1818 __be32 flowid; 1819 __u8 protocol; 1820 __u8 event_cause; 1821 __u8 flags; 1822 __u8 rjt_reason; 1823 __u8 cur_login_st; 1824 __u8 prev_login_st; 1825 __be16 rcv_fr_sz; 1826 __u8 rd_xfer_rdy_to_rport_type; 1827 __u8 vft_to_qos; 1828 __u8 org_proc_assoc_to_acc_rsp_code; 1829 __u8 enh_disc_to_tgt; 1830 __u8 wwnn[8]; 1831 __u8 wwpn[8]; 1832 __be16 iqid; 1833 __u8 fc_oui[3]; 1834 __u8 r_id[3]; 1835 } fcoe_rdev; 1836 struct iscsi_rdev_entry { 1837 __be32 flowid; 1838 __u8 protocol; 1839 __u8 event_cause; 1840 __u8 flags; 1841 __u8 r3; 1842 __be16 iscsi_opts; 1843 __be16 tcp_opts; 1844 __be16 ip_opts; 1845 __be16 max_rcv_len; 1846 __be16 max_snd_len; 1847 __be16 first_brst_len; 1848 __be16 max_brst_len; 1849 __be16 r4; 1850 __be16 def_time2wait; 1851 __be16 def_time2ret; 1852 __be16 nop_out_intrvl; 1853 __be16 non_scsi_to; 1854 __be16 isid; 1855 __be16 tsid; 1856 __be16 port; 1857 __be16 tpgt; 1858 __u8 r5[6]; 1859 __be16 iqid; 1860 } iscsi_rdev; 1861 } u; 1862 }; 1863 1864 #define S_FW_RDEV_WR_IMMDLEN 0 1865 #define M_FW_RDEV_WR_IMMDLEN 0xff 1866 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1867 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1868 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1869 1870 #define S_FW_RDEV_WR_ALLOC 31 1871 #define M_FW_RDEV_WR_ALLOC 0x1 1872 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1873 #define G_FW_RDEV_WR_ALLOC(x) \ 1874 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1875 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1876 1877 #define S_FW_RDEV_WR_FREE 30 1878 #define M_FW_RDEV_WR_FREE 0x1 1879 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1880 #define G_FW_RDEV_WR_FREE(x) \ 1881 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1882 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1883 1884 #define S_FW_RDEV_WR_MODIFY 29 1885 #define M_FW_RDEV_WR_MODIFY 0x1 1886 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1887 #define G_FW_RDEV_WR_MODIFY(x) \ 1888 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1889 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1890 1891 #define S_FW_RDEV_WR_FLOWID 8 1892 #define M_FW_RDEV_WR_FLOWID 0xfffff 1893 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1894 #define G_FW_RDEV_WR_FLOWID(x) \ 1895 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1896 1897 #define S_FW_RDEV_WR_LEN16 0 1898 #define M_FW_RDEV_WR_LEN16 0xff 1899 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1900 #define G_FW_RDEV_WR_LEN16(x) \ 1901 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1902 1903 #define S_FW_RDEV_WR_FLAGS 24 1904 #define M_FW_RDEV_WR_FLAGS 0xff 1905 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1906 #define G_FW_RDEV_WR_FLAGS(x) \ 1907 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1908 1909 #define S_FW_RDEV_WR_GET_NEXT 20 1910 #define M_FW_RDEV_WR_GET_NEXT 0xf 1911 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1912 #define G_FW_RDEV_WR_GET_NEXT(x) \ 1913 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1914 1915 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 1916 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1917 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1918 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1919 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1920 1921 #define S_FW_RDEV_WR_RJT 7 1922 #define M_FW_RDEV_WR_RJT 0x1 1923 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1924 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1925 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1926 1927 #define S_FW_RDEV_WR_REASON 0 1928 #define M_FW_RDEV_WR_REASON 0x7f 1929 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1930 #define G_FW_RDEV_WR_REASON(x) \ 1931 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1932 1933 #define S_FW_RDEV_WR_RD_XFER_RDY 7 1934 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1935 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 1936 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 1937 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 1938 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 1939 1940 #define S_FW_RDEV_WR_WR_XFER_RDY 6 1941 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 1942 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 1943 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 1944 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 1945 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 1946 1947 #define S_FW_RDEV_WR_FC_SP 5 1948 #define M_FW_RDEV_WR_FC_SP 0x1 1949 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 1950 #define G_FW_RDEV_WR_FC_SP(x) \ 1951 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 1952 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 1953 1954 #define S_FW_RDEV_WR_RPORT_TYPE 0 1955 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 1956 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 1957 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 1958 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 1959 1960 #define S_FW_RDEV_WR_VFT 7 1961 #define M_FW_RDEV_WR_VFT 0x1 1962 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 1963 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 1964 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 1965 1966 #define S_FW_RDEV_WR_NPIV 6 1967 #define M_FW_RDEV_WR_NPIV 0x1 1968 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 1969 #define G_FW_RDEV_WR_NPIV(x) \ 1970 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 1971 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 1972 1973 #define S_FW_RDEV_WR_CLASS 4 1974 #define M_FW_RDEV_WR_CLASS 0x3 1975 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 1976 #define G_FW_RDEV_WR_CLASS(x) \ 1977 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 1978 1979 #define S_FW_RDEV_WR_SEQ_DEL 3 1980 #define M_FW_RDEV_WR_SEQ_DEL 0x1 1981 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 1982 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 1983 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 1984 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 1985 1986 #define S_FW_RDEV_WR_PRIO_PREEMP 2 1987 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 1988 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 1989 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 1990 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 1991 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 1992 1993 #define S_FW_RDEV_WR_PREF 1 1994 #define M_FW_RDEV_WR_PREF 0x1 1995 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 1996 #define G_FW_RDEV_WR_PREF(x) \ 1997 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 1998 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 1999 2000 #define S_FW_RDEV_WR_QOS 0 2001 #define M_FW_RDEV_WR_QOS 0x1 2002 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2003 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2004 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2005 2006 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2007 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2008 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2009 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2010 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2011 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2012 2013 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2014 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2015 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2016 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2017 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2018 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2019 2020 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2021 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2022 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2023 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2024 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2025 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2026 2027 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2028 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2029 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2030 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2031 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2032 2033 #define S_FW_RDEV_WR_ENH_DISC 7 2034 #define M_FW_RDEV_WR_ENH_DISC 0x1 2035 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2036 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2037 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2038 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2039 2040 #define S_FW_RDEV_WR_REC 6 2041 #define M_FW_RDEV_WR_REC 0x1 2042 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2043 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2044 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2045 2046 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2047 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2048 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2049 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2050 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2051 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2052 2053 #define S_FW_RDEV_WR_RETRY 4 2054 #define M_FW_RDEV_WR_RETRY 0x1 2055 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2056 #define G_FW_RDEV_WR_RETRY(x) \ 2057 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2058 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2059 2060 #define S_FW_RDEV_WR_CONF_CMPL 3 2061 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2062 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2063 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2064 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2065 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2066 2067 #define S_FW_RDEV_WR_DATA_OVLY 2 2068 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2069 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2070 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2071 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2072 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2073 2074 #define S_FW_RDEV_WR_INI 1 2075 #define M_FW_RDEV_WR_INI 0x1 2076 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2077 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2078 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2079 2080 #define S_FW_RDEV_WR_TGT 0 2081 #define M_FW_RDEV_WR_TGT 0x1 2082 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2083 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2084 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2085 2086 struct fw_foiscsi_node_wr { 2087 __be32 op_to_immdlen; 2088 __be32 flowid_len16; 2089 __u64 cookie; 2090 __u8 subop; 2091 __u8 status; 2092 __u8 alias_len; 2093 __u8 iqn_len; 2094 __be32 node_flowid; 2095 __be16 nodeid; 2096 __be16 login_retry; 2097 __be16 retry_timeout; 2098 __be16 r3; 2099 __u8 iqn[224]; 2100 __u8 alias[224]; 2101 }; 2102 2103 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2104 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2105 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2106 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2107 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2108 2109 struct fw_foiscsi_ctrl_wr { 2110 __be32 op_compl; 2111 __be32 flowid_len16; 2112 __u64 cookie; 2113 __u8 subop; 2114 __u8 status; 2115 __u8 ctrl_state; 2116 __u8 io_state; 2117 __be32 node_id; 2118 __be32 ctrl_id; 2119 __be32 io_id; 2120 struct fw_foiscsi_sess_attr { 2121 __be32 sess_type_to_erl; 2122 __be16 max_conn; 2123 __be16 max_r2t; 2124 __be16 time2wait; 2125 __be16 time2retain; 2126 __be32 max_burst; 2127 __be32 first_burst; 2128 __be32 r1; 2129 } sess_attr; 2130 struct fw_foiscsi_conn_attr { 2131 __be32 hdigest_to_auth_policy; 2132 __be32 max_rcv_dsl; 2133 __be32 ping_tmo; 2134 __be16 dst_port; 2135 __be16 src_port; 2136 union fw_foiscsi_conn_attr_addr { 2137 struct fw_foiscsi_conn_attr_ipv6 { 2138 __be64 dst_addr[2]; 2139 __be64 src_addr[2]; 2140 } ipv6_addr; 2141 struct fw_foiscsi_conn_attr_ipv4 { 2142 __be32 dst_addr; 2143 __be32 src_addr; 2144 } ipv4_addr; 2145 } u; 2146 } conn_attr; 2147 __u8 tgt_name_len; 2148 __u8 r3[7]; 2149 __u8 tgt_name[224]; 2150 }; 2151 2152 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2153 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2154 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2155 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2156 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2157 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & \ 2158 M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2159 2160 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2161 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2162 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2163 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2164 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2165 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2166 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2167 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2168 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2169 2170 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2171 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2172 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2173 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2174 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2175 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2176 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2177 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2178 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2179 2180 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2181 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2182 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2183 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2184 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2185 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2186 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2187 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2188 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2189 2190 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2191 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2192 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2193 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2194 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2195 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2196 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2197 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2198 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2199 2200 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2201 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2202 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2203 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2204 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2205 2206 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2207 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2208 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2209 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2210 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2211 2212 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2213 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2214 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2215 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2216 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2217 2218 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2219 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2220 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2221 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2222 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2223 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2224 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2225 2226 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2227 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2228 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2229 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2230 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2231 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2232 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2233 2234 struct fw_foiscsi_chap_wr { 2235 __be32 op_compl; 2236 __be32 flowid_len16; 2237 __u64 cookie; 2238 __u8 status; 2239 __u8 id_len; 2240 __u8 sec_len; 2241 __u8 tgt_id_len; 2242 __u8 tgt_sec_len; 2243 __be16 node_id; 2244 __u8 r2; 2245 __u8 chap_id[64]; 2246 __u8 chap_sec[16]; 2247 __u8 tgt_id[64]; 2248 __u8 tgt_sec[16]; 2249 }; 2250 2251 /* 2252 * ***************************************** 2253 * F O F C O E W O R K R E Q U E S T s 2254 * ***************************************** 2255 */ 2256 2257 struct fw_fcoe_els_ct_wr { 2258 __be32 op_immdlen; 2259 __be32 flowid_len16; 2260 __be64 cookie; 2261 __be16 iqid; 2262 __u8 tmo_val; 2263 __u8 els_ct_type; 2264 __u8 ctl_pri; 2265 __u8 cp_en_class; 2266 __be16 xfer_cnt; 2267 __u8 fl_to_sp; 2268 __u8 l_id[3]; 2269 __u8 r5; 2270 __u8 r_id[3]; 2271 __be64 rsp_dmaaddr; 2272 __be32 rsp_dmalen; 2273 __be32 r6; 2274 }; 2275 2276 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2277 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2278 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2279 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2280 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2281 2282 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2283 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2284 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2285 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2286 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2287 2288 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2289 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2290 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2291 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2292 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2293 2294 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2295 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2296 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2297 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2298 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2299 2300 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2301 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2302 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2303 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2304 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2305 2306 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2307 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2308 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2309 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2310 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2311 2312 #define S_FW_FCOE_ELS_CT_WR_FL 2 2313 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2314 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2315 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2316 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2317 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2318 2319 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2320 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2321 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2322 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2323 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2324 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2325 2326 #define S_FW_FCOE_ELS_CT_WR_SP 0 2327 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2328 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2329 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2330 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2331 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2332 2333 /* 2334 * **************************************** 2335 * S C S I W O R K R E Q U E S T s 2336 * (FOiSCSI and FCOE unified data path) 2337 * **************************************** 2338 */ 2339 2340 struct fw_scsi_write_wr { 2341 __be32 op_immdlen; 2342 __be32 flowid_len16; 2343 __be64 cookie; 2344 __be16 iqid; 2345 __u8 tmo_val; 2346 __u8 use_xfer_cnt; 2347 union fw_scsi_write_priv { 2348 struct fcoe_write_priv { 2349 __u8 ctl_pri; 2350 __u8 cp_en_class; 2351 __u8 r3_lo[2]; 2352 } fcoe; 2353 struct iscsi_write_priv { 2354 __u8 r3[4]; 2355 } iscsi; 2356 } u; 2357 __be32 xfer_cnt; 2358 __be32 ini_xfer_cnt; 2359 __be64 rsp_dmaaddr; 2360 __be32 rsp_dmalen; 2361 __be32 r4; 2362 }; 2363 2364 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2365 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2366 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2367 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2368 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2369 2370 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2371 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2372 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2373 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2374 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2375 2376 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2377 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2378 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2379 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2380 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2381 2382 #define S_FW_SCSI_WRITE_WR_LEN16 0 2383 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2384 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2385 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2386 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2387 2388 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2389 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2390 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2391 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2392 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2393 2394 #define S_FW_SCSI_WRITE_WR_CLASS 4 2395 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2396 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2397 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2398 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2399 2400 struct fw_scsi_read_wr { 2401 __be32 op_immdlen; 2402 __be32 flowid_len16; 2403 __be64 cookie; 2404 __be16 iqid; 2405 __u8 tmo_val; 2406 __u8 use_xfer_cnt; 2407 union fw_scsi_read_priv { 2408 struct fcoe_read_priv { 2409 __u8 ctl_pri; 2410 __u8 cp_en_class; 2411 __u8 r3_lo[2]; 2412 } fcoe; 2413 struct iscsi_read_priv { 2414 __u8 r3[4]; 2415 } iscsi; 2416 } u; 2417 __be32 xfer_cnt; 2418 __be32 ini_xfer_cnt; 2419 __be64 rsp_dmaaddr; 2420 __be32 rsp_dmalen; 2421 __be32 r4; 2422 }; 2423 2424 #define S_FW_SCSI_READ_WR_OPCODE 24 2425 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2426 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2427 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2428 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2429 2430 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2431 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2432 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2433 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2434 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2435 2436 #define S_FW_SCSI_READ_WR_FLOWID 8 2437 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2438 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2439 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2440 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2441 2442 #define S_FW_SCSI_READ_WR_LEN16 0 2443 #define M_FW_SCSI_READ_WR_LEN16 0xff 2444 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2445 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2446 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2447 2448 #define S_FW_SCSI_READ_WR_CP_EN 6 2449 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2450 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2451 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2452 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2453 2454 #define S_FW_SCSI_READ_WR_CLASS 4 2455 #define M_FW_SCSI_READ_WR_CLASS 0x3 2456 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2457 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2458 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2459 2460 struct fw_scsi_cmd_wr { 2461 __be32 op_immdlen; 2462 __be32 flowid_len16; 2463 __be64 cookie; 2464 __be16 iqid; 2465 __u8 tmo_val; 2466 __u8 r3; 2467 union fw_scsi_cmd_priv { 2468 struct fcoe_cmd_priv { 2469 __u8 ctl_pri; 2470 __u8 cp_en_class; 2471 __u8 r4_lo[2]; 2472 } fcoe; 2473 struct iscsi_cmd_priv { 2474 __u8 r4[4]; 2475 } iscsi; 2476 } u; 2477 __u8 r5[8]; 2478 __be64 rsp_dmaaddr; 2479 __be32 rsp_dmalen; 2480 __be32 r6; 2481 }; 2482 2483 #define S_FW_SCSI_CMD_WR_OPCODE 24 2484 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2485 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2486 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2487 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2488 2489 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2490 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2491 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2492 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2493 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2494 2495 #define S_FW_SCSI_CMD_WR_FLOWID 8 2496 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2497 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2498 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2499 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2500 2501 #define S_FW_SCSI_CMD_WR_LEN16 0 2502 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2503 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2504 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2505 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2506 2507 #define S_FW_SCSI_CMD_WR_CP_EN 6 2508 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2509 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2510 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2511 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2512 2513 #define S_FW_SCSI_CMD_WR_CLASS 4 2514 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2515 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2516 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2517 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2518 2519 struct fw_scsi_abrt_cls_wr { 2520 __be32 op_immdlen; 2521 __be32 flowid_len16; 2522 __be64 cookie; 2523 __be16 iqid; 2524 __u8 tmo_val; 2525 __u8 sub_opcode_to_chk_all_io; 2526 __u8 r3[4]; 2527 __be64 t_cookie; 2528 }; 2529 2530 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2531 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2532 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2533 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2534 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2535 2536 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2537 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2538 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2539 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2540 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2541 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2542 2543 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2544 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2545 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2546 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2547 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2548 2549 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2550 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2551 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2552 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2553 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2554 2555 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2556 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2557 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2558 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2559 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2560 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2561 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2562 2563 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2564 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2565 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2566 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2567 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2568 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2569 2570 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2571 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2572 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2573 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2574 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2575 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2576 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2577 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2578 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2579 2580 struct fw_scsi_tgt_acc_wr { 2581 __be32 op_immdlen; 2582 __be32 flowid_len16; 2583 __be64 cookie; 2584 __be16 iqid; 2585 __u8 r3; 2586 __u8 use_burst_len; 2587 union fw_scsi_tgt_acc_priv { 2588 struct fcoe_tgt_acc_priv { 2589 __u8 ctl_pri; 2590 __u8 cp_en_class; 2591 __u8 r4_lo[2]; 2592 } fcoe; 2593 struct iscsi_tgt_acc_priv { 2594 __u8 r4[4]; 2595 } iscsi; 2596 } u; 2597 __be32 burst_len; 2598 __be32 rel_off; 2599 __be64 r5; 2600 __be32 r6; 2601 __be32 tot_xfer_len; 2602 }; 2603 2604 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2605 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2606 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2607 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2608 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2609 2610 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2611 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2612 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2613 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2614 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2615 2616 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2617 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2618 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2619 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2620 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2621 2622 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2623 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2624 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2625 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2626 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2627 2628 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2629 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2630 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2631 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2632 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2633 2634 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2635 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2636 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2637 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2638 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2639 2640 struct fw_scsi_tgt_xmit_wr { 2641 __be32 op_immdlen; 2642 __be32 flowid_len16; 2643 __be64 cookie; 2644 __be16 iqid; 2645 __u8 auto_rsp; 2646 __u8 use_xfer_cnt; 2647 union fw_scsi_tgt_xmit_priv { 2648 struct fcoe_tgt_xmit_priv { 2649 __u8 ctl_pri; 2650 __u8 cp_en_class; 2651 __u8 r3_lo[2]; 2652 } fcoe; 2653 struct iscsi_tgt_xmit_priv { 2654 __u8 r3[4]; 2655 } iscsi; 2656 } u; 2657 __be32 xfer_cnt; 2658 __be32 r4; 2659 __be64 r5; 2660 __be32 r6; 2661 __be32 tot_xfer_len; 2662 }; 2663 2664 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2665 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2666 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2667 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2668 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2669 2670 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2671 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2672 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2673 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2674 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2675 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2676 2677 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2678 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2679 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2680 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2681 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2682 2683 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2684 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2685 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2686 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2687 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2688 2689 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2690 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2691 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2692 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2693 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2694 2695 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2696 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2697 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2698 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2699 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2700 2701 struct fw_scsi_tgt_rsp_wr { 2702 __be32 op_immdlen; 2703 __be32 flowid_len16; 2704 __be64 cookie; 2705 __be16 iqid; 2706 __u8 r3[2]; 2707 union fw_scsi_tgt_rsp_priv { 2708 struct fcoe_tgt_rsp_priv { 2709 __u8 ctl_pri; 2710 __u8 cp_en_class; 2711 __u8 r4_lo[2]; 2712 } fcoe; 2713 struct iscsi_tgt_rsp_priv { 2714 __u8 r4[4]; 2715 } iscsi; 2716 } u; 2717 __u8 r5[8]; 2718 }; 2719 2720 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2721 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2722 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2723 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2724 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2725 2726 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2727 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2728 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2729 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2730 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2731 2732 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2733 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2734 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2735 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2736 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2737 2738 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2739 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2740 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2741 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2742 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2743 2744 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2745 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2746 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2747 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2748 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2749 2750 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2751 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2752 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2753 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2754 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2755 2756 /* 2757 * ******************* 2758 * C O M M A N D s 2759 * ******************* 2760 */ 2761 2762 /* 2763 * The maximum length of time, in miliseconds, that we expect any firmware 2764 * command to take to execute and return a reply to the host. The RESET 2765 * and INITIALIZE commands can take a fair amount of time to execute but 2766 * most execute in far less time than this maximum. This constant is used 2767 * by host software to determine how long to wait for a firmware command 2768 * reply before declaring the firmware as dead/unreachable ... 2769 */ 2770 #define FW_CMD_MAX_TIMEOUT 10000 2771 2772 /* 2773 * If a host driver does a HELLO and discovers that there's already a MASTER 2774 * selected, we may have to wait for that MASTER to finish issuing RESET, 2775 * configuration and INITIALIZE commands. Also, there's a possibility that 2776 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2777 * RESET command, so we need to be willing to make a few retries of our HELLO. 2778 */ 2779 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2780 #define FW_CMD_HELLO_RETRIES 3 2781 2782 enum fw_cmd_opcodes { 2783 FW_LDST_CMD = 0x01, 2784 FW_RESET_CMD = 0x03, 2785 FW_HELLO_CMD = 0x04, 2786 FW_BYE_CMD = 0x05, 2787 FW_INITIALIZE_CMD = 0x06, 2788 FW_CAPS_CONFIG_CMD = 0x07, 2789 FW_PARAMS_CMD = 0x08, 2790 FW_PFVF_CMD = 0x09, 2791 FW_IQ_CMD = 0x10, 2792 FW_EQ_MNGT_CMD = 0x11, 2793 FW_EQ_ETH_CMD = 0x12, 2794 FW_EQ_CTRL_CMD = 0x13, 2795 FW_EQ_OFLD_CMD = 0x21, 2796 FW_VI_CMD = 0x14, 2797 FW_VI_MAC_CMD = 0x15, 2798 FW_VI_RXMODE_CMD = 0x16, 2799 FW_VI_ENABLE_CMD = 0x17, 2800 FW_VI_STATS_CMD = 0x1a, 2801 FW_ACL_MAC_CMD = 0x18, 2802 FW_ACL_VLAN_CMD = 0x19, 2803 FW_PORT_CMD = 0x1b, 2804 FW_PORT_STATS_CMD = 0x1c, 2805 FW_PORT_LB_STATS_CMD = 0x1d, 2806 FW_PORT_TRACE_CMD = 0x1e, 2807 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2808 FW_RSS_IND_TBL_CMD = 0x20, 2809 FW_RSS_GLB_CONFIG_CMD = 0x22, 2810 FW_RSS_VI_CONFIG_CMD = 0x23, 2811 FW_SCHED_CMD = 0x24, 2812 FW_DEVLOG_CMD = 0x25, 2813 FW_WATCHDOG_CMD = 0x27, 2814 FW_CLIP_CMD = 0x28, 2815 FW_CHNET_IFACE_CMD = 0x26, 2816 FW_FCOE_RES_INFO_CMD = 0x31, 2817 FW_FCOE_LINK_CMD = 0x32, 2818 FW_FCOE_VNP_CMD = 0x33, 2819 FW_FCOE_SPARAMS_CMD = 0x35, 2820 FW_FCOE_STATS_CMD = 0x37, 2821 FW_FCOE_FCF_CMD = 0x38, 2822 FW_LASTC2E_CMD = 0x40, 2823 FW_ERROR_CMD = 0x80, 2824 FW_DEBUG_CMD = 0x81, 2825 }; 2826 2827 enum fw_cmd_cap { 2828 FW_CMD_CAP_PF = 0x01, 2829 FW_CMD_CAP_DMAQ = 0x02, 2830 FW_CMD_CAP_PORT = 0x04, 2831 FW_CMD_CAP_PORTPROMISC = 0x08, 2832 FW_CMD_CAP_PORTSTATS = 0x10, 2833 FW_CMD_CAP_VF = 0x80, 2834 }; 2835 2836 /* 2837 * Generic command header flit0 2838 */ 2839 struct fw_cmd_hdr { 2840 __be32 hi; 2841 __be32 lo; 2842 }; 2843 2844 #define S_FW_CMD_OP 24 2845 #define M_FW_CMD_OP 0xff 2846 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2847 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2848 2849 #define S_FW_CMD_REQUEST 23 2850 #define M_FW_CMD_REQUEST 0x1 2851 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2852 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2853 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2854 2855 #define S_FW_CMD_READ 22 2856 #define M_FW_CMD_READ 0x1 2857 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 2858 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 2859 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 2860 2861 #define S_FW_CMD_WRITE 21 2862 #define M_FW_CMD_WRITE 0x1 2863 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 2864 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 2865 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 2866 2867 #define S_FW_CMD_EXEC 20 2868 #define M_FW_CMD_EXEC 0x1 2869 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 2870 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 2871 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 2872 2873 #define S_FW_CMD_RAMASK 20 2874 #define M_FW_CMD_RAMASK 0xf 2875 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 2876 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 2877 2878 #define S_FW_CMD_RETVAL 8 2879 #define M_FW_CMD_RETVAL 0xff 2880 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 2881 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 2882 2883 #define S_FW_CMD_LEN16 0 2884 #define M_FW_CMD_LEN16 0xff 2885 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 2886 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 2887 2888 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof (fw_struct) / 16) 2889 2890 /* 2891 * address spaces 2892 */ 2893 enum fw_ldst_addrspc { 2894 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 2895 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 2896 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 2897 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 2898 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2899 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2900 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2901 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2902 FW_LDST_ADDRSPC_MDIO = 0x0018, 2903 FW_LDST_ADDRSPC_MPS = 0x0020, 2904 FW_LDST_ADDRSPC_FUNC = 0x0028, 2905 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 2906 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, 2907 FW_LDST_ADDRSPC_LE = 0x0030, 2908 }; 2909 2910 /* 2911 * MDIO VSC8634 register access control field 2912 */ 2913 enum fw_ldst_mdio_vsc8634_aid { 2914 FW_LDST_MDIO_VS_STANDARD, 2915 FW_LDST_MDIO_VS_EXTENDED, 2916 FW_LDST_MDIO_VS_GPIO 2917 }; 2918 2919 enum fw_ldst_mps_fid { 2920 FW_LDST_MPS_ATRB, 2921 FW_LDST_MPS_RPLC 2922 }; 2923 2924 enum fw_ldst_func_access_ctl { 2925 FW_LDST_FUNC_ACC_CTL_VIID, 2926 FW_LDST_FUNC_ACC_CTL_FID 2927 }; 2928 2929 enum fw_ldst_func_mod_index { 2930 FW_LDST_FUNC_MPS 2931 }; 2932 2933 struct fw_ldst_cmd { 2934 __be32 op_to_addrspace; 2935 __be32 cycles_to_len16; 2936 union fw_ldst { 2937 struct fw_ldst_addrval { 2938 __be32 addr; 2939 __be32 val; 2940 } addrval; 2941 struct fw_ldst_idctxt { 2942 __be32 physid; 2943 __be32 msg_ctxtflush; 2944 __be32 ctxt_data7; 2945 __be32 ctxt_data6; 2946 __be32 ctxt_data5; 2947 __be32 ctxt_data4; 2948 __be32 ctxt_data3; 2949 __be32 ctxt_data2; 2950 __be32 ctxt_data1; 2951 __be32 ctxt_data0; 2952 } idctxt; 2953 struct fw_ldst_mdio { 2954 __be16 paddr_mmd; 2955 __be16 raddr; 2956 __be16 vctl; 2957 __be16 rval; 2958 } mdio; 2959 struct fw_ldst_mps { 2960 __be16 fid_ctl; 2961 __be16 rplcpf_pkd; 2962 __be32 rplc127_96; 2963 __be32 rplc95_64; 2964 __be32 rplc63_32; 2965 __be32 rplc31_0; 2966 __be32 atrb; 2967 __be16 vlan[16]; 2968 } mps; 2969 struct fw_ldst_func { 2970 __u8 access_ctl; 2971 __u8 mod_index; 2972 __be16 ctl_id; 2973 __be32 offset; 2974 __be64 data0; 2975 __be64 data1; 2976 } func; 2977 struct fw_ldst_pcie { 2978 __u8 ctrl_to_fn; 2979 __u8 bnum; 2980 __u8 r; 2981 __u8 ext_r; 2982 __u8 select_naccess; 2983 __u8 pcie_fn; 2984 __be16 nset_pkd; 2985 __be32 data[12]; 2986 } pcie; 2987 struct fw_ldst_i2c { 2988 __u8 pid_pkd; 2989 __u8 base; 2990 __u8 boffset; 2991 __u8 data; 2992 __be32 r9; 2993 } i2c; 2994 struct fw_ldst_le { 2995 __be16 region; 2996 __be16 nval; 2997 __u32 val[12]; 2998 } le; 2999 } u; 3000 }; 3001 3002 #define S_FW_LDST_CMD_ADDRSPACE 0 3003 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3004 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3005 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3006 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3007 3008 #define S_FW_LDST_CMD_CYCLES 16 3009 #define M_FW_LDST_CMD_CYCLES 0xffff 3010 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3011 #define G_FW_LDST_CMD_CYCLES(x) \ 3012 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3013 3014 #define S_FW_LDST_CMD_MSG 31 3015 #define M_FW_LDST_CMD_MSG 0x1 3016 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3017 #define G_FW_LDST_CMD_MSG(x) \ 3018 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3019 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3020 3021 #define S_FW_LDST_CMD_CTXTFLUSH 30 3022 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3023 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3024 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3025 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3026 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3027 3028 #define S_FW_LDST_CMD_PADDR 8 3029 #define M_FW_LDST_CMD_PADDR 0x1f 3030 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3031 #define G_FW_LDST_CMD_PADDR(x) \ 3032 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3033 3034 #define S_FW_LDST_CMD_MMD 0 3035 #define M_FW_LDST_CMD_MMD 0x1f 3036 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3037 #define G_FW_LDST_CMD_MMD(x) \ 3038 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3039 3040 #define S_FW_LDST_CMD_FID 15 3041 #define M_FW_LDST_CMD_FID 0x1 3042 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3043 #define G_FW_LDST_CMD_FID(x) \ 3044 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3045 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3046 3047 #define S_FW_LDST_CMD_CTL 0 3048 #define M_FW_LDST_CMD_CTL 0x7fff 3049 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3050 #define G_FW_LDST_CMD_CTL(x) \ 3051 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3052 3053 #define S_FW_LDST_CMD_RPLCPF 0 3054 #define M_FW_LDST_CMD_RPLCPF 0xff 3055 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3056 #define G_FW_LDST_CMD_RPLCPF(x) \ 3057 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3058 3059 #define S_FW_LDST_CMD_CTRL 7 3060 #define M_FW_LDST_CMD_CTRL 0x1 3061 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3062 #define G_FW_LDST_CMD_CTRL(x) \ 3063 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3064 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3065 3066 #define S_FW_LDST_CMD_LC 4 3067 #define M_FW_LDST_CMD_LC 0x1 3068 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3069 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3070 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3071 3072 #define S_FW_LDST_CMD_AI 3 3073 #define M_FW_LDST_CMD_AI