1 /*
2  * Chelsio Terminator 4 (T4) Firmware interface header file.
3  *
4  * Copyright (C) 2009-2014 Chelsio Communications.  All rights reserved.
5  *
6  * Written by felix marti (felix@chelsio.com)
7  *
8  * This program is distributed in the hope that it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
11  * release for licensing terms and conditions.
12  */
13 
14 #ifndef _T4FW_INTERFACE_H_
15 #define _T4FW_INTERFACE_H_
16 
17 /******************************************************************************
18  *   R E T U R N   V A L U E S
19  ********************************/
20 
21 enum fw_retval {
22 	FW_SUCCESS		= 0,	/* completed sucessfully */
23 	FW_EPERM		= 1,	/* operation not permitted */
24 	FW_ENOENT		= 2,	/* no such file or directory */
25 	FW_EIO			= 5,	/* input/output error; hw bad */
26 	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
27 	FW_EAGAIN		= 11,	/* try again */
28 	FW_ENOMEM		= 12,	/* out of memory */
29 	FW_EFAULT		= 14,	/* bad address; fw bad */
30 	FW_EBUSY		= 16,	/* resource busy */
31 	FW_EEXIST		= 17,	/* file exists */
32 	FW_ENODEV		= 19,	/* no such device */
33 	FW_EINVAL		= 22,	/* invalid argument */
34 	FW_ENOSPC		= 28,	/* no space left on device */
35 	FW_ENOSYS		= 38,	/* functionality not implemented */
36 	FW_ENODATA		= 61,	/* no data available */
37 	FW_EPROTO		= 71,	/* protocol error */
38 	FW_EADDRINUSE		= 98,	/* address already in use */
39 	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
40 	FW_ENETDOWN		= 100,	/* network is down */
41 	FW_ENETUNREACH		= 101,	/* network is unreachable */
42 	FW_ENOBUFS		= 105,	/* no buffer space available */
43 	FW_ETIMEDOUT		= 110,	/* timeout */
44 	FW_EINPROGRESS		= 115,	/* fw internal */
45 	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
46 	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
47 	FW_SCSI_ABORTED		= 130,	/* */
48 	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
49 	FW_ERR_LINK_DOWN	= 132,	/* */
50 	FW_RDEV_NOT_READY	= 133,	/* */
51 	FW_ERR_RDEV_LOST	= 134,	/* */
52 	FW_ERR_RDEV_LOGO	= 135,	/* */
53 	FW_FCOE_NO_XCHG		= 136,	/* */
54 	FW_SCSI_RSP_ERR		= 137,	/* */
55 	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
56 	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
57 	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
58 	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
59 	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
60 };
61 
62 /******************************************************************************
63  *   M E M O R Y   T Y P E s
64  ******************************/
65 
66 enum fw_memtype {
67 	FW_MEMTYPE_EDC0		= 0x0,
68 	FW_MEMTYPE_EDC1		= 0x1,
69 	FW_MEMTYPE_EXTMEM	= 0x2,
70 	FW_MEMTYPE_FLASH	= 0x4,
71 	FW_MEMTYPE_INTERNAL	= 0x5,
72 	FW_MEMTYPE_EXTMEM1	= 0x6,
73 };
74 
75 /******************************************************************************
76  *   W O R K   R E Q U E S T s
77  ********************************/
78 
79 enum fw_wr_opcodes {
80 	FW_FRAG_WR		= 0x1d,
81 	FW_FILTER_WR		= 0x02,
82 	FW_ULPTX_WR		= 0x04,
83 	FW_TP_WR		= 0x05,
84 	FW_ETH_TX_PKT_WR	= 0x08,
85 	FW_ETH_TX_PKT2_WR	= 0x44,
86 	FW_ETH_TX_PKTS_WR	= 0x09,
87 	FW_ETH_TX_PKTS2_WR	= 0x78,
88 	FW_ETH_TX_EO_WR		= 0x1c,
89 	FW_EQ_FLUSH_WR		= 0x1b,
90 	FW_OFLD_CONNECTION_WR	= 0x2f,
91 	FW_FLOWC_WR		= 0x0a,
92 	FW_OFLD_TX_DATA_WR	= 0x0b,
93 	FW_CMD_WR		= 0x10,
94 	FW_ETH_TX_PKT_VM_WR	= 0x11,
95 	FW_RI_RES_WR		= 0x0c,
96 	FW_RI_RDMA_WRITE_WR	= 0x14,
97 	FW_RI_SEND_WR		= 0x15,
98 	FW_RI_RDMA_READ_WR	= 0x16,
99 	FW_RI_RECV_WR		= 0x17,
100 	FW_RI_BIND_MW_WR	= 0x18,
101 	FW_RI_FR_NSMR_WR	= 0x19,
102 	FW_RI_FR_NSMR_TPTE_WR	= 0x20,
103 	FW_RI_INV_LSTAG_WR	= 0x1a,
104 	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
105 	FW_RI_ATOMIC_WR		= 0x16,
106 	FW_RI_WR		= 0x0d,
107 	FW_CHNET_IFCONF_WR	= 0x6b,
108 	FW_RDEV_WR		= 0x38,
109 	FW_FOISCSI_NODE_WR	= 0x60,
110 	FW_FOISCSI_CTRL_WR	= 0x6a,
111 	FW_FOISCSI_CHAP_WR	= 0x6c,
112 	FW_FCOE_ELS_CT_WR	= 0x30,
113 	FW_SCSI_WRITE_WR	= 0x31,
114 	FW_SCSI_READ_WR		= 0x32,
115 	FW_SCSI_CMD_WR		= 0x33,
116 	FW_SCSI_ABRT_CLS_WR	= 0x34,
117 	FW_SCSI_TGT_ACC_WR	= 0x35,
118 	FW_SCSI_TGT_XMIT_WR	= 0x36,
119 	FW_SCSI_TGT_RSP_WR	= 0x37,
120 	FW_POFCOE_TCB_WR	= 0x42,
121 	FW_POFCOE_ULPTX_WR	= 0x43,
122 	FW_ISCSI_TX_DATA_WR	= 0x45,
123 	FW_PTP_TX_PKT_WR        = 0x46,
124 	FW_TLSTX_DATA_WR	= 0x68,
125 	FW_TLS_KEYCTX_TX_WR	= 0x69,
126 	FW_CRYPTO_LOOKASIDE_WR	= 0x6d,
127 	FW_COiSCSI_TGT_WR	= 0x70,
128 	FW_COiSCSI_TGT_CONN_WR	= 0x71,
129 	FW_COiSCSI_TGT_XMIT_WR	= 0x72,
130 	FW_ISNS_WR		= 0x75,
131 	FW_ISNS_XMIT_WR		= 0x76,
132 	FW_FILTER2_WR		= 0x77,
133 	FW_LASTC2E_WR		= 0x80
134 };
135 
136 /*
137  * Generic work request header flit0
138  */
139 struct fw_wr_hdr {
140 	__be32 hi;
141 	__be32 lo;
142 };
143 
144 /*	work request opcode (hi)
145  */
146 #define S_FW_WR_OP		24
147 #define M_FW_WR_OP		0xff
148 #define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
149 #define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
150 
151 /*	atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
152  */
153 #define S_FW_WR_ATOMIC		23
154 #define M_FW_WR_ATOMIC		0x1
155 #define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
156 #define G_FW_WR_ATOMIC(x)	\
157     (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
158 #define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
159 
160 /*	flush flag (hi) - firmware flushes flushable work request buffered
161  *			      in the flow context.
162  */
163 #define S_FW_WR_FLUSH     22
164 #define M_FW_WR_FLUSH     0x1
165 #define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
166 #define G_FW_WR_FLUSH(x)  \
167     (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
168 #define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
169 
170 /*	completion flag (hi) - firmware generates a cpl_fw6_ack
171  */
172 #define S_FW_WR_COMPL     21
173 #define M_FW_WR_COMPL     0x1
174 #define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
175 #define G_FW_WR_COMPL(x)  \
176     (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
177 #define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
178 
179 
180 /*	work request immediate data lengh (hi)
181  */
182 #define S_FW_WR_IMMDLEN	0
183 #define M_FW_WR_IMMDLEN	0xff
184 #define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
185 #define G_FW_WR_IMMDLEN(x)	\
186     (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
187 
188 /*	egress queue status update to associated ingress queue entry (lo)
189  */
190 #define S_FW_WR_EQUIQ		31
191 #define M_FW_WR_EQUIQ		0x1
192 #define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
193 #define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
194 #define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
195 
196 /*	egress queue status update to egress queue status entry (lo)
197  */
198 #define S_FW_WR_EQUEQ		30
199 #define M_FW_WR_EQUEQ		0x1
200 #define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
201 #define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
202 #define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
203 
204 /*	flow context identifier (lo)
205  */
206 #define S_FW_WR_FLOWID		8
207 #define M_FW_WR_FLOWID		0xfffff
208 #define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
209 #define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
210 
211 /*	length in units of 16-bytes (lo)
212  */
213 #define S_FW_WR_LEN16		0
214 #define M_FW_WR_LEN16		0xff
215 #define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
216 #define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
217 
218 struct fw_frag_wr {
219 	__be32 op_to_fragoff16;
220 	__be32 flowid_len16;
221 	__be64 r4;
222 };
223 
224 #define S_FW_FRAG_WR_EOF	15
225 #define M_FW_FRAG_WR_EOF	0x1
226 #define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
227 #define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
228 #define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
229 
230 #define S_FW_FRAG_WR_FRAGOFF16		8
231 #define M_FW_FRAG_WR_FRAGOFF16		0x7f
232 #define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
233 #define G_FW_FRAG_WR_FRAGOFF16(x)	\
234     (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
235 
236 /* valid filter configurations for compressed tuple
237  * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
238  * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
239  * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
240  * OV - Outer VLAN/VNIC_ID,
241 */
242 #define HW_TPL_FR_MT_M_E_P_FC		0x3C3
243 #define HW_TPL_FR_MT_M_PR_T_FC		0x3B3
244 #define HW_TPL_FR_MT_M_IV_P_FC		0x38B
245 #define HW_TPL_FR_MT_M_OV_P_FC		0x387
246 #define HW_TPL_FR_MT_E_PR_T		0x370
247 #define HW_TPL_FR_MT_E_PR_P_FC		0X363
248 #define HW_TPL_FR_MT_E_T_P_FC		0X353
249 #define HW_TPL_FR_MT_PR_IV_P_FC		0X32B
250 #define HW_TPL_FR_MT_PR_OV_P_FC		0X327
251 #define HW_TPL_FR_MT_T_IV_P_FC		0X31B
252 #define HW_TPL_FR_MT_T_OV_P_FC		0X317
253 #define HW_TPL_FR_M_E_PR_FC		0X2E1
254 #define HW_TPL_FR_M_E_T_FC		0X2D1
255 #define HW_TPL_FR_M_PR_IV_FC		0X2A9
256 #define HW_TPL_FR_M_PR_OV_FC		0X2A5
257 #define HW_TPL_FR_M_T_IV_FC		0X299
258 #define HW_TPL_FR_M_T_OV_FC		0X295
259 #define HW_TPL_FR_E_PR_T_P		0X272
260 #define HW_TPL_FR_E_PR_T_FC		0X271
261 #define HW_TPL_FR_E_IV_FC		0X249
262 #define HW_TPL_FR_E_OV_FC		0X245
263 #define HW_TPL_FR_PR_T_IV_FC		0X239
264 #define HW_TPL_FR_PR_T_OV_FC		0X235
265 #define HW_TPL_FR_IV_OV_FC		0X20D
266 #define HW_TPL_MT_M_E_PR		0X1E0
267 #define HW_TPL_MT_M_E_T			0X1D0
268 #define HW_TPL_MT_E_PR_T_FC		0X171
269 #define HW_TPL_MT_E_IV			0X148
270 #define HW_TPL_MT_E_OV			0X144
271 #define HW_TPL_MT_PR_T_IV		0X138
272 #define HW_TPL_MT_PR_T_OV		0X134
273 #define HW_TPL_M_E_PR_P			0X0E2
274 #define HW_TPL_M_E_T_P			0X0D2
275 #define HW_TPL_E_PR_T_P_FC		0X073
276 #define HW_TPL_E_IV_P			0X04A
277 #define HW_TPL_E_OV_P			0X046
278 #define HW_TPL_PR_T_IV_P		0X03A
279 #define HW_TPL_PR_T_OV_P		0X036
280 
281 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
282 enum fw_filter_wr_cookie {
283 	FW_FILTER_WR_SUCCESS,
284 	FW_FILTER_WR_FLT_ADDED,
285 	FW_FILTER_WR_FLT_DELETED,
286 	FW_FILTER_WR_SMT_TBL_FULL,
287 	FW_FILTER_WR_EINVAL,
288 };
289 
290 enum fw_filter_wr_nat_mode {
291 	FW_FILTER_WR_NATMODE_NONE = 0,
292 	FW_FILTER_WR_NATMODE_DIP ,
293 	FW_FILTER_WR_NATMODE_DIPDP,
294 	FW_FILTER_WR_NATMODE_DIPDPSIP,
295 	FW_FILTER_WR_NATMODE_DIPDPSP,
296 	FW_FILTER_WR_NATMODE_SIPSP,
297 	FW_FILTER_WR_NATMODE_DIPSIPSP,
298 	FW_FILTER_WR_NATMODE_FOURTUPLE,
299 };
300 
301 struct fw_filter_wr {
302 	__be32 op_pkd;
303 	__be32 len16_pkd;
304 	__be64 r3;
305 	__be32 tid_to_iq;
306 	__be32 del_filter_to_l2tix;
307 	__be16 ethtype;
308 	__be16 ethtypem;
309 	__u8   frag_to_ovlan_vldm;
310 	__u8   smac_sel;
311 	__be16 rx_chan_rx_rpl_iq;
312 	__be32 maci_to_matchtypem;
313 	__u8   ptcl;
314 	__u8   ptclm;
315 	__u8   ttyp;
316 	__u8   ttypm;
317 	__be16 ivlan;
318 	__be16 ivlanm;
319 	__be16 ovlan;
320 	__be16 ovlanm;
321 	__u8   lip[16];
322 	__u8   lipm[16];
323 	__u8   fip[16];
324 	__u8   fipm[16];
325 	__be16 lp;
326 	__be16 lpm;
327 	__be16 fp;
328 	__be16 fpm;
329 	__be16 r7;
330 	__u8   sma[6];
331 };
332 
333 struct fw_filter2_wr {
334 	__be32 op_pkd;
335 	__be32 len16_pkd;
336 	__be64 r3;
337 	__be32 tid_to_iq;
338 	__be32 del_filter_to_l2tix;
339 	__be16 ethtype;
340 	__be16 ethtypem;
341 	__u8   frag_to_ovlan_vldm;
342 	__u8   smac_sel;
343 	__be16 rx_chan_rx_rpl_iq;
344 	__be32 maci_to_matchtypem;
345 	__u8   ptcl;
346 	__u8   ptclm;
347 	__u8   ttyp;
348 	__u8   ttypm;
349 	__be16 ivlan;
350 	__be16 ivlanm;
351 	__be16 ovlan;
352 	__be16 ovlanm;
353 	__u8   lip[16];
354 	__u8   lipm[16];
355 	__u8   fip[16];
356 	__u8   fipm[16];
357 	__be16 lp;
358 	__be16 lpm;
359 	__be16 fp;
360 	__be16 fpm;
361 	__be16 r7;
362 	__u8   sma[6];
363 	__u8   r8_hi[2];
364 	__u8   filter_type_swapmac;
365 	__u8   natmode_to_ulp_type;
366 	__be16 newlport;
367 	__be16 newfport;
368 	__u8   newlip[16];
369 	__u8   newfip[16];
370 	__be32 natseqcheck;
371 	__be32 dip_hit_vni;
372 	__be64 r10;
373 	__be64 r11;
374 	__be64 r12;
375 	__be64 r13;
376 };
377 
378 #define S_FW_FILTER_WR_TID	12
379 #define M_FW_FILTER_WR_TID	0xfffff
380 #define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
381 #define G_FW_FILTER_WR_TID(x)	\
382     (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
383 
384 #define S_FW_FILTER_WR_RQTYPE		11
385 #define M_FW_FILTER_WR_RQTYPE		0x1
386 #define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
387 #define G_FW_FILTER_WR_RQTYPE(x)	\
388     (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
389 #define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
390 
391 #define S_FW_FILTER_WR_NOREPLY		10
392 #define M_FW_FILTER_WR_NOREPLY		0x1
393 #define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
394 #define G_FW_FILTER_WR_NOREPLY(x)	\
395     (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
396 #define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
397 
398 #define S_FW_FILTER_WR_IQ	0
399 #define M_FW_FILTER_WR_IQ	0x3ff
400 #define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
401 #define G_FW_FILTER_WR_IQ(x)	\
402     (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
403 
404 #define S_FW_FILTER_WR_DEL_FILTER	31
405 #define M_FW_FILTER_WR_DEL_FILTER	0x1
406 #define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
407 #define G_FW_FILTER_WR_DEL_FILTER(x)	\
408     (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
409 #define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
410 
411 #define S_FW_FILTER_WR_RPTTID		25
412 #define M_FW_FILTER_WR_RPTTID		0x1
413 #define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
414 #define G_FW_FILTER_WR_RPTTID(x)	\
415     (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
416 #define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
417 
418 #define S_FW_FILTER_WR_DROP	24
419 #define M_FW_FILTER_WR_DROP	0x1
420 #define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
421 #define G_FW_FILTER_WR_DROP(x)	\
422     (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
423 #define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
424 
425 #define S_FW_FILTER_WR_DIRSTEER		23
426 #define M_FW_FILTER_WR_DIRSTEER		0x1
427 #define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
428 #define G_FW_FILTER_WR_DIRSTEER(x)	\
429     (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
430 #define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
431 
432 #define S_FW_FILTER_WR_MASKHASH		22
433 #define M_FW_FILTER_WR_MASKHASH		0x1
434 #define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
435 #define G_FW_FILTER_WR_MASKHASH(x)	\
436     (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
437 #define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
438 
439 #define S_FW_FILTER_WR_DIRSTEERHASH	21
440 #define M_FW_FILTER_WR_DIRSTEERHASH	0x1
441 #define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
442 #define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
443     (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
444 #define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
445 
446 #define S_FW_FILTER_WR_LPBK	20
447 #define M_FW_FILTER_WR_LPBK	0x1
448 #define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
449 #define G_FW_FILTER_WR_LPBK(x)	\
450     (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
451 #define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
452 
453 #define S_FW_FILTER_WR_DMAC	19
454 #define M_FW_FILTER_WR_DMAC	0x1
455 #define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
456 #define G_FW_FILTER_WR_DMAC(x)	\
457     (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
458 #define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
459 
460 #define S_FW_FILTER_WR_SMAC	18
461 #define M_FW_FILTER_WR_SMAC	0x1
462 #define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
463 #define G_FW_FILTER_WR_SMAC(x)	\
464     (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
465 #define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
466 
467 #define S_FW_FILTER_WR_INSVLAN		17
468 #define M_FW_FILTER_WR_INSVLAN		0x1
469 #define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
470 #define G_FW_FILTER_WR_INSVLAN(x)	\
471     (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
472 #define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
473 
474 #define S_FW_FILTER_WR_RMVLAN		16
475 #define M_FW_FILTER_WR_RMVLAN		0x1
476 #define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
477 #define G_FW_FILTER_WR_RMVLAN(x)	\
478     (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
479 #define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
480 
481 #define S_FW_FILTER_WR_HITCNTS		15
482 #define M_FW_FILTER_WR_HITCNTS		0x1
483 #define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
484 #define G_FW_FILTER_WR_HITCNTS(x)	\
485     (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
486 #define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
487 
488 #define S_FW_FILTER_WR_TXCHAN		13
489 #define M_FW_FILTER_WR_TXCHAN		0x3
490 #define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
491 #define G_FW_FILTER_WR_TXCHAN(x)	\
492     (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
493 
494 #define S_FW_FILTER_WR_PRIO	12
495 #define M_FW_FILTER_WR_PRIO	0x1
496 #define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
497 #define G_FW_FILTER_WR_PRIO(x)	\
498     (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
499 #define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
500 
501 #define S_FW_FILTER_WR_L2TIX	0
502 #define M_FW_FILTER_WR_L2TIX	0xfff
503 #define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
504 #define G_FW_FILTER_WR_L2TIX(x)	\
505     (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
506 
507 #define S_FW_FILTER_WR_FRAG	7
508 #define M_FW_FILTER_WR_FRAG	0x1
509 #define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
510 #define G_FW_FILTER_WR_FRAG(x)	\
511     (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
512 #define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
513 
514 #define S_FW_FILTER_WR_FRAGM	6
515 #define M_FW_FILTER_WR_FRAGM	0x1
516 #define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
517 #define G_FW_FILTER_WR_FRAGM(x)	\
518     (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
519 #define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
520 
521 #define S_FW_FILTER_WR_IVLAN_VLD	5
522 #define M_FW_FILTER_WR_IVLAN_VLD	0x1
523 #define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
524 #define G_FW_FILTER_WR_IVLAN_VLD(x)	\
525     (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
526 #define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
527 
528 #define S_FW_FILTER_WR_OVLAN_VLD	4
529 #define M_FW_FILTER_WR_OVLAN_VLD	0x1
530 #define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
531 #define G_FW_FILTER_WR_OVLAN_VLD(x)	\
532     (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
533 #define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
534 
535 #define S_FW_FILTER_WR_IVLAN_VLDM	3
536 #define M_FW_FILTER_WR_IVLAN_VLDM	0x1
537 #define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
538 #define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
539     (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
540 #define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
541 
542 #define S_FW_FILTER_WR_OVLAN_VLDM	2
543 #define M_FW_FILTER_WR_OVLAN_VLDM	0x1
544 #define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
545 #define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
546     (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
547 #define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
548 
549 #define S_FW_FILTER_WR_RX_CHAN		15
550 #define M_FW_FILTER_WR_RX_CHAN		0x1
551 #define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
552 #define G_FW_FILTER_WR_RX_CHAN(x)	\
553     (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
554 #define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
555 
556 #define S_FW_FILTER_WR_RX_RPL_IQ	0
557 #define M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
558 #define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
559 #define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
560     (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
561 
562 #define S_FW_FILTER2_WR_FILTER_TYPE	1
563 #define M_FW_FILTER2_WR_FILTER_TYPE	0x1
564 #define V_FW_FILTER2_WR_FILTER_TYPE(x)	((x) << S_FW_FILTER2_WR_FILTER_TYPE)
565 #define G_FW_FILTER2_WR_FILTER_TYPE(x)	\
566     (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
567 #define F_FW_FILTER2_WR_FILTER_TYPE	V_FW_FILTER2_WR_FILTER_TYPE(1U)
568 
569 #define S_FW_FILTER2_WR_SWAPMAC		0
570 #define M_FW_FILTER2_WR_SWAPMAC		0x1
571 #define V_FW_FILTER2_WR_SWAPMAC(x)	((x) << S_FW_FILTER2_WR_SWAPMAC)
572 #define G_FW_FILTER2_WR_SWAPMAC(x)	\
573     (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
574 #define F_FW_FILTER2_WR_SWAPMAC		V_FW_FILTER2_WR_SWAPMAC(1U)
575 
576 #define S_FW_FILTER2_WR_NATMODE		5
577 #define M_FW_FILTER2_WR_NATMODE		0x7
578 #define V_FW_FILTER2_WR_NATMODE(x)	((x) << S_FW_FILTER2_WR_NATMODE)
579 #define G_FW_FILTER2_WR_NATMODE(x)	\
580     (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
581 
582 #define S_FW_FILTER2_WR_NATFLAGCHECK	4
583 #define M_FW_FILTER2_WR_NATFLAGCHECK	0x1
584 #define V_FW_FILTER2_WR_NATFLAGCHECK(x)	((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
585 #define G_FW_FILTER2_WR_NATFLAGCHECK(x)	\
586     (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
587 #define F_FW_FILTER2_WR_NATFLAGCHECK	V_FW_FILTER2_WR_NATFLAGCHECK(1U)
588 
589 #define S_FW_FILTER2_WR_ULP_TYPE	0
590 #define M_FW_FILTER2_WR_ULP_TYPE	0xf
591 #define V_FW_FILTER2_WR_ULP_TYPE(x)	((x) << S_FW_FILTER2_WR_ULP_TYPE)
592 #define G_FW_FILTER2_WR_ULP_TYPE(x)	\
593     (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
594 
595 #define S_FW_FILTER2_WR_DIP_HIT		24
596 #define M_FW_FILTER2_WR_DIP_HIT		0x1
597 #define V_FW_FILTER2_WR_DIP_HIT(x)	((x) << S_FW_FILTER2_WR_DIP_HIT)
598 #define G_FW_FILTER2_WR_DIP_HIT(x)	\
599     (((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT)
600 #define F_FW_FILTER2_WR_DIP_HIT		V_FW_FILTER2_WR_DIP_HIT(1U)
601 
602 #define S_FW_FILTER2_WR_VNI		0
603 #define M_FW_FILTER2_WR_VNI		0xffffff
604 #define V_FW_FILTER2_WR_VNI(x)		((x) << S_FW_FILTER2_WR_VNI)
605 #define G_FW_FILTER2_WR_VNI(x)		\
606     (((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI)
607 
608 #define S_FW_FILTER_WR_MACI	23
609 #define M_FW_FILTER_WR_MACI	0x1ff
610 #define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
611 #define G_FW_FILTER_WR_MACI(x)	\
612     (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
613 
614 #define S_FW_FILTER_WR_MACIM	14
615 #define M_FW_FILTER_WR_MACIM	0x1ff
616 #define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
617 #define G_FW_FILTER_WR_MACIM(x)	\
618     (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
619 
620 #define S_FW_FILTER_WR_FCOE	13
621 #define M_FW_FILTER_WR_FCOE	0x1
622 #define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
623 #define G_FW_FILTER_WR_FCOE(x)	\
624     (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
625 #define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
626 
627 #define S_FW_FILTER_WR_FCOEM	12
628 #define M_FW_FILTER_WR_FCOEM	0x1
629 #define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
630 #define G_FW_FILTER_WR_FCOEM(x)	\
631     (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
632 #define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
633 
634 #define S_FW_FILTER_WR_PORT	9
635 #define M_FW_FILTER_WR_PORT	0x7
636 #define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
637 #define G_FW_FILTER_WR_PORT(x)	\
638     (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
639 
640 #define S_FW_FILTER_WR_PORTM	6
641 #define M_FW_FILTER_WR_PORTM	0x7
642 #define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
643 #define G_FW_FILTER_WR_PORTM(x)	\
644     (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
645 
646 #define S_FW_FILTER_WR_MATCHTYPE	3
647 #define M_FW_FILTER_WR_MATCHTYPE	0x7
648 #define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
649 #define G_FW_FILTER_WR_MATCHTYPE(x)	\
650     (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
651 
652 #define S_FW_FILTER_WR_MATCHTYPEM	0
653 #define M_FW_FILTER_WR_MATCHTYPEM	0x7
654 #define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
655 #define G_FW_FILTER_WR_MATCHTYPEM(x)	\
656     (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
657 
658 struct fw_ulptx_wr {
659 	__be32 op_to_compl;
660 	__be32 flowid_len16;
661 	__u64  cookie;
662 };
663 
664 struct fw_tp_wr {
665 	__be32 op_to_immdlen;
666 	__be32 flowid_len16;
667 	__u64  cookie;
668 };
669 
670 struct fw_eth_tx_pkt_wr {
671 	__be32 op_immdlen;
672 	__be32 equiq_to_len16;
673 	__be64 r3;
674 };
675 
676 #define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
677 #define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
678 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
679 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
680     (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
681 
682 struct fw_eth_tx_pkt2_wr {
683 	__be32 op_immdlen;
684 	__be32 equiq_to_len16;
685 	__be32 r3;
686 	__be32 L4ChkDisable_to_IpHdrLen;
687 };
688 
689 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
690 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
691 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
692 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
693     (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
694 
695 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
696 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
697 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
698     ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
699 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
700     (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
701      M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
702 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
703     V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
704 
705 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
706 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
707 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
708     ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
709 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
710     (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
711      M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
712 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
713     V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
714 
715 #define S_FW_ETH_TX_PKT2_WR_IVLAN	28
716 #define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
717 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
718 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
719     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
720 #define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
721 
722 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
723 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
724 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
725 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
726     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
727 
728 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
729 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
730 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
731 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
732     (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
733 
734 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
735 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
736 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
737 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
738     (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
739 
740 struct fw_eth_tx_pkts_wr {
741 	__be32 op_pkd;
742 	__be32 equiq_to_len16;
743 	__be32 r3;
744 	__be16 plen;
745 	__u8   npkt;
746 	__u8   type;
747 };
748 
749 #define S_FW_PTP_TX_PKT_WR_IMMDLEN      0
750 #define M_FW_PTP_TX_PKT_WR_IMMDLEN      0x1ff
751 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
752 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x)   \
753     (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
754 
755 struct fw_eth_tx_pkt_ptp_wr {
756 	__be32 op_immdlen;
757 	__be32 equiq_to_len16;
758 	__be64 r3;
759 };
760 
761 enum fw_eth_tx_eo_type {
762 	FW_ETH_TX_EO_TYPE_UDPSEG,
763 	FW_ETH_TX_EO_TYPE_TCPSEG,
764 	FW_ETH_TX_EO_TYPE_NVGRESEG,
765 	FW_ETH_TX_EO_TYPE_VXLANSEG,
766 	FW_ETH_TX_EO_TYPE_GENEVESEG,
767 };
768 
769 struct fw_eth_tx_eo_wr {
770 	__be32 op_immdlen;
771 	__be32 equiq_to_len16;
772 	__be64 r3;
773 	union fw_eth_tx_eo {
774 		struct fw_eth_tx_eo_udpseg {
775 			__u8   type;
776 			__u8   ethlen;
777 			__be16 iplen;
778 			__u8   udplen;
779 			__u8   rtplen;
780 			__be16 r4;
781 			__be16 mss;
782 			__be16 schedpktsize;
783 			__be32 plen;
784 		} udpseg;
785 		struct fw_eth_tx_eo_tcpseg {
786 			__u8   type;
787 			__u8   ethlen;
788 			__be16 iplen;
789 			__u8   tcplen;
790 			__u8   tsclk_tsoff;
791 			__be16 r4;
792 			__be16 mss;
793 			__be16 r5;
794 			__be32 plen;
795 		} tcpseg;
796 		struct fw_eth_tx_eo_nvgreseg {
797 			__u8   type;
798 			__u8   iphdroffout;
799 			__be16 grehdroff;
800 			__be16 iphdroffin;
801 			__be16 tcphdroffin;
802 			__be16 mss;
803 			__be16 r4;
804 			__be32 plen;
805 		} nvgreseg;
806 		struct fw_eth_tx_eo_vxlanseg {
807 			__u8   type;
808 			__u8   iphdroffout;
809 			__be16 vxlanhdroff;
810 			__be16 iphdroffin;
811 			__be16 tcphdroffin;
812 			__be16 mss;
813 			__be16 r4;
814 			__be32 plen;
815 
816 		} vxlanseg;
817 		struct fw_eth_tx_eo_geneveseg {
818 			__u8   type;
819 			__u8   iphdroffout;
820 			__be16 genevehdroff;
821 			__be16 iphdroffin;
822 			__be16 tcphdroffin;
823 			__be16 mss;
824 			__be16 r4;
825 			__be32 plen;
826 		} geneveseg;
827 	} u;
828 };
829 
830 #define S_FW_ETH_TX_EO_WR_IMMDLEN	0
831 #define M_FW_ETH_TX_EO_WR_IMMDLEN	0x1ff
832 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
833 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x)	\
834     (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
835 
836 #define S_FW_ETH_TX_EO_WR_TSCLK		6
837 #define M_FW_ETH_TX_EO_WR_TSCLK		0x3
838 #define V_FW_ETH_TX_EO_WR_TSCLK(x)	((x) << S_FW_ETH_TX_EO_WR_TSCLK)
839 #define G_FW_ETH_TX_EO_WR_TSCLK(x)	\
840     (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
841 
842 #define S_FW_ETH_TX_EO_WR_TSOFF		0
843 #define M_FW_ETH_TX_EO_WR_TSOFF		0x3f
844 #define V_FW_ETH_TX_EO_WR_TSOFF(x)	((x) << S_FW_ETH_TX_EO_WR_TSOFF)
845 #define G_FW_ETH_TX_EO_WR_TSOFF(x)	\
846     (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
847 
848 struct fw_eq_flush_wr {
849 	__u8   opcode;
850 	__u8   r1[3];
851 	__be32 equiq_to_len16;
852 	__be64 r3;
853 };
854 
855 struct fw_ofld_connection_wr {
856 	__be32 op_compl;
857 	__be32 len16_pkd;
858 	__u64  cookie;
859 	__be64 r2;
860 	__be64 r3;
861 	struct fw_ofld_connection_le {
862 		__be32 version_cpl;
863 		__be32 filter;
864 		__be32 r1;
865 		__be16 lport;
866 		__be16 pport;
867 		union fw_ofld_connection_leip {
868 			struct fw_ofld_connection_le_ipv4 {
869 				__be32 pip;
870 				__be32 lip;
871 				__be64 r0;
872 				__be64 r1;
873 				__be64 r2;
874 			} ipv4;
875 			struct fw_ofld_connection_le_ipv6 {
876 				__be64 pip_hi;
877 				__be64 pip_lo;
878 				__be64 lip_hi;
879 				__be64 lip_lo;
880 			} ipv6;
881 		} u;
882 	} le;
883 	struct fw_ofld_connection_tcb {
884 		__be32 t_state_to_astid;
885 		__be16 cplrxdataack_cplpassacceptrpl;
886 		__be16 rcv_adv;
887 		__be32 rcv_nxt;
888 		__be32 tx_max;
889 		__be64 opt0;
890 		__be32 opt2;
891 		__be32 r1;
892 		__be64 r2;
893 		__be64 r3;
894 	} tcb;
895 };
896 
897 #define S_FW_OFLD_CONNECTION_WR_VERSION		31
898 #define M_FW_OFLD_CONNECTION_WR_VERSION		0x1
899 #define V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
900     ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
901 #define G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
902     (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
903      M_FW_OFLD_CONNECTION_WR_VERSION)
904 #define F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
905 
906 #define S_FW_OFLD_CONNECTION_WR_CPL	30
907 #define M_FW_OFLD_CONNECTION_WR_CPL	0x1
908 #define V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
909 #define G_FW_OFLD_CONNECTION_WR_CPL(x)	\
910     (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
911 #define F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
912 
913 #define S_FW_OFLD_CONNECTION_WR_T_STATE		28
914 #define M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
915 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
916     ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
917 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
918     (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
919      M_FW_OFLD_CONNECTION_WR_T_STATE)
920 
921 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
922 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
923 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
924     ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
925 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
926     (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
927      M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
928 
929 #define S_FW_OFLD_CONNECTION_WR_ASTID		0
930 #define M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
931 #define V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
932     ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
933 #define G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
934     (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
935 
936 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
937 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
938 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
939     ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
940 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
941     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
942      M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
943 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
944     V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
945 
946 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
947 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
948 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
949     ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
950 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
951     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
952      M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
953 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
954     V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
955 
956 enum fw_flowc_mnem_tcpstate {
957 	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0, /* illegal */
958 	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1, /* illegal */
959 	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2, /* illegal */
960 	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
961 	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
962 	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
963 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6, /* haven't gotten ACK for FIN and
964 					      * will resend FIN - equiv ESTAB
965 					      */
966 	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7, /* haven't gotten ACK for FIN and
967 					      * will resend FIN but have
968 					      * received FIN
969 					      */
970 	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8, /* haven't gotten ACK for FIN and
971 					      * will resend FIN but have
972 					      * received FIN
973 					      */
974 	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9, /* sent FIN and got FIN + ACK,
975 					      * waiting for FIN
976 					      */
977 	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10, /* not expected */
978 };
979 
980 enum fw_flowc_mnem_eostate {
981 	FW_FLOWC_MNEM_EOSTATE_CLOSED	= 0, /* illegal */
982 	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
983 	FW_FLOWC_MNEM_EOSTATE_CLOSING	= 2, /* graceful close, after sending
984 					      * outstanding payload
985 					      */
986 	FW_FLOWC_MNEM_EOSTATE_ABORTING	= 3, /* immediate close, after
987 					      * discarding outstanding payload
988 					      */
989 };
990 
991 enum fw_flowc_mnem {
992 	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
993 	FW_FLOWC_MNEM_CH		= 1,
994 	FW_FLOWC_MNEM_PORT		= 2,
995 	FW_FLOWC_MNEM_IQID		= 3,
996 	FW_FLOWC_MNEM_SNDNXT		= 4,
997 	FW_FLOWC_MNEM_RCVNXT		= 5,
998 	FW_FLOWC_MNEM_SNDBUF		= 6,
999 	FW_FLOWC_MNEM_MSS		= 7,
1000 	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
1001 	FW_FLOWC_MNEM_TCPSTATE		= 9,
1002 	FW_FLOWC_MNEM_EOSTATE		= 10,
1003 	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
1004 	FW_FLOWC_MNEM_DCBPRIO		= 12,
1005 	FW_FLOWC_MNEM_SND_SCALE		= 13,
1006 	FW_FLOWC_MNEM_RCV_SCALE		= 14,
1007 	FW_FLOWC_MNEM_ULP_MODE		= 15,
1008 	FW_FLOWC_MNEM_MAX		= 16,
1009 };
1010 
1011 struct fw_flowc_mnemval {
1012 	__u8   mnemonic;
1013 	__u8   r4[3];
1014 	__be32 val;
1015 };
1016 
1017 struct fw_flowc_wr {
1018 	__be32 op_to_nparams;
1019 	__be32 flowid_len16;
1020 #ifndef C99_NOT_SUPPORTED
1021 	struct fw_flowc_mnemval mnemval[0];
1022 #endif
1023 };
1024 
1025 #define S_FW_FLOWC_WR_NPARAMS		0
1026 #define M_FW_FLOWC_WR_NPARAMS		0xff
1027 #define V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
1028 #define G_FW_FLOWC_WR_NPARAMS(x)	\
1029     (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1030 
1031 struct fw_ofld_tx_data_wr {
1032 	__be32 op_to_immdlen;
1033 	__be32 flowid_len16;
1034 	__be32 plen;
1035 	__be32 lsodisable_to_flags;
1036 };
1037 
1038 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE		31
1039 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE		0x1
1040 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1041     ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1042 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1043     (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1044      M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1045 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE	V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1046 
1047 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD		30
1048 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD		0x1
1049 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1050     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1051 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1052     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1053 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD	V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1054 
1055 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	29
1056 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	0x1
1057 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1058     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1059 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1060     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1061      M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1062 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	\
1063     V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1064 
1065 #define S_FW_OFLD_TX_DATA_WR_FLAGS	0
1066 #define M_FW_OFLD_TX_DATA_WR_FLAGS	0xfffffff
1067 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1068 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x)	\
1069     (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1070 
1071 
1072 /* Use fw_ofld_tx_data_wr structure */
1073 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI		10
1074 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI		0x3fffff
1075 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1076     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1077 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1078     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1079 
1080 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	9
1081 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	0x1
1082 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1083     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1084 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1085     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1086      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1087 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO	\
1088     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1089 
1090 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	8
1091 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	0x1
1092 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1093     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1094 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1095     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1096      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1097 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI	\
1098     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1099 
1100 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		7
1101 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC		0x1
1102 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1103     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1104 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1105     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1106      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1107 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC	\
1108     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1109 
1110 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		6
1111 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC		0x1
1112 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1113     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1114 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1115     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1116      M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1117 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC	\
1118     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1119 
1120 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0
1121 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO		0x3f
1122 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1123     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1124 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1125     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1126 
1127 struct fw_cmd_wr {
1128 	__be32 op_dma;
1129 	__be32 len16_pkd;
1130 	__be64 cookie_daddr;
1131 };
1132 
1133 #define S_FW_CMD_WR_DMA		17
1134 #define M_FW_CMD_WR_DMA		0x1
1135 #define V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
1136 #define G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1137 #define F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
1138 
1139 struct fw_eth_tx_pkt_vm_wr {
1140 	__be32 op_immdlen;
1141 	__be32 equiq_to_len16;
1142 	__be32 r3[2];
1143 	__u8   ethmacdst[6];
1144 	__u8   ethmacsrc[6];
1145 	__be16 ethtype;
1146 	__be16 vlantci;
1147 };
1148 
1149 /******************************************************************************
1150  *   R I   W O R K   R E Q U E S T s
1151  **************************************/
1152 
1153 enum fw_ri_wr_opcode {
1154 	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
1155 	FW_RI_READ_REQ			= 0x1,
1156 	FW_RI_READ_RESP			= 0x2,
1157 	FW_RI_SEND			= 0x3,
1158 	FW_RI_SEND_WITH_INV		= 0x4,
1159 	FW_RI_SEND_WITH_SE		= 0x5,
1160 	FW_RI_SEND_WITH_SE_INV		= 0x6,
1161 	FW_RI_TERMINATE			= 0x7,
1162 	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
1163 	FW_RI_BIND_MW			= 0x9,
1164 	FW_RI_FAST_REGISTER		= 0xa,
1165 	FW_RI_LOCAL_INV			= 0xb,
1166 	FW_RI_QP_MODIFY			= 0xc,
1167 	FW_RI_BYPASS			= 0xd,
1168 	FW_RI_RECEIVE			= 0xe,
1169 #if 0
1170 	FW_RI_SEND_IMMEDIATE		= 0x8,
1171 	FW_RI_SEND_IMMEDIATE_WITH_SE	= 0x9,
1172 	FW_RI_ATOMIC_REQUEST		= 0xa,
1173 	FW_RI_ATOMIC_RESPONSE		= 0xb,
1174 
1175 	FW_RI_BIND_MW			= 0xc, /* CHELSIO RI specific ... */
1176 	FW_RI_FAST_REGISTER		= 0xd,
1177 	FW_RI_LOCAL_INV			= 0xe,
1178 #endif
1179 	FW_RI_SGE_EC_CR_RETURN		= 0xf
1180 };
1181 
1182 enum fw_ri_wr_flags {
1183 	FW_RI_COMPLETION_FLAG		= 0x01,
1184 	FW_RI_NOTIFICATION_FLAG		= 0x02,
1185 	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
1186 	FW_RI_READ_FENCE_FLAG		= 0x08,
1187 	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
1188 	FW_RI_RDMA_READ_INVALIDATE	= 0x20
1189 };
1190 
1191 enum fw_ri_mpa_attrs {
1192 	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
1193 	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
1194 	FW_RI_MPA_CRC_ENABLE		= 0x04,
1195 	FW_RI_MPA_IETF_ENABLE		= 0x08
1196 };
1197 
1198 enum fw_ri_qp_caps {
1199 	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
1200 	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
1201 	FW_RI_QP_BIND_ENABLE		= 0x04,
1202 	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
1203 	FW_RI_QP_STAG0_ENABLE		= 0x10,
1204 	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1205 };
1206 
1207 enum fw_ri_addr_type {
1208 	FW_RI_ZERO_BASED_TO		= 0x00,
1209 	FW_RI_VA_BASED_TO		= 0x01
1210 };
1211 
1212 enum fw_ri_mem_perms {
1213 	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
1214 	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
1215 	FW_RI_MEM_ACCESS_REM		= 0x03,
1216 	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
1217 	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
1218 	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
1219 };
1220 
1221 enum fw_ri_stag_type {
1222 	FW_RI_STAG_NSMR			= 0x00,
1223 	FW_RI_STAG_SMR			= 0x01,
1224 	FW_RI_STAG_MW			= 0x02,
1225 	FW_RI_STAG_MW_RELAXED		= 0x03
1226 };
1227 
1228 enum fw_ri_data_op {
1229 	FW_RI_DATA_IMMD			= 0x81,
1230 	FW_RI_DATA_DSGL			= 0x82,
1231 	FW_RI_DATA_ISGL			= 0x83
1232 };
1233 
1234 enum fw_ri_sgl_depth {
1235 	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
1236 	FW_RI_SGL_DEPTH_MAX_RQ		= 4
1237 };
1238 
1239 enum fw_ri_cqe_err {
1240 	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
1241 	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
1242 	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
1243 	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
1244 	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
1245 	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
1246 	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
1247 	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1248 	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1249 	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
1250 	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1251 	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B, /* pbl address out of bound : software error */
1252 	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
1253 	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
1254 	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
1255 	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
1256 	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
1257 	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
1258 	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
1259 	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
1260 	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
1261 	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
1262 	FW_RI_CQE_ERR_MO		= 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1263 	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
1264 	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
1265 	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
1266 	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E, /*  RQE address out of bound : software error */
1267 	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F  /* internel error (opcode mismatch) */
1268 
1269 };
1270 
1271 struct fw_ri_dsge_pair {
1272 	__be32	len[2];
1273 	__be64	addr[2];
1274 };
1275 
1276 struct fw_ri_dsgl {
1277 	__u8	op;
1278 	__u8	r1;
1279 	__be16	nsge;
1280 	__be32	len0;
1281 	__be64	addr0;
1282 #ifndef C99_NOT_SUPPORTED
1283 	struct fw_ri_dsge_pair sge[0];
1284 #endif
1285 };
1286 
1287 struct fw_ri_sge {
1288 	__be32 stag;
1289 	__be32 len;
1290 	__be64 to;
1291 };
1292 
1293 struct fw_ri_isgl {
1294 	__u8	op;
1295 	__u8	r1;
1296 	__be16	nsge;
1297 	__be32	r2;
1298 #ifndef C99_NOT_SUPPORTED
1299 	struct fw_ri_sge sge[0];
1300 #endif
1301 };
1302 
1303 struct fw_ri_immd {
1304 	__u8	op;
1305 	__u8	r1;
1306 	__be16	r2;
1307 	__be32	immdlen;
1308 #ifndef C99_NOT_SUPPORTED
1309 	__u8	data[0];
1310 #endif
1311 };
1312 
1313 struct fw_ri_tpte {
1314 	__be32 valid_to_pdid;
1315 	__be32 locread_to_qpid;
1316 	__be32 nosnoop_pbladdr;
1317 	__be32 len_lo;
1318 	__be32 va_hi;
1319 	__be32 va_lo_fbo;
1320 	__be32 dca_mwbcnt_pstag;
1321 	__be32 len_hi;
1322 };
1323 
1324 #define S_FW_RI_TPTE_VALID		31
1325 #define M_FW_RI_TPTE_VALID		0x1
1326 #define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
1327 #define G_FW_RI_TPTE_VALID(x)		\
1328     (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1329 #define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1330 
1331 #define S_FW_RI_TPTE_STAGKEY		23
1332 #define M_FW_RI_TPTE_STAGKEY		0xff
1333 #define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1334 #define G_FW_RI_TPTE_STAGKEY(x)		\
1335     (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1336 
1337 #define S_FW_RI_TPTE_STAGSTATE		22
1338 #define M_FW_RI_TPTE_STAGSTATE		0x1
1339 #define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1340 #define G_FW_RI_TPTE_STAGSTATE(x)	\
1341     (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1342 #define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1343 
1344 #define S_FW_RI_TPTE_STAGTYPE		20
1345 #define M_FW_RI_TPTE_STAGTYPE		0x3
1346 #define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1347 #define G_FW_RI_TPTE_STAGTYPE(x)	\
1348     (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1349 
1350 #define S_FW_RI_TPTE_PDID		0
1351 #define M_FW_RI_TPTE_PDID		0xfffff
1352 #define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1353 #define G_FW_RI_TPTE_PDID(x)		\
1354     (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1355 
1356 #define S_FW_RI_TPTE_PERM		28
1357 #define M_FW_RI_TPTE_PERM		0xf
1358 #define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1359 #define G_FW_RI_TPTE_PERM(x)		\
1360     (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1361 
1362 #define S_FW_RI_TPTE_REMINVDIS		27
1363 #define M_FW_RI_TPTE_REMINVDIS		0x1
1364 #define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1365 #define G_FW_RI_TPTE_REMINVDIS(x)	\
1366     (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1367 #define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1368 
1369 #define S_FW_RI_TPTE_ADDRTYPE		26
1370 #define M_FW_RI_TPTE_ADDRTYPE		1
1371 #define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1372 #define G_FW_RI_TPTE_ADDRTYPE(x)	\
1373     (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1374 #define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1375 
1376 #define S_FW_RI_TPTE_MWBINDEN		25
1377 #define M_FW_RI_TPTE_MWBINDEN		0x1
1378 #define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1379 #define G_FW_RI_TPTE_MWBINDEN(x)	\
1380     (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1381 #define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1382 
1383 #define S_FW_RI_TPTE_PS			20
1384 #define M_FW_RI_TPTE_PS			0x1f
1385 #define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1386 #define G_FW_RI_TPTE_PS(x)		\
1387     (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1388 
1389 #define S_FW_RI_TPTE_QPID		0
1390 #define M_FW_RI_TPTE_QPID		0xfffff
1391 #define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1392 #define G_FW_RI_TPTE_QPID(x)		\
1393     (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1394 
1395 #define S_FW_RI_TPTE_NOSNOOP		31
1396 #define M_FW_RI_TPTE_NOSNOOP		0x1
1397 #define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1398 #define G_FW_RI_TPTE_NOSNOOP(x)		\
1399     (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1400 #define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1401 
1402 #define S_FW_RI_TPTE_PBLADDR		0
1403 #define M_FW_RI_TPTE_PBLADDR		0x1fffffff
1404 #define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1405 #define G_FW_RI_TPTE_PBLADDR(x)		\
1406     (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1407 
1408 #define S_FW_RI_TPTE_DCA		24
1409 #define M_FW_RI_TPTE_DCA		0x1f
1410 #define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1411 #define G_FW_RI_TPTE_DCA(x)		\
1412     (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1413 
1414 #define S_FW_RI_TPTE_MWBCNT_PSTAG	0
1415 #define M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
1416 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1417     ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1418 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1419     (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1420 
1421 enum fw_ri_cqe_rxtx {
1422 	FW_RI_CQE_RXTX_RX = 0x0,
1423 	FW_RI_CQE_RXTX_TX = 0x1,
1424 };
1425 
1426 struct fw_ri_cqe {
1427 	union fw_ri_rxtx {
1428 		struct fw_ri_scqe {
1429 		__be32	qpid_n_stat_rxtx_type;
1430 		__be32	plen;
1431 		__be32	stag;
1432 		__be32	wrid;
1433 		} scqe;
1434 		struct fw_ri_rcqe {
1435 		__be32	qpid_n_stat_rxtx_type;
1436 		__be32	plen;
1437 		__be32	stag;
1438 		__be32	msn;
1439 		} rcqe;
1440 	} u;
1441 };
1442 
1443 #define S_FW_RI_CQE_QPID      12
1444 #define M_FW_RI_CQE_QPID      0xfffff
1445 #define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1446 #define G_FW_RI_CQE_QPID(x)   \
1447     (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1448 
1449 #define S_FW_RI_CQE_NOTIFY    10
1450 #define M_FW_RI_CQE_NOTIFY    0x1
1451 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1452 #define G_FW_RI_CQE_NOTIFY(x) \
1453     (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1454 
1455 #define S_FW_RI_CQE_STATUS    5
1456 #define M_FW_RI_CQE_STATUS    0x1f
1457 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1458 #define G_FW_RI_CQE_STATUS(x) \
1459     (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1460 
1461 
1462 #define S_FW_RI_CQE_RXTX      4
1463 #define M_FW_RI_CQE_RXTX      0x1
1464 #define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1465 #define G_FW_RI_CQE_RXTX(x)   \
1466     (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1467 
1468 #define S_FW_RI_CQE_TYPE      0
1469 #define M_FW_RI_CQE_TYPE      0xf
1470 #define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1471 #define G_FW_RI_CQE_TYPE(x)   \
1472     (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1473 
1474 enum fw_ri_res_type {
1475 	FW_RI_RES_TYPE_SQ,
1476 	FW_RI_RES_TYPE_RQ,
1477 	FW_RI_RES_TYPE_CQ,
1478 	FW_RI_RES_TYPE_SRQ,
1479 };
1480 
1481 enum fw_ri_res_op {
1482 	FW_RI_RES_OP_WRITE,
1483 	FW_RI_RES_OP_RESET,
1484 };
1485 
1486 struct fw_ri_res {
1487 	union fw_ri_restype {
1488 		struct fw_ri_res_sqrq {
1489 			__u8   restype;
1490 			__u8   op;
1491 			__be16 r3;
1492 			__be32 eqid;
1493 			__be32 r4[2];
1494 			__be32 fetchszm_to_iqid;
1495 			__be32 dcaen_to_eqsize;
1496 			__be64 eqaddr;
1497 		} sqrq;
1498 		struct fw_ri_res_cq {
1499 			__u8   restype;
1500 			__u8   op;
1501 			__be16 r3;
1502 			__be32 iqid;
1503 			__be32 r4[2];
1504 			__be32 iqandst_to_iqandstindex;
1505 			__be16 iqdroprss_to_iqesize;
1506 			__be16 iqsize;
1507 			__be64 iqaddr;
1508 			__be32 iqns_iqro;
1509 			__be32 r6_lo;
1510 			__be64 r7;
1511 		} cq;
1512 		struct fw_ri_res_srq {
1513 			__u8   restype;
1514 			__u8   op;
1515 			__be16 r3;
1516 			__be32 eqid;
1517 			__be32 r4[2];
1518 			__be32 fetchszm_to_iqid;
1519 			__be32 dcaen_to_eqsize;
1520 			__be64 eqaddr;
1521 			__be32 srqid;
1522 			__be32 pdid;
1523 			__be32 hwsrqsize;
1524 			__be32 hwsrqaddr;
1525 		} srq;
1526 	} u;
1527 };
1528 
1529 struct fw_ri_res_wr {
1530 	__be32 op_nres;
1531 	__be32 len16_pkd;
1532 	__u64  cookie;
1533 #ifndef C99_NOT_SUPPORTED
1534 	struct fw_ri_res res[0];
1535 #endif
1536 };
1537 
1538 #define S_FW_RI_RES_WR_VFN		8
1539 #define M_FW_RI_RES_WR_VFN		0xff
1540 #define V_FW_RI_RES_WR_VFN(x)		((x) << S_FW_RI_RES_WR_VFN)
1541 #define G_FW_RI_RES_WR_VFN(x)		\
1542     (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1543 
1544 #define S_FW_RI_RES_WR_NRES	0
1545 #define M_FW_RI_RES_WR_NRES	0xff
1546 #define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1547 #define G_FW_RI_RES_WR_NRES(x)	\
1548     (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1549 
1550 #define S_FW_RI_RES_WR_FETCHSZM		26
1551 #define M_FW_RI_RES_WR_FETCHSZM		0x1
1552 #define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1553 #define G_FW_RI_RES_WR_FETCHSZM(x)	\
1554     (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1555 #define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1556 
1557 #define S_FW_RI_RES_WR_STATUSPGNS	25
1558 #define M_FW_RI_RES_WR_STATUSPGNS	0x1
1559 #define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1560 #define G_FW_RI_RES_WR_STATUSPGNS(x)	\
1561     (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1562 #define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1563 
1564 #define S_FW_RI_RES_WR_STATUSPGRO	24
1565 #define M_FW_RI_RES_WR_STATUSPGRO	0x1
1566 #define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1567 #define G_FW_RI_RES_WR_STATUSPGRO(x)	\
1568     (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1569 #define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
1570 
1571 #define S_FW_RI_RES_WR_FETCHNS		23
1572 #define M_FW_RI_RES_WR_FETCHNS		0x1
1573 #define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
1574 #define G_FW_RI_RES_WR_FETCHNS(x)	\
1575     (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1576 #define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
1577 
1578 #define S_FW_RI_RES_WR_FETCHRO		22
1579 #define M_FW_RI_RES_WR_FETCHRO		0x1
1580 #define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
1581 #define G_FW_RI_RES_WR_FETCHRO(x)	\
1582     (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1583 #define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
1584 
1585 #define S_FW_RI_RES_WR_HOSTFCMODE	20
1586 #define M_FW_RI_RES_WR_HOSTFCMODE	0x3
1587 #define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1588 #define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
1589     (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1590 
1591 #define S_FW_RI_RES_WR_CPRIO	19
1592 #define M_FW_RI_RES_WR_CPRIO	0x1
1593 #define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
1594 #define G_FW_RI_RES_WR_CPRIO(x)	\
1595     (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1596 #define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
1597 
1598 #define S_FW_RI_RES_WR_ONCHIP		18
1599 #define M_FW_RI_RES_WR_ONCHIP		0x1
1600 #define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
1601 #define G_FW_RI_RES_WR_ONCHIP(x)	\
1602     (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1603 #define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
1604 
1605 #define S_FW_RI_RES_WR_PCIECHN		16
1606 #define M_FW_RI_RES_WR_PCIECHN		0x3
1607 #define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
1608 #define G_FW_RI_RES_WR_PCIECHN(x)	\
1609     (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1610 
1611 #define S_FW_RI_RES_WR_IQID	0
1612 #define M_FW_RI_RES_WR_IQID	0xffff
1613 #define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
1614 #define G_FW_RI_RES_WR_IQID(x)	\
1615     (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1616 
1617 #define S_FW_RI_RES_WR_DCAEN	31
1618 #define M_FW_RI_RES_WR_DCAEN	0x1
1619 #define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
1620 #define G_FW_RI_RES_WR_DCAEN(x)	\
1621     (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1622 #define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
1623 
1624 #define S_FW_RI_RES_WR_DCACPU		26
1625 #define M_FW_RI_RES_WR_DCACPU		0x1f
1626 #define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
1627 #define G_FW_RI_RES_WR_DCACPU(x)	\
1628     (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1629 
1630 #define S_FW_RI_RES_WR_FBMIN	23
1631 #define M_FW_RI_RES_WR_FBMIN	0x7
1632 #define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
1633 #define G_FW_RI_RES_WR_FBMIN(x)	\
1634     (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1635 
1636 #define S_FW_RI_RES_WR_FBMAX	20
1637 #define M_FW_RI_RES_WR_FBMAX	0x7
1638 #define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
1639 #define G_FW_RI_RES_WR_FBMAX(x)	\
1640     (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1641 
1642 #define S_FW_RI_RES_WR_CIDXFTHRESHO	19
1643 #define M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
1644 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1645 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
1646     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1647 #define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1648 
1649 #define S_FW_RI_RES_WR_CIDXFTHRESH	16
1650 #define M_FW_RI_RES_WR_CIDXFTHRESH	0x7
1651 #define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1652 #define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
1653     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1654 
1655 #define S_FW_RI_RES_WR_EQSIZE		0
1656 #define M_FW_RI_RES_WR_EQSIZE		0xffff
1657 #define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
1658 #define G_FW_RI_RES_WR_EQSIZE(x)	\
1659     (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1660 
1661 #define S_FW_RI_RES_WR_IQANDST		15
1662 #define M_FW_RI_RES_WR_IQANDST		0x1
1663 #define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
1664 #define G_FW_RI_RES_WR_IQANDST(x)	\
1665     (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1666 #define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
1667 
1668 #define S_FW_RI_RES_WR_IQANUS		14
1669 #define M_FW_RI_RES_WR_IQANUS		0x1
1670 #define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
1671 #define G_FW_RI_RES_WR_IQANUS(x)	\
1672     (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1673 #define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
1674 
1675 #define S_FW_RI_RES_WR_IQANUD		12
1676 #define M_FW_RI_RES_WR_IQANUD		0x3
1677 #define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
1678 #define G_FW_RI_RES_WR_IQANUD(x)	\
1679     (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1680 
1681 #define S_FW_RI_RES_WR_IQANDSTINDEX	0
1682 #define M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
1683 #define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1684 #define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
1685     (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1686 
1687 #define S_FW_RI_RES_WR_IQDROPRSS	15
1688 #define M_FW_RI_RES_WR_IQDROPRSS	0x1
1689 #define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
1690 #define G_FW_RI_RES_WR_IQDROPRSS(x)	\
1691     (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1692 #define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
1693 
1694 #define S_FW_RI_RES_WR_IQGTSMODE	14
1695 #define M_FW_RI_RES_WR_IQGTSMODE	0x1
1696 #define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
1697 #define G_FW_RI_RES_WR_IQGTSMODE(x)	\
1698     (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1699 #define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
1700 
1701 #define S_FW_RI_RES_WR_IQPCIECH		12
1702 #define M_FW_RI_RES_WR_IQPCIECH		0x3
1703 #define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
1704 #define G_FW_RI_RES_WR_IQPCIECH(x)	\
1705     (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1706 
1707 #define S_FW_RI_RES_WR_IQDCAEN		11
1708 #define M_FW_RI_RES_WR_IQDCAEN		0x1
1709 #define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
1710 #define G_FW_RI_RES_WR_IQDCAEN(x)	\
1711     (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1712 #define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
1713 
1714 #define S_FW_RI_RES_WR_IQDCACPU		6
1715 #define M_FW_RI_RES_WR_IQDCACPU		0x1f
1716 #define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
1717 #define G_FW_RI_RES_WR_IQDCACPU(x)	\
1718     (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1719 
1720 #define S_FW_RI_RES_WR_IQINTCNTTHRESH		4
1721 #define M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
1722 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1723     ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1724 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
1725     (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1726 
1727 #define S_FW_RI_RES_WR_IQO	3
1728 #define M_FW_RI_RES_WR_IQO	0x1
1729 #define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
1730 #define G_FW_RI_RES_WR_IQO(x)	\
1731     (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1732 #define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
1733 
1734 #define S_FW_RI_RES_WR_IQCPRIO		2
1735 #define M_FW_RI_RES_WR_IQCPRIO		0x1
1736 #define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
1737 #define G_FW_RI_RES_WR_IQCPRIO(x)	\
1738     (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1739 #define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
1740 
1741 #define S_FW_RI_RES_WR_IQESIZE		0
1742 #define M_FW_RI_RES_WR_IQESIZE		0x3
1743 #define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
1744 #define G_FW_RI_RES_WR_IQESIZE(x)	\
1745     (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1746 
1747 #define S_FW_RI_RES_WR_IQNS	31
1748 #define M_FW_RI_RES_WR_IQNS	0x1
1749 #define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
1750 #define G_FW_RI_RES_WR_IQNS(x)	\
1751     (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1752 #define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
1753 
1754 #define S_FW_RI_RES_WR_IQRO	30
1755 #define M_FW_RI_RES_WR_IQRO	0x1
1756 #define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
1757 #define G_FW_RI_RES_WR_IQRO(x)	\
1758     (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1759 #define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
1760 
1761 struct fw_ri_rdma_write_wr {
1762 	__u8   opcode;
1763 	__u8   flags;
1764 	__u16  wrid;
1765 	__u8   r1[3];
1766 	__u8   len16;
1767 	__be64 r2;
1768 	__be32 plen;
1769 	__be32 stag_sink;
1770 	__be64 to_sink;
1771 #ifndef C99_NOT_SUPPORTED
1772 	union {
1773 		struct fw_ri_immd immd_src[0];
1774 		struct fw_ri_isgl isgl_src[0];
1775 	} u;
1776 #endif
1777 };
1778 
1779 struct fw_ri_send_wr {
1780 	__u8   opcode;
1781 	__u8   flags;
1782 	__u16  wrid;
1783 	__u8   r1[3];
1784 	__u8   len16;
1785 	__be32 sendop_pkd;
1786 	__be32 stag_inv;
1787 	__be32 plen;
1788 	__be32 r3;
1789 	__be64 r4;
1790 #ifndef C99_NOT_SUPPORTED
1791 	union {
1792 		struct fw_ri_immd immd_src[0];
1793 		struct fw_ri_isgl isgl_src[0];
1794 	} u;
1795 #endif
1796 };
1797 
1798 #define S_FW_RI_SEND_WR_SENDOP		0
1799 #define M_FW_RI_SEND_WR_SENDOP		0xf
1800 #define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
1801 #define G_FW_RI_SEND_WR_SENDOP(x)	\
1802     (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1803 
1804 struct fw_ri_rdma_read_wr {
1805 	__u8   opcode;
1806 	__u8   flags;
1807 	__u16  wrid;
1808 	__u8   r1[3];
1809 	__u8   len16;
1810 	__be64 r2;
1811 	__be32 stag_sink;
1812 	__be32 to_sink_hi;
1813 	__be32 to_sink_lo;
1814 	__be32 plen;
1815 	__be32 stag_src;
1816 	__be32 to_src_hi;
1817 	__be32 to_src_lo;
1818 	__be32 r5;
1819 };
1820 
1821 struct fw_ri_recv_wr {
1822 	__u8   opcode;
1823 	__u8   r1;
1824 	__u16  wrid;
1825 	__u8   r2[3];
1826 	__u8   len16;
1827 	struct fw_ri_isgl isgl;
1828 };
1829 
1830 struct fw_ri_bind_mw_wr {
1831 	__u8   opcode;
1832 	__u8   flags;
1833 	__u16  wrid;
1834 	__u8   r1[3];
1835 	__u8   len16;
1836 	__u8   qpbinde_to_dcacpu;
1837 	__u8   pgsz_shift;
1838 	__u8   addr_type;
1839 	__u8   mem_perms;
1840 	__be32 stag_mr;
1841 	__be32 stag_mw;
1842 	__be32 r3;
1843 	__be64 len_mw;
1844 	__be64 va_fbo;
1845 	__be64 r4;
1846 };
1847 
1848 #define S_FW_RI_BIND_MW_WR_QPBINDE	6
1849 #define M_FW_RI_BIND_MW_WR_QPBINDE	0x1
1850 #define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1851 #define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
1852     (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1853 #define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1854 
1855 #define S_FW_RI_BIND_MW_WR_NS		5
1856 #define M_FW_RI_BIND_MW_WR_NS		0x1
1857 #define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
1858 #define G_FW_RI_BIND_MW_WR_NS(x)	\
1859     (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1860 #define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
1861 
1862 #define S_FW_RI_BIND_MW_WR_DCACPU	0
1863 #define M_FW_RI_BIND_MW_WR_DCACPU	0x1f
1864 #define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1865 #define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
1866     (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1867 
1868 struct fw_ri_fr_nsmr_wr {
1869 	__u8   opcode;
1870 	__u8   flags;
1871 	__u16  wrid;
1872 	__u8   r1[3];
1873 	__u8   len16;
1874 	__u8   qpbinde_to_dcacpu;
1875 	__u8   pgsz_shift;
1876 	__u8   addr_type;
1877 	__u8   mem_perms;
1878 	__be32 stag;
1879 	__be32 len_hi;
1880 	__be32 len_lo;
1881 	__be32 va_hi;
1882 	__be32 va_lo_fbo;
1883 };
1884 
1885 #define S_FW_RI_FR_NSMR_WR_QPBINDE	6
1886 #define M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
1887 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1888 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
1889     (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1890 #define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1891 
1892 #define S_FW_RI_FR_NSMR_WR_NS		5
1893 #define M_FW_RI_FR_NSMR_WR_NS		0x1
1894 #define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
1895 #define G_FW_RI_FR_NSMR_WR_NS(x)	\
1896     (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1897 #define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
1898 
1899 #define S_FW_RI_FR_NSMR_WR_DCACPU	0
1900 #define M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
1901 #define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1902 #define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
1903     (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1904 
1905 struct fw_ri_fr_nsmr_tpte_wr {
1906 	__u8   opcode;
1907 	__u8   flags;
1908 	__u16  wrid;
1909 	__u8   r1[3];
1910 	__u8   len16;
1911 	__be32 r2;
1912 	__be32 stag;
1913 	struct fw_ri_tpte tpte;
1914 	__be64 pbl[2];
1915 };
1916 
1917 struct fw_ri_inv_lstag_wr {
1918 	__u8   opcode;
1919 	__u8   flags;
1920 	__u16  wrid;
1921 	__u8   r1[3];
1922 	__u8   len16;
1923 	__be32 r2;
1924 	__be32 stag_inv;
1925 };
1926 
1927 struct fw_ri_send_immediate_wr {
1928 	__u8   opcode;
1929 	__u8   flags;
1930 	__u16  wrid;
1931 	__u8   r1[3];
1932 	__u8   len16;
1933 	__be32 sendimmop_pkd;
1934 	__be32 r3;
1935 	__be32 plen;
1936 	__be32 r4;
1937 	__be64 r5;
1938 #ifndef C99_NOT_SUPPORTED
1939 	struct fw_ri_immd immd_src[0];
1940 #endif
1941 };
1942 
1943 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
1944 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
1945 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1946     ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1947 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
1948     (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1949      M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1950 
1951 enum fw_ri_atomic_op {
1952 	FW_RI_ATOMIC_OP_FETCHADD,
1953 	FW_RI_ATOMIC_OP_SWAP,
1954 	FW_RI_ATOMIC_OP_CMDSWAP,
1955 };
1956 
1957 struct fw_ri_atomic_wr {
1958 	__u8   opcode;
1959 	__u8   flags;
1960 	__u16  wrid;
1961 	__u8   r1[3];
1962 	__u8   len16;
1963 	__be32 atomicop_pkd;
1964 	__be64 r3;
1965 	__be32 aopcode_pkd;
1966 	__be32 reqid;
1967 	__be32 stag;
1968 	__be32 to_hi;
1969 	__be32 to_lo;
1970 	__be32 addswap_data_hi;
1971 	__be32 addswap_data_lo;
1972 	__be32 addswap_mask_hi;
1973 	__be32 addswap_mask_lo;
1974 	__be32 compare_data_hi;
1975 	__be32 compare_data_lo;
1976 	__be32 compare_mask_hi;
1977 	__be32 compare_mask_lo;
1978 	__be32 r5;
1979 };
1980 
1981 #define S_FW_RI_ATOMIC_WR_ATOMICOP	0
1982 #define M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
1983 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1984 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
1985     (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1986 
1987 #define S_FW_RI_ATOMIC_WR_AOPCODE	0
1988 #define M_FW_RI_ATOMIC_WR_AOPCODE	0xf
1989 #define V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1990 #define G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
1991     (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1992 
1993 enum fw_ri_type {
1994 	FW_RI_TYPE_INIT,
1995 	FW_RI_TYPE_FINI,
1996 	FW_RI_TYPE_TERMINATE
1997 };
1998 
1999 enum fw_ri_init_p2ptype {
2000 	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
2001 	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
2002 	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
2003 	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
2004 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
2005 	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
2006 	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
2007 };
2008 
2009 enum fw_ri_init_rqeqid_srq {
2010 	FW_RI_INIT_RQEQID_SRQ			= 1U << 31,
2011 };
2012 
2013 struct fw_ri_wr {
2014 	__be32 op_compl;
2015 	__be32 flowid_len16;
2016 	__u64  cookie;
2017 	union fw_ri {
2018 		struct fw_ri_init {
2019 			__u8   type;
2020 			__u8   mpareqbit_p2ptype;
2021 			__u8   r4[2];
2022 			__u8   mpa_attrs;
2023 			__u8   qp_caps;
2024 			__be16 nrqe;
2025 			__be32 pdid;
2026 			__be32 qpid;
2027 			__be32 sq_eqid;
2028 			__be32 rq_eqid;
2029 			__be32 scqid;
2030 			__be32 rcqid;
2031 			__be32 ord_max;
2032 			__be32 ird_max;
2033 			__be32 iss;
2034 			__be32 irs;
2035 			__be32 hwrqsize;
2036 			__be32 hwrqaddr;
2037 			__be64 r5;
2038 			union fw_ri_init_p2p {
2039 				struct fw_ri_rdma_write_wr write;
2040 				struct fw_ri_rdma_read_wr read;
2041 				struct fw_ri_send_wr send;
2042 			} u;
2043 		} init;
2044 		struct fw_ri_fini {
2045 			__u8   type;
2046 			__u8   r3[7];
2047 			__be64 r4;
2048 		} fini;
2049 		struct fw_ri_terminate {
2050 			__u8   type;
2051 			__u8   r3[3];
2052 			__be32 immdlen;
2053 			__u8   termmsg[40];
2054 		} terminate;
2055 	} u;
2056 };
2057 
2058 #define S_FW_RI_WR_MPAREQBIT	7
2059 #define M_FW_RI_WR_MPAREQBIT	0x1
2060 #define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
2061 #define G_FW_RI_WR_MPAREQBIT(x)	\
2062     (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2063 #define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
2064 
2065 #define S_FW_RI_WR_0BRRBIT	6
2066 #define M_FW_RI_WR_0BRRBIT	0x1
2067 #define V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
2068 #define G_FW_RI_WR_0BRRBIT(x)	\
2069     (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2070 #define F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
2071 
2072 #define S_FW_RI_WR_P2PTYPE	0
2073 #define M_FW_RI_WR_P2PTYPE	0xf
2074 #define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
2075 #define G_FW_RI_WR_P2PTYPE(x)	\
2076     (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2077 
2078 /******************************************************************************
2079  *  F O i S C S I   W O R K R E Q U E S T s
2080  *********************************************/
2081 
2082 #define	FW_FOISCSI_NAME_MAX_LEN		224
2083 #define	FW_FOISCSI_ALIAS_MAX_LEN	224
2084 #define FW_FOISCSI_CHAP_SEC_MAX_LEN	128
2085 #define	FW_FOISCSI_INIT_NODE_MAX	8
2086 
2087 enum fw_chnet_ifconf_wr_subop {
2088 	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2089 
2090 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2091 	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2092 
2093 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2094 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2095 
2096 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2097 	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2098 
2099 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2100 	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2101 
2102 	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2103 	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2104 
2105 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2106 	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2107 
2108 	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2109 	FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2110 
2111 	FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2112 	FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2113 	FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2114 
2115 	FW_CHNET_IFCONF_WR_SUBOP_MAX,
2116 };
2117 
2118 struct fw_chnet_ifconf_wr {
2119 	__be32 op_compl;
2120 	__be32 flowid_len16;
2121 	__be64 cookie;
2122 	__be32 if_flowid;
2123 	__u8   idx;
2124 	__u8   subop;
2125 	__u8   retval;
2126 	__u8   r2;
2127 	__be64 r3;
2128 	struct fw_chnet_ifconf_params {
2129 		__be32 r0;
2130 		__be16 vlanid;
2131 		__be16 mtu;
2132 		union fw_chnet_ifconf_addr_type {
2133 			struct fw_chnet_ifconf_ipv4 {
2134 				__be32 addr;
2135 				__be32 mask;
2136 				__be32 router;
2137 				__be32 r0;
2138 				__be64 r1;
2139 			} ipv4;
2140 			struct fw_chnet_ifconf_ipv6 {
2141 				__u8   prefix_len;
2142 				__u8   r0;
2143 				__be16 r1;
2144 				__be32 r2;
2145 				__be64 addr_hi;
2146 				__be64 addr_lo;
2147 				__be64 router_hi;
2148 				__be64 router_lo;
2149 			} ipv6;
2150 		} in_attr;
2151 	} param;
2152 };
2153 
2154 enum fw_foiscsi_node_type {
2155 	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2156 	FW_FOISCSI_NODE_TYPE_TARGET,
2157 };
2158 
2159 enum fw_foiscsi_session_type {
2160 	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2161 	FW_FOISCSI_SESSION_TYPE_NORMAL,
2162 };
2163 
2164 enum fw_foiscsi_auth_policy {
2165 	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2166 	FW_FOISCSI_AUTH_POLICY_MUTUAL,
2167 };
2168 
2169 enum fw_foiscsi_auth_method {
2170 	FW_FOISCSI_AUTH_METHOD_NONE = 0,
2171 	FW_FOISCSI_AUTH_METHOD_CHAP,
2172 	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2173 	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2174 };
2175 
2176 enum fw_foiscsi_digest_type {
2177 	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2178 	FW_FOISCSI_DIGEST_TYPE_CRC32,
2179 	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2180 	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2181 };
2182 
2183 enum fw_foiscsi_wr_subop {
2184 	FW_FOISCSI_WR_SUBOP_ADD = 1,
2185 	FW_FOISCSI_WR_SUBOP_DEL = 2,
2186 	FW_FOISCSI_WR_SUBOP_MOD = 4,
2187 };
2188 
2189 enum fw_foiscsi_ctrl_state {
2190 	FW_FOISCSI_CTRL_STATE_FREE = 0,
2191 	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2192 	FW_FOISCSI_CTRL_STATE_FAILED,
2193 	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2194 	FW_FOISCSI_CTRL_STATE_REDIRECT,
2195 };
2196 
2197 struct fw_rdev_wr {
2198 	__be32 op_to_immdlen;
2199 	__be32 alloc_to_len16;
2200 	__be64 cookie;
2201 	__u8   protocol;
2202 	__u8   event_cause;
2203 	__u8   cur_state;
2204 	__u8   prev_state;
2205 	__be32 flags_to_assoc_flowid;
2206 	union rdev_entry {
2207 		struct fcoe_rdev_entry {
2208 			__be32 flowid;
2209 			__u8   protocol;
2210 			__u8   event_cause;
2211 			__u8   flags;
2212 			__u8   rjt_reason;
2213 			__u8   cur_login_st;
2214 			__u8   prev_login_st;
2215 			__be16 rcv_fr_sz;
2216 			__u8   rd_xfer_rdy_to_rport_type;
2217 			__u8   vft_to_qos;
2218 			__u8   org_proc_assoc_to_acc_rsp_code;
2219 			__u8   enh_disc_to_tgt;
2220 			__u8   wwnn[8];
2221 			__u8   wwpn[8];
2222 			__be16 iqid;
2223 			__u8   fc_oui[3];
2224 			__u8   r_id[3];
2225 		} fcoe_rdev;
2226 		struct iscsi_rdev_entry {
2227 			__be32 flowid;
2228 			__u8   protocol;
2229 			__u8   event_cause;
2230 			__u8   flags;
2231 			__u8   r3;
2232 			__be16 iscsi_opts;
2233 			__be16 tcp_opts;
2234 			__be16 ip_opts;
2235 			__be16 max_rcv_len;
2236 			__be16 max_snd_len;
2237 			__be16 first_brst_len;
2238 			__be16 max_brst_len;
2239 			__be16 r4;
2240 			__be16 def_time2wait;
2241 			__be16 def_time2ret;
2242 			__be16 nop_out_intrvl;
2243 			__be16 non_scsi_to;
2244 			__be16 isid;
2245 			__be16 tsid;
2246 			__be16 port;
2247 			__be16 tpgt;
2248 			__u8   r5[6];
2249 			__be16 iqid;
2250 		} iscsi_rdev;
2251 	} u;
2252 };
2253 
2254 #define S_FW_RDEV_WR_IMMDLEN	0
2255 #define M_FW_RDEV_WR_IMMDLEN	0xff
2256 #define V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
2257 #define G_FW_RDEV_WR_IMMDLEN(x)	\
2258     (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2259 
2260 #define S_FW_RDEV_WR_ALLOC	31
2261 #define M_FW_RDEV_WR_ALLOC	0x1
2262 #define V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
2263 #define G_FW_RDEV_WR_ALLOC(x)	\
2264     (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2265 #define F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
2266 
2267 #define S_FW_RDEV_WR_FREE	30
2268 #define M_FW_RDEV_WR_FREE	0x1
2269 #define V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
2270 #define G_FW_RDEV_WR_FREE(x)	\
2271     (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2272 #define F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
2273 
2274 #define S_FW_RDEV_WR_MODIFY	29
2275 #define M_FW_RDEV_WR_MODIFY	0x1
2276 #define V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
2277 #define G_FW_RDEV_WR_MODIFY(x)	\
2278     (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2279 #define F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
2280 
2281 #define S_FW_RDEV_WR_FLOWID	8
2282 #define M_FW_RDEV_WR_FLOWID	0xfffff
2283 #define V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
2284 #define G_FW_RDEV_WR_FLOWID(x)	\
2285     (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2286 
2287 #define S_FW_RDEV_WR_LEN16	0
2288 #define M_FW_RDEV_WR_LEN16	0xff
2289 #define V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
2290 #define G_FW_RDEV_WR_LEN16(x)	\
2291     (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2292 
2293 #define S_FW_RDEV_WR_FLAGS	24
2294 #define M_FW_RDEV_WR_FLAGS	0xff
2295 #define V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
2296 #define G_FW_RDEV_WR_FLAGS(x)	\
2297     (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2298 
2299 #define S_FW_RDEV_WR_GET_NEXT		20
2300 #define M_FW_RDEV_WR_GET_NEXT		0xf
2301 #define V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
2302 #define G_FW_RDEV_WR_GET_NEXT(x)	\
2303     (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2304 
2305 #define S_FW_RDEV_WR_ASSOC_FLOWID	0
2306 #define M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
2307 #define V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2308 #define G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
2309     (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2310 
2311 #define S_FW_RDEV_WR_RJT	7
2312 #define M_FW_RDEV_WR_RJT	0x1
2313 #define V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
2314 #define G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2315 #define F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
2316 
2317 #define S_FW_RDEV_WR_REASON	0
2318 #define M_FW_RDEV_WR_REASON	0x7f
2319 #define V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
2320 #define G_FW_RDEV_WR_REASON(x)	\
2321     (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2322 
2323 #define S_FW_RDEV_WR_RD_XFER_RDY	7
2324 #define M_FW_RDEV_WR_RD_XFER_RDY	0x1
2325 #define V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2326 #define G_FW_RDEV_WR_RD_XFER_RDY(x)	\
2327     (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2328 #define F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
2329 
2330 #define S_FW_RDEV_WR_WR_XFER_RDY	6
2331 #define M_FW_RDEV_WR_WR_XFER_RDY	0x1
2332 #define V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2333 #define G_FW_RDEV_WR_WR_XFER_RDY(x)	\
2334     (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2335 #define F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
2336 
2337 #define S_FW_RDEV_WR_FC_SP	5
2338 #define M_FW_RDEV_WR_FC_SP	0x1
2339 #define V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
2340 #define G_FW_RDEV_WR_FC_SP(x)	\
2341     (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2342 #define F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
2343 
2344 #define S_FW_RDEV_WR_RPORT_TYPE		0
2345 #define M_FW_RDEV_WR_RPORT_TYPE		0x1f
2346 #define V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
2347 #define G_FW_RDEV_WR_RPORT_TYPE(x)	\
2348     (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2349 
2350 #define S_FW_RDEV_WR_VFT	7
2351 #define M_FW_RDEV_WR_VFT	0x1
2352 #define V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
2353 #define G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2354 #define F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
2355 
2356 #define S_FW_RDEV_WR_NPIV	6
2357 #define M_FW_RDEV_WR_NPIV	0x1
2358 #define V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
2359 #define G_FW_RDEV_WR_NPIV(x)	\
2360     (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2361 #define F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
2362 
2363 #define S_FW_RDEV_WR_CLASS	4
2364 #define M_FW_RDEV_WR_CLASS	0x3
2365 #define V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
2366 #define G_FW_RDEV_WR_CLASS(x)	\
2367     (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2368 
2369 #define S_FW_RDEV_WR_SEQ_DEL	3
2370 #define M_FW_RDEV_WR_SEQ_DEL	0x1
2371 #define V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
2372 #define G_FW_RDEV_WR_SEQ_DEL(x)	\
2373     (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2374 #define F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
2375 
2376 #define S_FW_RDEV_WR_PRIO_PREEMP	2
2377 #define M_FW_RDEV_WR_PRIO_PREEMP	0x1
2378 #define V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2379 #define G_FW_RDEV_WR_PRIO_PREEMP(x)	\
2380     (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2381 #define F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
2382 
2383 #define S_FW_RDEV_WR_PREF	1
2384 #define M_FW_RDEV_WR_PREF	0x1
2385 #define V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
2386 #define G_FW_RDEV_WR_PREF(x)	\
2387     (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2388 #define F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
2389 
2390 #define S_FW_RDEV_WR_QOS	0
2391 #define M_FW_RDEV_WR_QOS	0x1
2392 #define V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
2393 #define G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2394 #define F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
2395 
2396 #define S_FW_RDEV_WR_ORG_PROC_ASSOC	7
2397 #define M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
2398 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2399 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
2400     (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2401 #define F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2402 
2403 #define S_FW_RDEV_WR_RSP_PROC_ASSOC	6
2404 #define M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
2405 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2406 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
2407     (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2408 #define F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2409 
2410 #define S_FW_RDEV_WR_IMAGE_PAIR		5
2411 #define M_FW_RDEV_WR_IMAGE_PAIR		0x1
2412 #define V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2413 #define G_FW_RDEV_WR_IMAGE_PAIR(x)	\
2414     (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2415 #define F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
2416 
2417 #define S_FW_RDEV_WR_ACC_RSP_CODE	0
2418 #define M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
2419 #define V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2420 #define G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
2421     (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2422 
2423 #define S_FW_RDEV_WR_ENH_DISC		7
2424 #define M_FW_RDEV_WR_ENH_DISC		0x1
2425 #define V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
2426 #define G_FW_RDEV_WR_ENH_DISC(x)	\
2427     (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2428 #define F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
2429 
2430 #define S_FW_RDEV_WR_REC	6
2431 #define M_FW_RDEV_WR_REC	0x1
2432 #define V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
2433 #define G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2434 #define F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
2435 
2436 #define S_FW_RDEV_WR_TASK_RETRY_ID	5
2437 #define M_FW_RDEV_WR_TASK_RETRY_ID	0x1
2438 #define V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2439 #define G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
2440     (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2441 #define F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2442 
2443 #define S_FW_RDEV_WR_RETRY	4
2444 #define M_FW_RDEV_WR_RETRY	0x1
2445 #define V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
2446 #define G_FW_RDEV_WR_RETRY(x)	\
2447     (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2448 #define F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
2449 
2450 #define S_FW_RDEV_WR_CONF_CMPL		3
2451 #define M_FW_RDEV_WR_CONF_CMPL		0x1
2452 #define V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
2453 #define G_FW_RDEV_WR_CONF_CMPL(x)	\
2454     (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2455 #define F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
2456 
2457 #define S_FW_RDEV_WR_DATA_OVLY		2
2458 #define M_FW_RDEV_WR_DATA_OVLY		0x1
2459 #define V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
2460 #define G_FW_RDEV_WR_DATA_OVLY(x)	\
2461     (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2462 #define F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
2463 
2464 #define S_FW_RDEV_WR_INI	1
2465 #define M_FW_RDEV_WR_INI	0x1
2466 #define V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
2467 #define G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2468 #define F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
2469 
2470 #define S_FW_RDEV_WR_TGT	0
2471 #define M_FW_RDEV_WR_TGT	0x1
2472 #define V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
2473 #define G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2474 #define F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
2475 
2476 struct fw_foiscsi_node_wr {
2477 	__be32 op_to_immdlen;
2478 	__be32 flowid_len16;
2479 	__u64  cookie;
2480 	__u8   subop;
2481 	__u8   status;
2482 	__u8   alias_len;
2483 	__u8   iqn_len;
2484 	__be32 node_flowid;
2485 	__be16 nodeid;
2486 	__be16 login_retry;
2487 	__be16 retry_timeout;
2488 	__be16 r3;
2489 	__u8   iqn[224];
2490 	__u8   alias[224];
2491 };
2492 
2493 #define S_FW_FOISCSI_NODE_WR_IMMDLEN	0
2494 #define M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
2495 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2496 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
2497     (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2498 
2499 struct fw_foiscsi_ctrl_wr {
2500 	__be32 op_compl;
2501 	__be32 flowid_len16;
2502 	__u64  cookie;
2503 	__u8   subop;
2504 	__u8   status;
2505 	__u8   ctrl_state;
2506 	__u8   io_state;
2507 	__be32 node_id;
2508 	__be32 ctrl_id;
2509 	__be32 io_id;
2510 	struct fw_foiscsi_sess_attr {
2511 		__be32 sess_type_to_erl;
2512 		__be16 max_conn;
2513 		__be16 max_r2t;
2514 		__be16 time2wait;
2515 		__be16 time2retain;
2516 		__be32 max_burst;
2517 		__be32 first_burst;
2518 		__be32 r1;
2519 	} sess_attr;
2520 	struct fw_foiscsi_conn_attr {
2521 		__be32 hdigest_to_ddp_pgsz;
2522 		__be32 max_rcv_dsl;
2523 		__be32 ping_tmo;
2524 		__be16 dst_port;
2525 		__be16 src_port;
2526 		union fw_foiscsi_conn_attr_addr {
2527 			struct fw_foiscsi_conn_attr_ipv6 {
2528 				__be64 dst_addr[2];
2529 				__be64 src_addr[2];
2530 			} ipv6_addr;
2531 			struct fw_foiscsi_conn_attr_ipv4 {
2532 				__be32 dst_addr;
2533 				__be32 src_addr;
2534 			} ipv4_addr;
2535 		} u;
2536 	} conn_attr;
2537 	__u8   tgt_name_len;
2538 	__u8   r3[7];
2539 	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2540 };
2541 
2542 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
2543 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
2544 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2545     ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2546 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
2547     (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2548 
2549 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
2550 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
2551 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2552     ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2553 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
2554     (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2555      M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2556 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
2557     V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2558 
2559 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
2560 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
2561 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2562     ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2563 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
2564     (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2565      M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2566 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
2567     V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2568 
2569 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
2570 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
2571 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2572     ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2573 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
2574     (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2575      M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2576 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
2577     V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2578 
2579 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
2580 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
2581 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2582     ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2583 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
2584     (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2585      M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2586 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
2587     V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2588 
2589 #define S_FW_FOISCSI_CTRL_WR_ERL	24
2590 #define M_FW_FOISCSI_CTRL_WR_ERL	0x3
2591 #define V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2592 #define G_FW_FOISCSI_CTRL_WR_ERL(x)	\
2593     (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2594 
2595 #define S_FW_FOISCSI_CTRL_WR_HDIGEST	30
2596 #define M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
2597 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2598 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
2599     (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2600 
2601 #define S_FW_FOISCSI_CTRL_WR_DDIGEST	28
2602 #define M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
2603 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2604 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
2605     (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2606 
2607 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
2608 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
2609 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2610     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2611 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
2612     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2613      M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2614 
2615 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
2616 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
2617 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2618     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2619 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
2620     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2621      M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2622 
2623 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
2624 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
2625 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2626     ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2627 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
2628     (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2629 
2630 #define S_FW_FOISCSI_CTRL_WR_IPV6	20
2631 #define M_FW_FOISCSI_CTRL_WR_IPV6	0x1
2632 #define V_FW_FOISCSI_CTRL_WR_IPV6(x)	((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2633 #define G_FW_FOISCSI_CTRL_WR_IPV6(x)	\
2634     (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2635 #define F_FW_FOISCSI_CTRL_WR_IPV6	V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2636 
2637 struct fw_foiscsi_chap_wr {
2638 	__be32 op_compl;
2639 	__be32 flowid_len16;
2640 	__u64  cookie;
2641 	__u8   status;
2642 	__u8   id_len;
2643 	__u8   sec_len;
2644 	__u8   node_type;
2645 	__be16 node_id;
2646 	__u8   r3[2];
2647 	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
2648 	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2649 };
2650 
2651 /******************************************************************************
2652  *  C O i S C S I  W O R K R E Q U E S T S
2653  ********************************************/
2654 
2655 enum fw_chnet_addr_type {
2656 	FW_CHNET_ADDD_TYPE_NONE = 0,
2657 	FW_CHNET_ADDR_TYPE_IPV4,
2658 	FW_CHNET_ADDR_TYPE_IPV6,
2659 };
2660 
2661 enum fw_msg_wr_type {
2662 	FW_MSG_WR_TYPE_RPL = 0,
2663 	FW_MSG_WR_TYPE_ERR,
2664 	FW_MSG_WR_TYPE_PLD,
2665 };
2666 
2667 struct fw_coiscsi_tgt_wr {
2668 	__be32 op_compl;
2669 	__be32 flowid_len16;
2670 	__u64  cookie;
2671 	__u8   subop;
2672 	__u8   status;
2673 	__be16 r4;
2674 	__be32 flags;
2675 	struct fw_coiscsi_tgt_conn_attr {
2676 		__be32 in_tid;
2677 		__be16 in_port;
2678 		__u8   in_type;
2679 		__u8   r6;
2680 		union fw_coiscsi_tgt_conn_attr_addr {
2681 			struct fw_coiscsi_tgt_conn_attr_in_addr {
2682 				__be32 addr;
2683 				__be32 r7;
2684 				__be32 r8[2];
2685 			} in_addr;
2686 			struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2687 				__be64 addr[2];
2688 			} in_addr6;
2689 		} u;
2690 	} conn_attr;
2691 };
2692 
2693 struct fw_coiscsi_tgt_xmit_wr {
2694 	__be32 op_to_immdlen;
2695 	__be32 flowid_len16;
2696 	__be64 cookie;
2697 	__be16 iq_id;
2698 	__be16 r4;
2699 	__be32 datasn;
2700 	__be32 t_xfer_len;
2701 	__be32 flags;
2702 	__be32 tag;
2703 	__be32 tidx;
2704 	__be32 r5[2];
2705 };
2706 
2707 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST		23
2708 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST		0x1
2709 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2710     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2711 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x)	\
2712     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2713 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST	V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
2714 
2715 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST		22
2716 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST		0x1
2717 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2718     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2719 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x)	\
2720     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2721 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST	V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
2722 
2723 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP	20
2724 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP	0x1
2725 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
2726 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x)	\
2727     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
2728 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP	V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
2729 
2730 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT		19
2731 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT		0x1
2732 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2733     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2734 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x)	\
2735     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2736 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT	V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U)
2737 
2738 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL		18
2739 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL		0x1
2740 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2741     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2742 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x)	\
2743     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2744 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL	V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U)
2745 
2746 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN		16
2747 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN		0x3
2748 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2749     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2750 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x)	\
2751     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \
2752      M_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2753 
2754 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0
2755 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN	0xff
2756 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2757     ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2758 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x)	\
2759     (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
2760      M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2761 
2762 struct fw_isns_wr {
2763 	__be32 op_compl;
2764 	__be32 flowid_len16;
2765 	__u64  cookie;
2766 	__u8   subop;
2767 	__u8   status;
2768 	__be16 iq_id;
2769 	__be32 r4;
2770 	struct fw_tcp_conn_attr {
2771 		__be32 in_tid;
2772 		__be16 in_port;
2773 		__u8   in_type;
2774 		__u8   r6;
2775 		union fw_tcp_conn_attr_addr {
2776 			struct fw_tcp_conn_attr_in_addr {
2777 				__be32 addr;
2778 				__be32 r7;
2779 				__be32 r8[2];
2780 			} in_addr;
2781 			struct fw_tcp_conn_attr_in_addr6 {
2782 				__be64 addr[2];
2783 			} in_addr6;
2784 		} u;
2785 	} conn_attr;
2786 };
2787 
2788 struct fw_isns_xmit_wr {
2789 	__be32 op_to_immdlen;
2790 	__be32 flowid_len16;
2791 	__be64 cookie;
2792 	__be16 iq_id;
2793 	__be16 r4;
2794 	__be32 xfer_len;
2795 	__be64 r5;
2796 };
2797 
2798 #define S_FW_ISNS_XMIT_WR_IMMDLEN	0
2799 #define M_FW_ISNS_XMIT_WR_IMMDLEN	0xff
2800 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x)	((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
2801 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x)	\
2802     (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
2803 
2804 /******************************************************************************
2805  *  F O F C O E   W O R K R E Q U E S T s
2806  *******************************************/
2807 
2808 struct fw_fcoe_els_ct_wr {
2809 	__be32 op_immdlen;
2810 	__be32 flowid_len16;
2811 	__be64 cookie;
2812 	__be16 iqid;
2813 	__u8   tmo_val;
2814 	__u8   els_ct_type;
2815 	__u8   ctl_pri;
2816 	__u8   cp_en_class;
2817 	__be16 xfer_cnt;
2818 	__u8   fl_to_sp;
2819 	__u8   l_id[3];
2820 	__u8   r5;
2821 	__u8   r_id[3];
2822 	__be64 rsp_dmaaddr;
2823 	__be32 rsp_dmalen;
2824 	__be32 r6;
2825 };
2826 
2827 #define S_FW_FCOE_ELS_CT_WR_OPCODE	24
2828 #define M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
2829 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2830 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
2831     (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2832 
2833 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
2834 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
2835 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2836 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
2837     (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2838 
2839 #define S_FW_FCOE_ELS_CT_WR_FLOWID	8
2840 #define M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
2841 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2842 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
2843     (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2844 
2845 #define S_FW_FCOE_ELS_CT_WR_LEN16	0
2846 #define M_FW_FCOE_ELS_CT_WR_LEN16	0xff
2847 #define V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2848 #define G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
2849     (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2850 
2851 #define S_FW_FCOE_ELS_CT_WR_CP_EN	6
2852 #define M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
2853 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2854 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
2855     (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2856 
2857 #define S_FW_FCOE_ELS_CT_WR_CLASS	4
2858 #define M_FW_FCOE_ELS_CT_WR_CLASS	0x3
2859 #define V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2860 #define G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
2861     (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2862 
2863 #define S_FW_FCOE_ELS_CT_WR_FL		2
2864 #define M_FW_FCOE_ELS_CT_WR_FL		0x1
2865 #define V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
2866 #define G_FW_FCOE_ELS_CT_WR_FL(x)	\
2867     (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2868 #define F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
2869 
2870 #define S_FW_FCOE_ELS_CT_WR_NPIV	1
2871 #define M_FW_FCOE_ELS_CT_WR_NPIV	0x1
2872 #define V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2873 #define G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
2874     (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2875 #define F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2876 
2877 #define S_FW_FCOE_ELS_CT_WR_SP		0
2878 #define M_FW_FCOE_ELS_CT_WR_SP		0x1
2879 #define V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
2880 #define G_FW_FCOE_ELS_CT_WR_SP(x)	\
2881     (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2882 #define F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
2883 
2884 /******************************************************************************
2885  *  S C S I   W O R K R E Q U E S T s   (FOiSCSI and FCOE unified data path)
2886  *****************************************************************************/
2887 
2888 struct fw_scsi_write_wr {
2889 	__be32 op_immdlen;
2890 	__be32 flowid_len16;
2891 	__be64 cookie;
2892 	__be16 iqid;
2893 	__u8   tmo_val;
2894 	__u8   use_xfer_cnt;
2895 	union fw_scsi_write_priv {
2896 		struct fcoe_write_priv {
2897 			__u8   ctl_pri;
2898 			__u8   cp_en_class;
2899 			__u8   r3_lo[2];
2900 		} fcoe;
2901 		struct iscsi_write_priv {
2902 			__u8   r3[4];
2903 		} iscsi;
2904 	} u;
2905 	__be32 xfer_cnt;
2906 	__be32 ini_xfer_cnt;
2907 	__be64 rsp_dmaaddr;
2908 	__be32 rsp_dmalen;
2909 	__be32 r4;
2910 };
2911 
2912 #define S_FW_SCSI_WRITE_WR_OPCODE	24
2913 #define M_FW_SCSI_WRITE_WR_OPCODE	0xff
2914 #define V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2915 #define G_FW_SCSI_WRITE_WR_OPCODE(x)	\
2916     (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2917 
2918 #define S_FW_SCSI_WRITE_WR_IMMDLEN	0
2919 #define M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
2920 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2921 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
2922     (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2923 
2924 #define S_FW_SCSI_WRITE_WR_FLOWID	8
2925 #define M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
2926 #define V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2927 #define G_FW_SCSI_WRITE_WR_FLOWID(x)	\
2928     (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2929 
2930 #define S_FW_SCSI_WRITE_WR_LEN16	0
2931 #define M_FW_SCSI_WRITE_WR_LEN16	0xff
2932 #define V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
2933 #define G_FW_SCSI_WRITE_WR_LEN16(x)	\
2934     (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2935 
2936 #define S_FW_SCSI_WRITE_WR_CP_EN	6
2937 #define M_FW_SCSI_WRITE_WR_CP_EN	0x3
2938 #define V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2939 #define G_FW_SCSI_WRITE_WR_CP_EN(x)	\
2940     (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2941 
2942 #define S_FW_SCSI_WRITE_WR_CLASS	4
2943 #define M_FW_SCSI_WRITE_WR_CLASS	0x3
2944 #define V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
2945 #define G_FW_SCSI_WRITE_WR_CLASS(x)	\
2946     (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2947 
2948 struct fw_scsi_read_wr {
2949 	__be32 op_immdlen;
2950 	__be32 flowid_len16;
2951 	__be64 cookie;
2952 	__be16 iqid;
2953 	__u8   tmo_val;
2954 	__u8   use_xfer_cnt;
2955 	union fw_scsi_read_priv {
2956 		struct fcoe_read_priv {
2957 			__u8   ctl_pri;
2958 			__u8   cp_en_class;
2959 			__u8   r3_lo[2];
2960 		} fcoe;
2961 		struct iscsi_read_priv {
2962 			__u8   r3[4];
2963 		} iscsi;
2964 	} u;
2965 	__be32 xfer_cnt;
2966 	__be32 ini_xfer_cnt;
2967 	__be64 rsp_dmaaddr;
2968 	__be32 rsp_dmalen;
2969 	__be32 r4;
2970 };
2971 
2972 #define S_FW_SCSI_READ_WR_OPCODE	24
2973 #define M_FW_SCSI_READ_WR_OPCODE	0xff
2974 #define V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
2975 #define G_FW_SCSI_READ_WR_OPCODE(x)	\
2976     (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2977 
2978 #define S_FW_SCSI_READ_WR_IMMDLEN	0
2979 #define M_FW_SCSI_READ_WR_IMMDLEN	0xff
2980 #define V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2981 #define G_FW_SCSI_READ_WR_IMMDLEN(x)	\
2982     (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2983 
2984 #define S_FW_SCSI_READ_WR_FLOWID	8
2985 #define M_FW_SCSI_READ_WR_FLOWID	0xfffff
2986 #define V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
2987 #define G_FW_SCSI_READ_WR_FLOWID(x)	\
2988     (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2989 
2990 #define S_FW_SCSI_READ_WR_LEN16		0
2991 #define M_FW_SCSI_READ_WR_LEN16		0xff
2992 #define V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
2993 #define G_FW_SCSI_READ_WR_LEN16(x)	\
2994     (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2995 
2996 #define S_FW_SCSI_READ_WR_CP_EN		6
2997 #define M_FW_SCSI_READ_WR_CP_EN		0x3
2998 #define V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
2999 #define G_FW_SCSI_READ_WR_CP_EN(x)	\
3000     (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3001 
3002 #define S_FW_SCSI_READ_WR_CLASS		4
3003 #define M_FW_SCSI_READ_WR_CLASS		0x3
3004 #define V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
3005 #define G_FW_SCSI_READ_WR_CLASS(x)	\
3006     (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3007 
3008 struct fw_scsi_cmd_wr {
3009 	__be32 op_immdlen;
3010 	__be32 flowid_len16;
3011 	__be64 cookie;
3012 	__be16 iqid;
3013 	__u8   tmo_val;
3014 	__u8   r3;
3015 	union fw_scsi_cmd_priv {
3016 		struct fcoe_cmd_priv {
3017 			__u8   ctl_pri;
3018 			__u8   cp_en_class;
3019 			__u8   r4_lo[2];
3020 		} fcoe;
3021 		struct iscsi_cmd_priv {
3022 			__u8   r4[4];
3023 		} iscsi;
3024 	} u;
3025 	__u8   r5[8];
3026 	__be64 rsp_dmaaddr;
3027 	__be32 rsp_dmalen;
3028 	__be32 r6;
3029 };
3030 
3031 #define S_FW_SCSI_CMD_WR_OPCODE		24
3032 #define M_FW_SCSI_CMD_WR_OPCODE		0xff
3033 #define V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
3034 #define G_FW_SCSI_CMD_WR_OPCODE(x)	\
3035     (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3036 
3037 #define S_FW_SCSI_CMD_WR_IMMDLEN	0
3038 #define M_FW_SCSI_CMD_WR_IMMDLEN	0xff
3039 #define V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3040 #define G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
3041     (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3042 
3043 #define S_FW_SCSI_CMD_WR_FLOWID		8
3044 #define M_FW_SCSI_CMD_WR_FLOWID		0xfffff
3045 #define V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
3046 #define G_FW_SCSI_CMD_WR_FLOWID(x)	\
3047     (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3048 
3049 #define S_FW_SCSI_CMD_WR_LEN16		0
3050 #define M_FW_SCSI_CMD_WR_LEN16		0xff
3051 #define V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
3052 #define G_FW_SCSI_CMD_WR_LEN16(x)	\
3053     (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3054 
3055 #define S_FW_SCSI_CMD_WR_CP_EN		6
3056 #define M_FW_SCSI_CMD_WR_CP_EN		0x3
3057 #define V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
3058 #define G_FW_SCSI_CMD_WR_CP_EN(x)	\
3059     (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3060 
3061 #define S_FW_SCSI_CMD_WR_CLASS		4
3062 #define M_FW_SCSI_CMD_WR_CLASS		0x3
3063 #define V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
3064 #define G_FW_SCSI_CMD_WR_CLASS(x)	\
3065     (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3066 
3067 struct fw_scsi_abrt_cls_wr {
3068 	__be32 op_immdlen;
3069 	__be32 flowid_len16;
3070 	__be64 cookie;
3071 	__be16 iqid;
3072 	__u8   tmo_val;
3073 	__u8   sub_opcode_to_chk_all_io;
3074 	__u8   r3[4];
3075 	__be64