1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * This file is part of the Chelsio T4 Ethernet driver. 14 * 15 * Copyright (C) 2005-2013 Chelsio Communications. All rights reserved. 16 * 17 * This program is distributed in the hope that it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 20 * release for licensing terms and conditions. 21 */ 22 23 #ifndef __CXGBE_COMMON_H 24 #define __CXGBE_COMMON_H 25 26 #include "shared.h" 27 #include "t4_hw.h" 28 #include "t4_chip_type.h" 29 30 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC | F_EDC0 | \ 31 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 32 F_CPL_SWITCH | F_SGE | F_ULP_TX) 33 34 enum { 35 MAX_NPORTS = 4, /* max # of ports */ 36 SERNUM_LEN = 24, /* Serial # length */ 37 EC_LEN = 16, /* E/C length */ 38 ID_LEN = 16, /* ID length */ 39 PN_LEN = 16, /* Part Number length */ 40 MACADDR_LEN = 12, /* MAC Address length */ 41 }; 42 43 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 44 45 enum { 46 MEMWIN0_APERTURE = 2048, 47 MEMWIN0_BASE = 0x1b800, 48 MEMWIN1_APERTURE = 32768, 49 MEMWIN1_BASE = 0x28000, 50 51 MEMWIN2_APERTURE_T4 = 65536, 52 MEMWIN2_BASE_T4 = 0x30000, 53 54 MEMWIN2_APERTURE_T5 = 128 * 1024, 55 MEMWIN2_BASE_T5 = 0x60000, 56 }; 57 58 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 59 60 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 61 62 enum { 63 PAUSE_RX = 1 << 0, 64 PAUSE_TX = 1 << 1, 65 PAUSE_AUTONEG = 1 << 2 66 }; 67 68 struct memwin { 69 uint32_t base; 70 uint32_t aperture; 71 }; 72 73 struct port_stats { 74 u64 tx_octets; /* total # of octets in good frames */ 75 u64 tx_frames; /* all good frames */ 76 u64 tx_bcast_frames; /* all broadcast frames */ 77 u64 tx_mcast_frames; /* all multicast frames */ 78 u64 tx_ucast_frames; /* all unicast frames */ 79 u64 tx_error_frames; /* all error frames */ 80 81 u64 tx_frames_64; /* # of Tx frames in a particular range */ 82 u64 tx_frames_65_127; 83 u64 tx_frames_128_255; 84 u64 tx_frames_256_511; 85 u64 tx_frames_512_1023; 86 u64 tx_frames_1024_1518; 87 u64 tx_frames_1519_max; 88 89 u64 tx_drop; /* # of dropped Tx frames */ 90 u64 tx_pause; /* # of transmitted pause frames */ 91 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 92 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 93 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 94 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 95 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 96 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 97 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 98 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 99 100 u64 rx_octets; /* total # of octets in good frames */ 101 u64 rx_frames; /* all good frames */ 102 u64 rx_bcast_frames; /* all broadcast frames */ 103 u64 rx_mcast_frames; /* all multicast frames */ 104 u64 rx_ucast_frames; /* all unicast frames */ 105 u64 rx_too_long; /* # of frames exceeding MTU */ 106 u64 rx_jabber; /* # of jabber frames */ 107 u64 rx_fcs_err; /* # of received frames with bad FCS */ 108 u64 rx_len_err; /* # of received frames with length error */ 109 u64 rx_symbol_err; /* symbol errors */ 110 u64 rx_runt; /* # of short frames */ 111 112 u64 rx_frames_64; /* # of Rx frames in a particular range */ 113 u64 rx_frames_65_127; 114 u64 rx_frames_128_255; 115 u64 rx_frames_256_511; 116 u64 rx_frames_512_1023; 117 u64 rx_frames_1024_1518; 118 u64 rx_frames_1519_max; 119 120 u64 rx_pause; /* # of received pause frames */ 121 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 122 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 123 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 124 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 125 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 126 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 127 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 128 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 129 130 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 131 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 132 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 133 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 134 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 135 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 136 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 137 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 138 }; 139 140 struct lb_port_stats { 141 u64 octets; 142 u64 frames; 143 u64 bcast_frames; 144 u64 mcast_frames; 145 u64 ucast_frames; 146 u64 error_frames; 147 148 u64 frames_64; 149 u64 frames_65_127; 150 u64 frames_128_255; 151 u64 frames_256_511; 152 u64 frames_512_1023; 153 u64 frames_1024_1518; 154 u64 frames_1519_max; 155 156 u64 drop; 157 158 u64 ovflow0; 159 u64 ovflow1; 160 u64 ovflow2; 161 u64 ovflow3; 162 u64 trunc0; 163 u64 trunc1; 164 u64 trunc2; 165 u64 trunc3; 166 }; 167 168 struct tp_tcp_stats { 169 u32 tcpOutRsts; 170 u64 tcpInSegs; 171 u64 tcpOutSegs; 172 u64 tcpRetransSegs; 173 }; 174 175 struct tp_usm_stats { 176 u32 frames; 177 u32 drops; 178 u64 octets; 179 }; 180 181 struct tp_fcoe_stats { 182 u32 framesDDP; 183 u32 framesDrop; 184 u64 octetsDDP; 185 }; 186 187 struct tp_err_stats { 188 u32 macInErrs[4]; 189 u32 hdrInErrs[4]; 190 u32 tcpInErrs[4]; 191 u32 tnlCongDrops[4]; 192 u32 ofldChanDrops[4]; 193 u32 tnlTxDrops[4]; 194 u32 ofldVlanDrops[4]; 195 u32 tcp6InErrs[4]; 196 u32 ofldNoNeigh; 197 u32 ofldCongDefer; 198 }; 199 200 struct tp_proxy_stats { 201 u32 proxy[4]; 202 }; 203 204 struct tp_cpl_stats { 205 u32 req[4]; 206 u32 rsp[4]; 207 }; 208 209 struct tp_rdma_stats { 210 u32 rqe_dfr_mod; 211 u32 rqe_dfr_pkt; 212 }; 213 214 struct tp_params { 215 unsigned int ntxchan; /* # of Tx channels */ 216 unsigned int tre; /* log2 of core clocks per TP tick */ 217 unsigned int dack_re; /* DACK timer resolution */ 218 unsigned int la_mask; /* what events are recorded by TP LA */ 219 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */ 220 }; 221 222 struct vpd_params { 223 unsigned int cclk; 224 u8 ec[EC_LEN + 1]; 225 u8 sn[SERNUM_LEN + 1]; 226 u8 id[ID_LEN + 1]; 227 u8 pn[PN_LEN + 1]; 228 u8 na[MACADDR_LEN + 1]; 229 }; 230 231 struct pci_params { 232 unsigned int vpd_cap_addr; 233 unsigned short speed; 234 unsigned char width; 235 }; 236 237 /* 238 * Firmware device log. 239 */ 240 struct devlog_params { 241 u32 memtype; /* which memory (EDC0, EDC1, MC) */ 242 u32 start; /* start of log in firmware memory */ 243 u32 size; /* size of log */ 244 }; 245 246 struct adapter_params { 247 struct tp_params tp; 248 struct vpd_params vpd; 249 struct pci_params pci; 250 struct devlog_params devlog; 251 252 unsigned int sf_size; /* serial flash size in bytes */ 253 unsigned int sf_nsec; /* # of flash sectors */ 254 255 unsigned int fw_vers; 256 unsigned int tp_vers; 257 u8 api_vers[7]; 258 259 unsigned short mtus[NMTUS]; 260 unsigned short a_wnd[NCCTRL_WIN]; 261 unsigned short b_wnd[NCCTRL_WIN]; 262 263 unsigned int mc_size; /* MC memory size */ 264 unsigned int nfilters; /* size of filter region */ 265 266 unsigned int cim_la_size; 267 268 unsigned int nports; /* # of ethernet ports */ 269 unsigned int portvec; 270 unsigned int rev; /* chip revision */ 271 unsigned int offload; 272 273 unsigned char bypass; 274 275 enum chip_type chip; /* chip code */ 276 277 unsigned int ofldq_wr_cred; 278 279 unsigned int nsched_cls; /* number of traffic classes */ 280 281 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ 282 unsigned int max_ird_adapter; /* Max read depth per adapter */ 283 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 284 }; 285 286 enum { /* chip revisions */ 287 T4_REV_A = 0, 288 }; 289 290 struct trace_params { 291 u32 data[TRACE_LEN / 4]; 292 u32 mask[TRACE_LEN / 4]; 293 unsigned short snap_len; 294 unsigned short min_len; 295 unsigned char skip_ofst; 296 unsigned char skip_len; 297 unsigned char invert; 298 unsigned char port; 299 }; 300 301 struct link_config { 302 unsigned short supported; /* link capabilities */ 303 unsigned short advertising; /* advertised capabilities */ 304 unsigned short requested_speed; /* speed user has requested */ 305 unsigned short speed; /* actual link speed */ 306 unsigned char requested_fc; /* flow control user has requested */ 307 unsigned char fc; /* actual link flow control */ 308 unsigned char autoneg; /* autonegotiating? */ 309 unsigned char link_ok; /* link up? */ 310 }; 311 312 #include "adapter.h" 313 314 #ifndef PCI_VENDOR_ID_CHELSIO 315 #define PCI_VENDOR_ID_CHELSIO 0x1425 316 #endif 317 318 #define for_each_port(adapter, iter) \ 319 for (iter = 0; iter < (adapter)->params.nports; ++iter) 320 321 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 322 u32 val); 323 324 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 325 void *rpl, bool sleep_ok); 326 327 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 328 int size, void *rpl); 329 330 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 331 unsigned int data_reg, u32 *vals, unsigned int nregs, 332 unsigned int start_idx); 333 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 334 unsigned int data_reg, const u32 *vals, 335 unsigned int nregs, unsigned int start_idx); 336 337 struct fw_filter_wr; 338 339 void t4_intr_enable(struct adapter *adapter); 340 void t4_intr_disable(struct adapter *adapter); 341 void t4_intr_clear(struct adapter *adapter); 342 int t4_slow_intr_handler(struct adapter *adapter); 343 344 int t4_hash_mac_addr(const u8 *addr); 345 int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port, 346 struct link_config *lc); 347 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 348 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 349 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 350 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 351 int t4_seeprom_wp(struct adapter *adapter, int enable); 352 int t4_read_flash(struct adapter *adapter, unsigned int addr, 353 unsigned int nwords, u32 *data, int byte_oriented); 354 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 355 int t4_flash_cfg_addr(struct adapter *adapter); 356 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 357 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 358 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 359 int t4_check_fw_version(struct adapter *adapter); 360 int t4_init_hw(struct adapter *adapter, u32 fw_params); 361 int t4_prep_adapter(struct adapter *adapter); 362 int t4_port_init(struct port_info *p, int mbox, int pf, int vf); 363 int t4_reinit_adapter(struct adapter *adap); 364 void t4_fatal_err(struct adapter *adapter); 365 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 366 int filter_index, int enable); 367 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 368 int filter_index, int *enabled); 369 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 370 int start, int n, const u16 *rspq, unsigned int nrspq); 371 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 372 unsigned int flags); 373 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 374 unsigned int flags, unsigned int defq); 375 int t4_read_rss(struct adapter *adapter, u16 *entries); 376 void t4_read_rss_key(struct adapter *adapter, u32 *key); 377 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 378 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 379 u32 *valp); 380 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 381 u32 val); 382 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 383 u32 *vfl, u32 *vfh); 384 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 385 u32 vfl, u32 vfh); 386 u32 t4_read_rss_pf_map(struct adapter *adapter); 387 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 388 u32 t4_read_rss_pf_mask(struct adapter *adapter); 389 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 390 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 391 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 392 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 393 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 394 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, 395 size_t n); 396 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, 397 size_t n); 398 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 399 unsigned int *valp); 400 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 401 const unsigned int *valp); 402 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 403 unsigned int *valp); 404 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 405 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 406 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 407 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 408 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 409 __be32 *data, u64 *parity); 410 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 411 u64 *parity); 412 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 413 __be32 *data); 414 int t4_mem_win_read(struct adapter *adap, u32 addr, __be32 *data); 415 416 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 417 void t4_get_port_stats_offset(struct adapter *adap, int idx, 418 struct port_stats *stats, 419 struct port_stats *offset); 420 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 421 void t4_clr_port_stats(struct adapter *adap, int idx); 422 423 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 424 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 425 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 426 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, 427 unsigned int *kbps, unsigned int *ipg); 428 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 429 unsigned int mask, unsigned int val); 430 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 431 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 432 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 433 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 434 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 435 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 436 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 437 struct tp_tcp_stats *v6); 438 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 439 struct tp_fcoe_stats *st); 440 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 441 const unsigned short *alpha, const unsigned short *beta); 442 443 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 444 445 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 446 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 447 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 448 unsigned int start, unsigned int n); 449 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 450 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 451 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 452 453 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 454 const u8 *addr); 455 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 456 u64 mask0, u64 mask1, unsigned int crc, bool enable); 457 458 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 459 enum dev_master master, enum dev_state *state); 460 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 461 int t4_early_init(struct adapter *adap, unsigned int mbox); 462 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 463 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 464 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 465 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 466 const u8 *fw_data, unsigned int size, int force); 467 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 468 469 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 470 unsigned int vf, unsigned int nparams, const u32 *params, u32 *val); 471 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 472 unsigned int vf, unsigned int nparams, const u32 *params, 473 const u32 *val); 474 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 475 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 476 unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi, 477 unsigned int cmask, unsigned int pmask, unsigned int exactf, 478 unsigned int rcaps, unsigned int wxcaps); 479 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 480 unsigned int port, unsigned int pf, unsigned int vf, 481 unsigned int nmac, u8 *mac, unsigned int *rss_size, 482 unsigned int portfunc, unsigned int idstype); 483 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 484 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 485 unsigned int *rss_size); 486 int t4_free_vi(struct adapter *adap, unsigned int mbox, 487 unsigned int pf, unsigned int vf, unsigned int viid); 488 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 489 int mtu, int promisc, int all_multi, int bcast, int vlanex, 490 bool sleep_ok); 491 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 492 unsigned int viid, bool free, unsigned int naddr, const u8 **addr, 493 u16 *idx, u64 *hash, bool sleep_ok); 494 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 495 int idx, const u8 *addr, bool persist, bool add_smt); 496 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 497 bool ucast, u64 vec, bool sleep_ok); 498 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 499 bool rx_en, bool tx_en); 500 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 501 unsigned int nblinks); 502 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 503 unsigned int mmd, unsigned int reg, unsigned int *valp); 504 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 505 unsigned int mmd, unsigned int reg, unsigned int val); 506 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start, 507 unsigned int pf, unsigned int vf, unsigned int iqid, unsigned int fl0id, 508 unsigned int fl1id); 509 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 510 unsigned int vf, unsigned int iqtype, unsigned int iqid, 511 unsigned int fl0id, unsigned int fl1id); 512 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 513 unsigned int vf, unsigned int eqid); 514 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 515 unsigned int vf, unsigned int eqid); 516 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 517 unsigned int vf, unsigned int eqid); 518 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 519 enum ctxt_type ctype, u32 *data); 520 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, 521 enum ctxt_type ctype, u32 *data); 522 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 523 /* common.c */ 524 int is_offload(const struct adapter *adap); 525 unsigned int core_ticks_per_usec(const struct adapter *adap); 526 int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, int size, 527 void *rpl); 528 int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, int size, 529 void *rpl); 530 unsigned int us_to_core_ticks(const struct adapter *adap, unsigned int us); 531 unsigned int core_ticks_to_us(const struct adapter *adapter, 532 unsigned int ticks); 533 unsigned int dack_ticks_to_usec(const struct adapter *adap, unsigned int ticks); 534 int is_bypass(const adapter_t *adap); 535 int is_bypass_device(int device); 536 int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, int polarity, 537 int attempts, int delay); 538 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 539 int polarity, int attempts, int delay, u32 *valp); 540 541 int is_t4(enum chip_type chip); 542 int is_t5(enum chip_type chip); 543 int is_fpga(enum chip_type chip); 544 #endif /* __CXGBE_COMMON_H */ 545