1*80c94ecdSKeith M Wesolowski /* 2*80c94ecdSKeith M Wesolowski * This file and its contents are supplied under the terms of the 3*80c94ecdSKeith M Wesolowski * Common Development and Distribution License ("CDDL"), version 1.0. 4*80c94ecdSKeith M Wesolowski * You may only use this file in accordance with the terms of version 5*80c94ecdSKeith M Wesolowski * 1.0 of the CDDL. 6*80c94ecdSKeith M Wesolowski * 7*80c94ecdSKeith M Wesolowski * A full copy of the text of the CDDL should have accompanied this 8*80c94ecdSKeith M Wesolowski * source. A copy of the CDDL is also available via the Internet at 9*80c94ecdSKeith M Wesolowski * http://www.illumos.org/license/CDDL. 10*80c94ecdSKeith M Wesolowski */ 11*80c94ecdSKeith M Wesolowski 12*80c94ecdSKeith M Wesolowski /* 13*80c94ecdSKeith M Wesolowski * Copyright (C) 2013 Hewlett-Packard Development Company, L.P. 14*80c94ecdSKeith M Wesolowski */ 15*80c94ecdSKeith M Wesolowski 16*80c94ecdSKeith M Wesolowski #ifndef _CPQARY3_H 17*80c94ecdSKeith M Wesolowski #define _CPQARY3_H 18*80c94ecdSKeith M Wesolowski 19*80c94ecdSKeith M Wesolowski #include <sys/types.h> 20*80c94ecdSKeith M Wesolowski #include <sys/pci.h> 21*80c94ecdSKeith M Wesolowski #include <sys/param.h> 22*80c94ecdSKeith M Wesolowski #include <sys/errno.h> 23*80c94ecdSKeith M Wesolowski #include <sys/conf.h> 24*80c94ecdSKeith M Wesolowski #include <sys/map.h> 25*80c94ecdSKeith M Wesolowski #include <sys/modctl.h> 26*80c94ecdSKeith M Wesolowski #include <sys/kmem.h> 27*80c94ecdSKeith M Wesolowski #include <sys/cmn_err.h> 28*80c94ecdSKeith M Wesolowski #include <sys/stat.h> 29*80c94ecdSKeith M Wesolowski #include <sys/scsi/scsi.h> 30*80c94ecdSKeith M Wesolowski #include <sys/devops.h> 31*80c94ecdSKeith M Wesolowski #include <sys/ddi.h> 32*80c94ecdSKeith M Wesolowski #include <sys/sunddi.h> 33*80c94ecdSKeith M Wesolowski 34*80c94ecdSKeith M Wesolowski #include <cpqary3_ciss.h> 35*80c94ecdSKeith M Wesolowski #include <cpqary3_bd.h> 36*80c94ecdSKeith M Wesolowski 37*80c94ecdSKeith M Wesolowski #ifdef __cplusplus 38*80c94ecdSKeith M Wesolowski extern "C" { 39*80c94ecdSKeith M Wesolowski #endif 40*80c94ecdSKeith M Wesolowski 41*80c94ecdSKeith M Wesolowski /* 42*80c94ecdSKeith M Wesolowski * Ioctl Commands 43*80c94ecdSKeith M Wesolowski */ 44*80c94ecdSKeith M Wesolowski #define CPQARY3_IOCTL_CMD ('c' << 4) 45*80c94ecdSKeith M Wesolowski #define CPQARY3_IOCTL_DRIVER_INFO CPQARY3_IOCTL_CMD | 0x01 46*80c94ecdSKeith M Wesolowski #define CPQARY3_IOCTL_CTLR_INFO CPQARY3_IOCTL_CMD | 0x02 47*80c94ecdSKeith M Wesolowski #define CPQARY3_IOCTL_BMIC_PASS CPQARY3_IOCTL_CMD | 0x04 48*80c94ecdSKeith M Wesolowski #define CPQARY3_IOCTL_SCSI_PASS CPQARY3_IOCTL_CMD | 0x08 49*80c94ecdSKeith M Wesolowski 50*80c94ecdSKeith M Wesolowski /* Driver Revision : Used in Ioctl */ 51*80c94ecdSKeith M Wesolowski #define CPQARY3_MINOR_REV_NO 00 52*80c94ecdSKeith M Wesolowski #define CPQARY3_MAJOR_REV_NO 01 53*80c94ecdSKeith M Wesolowski #define CPQARY3_REV_DATE 05 54*80c94ecdSKeith M Wesolowski #define CPQARY3_REV_MONTH 04 55*80c94ecdSKeith M Wesolowski #define CPQARY3_REV_YEAR 2001 56*80c94ecdSKeith M Wesolowski 57*80c94ecdSKeith M Wesolowski /* Some Useful definations */ 58*80c94ecdSKeith M Wesolowski #define CPQARY3_FAILURE 0 59*80c94ecdSKeith M Wesolowski #define CPQARY3_SUCCESS 1 60*80c94ecdSKeith M Wesolowski #define CPQARY3_SENT 2 61*80c94ecdSKeith M Wesolowski #define CPQARY3_SUBMITTED 3 62*80c94ecdSKeith M Wesolowski #define CPQARY3_NO_SIG 4 63*80c94ecdSKeith M Wesolowski 64*80c94ecdSKeith M Wesolowski #define CPQARY3_TRUE 1 65*80c94ecdSKeith M Wesolowski #define CPQARY3_FALSE 0 66*80c94ecdSKeith M Wesolowski 67*80c94ecdSKeith M Wesolowski #define CTLR_SCSI_ID 7 68*80c94ecdSKeith M Wesolowski #define CPQARY3_LD_FAILED 1 69*80c94ecdSKeith M Wesolowski /* 70*80c94ecdSKeith M Wesolowski * Defines for cleanup in cpqary3_attach and cpqary3_detach. 71*80c94ecdSKeith M Wesolowski */ 72*80c94ecdSKeith M Wesolowski #define CPQARY3_HBA_TRAN_ALLOC_DONE 0x0001 73*80c94ecdSKeith M Wesolowski #define CPQARY3_HBA_TRAN_ATTACH_DONE 0x0002 74*80c94ecdSKeith M Wesolowski #define CPQARY3_CTLR_CONFIG_DONE 0x0004 75*80c94ecdSKeith M Wesolowski #define CPQARY3_INTR_HDLR_SET 0x0008 76*80c94ecdSKeith M Wesolowski #define CPQARY3_CREATE_MINOR_NODE 0x0010 77*80c94ecdSKeith M Wesolowski #define CPQARY3_SOFTSTATE_ALLOC_DONE 0x0020 78*80c94ecdSKeith M Wesolowski #define CPQARY3_MUTEX_INIT_DONE 0x0040 79*80c94ecdSKeith M Wesolowski #define CPQARY3_TICK_TMOUT_REGD 0x0080 80*80c94ecdSKeith M Wesolowski #define CPQARY3_MEM_MAPPED 0x0100 81*80c94ecdSKeith M Wesolowski #define CPQARY3_SW_INTR_HDLR_SET 0x0200 82*80c94ecdSKeith M Wesolowski #define CPQARY3_SW_MUTEX_INIT_DONE 0x0400 83*80c94ecdSKeith M Wesolowski #define CPQARY3_NOE_INIT_DONE 0x0800 84*80c94ecdSKeith M Wesolowski 85*80c94ecdSKeith M Wesolowski #define CPQARY3_CLEAN_ALL 0x0FFF 86*80c94ecdSKeith M Wesolowski 87*80c94ecdSKeith M Wesolowski #define CPQARY3_TICKTMOUT_VALUE 180000000 /* 180 seconds */ 88*80c94ecdSKeith M Wesolowski 89*80c94ecdSKeith M Wesolowski /* 90*80c94ecdSKeith M Wesolowski * Defines for Maximum and Default Settings. 91*80c94ecdSKeith M Wesolowski */ 92*80c94ecdSKeith M Wesolowski 93*80c94ecdSKeith M Wesolowski #define MAX_LOGDRV 64 /* Max supported Logical Drivers */ 94*80c94ecdSKeith M Wesolowski #define MAX_CTLRS 8 /* Max supported Controllers */ 95*80c94ecdSKeith M Wesolowski #define MAX_TAPE 28 96*80c94ecdSKeith M Wesolowski /* 97*80c94ecdSKeith M Wesolowski * NOTE: When changing the below two entries, Max SG count in cpqary3_ciss.h 98*80c94ecdSKeith M Wesolowski * should also be changed. 99*80c94ecdSKeith M Wesolowski */ 100*80c94ecdSKeith M Wesolowski /* SG */ 101*80c94ecdSKeith M Wesolowski #define MAX_PERF_SG_CNT 64 /* Maximum S/G in performant mode */ 102*80c94ecdSKeith M Wesolowski #define CPQARY3_SG_CNT 30 /* minimum S/G in simple mode */ 103*80c94ecdSKeith M Wesolowski #define CPQARY3_PERF_SG_CNT 31 /* minimum S/G for performant mode */ 104*80c94ecdSKeith M Wesolowski /* SG */ 105*80c94ecdSKeith M Wesolowski 106*80c94ecdSKeith M Wesolowski 107*80c94ecdSKeith M Wesolowski #define CPQARY3_MAX_TGT (MAX_LOGDRV + MAX_TAPE + 1) 108*80c94ecdSKeith M Wesolowski 109*80c94ecdSKeith M Wesolowski /* 110*80c94ecdSKeith M Wesolowski * SCSI Capabilities Related IDs 111*80c94ecdSKeith M Wesolowski */ 112*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_DISCON_ENABLED 0x01 113*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_SYNC_ENABLED 0x02 114*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_WIDE_XFER_ENABLED 0x04 115*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_ARQ_ENABLED 0x08 116*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_TAG_QING_ENABLED 0x10 117*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_TAG_QING_SUPP 0x20 118*80c94ecdSKeith M Wesolowski #define CPQARY3_CAP_UNTAG_DRV_QING_ENABLED 0x40 119*80c94ecdSKeith M Wesolowski 120*80c94ecdSKeith M Wesolowski /* 121*80c94ecdSKeith M Wesolowski * Defines for HBA 122*80c94ecdSKeith M Wesolowski */ 123*80c94ecdSKeith M Wesolowski #define CAP_NOT_DEFINED -1 124*80c94ecdSKeith M Wesolowski #define CAP_CHG_NOT_ALLOWED 0 125*80c94ecdSKeith M Wesolowski #define CAP_CHG_SUCCESS 1 126*80c94ecdSKeith M Wesolowski 127*80c94ecdSKeith M Wesolowski /* 128*80c94ecdSKeith M Wesolowski * Macros for Data Access 129*80c94ecdSKeith M Wesolowski */ 130*80c94ecdSKeith M Wesolowski 131*80c94ecdSKeith M Wesolowski /* SCSI Addr to Per Controller */ 132*80c94ecdSKeith M Wesolowski #define SA2CTLR(saddr) ((cpqary3_t *)((saddr)->a_hba_tran->tran_hba_private)) 133*80c94ecdSKeith M Wesolowski #define SA2TGT(sa) (sa)->a_target /* SCSI Addr to Target ID */ 134*80c94ecdSKeith M Wesolowski #define SD2TGT(sd) (sd)->sd_address.a_target /* SCSI Dev to Target ID */ 135*80c94ecdSKeith M Wesolowski #define SD2LUN(sd) (sd)->sd_address.a_lun /* SCSI Dev to Lun */ 136*80c94ecdSKeith M Wesolowski #define SD2SA(sd) ((sd)->sd_address) /* SCSI Dev to SCSI Addr */ 137*80c94ecdSKeith M Wesolowski 138*80c94ecdSKeith M Wesolowski /* SCSI Dev to Per Controller */ 139*80c94ecdSKeith M Wesolowski #define SD2CTLR(sd) \ 140*80c94ecdSKeith M Wesolowski ((cpqary3_t *)sd->sd_address.a_hba_tran->tran_hba_private) 141*80c94ecdSKeith M Wesolowski 142*80c94ecdSKeith M Wesolowski #define PKT2PVTPKT(sp) ((cpqary3_pkt_t *)((sp)->pkt_ha_private)) 143*80c94ecdSKeith M Wesolowski #define PVTPKT2MEM(p) ((cpqary3_cmdpvt_t *)p->memp) 144*80c94ecdSKeith M Wesolowski #define MEM2CMD(m) ((CommandList_t *)m->cmdlist_memaddr) 145*80c94ecdSKeith M Wesolowski #define SP2CMD(sp) MEM2CMD(PVTPKT2MEM(PKT2PVTPKT(sp))) 146*80c94ecdSKeith M Wesolowski #define CTLR2MEMLISTP(ctlr) ((cpqary3_cmdmemlist_t *)ctlr->cmdmemlistp) 147*80c94ecdSKeith M Wesolowski #define MEM2PVTPKT(m) ((cpqary3_pkt_t *)m->pvt_pkt) 148*80c94ecdSKeith M Wesolowski #define MEM2DRVPVT(m) ((cpqary3_private_t *)m->driverdata) 149*80c94ecdSKeith M Wesolowski #define TAG2MEM(ctlr, tag) \ 150*80c94ecdSKeith M Wesolowski ((cpqary3_cmdpvt_t *)(CTLR2MEMLISTP(ctlr)->pool[tag])) 151*80c94ecdSKeith M Wesolowski 152*80c94ecdSKeith M Wesolowski /* MACROS */ 153*80c94ecdSKeith M Wesolowski #define CPQARY3_MIN(x, y) (x < y ? x : y) 154*80c94ecdSKeith M Wesolowski #define CPQARY3_SWAP(val) ((val >> 8) | ((val & 0xff) << 8)) 155*80c94ecdSKeith M Wesolowski #define RETURN_VOID_IF_NULL(x) if (NULL == x) return 156*80c94ecdSKeith M Wesolowski #define RETURN_NULL_IF_NULL(x) if (NULL == x) return (NULL) 157*80c94ecdSKeith M Wesolowski #define RETURN_FAILURE_IF_NULL(x) if (NULL == x) return (CPQARY3_FAILURE) 158*80c94ecdSKeith M Wesolowski 159*80c94ecdSKeith M Wesolowski /* 160*80c94ecdSKeith M Wesolowski * Macros for memory allocation/deallocations 161*80c94ecdSKeith M Wesolowski */ 162*80c94ecdSKeith M Wesolowski #define MEM_ZALLOC(x) kmem_zalloc(x, KM_NOSLEEP) 163*80c94ecdSKeith M Wesolowski #define MEM_SFREE(x, y) if (x) kmem_free((void*)x, y) 164*80c94ecdSKeith M Wesolowski 165*80c94ecdSKeith M Wesolowski /* 166*80c94ecdSKeith M Wesolowski * Convenient macros for reading/writing Configuration table registers 167*80c94ecdSKeith M Wesolowski */ 168*80c94ecdSKeith M Wesolowski #define DDI_GET8(ctlr, regp) \ 169*80c94ecdSKeith M Wesolowski ddi_get8((ctlr)->ct_handle, (uint8_t *)(regp)) 170*80c94ecdSKeith M Wesolowski #define DDI_PUT8(ctlr, regp, value) \ 171*80c94ecdSKeith M Wesolowski ddi_put8((ctlr)->ct_handle, (uint8_t *)(regp), (value)) 172*80c94ecdSKeith M Wesolowski #define DDI_GET16(ctlr, regp) \ 173*80c94ecdSKeith M Wesolowski ddi_get16((ctlr)->ct_handle, (uint16_t *)(regp)) 174*80c94ecdSKeith M Wesolowski #define DDI_PUT16(ctlr, regp, value) \ 175*80c94ecdSKeith M Wesolowski ddi_put16((ctlr)->ct_handle, (uint16_t *)(regp), (value)) 176*80c94ecdSKeith M Wesolowski #define DDI_GET32(ctlr, regp) \ 177*80c94ecdSKeith M Wesolowski ddi_get32((ctlr)->ct_handle, (uint32_t *)(regp)) 178*80c94ecdSKeith M Wesolowski #define DDI_PUT32(ctlr, regp, value) \ 179*80c94ecdSKeith M Wesolowski ddi_put32((ctlr)->ct_handle, (uint32_t *)(regp), (value)) 180*80c94ecdSKeith M Wesolowski /* PERF */ 181*80c94ecdSKeith M Wesolowski #define DDI_PUT32_CP(ctlr, regp, value) \ 182*80c94ecdSKeith M Wesolowski ddi_put32((ctlr)->cp_handle, (uint32_t *)(regp), (value)) 183*80c94ecdSKeith M Wesolowski /* PERF */ 184*80c94ecdSKeith M Wesolowski 185*80c94ecdSKeith M Wesolowski #define CPQARY3_BUFFER_ERROR_CLEAR 0x0 /* to be used with bioerror */ 186*80c94ecdSKeith M Wesolowski #define CPQARY3_DMA_NO_CALLBACK 0x0 /* to be used with DMA calls */ 187*80c94ecdSKeith M Wesolowski #define CPQARY3_DMA_ALLOC_HANDLE_DONE 0x01 188*80c94ecdSKeith M Wesolowski #define CPQARY3_DMA_ALLOC_MEM_DONE 0x02 189*80c94ecdSKeith M Wesolowski #define CPQARY3_DMA_BIND_ADDR_DONE 0x04 190*80c94ecdSKeith M Wesolowski #define CPQARY3_FREE_PHYCTG_MEM 0x07 191*80c94ecdSKeith M Wesolowski #define CPQARY3_SYNCCMD_SEND_WAITSIG (0x0001) 192*80c94ecdSKeith M Wesolowski 193*80c94ecdSKeith M Wesolowski /* 194*80c94ecdSKeith M Wesolowski * Include the driver specific relevant header files here. 195*80c94ecdSKeith M Wesolowski */ 196*80c94ecdSKeith M Wesolowski #include "cpqary3_ciss.h" 197*80c94ecdSKeith M Wesolowski #include "cpqary3_q_mem.h" 198*80c94ecdSKeith M Wesolowski #include "cpqary3_noe.h" 199*80c94ecdSKeith M Wesolowski #include "cpqary3_scsi.h" 200*80c94ecdSKeith M Wesolowski #include "cpqary3_ioctl.h" 201*80c94ecdSKeith M Wesolowski 202*80c94ecdSKeith M Wesolowski /* 203*80c94ecdSKeith M Wesolowski * Per Target Structure 204*80c94ecdSKeith M Wesolowski */ 205*80c94ecdSKeith M Wesolowski 206*80c94ecdSKeith M Wesolowski typedef struct cpqary3_target { 207*80c94ecdSKeith M Wesolowski uint32_t logical_id : 30; /* at most 64 : 63 drives + 1 CTLR */ 208*80c94ecdSKeith M Wesolowski uint32_t type : 2; /* NONE, CTLR, LOGICAL DRIVE, TAPE */ 209*80c94ecdSKeith M Wesolowski PhysDevAddr_t PhysID; 210*80c94ecdSKeith M Wesolowski union { 211*80c94ecdSKeith M Wesolowski struct { 212*80c94ecdSKeith M Wesolowski uint8_t id; 213*80c94ecdSKeith M Wesolowski uint8_t bus; 214*80c94ecdSKeith M Wesolowski } scsi; /* To support tapes */ 215*80c94ecdSKeith M Wesolowski struct { 216*80c94ecdSKeith M Wesolowski uint8_t heads; 217*80c94ecdSKeith M Wesolowski uint8_t sectors; 218*80c94ecdSKeith M Wesolowski } drive; /* Logical drives */ 219*80c94ecdSKeith M Wesolowski } properties; 220*80c94ecdSKeith M Wesolowski 221*80c94ecdSKeith M Wesolowski uint32_t ctlr_flags; 222*80c94ecdSKeith M Wesolowski dev_info_t *tgt_dip; 223*80c94ecdSKeith M Wesolowski ddi_dma_attr_t dma_attrs; 224*80c94ecdSKeith M Wesolowski } cpqary3_tgt_t; 225*80c94ecdSKeith M Wesolowski 226*80c94ecdSKeith M Wesolowski 227*80c94ecdSKeith M Wesolowski /* 228*80c94ecdSKeith M Wesolowski * Values for the type field in the Per Target Structure (above) 229*80c94ecdSKeith M Wesolowski */ 230*80c94ecdSKeith M Wesolowski #define CPQARY3_TARGET_NONE 0 /* No Device */ 231*80c94ecdSKeith M Wesolowski #define CPQARY3_TARGET_CTLR 1 /* Controller */ 232*80c94ecdSKeith M Wesolowski #define CPQARY3_TARGET_LOG_VOL 2 /* Logical Volume */ 233*80c94ecdSKeith M Wesolowski #define CPQARY3_TARGET_TAPE 3 /* SCSI Device - Tape */ 234*80c94ecdSKeith M Wesolowski 235*80c94ecdSKeith M Wesolowski /* 236*80c94ecdSKeith M Wesolowski * Index into PCI Configuration Registers for Base Address Registers(BAR) 237*80c94ecdSKeith M Wesolowski * Currently, only index for BAR 0 and BAR 1 are defined 238*80c94ecdSKeith M Wesolowski */ 239*80c94ecdSKeith M Wesolowski #define INDEX_PCI_BASE0 1 /* offset 0x10 */ 240*80c94ecdSKeith M Wesolowski #define INDEX_PCI_BASE1 2 /* offset 0x14 */ 241*80c94ecdSKeith M Wesolowski 242*80c94ecdSKeith M Wesolowski /* Offset Values for IO interface from BAR 0 */ 243*80c94ecdSKeith M Wesolowski #define INBOUND_DOORBELL 0x20 244*80c94ecdSKeith M Wesolowski #define OUTBOUND_LIST_STATUS 0x30 245*80c94ecdSKeith M Wesolowski #define OUTBOUND_INTERRUPT_MASK 0x34 246*80c94ecdSKeith M Wesolowski #define INBOUND_QUEUE 0x40 247*80c94ecdSKeith M Wesolowski #define OUTBOUND_QUEUE 0x44 248*80c94ecdSKeith M Wesolowski 249*80c94ecdSKeith M Wesolowski /* Offset Values for IO interface from BAR 1 */ 250*80c94ecdSKeith M Wesolowski #define CONFIGURATION_TABLE 0x00 251*80c94ecdSKeith M Wesolowski 252*80c94ecdSKeith M Wesolowski #define INTR_DISABLE_5300_MASK 0x00000008l 253*80c94ecdSKeith M Wesolowski #define INTR_DISABLE_5I_MASK 0x00000004l 254*80c94ecdSKeith M Wesolowski 255*80c94ecdSKeith M Wesolowski #define OUTBOUND_LIST_5300_EXISTS 0x00000008l 256*80c94ecdSKeith M Wesolowski #define OUTBOUND_LIST_5I_EXISTS 0x00000004l 257*80c94ecdSKeith M Wesolowski 258*80c94ecdSKeith M Wesolowski #define INTR_PERF_MASK 0x00000001l 259*80c94ecdSKeith M Wesolowski 260*80c94ecdSKeith M Wesolowski #define INTR_PERF_LOCKUP_MASK 0x00000004l 261*80c94ecdSKeith M Wesolowski 262*80c94ecdSKeith M Wesolowski #define INTR_E200_PERF_MASK 0x00000004l 263*80c94ecdSKeith M Wesolowski 264*80c94ecdSKeith M Wesolowski #define INTR_SIMPLE_MASK 0x00000008l 265*80c94ecdSKeith M Wesolowski #define INTR_SIMPLE_LOCKUP_MASK 0x0000000cl 266*80c94ecdSKeith M Wesolowski 267*80c94ecdSKeith M Wesolowski 268*80c94ecdSKeith M Wesolowski #define INTR_SIMPLE_5I_MASK 0x00000004l 269*80c94ecdSKeith M Wesolowski #define INTR_SIMPLE_5I_LOCKUP_MASK 0x0000000cl 270*80c94ecdSKeith M Wesolowski 271*80c94ecdSKeith M Wesolowski typedef struct cpqary3_per_controller CTLR; 272*80c94ecdSKeith M Wesolowski /* 273*80c94ecdSKeith M Wesolowski * Per Controller Structure 274*80c94ecdSKeith M Wesolowski */ 275*80c94ecdSKeith M Wesolowski typedef struct cpqary3_per_controller { 276*80c94ecdSKeith M Wesolowski /* System Dependent Entities */ 277*80c94ecdSKeith M Wesolowski uint8_t bus; 278*80c94ecdSKeith M Wesolowski uint8_t dev : 5; 279*80c94ecdSKeith M Wesolowski uint8_t fun : 3; 280*80c94ecdSKeith M Wesolowski uint32_t instance; 281*80c94ecdSKeith M Wesolowski dev_info_t *dip; 282*80c94ecdSKeith M Wesolowski 283*80c94ecdSKeith M Wesolowski /* Controller Specific Information */ 284*80c94ecdSKeith M Wesolowski int8_t hba_name[38]; 285*80c94ecdSKeith M Wesolowski ulong_t num_of_targets; 286*80c94ecdSKeith M Wesolowski uint32_t heartbeat; 287*80c94ecdSKeith M Wesolowski uint32_t board_id; 288*80c94ecdSKeith M Wesolowski cpqary3_bd_t *bddef; 289*80c94ecdSKeith M Wesolowski 290*80c94ecdSKeith M Wesolowski /* Condition Variables used */ 291*80c94ecdSKeith M Wesolowski kcondvar_t cv_immediate_wait; 292*80c94ecdSKeith M Wesolowski kcondvar_t cv_noe_wait; 293*80c94ecdSKeith M Wesolowski kcondvar_t cv_flushcache_wait; 294*80c94ecdSKeith M Wesolowski kcondvar_t cv_abort_wait; 295*80c94ecdSKeith M Wesolowski kcondvar_t cv_ioctl_wait; /* Variable for ioctls */ 296*80c94ecdSKeith M Wesolowski 297*80c94ecdSKeith M Wesolowski /* 298*80c94ecdSKeith M Wesolowski * CPQary3 driver related entities related to : 299*80c94ecdSKeith M Wesolowski * Hardware & Software Interrupts, Cookies & Mutex. 300*80c94ecdSKeith M Wesolowski * Timeout Handler 301*80c94ecdSKeith M Wesolowski * Driver Transport Layer/Structure 302*80c94ecdSKeith M Wesolowski * Database for the per-controller Command Memory Pool 303*80c94ecdSKeith M Wesolowski * Target List for the per-controller 304*80c94ecdSKeith M Wesolowski */ 305*80c94ecdSKeith M Wesolowski uint8_t irq; /* h/w IRQ */ 306*80c94ecdSKeith M Wesolowski ddi_iblock_cookie_t hw_iblock_cookie; /* cookie for h/w intr */ 307*80c94ecdSKeith M Wesolowski kmutex_t hw_mutex; /* h/w mutex */ 308*80c94ecdSKeith M Wesolowski ddi_iblock_cookie_t sw_iblock_cookie; /* cookie for s/w intr */ 309*80c94ecdSKeith M Wesolowski kmutex_t sw_mutex; /* s/w mutex */ 310*80c94ecdSKeith M Wesolowski ddi_softintr_t cpqary3_softintr_id; /* s/w intr identifier */ 311*80c94ecdSKeith M Wesolowski uint8_t swintr_flag; 312*80c94ecdSKeith M Wesolowski timeout_id_t tick_tmout_id; /* timeout identifier */ 313*80c94ecdSKeith M Wesolowski uint8_t cpqary3_tick_hdlr; 314*80c94ecdSKeith M Wesolowski scsi_hba_tran_t *hba_tran; /* transport structure */ 315*80c94ecdSKeith M Wesolowski cpqary3_cmdmemlist_t *cmdmemlistp; /* database - Memory Pool */ 316*80c94ecdSKeith M Wesolowski cpqary3_tgt_t *cpqary3_tgtp[CPQARY3_MAX_TGT]; 317*80c94ecdSKeith M Wesolowski cpqary3_drvr_replyq_t *drvr_replyq; 318*80c94ecdSKeith M Wesolowski 319*80c94ecdSKeith M Wesolowski 320*80c94ecdSKeith M Wesolowski uint8_t (*check_ctlr_intr)(CTLR *); 321*80c94ecdSKeith M Wesolowski 322*80c94ecdSKeith M Wesolowski /* 323*80c94ecdSKeith M Wesolowski * PCI Configuration Registers 324*80c94ecdSKeith M Wesolowski * 0x10 Primary I2O Memory BAR - for Host Interface 325*80c94ecdSKeith M Wesolowski * 0x14 Primary DRAM 1 BAR - for Transport Configuration Table 326*80c94ecdSKeith M Wesolowski * 327*80c94ecdSKeith M Wesolowski * Host Interface Registers 328*80c94ecdSKeith M Wesolowski * Offset from Primary I2O Memory BAR 329*80c94ecdSKeith M Wesolowski * 0x20 Inbound Doorbell - for interrupting controller 330*80c94ecdSKeith M Wesolowski * 0x30 Outbound List Status - for signalling status of Reply Q 331*80c94ecdSKeith M Wesolowski * 0x34 Outbound Interrupt Mask - for masking Interrupts to host 332*80c94ecdSKeith M Wesolowski * 0x40 Host Inbound Queue - Request Q 333*80c94ecdSKeith M Wesolowski * 0x44 Host Outbound Queue - reply Q 334*80c94ecdSKeith M Wesolowski * 335*80c94ecdSKeith M Wesolowski * Offset from Primary DRAM 1 BAR 336*80c94ecdSKeith M Wesolowski * 0x00 Configuration Table - for Controller Transport Layer 337*80c94ecdSKeith M Wesolowski */ 338*80c94ecdSKeith M Wesolowski 339*80c94ecdSKeith M Wesolowski uint32_t *idr; 340*80c94ecdSKeith M Wesolowski ddi_acc_handle_t idr_handle; 341*80c94ecdSKeith M Wesolowski 342*80c94ecdSKeith M Wesolowski /* LOCKUP CODE */ 343*80c94ecdSKeith M Wesolowski uint32_t *spr0; 344*80c94ecdSKeith M Wesolowski ddi_acc_handle_t spr0_handle; 345*80c94ecdSKeith M Wesolowski /* LOCKUP CODE */ 346*80c94ecdSKeith M Wesolowski 347*80c94ecdSKeith M Wesolowski uint32_t *odr; 348*80c94ecdSKeith M Wesolowski ddi_acc_handle_t odr_handle; 349*80c94ecdSKeith M Wesolowski 350*80c94ecdSKeith M Wesolowski uint32_t *odr_cl; 351*80c94ecdSKeith M Wesolowski ddi_acc_handle_t odr_cl_handle; 352*80c94ecdSKeith M Wesolowski 353*80c94ecdSKeith M Wesolowski uint32_t *isr; 354*80c94ecdSKeith M Wesolowski ddi_acc_handle_t isr_handle; 355*80c94ecdSKeith M Wesolowski 356*80c94ecdSKeith M Wesolowski uint32_t *imr; 357*80c94ecdSKeith M Wesolowski ddi_acc_handle_t imr_handle; 358*80c94ecdSKeith M Wesolowski 359*80c94ecdSKeith M Wesolowski uint32_t *ipq; 360*80c94ecdSKeith M Wesolowski ddi_acc_handle_t ipq_handle; 361*80c94ecdSKeith M Wesolowski 362*80c94ecdSKeith M Wesolowski uint32_t *opq; 363*80c94ecdSKeith M Wesolowski ddi_acc_handle_t opq_handle; 364*80c94ecdSKeith M Wesolowski 365*80c94ecdSKeith M Wesolowski CfgTable_t *ct; 366*80c94ecdSKeith M Wesolowski ddi_acc_handle_t ct_handle; 367*80c94ecdSKeith M Wesolowski 368*80c94ecdSKeith M Wesolowski CfgTrans_Perf_t *cp; 369*80c94ecdSKeith M Wesolowski ddi_acc_handle_t cp_handle; 370*80c94ecdSKeith M Wesolowski 371*80c94ecdSKeith M Wesolowski uint32_t legacy_mapping; 372*80c94ecdSKeith M Wesolowski uint32_t noe_support; 373*80c94ecdSKeith M Wesolowski /* SG */ 374*80c94ecdSKeith M Wesolowski uint32_t sg_cnt; 375*80c94ecdSKeith M Wesolowski /* SG */ 376*80c94ecdSKeith M Wesolowski uint32_t ctlr_maxcmds; 377*80c94ecdSKeith M Wesolowski uint32_t host_support; 378*80c94ecdSKeith M Wesolowski uint8_t controller_lockup; 379*80c94ecdSKeith M Wesolowski uint8_t lockup_logged; 380*80c94ecdSKeith M Wesolowski uint32_t poll_flag; 381*80c94ecdSKeith M Wesolowski } cpqary3_t; 382*80c94ecdSKeith M Wesolowski 383*80c94ecdSKeith M Wesolowski 384*80c94ecdSKeith M Wesolowski /* 385*80c94ecdSKeith M Wesolowski * Private Structure for Self Issued Commands 386*80c94ecdSKeith M Wesolowski */ 387*80c94ecdSKeith M Wesolowski 388*80c94ecdSKeith M Wesolowski typedef struct cpqary3_driver_private { 389*80c94ecdSKeith M Wesolowski void *sg; 390*80c94ecdSKeith M Wesolowski cpqary3_phyctg_t *phyctgp; 391*80c94ecdSKeith M Wesolowski }cpqary3_private_t; 392*80c94ecdSKeith M Wesolowski 393*80c94ecdSKeith M Wesolowski /* cmd_flags */ 394*80c94ecdSKeith M Wesolowski #define CFLAG_DMASEND 0x01 395*80c94ecdSKeith M Wesolowski #define CFLAG_CMDIOPB 0x02 396*80c94ecdSKeith M Wesolowski #define CFLAG_DMAVALID 0x04 397*80c94ecdSKeith M Wesolowski 398*80c94ecdSKeith M Wesolowski /* 399*80c94ecdSKeith M Wesolowski * Driver Private Packet 400*80c94ecdSKeith M Wesolowski */ 401*80c94ecdSKeith M Wesolowski typedef struct cpqary3_pkt { 402*80c94ecdSKeith M Wesolowski struct scsi_pkt *scsi_cmd_pkt; 403*80c94ecdSKeith M Wesolowski ddi_dma_win_t prev_winp; 404*80c94ecdSKeith M Wesolowski ddi_dma_seg_t prev_segp; 405*80c94ecdSKeith M Wesolowski clock_t cmd_start_time; 406*80c94ecdSKeith M Wesolowski /* SG */ 407*80c94ecdSKeith M Wesolowski ddi_dma_cookie_t cmd_dmacookies[MAX_PERF_SG_CNT]; 408*80c94ecdSKeith M Wesolowski /* SG */ 409*80c94ecdSKeith M Wesolowski uint32_t cmd_ncookies; 410*80c94ecdSKeith M Wesolowski uint32_t cmd_cookie; 411*80c94ecdSKeith M Wesolowski uint32_t cmd_cookiecnt; 412*80c94ecdSKeith M Wesolowski uint32_t cmd_nwin; 413*80c94ecdSKeith M Wesolowski uint32_t cmd_curwin; 414*80c94ecdSKeith M Wesolowski off_t cmd_dma_offset; 415*80c94ecdSKeith M Wesolowski size_t cmd_dma_len; 416*80c94ecdSKeith M Wesolowski size_t cmd_dmacount; 417*80c94ecdSKeith M Wesolowski struct buf *bf; 418*80c94ecdSKeith M Wesolowski ddi_dma_handle_t cmd_dmahandle; 419*80c94ecdSKeith M Wesolowski uint32_t bytes; 420*80c94ecdSKeith M Wesolowski uint32_t cmd_flags; 421*80c94ecdSKeith M Wesolowski uint32_t cdb_len; 422*80c94ecdSKeith M Wesolowski uint32_t scb_len; 423*80c94ecdSKeith M Wesolowski cpqary3_cmdpvt_t *memp; 424*80c94ecdSKeith M Wesolowski } cpqary3_pkt_t; 425*80c94ecdSKeith M Wesolowski 426*80c94ecdSKeith M Wesolowski #pragma pack(1) 427*80c94ecdSKeith M Wesolowski 428*80c94ecdSKeith M Wesolowski typedef struct cpqary3_ioctlresp { 429*80c94ecdSKeith M Wesolowski /* Driver Revision */ 430*80c94ecdSKeith M Wesolowski struct cpqary3_revision { 431*80c94ecdSKeith M Wesolowski uint8_t minor; /* Version */ 432*80c94ecdSKeith M Wesolowski uint8_t major; 433*80c94ecdSKeith M Wesolowski uint8_t mm; /* Revision Date */ 434*80c94ecdSKeith M Wesolowski uint8_t dd; 435*80c94ecdSKeith M Wesolowski uint16_t yyyy; 436*80c94ecdSKeith M Wesolowski } cpqary3_drvrev; 437*80c94ecdSKeith M Wesolowski 438*80c94ecdSKeith M Wesolowski /* HBA Info */ 439*80c94ecdSKeith M Wesolowski struct cpqary3_ctlr { 440*80c94ecdSKeith M Wesolowski uint8_t num_of_tgts; /* No of Logical Drive */ 441*80c94ecdSKeith M Wesolowski uint8_t *name; 442*80c94ecdSKeith M Wesolowski } cpqary3_ctlr; 443*80c94ecdSKeith M Wesolowski } cpqary3_ioctlresp_t; 444*80c94ecdSKeith M Wesolowski 445*80c94ecdSKeith M Wesolowski typedef struct cpqary3_ioctlreq { 446*80c94ecdSKeith M Wesolowski cpqary3_ioctlresp_t *cpqary3_ioctlrespp; 447*80c94ecdSKeith M Wesolowski } cpqary3_ioctlreq_t; 448*80c94ecdSKeith M Wesolowski 449*80c94ecdSKeith M Wesolowski #pragma pack() 450*80c94ecdSKeith M Wesolowski 451*80c94ecdSKeith M Wesolowski /* Driver function definitions */ 452*80c94ecdSKeith M Wesolowski 453*80c94ecdSKeith M Wesolowski void cpqary3_init_hbatran(cpqary3_t *); 454*80c94ecdSKeith M Wesolowski void cpqary3_read_conf_file(dev_info_t *, cpqary3_t *); 455*80c94ecdSKeith M Wesolowski void cpqary3_tick_hdlr(void *); 456*80c94ecdSKeith M Wesolowski void cpqary3_flush_cache(cpqary3_t *); 457*80c94ecdSKeith M Wesolowski void cpqary3_intr_onoff(cpqary3_t *, uint8_t); 458*80c94ecdSKeith M Wesolowski void cpqary3_lockup_intr_onoff(cpqary3_t *, uint8_t); 459*80c94ecdSKeith M Wesolowski uint8_t cpqary3_disable_NOE_command(cpqary3_t *); 460*80c94ecdSKeith M Wesolowski uint8_t cpqary3_send_NOE_command(cpqary3_t *, cpqary3_cmdpvt_t *, uint8_t); 461*80c94ecdSKeith M Wesolowski uint16_t cpqary3_init_ctlr_resource(cpqary3_t *); 462*80c94ecdSKeith M Wesolowski uint32_t cpqary3_hw_isr(caddr_t); 463*80c94ecdSKeith M Wesolowski uint32_t cpqary3_sw_isr(caddr_t); 464*80c94ecdSKeith M Wesolowski int32_t cpqary3_ioctl_driver_info(uintptr_t, int); 465*80c94ecdSKeith M Wesolowski int32_t cpqary3_ioctl_ctlr_info(uintptr_t, cpqary3_t *, int); 466*80c94ecdSKeith M Wesolowski int32_t cpqary3_ioctl_bmic_pass(uintptr_t, cpqary3_t *, int); 467*80c94ecdSKeith M Wesolowski int32_t cpqary3_ioctl_scsi_pass(uintptr_t, cpqary3_t *, int); 468*80c94ecdSKeith M Wesolowski uint8_t cpqary3_probe4targets(cpqary3_t *); 469*80c94ecdSKeith M Wesolowski void cpqary3_cmdlist_release(cpqary3_cmdpvt_t *, uint8_t); 470*80c94ecdSKeith M Wesolowski int32_t cpqary3_submit(cpqary3_t *, uint32_t); 471*80c94ecdSKeith M Wesolowski void cpqary3_free_phyctgs_mem(cpqary3_phyctg_t *, uint8_t); 472*80c94ecdSKeith M Wesolowski caddr_t cpqary3_alloc_phyctgs_mem(cpqary3_t *, size_t, uint32_t *, 473*80c94ecdSKeith M Wesolowski cpqary3_phyctg_t *); 474*80c94ecdSKeith M Wesolowski cpqary3_cmdpvt_t *cpqary3_cmdlist_occupy(cpqary3_t *); 475*80c94ecdSKeith M Wesolowski void cpqary3_synccmd_complete(cpqary3_cmdpvt_t *); 476*80c94ecdSKeith M Wesolowski void cpqary3_NOE_handler(cpqary3_cmdpvt_t *); 477*80c94ecdSKeith M Wesolowski uint8_t cpqary3_retrieve(cpqary3_t *); 478*80c94ecdSKeith M Wesolowski void cpqary3_synccmd_cleanup(cpqary3_cmdpvt_t *); 479*80c94ecdSKeith M Wesolowski int cpqary3_target_geometry(struct scsi_address *); 480*80c94ecdSKeith M Wesolowski uint8_t cpqary3_send_abortcmd(cpqary3_t *, uint16_t, CommandList_t *); 481*80c94ecdSKeith M Wesolowski void cpqary3_memfini(cpqary3_t *, uint8_t); 482*80c94ecdSKeith M Wesolowski uint8_t cpqary3_init_ctlr(cpqary3_t *); 483*80c94ecdSKeith M Wesolowski int16_t cpqary3_meminit(cpqary3_t *); 484*80c94ecdSKeith M Wesolowski void cpqary3_noe_complete(cpqary3_cmdpvt_t *cpqary3_cmdpvtp); 485*80c94ecdSKeith M Wesolowski cpqary3_cmdpvt_t *cpqary3_synccmd_alloc(cpqary3_t *, size_t); 486*80c94ecdSKeith M Wesolowski void cpqary3_synccmd_free(cpqary3_t *, cpqary3_cmdpvt_t *); 487*80c94ecdSKeith M Wesolowski int cpqary3_synccmd_send(cpqary3_t *, cpqary3_cmdpvt_t *, clock_t, int); 488*80c94ecdSKeith M Wesolowski uint8_t cpqary3_poll_retrieve(cpqary3_t *cpqary3p, uint32_t poll_tag); 489*80c94ecdSKeith M Wesolowski uint8_t cpqary3_build_cmdlist(cpqary3_cmdpvt_t *cpqary3_cmdpvtp, uint32_t tid); 490*80c94ecdSKeith M Wesolowski 491*80c94ecdSKeith M Wesolowski #ifdef __cplusplus 492*80c94ecdSKeith M Wesolowski } 493*80c94ecdSKeith M Wesolowski #endif 494*80c94ecdSKeith M Wesolowski 495*80c94ecdSKeith M Wesolowski #endif /* _CPQARY3_H */ 496