1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 #ifndef _QLT_REGS_H 26 #define _QLT_REGS_H 27 28 #include <stmf_defines.h> 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * Register offsets 36 */ 37 #define REG_FLASH_ADDR 0x00 38 #define REG_FLASH_DATA 0x04 39 #define REG_CTRL_STATUS 0x08 40 #define REG_INTR_CTRL 0x0C 41 #define REG_INTR_STATUS 0x10 42 #define REG_REQ_IN_PTR 0x1C 43 #define REG_REQ_OUT_PTR 0x20 44 #define REG_RESP_IN_PTR 0x24 45 #define REG_RESP_OUT_PTR 0x28 46 #define REG_PREQ_IN_PTR 0x2C 47 #define REG_PREQ_OUT_PTR 0x30 48 #define REG_ATIO_IN_PTR 0x3C 49 #define REG_ATIO_OUT_PTR 0x40 50 #define REG_RISC_STATUS 0x44 51 #define REG_HCCR 0x48 52 #define REG_GPIO_DATA 0x4C 53 #define REG_GPIO_ENABLE 0x50 54 #define REG_IOBUS_BASE_ADDR 0x54 55 #define REG_HOST_SEMA 0x58 56 #define REG_MBOX0 0x80 57 58 #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 59 60 #define MAX_MBOXES 32 61 62 /* 63 * Ctrl Status register definitions 64 */ 65 #define FLASH_ERROR BIT_18 66 #define DMA_ACTIVE_STATUS BIT_17 67 #define DMA_SHUTDOWN_CTRL BIT_16 68 #define FUNCTION_NUMBER BIT_15 69 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 70 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 71 #define PCI_64_BIT_SLOT BIT_2 72 #define FLASH_WRITE_ENABLE BIT_1 73 #define CHIP_SOFT_RESET BIT_0 74 75 /* 76 * INTR_CTRL register 77 */ 78 #define ENABLE_RISC_INTR BIT_3 79 80 /* 81 * INTR_STATUS register 82 */ 83 #define RISC_INTR_REQUEST BIT_3 84 85 /* 86 * HCCR commands 87 */ 88 #define HCCR_CMD_NOP 0 89 #define HCCR_CMD_SET_RISC_RESET 0x10000000 90 #define HCCR_CMD_CLEAR_RISC_RESET 0x20000000 91 #define HCCR_CMD_SET_RISC_PAUSE 0x30000000 92 #define HCCR_CMD_CLEAR_RISC_PAUSE 0x40000000 93 #define HCCR_CMD_SET_HOST_TO_RISC_INTR 0x50000000 94 #define HCCR_CMD_CLEAR_HOST_TO_RISC_INTR 0x60000000 95 #define HCCR_CMD_CLEAR_RISC_TO_PCI_INTR 0xA0000000 96 97 /* 98 * Flash/NVRAM definitions 99 */ 100 #define FLASH_DATA_FLAG BIT_31 101 #define FLASH_CONF_ADDR 0x7FFD0000 102 #define FLASH_DATA_ADDR 0x7FF00000 103 #define NVRAM_CONF_ADDR 0x7FFF0000 104 #define NVRAM_DATA_ADDR 0x7FFE0000 105 106 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 107 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 108 109 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 110 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 111 112 typedef struct qlt_nvram { 113 /* NVRAM header. */ 114 uint8_t id[4]; 115 uint8_t nvram_version[2]; 116 uint8_t reserved_0[2]; 117 118 /* Firmware Initialization Control Block. */ 119 uint8_t version[2]; 120 uint8_t reserved_1[2]; 121 uint8_t max_frame_length[2]; 122 uint8_t execution_throttle[2]; 123 uint8_t exchange_count[2]; 124 uint8_t hard_address[2]; 125 uint8_t port_name[8]; 126 uint8_t node_name[8]; 127 uint8_t login_retry_count[2]; 128 uint8_t link_down_on_nos[2]; 129 uint8_t interrupt_delay_timer[2]; 130 uint8_t login_timeout[2]; 131 132 /* 133 * BIT 0 = Hard Assigned Loop ID 134 * BIT 1 = Enable Fairness 135 * BIT 2 = Enable Full-Duplex 136 * BIT 3 = Reserved 137 * BIT 4 = Target Mode Enable 138 * BIT 5 = Initiator Mode Disable 139 * BIT 6 = Reserved 140 * BIT 7 = Reserved 141 * 142 * BIT 8 = Reserved 143 * BIT 9 = Disable Initial LIP 144 * BIT 10 = Descending Loop ID Search 145 * BIT 11 = Previous Assigned Loop ID 146 * BIT 12 = Reserved 147 * BIT 13 = Full Login after LIP 148 * BIT 14 = Node Name Option 149 * BIT 15-31 = Reserved 150 */ 151 uint8_t firmware_options_1[4]; 152 153 /* 154 * BIT 0 = Operation Mode bit 0 155 * BIT 1 = Operation Mode bit 1 156 * BIT 2 = Operation Mode bit 2 157 * BIT 3 = Operation Mode bit 3 158 * BIT 4 = Connection Options bit 0 159 * BIT 5 = Connection Options bit 1 160 * BIT 6 = Connection Options bit 2 161 * BIT 7 = Enable Non part on LIHA failure 162 * 163 * BIT 8 = Enable Class 2 164 * BIT 9 = Enable ACK0 165 * BIT 10 = Reserved 166 * BIT 11 = Enable FC-SP Security 167 * BIT 12 = FC Tape Enable 168 * BIT 13-31 = Reserved 169 */ 170 uint8_t firmware_options_2[4]; 171 172 /* 173 * BIT 0 = Reserved 174 * BIT 1 = Soft ID only 175 * BIT 2 = Reserved 176 * BIT 3 = Reserved 177 * BIT 4 = FCP RSP Payload bit 0 178 * BIT 5 = FCP RSP Payload bit 1 179 * BIT 6 = Enable Rec Out-of-Order data frame handling 180 * BIT 7 = Disable Automatic PLOGI on Local Loop 181 * 182 * BIT 8 = Reserved 183 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 184 * offset handling 185 * BIT 10 = Reserved 186 * BIT 11 = Reserved 187 * BIT 12 = Reserved 188 * BIT 13 = Data Rate bit 0 189 * BIT 14 = Data Rate bit 1 190 * BIT 15 = Data Rate bit 2 191 * BIT 16 = 75-ohm Termination Select 192 * BIT 17-31 = Reserved 193 */ 194 uint8_t firmware_options_3[4]; 195 196 /* 197 * Serial Link Control (offset 56) 198 * BIT 0 = control enable 199 * BIT 1-15 = Reserved 200 */ 201 uint8_t swing_opt[2]; 202 203 /* 204 * Serial Link Control 1G (offset 58) 205 * BIT 0-7 = Reserved 206 * 207 * BIT 8-10 = output swing 208 * BIT 11-13 = output emphasis 209 * BIT 14-15 = Reserved 210 */ 211 uint8_t swing_1g[2]; 212 213 /* 214 * Serial Link Control 2G (offset 60) 215 * BIT 0-7 = Reserved 216 * 217 * BIT 8-10 = output swing 218 * BIT 11-13 = output emphasis 219 * BIT 14-15 = Reserved 220 */ 221 uint8_t swing_2g[2]; 222 223 /* 224 * Serial Link Control 4G (offset 62) 225 * BIT 0-7 = Reserved 226 * 227 * BIT 8-10 = output swing 228 * BIT 11-13 = output emphasis 229 * BIT 14-15 = Reserved 230 */ 231 uint8_t swing_4g[2]; 232 233 /* Offset 64. */ 234 uint8_t reserved_2[32]; 235 236 /* Offset 96. */ 237 uint8_t reserved_3[32]; 238 239 /* PCIe table entries. */ 240 uint8_t reserved_4[32]; 241 242 /* Offset 160. */ 243 uint8_t reserved_5[32]; 244 245 /* Offset 192. */ 246 uint8_t reserved_6[32]; 247 248 /* Offset 224. */ 249 uint8_t reserved_7[32]; 250 251 /* 252 * BIT 0 = Enable spinup delay 253 * BIT 1 = Disable BIOS 254 * BIT 2 = Enable Memory Map BIOS 255 * BIT 3 = Enable Selectable Boot 256 * BIT 4 = Disable RISC code load 257 * BIT 5 = Disable serdes 258 * BIT 6 = Enable opt boot mode 259 * BIT 7 = Enable int mode BIOS 260 * 261 * BIT 8 = 262 * BIT 9 = 263 * BIT 10 = Enable lip full login 264 * BIT 11 = Enable target reset 265 * BIT 12 = 266 * BIT 13 = Default Node Name Option 267 * BIT 14 = Default valid 268 * BIT 15 = Enable alternate WWN 269 * 270 * BIT 16-31 = 271 */ 272 uint8_t host_p[4]; 273 274 uint8_t alternate_port_name[8]; 275 uint8_t alternate_node_name[8]; 276 277 uint8_t boot_port_name[8]; 278 uint8_t boot_lun_number[2]; 279 uint8_t reserved_8[2]; 280 281 uint8_t alt1_boot_port_name[8]; 282 uint8_t alt1_boot_lun_number[2]; 283 uint8_t reserved_9[2]; 284 285 uint8_t alt2_boot_port_name[8]; 286 uint8_t alt2_boot_lun_number[2]; 287 uint8_t reserved_10[2]; 288 289 uint8_t alt3_boot_port_name[8]; 290 uint8_t alt3_boot_lun_number[2]; 291 uint8_t reserved_11[2]; 292 293 /* 294 * BIT 0 = Selective Login 295 * BIT 1 = Alt-Boot Enable 296 * BIT 2 = Reserved 297 * BIT 3 = Enable Boot Order List 298 * BIT 4 = Reserved 299 * BIT 5 = Enable Selective LUN 300 * BIT 6 = Reserved 301 * BIT 7-31 = 302 */ 303 uint8_t efi_parameters[4]; 304 305 uint8_t reset_delay; 306 uint8_t reserved_12; 307 uint8_t reserved_13[2]; 308 309 uint8_t boot_id_number[2]; 310 uint8_t reserved_14[2]; 311 312 uint8_t max_luns_per_target[2]; 313 uint8_t reserved_15[2]; 314 315 uint8_t port_down_retry_count[2]; 316 uint8_t link_down_timeout[2]; 317 318 /* 319 * FCode parameters word (offset 344) 320 * 321 * BIT 0 = Enable BIOS pathname 322 * BIT 1 = fcode qlc 323 * BIT 2 = fcode host 324 * BIT 3-7 = 325 */ 326 uint8_t fcode_p0; 327 uint8_t reserved_16[7]; 328 329 /* Offset 352. */ 330 uint8_t prev_drv_ver_major; 331 uint8_t prev_drv_ver_submajob; 332 uint8_t prev_drv_ver_minor; 333 uint8_t prev_drv_ver_subminor; 334 335 uint8_t prev_bios_ver_major[2]; 336 uint8_t prev_bios_ver_minor[2]; 337 338 uint8_t prev_efi_ver_major[2]; 339 uint8_t prev_efi_ver_minor[2]; 340 341 uint8_t prev_fw_ver_major[2]; 342 uint8_t prev_fw_ver_minor; 343 uint8_t prev_fw_ver_subminor; 344 345 uint8_t reserved_17[16]; 346 347 /* Offset 384. */ 348 uint8_t def_port_name[8]; 349 uint8_t def_node_name[8]; 350 351 uint8_t reserved_18[16]; 352 353 /* Offset 416. */ 354 uint8_t reserved_19[32]; 355 356 /* Offset 448. */ 357 uint8_t reserved_20[28]; 358 359 /* Offset 476. */ 360 uint8_t fw_table_offset[2]; 361 uint8_t fw_table_sig[2]; 362 363 /* Offset 480. */ 364 uint8_t model_name[8]; 365 366 /* Offset 488. */ 367 uint8_t power_table[16]; 368 369 uint8_t subsystem_vendor_id[2]; 370 uint8_t subsystem_device_id[2]; 371 372 uint8_t checksum[4]; 373 } qlt_nvram_t; 374 375 #ifdef __cplusplus 376 } 377 #endif 378 379 #endif /* _QLT_REGS_H */ 380