1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 QLogic Corporation. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 29 * Use is subject to license terms. 30 */ 31 32 #ifndef _QLT_REGS_H 33 #define _QLT_REGS_H 34 35 #include <stmf_defines.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* 42 * Register offsets 43 */ 44 #define REG_FLASH_ADDR 0x00 45 #define REG_FLASH_DATA 0x04 46 #define REG_CTRL_STATUS 0x08 47 #define REG_INTR_CTRL 0x0C 48 #define REG_INTR_STATUS 0x10 49 #define REG_REQ_IN_PTR 0x1C 50 #define REG_REQ_OUT_PTR 0x20 51 #define REG_RESP_IN_PTR 0x24 52 #define REG_RESP_OUT_PTR 0x28 53 #define REG_PREQ_IN_PTR 0x2C 54 #define REG_PREQ_OUT_PTR 0x30 55 #define REG_ATIO_IN_PTR 0x3C 56 #define REG_ATIO_OUT_PTR 0x40 57 #define REG_RISC_STATUS 0x44 58 #define REG_HCCR 0x48 59 #define REG_GPIO_DATA 0x4C 60 #define REG_GPIO_ENABLE 0x50 61 #define REG_IOBUS_BASE_ADDR 0x54 62 #define REG_HOST_SEMA 0x58 63 #define REG_MBOX0 0x80 64 65 #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 66 67 #define MAX_MBOXES 32 68 69 /* 70 * Ctrl Status register definitions 71 */ 72 #define FLASH_ERROR BIT_18 73 #define DMA_ACTIVE_STATUS BIT_17 74 #define DMA_SHUTDOWN_CTRL BIT_16 75 #define FUNCTION_NUMBER BIT_15 76 /* 77 * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12 78 */ 79 #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 80 #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 81 #define PCI_64_BIT_SLOT BIT_2 82 #define FLASH_WRITE_ENABLE BIT_1 83 #define CHIP_SOFT_RESET BIT_0 84 85 /* 86 * INTR_CTRL register 87 */ 88 #define ENABLE_RISC_INTR BIT_3 89 90 /* 91 * INTR_STATUS register 92 */ 93 #define RISC_PCI_INTR_REQUEST BIT_3 94 95 /* 96 * RISC_STATUS register 97 */ 98 #define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \ 99 BIT_11 | BIT_10 | BIT_9 | BIT_8 | \ 100 BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 101 BIT_3 | BIT_2 | BIT_1) 102 #define FW_INTR_INFO_SHIFT 18 103 104 #define FW_INTR_INFO(status) (status & (FW_INTR_INFO_MASK << \ 105 FW_INTR_INFO_SHIFT)) 106 #define RISC_HOST_INTR_REQUEST BIT_15 107 #define RISC_PAUSED BIT_8 108 109 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 110 BIT_3 | BIT_2 | BIT_1 | BIT_0) 111 112 #define ROM_MBX_CMD_SUCCESSFUL 0x01 113 #define ROM_MBX_CMD_NOT_SUCCESSFUL 0x02 114 #define MBX_CMD_SUCCESSFUL 0x10 115 #define MBX_CMD_NOT_SUCCESSFUL 0x11 116 #define ASYNC_EVENT 0x12 117 #define RESP_Q_UPDATE 0x13 118 #define ATIO_Q_UPDATE 0x1c 119 #define RESP_ATIO_Q_UPDATE 0x1d 120 121 /* 122 * Mailbox command completion status. 123 */ 124 #define QLT_MBX_CMD_SUCCESS 0x4000 125 126 /* 127 * HCCR commands 128 */ 129 #define NOP 0x00 130 #define SET_RISC_RESET 0x01 131 #define CLEAR_RISC_RESET 0x02 132 #define SET_RISC_PAUSE 0x03 133 #define CLEAR_RISC_PAUSE 0x04 134 #define SET_HOST_TO_RISC_INTR 0x05 135 #define CLEAR_HOST_TO_RISC_INTR 0x06 136 #define CLEAR_RISC_TO_PCI_INTR 0x0A 137 138 #define HCCR_CMD_SHIFT 28 139 #define HCCR_CMD(cmd) ((uint32_t)cmd << HCCR_CMD_SHIFT) 140 141 #define MBC_STOP_FIRMWARE 0x14 142 143 /* 144 * Flash/NVRAM definitions 145 */ 146 #define FLASH_DATA_FLAG BIT_31 147 #define FLASH_CONF_ADDR 0x7FFD0000 148 #define FLASH_DATA_ADDR 0x7FF00000 149 #define FLASH_DATA_ADDR_81XX 0x7F8D0000 150 #define NVRAM_CONF_ADDR 0x7FFF0000 151 #define NVRAM_DATA_ADDR 0x7FFE0000 152 153 #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 154 #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 155 156 #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 157 #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 158 159 #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80) 160 #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180) 161 162 typedef struct qlt_nvram { 163 /* NVRAM header. */ 164 uint8_t id[4]; 165 uint8_t nvram_version[2]; 166 uint8_t reserved_0[2]; 167 168 /* Firmware Initialization Control Block. */ 169 uint8_t version[2]; 170 uint8_t reserved_1[2]; 171 uint8_t max_frame_length[2]; 172 uint8_t execution_throttle[2]; 173 uint8_t exchange_count[2]; 174 uint8_t hard_address[2]; 175 uint8_t port_name[8]; 176 uint8_t node_name[8]; 177 uint8_t login_retry_count[2]; 178 uint8_t link_down_on_nos[2]; 179 uint8_t interrupt_delay_timer[2]; 180 uint8_t login_timeout[2]; 181 182 /* 183 * BIT 0 = Hard Assigned Loop ID 184 * BIT 1 = Enable Fairness 185 * BIT 2 = Enable Full-Duplex 186 * BIT 3 = Reserved 187 * BIT 4 = Target Mode Enable 188 * BIT 5 = Initiator Mode Disable 189 * BIT 6 = Reserved 190 * BIT 7 = Reserved 191 * 192 * BIT 8 = Reserved 193 * BIT 9 = Disable Initial LIP 194 * BIT 10 = Descending Loop ID Search 195 * BIT 11 = Previous Assigned Loop ID 196 * BIT 12 = Reserved 197 * BIT 13 = Full Login after LIP 198 * BIT 14 = Node Name Option 199 * BIT 15-31 = Reserved 200 */ 201 uint8_t firmware_options_1[4]; 202 203 /* 204 * BIT 0 = Operation Mode bit 0 205 * BIT 1 = Operation Mode bit 1 206 * BIT 2 = Operation Mode bit 2 207 * BIT 3 = Operation Mode bit 3 208 * BIT 4 = Connection Options bit 0 209 * BIT 5 = Connection Options bit 1 210 * BIT 6 = Connection Options bit 2 211 * BIT 7 = Enable Non part on LIHA failure 212 * 213 * BIT 8 = Enable Class 2 214 * BIT 9 = Enable ACK0 215 * BIT 10 = Reserved 216 * BIT 11 = Enable FC-SP Security 217 * BIT 12 = FC Tape Enable 218 * BIT 13-31 = Reserved 219 */ 220 uint8_t firmware_options_2[4]; 221 222 /* 223 * BIT 0 = Reserved 224 * BIT 1 = Soft ID only 225 * BIT 2 = Reserved 226 * BIT 3 = Reserved 227 * BIT 4 = FCP RSP Payload bit 0 228 * BIT 5 = FCP RSP Payload bit 1 229 * BIT 6 = Enable Rec Out-of-Order data frame handling 230 * BIT 7 = Disable Automatic PLOGI on Local Loop 231 * 232 * BIT 8 = Reserved 233 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 234 * offset handling 235 * BIT 10 = Reserved 236 * BIT 11 = Reserved 237 * BIT 12 = Reserved 238 * BIT 13 = Data Rate bit 0 239 * BIT 14 = Data Rate bit 1 240 * BIT 15 = Data Rate bit 2 241 * BIT 16 = 75-ohm Termination Select 242 * BIT 17-31 = Reserved 243 */ 244 uint8_t firmware_options_3[4]; 245 246 /* 247 * Serial Link Control (offset 56) 248 * BIT 0 = control enable 249 * BIT 1-15 = Reserved 250 */ 251 uint8_t swing_opt[2]; 252 253 /* 254 * Serial Link Control 1G (offset 58) 255 * BIT 0-7 = Reserved 256 * 257 * BIT 8-10 = output swing 258 * BIT 11-13 = output emphasis 259 * BIT 14-15 = Reserved 260 */ 261 uint8_t swing_1g[2]; 262 263 /* 264 * Serial Link Control 2G (offset 60) 265 * BIT 0-7 = Reserved 266 * 267 * BIT 8-10 = output swing 268 * BIT 11-13 = output emphasis 269 * BIT 14-15 = Reserved 270 */ 271 uint8_t swing_2g[2]; 272 273 /* 274 * Serial Link Control 4G (offset 62) 275 * BIT 0-7 = Reserved 276 * 277 * BIT 8-10 = output swing 278 * BIT 11-13 = output emphasis 279 * BIT 14-15 = Reserved 280 */ 281 uint8_t swing_4g[2]; 282 283 /* Offset 64. */ 284 uint8_t reserved_2[32]; 285 286 /* Offset 96. */ 287 uint8_t reserved_3[32]; 288 289 /* PCIe table entries. */ 290 uint8_t reserved_4[32]; 291 292 /* Offset 160. */ 293 uint8_t reserved_5[32]; 294 295 /* Offset 192. */ 296 uint8_t reserved_6[32]; 297 298 /* Offset 224. */ 299 uint8_t reserved_7[32]; 300 301 /* 302 * BIT 0 = Enable spinup delay 303 * BIT 1 = Disable BIOS 304 * BIT 2 = Enable Memory Map BIOS 305 * BIT 3 = Enable Selectable Boot 306 * BIT 4 = Disable RISC code load 307 * BIT 5 = Disable serdes 308 * BIT 6 = Enable opt boot mode 309 * BIT 7 = Enable int mode BIOS 310 * 311 * BIT 8 = 312 * BIT 9 = 313 * BIT 10 = Enable lip full login 314 * BIT 11 = Enable target reset 315 * BIT 12 = 316 * BIT 13 = Default Node Name Option 317 * BIT 14 = Default valid 318 * BIT 15 = Enable alternate WWN 319 * 320 * BIT 16-31 = 321 */ 322 uint8_t host_p[4]; 323 324 uint8_t alternate_port_name[8]; 325 uint8_t alternate_node_name[8]; 326 327 uint8_t boot_port_name[8]; 328 uint8_t boot_lun_number[2]; 329 uint8_t reserved_8[2]; 330 331 uint8_t alt1_boot_port_name[8]; 332 uint8_t alt1_boot_lun_number[2]; 333 uint8_t reserved_9[2]; 334 335 uint8_t alt2_boot_port_name[8]; 336 uint8_t alt2_boot_lun_number[2]; 337 uint8_t reserved_10[2]; 338 339 uint8_t alt3_boot_port_name[8]; 340 uint8_t alt3_boot_lun_number[2]; 341 uint8_t reserved_11[2]; 342 343 /* 344 * BIT 0 = Selective Login 345 * BIT 1 = Alt-Boot Enable 346 * BIT 2 = Reserved 347 * BIT 3 = Enable Boot Order List 348 * BIT 4 = Reserved 349 * BIT 5 = Enable Selective LUN 350 * BIT 6 = Reserved 351 * BIT 7-31 = 352 */ 353 uint8_t efi_parameters[4]; 354 355 uint8_t reset_delay; 356 uint8_t reserved_12; 357 uint8_t reserved_13[2]; 358 359 uint8_t boot_id_number[2]; 360 uint8_t reserved_14[2]; 361 362 uint8_t max_luns_per_target[2]; 363 uint8_t reserved_15[2]; 364 365 uint8_t port_down_retry_count[2]; 366 uint8_t link_down_timeout[2]; 367 368 /* 369 * FCode parameters word (offset 344) 370 * 371 * BIT 0 = Enable BIOS pathname 372 * BIT 1 = fcode qlc 373 * BIT 2 = fcode host 374 * BIT 3-7 = 375 */ 376 uint8_t fcode_p0; 377 uint8_t reserved_16[7]; 378 379 /* Offset 352. */ 380 uint8_t prev_drv_ver_major; 381 uint8_t prev_drv_ver_submajob; 382 uint8_t prev_drv_ver_minor; 383 uint8_t prev_drv_ver_subminor; 384 385 uint8_t prev_bios_ver_major[2]; 386 uint8_t prev_bios_ver_minor[2]; 387 388 uint8_t prev_efi_ver_major[2]; 389 uint8_t prev_efi_ver_minor[2]; 390 391 uint8_t prev_fw_ver_major[2]; 392 uint8_t prev_fw_ver_minor; 393 uint8_t prev_fw_ver_subminor; 394 395 uint8_t reserved_17[16]; 396 397 /* Offset 384. */ 398 uint8_t def_port_name[8]; 399 uint8_t def_node_name[8]; 400 401 uint8_t reserved_18[16]; 402 403 /* Offset 416. */ 404 uint8_t reserved_19[32]; 405 406 /* Offset 448. */ 407 uint8_t reserved_20[28]; 408 409 /* Offset 476. */ 410 uint8_t fw_table_offset[2]; 411 uint8_t fw_table_sig[2]; 412 413 /* Offset 480. */ 414 uint8_t model_name[8]; 415 416 /* Offset 488. */ 417 uint8_t power_table[16]; 418 419 uint8_t subsystem_vendor_id[2]; 420 uint8_t subsystem_device_id[2]; 421 422 uint8_t checksum[4]; 423 } qlt_nvram_t; 424 425 /* ISP81xx Extended Initialisation Control Block */ 426 typedef struct qlt_ext_icb_81xx { 427 428 uint8_t version[2]; 429 uint8_t fcf_vlan_match; 430 uint8_t reserved_6[3]; 431 uint8_t fcf_vlan_id[2]; 432 uint8_t fcf_fabric_name[8]; 433 uint8_t reserved_7[14]; 434 uint8_t spma_proposed_mac_address[6]; 435 uint8_t reserved_8[28]; 436 437 } qlt_ext_icb_81xx_t; 438 439 typedef struct qlt_nvram_81xx { 440 /* NVRAM header. */ 441 uint8_t id[4]; 442 uint8_t nvram_version[2]; 443 uint8_t reserved_0[2]; 444 445 /* Firmware Initialization Control Block. */ 446 uint8_t version[2]; 447 uint8_t reserved_1[2]; 448 uint8_t max_frame_length[2]; 449 uint8_t execution_throttle[2]; 450 uint8_t exchange_count[2]; 451 uint8_t reserved_2[2]; 452 uint8_t port_name[8]; 453 uint8_t node_name[8]; 454 uint8_t login_retry_count[2]; 455 uint8_t reserved_3[2]; 456 uint8_t interrupt_delay_timer[2]; 457 uint8_t login_timeout[2]; 458 459 /* 460 * BIT 0 = Hard Assigned Loop ID 461 * BIT 1 = Enable Fairness 462 * BIT 2 = Enable Full-Duplex 463 * BIT 3 = Reserved 464 * BIT 4 = Target Mode Enable 465 * BIT 5 = Initiator Mode Disable 466 * BIT 6 = Reserved 467 * BIT 7 = Reserved 468 * 469 * BIT 8 = Reserved 470 * BIT 9 = Reserved 471 * BIT 10 = Reserved 472 * BIT 11 = Reserved 473 * BIT 12 = Reserved 474 * BIT 13 = Reserved 475 * BIT 14 = Node Name Option 476 * BIT 15-31 = Reserved 477 */ 478 uint8_t firmware_options_1[4]; 479 480 /* 481 * BIT 0 = Operation Mode bit 0 482 * BIT 1 = Operation Mode bit 1 483 * BIT 2 = Operation Mode bit 2 484 * BIT 3 = Operation Mode bit 3 485 * BIT 4 = Reserved 486 * BIT 5 = Reserved 487 * BIT 6 = Reserved 488 * BIT 7 = Reserved 489 * 490 * BIT 8 = Enable Class 2 491 * BIT 9 = Enable ACK0 492 * BIT 10 = Reserved 493 * BIT 11 = Enable FC-SP Security 494 * BIT 12 = FC Tape Enable 495 * BIT 13 = Reserved 496 * BIT 14 = Target PRLI Control 497 * BIT 15-31 = Reserved 498 */ 499 uint8_t firmware_options_2[4]; 500 501 /* 502 * BIT 0 = Reserved 503 * BIT 1 = Soft ID only 504 * BIT 2 = Reserved 505 * BIT 3 = Reserved 506 * BIT 4 = FCP RSP Payload bit 0 507 * BIT 5 = FCP RSP Payload bit 1 508 * BIT 6 = Enable Rec Out-of-Order data frame handling 509 * BIT 7 = Reserved 510 * 511 * BIT 8 = Reserved 512 * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 513 * offset handling 514 * BIT 10 = Reserved 515 * BIT 11 = Reserved 516 * BIT 12 = Reserved 517 * BIT 13 = Reserved 518 * BIT 14 = Reserved 519 * BIT 15 = Reserved 520 * BIT 16 = Reserved 521 * BIT 17 = Enable Multiple FCFs 522 * BIT 18-20 = MAC Addressing Mode 523 * BIT 21-25 = Ethernet Data Rate 524 * BIT 26 = Enable Ethernet Header Receive ATIO_Q 525 * BIT 27 = Enable Ethernet Header Receive RSP_Q 526 * BIT 28-29 = SPMA Selection 527 * BIT 30-31 = Reserved 528 */ 529 uint8_t firmware_options_3[4]; 530 531 /* Offset 56 (38h). */ 532 uint8_t reserved_4[8]; 533 534 /* Offset 64 (40h). */ 535 uint8_t enode_mac[6]; 536 537 /* Offset 70 (46h). */ 538 uint8_t reserved_5[26]; 539 540 /* Offset 96 (60h). */ 541 uint8_t oem_specific; 542 uint8_t reserved_6[15]; 543 544 /* Offset 112 (70h). */ 545 uint8_t reserved_7[16]; 546 547 /* Offset 128 (80h). */ 548 qlt_ext_icb_81xx_t ext_blk; 549 550 /* Offset 192. */ 551 uint8_t reserved_8[32]; 552 553 /* Offset 224. */ 554 uint8_t reserved_9[32]; 555 556 uint8_t host_p[4]; 557 558 uint8_t alternate_port_name[8]; 559 uint8_t alternate_name_name[8]; 560 561 uint8_t boot_port_name[8]; 562 uint8_t boot_lun_number[2]; 563 uint8_t reserved_10[2]; 564 565 uint8_t alt1_boot_port_name[8]; 566 uint8_t alt1_boot_lun_number[2]; 567 uint8_t reserved_11[2]; 568 569 uint8_t alt2_boot_port_name[8]; 570 uint8_t alt2_boot_lun_number[2]; 571 uint8_t reserved_12[2]; 572 573 uint8_t alt3_boot_port_name[8]; 574 uint8_t alt3_boot_lun_number[2]; 575 uint8_t reserved_13[2]; 576 577 /* 578 * BIT 0 = Selective Login 579 * BIT 1 = Alt-Boot Enable 580 * BIT 2 = Reserved 581 * BIT 3 = Enable Boot Order List 582 * BIT 4 = Reserved 583 * BIT 5 = Enable Selective LUN 584 * BIT 6 = Reserved 585 * BIT 7-31 = 586 */ 587 uint8_t efi_parameters[4]; 588 589 uint8_t reset_delay; 590 uint8_t reserved_14; 591 uint8_t reserved_15[2]; 592 593 uint8_t boot_id_number[2]; 594 uint8_t reserved_16[2]; 595 596 uint8_t max_luns_per_target[2]; 597 uint8_t reserved_17[2]; 598 599 uint8_t port_down_retry_count[2]; 600 uint8_t link_down_timeout[2]; 601 602 /* 603 * FCode parameters word (offset 344) 604 * 605 * BIT 0 = Enable BIOS pathname 606 * BIT 1 = fcode qlc 607 * BIT 2 = fcode host 608 * BIT 3-7 = 609 */ 610 uint8_t fcode_parameter[2]; 611 uint8_t reserved_18[6]; 612 613 /* Offset 352. */ 614 uint8_t reserved_19[4]; 615 uint8_t reserved_20[10]; 616 uint8_t reserved_21[2]; 617 uint8_t reserved_22[16]; 618 619 /* Offset 384. */ 620 uint8_t reserved_23[16]; 621 uint8_t reserved_24[16]; 622 623 /* Offset 416. */ 624 uint8_t reserved_25[64]; 625 626 /* Offset 480. */ 627 uint8_t model_name[16]; 628 629 /* Offset 496. */ 630 uint8_t feature_mask_l[2]; 631 uint8_t feature_mask_h[2]; 632 uint8_t reserved_26[4]; 633 634 uint8_t subsystem_vendor_id[2]; 635 uint8_t subsystem_device_id[2]; 636 637 uint8_t checksum[4]; 638 639 } qlt_nvram_81xx_t; 640 641 #ifdef __cplusplus 642 } 643 #endif 644 645 #endif /* _QLT_REGS_H */ 646