1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 QLogic Corporation.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
29  * Use is subject to license terms.
30  */
31 
32 #ifndef	_QLT_REGS_H
33 #define	_QLT_REGS_H
34 
35 #include <stmf_defines.h>
36 
37 #ifdef	__cplusplus
38 extern "C" {
39 #endif
40 
41 /*
42  * Register offsets
43  */
44 #define	REG_FLASH_ADDR		0x00
45 #define	REG_FLASH_DATA		0x04
46 #define	REG_CTRL_STATUS		0x08
47 #define	REG_INTR_CTRL		0x0C
48 #define	REG_INTR_STATUS		0x10
49 #define	REG_REQ_IN_PTR		0x1C
50 #define	REG_REQ_OUT_PTR		0x20
51 #define	REG_RESP_IN_PTR		0x24
52 #define	REG_RESP_OUT_PTR	0x28
53 #define	REG_PREQ_IN_PTR		0x2C
54 #define	REG_PREQ_OUT_PTR	0x30
55 #define	REG_ATIO_IN_PTR		0x3C
56 #define	REG_ATIO_OUT_PTR	0x40
57 #define	REG_RISC_STATUS		0x44
58 #define	REG_HCCR		0x48
59 #define	REG_GPIO_DATA		0x4C
60 #define	REG_GPIO_ENABLE		0x50
61 #define	REG_IOBUS_BASE_ADDR	0x54
62 #define	REG_HOST_SEMA		0x58
63 #define	REG_MBOX0		0x80
64 
65 #define	REG_MBOX(n)		(REG_MBOX0 + (n << 1))
66 
67 #define	MAX_MBOXES		32
68 
69 /*
70  * Ctrl Status register definitions
71  */
72 #define	FLASH_ERROR		BIT_18
73 #define	DMA_ACTIVE_STATUS	BIT_17
74 #define	DMA_SHUTDOWN_CTRL	BIT_16
75 #define	FUNCTION_NUMBER		BIT_15
76 /*
77  * #define	81XX_FUNCTION_NUMBER	BIT_15 | BIT_14 | BIT_13 | BIT_12
78  */
79 #define	PCI_X_BUS_MODE		(BIT_8 | BIT_9 | BIT_10 | BIT_11)
80 #define	PCI_X_XFER_CTRL		(BIT_4 | BIT_5)
81 #define	PCI_64_BIT_SLOT		BIT_2
82 #define	FLASH_WRITE_ENABLE	BIT_1
83 #define	CHIP_SOFT_RESET		BIT_0
84 
85 /*
86  * INTR_CTRL register
87  */
88 #define	ENABLE_RISC_INTR	BIT_3
89 
90 /*
91  * INTR_STATUS register
92  */
93 #define	RISC_INTR_REQUEST	BIT_3
94 
95 /*
96  * HCCR commands
97  */
98 #define	HCCR_CMD_NOP				0
99 #define	HCCR_CMD_SET_RISC_RESET			0x10000000
100 #define	HCCR_CMD_CLEAR_RISC_RESET		0x20000000
101 #define	HCCR_CMD_SET_RISC_PAUSE			0x30000000
102 #define	HCCR_CMD_CLEAR_RISC_PAUSE		0x40000000
103 #define	HCCR_CMD_SET_HOST_TO_RISC_INTR		0x50000000
104 #define	HCCR_CMD_CLEAR_HOST_TO_RISC_INTR	0x60000000
105 #define	HCCR_CMD_CLEAR_RISC_TO_PCI_INTR		0xA0000000
106 
107 /*
108  * Flash/NVRAM definitions
109  */
110 #define	FLASH_DATA_FLAG		BIT_31
111 #define	FLASH_CONF_ADDR		0x7FFD0000
112 #define	FLASH_DATA_ADDR		0x7FF00000
113 #define	FLASH_DATA_ADDR_81XX	0x7F8D0000
114 #define	NVRAM_CONF_ADDR		0x7FFF0000
115 #define	NVRAM_DATA_ADDR		0x7FFE0000
116 
117 #define	NVRAM_FUNC0_ADDR	(NVRAM_DATA_ADDR + 0x80)
118 #define	NVRAM_FUNC1_ADDR	(NVRAM_DATA_ADDR + 0x180)
119 
120 #define	QLT25_NVRAM_FUNC0_ADDR	(FLASH_DATA_ADDR + 0x48080)
121 #define	QLT25_NVRAM_FUNC1_ADDR	(FLASH_DATA_ADDR + 0x48180)
122 
123 #define	QLT81_NVRAM_FUNC0_ADDR	(FLASH_DATA_ADDR_81XX + 0x80)
124 #define	QLT81_NVRAM_FUNC1_ADDR	(FLASH_DATA_ADDR_81XX + 0x180)
125 
126 typedef struct qlt_nvram {
127 	/* NVRAM header. */
128 	uint8_t id[4];
129 	uint8_t nvram_version[2];
130 	uint8_t reserved_0[2];
131 
132 	/* Firmware Initialization Control Block. */
133 	uint8_t version[2];
134 	uint8_t reserved_1[2];
135 	uint8_t max_frame_length[2];
136 	uint8_t execution_throttle[2];
137 	uint8_t exchange_count[2];
138 	uint8_t hard_address[2];
139 	uint8_t port_name[8];
140 	uint8_t node_name[8];
141 	uint8_t login_retry_count[2];
142 	uint8_t link_down_on_nos[2];
143 	uint8_t interrupt_delay_timer[2];
144 	uint8_t login_timeout[2];
145 
146 	/*
147 	 * BIT 0  = Hard Assigned Loop ID
148 	 * BIT 1  = Enable Fairness
149 	 * BIT 2  = Enable Full-Duplex
150 	 * BIT 3  = Reserved
151 	 * BIT 4  = Target Mode Enable
152 	 * BIT 5  = Initiator Mode Disable
153 	 * BIT 6  = Reserved
154 	 * BIT 7  = Reserved
155 	 *
156 	 * BIT 8  = Reserved
157 	 * BIT 9  = Disable Initial LIP
158 	 * BIT 10 = Descending Loop ID Search
159 	 * BIT 11 = Previous Assigned Loop ID
160 	 * BIT 12 = Reserved
161 	 * BIT 13 = Full Login after LIP
162 	 * BIT 14 = Node Name Option
163 	 * BIT 15-31 = Reserved
164 	 */
165 	uint8_t firmware_options_1[4];
166 
167 	/*
168 	 * BIT 0  = Operation Mode bit 0
169 	 * BIT 1  = Operation Mode bit 1
170 	 * BIT 2  = Operation Mode bit 2
171 	 * BIT 3  = Operation Mode bit 3
172 	 * BIT 4  = Connection Options bit 0
173 	 * BIT 5  = Connection Options bit 1
174 	 * BIT 6  = Connection Options bit 2
175 	 * BIT 7  = Enable Non part on LIHA failure
176 	 *
177 	 * BIT 8  = Enable Class 2
178 	 * BIT 9  = Enable ACK0
179 	 * BIT 10 = Reserved
180 	 * BIT 11 = Enable FC-SP Security
181 	 * BIT 12 = FC Tape Enable
182 	 * BIT 13-31 = Reserved
183 	 */
184 	uint8_t firmware_options_2[4];
185 
186 	/*
187 	 * BIT 0  = Reserved
188 	 * BIT 1  = Soft ID only
189 	 * BIT 2  = Reserved
190 	 * BIT 3  = Reserved
191 	 * BIT 4  = FCP RSP Payload bit 0
192 	 * BIT 5  = FCP RSP Payload bit 1
193 	 * BIT 6  = Enable Rec Out-of-Order data frame handling
194 	 * BIT 7  = Disable Automatic PLOGI on Local Loop
195 	 *
196 	 * BIT 8  = Reserved
197 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative
198 	 *	    offset handling
199 	 * BIT 10 = Reserved
200 	 * BIT 11 = Reserved
201 	 * BIT 12 = Reserved
202 	 * BIT 13 = Data Rate bit 0
203 	 * BIT 14 = Data Rate bit 1
204 	 * BIT 15 = Data Rate bit 2
205 	 * BIT 16 = 75-ohm Termination Select
206 	 * BIT 17-31 = Reserved
207 	 */
208 	uint8_t firmware_options_3[4];
209 
210 	/*
211 	 * Serial Link Control (offset 56)
212 	 * BIT 0  = control enable
213 	 * BIT 1-15 = Reserved
214 	 */
215 	uint8_t swing_opt[2];
216 
217 	/*
218 	 * Serial Link Control 1G (offset 58)
219 	 * BIT 0-7   = Reserved
220 	 *
221 	 * BIT 8-10  = output swing
222 	 * BIT 11-13 = output emphasis
223 	 * BIT 14-15 = Reserved
224 	 */
225 	uint8_t swing_1g[2];
226 
227 	/*
228 	 * Serial Link Control 2G (offset 60)
229 	 * BIT 0-7   = Reserved
230 	 *
231 	 * BIT 8-10  = output swing
232 	 * BIT 11-13 = output emphasis
233 	 * BIT 14-15 = Reserved
234 	 */
235 	uint8_t swing_2g[2];
236 
237 	/*
238 	 * Serial Link Control 4G (offset 62)
239 	 * BIT 0-7   = Reserved
240 	 *
241 	 * BIT 8-10  = output swing
242 	 * BIT 11-13 = output emphasis
243 	 * BIT 14-15 = Reserved
244 	 */
245 	uint8_t swing_4g[2];
246 
247 	/* Offset 64. */
248 	uint8_t reserved_2[32];
249 
250 	/* Offset 96. */
251 	uint8_t reserved_3[32];
252 
253 	/* PCIe table entries. */
254 	uint8_t reserved_4[32];
255 
256 	/* Offset 160. */
257 	uint8_t reserved_5[32];
258 
259 	/* Offset 192. */
260 	uint8_t reserved_6[32];
261 
262 	/* Offset 224. */
263 	uint8_t reserved_7[32];
264 
265 	/*
266 	 * BIT 0  = Enable spinup delay
267 	 * BIT 1  = Disable BIOS
268 	 * BIT 2  = Enable Memory Map BIOS
269 	 * BIT 3  = Enable Selectable Boot
270 	 * BIT 4  = Disable RISC code load
271 	 * BIT 5  = Disable serdes
272 	 * BIT 6  = Enable opt boot mode
273 	 * BIT 7  = Enable int mode BIOS
274 	 *
275 	 * BIT 8  =
276 	 * BIT 9  =
277 	 * BIT 10 = Enable lip full login
278 	 * BIT 11 = Enable target reset
279 	 * BIT 12 =
280 	 * BIT 13 = Default Node Name Option
281 	 * BIT 14 = Default valid
282 	 * BIT 15 = Enable alternate WWN
283 	 *
284 	 * BIT 16-31 =
285 	 */
286 	uint8_t host_p[4];
287 
288 	uint8_t alternate_port_name[8];
289 	uint8_t alternate_node_name[8];
290 
291 	uint8_t boot_port_name[8];
292 	uint8_t boot_lun_number[2];
293 	uint8_t reserved_8[2];
294 
295 	uint8_t alt1_boot_port_name[8];
296 	uint8_t alt1_boot_lun_number[2];
297 	uint8_t reserved_9[2];
298 
299 	uint8_t alt2_boot_port_name[8];
300 	uint8_t alt2_boot_lun_number[2];
301 	uint8_t reserved_10[2];
302 
303 	uint8_t alt3_boot_port_name[8];
304 	uint8_t alt3_boot_lun_number[2];
305 	uint8_t reserved_11[2];
306 
307 	/*
308 	 * BIT 0 = Selective Login
309 	 * BIT 1 = Alt-Boot Enable
310 	 * BIT 2 = Reserved
311 	 * BIT 3 = Enable Boot Order List
312 	 * BIT 4 = Reserved
313 	 * BIT 5 = Enable Selective LUN
314 	 * BIT 6 = Reserved
315 	 * BIT 7-31 =
316 	 */
317 	uint8_t efi_parameters[4];
318 
319 	uint8_t reset_delay;
320 	uint8_t reserved_12;
321 	uint8_t reserved_13[2];
322 
323 	uint8_t boot_id_number[2];
324 	uint8_t reserved_14[2];
325 
326 	uint8_t max_luns_per_target[2];
327 	uint8_t reserved_15[2];
328 
329 	uint8_t port_down_retry_count[2];
330 	uint8_t link_down_timeout[2];
331 
332 	/*
333 	 * FCode parameters word (offset 344)
334 	 *
335 	 * BIT 0 = Enable BIOS pathname
336 	 * BIT 1 = fcode qlc
337 	 * BIT 2 = fcode host
338 	 * BIT 3-7 =
339 	 */
340 	uint8_t	fcode_p0;
341 	uint8_t reserved_16[7];
342 
343 	/* Offset 352. */
344 	uint8_t prev_drv_ver_major;
345 	uint8_t prev_drv_ver_submajob;
346 	uint8_t prev_drv_ver_minor;
347 	uint8_t prev_drv_ver_subminor;
348 
349 	uint8_t prev_bios_ver_major[2];
350 	uint8_t prev_bios_ver_minor[2];
351 
352 	uint8_t prev_efi_ver_major[2];
353 	uint8_t prev_efi_ver_minor[2];
354 
355 	uint8_t prev_fw_ver_major[2];
356 	uint8_t prev_fw_ver_minor;
357 	uint8_t prev_fw_ver_subminor;
358 
359 	uint8_t reserved_17[16];
360 
361 	/* Offset 384. */
362 	uint8_t	def_port_name[8];
363 	uint8_t def_node_name[8];
364 
365 	uint8_t reserved_18[16];
366 
367 	/* Offset 416. */
368 	uint8_t reserved_19[32];
369 
370 	/* Offset 448. */
371 	uint8_t reserved_20[28];
372 
373 	/* Offset 476. */
374 	uint8_t	fw_table_offset[2];
375 	uint8_t fw_table_sig[2];
376 
377 	/* Offset 480. */
378 	uint8_t model_name[8];
379 
380 	/* Offset 488. */
381 	uint8_t power_table[16];
382 
383 	uint8_t subsystem_vendor_id[2];
384 	uint8_t subsystem_device_id[2];
385 
386 	uint8_t checksum[4];
387 } qlt_nvram_t;
388 
389 /* ISP81xx Extended Initialisation Control Block */
390 typedef struct qlt_ext_icb_81xx {
391 
392 	uint8_t version[2];
393 	uint8_t fcf_vlan_match;
394 	uint8_t reserved_6[3];
395 	uint8_t fcf_vlan_id[2];
396 	uint8_t fcf_fabric_name[8];
397 	uint8_t reserved_7[14];
398 	uint8_t spma_proposed_mac_address[6];
399 	uint8_t reserved_8[28];
400 
401 } qlt_ext_icb_81xx_t;
402 
403 typedef struct qlt_nvram_81xx {
404 	/* NVRAM header. */
405 	uint8_t id[4];
406 	uint8_t nvram_version[2];
407 	uint8_t reserved_0[2];
408 
409 	/* Firmware Initialization Control Block. */
410 	uint8_t version[2];
411 	uint8_t reserved_1[2];
412 	uint8_t max_frame_length[2];
413 	uint8_t execution_throttle[2];
414 	uint8_t exchange_count[2];
415 	uint8_t reserved_2[2];
416 	uint8_t port_name[8];
417 	uint8_t node_name[8];
418 	uint8_t login_retry_count[2];
419 	uint8_t reserved_3[2];
420 	uint8_t interrupt_delay_timer[2];
421 	uint8_t login_timeout[2];
422 
423 	/*
424 	 * BIT 0  = Hard Assigned Loop ID
425 	 * BIT 1  = Enable Fairness
426 	 * BIT 2  = Enable Full-Duplex
427 	 * BIT 3  = Reserved
428 	 * BIT 4  = Target Mode Enable
429 	 * BIT 5  = Initiator Mode Disable
430 	 * BIT 6  = Reserved
431 	 * BIT 7  = Reserved
432 	 *
433 	 * BIT 8  = Reserved
434 	 * BIT 9  = Reserved
435 	 * BIT 10 = Reserved
436 	 * BIT 11 = Reserved
437 	 * BIT 12 = Reserved
438 	 * BIT 13 = Reserved
439 	 * BIT 14 = Node Name Option
440 	 * BIT 15-31 = Reserved
441 	 */
442 	uint8_t firmware_options_1[4];
443 
444 	/*
445 	 * BIT 0  = Operation Mode bit 0
446 	 * BIT 1  = Operation Mode bit 1
447 	 * BIT 2  = Operation Mode bit 2
448 	 * BIT 3  = Operation Mode bit 3
449 	 * BIT 4  = Reserved
450 	 * BIT 5  = Reserved
451 	 * BIT 6  = Reserved
452 	 * BIT 7  = Reserved
453 	 *
454 	 * BIT 8  = Enable Class 2
455 	 * BIT 9  = Enable ACK0
456 	 * BIT 10 = Reserved
457 	 * BIT 11 = Enable FC-SP Security
458 	 * BIT 12 = FC Tape Enable
459 	 * BIT 13 = Reserved
460 	 * BIT 14 = Target PRLI Control
461 	 * BIT 15-31 = Reserved
462 	 */
463 	uint8_t firmware_options_2[4];
464 
465 	/*
466 	 * BIT 0  = Reserved
467 	 * BIT 1  = Soft ID only
468 	 * BIT 2  = Reserved
469 	 * BIT 3  = Reserved
470 	 * BIT 4  = FCP RSP Payload bit 0
471 	 * BIT 5  = FCP RSP Payload bit 1
472 	 * BIT 6  = Enable Rec Out-of-Order data frame handling
473 	 * BIT 7  = Reserved
474 	 *
475 	 * BIT 8  = Reserved
476 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative
477 	 *	    offset handling
478 	 * BIT 10 = Reserved
479 	 * BIT 11 = Reserved
480 	 * BIT 12 = Reserved
481 	 * BIT 13 = Reserved
482 	 * BIT 14 = Reserved
483 	 * BIT 15 = Reserved
484 	 * BIT 16 = Reserved
485 	 * BIT 17 = Enable Multiple FCFs
486 	 * BIT 18-20 = MAC Addressing Mode
487 	 * BIT 21-25 = Ethernet Data Rate
488 	 * BIT 26 = Enable Ethernet Header Receive ATIO_Q
489 	 * BIT 27 = Enable Ethernet Header Receive RSP_Q
490 	 * BIT 28-29 = SPMA Selection
491 	 * BIT 30-31 = Reserved
492 	 */
493 	uint8_t firmware_options_3[4];
494 
495 	/* Offset 56 (38h). */
496 	uint8_t reserved_4[8];
497 
498 	/* Offset 64 (40h). */
499 	uint8_t enode_mac[6];
500 
501 	/* Offset 70 (46h). */
502 	uint8_t reserved_5[26];
503 
504 	/* Offset 96 (60h). */
505 	uint8_t oem_specific;
506 	uint8_t reserved_6[15];
507 
508 	/* Offset 112 (70h). */
509 	uint8_t reserved_7[16];
510 
511 	/* Offset 128 (80h). */
512 	qlt_ext_icb_81xx_t   ext_blk;
513 
514 	/* Offset 192. */
515 	uint8_t reserved_8[32];
516 
517 	/* Offset 224. */
518 	uint8_t reserved_9[32];
519 
520 	uint8_t host_p[4];
521 
522 	uint8_t alternate_port_name[8];
523 	uint8_t alternate_name_name[8];
524 
525 	uint8_t boot_port_name[8];
526 	uint8_t boot_lun_number[2];
527 	uint8_t reserved_10[2];
528 
529 	uint8_t alt1_boot_port_name[8];
530 	uint8_t alt1_boot_lun_number[2];
531 	uint8_t reserved_11[2];
532 
533 	uint8_t alt2_boot_port_name[8];
534 	uint8_t alt2_boot_lun_number[2];
535 	uint8_t reserved_12[2];
536 
537 	uint8_t alt3_boot_port_name[8];
538 	uint8_t alt3_boot_lun_number[2];
539 	uint8_t reserved_13[2];
540 
541 	/*
542 	 * BIT 0 = Selective Login
543 	 * BIT 1 = Alt-Boot Enable
544 	 * BIT 2 = Reserved
545 	 * BIT 3 = Enable Boot Order List
546 	 * BIT 4 = Reserved
547 	 * BIT 5 = Enable Selective LUN
548 	 * BIT 6 = Reserved
549 	 * BIT 7-31 =
550 	 */
551 	uint8_t efi_parameters[4];
552 
553 	uint8_t reset_delay;
554 	uint8_t reserved_14;
555 	uint8_t reserved_15[2];
556 
557 	uint8_t boot_id_number[2];
558 	uint8_t reserved_16[2];
559 
560 	uint8_t max_luns_per_target[2];
561 	uint8_t reserved_17[2];
562 
563 	uint8_t port_down_retry_count[2];
564 	uint8_t link_down_timeout[2];
565 
566 	/*
567 	 * FCode parameters word (offset 344)
568 	 *
569 	 * BIT 0 = Enable BIOS pathname
570 	 * BIT 1 = fcode qlc
571 	 * BIT 2 = fcode host
572 	 * BIT 3-7 =
573 	 */
574 	uint8_t	fcode_parameter[2];
575 	uint8_t reserved_18[6];
576 
577 	/* Offset 352. */
578 	uint8_t reserved_19[4];
579 	uint8_t reserved_20[10];
580 	uint8_t reserved_21[2];
581 	uint8_t reserved_22[16];
582 
583 	/* Offset 384. */
584 	uint8_t	reserved_23[16];
585 	uint8_t reserved_24[16];
586 
587 	/* Offset 416. */
588 	uint8_t reserved_25[64];
589 
590 	/* Offset 480. */
591 	uint8_t model_name[16];
592 
593 	/* Offset 496. */
594 	uint8_t feature_mask_l[2];
595 	uint8_t feature_mask_h[2];
596 	uint8_t reserved_26[4];
597 
598 	uint8_t subsystem_vendor_id[2];
599 	uint8_t subsystem_device_id[2];
600 
601 	uint8_t checksum[4];
602 
603 } qlt_nvram_81xx_t;
604 
605 #ifdef	__cplusplus
606 }
607 #endif
608 
609 #endif /* _QLT_REGS_H */
610