1fcf3ce44SJohn Forte /* 2fcf3ce44SJohn Forte * CDDL HEADER START 3fcf3ce44SJohn Forte * 4fcf3ce44SJohn Forte * The contents of this file are subject to the terms of the 5fcf3ce44SJohn Forte * Common Development and Distribution License (the "License"). 6fcf3ce44SJohn Forte * You may not use this file except in compliance with the License. 7fcf3ce44SJohn Forte * 8fcf3ce44SJohn Forte * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9fcf3ce44SJohn Forte * or http://www.opensolaris.org/os/licensing. 10fcf3ce44SJohn Forte * See the License for the specific language governing permissions 11fcf3ce44SJohn Forte * and limitations under the License. 12fcf3ce44SJohn Forte * 13fcf3ce44SJohn Forte * When distributing Covered Code, include this CDDL HEADER in each 14fcf3ce44SJohn Forte * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15fcf3ce44SJohn Forte * If applicable, add the following below this CDDL HEADER, with the 16fcf3ce44SJohn Forte * fields enclosed by brackets "[]" replaced with your own identifying 17fcf3ce44SJohn Forte * information: Portions Copyright [yyyy] [name of copyright owner] 18fcf3ce44SJohn Forte * 19fcf3ce44SJohn Forte * CDDL HEADER END 20fcf3ce44SJohn Forte */ 21c4ddbbe1SDaniel Beauregard 22c4ddbbe1SDaniel Beauregard /* 23c4ddbbe1SDaniel Beauregard * Copyright 2009 QLogic Corporation. All rights reserved. 24c4ddbbe1SDaniel Beauregard * Use is subject to license terms. 25c4ddbbe1SDaniel Beauregard */ 26c4ddbbe1SDaniel Beauregard 27fcf3ce44SJohn Forte /* 28*4558d122SViswanathan Kannappan * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 29fcf3ce44SJohn Forte */ 30c4ddbbe1SDaniel Beauregard 31fcf3ce44SJohn Forte #ifndef _QLT_REGS_H 32fcf3ce44SJohn Forte #define _QLT_REGS_H 33fcf3ce44SJohn Forte 34*4558d122SViswanathan Kannappan #include <sys/stmf_defines.h> 35fcf3ce44SJohn Forte 36fcf3ce44SJohn Forte #ifdef __cplusplus 37fcf3ce44SJohn Forte extern "C" { 38fcf3ce44SJohn Forte #endif 39fcf3ce44SJohn Forte 40fcf3ce44SJohn Forte /* 41fcf3ce44SJohn Forte * Register offsets 42fcf3ce44SJohn Forte */ 43fcf3ce44SJohn Forte #define REG_FLASH_ADDR 0x00 44fcf3ce44SJohn Forte #define REG_FLASH_DATA 0x04 45fcf3ce44SJohn Forte #define REG_CTRL_STATUS 0x08 46fcf3ce44SJohn Forte #define REG_INTR_CTRL 0x0C 47fcf3ce44SJohn Forte #define REG_INTR_STATUS 0x10 48fcf3ce44SJohn Forte #define REG_REQ_IN_PTR 0x1C 49fcf3ce44SJohn Forte #define REG_REQ_OUT_PTR 0x20 50fcf3ce44SJohn Forte #define REG_RESP_IN_PTR 0x24 51fcf3ce44SJohn Forte #define REG_RESP_OUT_PTR 0x28 52fcf3ce44SJohn Forte #define REG_PREQ_IN_PTR 0x2C 53fcf3ce44SJohn Forte #define REG_PREQ_OUT_PTR 0x30 54fcf3ce44SJohn Forte #define REG_ATIO_IN_PTR 0x3C 55fcf3ce44SJohn Forte #define REG_ATIO_OUT_PTR 0x40 56fcf3ce44SJohn Forte #define REG_RISC_STATUS 0x44 57fcf3ce44SJohn Forte #define REG_HCCR 0x48 58fcf3ce44SJohn Forte #define REG_GPIO_DATA 0x4C 59fcf3ce44SJohn Forte #define REG_GPIO_ENABLE 0x50 60fcf3ce44SJohn Forte #define REG_IOBUS_BASE_ADDR 0x54 61fcf3ce44SJohn Forte #define REG_HOST_SEMA 0x58 62fcf3ce44SJohn Forte #define REG_MBOX0 0x80 63fcf3ce44SJohn Forte 64fcf3ce44SJohn Forte #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 65fcf3ce44SJohn Forte 66fcf3ce44SJohn Forte #define MAX_MBOXES 32 67fcf3ce44SJohn Forte 68fcf3ce44SJohn Forte /* 69fcf3ce44SJohn Forte * Ctrl Status register definitions 70fcf3ce44SJohn Forte */ 71fcf3ce44SJohn Forte #define FLASH_ERROR BIT_18 72fcf3ce44SJohn Forte #define DMA_ACTIVE_STATUS BIT_17 73fcf3ce44SJohn Forte #define DMA_SHUTDOWN_CTRL BIT_16 74fcf3ce44SJohn Forte #define FUNCTION_NUMBER BIT_15 75c4ddbbe1SDaniel Beauregard /* 76c4ddbbe1SDaniel Beauregard * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12 77c4ddbbe1SDaniel Beauregard */ 78fcf3ce44SJohn Forte #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 79fcf3ce44SJohn Forte #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 80fcf3ce44SJohn Forte #define PCI_64_BIT_SLOT BIT_2 81fcf3ce44SJohn Forte #define FLASH_WRITE_ENABLE BIT_1 82fcf3ce44SJohn Forte #define CHIP_SOFT_RESET BIT_0 83fcf3ce44SJohn Forte 84fcf3ce44SJohn Forte /* 85fcf3ce44SJohn Forte * INTR_CTRL register 86fcf3ce44SJohn Forte */ 87fcf3ce44SJohn Forte #define ENABLE_RISC_INTR BIT_3 88fcf3ce44SJohn Forte 89fcf3ce44SJohn Forte /* 90fcf3ce44SJohn Forte * INTR_STATUS register 91fcf3ce44SJohn Forte */ 92a2255df3SDaniel Beauregard #define RISC_PCI_INTR_REQUEST BIT_3 93fcf3ce44SJohn Forte 940ff6bfafSDaniel Beauregard /* 950ff6bfafSDaniel Beauregard * RISC_STATUS register 960ff6bfafSDaniel Beauregard */ 97a2255df3SDaniel Beauregard #define FW_INTR_INFO_MASK (BIT_15 | BIT_14 | BIT_13 | BIT_12 | \ 98a2255df3SDaniel Beauregard BIT_11 | BIT_10 | BIT_9 | BIT_8 | \ 99a2255df3SDaniel Beauregard BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 100a2255df3SDaniel Beauregard BIT_3 | BIT_2 | BIT_1) 101a2255df3SDaniel Beauregard #define FW_INTR_INFO_SHIFT 18 102a2255df3SDaniel Beauregard 103a2255df3SDaniel Beauregard #define FW_INTR_INFO(status) (status & (FW_INTR_INFO_MASK << \ 104a2255df3SDaniel Beauregard FW_INTR_INFO_SHIFT)) 105a2255df3SDaniel Beauregard #define RISC_HOST_INTR_REQUEST BIT_15 106a2255df3SDaniel Beauregard #define RISC_PAUSED BIT_8 107a2255df3SDaniel Beauregard 108a2255df3SDaniel Beauregard #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \ 109a2255df3SDaniel Beauregard BIT_3 | BIT_2 | BIT_1 | BIT_0) 110a2255df3SDaniel Beauregard 111a2255df3SDaniel Beauregard #define ROM_MBX_CMD_SUCCESSFUL 0x01 112a2255df3SDaniel Beauregard #define ROM_MBX_CMD_NOT_SUCCESSFUL 0x02 113a2255df3SDaniel Beauregard #define MBX_CMD_SUCCESSFUL 0x10 114a2255df3SDaniel Beauregard #define MBX_CMD_NOT_SUCCESSFUL 0x11 115a2255df3SDaniel Beauregard #define ASYNC_EVENT 0x12 116a2255df3SDaniel Beauregard #define RESP_Q_UPDATE 0x13 117a2255df3SDaniel Beauregard #define ATIO_Q_UPDATE 0x1c 118a2255df3SDaniel Beauregard #define RESP_ATIO_Q_UPDATE 0x1d 119a2255df3SDaniel Beauregard 120a2255df3SDaniel Beauregard /* 121a2255df3SDaniel Beauregard * Mailbox command completion status. 122a2255df3SDaniel Beauregard */ 123a2255df3SDaniel Beauregard #define QLT_MBX_CMD_SUCCESS 0x4000 1240ff6bfafSDaniel Beauregard 125fcf3ce44SJohn Forte /* 126fcf3ce44SJohn Forte * HCCR commands 127fcf3ce44SJohn Forte */ 128a2255df3SDaniel Beauregard #define NOP 0x00 129a2255df3SDaniel Beauregard #define SET_RISC_RESET 0x01 130a2255df3SDaniel Beauregard #define CLEAR_RISC_RESET 0x02 131a2255df3SDaniel Beauregard #define SET_RISC_PAUSE 0x03 132a2255df3SDaniel Beauregard #define CLEAR_RISC_PAUSE 0x04 133a2255df3SDaniel Beauregard #define SET_HOST_TO_RISC_INTR 0x05 134a2255df3SDaniel Beauregard #define CLEAR_HOST_TO_RISC_INTR 0x06 135a2255df3SDaniel Beauregard #define CLEAR_RISC_TO_PCI_INTR 0x0A 136a2255df3SDaniel Beauregard 137a2255df3SDaniel Beauregard #define HCCR_CMD_SHIFT 28 138a2255df3SDaniel Beauregard #define HCCR_CMD(cmd) ((uint32_t)cmd << HCCR_CMD_SHIFT) 139fcf3ce44SJohn Forte 140a2255df3SDaniel Beauregard #define MBC_STOP_FIRMWARE 0x14 1410ff6bfafSDaniel Beauregard 142fcf3ce44SJohn Forte /* 143fcf3ce44SJohn Forte * Flash/NVRAM definitions 144fcf3ce44SJohn Forte */ 145a2255df3SDaniel Beauregard #define FLASH_DATA_FLAG BIT_31 146a2255df3SDaniel Beauregard #define FLASH_CONF_ADDR 0x7FFD0000 147a2255df3SDaniel Beauregard #define FLASH_DATA_ADDR 0x7FF00000 148a2255df3SDaniel Beauregard #define FLASH_DATA_ADDR_81XX 0x7F8D0000 149a2255df3SDaniel Beauregard #define NVRAM_CONF_ADDR 0x7FFF0000 150a2255df3SDaniel Beauregard #define NVRAM_DATA_ADDR 0x7FFE0000 151fcf3ce44SJohn Forte 152a2255df3SDaniel Beauregard #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 153a2255df3SDaniel Beauregard #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 154fcf3ce44SJohn Forte 155a2255df3SDaniel Beauregard #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 156a2255df3SDaniel Beauregard #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 157fcf3ce44SJohn Forte 158a2255df3SDaniel Beauregard #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80) 159a2255df3SDaniel Beauregard #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180) 160c4ddbbe1SDaniel Beauregard 161fcf3ce44SJohn Forte typedef struct qlt_nvram { 162fcf3ce44SJohn Forte /* NVRAM header. */ 163fcf3ce44SJohn Forte uint8_t id[4]; 164fcf3ce44SJohn Forte uint8_t nvram_version[2]; 165fcf3ce44SJohn Forte uint8_t reserved_0[2]; 166fcf3ce44SJohn Forte 167fcf3ce44SJohn Forte /* Firmware Initialization Control Block. */ 168fcf3ce44SJohn Forte uint8_t version[2]; 169fcf3ce44SJohn Forte uint8_t reserved_1[2]; 170fcf3ce44SJohn Forte uint8_t max_frame_length[2]; 171fcf3ce44SJohn Forte uint8_t execution_throttle[2]; 172fcf3ce44SJohn Forte uint8_t exchange_count[2]; 173fcf3ce44SJohn Forte uint8_t hard_address[2]; 174fcf3ce44SJohn Forte uint8_t port_name[8]; 175fcf3ce44SJohn Forte uint8_t node_name[8]; 176fcf3ce44SJohn Forte uint8_t login_retry_count[2]; 177fcf3ce44SJohn Forte uint8_t link_down_on_nos[2]; 178fcf3ce44SJohn Forte uint8_t interrupt_delay_timer[2]; 179fcf3ce44SJohn Forte uint8_t login_timeout[2]; 180fcf3ce44SJohn Forte 181fcf3ce44SJohn Forte /* 182fcf3ce44SJohn Forte * BIT 0 = Hard Assigned Loop ID 183fcf3ce44SJohn Forte * BIT 1 = Enable Fairness 184fcf3ce44SJohn Forte * BIT 2 = Enable Full-Duplex 185fcf3ce44SJohn Forte * BIT 3 = Reserved 186fcf3ce44SJohn Forte * BIT 4 = Target Mode Enable 187fcf3ce44SJohn Forte * BIT 5 = Initiator Mode Disable 188fcf3ce44SJohn Forte * BIT 6 = Reserved 189fcf3ce44SJohn Forte * BIT 7 = Reserved 190fcf3ce44SJohn Forte * 191fcf3ce44SJohn Forte * BIT 8 = Reserved 192fcf3ce44SJohn Forte * BIT 9 = Disable Initial LIP 193fcf3ce44SJohn Forte * BIT 10 = Descending Loop ID Search 194fcf3ce44SJohn Forte * BIT 11 = Previous Assigned Loop ID 195fcf3ce44SJohn Forte * BIT 12 = Reserved 196fcf3ce44SJohn Forte * BIT 13 = Full Login after LIP 197fcf3ce44SJohn Forte * BIT 14 = Node Name Option 198fcf3ce44SJohn Forte * BIT 15-31 = Reserved 199fcf3ce44SJohn Forte */ 200fcf3ce44SJohn Forte uint8_t firmware_options_1[4]; 201fcf3ce44SJohn Forte 202fcf3ce44SJohn Forte /* 203fcf3ce44SJohn Forte * BIT 0 = Operation Mode bit 0 204fcf3ce44SJohn Forte * BIT 1 = Operation Mode bit 1 205fcf3ce44SJohn Forte * BIT 2 = Operation Mode bit 2 206fcf3ce44SJohn Forte * BIT 3 = Operation Mode bit 3 207fcf3ce44SJohn Forte * BIT 4 = Connection Options bit 0 208fcf3ce44SJohn Forte * BIT 5 = Connection Options bit 1 209fcf3ce44SJohn Forte * BIT 6 = Connection Options bit 2 210fcf3ce44SJohn Forte * BIT 7 = Enable Non part on LIHA failure 211fcf3ce44SJohn Forte * 212fcf3ce44SJohn Forte * BIT 8 = Enable Class 2 213fcf3ce44SJohn Forte * BIT 9 = Enable ACK0 214fcf3ce44SJohn Forte * BIT 10 = Reserved 215fcf3ce44SJohn Forte * BIT 11 = Enable FC-SP Security 216fcf3ce44SJohn Forte * BIT 12 = FC Tape Enable 217fcf3ce44SJohn Forte * BIT 13-31 = Reserved 218fcf3ce44SJohn Forte */ 219fcf3ce44SJohn Forte uint8_t firmware_options_2[4]; 220fcf3ce44SJohn Forte 221fcf3ce44SJohn Forte /* 222fcf3ce44SJohn Forte * BIT 0 = Reserved 223fcf3ce44SJohn Forte * BIT 1 = Soft ID only 224fcf3ce44SJohn Forte * BIT 2 = Reserved 225fcf3ce44SJohn Forte * BIT 3 = Reserved 226fcf3ce44SJohn Forte * BIT 4 = FCP RSP Payload bit 0 227fcf3ce44SJohn Forte * BIT 5 = FCP RSP Payload bit 1 228fcf3ce44SJohn Forte * BIT 6 = Enable Rec Out-of-Order data frame handling 229fcf3ce44SJohn Forte * BIT 7 = Disable Automatic PLOGI on Local Loop 230fcf3ce44SJohn Forte * 231fcf3ce44SJohn Forte * BIT 8 = Reserved 232fcf3ce44SJohn Forte * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 233fcf3ce44SJohn Forte * offset handling 234fcf3ce44SJohn Forte * BIT 10 = Reserved 235fcf3ce44SJohn Forte * BIT 11 = Reserved 236fcf3ce44SJohn Forte * BIT 12 = Reserved 237fcf3ce44SJohn Forte * BIT 13 = Data Rate bit 0 238fcf3ce44SJohn Forte * BIT 14 = Data Rate bit 1 239fcf3ce44SJohn Forte * BIT 15 = Data Rate bit 2 240fcf3ce44SJohn Forte * BIT 16 = 75-ohm Termination Select 241fcf3ce44SJohn Forte * BIT 17-31 = Reserved 242fcf3ce44SJohn Forte */ 243fcf3ce44SJohn Forte uint8_t firmware_options_3[4]; 244fcf3ce44SJohn Forte 245fcf3ce44SJohn Forte /* 246fcf3ce44SJohn Forte * Serial Link Control (offset 56) 247fcf3ce44SJohn Forte * BIT 0 = control enable 248fcf3ce44SJohn Forte * BIT 1-15 = Reserved 249fcf3ce44SJohn Forte */ 250fcf3ce44SJohn Forte uint8_t swing_opt[2]; 251fcf3ce44SJohn Forte 252fcf3ce44SJohn Forte /* 253fcf3ce44SJohn Forte * Serial Link Control 1G (offset 58) 254fcf3ce44SJohn Forte * BIT 0-7 = Reserved 255fcf3ce44SJohn Forte * 256fcf3ce44SJohn Forte * BIT 8-10 = output swing 257fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 258fcf3ce44SJohn Forte * BIT 14-15 = Reserved 259fcf3ce44SJohn Forte */ 260fcf3ce44SJohn Forte uint8_t swing_1g[2]; 261fcf3ce44SJohn Forte 262fcf3ce44SJohn Forte /* 263fcf3ce44SJohn Forte * Serial Link Control 2G (offset 60) 264fcf3ce44SJohn Forte * BIT 0-7 = Reserved 265fcf3ce44SJohn Forte * 266fcf3ce44SJohn Forte * BIT 8-10 = output swing 267fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 268fcf3ce44SJohn Forte * BIT 14-15 = Reserved 269fcf3ce44SJohn Forte */ 270fcf3ce44SJohn Forte uint8_t swing_2g[2]; 271fcf3ce44SJohn Forte 272fcf3ce44SJohn Forte /* 273fcf3ce44SJohn Forte * Serial Link Control 4G (offset 62) 274fcf3ce44SJohn Forte * BIT 0-7 = Reserved 275fcf3ce44SJohn Forte * 276fcf3ce44SJohn Forte * BIT 8-10 = output swing 277fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 278fcf3ce44SJohn Forte * BIT 14-15 = Reserved 279fcf3ce44SJohn Forte */ 280fcf3ce44SJohn Forte uint8_t swing_4g[2]; 281fcf3ce44SJohn Forte 282fcf3ce44SJohn Forte /* Offset 64. */ 283fcf3ce44SJohn Forte uint8_t reserved_2[32]; 284fcf3ce44SJohn Forte 285fcf3ce44SJohn Forte /* Offset 96. */ 286fcf3ce44SJohn Forte uint8_t reserved_3[32]; 287fcf3ce44SJohn Forte 288fcf3ce44SJohn Forte /* PCIe table entries. */ 289fcf3ce44SJohn Forte uint8_t reserved_4[32]; 290fcf3ce44SJohn Forte 291fcf3ce44SJohn Forte /* Offset 160. */ 292fcf3ce44SJohn Forte uint8_t reserved_5[32]; 293fcf3ce44SJohn Forte 294fcf3ce44SJohn Forte /* Offset 192. */ 295fcf3ce44SJohn Forte uint8_t reserved_6[32]; 296fcf3ce44SJohn Forte 297fcf3ce44SJohn Forte /* Offset 224. */ 298fcf3ce44SJohn Forte uint8_t reserved_7[32]; 299fcf3ce44SJohn Forte 300fcf3ce44SJohn Forte /* 301fcf3ce44SJohn Forte * BIT 0 = Enable spinup delay 302fcf3ce44SJohn Forte * BIT 1 = Disable BIOS 303fcf3ce44SJohn Forte * BIT 2 = Enable Memory Map BIOS 304fcf3ce44SJohn Forte * BIT 3 = Enable Selectable Boot 305fcf3ce44SJohn Forte * BIT 4 = Disable RISC code load 306fcf3ce44SJohn Forte * BIT 5 = Disable serdes 307fcf3ce44SJohn Forte * BIT 6 = Enable opt boot mode 308fcf3ce44SJohn Forte * BIT 7 = Enable int mode BIOS 309fcf3ce44SJohn Forte * 310fcf3ce44SJohn Forte * BIT 8 = 311fcf3ce44SJohn Forte * BIT 9 = 312fcf3ce44SJohn Forte * BIT 10 = Enable lip full login 313fcf3ce44SJohn Forte * BIT 11 = Enable target reset 314fcf3ce44SJohn Forte * BIT 12 = 315fcf3ce44SJohn Forte * BIT 13 = Default Node Name Option 316fcf3ce44SJohn Forte * BIT 14 = Default valid 317fcf3ce44SJohn Forte * BIT 15 = Enable alternate WWN 318fcf3ce44SJohn Forte * 319fcf3ce44SJohn Forte * BIT 16-31 = 320fcf3ce44SJohn Forte */ 321fcf3ce44SJohn Forte uint8_t host_p[4]; 322fcf3ce44SJohn Forte 323fcf3ce44SJohn Forte uint8_t alternate_port_name[8]; 324fcf3ce44SJohn Forte uint8_t alternate_node_name[8]; 325fcf3ce44SJohn Forte 326fcf3ce44SJohn Forte uint8_t boot_port_name[8]; 327fcf3ce44SJohn Forte uint8_t boot_lun_number[2]; 328fcf3ce44SJohn Forte uint8_t reserved_8[2]; 329fcf3ce44SJohn Forte 330fcf3ce44SJohn Forte uint8_t alt1_boot_port_name[8]; 331fcf3ce44SJohn Forte uint8_t alt1_boot_lun_number[2]; 332fcf3ce44SJohn Forte uint8_t reserved_9[2]; 333fcf3ce44SJohn Forte 334fcf3ce44SJohn Forte uint8_t alt2_boot_port_name[8]; 335fcf3ce44SJohn Forte uint8_t alt2_boot_lun_number[2]; 336fcf3ce44SJohn Forte uint8_t reserved_10[2]; 337fcf3ce44SJohn Forte 338fcf3ce44SJohn Forte uint8_t alt3_boot_port_name[8]; 339fcf3ce44SJohn Forte uint8_t alt3_boot_lun_number[2]; 340fcf3ce44SJohn Forte uint8_t reserved_11[2]; 341fcf3ce44SJohn Forte 342fcf3ce44SJohn Forte /* 343fcf3ce44SJohn Forte * BIT 0 = Selective Login 344fcf3ce44SJohn Forte * BIT 1 = Alt-Boot Enable 345fcf3ce44SJohn Forte * BIT 2 = Reserved 346fcf3ce44SJohn Forte * BIT 3 = Enable Boot Order List 347fcf3ce44SJohn Forte * BIT 4 = Reserved 348fcf3ce44SJohn Forte * BIT 5 = Enable Selective LUN 349fcf3ce44SJohn Forte * BIT 6 = Reserved 350fcf3ce44SJohn Forte * BIT 7-31 = 351fcf3ce44SJohn Forte */ 352fcf3ce44SJohn Forte uint8_t efi_parameters[4]; 353fcf3ce44SJohn Forte 354fcf3ce44SJohn Forte uint8_t reset_delay; 355fcf3ce44SJohn Forte uint8_t reserved_12; 356fcf3ce44SJohn Forte uint8_t reserved_13[2]; 357fcf3ce44SJohn Forte 358fcf3ce44SJohn Forte uint8_t boot_id_number[2]; 359fcf3ce44SJohn Forte uint8_t reserved_14[2]; 360fcf3ce44SJohn Forte 361fcf3ce44SJohn Forte uint8_t max_luns_per_target[2]; 362fcf3ce44SJohn Forte uint8_t reserved_15[2]; 363fcf3ce44SJohn Forte 364fcf3ce44SJohn Forte uint8_t port_down_retry_count[2]; 365fcf3ce44SJohn Forte uint8_t link_down_timeout[2]; 366fcf3ce44SJohn Forte 367fcf3ce44SJohn Forte /* 368fcf3ce44SJohn Forte * FCode parameters word (offset 344) 369fcf3ce44SJohn Forte * 370fcf3ce44SJohn Forte * BIT 0 = Enable BIOS pathname 371fcf3ce44SJohn Forte * BIT 1 = fcode qlc 372fcf3ce44SJohn Forte * BIT 2 = fcode host 373fcf3ce44SJohn Forte * BIT 3-7 = 374fcf3ce44SJohn Forte */ 375fcf3ce44SJohn Forte uint8_t fcode_p0; 376fcf3ce44SJohn Forte uint8_t reserved_16[7]; 377fcf3ce44SJohn Forte 378fcf3ce44SJohn Forte /* Offset 352. */ 379fcf3ce44SJohn Forte uint8_t prev_drv_ver_major; 380fcf3ce44SJohn Forte uint8_t prev_drv_ver_submajob; 381fcf3ce44SJohn Forte uint8_t prev_drv_ver_minor; 382fcf3ce44SJohn Forte uint8_t prev_drv_ver_subminor; 383fcf3ce44SJohn Forte 384fcf3ce44SJohn Forte uint8_t prev_bios_ver_major[2]; 385fcf3ce44SJohn Forte uint8_t prev_bios_ver_minor[2]; 386fcf3ce44SJohn Forte 387fcf3ce44SJohn Forte uint8_t prev_efi_ver_major[2]; 388fcf3ce44SJohn Forte uint8_t prev_efi_ver_minor[2]; 389fcf3ce44SJohn Forte 390fcf3ce44SJohn Forte uint8_t prev_fw_ver_major[2]; 391fcf3ce44SJohn Forte uint8_t prev_fw_ver_minor; 392fcf3ce44SJohn Forte uint8_t prev_fw_ver_subminor; 393fcf3ce44SJohn Forte 394fcf3ce44SJohn Forte uint8_t reserved_17[16]; 395fcf3ce44SJohn Forte 396fcf3ce44SJohn Forte /* Offset 384. */ 397fcf3ce44SJohn Forte uint8_t def_port_name[8]; 398fcf3ce44SJohn Forte uint8_t def_node_name[8]; 399fcf3ce44SJohn Forte 400fcf3ce44SJohn Forte uint8_t reserved_18[16]; 401fcf3ce44SJohn Forte 402fcf3ce44SJohn Forte /* Offset 416. */ 403fcf3ce44SJohn Forte uint8_t reserved_19[32]; 404fcf3ce44SJohn Forte 405fcf3ce44SJohn Forte /* Offset 448. */ 406fcf3ce44SJohn Forte uint8_t reserved_20[28]; 407fcf3ce44SJohn Forte 408fcf3ce44SJohn Forte /* Offset 476. */ 409fcf3ce44SJohn Forte uint8_t fw_table_offset[2]; 410fcf3ce44SJohn Forte uint8_t fw_table_sig[2]; 411fcf3ce44SJohn Forte 412fcf3ce44SJohn Forte /* Offset 480. */ 413fcf3ce44SJohn Forte uint8_t model_name[8]; 414fcf3ce44SJohn Forte 415fcf3ce44SJohn Forte /* Offset 488. */ 416fcf3ce44SJohn Forte uint8_t power_table[16]; 417fcf3ce44SJohn Forte 418fcf3ce44SJohn Forte uint8_t subsystem_vendor_id[2]; 419fcf3ce44SJohn Forte uint8_t subsystem_device_id[2]; 420fcf3ce44SJohn Forte 421fcf3ce44SJohn Forte uint8_t checksum[4]; 422fcf3ce44SJohn Forte } qlt_nvram_t; 423fcf3ce44SJohn Forte 424c4ddbbe1SDaniel Beauregard /* ISP81xx Extended Initialisation Control Block */ 425c4ddbbe1SDaniel Beauregard typedef struct qlt_ext_icb_81xx { 426c4ddbbe1SDaniel Beauregard 427c4ddbbe1SDaniel Beauregard uint8_t version[2]; 428c4ddbbe1SDaniel Beauregard uint8_t fcf_vlan_match; 429c4ddbbe1SDaniel Beauregard uint8_t reserved_6[3]; 430c4ddbbe1SDaniel Beauregard uint8_t fcf_vlan_id[2]; 431c4ddbbe1SDaniel Beauregard uint8_t fcf_fabric_name[8]; 432c4ddbbe1SDaniel Beauregard uint8_t reserved_7[14]; 433c4ddbbe1SDaniel Beauregard uint8_t spma_proposed_mac_address[6]; 434c4ddbbe1SDaniel Beauregard uint8_t reserved_8[28]; 435c4ddbbe1SDaniel Beauregard 436c4ddbbe1SDaniel Beauregard } qlt_ext_icb_81xx_t; 437c4ddbbe1SDaniel Beauregard 438c4ddbbe1SDaniel Beauregard typedef struct qlt_nvram_81xx { 439c4ddbbe1SDaniel Beauregard /* NVRAM header. */ 440c4ddbbe1SDaniel Beauregard uint8_t id[4]; 441c4ddbbe1SDaniel Beauregard uint8_t nvram_version[2]; 442c4ddbbe1SDaniel Beauregard uint8_t reserved_0[2]; 443c4ddbbe1SDaniel Beauregard 444c4ddbbe1SDaniel Beauregard /* Firmware Initialization Control Block. */ 445c4ddbbe1SDaniel Beauregard uint8_t version[2]; 446c4ddbbe1SDaniel Beauregard uint8_t reserved_1[2]; 447c4ddbbe1SDaniel Beauregard uint8_t max_frame_length[2]; 448c4ddbbe1SDaniel Beauregard uint8_t execution_throttle[2]; 449c4ddbbe1SDaniel Beauregard uint8_t exchange_count[2]; 450c4ddbbe1SDaniel Beauregard uint8_t reserved_2[2]; 451c4ddbbe1SDaniel Beauregard uint8_t port_name[8]; 452c4ddbbe1SDaniel Beauregard uint8_t node_name[8]; 453c4ddbbe1SDaniel Beauregard uint8_t login_retry_count[2]; 454c4ddbbe1SDaniel Beauregard uint8_t reserved_3[2]; 455c4ddbbe1SDaniel Beauregard uint8_t interrupt_delay_timer[2]; 456c4ddbbe1SDaniel Beauregard uint8_t login_timeout[2]; 457c4ddbbe1SDaniel Beauregard 458c4ddbbe1SDaniel Beauregard /* 459c4ddbbe1SDaniel Beauregard * BIT 0 = Hard Assigned Loop ID 460c4ddbbe1SDaniel Beauregard * BIT 1 = Enable Fairness 461c4ddbbe1SDaniel Beauregard * BIT 2 = Enable Full-Duplex 462c4ddbbe1SDaniel Beauregard * BIT 3 = Reserved 463c4ddbbe1SDaniel Beauregard * BIT 4 = Target Mode Enable 464c4ddbbe1SDaniel Beauregard * BIT 5 = Initiator Mode Disable 465c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 466c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 467c4ddbbe1SDaniel Beauregard * 468c4ddbbe1SDaniel Beauregard * BIT 8 = Reserved 469c4ddbbe1SDaniel Beauregard * BIT 9 = Reserved 470c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 471c4ddbbe1SDaniel Beauregard * BIT 11 = Reserved 472c4ddbbe1SDaniel Beauregard * BIT 12 = Reserved 473c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 474c4ddbbe1SDaniel Beauregard * BIT 14 = Node Name Option 475c4ddbbe1SDaniel Beauregard * BIT 15-31 = Reserved 476c4ddbbe1SDaniel Beauregard */ 477c4ddbbe1SDaniel Beauregard uint8_t firmware_options_1[4]; 478c4ddbbe1SDaniel Beauregard 479c4ddbbe1SDaniel Beauregard /* 480c4ddbbe1SDaniel Beauregard * BIT 0 = Operation Mode bit 0 481c4ddbbe1SDaniel Beauregard * BIT 1 = Operation Mode bit 1 482c4ddbbe1SDaniel Beauregard * BIT 2 = Operation Mode bit 2 483c4ddbbe1SDaniel Beauregard * BIT 3 = Operation Mode bit 3 484c4ddbbe1SDaniel Beauregard * BIT 4 = Reserved 485c4ddbbe1SDaniel Beauregard * BIT 5 = Reserved 486c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 487c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 488c4ddbbe1SDaniel Beauregard * 489c4ddbbe1SDaniel Beauregard * BIT 8 = Enable Class 2 490c4ddbbe1SDaniel Beauregard * BIT 9 = Enable ACK0 491c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 492c4ddbbe1SDaniel Beauregard * BIT 11 = Enable FC-SP Security 493c4ddbbe1SDaniel Beauregard * BIT 12 = FC Tape Enable 494c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 495c4ddbbe1SDaniel Beauregard * BIT 14 = Target PRLI Control 496c4ddbbe1SDaniel Beauregard * BIT 15-31 = Reserved 497c4ddbbe1SDaniel Beauregard */ 498c4ddbbe1SDaniel Beauregard uint8_t firmware_options_2[4]; 499c4ddbbe1SDaniel Beauregard 500c4ddbbe1SDaniel Beauregard /* 501c4ddbbe1SDaniel Beauregard * BIT 0 = Reserved 502c4ddbbe1SDaniel Beauregard * BIT 1 = Soft ID only 503c4ddbbe1SDaniel Beauregard * BIT 2 = Reserved 504c4ddbbe1SDaniel Beauregard * BIT 3 = Reserved 505c4ddbbe1SDaniel Beauregard * BIT 4 = FCP RSP Payload bit 0 506c4ddbbe1SDaniel Beauregard * BIT 5 = FCP RSP Payload bit 1 507c4ddbbe1SDaniel Beauregard * BIT 6 = Enable Rec Out-of-Order data frame handling 508c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 509c4ddbbe1SDaniel Beauregard * 510c4ddbbe1SDaniel Beauregard * BIT 8 = Reserved 511c4ddbbe1SDaniel Beauregard * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 512c4ddbbe1SDaniel Beauregard * offset handling 513c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 514c4ddbbe1SDaniel Beauregard * BIT 11 = Reserved 515c4ddbbe1SDaniel Beauregard * BIT 12 = Reserved 516c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 517c4ddbbe1SDaniel Beauregard * BIT 14 = Reserved 518c4ddbbe1SDaniel Beauregard * BIT 15 = Reserved 519c4ddbbe1SDaniel Beauregard * BIT 16 = Reserved 520c4ddbbe1SDaniel Beauregard * BIT 17 = Enable Multiple FCFs 521c4ddbbe1SDaniel Beauregard * BIT 18-20 = MAC Addressing Mode 522c4ddbbe1SDaniel Beauregard * BIT 21-25 = Ethernet Data Rate 523c4ddbbe1SDaniel Beauregard * BIT 26 = Enable Ethernet Header Receive ATIO_Q 524c4ddbbe1SDaniel Beauregard * BIT 27 = Enable Ethernet Header Receive RSP_Q 525c4ddbbe1SDaniel Beauregard * BIT 28-29 = SPMA Selection 526c4ddbbe1SDaniel Beauregard * BIT 30-31 = Reserved 527c4ddbbe1SDaniel Beauregard */ 528c4ddbbe1SDaniel Beauregard uint8_t firmware_options_3[4]; 529c4ddbbe1SDaniel Beauregard 530c4ddbbe1SDaniel Beauregard /* Offset 56 (38h). */ 531c4ddbbe1SDaniel Beauregard uint8_t reserved_4[8]; 532c4ddbbe1SDaniel Beauregard 533c4ddbbe1SDaniel Beauregard /* Offset 64 (40h). */ 534c4ddbbe1SDaniel Beauregard uint8_t enode_mac[6]; 535c4ddbbe1SDaniel Beauregard 536c4ddbbe1SDaniel Beauregard /* Offset 70 (46h). */ 537c4ddbbe1SDaniel Beauregard uint8_t reserved_5[26]; 538c4ddbbe1SDaniel Beauregard 539c4ddbbe1SDaniel Beauregard /* Offset 96 (60h). */ 540c4ddbbe1SDaniel Beauregard uint8_t oem_specific; 541c4ddbbe1SDaniel Beauregard uint8_t reserved_6[15]; 542c4ddbbe1SDaniel Beauregard 543c4ddbbe1SDaniel Beauregard /* Offset 112 (70h). */ 544c4ddbbe1SDaniel Beauregard uint8_t reserved_7[16]; 545c4ddbbe1SDaniel Beauregard 546c4ddbbe1SDaniel Beauregard /* Offset 128 (80h). */ 547c4ddbbe1SDaniel Beauregard qlt_ext_icb_81xx_t ext_blk; 548c4ddbbe1SDaniel Beauregard 549c4ddbbe1SDaniel Beauregard /* Offset 192. */ 550c4ddbbe1SDaniel Beauregard uint8_t reserved_8[32]; 551c4ddbbe1SDaniel Beauregard 552c4ddbbe1SDaniel Beauregard /* Offset 224. */ 553c4ddbbe1SDaniel Beauregard uint8_t reserved_9[32]; 554c4ddbbe1SDaniel Beauregard 555c4ddbbe1SDaniel Beauregard uint8_t host_p[4]; 556c4ddbbe1SDaniel Beauregard 557c4ddbbe1SDaniel Beauregard uint8_t alternate_port_name[8]; 558c4ddbbe1SDaniel Beauregard uint8_t alternate_name_name[8]; 559c4ddbbe1SDaniel Beauregard 560c4ddbbe1SDaniel Beauregard uint8_t boot_port_name[8]; 561c4ddbbe1SDaniel Beauregard uint8_t boot_lun_number[2]; 562c4ddbbe1SDaniel Beauregard uint8_t reserved_10[2]; 563c4ddbbe1SDaniel Beauregard 564c4ddbbe1SDaniel Beauregard uint8_t alt1_boot_port_name[8]; 565c4ddbbe1SDaniel Beauregard uint8_t alt1_boot_lun_number[2]; 566c4ddbbe1SDaniel Beauregard uint8_t reserved_11[2]; 567c4ddbbe1SDaniel Beauregard 568c4ddbbe1SDaniel Beauregard uint8_t alt2_boot_port_name[8]; 569c4ddbbe1SDaniel Beauregard uint8_t alt2_boot_lun_number[2]; 570c4ddbbe1SDaniel Beauregard uint8_t reserved_12[2]; 571c4ddbbe1SDaniel Beauregard 572c4ddbbe1SDaniel Beauregard uint8_t alt3_boot_port_name[8]; 573c4ddbbe1SDaniel Beauregard uint8_t alt3_boot_lun_number[2]; 574c4ddbbe1SDaniel Beauregard uint8_t reserved_13[2]; 575c4ddbbe1SDaniel Beauregard 576c4ddbbe1SDaniel Beauregard /* 577c4ddbbe1SDaniel Beauregard * BIT 0 = Selective Login 578c4ddbbe1SDaniel Beauregard * BIT 1 = Alt-Boot Enable 579c4ddbbe1SDaniel Beauregard * BIT 2 = Reserved 580c4ddbbe1SDaniel Beauregard * BIT 3 = Enable Boot Order List 581c4ddbbe1SDaniel Beauregard * BIT 4 = Reserved 582c4ddbbe1SDaniel Beauregard * BIT 5 = Enable Selective LUN 583c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 584c4ddbbe1SDaniel Beauregard * BIT 7-31 = 585c4ddbbe1SDaniel Beauregard */ 586c4ddbbe1SDaniel Beauregard uint8_t efi_parameters[4]; 587c4ddbbe1SDaniel Beauregard 588c4ddbbe1SDaniel Beauregard uint8_t reset_delay; 589c4ddbbe1SDaniel Beauregard uint8_t reserved_14; 590c4ddbbe1SDaniel Beauregard uint8_t reserved_15[2]; 591c4ddbbe1SDaniel Beauregard 592c4ddbbe1SDaniel Beauregard uint8_t boot_id_number[2]; 593c4ddbbe1SDaniel Beauregard uint8_t reserved_16[2]; 594c4ddbbe1SDaniel Beauregard 595c4ddbbe1SDaniel Beauregard uint8_t max_luns_per_target[2]; 596c4ddbbe1SDaniel Beauregard uint8_t reserved_17[2]; 597c4ddbbe1SDaniel Beauregard 598c4ddbbe1SDaniel Beauregard uint8_t port_down_retry_count[2]; 599c4ddbbe1SDaniel Beauregard uint8_t link_down_timeout[2]; 600c4ddbbe1SDaniel Beauregard 601c4ddbbe1SDaniel Beauregard /* 602c4ddbbe1SDaniel Beauregard * FCode parameters word (offset 344) 603c4ddbbe1SDaniel Beauregard * 604c4ddbbe1SDaniel Beauregard * BIT 0 = Enable BIOS pathname 605c4ddbbe1SDaniel Beauregard * BIT 1 = fcode qlc 606c4ddbbe1SDaniel Beauregard * BIT 2 = fcode host 607c4ddbbe1SDaniel Beauregard * BIT 3-7 = 608c4ddbbe1SDaniel Beauregard */ 609c4ddbbe1SDaniel Beauregard uint8_t fcode_parameter[2]; 610c4ddbbe1SDaniel Beauregard uint8_t reserved_18[6]; 611c4ddbbe1SDaniel Beauregard 612c4ddbbe1SDaniel Beauregard /* Offset 352. */ 613c4ddbbe1SDaniel Beauregard uint8_t reserved_19[4]; 614c4ddbbe1SDaniel Beauregard uint8_t reserved_20[10]; 615c4ddbbe1SDaniel Beauregard uint8_t reserved_21[2]; 616c4ddbbe1SDaniel Beauregard uint8_t reserved_22[16]; 617c4ddbbe1SDaniel Beauregard 618c4ddbbe1SDaniel Beauregard /* Offset 384. */ 619c4ddbbe1SDaniel Beauregard uint8_t reserved_23[16]; 620c4ddbbe1SDaniel Beauregard uint8_t reserved_24[16]; 621c4ddbbe1SDaniel Beauregard 622c4ddbbe1SDaniel Beauregard /* Offset 416. */ 623c4ddbbe1SDaniel Beauregard uint8_t reserved_25[64]; 624c4ddbbe1SDaniel Beauregard 625c4ddbbe1SDaniel Beauregard /* Offset 480. */ 626c4ddbbe1SDaniel Beauregard uint8_t model_name[16]; 627c4ddbbe1SDaniel Beauregard 628c4ddbbe1SDaniel Beauregard /* Offset 496. */ 629c4ddbbe1SDaniel Beauregard uint8_t feature_mask_l[2]; 630c4ddbbe1SDaniel Beauregard uint8_t feature_mask_h[2]; 631c4ddbbe1SDaniel Beauregard uint8_t reserved_26[4]; 632c4ddbbe1SDaniel Beauregard 633c4ddbbe1SDaniel Beauregard uint8_t subsystem_vendor_id[2]; 634c4ddbbe1SDaniel Beauregard uint8_t subsystem_device_id[2]; 635c4ddbbe1SDaniel Beauregard 636c4ddbbe1SDaniel Beauregard uint8_t checksum[4]; 637c4ddbbe1SDaniel Beauregard 638c4ddbbe1SDaniel Beauregard } qlt_nvram_81xx_t; 639c4ddbbe1SDaniel Beauregard 640fcf3ce44SJohn Forte #ifdef __cplusplus 641fcf3ce44SJohn Forte } 642fcf3ce44SJohn Forte #endif 643fcf3ce44SJohn Forte 644fcf3ce44SJohn Forte #endif /* _QLT_REGS_H */ 645