1fcf3ce44SJohn Forte /* 2fcf3ce44SJohn Forte * CDDL HEADER START 3fcf3ce44SJohn Forte * 4fcf3ce44SJohn Forte * The contents of this file are subject to the terms of the 5fcf3ce44SJohn Forte * Common Development and Distribution License (the "License"). 6fcf3ce44SJohn Forte * You may not use this file except in compliance with the License. 7fcf3ce44SJohn Forte * 8fcf3ce44SJohn Forte * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9fcf3ce44SJohn Forte * or http://www.opensolaris.org/os/licensing. 10fcf3ce44SJohn Forte * See the License for the specific language governing permissions 11fcf3ce44SJohn Forte * and limitations under the License. 12fcf3ce44SJohn Forte * 13fcf3ce44SJohn Forte * When distributing Covered Code, include this CDDL HEADER in each 14fcf3ce44SJohn Forte * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15fcf3ce44SJohn Forte * If applicable, add the following below this CDDL HEADER, with the 16fcf3ce44SJohn Forte * fields enclosed by brackets "[]" replaced with your own identifying 17fcf3ce44SJohn Forte * information: Portions Copyright [yyyy] [name of copyright owner] 18fcf3ce44SJohn Forte * 19fcf3ce44SJohn Forte * CDDL HEADER END 20fcf3ce44SJohn Forte */ 21*c4ddbbe1SDaniel Beauregard 22*c4ddbbe1SDaniel Beauregard /* 23*c4ddbbe1SDaniel Beauregard * Copyright 2009 QLogic Corporation. All rights reserved. 24*c4ddbbe1SDaniel Beauregard * Use is subject to license terms. 25*c4ddbbe1SDaniel Beauregard */ 26*c4ddbbe1SDaniel Beauregard 27fcf3ce44SJohn Forte /* 28fcf3ce44SJohn Forte * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 29fcf3ce44SJohn Forte * Use is subject to license terms. 30fcf3ce44SJohn Forte */ 31*c4ddbbe1SDaniel Beauregard 32fcf3ce44SJohn Forte #ifndef _QLT_REGS_H 33fcf3ce44SJohn Forte #define _QLT_REGS_H 34fcf3ce44SJohn Forte 35fcf3ce44SJohn Forte #include <stmf_defines.h> 36fcf3ce44SJohn Forte 37fcf3ce44SJohn Forte #ifdef __cplusplus 38fcf3ce44SJohn Forte extern "C" { 39fcf3ce44SJohn Forte #endif 40fcf3ce44SJohn Forte 41fcf3ce44SJohn Forte /* 42fcf3ce44SJohn Forte * Register offsets 43fcf3ce44SJohn Forte */ 44fcf3ce44SJohn Forte #define REG_FLASH_ADDR 0x00 45fcf3ce44SJohn Forte #define REG_FLASH_DATA 0x04 46fcf3ce44SJohn Forte #define REG_CTRL_STATUS 0x08 47fcf3ce44SJohn Forte #define REG_INTR_CTRL 0x0C 48fcf3ce44SJohn Forte #define REG_INTR_STATUS 0x10 49fcf3ce44SJohn Forte #define REG_REQ_IN_PTR 0x1C 50fcf3ce44SJohn Forte #define REG_REQ_OUT_PTR 0x20 51fcf3ce44SJohn Forte #define REG_RESP_IN_PTR 0x24 52fcf3ce44SJohn Forte #define REG_RESP_OUT_PTR 0x28 53fcf3ce44SJohn Forte #define REG_PREQ_IN_PTR 0x2C 54fcf3ce44SJohn Forte #define REG_PREQ_OUT_PTR 0x30 55fcf3ce44SJohn Forte #define REG_ATIO_IN_PTR 0x3C 56fcf3ce44SJohn Forte #define REG_ATIO_OUT_PTR 0x40 57fcf3ce44SJohn Forte #define REG_RISC_STATUS 0x44 58fcf3ce44SJohn Forte #define REG_HCCR 0x48 59fcf3ce44SJohn Forte #define REG_GPIO_DATA 0x4C 60fcf3ce44SJohn Forte #define REG_GPIO_ENABLE 0x50 61fcf3ce44SJohn Forte #define REG_IOBUS_BASE_ADDR 0x54 62fcf3ce44SJohn Forte #define REG_HOST_SEMA 0x58 63fcf3ce44SJohn Forte #define REG_MBOX0 0x80 64fcf3ce44SJohn Forte 65fcf3ce44SJohn Forte #define REG_MBOX(n) (REG_MBOX0 + (n << 1)) 66fcf3ce44SJohn Forte 67fcf3ce44SJohn Forte #define MAX_MBOXES 32 68fcf3ce44SJohn Forte 69fcf3ce44SJohn Forte /* 70fcf3ce44SJohn Forte * Ctrl Status register definitions 71fcf3ce44SJohn Forte */ 72fcf3ce44SJohn Forte #define FLASH_ERROR BIT_18 73fcf3ce44SJohn Forte #define DMA_ACTIVE_STATUS BIT_17 74fcf3ce44SJohn Forte #define DMA_SHUTDOWN_CTRL BIT_16 75fcf3ce44SJohn Forte #define FUNCTION_NUMBER BIT_15 76*c4ddbbe1SDaniel Beauregard /* 77*c4ddbbe1SDaniel Beauregard * #define 81XX_FUNCTION_NUMBER BIT_15 | BIT_14 | BIT_13 | BIT_12 78*c4ddbbe1SDaniel Beauregard */ 79fcf3ce44SJohn Forte #define PCI_X_BUS_MODE (BIT_8 | BIT_9 | BIT_10 | BIT_11) 80fcf3ce44SJohn Forte #define PCI_X_XFER_CTRL (BIT_4 | BIT_5) 81fcf3ce44SJohn Forte #define PCI_64_BIT_SLOT BIT_2 82fcf3ce44SJohn Forte #define FLASH_WRITE_ENABLE BIT_1 83fcf3ce44SJohn Forte #define CHIP_SOFT_RESET BIT_0 84fcf3ce44SJohn Forte 85fcf3ce44SJohn Forte /* 86fcf3ce44SJohn Forte * INTR_CTRL register 87fcf3ce44SJohn Forte */ 88fcf3ce44SJohn Forte #define ENABLE_RISC_INTR BIT_3 89fcf3ce44SJohn Forte 90fcf3ce44SJohn Forte /* 91fcf3ce44SJohn Forte * INTR_STATUS register 92fcf3ce44SJohn Forte */ 93fcf3ce44SJohn Forte #define RISC_INTR_REQUEST BIT_3 94fcf3ce44SJohn Forte 95fcf3ce44SJohn Forte /* 96fcf3ce44SJohn Forte * HCCR commands 97fcf3ce44SJohn Forte */ 98fcf3ce44SJohn Forte #define HCCR_CMD_NOP 0 99fcf3ce44SJohn Forte #define HCCR_CMD_SET_RISC_RESET 0x10000000 100fcf3ce44SJohn Forte #define HCCR_CMD_CLEAR_RISC_RESET 0x20000000 101fcf3ce44SJohn Forte #define HCCR_CMD_SET_RISC_PAUSE 0x30000000 102fcf3ce44SJohn Forte #define HCCR_CMD_CLEAR_RISC_PAUSE 0x40000000 103fcf3ce44SJohn Forte #define HCCR_CMD_SET_HOST_TO_RISC_INTR 0x50000000 104fcf3ce44SJohn Forte #define HCCR_CMD_CLEAR_HOST_TO_RISC_INTR 0x60000000 105fcf3ce44SJohn Forte #define HCCR_CMD_CLEAR_RISC_TO_PCI_INTR 0xA0000000 106fcf3ce44SJohn Forte 107fcf3ce44SJohn Forte /* 108fcf3ce44SJohn Forte * Flash/NVRAM definitions 109fcf3ce44SJohn Forte */ 110fcf3ce44SJohn Forte #define FLASH_DATA_FLAG BIT_31 111fcf3ce44SJohn Forte #define FLASH_CONF_ADDR 0x7FFD0000 112fcf3ce44SJohn Forte #define FLASH_DATA_ADDR 0x7FF00000 113*c4ddbbe1SDaniel Beauregard #define FLASH_DATA_ADDR_81XX 0x7F8D0000 114fcf3ce44SJohn Forte #define NVRAM_CONF_ADDR 0x7FFF0000 115fcf3ce44SJohn Forte #define NVRAM_DATA_ADDR 0x7FFE0000 116fcf3ce44SJohn Forte 117fcf3ce44SJohn Forte #define NVRAM_FUNC0_ADDR (NVRAM_DATA_ADDR + 0x80) 118fcf3ce44SJohn Forte #define NVRAM_FUNC1_ADDR (NVRAM_DATA_ADDR + 0x180) 119fcf3ce44SJohn Forte 120fcf3ce44SJohn Forte #define QLT25_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR + 0x48080) 121fcf3ce44SJohn Forte #define QLT25_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR + 0x48180) 122fcf3ce44SJohn Forte 123*c4ddbbe1SDaniel Beauregard #define QLT81_NVRAM_FUNC0_ADDR (FLASH_DATA_ADDR_81XX + 0x80) 124*c4ddbbe1SDaniel Beauregard #define QLT81_NVRAM_FUNC1_ADDR (FLASH_DATA_ADDR_81XX + 0x180) 125*c4ddbbe1SDaniel Beauregard 126fcf3ce44SJohn Forte typedef struct qlt_nvram { 127fcf3ce44SJohn Forte /* NVRAM header. */ 128fcf3ce44SJohn Forte uint8_t id[4]; 129fcf3ce44SJohn Forte uint8_t nvram_version[2]; 130fcf3ce44SJohn Forte uint8_t reserved_0[2]; 131fcf3ce44SJohn Forte 132fcf3ce44SJohn Forte /* Firmware Initialization Control Block. */ 133fcf3ce44SJohn Forte uint8_t version[2]; 134fcf3ce44SJohn Forte uint8_t reserved_1[2]; 135fcf3ce44SJohn Forte uint8_t max_frame_length[2]; 136fcf3ce44SJohn Forte uint8_t execution_throttle[2]; 137fcf3ce44SJohn Forte uint8_t exchange_count[2]; 138fcf3ce44SJohn Forte uint8_t hard_address[2]; 139fcf3ce44SJohn Forte uint8_t port_name[8]; 140fcf3ce44SJohn Forte uint8_t node_name[8]; 141fcf3ce44SJohn Forte uint8_t login_retry_count[2]; 142fcf3ce44SJohn Forte uint8_t link_down_on_nos[2]; 143fcf3ce44SJohn Forte uint8_t interrupt_delay_timer[2]; 144fcf3ce44SJohn Forte uint8_t login_timeout[2]; 145fcf3ce44SJohn Forte 146fcf3ce44SJohn Forte /* 147fcf3ce44SJohn Forte * BIT 0 = Hard Assigned Loop ID 148fcf3ce44SJohn Forte * BIT 1 = Enable Fairness 149fcf3ce44SJohn Forte * BIT 2 = Enable Full-Duplex 150fcf3ce44SJohn Forte * BIT 3 = Reserved 151fcf3ce44SJohn Forte * BIT 4 = Target Mode Enable 152fcf3ce44SJohn Forte * BIT 5 = Initiator Mode Disable 153fcf3ce44SJohn Forte * BIT 6 = Reserved 154fcf3ce44SJohn Forte * BIT 7 = Reserved 155fcf3ce44SJohn Forte * 156fcf3ce44SJohn Forte * BIT 8 = Reserved 157fcf3ce44SJohn Forte * BIT 9 = Disable Initial LIP 158fcf3ce44SJohn Forte * BIT 10 = Descending Loop ID Search 159fcf3ce44SJohn Forte * BIT 11 = Previous Assigned Loop ID 160fcf3ce44SJohn Forte * BIT 12 = Reserved 161fcf3ce44SJohn Forte * BIT 13 = Full Login after LIP 162fcf3ce44SJohn Forte * BIT 14 = Node Name Option 163fcf3ce44SJohn Forte * BIT 15-31 = Reserved 164fcf3ce44SJohn Forte */ 165fcf3ce44SJohn Forte uint8_t firmware_options_1[4]; 166fcf3ce44SJohn Forte 167fcf3ce44SJohn Forte /* 168fcf3ce44SJohn Forte * BIT 0 = Operation Mode bit 0 169fcf3ce44SJohn Forte * BIT 1 = Operation Mode bit 1 170fcf3ce44SJohn Forte * BIT 2 = Operation Mode bit 2 171fcf3ce44SJohn Forte * BIT 3 = Operation Mode bit 3 172fcf3ce44SJohn Forte * BIT 4 = Connection Options bit 0 173fcf3ce44SJohn Forte * BIT 5 = Connection Options bit 1 174fcf3ce44SJohn Forte * BIT 6 = Connection Options bit 2 175fcf3ce44SJohn Forte * BIT 7 = Enable Non part on LIHA failure 176fcf3ce44SJohn Forte * 177fcf3ce44SJohn Forte * BIT 8 = Enable Class 2 178fcf3ce44SJohn Forte * BIT 9 = Enable ACK0 179fcf3ce44SJohn Forte * BIT 10 = Reserved 180fcf3ce44SJohn Forte * BIT 11 = Enable FC-SP Security 181fcf3ce44SJohn Forte * BIT 12 = FC Tape Enable 182fcf3ce44SJohn Forte * BIT 13-31 = Reserved 183fcf3ce44SJohn Forte */ 184fcf3ce44SJohn Forte uint8_t firmware_options_2[4]; 185fcf3ce44SJohn Forte 186fcf3ce44SJohn Forte /* 187fcf3ce44SJohn Forte * BIT 0 = Reserved 188fcf3ce44SJohn Forte * BIT 1 = Soft ID only 189fcf3ce44SJohn Forte * BIT 2 = Reserved 190fcf3ce44SJohn Forte * BIT 3 = Reserved 191fcf3ce44SJohn Forte * BIT 4 = FCP RSP Payload bit 0 192fcf3ce44SJohn Forte * BIT 5 = FCP RSP Payload bit 1 193fcf3ce44SJohn Forte * BIT 6 = Enable Rec Out-of-Order data frame handling 194fcf3ce44SJohn Forte * BIT 7 = Disable Automatic PLOGI on Local Loop 195fcf3ce44SJohn Forte * 196fcf3ce44SJohn Forte * BIT 8 = Reserved 197fcf3ce44SJohn Forte * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 198fcf3ce44SJohn Forte * offset handling 199fcf3ce44SJohn Forte * BIT 10 = Reserved 200fcf3ce44SJohn Forte * BIT 11 = Reserved 201fcf3ce44SJohn Forte * BIT 12 = Reserved 202fcf3ce44SJohn Forte * BIT 13 = Data Rate bit 0 203fcf3ce44SJohn Forte * BIT 14 = Data Rate bit 1 204fcf3ce44SJohn Forte * BIT 15 = Data Rate bit 2 205fcf3ce44SJohn Forte * BIT 16 = 75-ohm Termination Select 206fcf3ce44SJohn Forte * BIT 17-31 = Reserved 207fcf3ce44SJohn Forte */ 208fcf3ce44SJohn Forte uint8_t firmware_options_3[4]; 209fcf3ce44SJohn Forte 210fcf3ce44SJohn Forte /* 211fcf3ce44SJohn Forte * Serial Link Control (offset 56) 212fcf3ce44SJohn Forte * BIT 0 = control enable 213fcf3ce44SJohn Forte * BIT 1-15 = Reserved 214fcf3ce44SJohn Forte */ 215fcf3ce44SJohn Forte uint8_t swing_opt[2]; 216fcf3ce44SJohn Forte 217fcf3ce44SJohn Forte /* 218fcf3ce44SJohn Forte * Serial Link Control 1G (offset 58) 219fcf3ce44SJohn Forte * BIT 0-7 = Reserved 220fcf3ce44SJohn Forte * 221fcf3ce44SJohn Forte * BIT 8-10 = output swing 222fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 223fcf3ce44SJohn Forte * BIT 14-15 = Reserved 224fcf3ce44SJohn Forte */ 225fcf3ce44SJohn Forte uint8_t swing_1g[2]; 226fcf3ce44SJohn Forte 227fcf3ce44SJohn Forte /* 228fcf3ce44SJohn Forte * Serial Link Control 2G (offset 60) 229fcf3ce44SJohn Forte * BIT 0-7 = Reserved 230fcf3ce44SJohn Forte * 231fcf3ce44SJohn Forte * BIT 8-10 = output swing 232fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 233fcf3ce44SJohn Forte * BIT 14-15 = Reserved 234fcf3ce44SJohn Forte */ 235fcf3ce44SJohn Forte uint8_t swing_2g[2]; 236fcf3ce44SJohn Forte 237fcf3ce44SJohn Forte /* 238fcf3ce44SJohn Forte * Serial Link Control 4G (offset 62) 239fcf3ce44SJohn Forte * BIT 0-7 = Reserved 240fcf3ce44SJohn Forte * 241fcf3ce44SJohn Forte * BIT 8-10 = output swing 242fcf3ce44SJohn Forte * BIT 11-13 = output emphasis 243fcf3ce44SJohn Forte * BIT 14-15 = Reserved 244fcf3ce44SJohn Forte */ 245fcf3ce44SJohn Forte uint8_t swing_4g[2]; 246fcf3ce44SJohn Forte 247fcf3ce44SJohn Forte /* Offset 64. */ 248fcf3ce44SJohn Forte uint8_t reserved_2[32]; 249fcf3ce44SJohn Forte 250fcf3ce44SJohn Forte /* Offset 96. */ 251fcf3ce44SJohn Forte uint8_t reserved_3[32]; 252fcf3ce44SJohn Forte 253fcf3ce44SJohn Forte /* PCIe table entries. */ 254fcf3ce44SJohn Forte uint8_t reserved_4[32]; 255fcf3ce44SJohn Forte 256fcf3ce44SJohn Forte /* Offset 160. */ 257fcf3ce44SJohn Forte uint8_t reserved_5[32]; 258fcf3ce44SJohn Forte 259fcf3ce44SJohn Forte /* Offset 192. */ 260fcf3ce44SJohn Forte uint8_t reserved_6[32]; 261fcf3ce44SJohn Forte 262fcf3ce44SJohn Forte /* Offset 224. */ 263fcf3ce44SJohn Forte uint8_t reserved_7[32]; 264fcf3ce44SJohn Forte 265fcf3ce44SJohn Forte /* 266fcf3ce44SJohn Forte * BIT 0 = Enable spinup delay 267fcf3ce44SJohn Forte * BIT 1 = Disable BIOS 268fcf3ce44SJohn Forte * BIT 2 = Enable Memory Map BIOS 269fcf3ce44SJohn Forte * BIT 3 = Enable Selectable Boot 270fcf3ce44SJohn Forte * BIT 4 = Disable RISC code load 271fcf3ce44SJohn Forte * BIT 5 = Disable serdes 272fcf3ce44SJohn Forte * BIT 6 = Enable opt boot mode 273fcf3ce44SJohn Forte * BIT 7 = Enable int mode BIOS 274fcf3ce44SJohn Forte * 275fcf3ce44SJohn Forte * BIT 8 = 276fcf3ce44SJohn Forte * BIT 9 = 277fcf3ce44SJohn Forte * BIT 10 = Enable lip full login 278fcf3ce44SJohn Forte * BIT 11 = Enable target reset 279fcf3ce44SJohn Forte * BIT 12 = 280fcf3ce44SJohn Forte * BIT 13 = Default Node Name Option 281fcf3ce44SJohn Forte * BIT 14 = Default valid 282fcf3ce44SJohn Forte * BIT 15 = Enable alternate WWN 283fcf3ce44SJohn Forte * 284fcf3ce44SJohn Forte * BIT 16-31 = 285fcf3ce44SJohn Forte */ 286fcf3ce44SJohn Forte uint8_t host_p[4]; 287fcf3ce44SJohn Forte 288fcf3ce44SJohn Forte uint8_t alternate_port_name[8]; 289fcf3ce44SJohn Forte uint8_t alternate_node_name[8]; 290fcf3ce44SJohn Forte 291fcf3ce44SJohn Forte uint8_t boot_port_name[8]; 292fcf3ce44SJohn Forte uint8_t boot_lun_number[2]; 293fcf3ce44SJohn Forte uint8_t reserved_8[2]; 294fcf3ce44SJohn Forte 295fcf3ce44SJohn Forte uint8_t alt1_boot_port_name[8]; 296fcf3ce44SJohn Forte uint8_t alt1_boot_lun_number[2]; 297fcf3ce44SJohn Forte uint8_t reserved_9[2]; 298fcf3ce44SJohn Forte 299fcf3ce44SJohn Forte uint8_t alt2_boot_port_name[8]; 300fcf3ce44SJohn Forte uint8_t alt2_boot_lun_number[2]; 301fcf3ce44SJohn Forte uint8_t reserved_10[2]; 302fcf3ce44SJohn Forte 303fcf3ce44SJohn Forte uint8_t alt3_boot_port_name[8]; 304fcf3ce44SJohn Forte uint8_t alt3_boot_lun_number[2]; 305fcf3ce44SJohn Forte uint8_t reserved_11[2]; 306fcf3ce44SJohn Forte 307fcf3ce44SJohn Forte /* 308fcf3ce44SJohn Forte * BIT 0 = Selective Login 309fcf3ce44SJohn Forte * BIT 1 = Alt-Boot Enable 310fcf3ce44SJohn Forte * BIT 2 = Reserved 311fcf3ce44SJohn Forte * BIT 3 = Enable Boot Order List 312fcf3ce44SJohn Forte * BIT 4 = Reserved 313fcf3ce44SJohn Forte * BIT 5 = Enable Selective LUN 314fcf3ce44SJohn Forte * BIT 6 = Reserved 315fcf3ce44SJohn Forte * BIT 7-31 = 316fcf3ce44SJohn Forte */ 317fcf3ce44SJohn Forte uint8_t efi_parameters[4]; 318fcf3ce44SJohn Forte 319fcf3ce44SJohn Forte uint8_t reset_delay; 320fcf3ce44SJohn Forte uint8_t reserved_12; 321fcf3ce44SJohn Forte uint8_t reserved_13[2]; 322fcf3ce44SJohn Forte 323fcf3ce44SJohn Forte uint8_t boot_id_number[2]; 324fcf3ce44SJohn Forte uint8_t reserved_14[2]; 325fcf3ce44SJohn Forte 326fcf3ce44SJohn Forte uint8_t max_luns_per_target[2]; 327fcf3ce44SJohn Forte uint8_t reserved_15[2]; 328fcf3ce44SJohn Forte 329fcf3ce44SJohn Forte uint8_t port_down_retry_count[2]; 330fcf3ce44SJohn Forte uint8_t link_down_timeout[2]; 331fcf3ce44SJohn Forte 332fcf3ce44SJohn Forte /* 333fcf3ce44SJohn Forte * FCode parameters word (offset 344) 334fcf3ce44SJohn Forte * 335fcf3ce44SJohn Forte * BIT 0 = Enable BIOS pathname 336fcf3ce44SJohn Forte * BIT 1 = fcode qlc 337fcf3ce44SJohn Forte * BIT 2 = fcode host 338fcf3ce44SJohn Forte * BIT 3-7 = 339fcf3ce44SJohn Forte */ 340fcf3ce44SJohn Forte uint8_t fcode_p0; 341fcf3ce44SJohn Forte uint8_t reserved_16[7]; 342fcf3ce44SJohn Forte 343fcf3ce44SJohn Forte /* Offset 352. */ 344fcf3ce44SJohn Forte uint8_t prev_drv_ver_major; 345fcf3ce44SJohn Forte uint8_t prev_drv_ver_submajob; 346fcf3ce44SJohn Forte uint8_t prev_drv_ver_minor; 347fcf3ce44SJohn Forte uint8_t prev_drv_ver_subminor; 348fcf3ce44SJohn Forte 349fcf3ce44SJohn Forte uint8_t prev_bios_ver_major[2]; 350fcf3ce44SJohn Forte uint8_t prev_bios_ver_minor[2]; 351fcf3ce44SJohn Forte 352fcf3ce44SJohn Forte uint8_t prev_efi_ver_major[2]; 353fcf3ce44SJohn Forte uint8_t prev_efi_ver_minor[2]; 354fcf3ce44SJohn Forte 355fcf3ce44SJohn Forte uint8_t prev_fw_ver_major[2]; 356fcf3ce44SJohn Forte uint8_t prev_fw_ver_minor; 357fcf3ce44SJohn Forte uint8_t prev_fw_ver_subminor; 358fcf3ce44SJohn Forte 359fcf3ce44SJohn Forte uint8_t reserved_17[16]; 360fcf3ce44SJohn Forte 361fcf3ce44SJohn Forte /* Offset 384. */ 362fcf3ce44SJohn Forte uint8_t def_port_name[8]; 363fcf3ce44SJohn Forte uint8_t def_node_name[8]; 364fcf3ce44SJohn Forte 365fcf3ce44SJohn Forte uint8_t reserved_18[16]; 366fcf3ce44SJohn Forte 367fcf3ce44SJohn Forte /* Offset 416. */ 368fcf3ce44SJohn Forte uint8_t reserved_19[32]; 369fcf3ce44SJohn Forte 370fcf3ce44SJohn Forte /* Offset 448. */ 371fcf3ce44SJohn Forte uint8_t reserved_20[28]; 372fcf3ce44SJohn Forte 373fcf3ce44SJohn Forte /* Offset 476. */ 374fcf3ce44SJohn Forte uint8_t fw_table_offset[2]; 375fcf3ce44SJohn Forte uint8_t fw_table_sig[2]; 376fcf3ce44SJohn Forte 377fcf3ce44SJohn Forte /* Offset 480. */ 378fcf3ce44SJohn Forte uint8_t model_name[8]; 379fcf3ce44SJohn Forte 380fcf3ce44SJohn Forte /* Offset 488. */ 381fcf3ce44SJohn Forte uint8_t power_table[16]; 382fcf3ce44SJohn Forte 383fcf3ce44SJohn Forte uint8_t subsystem_vendor_id[2]; 384fcf3ce44SJohn Forte uint8_t subsystem_device_id[2]; 385fcf3ce44SJohn Forte 386fcf3ce44SJohn Forte uint8_t checksum[4]; 387fcf3ce44SJohn Forte } qlt_nvram_t; 388fcf3ce44SJohn Forte 389*c4ddbbe1SDaniel Beauregard /* ISP81xx Extended Initialisation Control Block */ 390*c4ddbbe1SDaniel Beauregard typedef struct qlt_ext_icb_81xx { 391*c4ddbbe1SDaniel Beauregard 392*c4ddbbe1SDaniel Beauregard uint8_t version[2]; 393*c4ddbbe1SDaniel Beauregard uint8_t fcf_vlan_match; 394*c4ddbbe1SDaniel Beauregard uint8_t reserved_6[3]; 395*c4ddbbe1SDaniel Beauregard uint8_t fcf_vlan_id[2]; 396*c4ddbbe1SDaniel Beauregard uint8_t fcf_fabric_name[8]; 397*c4ddbbe1SDaniel Beauregard uint8_t reserved_7[14]; 398*c4ddbbe1SDaniel Beauregard uint8_t spma_proposed_mac_address[6]; 399*c4ddbbe1SDaniel Beauregard uint8_t reserved_8[28]; 400*c4ddbbe1SDaniel Beauregard 401*c4ddbbe1SDaniel Beauregard } qlt_ext_icb_81xx_t; 402*c4ddbbe1SDaniel Beauregard 403*c4ddbbe1SDaniel Beauregard typedef struct qlt_nvram_81xx { 404*c4ddbbe1SDaniel Beauregard /* NVRAM header. */ 405*c4ddbbe1SDaniel Beauregard uint8_t id[4]; 406*c4ddbbe1SDaniel Beauregard uint8_t nvram_version[2]; 407*c4ddbbe1SDaniel Beauregard uint8_t reserved_0[2]; 408*c4ddbbe1SDaniel Beauregard 409*c4ddbbe1SDaniel Beauregard /* Firmware Initialization Control Block. */ 410*c4ddbbe1SDaniel Beauregard uint8_t version[2]; 411*c4ddbbe1SDaniel Beauregard uint8_t reserved_1[2]; 412*c4ddbbe1SDaniel Beauregard uint8_t max_frame_length[2]; 413*c4ddbbe1SDaniel Beauregard uint8_t execution_throttle[2]; 414*c4ddbbe1SDaniel Beauregard uint8_t exchange_count[2]; 415*c4ddbbe1SDaniel Beauregard uint8_t reserved_2[2]; 416*c4ddbbe1SDaniel Beauregard uint8_t port_name[8]; 417*c4ddbbe1SDaniel Beauregard uint8_t node_name[8]; 418*c4ddbbe1SDaniel Beauregard uint8_t login_retry_count[2]; 419*c4ddbbe1SDaniel Beauregard uint8_t reserved_3[2]; 420*c4ddbbe1SDaniel Beauregard uint8_t interrupt_delay_timer[2]; 421*c4ddbbe1SDaniel Beauregard uint8_t login_timeout[2]; 422*c4ddbbe1SDaniel Beauregard 423*c4ddbbe1SDaniel Beauregard /* 424*c4ddbbe1SDaniel Beauregard * BIT 0 = Hard Assigned Loop ID 425*c4ddbbe1SDaniel Beauregard * BIT 1 = Enable Fairness 426*c4ddbbe1SDaniel Beauregard * BIT 2 = Enable Full-Duplex 427*c4ddbbe1SDaniel Beauregard * BIT 3 = Reserved 428*c4ddbbe1SDaniel Beauregard * BIT 4 = Target Mode Enable 429*c4ddbbe1SDaniel Beauregard * BIT 5 = Initiator Mode Disable 430*c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 431*c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 432*c4ddbbe1SDaniel Beauregard * 433*c4ddbbe1SDaniel Beauregard * BIT 8 = Reserved 434*c4ddbbe1SDaniel Beauregard * BIT 9 = Reserved 435*c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 436*c4ddbbe1SDaniel Beauregard * BIT 11 = Reserved 437*c4ddbbe1SDaniel Beauregard * BIT 12 = Reserved 438*c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 439*c4ddbbe1SDaniel Beauregard * BIT 14 = Node Name Option 440*c4ddbbe1SDaniel Beauregard * BIT 15-31 = Reserved 441*c4ddbbe1SDaniel Beauregard */ 442*c4ddbbe1SDaniel Beauregard uint8_t firmware_options_1[4]; 443*c4ddbbe1SDaniel Beauregard 444*c4ddbbe1SDaniel Beauregard /* 445*c4ddbbe1SDaniel Beauregard * BIT 0 = Operation Mode bit 0 446*c4ddbbe1SDaniel Beauregard * BIT 1 = Operation Mode bit 1 447*c4ddbbe1SDaniel Beauregard * BIT 2 = Operation Mode bit 2 448*c4ddbbe1SDaniel Beauregard * BIT 3 = Operation Mode bit 3 449*c4ddbbe1SDaniel Beauregard * BIT 4 = Reserved 450*c4ddbbe1SDaniel Beauregard * BIT 5 = Reserved 451*c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 452*c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 453*c4ddbbe1SDaniel Beauregard * 454*c4ddbbe1SDaniel Beauregard * BIT 8 = Enable Class 2 455*c4ddbbe1SDaniel Beauregard * BIT 9 = Enable ACK0 456*c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 457*c4ddbbe1SDaniel Beauregard * BIT 11 = Enable FC-SP Security 458*c4ddbbe1SDaniel Beauregard * BIT 12 = FC Tape Enable 459*c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 460*c4ddbbe1SDaniel Beauregard * BIT 14 = Target PRLI Control 461*c4ddbbe1SDaniel Beauregard * BIT 15-31 = Reserved 462*c4ddbbe1SDaniel Beauregard */ 463*c4ddbbe1SDaniel Beauregard uint8_t firmware_options_2[4]; 464*c4ddbbe1SDaniel Beauregard 465*c4ddbbe1SDaniel Beauregard /* 466*c4ddbbe1SDaniel Beauregard * BIT 0 = Reserved 467*c4ddbbe1SDaniel Beauregard * BIT 1 = Soft ID only 468*c4ddbbe1SDaniel Beauregard * BIT 2 = Reserved 469*c4ddbbe1SDaniel Beauregard * BIT 3 = Reserved 470*c4ddbbe1SDaniel Beauregard * BIT 4 = FCP RSP Payload bit 0 471*c4ddbbe1SDaniel Beauregard * BIT 5 = FCP RSP Payload bit 1 472*c4ddbbe1SDaniel Beauregard * BIT 6 = Enable Rec Out-of-Order data frame handling 473*c4ddbbe1SDaniel Beauregard * BIT 7 = Reserved 474*c4ddbbe1SDaniel Beauregard * 475*c4ddbbe1SDaniel Beauregard * BIT 8 = Reserved 476*c4ddbbe1SDaniel Beauregard * BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative 477*c4ddbbe1SDaniel Beauregard * offset handling 478*c4ddbbe1SDaniel Beauregard * BIT 10 = Reserved 479*c4ddbbe1SDaniel Beauregard * BIT 11 = Reserved 480*c4ddbbe1SDaniel Beauregard * BIT 12 = Reserved 481*c4ddbbe1SDaniel Beauregard * BIT 13 = Reserved 482*c4ddbbe1SDaniel Beauregard * BIT 14 = Reserved 483*c4ddbbe1SDaniel Beauregard * BIT 15 = Reserved 484*c4ddbbe1SDaniel Beauregard * BIT 16 = Reserved 485*c4ddbbe1SDaniel Beauregard * BIT 17 = Enable Multiple FCFs 486*c4ddbbe1SDaniel Beauregard * BIT 18-20 = MAC Addressing Mode 487*c4ddbbe1SDaniel Beauregard * BIT 21-25 = Ethernet Data Rate 488*c4ddbbe1SDaniel Beauregard * BIT 26 = Enable Ethernet Header Receive ATIO_Q 489*c4ddbbe1SDaniel Beauregard * BIT 27 = Enable Ethernet Header Receive RSP_Q 490*c4ddbbe1SDaniel Beauregard * BIT 28-29 = SPMA Selection 491*c4ddbbe1SDaniel Beauregard * BIT 30-31 = Reserved 492*c4ddbbe1SDaniel Beauregard */ 493*c4ddbbe1SDaniel Beauregard uint8_t firmware_options_3[4]; 494*c4ddbbe1SDaniel Beauregard 495*c4ddbbe1SDaniel Beauregard /* Offset 56 (38h). */ 496*c4ddbbe1SDaniel Beauregard uint8_t reserved_4[8]; 497*c4ddbbe1SDaniel Beauregard 498*c4ddbbe1SDaniel Beauregard /* Offset 64 (40h). */ 499*c4ddbbe1SDaniel Beauregard uint8_t enode_mac[6]; 500*c4ddbbe1SDaniel Beauregard 501*c4ddbbe1SDaniel Beauregard /* Offset 70 (46h). */ 502*c4ddbbe1SDaniel Beauregard uint8_t reserved_5[26]; 503*c4ddbbe1SDaniel Beauregard 504*c4ddbbe1SDaniel Beauregard /* Offset 96 (60h). */ 505*c4ddbbe1SDaniel Beauregard uint8_t oem_specific; 506*c4ddbbe1SDaniel Beauregard uint8_t reserved_6[15]; 507*c4ddbbe1SDaniel Beauregard 508*c4ddbbe1SDaniel Beauregard /* Offset 112 (70h). */ 509*c4ddbbe1SDaniel Beauregard uint8_t reserved_7[16]; 510*c4ddbbe1SDaniel Beauregard 511*c4ddbbe1SDaniel Beauregard /* Offset 128 (80h). */ 512*c4ddbbe1SDaniel Beauregard qlt_ext_icb_81xx_t ext_blk; 513*c4ddbbe1SDaniel Beauregard 514*c4ddbbe1SDaniel Beauregard /* Offset 192. */ 515*c4ddbbe1SDaniel Beauregard uint8_t reserved_8[32]; 516*c4ddbbe1SDaniel Beauregard 517*c4ddbbe1SDaniel Beauregard /* Offset 224. */ 518*c4ddbbe1SDaniel Beauregard uint8_t reserved_9[32]; 519*c4ddbbe1SDaniel Beauregard 520*c4ddbbe1SDaniel Beauregard uint8_t host_p[4]; 521*c4ddbbe1SDaniel Beauregard 522*c4ddbbe1SDaniel Beauregard uint8_t alternate_port_name[8]; 523*c4ddbbe1SDaniel Beauregard uint8_t alternate_name_name[8]; 524*c4ddbbe1SDaniel Beauregard 525*c4ddbbe1SDaniel Beauregard uint8_t boot_port_name[8]; 526*c4ddbbe1SDaniel Beauregard uint8_t boot_lun_number[2]; 527*c4ddbbe1SDaniel Beauregard uint8_t reserved_10[2]; 528*c4ddbbe1SDaniel Beauregard 529*c4ddbbe1SDaniel Beauregard uint8_t alt1_boot_port_name[8]; 530*c4ddbbe1SDaniel Beauregard uint8_t alt1_boot_lun_number[2]; 531*c4ddbbe1SDaniel Beauregard uint8_t reserved_11[2]; 532*c4ddbbe1SDaniel Beauregard 533*c4ddbbe1SDaniel Beauregard uint8_t alt2_boot_port_name[8]; 534*c4ddbbe1SDaniel Beauregard uint8_t alt2_boot_lun_number[2]; 535*c4ddbbe1SDaniel Beauregard uint8_t reserved_12[2]; 536*c4ddbbe1SDaniel Beauregard 537*c4ddbbe1SDaniel Beauregard uint8_t alt3_boot_port_name[8]; 538*c4ddbbe1SDaniel Beauregard uint8_t alt3_boot_lun_number[2]; 539*c4ddbbe1SDaniel Beauregard uint8_t reserved_13[2]; 540*c4ddbbe1SDaniel Beauregard 541*c4ddbbe1SDaniel Beauregard /* 542*c4ddbbe1SDaniel Beauregard * BIT 0 = Selective Login 543*c4ddbbe1SDaniel Beauregard * BIT 1 = Alt-Boot Enable 544*c4ddbbe1SDaniel Beauregard * BIT 2 = Reserved 545*c4ddbbe1SDaniel Beauregard * BIT 3 = Enable Boot Order List 546*c4ddbbe1SDaniel Beauregard * BIT 4 = Reserved 547*c4ddbbe1SDaniel Beauregard * BIT 5 = Enable Selective LUN 548*c4ddbbe1SDaniel Beauregard * BIT 6 = Reserved 549*c4ddbbe1SDaniel Beauregard * BIT 7-31 = 550*c4ddbbe1SDaniel Beauregard */ 551*c4ddbbe1SDaniel Beauregard uint8_t efi_parameters[4]; 552*c4ddbbe1SDaniel Beauregard 553*c4ddbbe1SDaniel Beauregard uint8_t reset_delay; 554*c4ddbbe1SDaniel Beauregard uint8_t reserved_14; 555*c4ddbbe1SDaniel Beauregard uint8_t reserved_15[2]; 556*c4ddbbe1SDaniel Beauregard 557*c4ddbbe1SDaniel Beauregard uint8_t boot_id_number[2]; 558*c4ddbbe1SDaniel Beauregard uint8_t reserved_16[2]; 559*c4ddbbe1SDaniel Beauregard 560*c4ddbbe1SDaniel Beauregard uint8_t max_luns_per_target[2]; 561*c4ddbbe1SDaniel Beauregard uint8_t reserved_17[2]; 562*c4ddbbe1SDaniel Beauregard 563*c4ddbbe1SDaniel Beauregard uint8_t port_down_retry_count[2]; 564*c4ddbbe1SDaniel Beauregard uint8_t link_down_timeout[2]; 565*c4ddbbe1SDaniel Beauregard 566*c4ddbbe1SDaniel Beauregard /* 567*c4ddbbe1SDaniel Beauregard * FCode parameters word (offset 344) 568*c4ddbbe1SDaniel Beauregard * 569*c4ddbbe1SDaniel Beauregard * BIT 0 = Enable BIOS pathname 570*c4ddbbe1SDaniel Beauregard * BIT 1 = fcode qlc 571*c4ddbbe1SDaniel Beauregard * BIT 2 = fcode host 572*c4ddbbe1SDaniel Beauregard * BIT 3-7 = 573*c4ddbbe1SDaniel Beauregard */ 574*c4ddbbe1SDaniel Beauregard uint8_t fcode_parameter[2]; 575*c4ddbbe1SDaniel Beauregard uint8_t reserved_18[6]; 576*c4ddbbe1SDaniel Beauregard 577*c4ddbbe1SDaniel Beauregard /* Offset 352. */ 578*c4ddbbe1SDaniel Beauregard uint8_t reserved_19[4]; 579*c4ddbbe1SDaniel Beauregard uint8_t reserved_20[10]; 580*c4ddbbe1SDaniel Beauregard uint8_t reserved_21[2]; 581*c4ddbbe1SDaniel Beauregard uint8_t reserved_22[16]; 582*c4ddbbe1SDaniel Beauregard 583*c4ddbbe1SDaniel Beauregard /* Offset 384. */ 584*c4ddbbe1SDaniel Beauregard uint8_t reserved_23[16]; 585*c4ddbbe1SDaniel Beauregard uint8_t reserved_24[16]; 586*c4ddbbe1SDaniel Beauregard 587*c4ddbbe1SDaniel Beauregard /* Offset 416. */ 588*c4ddbbe1SDaniel Beauregard uint8_t reserved_25[64]; 589*c4ddbbe1SDaniel Beauregard 590*c4ddbbe1SDaniel Beauregard /* Offset 480. */ 591*c4ddbbe1SDaniel Beauregard uint8_t model_name[16]; 592*c4ddbbe1SDaniel Beauregard 593*c4ddbbe1SDaniel Beauregard /* Offset 496. */ 594*c4ddbbe1SDaniel Beauregard uint8_t feature_mask_l[2]; 595*c4ddbbe1SDaniel Beauregard uint8_t feature_mask_h[2]; 596*c4ddbbe1SDaniel Beauregard uint8_t reserved_26[4]; 597*c4ddbbe1SDaniel Beauregard 598*c4ddbbe1SDaniel Beauregard uint8_t subsystem_vendor_id[2]; 599*c4ddbbe1SDaniel Beauregard uint8_t subsystem_device_id[2]; 600*c4ddbbe1SDaniel Beauregard 601*c4ddbbe1SDaniel Beauregard uint8_t checksum[4]; 602*c4ddbbe1SDaniel Beauregard 603*c4ddbbe1SDaniel Beauregard } qlt_nvram_81xx_t; 604*c4ddbbe1SDaniel Beauregard 605fcf3ce44SJohn Forte #ifdef __cplusplus 606fcf3ce44SJohn Forte } 607fcf3ce44SJohn Forte #endif 608fcf3ce44SJohn Forte 609fcf3ce44SJohn Forte #endif /* _QLT_REGS_H */ 610