xref: /illumos-gate/usr/src/uts/common/io/chxge/oschtoe.h (revision d39a76e7)
1*d39a76e7Sxw /*
2*d39a76e7Sxw  * CDDL HEADER START
3*d39a76e7Sxw  *
4*d39a76e7Sxw  * The contents of this file are subject to the terms of the
5*d39a76e7Sxw  * Common Development and Distribution License (the "License").
6*d39a76e7Sxw  * You may not use this file except in compliance with the License.
7*d39a76e7Sxw  *
8*d39a76e7Sxw  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*d39a76e7Sxw  * or http://www.opensolaris.org/os/licensing.
10*d39a76e7Sxw  * See the License for the specific language governing permissions
11*d39a76e7Sxw  * and limitations under the License.
12*d39a76e7Sxw  *
13*d39a76e7Sxw  * When distributing Covered Code, include this CDDL HEADER in each
14*d39a76e7Sxw  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*d39a76e7Sxw  * If applicable, add the following below this CDDL HEADER, with the
16*d39a76e7Sxw  * fields enclosed by brackets "[]" replaced with your own identifying
17*d39a76e7Sxw  * information: Portions Copyright [yyyy] [name of copyright owner]
18*d39a76e7Sxw  *
19*d39a76e7Sxw  * CDDL HEADER END
20*d39a76e7Sxw  */
22*d39a76e7Sxw /*
23*d39a76e7Sxw  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24*d39a76e7Sxw  * Use is subject to license terms.
25*d39a76e7Sxw  */
27*d39a76e7Sxw /*
28*d39a76e7Sxw  * This file is part of the Chelsio T1 Ethernet driver.
29*d39a76e7Sxw  *
30*d39a76e7Sxw  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
31*d39a76e7Sxw  */
33*d39a76e7Sxw #ifndef _CHELSIO_OSCHTOE_H
34*d39a76e7Sxw #define	_CHELSIO_OSCHTOE_H
36*d39a76e7Sxw #pragma ident	"%Z%%M%	%I%	%E% SMI"
38*d39a76e7Sxw #ifdef __cplusplus
39*d39a76e7Sxw extern "C" {
40*d39a76e7Sxw #endif
42*d39a76e7Sxw typedef struct _pesge  pesge;
44*d39a76e7Sxw /* looks like this should really be with mc5.h */
45*d39a76e7Sxw #define	DEFAULT_SERVER_REGION_LEN 256
46*d39a76e7Sxw #define	DEFAULT_RT_REGION_LEN 1024
48*d39a76e7Sxw /*
49*d39a76e7Sxw  * Bits used to configure driver behavior.
50*d39a76e7Sxw  */
51*d39a76e7Sxw #define	CFGDMP_RSPQ	0x00000001 /* dump respq info */
52*d39a76e7Sxw #define	CFGDMP_CMDQ0	0x00000010 /* dump cmdq0 info */
53*d39a76e7Sxw #define	CFGDMP_CMDQ0MB	0x00000020 /* dump cmdq0 mbufs */
54*d39a76e7Sxw #define	CFGDMP_CMDQ1	0x00000040 /* dump cmdq1 info */
55*d39a76e7Sxw #define	CFGDMP_CMDQ1MB	0x00000080 /* dump cmdq1 mbufs */
56*d39a76e7Sxw #define	CFGDMP_FLQ0	0x00000100 /* dump flq0 info */
57*d39a76e7Sxw #define	CFGDMP_FLQ0MB	0x00000200 /* dump flq0 mbufs */
58*d39a76e7Sxw #define	CFGDMP_FLQ1	0x00000400 /* dump flq1 info */
59*d39a76e7Sxw #define	CFGDMP_FLQ1MB	0x00000800 /* dump flq1 mbufs */
60*d39a76e7Sxw #define	CFGDMP_ISRC	0x00001000 /* dump ISR 32 bit cause */
61*d39a76e7Sxw #define	CFGDMP_ISR	0x00002000 /* dump ISR info */
62*d39a76e7Sxw #define	CFGDMP_OUT	0x00004000 /* dump OUT info */
63*d39a76e7Sxw #define	CFGDMP_GMACC	0x00010000 /* dump GMAC cause bits */
64*d39a76e7Sxw #define	CFGDMP_PCIXC	0x00020000 /* dump PCIX cause bits */
65*d39a76e7Sxw #define	CFGDMP_TPC	0x00040000 /* dump TP cause bits */
66*d39a76e7Sxw #define	CFGDMP_MC5C	0x00080000 /* dump MC5 cause bits */
68*d39a76e7Sxw #define	CFGMD_RINGB	0x00100000 /* Store all packets in ring buffer */
69*d39a76e7Sxw #define	CFGMD_PROFILE	0x00200000 /* Enable driver profiling */
71*d39a76e7Sxw #define	CFGDMP_ERR	0x01000000 /* dump errors */
72*d39a76e7Sxw #define	CFGDMP_WRN	0x02000000 /* dump warnings */
73*d39a76e7Sxw #define	CFGDMP_STA	0x04000000 /* dump status info */
74*d39a76e7Sxw #define	CFGDMP_PTH	0x08000000 /* dump function paths */
76*d39a76e7Sxw #define	CFGMD_TUNNEL	0x10000000 /* Global tunnel mode ( 0-offload mode ) */
77*d39a76e7Sxw #define	CFGMD_144BIT	0x20000000 /* Puts MC5 in 144 bit mode */
78*d39a76e7Sxw #define	CFGMD_CPLBPF	0x40000000 /* Include CPL header when bpf_map called */
80*d39a76e7Sxw /*
81*d39a76e7Sxw  * Structure used to store drivers configuration information.
82*d39a76e7Sxw  * Some of this information will be move out later or
83*d39a76e7Sxw  * stored elsewhere.  For now, it helps with development.
84*d39a76e7Sxw  */
85*d39a76e7Sxw typedef struct pe_config_data {
86*d39a76e7Sxw 	uint32_t gtm;			/* run in Global Tunnel Mode */
87*d39a76e7Sxw 	uint32_t global_config;		/* override global debug value */
89*d39a76e7Sxw 	uint32_t is_asic;
91*d39a76e7Sxw 	/*
92*d39a76e7Sxw 	 * 5-auto-neg
93*d39a76e7Sxw 	 * 2-1000Gbps(force);
94*d39a76e7Sxw 	 * 1-100Gbps(force);
95*d39a76e7Sxw 	 * 0-10Gbps(force)
96*d39a76e7Sxw 	 */
97*d39a76e7Sxw 	uint32_t link_speed;
99*d39a76e7Sxw 	uint32_t num_of_ports;		/* Set the number of ports [1-4] */
101*d39a76e7Sxw 	uint32_t tp_reset_cm;		/* reset CM memory map */
103*d39a76e7Sxw 	uint32_t phy_tx_fifo;		/* phy's tx fifo depth */
104*d39a76e7Sxw 	uint32_t phy_rx_fifo;		/* phy's rx fifo depth */
105*d39a76e7Sxw 	uint32_t phy_force_master;	/* force link always in master mode */
107*d39a76e7Sxw 	uint32_t mc5_rtbl_size;		/* TCAM routing table size */
108*d39a76e7Sxw 	uint32_t mc5_dbsvr_size;	/* TCAM server size */
109*d39a76e7Sxw 	uint32_t mc5_mode;		/* 72 bit or 144 bit mode */
110*d39a76e7Sxw 	uint32_t mc5_parity;		/* Enable parity error checking */
111*d39a76e7Sxw 	uint32_t mc5_issue_syn;		/* Allow for transaction overlap */
113*d39a76e7Sxw 	uint32_t packet_tracing;
115*d39a76e7Sxw 	uint32_t server_region_len;
116*d39a76e7Sxw 	uint32_t rt_region_len;
118*d39a76e7Sxw 	uint32_t offload_ip_cksum;	/* on/off checksum offloading */
119*d39a76e7Sxw 	uint32_t offload_udp_cksum;
120*d39a76e7Sxw 	uint32_t offload_tcp_cksum;
122*d39a76e7Sxw 	uint32_t sge_cmdq_sp;		/* set sw schedule policy */
123*d39a76e7Sxw 	uint32_t sge_cmdq_threshold;	/* used w/ sw schedule policy */
124*d39a76e7Sxw 	uint32_t sge_flq_threshold;	/* set SGE's flq threshold register */
126*d39a76e7Sxw 	uint32_t sge_cmdq0_cnt;		/* set # entries of cmdq0 */
127*d39a76e7Sxw 	uint32_t sge_cmdq1_cnt;		/* set # entries of cmdq1 */
128*d39a76e7Sxw 	uint32_t sge_flq0_cnt;		/* set # entries of flq0 */
129*d39a76e7Sxw 	uint32_t sge_flq1_cnt;		/* set # entries of flq1 */
130*d39a76e7Sxw 	uint32_t sge_respq_cnt;		/* set # entries of respq */
133*d39a76e7Sxw 	/*
134*d39a76e7Sxw 	 * Update MAC stats automatically.
135*d39a76e7Sxw 	 * Sometimes we don't want this to
136*d39a76e7Sxw 	 * happen when debugging
137*d39a76e7Sxw 	 */
138*d39a76e7Sxw 	uint32_t stats;
140*d39a76e7Sxw 	/*
141*d39a76e7Sxw 	 * Add microsecond delay to packets
142*d39a76e7Sxw 	 * sent in Tx direction. This is useful
143*d39a76e7Sxw 	 * in testing hardware.
144*d39a76e7Sxw 	 */
145*d39a76e7Sxw 	uint32_t tx_delay_us;
147*d39a76e7Sxw 	/*
148*d39a76e7Sxw 	 * Can change chip revision support
149*d39a76e7Sxw 	 * settting -1 default. Uses hardware
150*d39a76e7Sxw 	 * lookup table.
151*d39a76e7Sxw 	 * 0 force T1A
152*d39a76e7Sxw 	 * 1 force T1B
153*d39a76e7Sxw 	 */
154*d39a76e7Sxw 	uint32_t chip;
156*d39a76e7Sxw 	/*
157*d39a76e7Sxw 	 * Used to only initialize PCI so
158*d39a76e7Sxw 	 * read/write registers work. The
159*d39a76e7Sxw 	 * driver does not initialize anything
160*d39a76e7Sxw 	 * of the HW blocks.
161*d39a76e7Sxw 	 */
162*d39a76e7Sxw 	uint32_t exit_early;
164*d39a76e7Sxw 	/* local ring buffer */
165*d39a76e7Sxw 	uint32_t rb_num_of_entries;	/* number of entries */
166*d39a76e7Sxw 	uint32_t rb_size_of_entries;	/* bytes size of an entry */
167*d39a76e7Sxw 	uint32_t rb_flag;		/* varies flags */
169*d39a76e7Sxw 	/* Opt values used to store CATP options.  */
170*d39a76e7Sxw 	uint32_t type;
171*d39a76e7Sxw 	uint64_t cat_opt0;
172*d39a76e7Sxw 	uint64_t cat_opt1;
174*d39a76e7Sxw } pe_config_data_t;
176*d39a76e7Sxw struct pe_port_t {
177*d39a76e7Sxw 	uint8_t enaddr[6];
178*d39a76e7Sxw 	struct cmac *mac;
179*d39a76e7Sxw 	struct cphy *phy;
180*d39a76e7Sxw 	struct link_config link_config;
181*d39a76e7Sxw 	u32 line_up;
182*d39a76e7Sxw };
184*d39a76e7Sxw #define	DBGASSERT(c) ASSERT(c)
186*d39a76e7Sxw #define	t1_is_T1A(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1A)
187*d39a76e7Sxw #define	t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
188*d39a76e7Sxw #define	t1_is_T1C(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1C)
190*d39a76e7Sxw #ifdef __cplusplus
191*d39a76e7Sxw }
192*d39a76e7Sxw #endif
194*d39a76e7Sxw #endif /* _CHELSIO_OSCHTOE_H */