1*d39a76e7Sxw /*
2*d39a76e7Sxw  * CDDL HEADER START
3*d39a76e7Sxw  *
4*d39a76e7Sxw  * The contents of this file are subject to the terms of the
5*d39a76e7Sxw  * Common Development and Distribution License (the "License").
6*d39a76e7Sxw  * You may not use this file except in compliance with the License.
7*d39a76e7Sxw  *
8*d39a76e7Sxw  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*d39a76e7Sxw  * or http://www.opensolaris.org/os/licensing.
10*d39a76e7Sxw  * See the License for the specific language governing permissions
11*d39a76e7Sxw  * and limitations under the License.
12*d39a76e7Sxw  *
13*d39a76e7Sxw  * When distributing Covered Code, include this CDDL HEADER in each
14*d39a76e7Sxw  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*d39a76e7Sxw  * If applicable, add the following below this CDDL HEADER, with the
16*d39a76e7Sxw  * fields enclosed by brackets "[]" replaced with your own identifying
17*d39a76e7Sxw  * information: Portions Copyright [yyyy] [name of copyright owner]
18*d39a76e7Sxw  *
19*d39a76e7Sxw  * CDDL HEADER END
20*d39a76e7Sxw  */
21*d39a76e7Sxw 
22*d39a76e7Sxw /*
23*d39a76e7Sxw  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24*d39a76e7Sxw  */
25*d39a76e7Sxw 
26*d39a76e7Sxw #pragma ident	"%Z%%M%	%I%	%E% SMI"	/* vsc7321.c */
27*d39a76e7Sxw 
28*d39a76e7Sxw /* Driver for Vitesse VSC7321 (Meigs II) MAC */
29*d39a76e7Sxw 
30*d39a76e7Sxw 
31*d39a76e7Sxw #if 0
32*d39a76e7Sxw #ifndef INVARIANTS
33*d39a76e7Sxw #define INVARIANTS
34*d39a76e7Sxw #endif
35*d39a76e7Sxw 
36*d39a76e7Sxw #include <sys/param.h>
37*d39a76e7Sxw #include <sys/systm.h>
38*d39a76e7Sxw #include <sys/malloc.h>
39*d39a76e7Sxw #include <sys/kernel.h>
40*d39a76e7Sxw #include <sys/conf.h>
41*d39a76e7Sxw #include <pci/pcivar.h>
42*d39a76e7Sxw #include <pci/pcireg.h>
43*d39a76e7Sxw #endif
44*d39a76e7Sxw 
45*d39a76e7Sxw #include "gmac.h"
46*d39a76e7Sxw #include "elmer0.h"
47*d39a76e7Sxw #include "vsc7321_reg.h"
48*d39a76e7Sxw 
49*d39a76e7Sxw #define DEBUG 1
50*d39a76e7Sxw 
51*d39a76e7Sxw struct init_table {
52*d39a76e7Sxw     u32 addr;
53*d39a76e7Sxw     u32 data;
54*d39a76e7Sxw };
55*d39a76e7Sxw 
56*d39a76e7Sxw static struct cmac_ops vsc7321_ops;
57*d39a76e7Sxw 
58*d39a76e7Sxw struct _cmac_instance {
59*d39a76e7Sxw 	u32 mac_base;
60*d39a76e7Sxw 	u32 index;
61*d39a76e7Sxw 	u32 version;
62*d39a76e7Sxw };
63*d39a76e7Sxw 
64*d39a76e7Sxw #define INITBLOCK_SLEEP	0xffffffff
65*d39a76e7Sxw 
vsc_read(adapter_t * adapter,u32 addr,u32 * val)66*d39a76e7Sxw static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
67*d39a76e7Sxw {
68*d39a76e7Sxw     u32 status, vlo, vhi;
69*d39a76e7Sxw 
70*d39a76e7Sxw     (void) t1_tpi_read(adapter, (addr << 2) + 4, &vlo);
71*d39a76e7Sxw 
72*d39a76e7Sxw     do {
73*d39a76e7Sxw 	(void) t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
74*d39a76e7Sxw 	(void) t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
75*d39a76e7Sxw 	status = (vhi << 16) | vlo;
76*d39a76e7Sxw     } while ((status & 1) == 0);
77*d39a76e7Sxw 
78*d39a76e7Sxw     (void) t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
79*d39a76e7Sxw     (void) t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
80*d39a76e7Sxw 
81*d39a76e7Sxw     *val = (vhi << 16) | vlo;
82*d39a76e7Sxw }
83*d39a76e7Sxw 
vsc_write(adapter_t * adapter,u32 addr,u32 data)84*d39a76e7Sxw static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
85*d39a76e7Sxw {
86*d39a76e7Sxw     (void) t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
87*d39a76e7Sxw     (void) t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
88*d39a76e7Sxw }
89*d39a76e7Sxw 
90*d39a76e7Sxw /* Hard reset the MAC.  This wipes out *all* configuration. */
vsc7321_full_reset(adapter_t * adapter)91*d39a76e7Sxw static void vsc7321_full_reset(adapter_t* adapter)
92*d39a76e7Sxw {
93*d39a76e7Sxw     u32 val;
94*d39a76e7Sxw 
95*d39a76e7Sxw     (void) t1_tpi_read(adapter, A_ELMER0_GPO, &val);
96*d39a76e7Sxw     val &= ~1;
97*d39a76e7Sxw     (void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
98*d39a76e7Sxw     DELAY_US(2);
99*d39a76e7Sxw     val |= 0x80001;	/* Turn on SPI4_EN, and the MAC itself */
100*d39a76e7Sxw     if (is_10G(adapter)) {
101*d39a76e7Sxw 	val |= 0x40000;	/* Enable 10G section */
102*d39a76e7Sxw     } else {
103*d39a76e7Sxw 	val |= 0x20000;	/* Enable 1G section */
104*d39a76e7Sxw     }
105*d39a76e7Sxw     val &= ~0x800;	/* Turn off the red LED */
106*d39a76e7Sxw     (void) t1_tpi_write(adapter, A_ELMER0_GPO, val);
107*d39a76e7Sxw     DELAY_US(1000);
108*d39a76e7Sxw }
109*d39a76e7Sxw 
110*d39a76e7Sxw static struct init_table vsc7321_reset[] = {
111*d39a76e7Sxw     {        REG_SW_RESET, 0x80000001 },
112*d39a76e7Sxw     { INITBLOCK_SLEEP, 0x64 },
113*d39a76e7Sxw     {        REG_SW_RESET, 0x00000000 },
114*d39a76e7Sxw     {      REG_IFACE_MODE, 0x00000000 },
115*d39a76e7Sxw     {         REG_CRC_CFG, 0x00000020 },
116*d39a76e7Sxw     {   REG_PLL_CLK_SPEED, 0x00000000 },
117*d39a76e7Sxw     { INITBLOCK_SLEEP, 0x0a },
118*d39a76e7Sxw     {   REG_PLL_CLK_SPEED, 0x000000d4 },
119*d39a76e7Sxw     {       REG_SPI4_MISC, 0x00040009 },
120*d39a76e7Sxw     { REG_SPI4_ING_SETUP2, 0x04040004 },
121*d39a76e7Sxw     { REG_SPI4_ING_SETUP0, 0x0011100f },	/* FIXME: Multiport */
122*d39a76e7Sxw     { REG_SPI4_EGR_SETUP0, 0x0004100f },	/* FIXME: Multiport */
123*d39a76e7Sxw     { REG_SPI4_ING_SETUP1, 0x00100000 },
124*d39a76e7Sxw     {      REG_AGE_INC(0), 0x00000000 },
125*d39a76e7Sxw     {      REG_AGE_INC(1), 0x00000000 },
126*d39a76e7Sxw     {     REG_ING_CONTROL, 0x0a000014 },	/* FIXME: 1G vs 10G */
127*d39a76e7Sxw     {     REG_EGR_CONTROL, 0xa0010091 },	/* FIXME: 1G vs 10G */
128*d39a76e7Sxw };
129*d39a76e7Sxw 
130*d39a76e7Sxw static struct init_table vsc7321_portinit[4][20] = {
131*d39a76e7Sxw     {	/* Port 0 */
132*d39a76e7Sxw     		/* FIFO setup */
133*d39a76e7Sxw 	{        REG_TEST(0,0), 0x00000002 },
134*d39a76e7Sxw 	{        REG_TEST(1,0), 0x00000002 },
135*d39a76e7Sxw 	{  REG_TOP_BOTTOM(0,0), 0x00100000 },
136*d39a76e7Sxw 	{  REG_TOP_BOTTOM(1,0), 0x00100000 },
137*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(0,0), 0x0fff0fff },
138*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(1,0), 0x0fff0fff },
139*d39a76e7Sxw 	{   REG_CT_THRHLD(0,0), 0x00000000 },
140*d39a76e7Sxw 	{   REG_CT_THRHLD(1,0), 0x00000000 },
141*d39a76e7Sxw 	{        REG_TEST(0,0), 0x00000000 },
142*d39a76e7Sxw 	{        REG_TEST(1,0), 0x00000000 },
143*d39a76e7Sxw 		/* Port config */
144*d39a76e7Sxw 	{      REG_MODE_CFG(0), 0x0000054c },
145*d39a76e7Sxw 	{       REG_MAX_LEN(0), 0x000005ee },
146*d39a76e7Sxw 	{     REG_DEV_SETUP(0), 0x00000001 },
147*d39a76e7Sxw 	{    REG_TBI_CONFIG(0), 0x00000000 },
148*d39a76e7Sxw 	{     REG_DEV_SETUP(0), 0x00000046 },
149*d39a76e7Sxw 	{     REG_PAUSE_CFG(0), 0x00000000 },
150*d39a76e7Sxw 	{    REG_NORMALIZER(0), 0x00000064 },
151*d39a76e7Sxw 	{        REG_DENORM(0), 0x00000010 },
152*d39a76e7Sxw     },
153*d39a76e7Sxw     {	/* Port 1 */
154*d39a76e7Sxw     		/* FIFO setup */
155*d39a76e7Sxw 	{        REG_TEST(0,1), 0x00000002 },
156*d39a76e7Sxw 	{        REG_TEST(1,1), 0x00000002 },
157*d39a76e7Sxw 	{  REG_TOP_BOTTOM(0,1), 0x00100000 },
158*d39a76e7Sxw 	{  REG_TOP_BOTTOM(1,1), 0x00100000 },
159*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(0,1), 0x0fff0fff },
160*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(1,1), 0x0fff0fff },
161*d39a76e7Sxw 	{   REG_CT_THRHLD(0,1), 0x00000000 },
162*d39a76e7Sxw 	{   REG_CT_THRHLD(1,1), 0x00000000 },
163*d39a76e7Sxw 	{        REG_TEST(0,1), 0x00000000 },
164*d39a76e7Sxw 	{        REG_TEST(1,1), 0x00000000 },
165*d39a76e7Sxw 		/* Port config */
166*d39a76e7Sxw 	{      REG_MODE_CFG(1), 0x0000054c },
167*d39a76e7Sxw 	{       REG_MAX_LEN(1), 0x000005ee },
168*d39a76e7Sxw 	{     REG_DEV_SETUP(1), 0x00000001 },
169*d39a76e7Sxw 	{    REG_TBI_CONFIG(1), 0x00000000 },
170*d39a76e7Sxw 	{     REG_DEV_SETUP(1), 0x00000046 },
171*d39a76e7Sxw 	{     REG_PAUSE_CFG(1), 0x00000000 },
172*d39a76e7Sxw 	{    REG_NORMALIZER(1), 0x00000064 },
173*d39a76e7Sxw 	{        REG_DENORM(1), 0x00000010 },
174*d39a76e7Sxw     },
175*d39a76e7Sxw     {	/* Port 2 */
176*d39a76e7Sxw     		/* FIFO setup */
177*d39a76e7Sxw 	{        REG_TEST(0,2), 0x00000002 },
178*d39a76e7Sxw 	{        REG_TEST(1,2), 0x00000002 },
179*d39a76e7Sxw 	{  REG_TOP_BOTTOM(0,2), 0x00100000 },
180*d39a76e7Sxw 	{  REG_TOP_BOTTOM(1,2), 0x00100000 },
181*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(0,2), 0x0fff0fff },
182*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(1,2), 0x0fff0fff },
183*d39a76e7Sxw 	{   REG_CT_THRHLD(0,2), 0x00000000 },
184*d39a76e7Sxw 	{   REG_CT_THRHLD(1,2), 0x00000000 },
185*d39a76e7Sxw 	{        REG_TEST(0,2), 0x00000000 },
186*d39a76e7Sxw 	{        REG_TEST(1,2), 0x00000000 },
187*d39a76e7Sxw 		/* Port config */
188*d39a76e7Sxw 	{      REG_MODE_CFG(2), 0x0000054c },
189*d39a76e7Sxw 	{       REG_MAX_LEN(2), 0x000005ee },
190*d39a76e7Sxw 	{     REG_DEV_SETUP(2), 0x00000001 },
191*d39a76e7Sxw 	{    REG_TBI_CONFIG(2), 0x00000000 },
192*d39a76e7Sxw 	{     REG_DEV_SETUP(2), 0x00000046 },
193*d39a76e7Sxw 	{     REG_PAUSE_CFG(2), 0x00000000 },
194*d39a76e7Sxw 	{    REG_NORMALIZER(2), 0x00000064 },
195*d39a76e7Sxw 	{        REG_DENORM(2), 0x00000010 },
196*d39a76e7Sxw     },
197*d39a76e7Sxw     {	/* Port 3 */
198*d39a76e7Sxw     		/* FIFO setup */
199*d39a76e7Sxw 	{        REG_TEST(0,3), 0x00000002 },
200*d39a76e7Sxw 	{        REG_TEST(1,3), 0x00000002 },
201*d39a76e7Sxw 	{  REG_TOP_BOTTOM(0,3), 0x00100000 },
202*d39a76e7Sxw 	{  REG_TOP_BOTTOM(1,3), 0x00100000 },
203*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(0,3), 0x0fff0fff },
204*d39a76e7Sxw 	{ REG_HIGH_LOW_WM(1,3), 0x0fff0fff },
205*d39a76e7Sxw 	{   REG_CT_THRHLD(0,3), 0x00000000 },
206*d39a76e7Sxw 	{   REG_CT_THRHLD(1,3), 0x00000000 },
207*d39a76e7Sxw 	{        REG_TEST(0,3), 0x00000000 },
208*d39a76e7Sxw 	{        REG_TEST(1,3), 0x00000000 },
209*d39a76e7Sxw 		/* Port config */
210*d39a76e7Sxw 	{      REG_MODE_CFG(3), 0x0000054c },
211*d39a76e7Sxw 	{       REG_MAX_LEN(3), 0x000005ee },
212*d39a76e7Sxw 	{     REG_DEV_SETUP(3), 0x00000001 },
213*d39a76e7Sxw 	{    REG_TBI_CONFIG(3), 0x00000000 },
214*d39a76e7Sxw 	{     REG_DEV_SETUP(3), 0x00000046 },
215*d39a76e7Sxw 	{     REG_PAUSE_CFG(3), 0x00000000 },
216*d39a76e7Sxw 	{    REG_NORMALIZER(3), 0x00000064 },
217*d39a76e7Sxw 	{        REG_DENORM(3), 0x00000010 },
218*d39a76e7Sxw     },
219*d39a76e7Sxw };
220*d39a76e7Sxw 
run_table(adapter_t * adapter,struct init_table * ib,int len)221*d39a76e7Sxw static void run_table(adapter_t *adapter, struct init_table *ib, int len)
222*d39a76e7Sxw {
223*d39a76e7Sxw 	int i;
224*d39a76e7Sxw 
225*d39a76e7Sxw 	for (i = 0; i < len; i++) {
226*d39a76e7Sxw 		if (ib[i].addr == INITBLOCK_SLEEP) {
227*d39a76e7Sxw 			DELAY_US( ib[i].data );
228*d39a76e7Sxw 		} else {
229*d39a76e7Sxw 			vsc_write( adapter, ib[i].addr, ib[i].data );
230*d39a76e7Sxw 		}
231*d39a76e7Sxw 	}
232*d39a76e7Sxw }
233*d39a76e7Sxw 
234*d39a76e7Sxw /* ARGSUSED */
vsc7321_mac_reset(adapter_t * adapter)235*d39a76e7Sxw static int vsc7321_mac_reset(adapter_t *adapter)
236*d39a76e7Sxw {
237*d39a76e7Sxw 	return 0;
238*d39a76e7Sxw }
239*d39a76e7Sxw 
vsc7321_mac_create(adapter_t * adapter,int index)240*d39a76e7Sxw static struct cmac *vsc7321_mac_create(adapter_t *adapter, int index)
241*d39a76e7Sxw {
242*d39a76e7Sxw 	struct cmac *mac;
243*d39a76e7Sxw 	u32 val;
244*d39a76e7Sxw 	int i;
245*d39a76e7Sxw 
246*d39a76e7Sxw 	mac = t1_os_malloc_wait_zero(sizeof(*mac) + sizeof(cmac_instance));
247*d39a76e7Sxw 	if (!mac) return NULL;
248*d39a76e7Sxw 
249*d39a76e7Sxw 	mac->ops = &vsc7321_ops;
250*d39a76e7Sxw 	mac->instance = (cmac_instance *)(mac + 1);
251*d39a76e7Sxw 
252*d39a76e7Sxw 	mac->adapter   = adapter;
253*d39a76e7Sxw 	mac->instance->index = index;
254*d39a76e7Sxw 
255*d39a76e7Sxw 
256*d39a76e7Sxw 	vsc7321_full_reset(adapter);
257*d39a76e7Sxw 
258*d39a76e7Sxw 	i = 0;
259*d39a76e7Sxw 	do {
260*d39a76e7Sxw 		u32 vhi, vlo;
261*d39a76e7Sxw 
262*d39a76e7Sxw 		vhi = vlo = 0;
263*d39a76e7Sxw 		(void) t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
264*d39a76e7Sxw 		DELAY_US(1);
265*d39a76e7Sxw 		(void) t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
266*d39a76e7Sxw 		DELAY_US(5);
267*d39a76e7Sxw 		val = (vhi << 16) | vlo;
268*d39a76e7Sxw 	} while ((++i < 10000) && (val == 0xffffffff));
269*d39a76e7Sxw 
270*d39a76e7Sxw 
271*d39a76e7Sxw 	vsc_read(adapter, REG_CHIP_ID, &val);
272*d39a76e7Sxw 
273*d39a76e7Sxw 	if ((val & 0xfff0ffff) != 0x0F407321) {
274*d39a76e7Sxw 		CH_ERR("%s: Didn't find a VSC 7321.\n", adapter_name(adapter));
275*d39a76e7Sxw 		t1_os_free((void *)mac, sizeof(*mac) + sizeof(cmac_instance));
276*d39a76e7Sxw 		return NULL;
277*d39a76e7Sxw 	}
278*d39a76e7Sxw 
279*d39a76e7Sxw 	mac->instance->version = (val >> 16) & 0xf;
280*d39a76e7Sxw 
281*d39a76e7Sxw 	run_table(adapter, vsc7321_reset, DIMOF(vsc7321_reset));
282*d39a76e7Sxw 	return mac;
283*d39a76e7Sxw }
284*d39a76e7Sxw 
285*d39a76e7Sxw /* ARGSUSED */
mac_intr_handler(struct cmac * mac)286*d39a76e7Sxw static int mac_intr_handler(struct cmac *mac)
287*d39a76e7Sxw {
288*d39a76e7Sxw 	return 0;
289*d39a76e7Sxw }
290*d39a76e7Sxw 
291*d39a76e7Sxw /* ARGSUSED */
mac_intr_enable(struct cmac * mac)292*d39a76e7Sxw static int mac_intr_enable(struct cmac *mac)
293*d39a76e7Sxw {
294*d39a76e7Sxw 	return 0;
295*d39a76e7Sxw }
296*d39a76e7Sxw 
297*d39a76e7Sxw /* ARGSUSED */
mac_intr_disable(struct cmac * mac)298*d39a76e7Sxw static int mac_intr_disable(struct cmac *mac)
299*d39a76e7Sxw {
300*d39a76e7Sxw 	return 0;
301*d39a76e7Sxw }
302*d39a76e7Sxw 
303*d39a76e7Sxw /* ARGSUSED */
mac_intr_clear(struct cmac * mac)304*d39a76e7Sxw static int mac_intr_clear(struct cmac *mac)
305*d39a76e7Sxw {
306*d39a76e7Sxw     /* Nothing extra needed */
307*d39a76e7Sxw     return 0;
308*d39a76e7Sxw }
309*d39a76e7Sxw 
310*d39a76e7Sxw /* Expect MAC address to be in network byte order. */
mac_set_address(struct cmac * mac,u8 addr[6])311*d39a76e7Sxw static int mac_set_address(struct cmac* mac, u8 addr[6])
312*d39a76e7Sxw {
313*d39a76e7Sxw 	u32 addr_lo, addr_hi;
314*d39a76e7Sxw 	int port = mac->instance->index;
315*d39a76e7Sxw 
316*d39a76e7Sxw 	addr_lo = addr[3];
317*d39a76e7Sxw 	addr_lo = (addr_lo << 8) | addr[4];
318*d39a76e7Sxw 	addr_lo = (addr_lo << 8) | addr[5];
319*d39a76e7Sxw 
320*d39a76e7Sxw 	addr_hi = addr[0];
321*d39a76e7Sxw 	addr_hi = (addr_hi << 8) | addr[1];
322*d39a76e7Sxw 	addr_hi = (addr_hi << 8) | addr[2];
323*d39a76e7Sxw 
324*d39a76e7Sxw 	vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port), addr_lo);
325*d39a76e7Sxw 	vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port), addr_hi);
326*d39a76e7Sxw 	return 0;
327*d39a76e7Sxw }
328*d39a76e7Sxw 
mac_get_address(struct cmac * mac,u8 addr[6])329*d39a76e7Sxw static int mac_get_address(struct cmac *mac, u8 addr[6])
330*d39a76e7Sxw {
331*d39a76e7Sxw 	u32 addr_lo, addr_hi;
332*d39a76e7Sxw 	int port = mac->instance->index;
333*d39a76e7Sxw 
334*d39a76e7Sxw 	vsc_read(mac->adapter, REG_MAC_LOW_ADDR(port), &addr_lo);
335*d39a76e7Sxw 	vsc_read(mac->adapter, REG_MAC_HIGH_ADDR(port), &addr_hi);
336*d39a76e7Sxw 
337*d39a76e7Sxw 	addr[0] = (u8) (addr_hi >> 16);
338*d39a76e7Sxw 	addr[1] = (u8) (addr_hi >> 8);
339*d39a76e7Sxw 	addr[2] = (u8) addr_hi;
340*d39a76e7Sxw 	addr[3] = (u8) (addr_lo >> 16);
341*d39a76e7Sxw 	addr[4] = (u8) (addr_lo >> 8);
342*d39a76e7Sxw 	addr[5] = (u8) addr_lo;
343*d39a76e7Sxw 	return 0;
344*d39a76e7Sxw }
345*d39a76e7Sxw 
346*d39a76e7Sxw /* This is intended to reset a port, not the whole MAC */
mac_reset(struct cmac * mac)347*d39a76e7Sxw static int mac_reset(struct cmac *mac)
348*d39a76e7Sxw {
349*d39a76e7Sxw 	int index = mac->instance->index;
350*d39a76e7Sxw 
351*d39a76e7Sxw 	run_table(mac->adapter, vsc7321_portinit[index],
352*d39a76e7Sxw 		  DIMOF(vsc7321_portinit[index]));
353*d39a76e7Sxw 	return 0;
354*d39a76e7Sxw }
355*d39a76e7Sxw 
356*d39a76e7Sxw /* ARGSUSED */
mac_set_rx_mode(struct cmac * mac,struct t1_rx_mode * rm)357*d39a76e7Sxw static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
358*d39a76e7Sxw {
359*d39a76e7Sxw 	/* Meigs II is always promiscuous. */
360*d39a76e7Sxw 	return 0;
361*d39a76e7Sxw }
362*d39a76e7Sxw 
363*d39a76e7Sxw /* ARGSUSED */
mac_set_mtu(struct cmac * mac,int mtu)364*d39a76e7Sxw static int mac_set_mtu(struct cmac *mac, int mtu)
365*d39a76e7Sxw {
366*d39a76e7Sxw 	return 0;
367*d39a76e7Sxw }
368*d39a76e7Sxw 
369*d39a76e7Sxw /* ARGSUSED */
mac_set_speed_duplex_fc(struct cmac * mac,int speed,int duplex,int fc)370*d39a76e7Sxw static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
371*d39a76e7Sxw 				   int fc)
372*d39a76e7Sxw {
373*d39a76e7Sxw         /* XXX Fixme */
374*d39a76e7Sxw 	return 0;
375*d39a76e7Sxw }
376*d39a76e7Sxw 
mac_enable(struct cmac * mac,int which)377*d39a76e7Sxw static int mac_enable(struct cmac *mac, int which)
378*d39a76e7Sxw {
379*d39a76e7Sxw 	u32 val;
380*d39a76e7Sxw 	int port = mac->instance->index;
381*d39a76e7Sxw 
382*d39a76e7Sxw 	vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
383*d39a76e7Sxw 	if (which & MAC_DIRECTION_RX)
384*d39a76e7Sxw 		val |= 0x2;
385*d39a76e7Sxw 	if (which & MAC_DIRECTION_TX)
386*d39a76e7Sxw 		val |= 1;
387*d39a76e7Sxw 	vsc_write(mac->adapter, REG_MODE_CFG(port), val);
388*d39a76e7Sxw 	return 0;
389*d39a76e7Sxw }
390*d39a76e7Sxw 
mac_disable(struct cmac * mac,int which)391*d39a76e7Sxw static int mac_disable(struct cmac *mac, int which)
392*d39a76e7Sxw {
393*d39a76e7Sxw 	u32 val;
394*d39a76e7Sxw 	int port = mac->instance->index;
395*d39a76e7Sxw 
396*d39a76e7Sxw 	vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
397*d39a76e7Sxw 	if (which & MAC_DIRECTION_RX)
398*d39a76e7Sxw 		val &= ~0x2;
399*d39a76e7Sxw 	if (which & MAC_DIRECTION_TX)
400*d39a76e7Sxw 		val &= ~0x1;
401*d39a76e7Sxw 	vsc_write(mac->adapter, REG_MODE_CFG(port), val);
402*d39a76e7Sxw 	return 0;
403*d39a76e7Sxw }
404*d39a76e7Sxw 
405*d39a76e7Sxw #if 0
406*d39a76e7Sxw /* TBD XXX cmac interface stats will need to assigned to Chelsio's
407*d39a76e7Sxw  *         mac stats.  cmac stats is now just usings Chelsio's
408*d39a76e7Sxw  *         so we don't need the conversion.
409*d39a76e7Sxw  */
410*d39a76e7Sxw int mac_get_statistics(struct cmac* mac, struct cmac_statistics* ps)
411*d39a76e7Sxw {
412*d39a76e7Sxw     port_stats_update(mac);
413*d39a76e7Sxw     return 0;
414*d39a76e7Sxw }
415*d39a76e7Sxw #endif
416*d39a76e7Sxw 
417*d39a76e7Sxw /* ARGSUSED */
mac_update_statistics(struct cmac * mac,int flag)418*d39a76e7Sxw static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
419*d39a76e7Sxw 							   int flag)
420*d39a76e7Sxw {
421*d39a76e7Sxw 	return &mac->stats;
422*d39a76e7Sxw }
423*d39a76e7Sxw 
mac_destroy(struct cmac * mac)424*d39a76e7Sxw static void mac_destroy(struct cmac *mac)
425*d39a76e7Sxw {
426*d39a76e7Sxw 	t1_os_free((void *)mac, sizeof(*mac) + sizeof(cmac_instance));
427*d39a76e7Sxw }
428*d39a76e7Sxw 
429*d39a76e7Sxw #ifdef C99_NOT_SUPPORTED
430*d39a76e7Sxw static struct cmac_ops vsc7321_ops = {
431*d39a76e7Sxw 	mac_destroy,
432*d39a76e7Sxw 	mac_reset,
433*d39a76e7Sxw 	mac_intr_enable,
434*d39a76e7Sxw 	mac_intr_disable,
435*d39a76e7Sxw 	mac_intr_clear,
436*d39a76e7Sxw 	mac_intr_handler,
437*d39a76e7Sxw 	mac_enable,
438*d39a76e7Sxw 	mac_disable,
439*d39a76e7Sxw 	NULL,
440*d39a76e7Sxw 	NULL,
441*d39a76e7Sxw 	mac_set_mtu,
442*d39a76e7Sxw 	mac_set_rx_mode,
443*d39a76e7Sxw 	mac_set_speed_duplex_fc,
444*d39a76e7Sxw 	NULL,
445*d39a76e7Sxw 	mac_update_statistics,
446*d39a76e7Sxw 	mac_get_address,
447*d39a76e7Sxw 	mac_set_address
448*d39a76e7Sxw };
449*d39a76e7Sxw #else
450*d39a76e7Sxw static struct cmac_ops vsc7321_ops = {
451*d39a76e7Sxw 	.destroy                  = mac_destroy,
452*d39a76e7Sxw 	.reset                    = mac_reset,
453*d39a76e7Sxw 	.interrupt_handler        = mac_intr_handler,
454*d39a76e7Sxw 	.interrupt_enable         = mac_intr_enable,
455*d39a76e7Sxw 	.interrupt_disable        = mac_intr_disable,
456*d39a76e7Sxw 	.interrupt_clear          = mac_intr_clear,
457*d39a76e7Sxw 	.enable                   = mac_enable,
458*d39a76e7Sxw 	.disable                  = mac_disable,
459*d39a76e7Sxw 	.set_mtu                  = mac_set_mtu,
460*d39a76e7Sxw 	.set_rx_mode              = mac_set_rx_mode,
461*d39a76e7Sxw 	.set_speed_duplex_fc      = mac_set_speed_duplex_fc,
462*d39a76e7Sxw 	.statistics_update        = mac_update_statistics,
463*d39a76e7Sxw 	.macaddress_get           = mac_get_address,
464*d39a76e7Sxw 	.macaddress_set           = mac_set_address,
465*d39a76e7Sxw };
466*d39a76e7Sxw #endif
467*d39a76e7Sxw 
468*d39a76e7Sxw struct gmac t1_vsc7321_ops = {
469*d39a76e7Sxw 	0,
470*d39a76e7Sxw 	vsc7321_mac_create,
471*d39a76e7Sxw 	vsc7321_mac_reset
472*d39a76e7Sxw };
473