1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* This file is automatically generated --- do not edit */ 23*d39a76e7Sxw 24*d39a76e7Sxw /* SGE registers */ 25*d39a76e7Sxw #define A_SG_CONTROL 0x0 26*d39a76e7Sxw 27*d39a76e7Sxw #define S_CMDQ0_ENABLE 0 28*d39a76e7Sxw #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE) 29*d39a76e7Sxw #define F_CMDQ0_ENABLE V_CMDQ0_ENABLE(1U) 30*d39a76e7Sxw 31*d39a76e7Sxw #define S_CMDQ1_ENABLE 1 32*d39a76e7Sxw #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE) 33*d39a76e7Sxw #define F_CMDQ1_ENABLE V_CMDQ1_ENABLE(1U) 34*d39a76e7Sxw 35*d39a76e7Sxw #define S_FL0_ENABLE 2 36*d39a76e7Sxw #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE) 37*d39a76e7Sxw #define F_FL0_ENABLE V_FL0_ENABLE(1U) 38*d39a76e7Sxw 39*d39a76e7Sxw #define S_FL1_ENABLE 3 40*d39a76e7Sxw #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE) 41*d39a76e7Sxw #define F_FL1_ENABLE V_FL1_ENABLE(1U) 42*d39a76e7Sxw 43*d39a76e7Sxw #define S_CPL_ENABLE 4 44*d39a76e7Sxw #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE) 45*d39a76e7Sxw #define F_CPL_ENABLE V_CPL_ENABLE(1U) 46*d39a76e7Sxw 47*d39a76e7Sxw #define S_RESPONSE_QUEUE_ENABLE 5 48*d39a76e7Sxw #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE) 49*d39a76e7Sxw #define F_RESPONSE_QUEUE_ENABLE V_RESPONSE_QUEUE_ENABLE(1U) 50*d39a76e7Sxw 51*d39a76e7Sxw #define S_CMDQ_PRIORITY 6 52*d39a76e7Sxw #define M_CMDQ_PRIORITY 0x3 53*d39a76e7Sxw #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY) 54*d39a76e7Sxw #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY) 55*d39a76e7Sxw 56*d39a76e7Sxw #define S_DISABLE_CMDQ0_GTS 8 57*d39a76e7Sxw #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS) 58*d39a76e7Sxw #define F_DISABLE_CMDQ0_GTS V_DISABLE_CMDQ0_GTS(1U) 59*d39a76e7Sxw 60*d39a76e7Sxw #define S_DISABLE_CMDQ1_GTS 9 61*d39a76e7Sxw #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS) 62*d39a76e7Sxw #define F_DISABLE_CMDQ1_GTS V_DISABLE_CMDQ1_GTS(1U) 63*d39a76e7Sxw 64*d39a76e7Sxw #define S_DISABLE_FL0_GTS 10 65*d39a76e7Sxw #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS) 66*d39a76e7Sxw #define F_DISABLE_FL0_GTS V_DISABLE_FL0_GTS(1U) 67*d39a76e7Sxw 68*d39a76e7Sxw #define S_DISABLE_FL1_GTS 11 69*d39a76e7Sxw #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS) 70*d39a76e7Sxw #define F_DISABLE_FL1_GTS V_DISABLE_FL1_GTS(1U) 71*d39a76e7Sxw 72*d39a76e7Sxw #define S_ENABLE_BIG_ENDIAN 12 73*d39a76e7Sxw #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN) 74*d39a76e7Sxw #define F_ENABLE_BIG_ENDIAN V_ENABLE_BIG_ENDIAN(1U) 75*d39a76e7Sxw 76*d39a76e7Sxw #define S_FL_SELECTION_CRITERIA 13 77*d39a76e7Sxw #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA) 78*d39a76e7Sxw #define F_FL_SELECTION_CRITERIA V_FL_SELECTION_CRITERIA(1U) 79*d39a76e7Sxw 80*d39a76e7Sxw #define S_ISCSI_COALESCE 14 81*d39a76e7Sxw #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE) 82*d39a76e7Sxw #define F_ISCSI_COALESCE V_ISCSI_COALESCE(1U) 83*d39a76e7Sxw 84*d39a76e7Sxw #define S_RX_PKT_OFFSET 15 85*d39a76e7Sxw #define M_RX_PKT_OFFSET 0x7 86*d39a76e7Sxw #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET) 87*d39a76e7Sxw #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET) 88*d39a76e7Sxw 89*d39a76e7Sxw #define S_VLAN_XTRACT 18 90*d39a76e7Sxw #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT) 91*d39a76e7Sxw #define F_VLAN_XTRACT V_VLAN_XTRACT(1U) 92*d39a76e7Sxw 93*d39a76e7Sxw #define A_SG_DOORBELL 0x4 94*d39a76e7Sxw #define A_SG_CMD0BASELWR 0x8 95*d39a76e7Sxw #define A_SG_CMD0BASEUPR 0xc 96*d39a76e7Sxw #define A_SG_CMD1BASELWR 0x10 97*d39a76e7Sxw #define A_SG_CMD1BASEUPR 0x14 98*d39a76e7Sxw #define A_SG_FL0BASELWR 0x18 99*d39a76e7Sxw #define A_SG_FL0BASEUPR 0x1c 100*d39a76e7Sxw #define A_SG_FL1BASELWR 0x20 101*d39a76e7Sxw #define A_SG_FL1BASEUPR 0x24 102*d39a76e7Sxw #define A_SG_CMD0SIZE 0x28 103*d39a76e7Sxw 104*d39a76e7Sxw #define S_CMDQ0_SIZE 0 105*d39a76e7Sxw #define M_CMDQ0_SIZE 0x1ffff 106*d39a76e7Sxw #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE) 107*d39a76e7Sxw #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE) 108*d39a76e7Sxw 109*d39a76e7Sxw #define A_SG_FL0SIZE 0x2c 110*d39a76e7Sxw 111*d39a76e7Sxw #define S_FL0_SIZE 0 112*d39a76e7Sxw #define M_FL0_SIZE 0x1ffff 113*d39a76e7Sxw #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE) 114*d39a76e7Sxw #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE) 115*d39a76e7Sxw 116*d39a76e7Sxw #define A_SG_RSPSIZE 0x30 117*d39a76e7Sxw 118*d39a76e7Sxw #define S_RESPQ_SIZE 0 119*d39a76e7Sxw #define M_RESPQ_SIZE 0x1ffff 120*d39a76e7Sxw #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE) 121*d39a76e7Sxw #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE) 122*d39a76e7Sxw 123*d39a76e7Sxw #define A_SG_RSPBASELWR 0x34 124*d39a76e7Sxw #define A_SG_RSPBASEUPR 0x38 125*d39a76e7Sxw #define A_SG_FLTHRESHOLD 0x3c 126*d39a76e7Sxw 127*d39a76e7Sxw #define S_FL_THRESHOLD 0 128*d39a76e7Sxw #define M_FL_THRESHOLD 0xffff 129*d39a76e7Sxw #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD) 130*d39a76e7Sxw #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD) 131*d39a76e7Sxw 132*d39a76e7Sxw #define A_SG_RSPQUEUECREDIT 0x40 133*d39a76e7Sxw 134*d39a76e7Sxw #define S_RESPQ_CREDIT 0 135*d39a76e7Sxw #define M_RESPQ_CREDIT 0x1ffff 136*d39a76e7Sxw #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT) 137*d39a76e7Sxw #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT) 138*d39a76e7Sxw 139*d39a76e7Sxw #define A_SG_SLEEPING 0x48 140*d39a76e7Sxw 141*d39a76e7Sxw #define S_SLEEPING 0 142*d39a76e7Sxw #define M_SLEEPING 0xffff 143*d39a76e7Sxw #define V_SLEEPING(x) ((x) << S_SLEEPING) 144*d39a76e7Sxw #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING) 145*d39a76e7Sxw 146*d39a76e7Sxw #define A_SG_INTRTIMER 0x4c 147*d39a76e7Sxw 148*d39a76e7Sxw #define S_INTERRUPT_TIMER_COUNT 0 149*d39a76e7Sxw #define M_INTERRUPT_TIMER_COUNT 0xffffff 150*d39a76e7Sxw #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT) 151*d39a76e7Sxw #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT) 152*d39a76e7Sxw 153*d39a76e7Sxw #define A_SG_CMD0PTR 0x50 154*d39a76e7Sxw 155*d39a76e7Sxw #define S_CMDQ0_POINTER 0 156*d39a76e7Sxw #define M_CMDQ0_POINTER 0xffff 157*d39a76e7Sxw #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER) 158*d39a76e7Sxw #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER) 159*d39a76e7Sxw 160*d39a76e7Sxw #define S_CURRENT_GENERATION_BIT 16 161*d39a76e7Sxw #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT) 162*d39a76e7Sxw #define F_CURRENT_GENERATION_BIT V_CURRENT_GENERATION_BIT(1U) 163*d39a76e7Sxw 164*d39a76e7Sxw #define A_SG_CMD1PTR 0x54 165*d39a76e7Sxw 166*d39a76e7Sxw #define S_CMDQ1_POINTER 0 167*d39a76e7Sxw #define M_CMDQ1_POINTER 0xffff 168*d39a76e7Sxw #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER) 169*d39a76e7Sxw #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER) 170*d39a76e7Sxw 171*d39a76e7Sxw #define A_SG_FL0PTR 0x58 172*d39a76e7Sxw 173*d39a76e7Sxw #define S_FL0_POINTER 0 174*d39a76e7Sxw #define M_FL0_POINTER 0xffff 175*d39a76e7Sxw #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER) 176*d39a76e7Sxw #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER) 177*d39a76e7Sxw 178*d39a76e7Sxw #define A_SG_FL1PTR 0x5c 179*d39a76e7Sxw 180*d39a76e7Sxw #define S_FL1_POINTER 0 181*d39a76e7Sxw #define M_FL1_POINTER 0xffff 182*d39a76e7Sxw #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER) 183*d39a76e7Sxw #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER) 184*d39a76e7Sxw 185*d39a76e7Sxw #define A_SG_VERSION 0x6c 186*d39a76e7Sxw 187*d39a76e7Sxw #define S_DAY 0 188*d39a76e7Sxw #define M_DAY 0x1f 189*d39a76e7Sxw #define V_DAY(x) ((x) << S_DAY) 190*d39a76e7Sxw #define G_DAY(x) (((x) >> S_DAY) & M_DAY) 191*d39a76e7Sxw 192*d39a76e7Sxw #define S_MONTH 5 193*d39a76e7Sxw #define M_MONTH 0xf 194*d39a76e7Sxw #define V_MONTH(x) ((x) << S_MONTH) 195*d39a76e7Sxw #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH) 196*d39a76e7Sxw 197*d39a76e7Sxw #define A_SG_CMD1SIZE 0xb0 198*d39a76e7Sxw 199*d39a76e7Sxw #define S_CMDQ1_SIZE 0 200*d39a76e7Sxw #define M_CMDQ1_SIZE 0x1ffff 201*d39a76e7Sxw #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE) 202*d39a76e7Sxw #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE) 203*d39a76e7Sxw 204*d39a76e7Sxw #define A_SG_FL1SIZE 0xb4 205*d39a76e7Sxw 206*d39a76e7Sxw #define S_FL1_SIZE 0 207*d39a76e7Sxw #define M_FL1_SIZE 0x1ffff 208*d39a76e7Sxw #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE) 209*d39a76e7Sxw #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE) 210*d39a76e7Sxw 211*d39a76e7Sxw #define A_SG_INT_ENABLE 0xb8 212*d39a76e7Sxw 213*d39a76e7Sxw #define S_RESPQ_EXHAUSTED 0 214*d39a76e7Sxw #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED) 215*d39a76e7Sxw #define F_RESPQ_EXHAUSTED V_RESPQ_EXHAUSTED(1U) 216*d39a76e7Sxw 217*d39a76e7Sxw #define S_RESPQ_OVERFLOW 1 218*d39a76e7Sxw #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW) 219*d39a76e7Sxw #define F_RESPQ_OVERFLOW V_RESPQ_OVERFLOW(1U) 220*d39a76e7Sxw 221*d39a76e7Sxw #define S_FL_EXHAUSTED 2 222*d39a76e7Sxw #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED) 223*d39a76e7Sxw #define F_FL_EXHAUSTED V_FL_EXHAUSTED(1U) 224*d39a76e7Sxw 225*d39a76e7Sxw #define S_PACKET_TOO_BIG 3 226*d39a76e7Sxw #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG) 227*d39a76e7Sxw #define F_PACKET_TOO_BIG V_PACKET_TOO_BIG(1U) 228*d39a76e7Sxw 229*d39a76e7Sxw #define S_PACKET_MISMATCH 4 230*d39a76e7Sxw #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH) 231*d39a76e7Sxw #define F_PACKET_MISMATCH V_PACKET_MISMATCH(1U) 232*d39a76e7Sxw 233*d39a76e7Sxw #define A_SG_INT_CAUSE 0xbc 234*d39a76e7Sxw #define A_SG_RESPACCUTIMER 0xc0 235*d39a76e7Sxw 236*d39a76e7Sxw /* MC3 registers */ 237*d39a76e7Sxw #define A_MC3_CFG 0x100 238*d39a76e7Sxw 239*d39a76e7Sxw #define S_CLK_ENABLE 0 240*d39a76e7Sxw #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE) 241*d39a76e7Sxw #define F_CLK_ENABLE V_CLK_ENABLE(1U) 242*d39a76e7Sxw 243*d39a76e7Sxw #define S_READY 1 244*d39a76e7Sxw #define V_READY(x) ((x) << S_READY) 245*d39a76e7Sxw #define F_READY V_READY(1U) 246*d39a76e7Sxw 247*d39a76e7Sxw #define S_READ_TO_WRITE_DELAY 2 248*d39a76e7Sxw #define M_READ_TO_WRITE_DELAY 0x7 249*d39a76e7Sxw #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY) 250*d39a76e7Sxw #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY) 251*d39a76e7Sxw 252*d39a76e7Sxw #define S_WRITE_TO_READ_DELAY 5 253*d39a76e7Sxw #define M_WRITE_TO_READ_DELAY 0x7 254*d39a76e7Sxw #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY) 255*d39a76e7Sxw #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY) 256*d39a76e7Sxw 257*d39a76e7Sxw #define S_MC3_BANK_CYCLE 8 258*d39a76e7Sxw #define M_MC3_BANK_CYCLE 0xf 259*d39a76e7Sxw #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE) 260*d39a76e7Sxw #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE) 261*d39a76e7Sxw 262*d39a76e7Sxw #define S_REFRESH_CYCLE 12 263*d39a76e7Sxw #define M_REFRESH_CYCLE 0xf 264*d39a76e7Sxw #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE) 265*d39a76e7Sxw #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE) 266*d39a76e7Sxw 267*d39a76e7Sxw #define S_PRECHARGE_CYCLE 16 268*d39a76e7Sxw #define M_PRECHARGE_CYCLE 0x3 269*d39a76e7Sxw #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE) 270*d39a76e7Sxw #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE) 271*d39a76e7Sxw 272*d39a76e7Sxw #define S_ACTIVE_TO_READ_WRITE_DELAY 18 273*d39a76e7Sxw #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY) 274*d39a76e7Sxw #define F_ACTIVE_TO_READ_WRITE_DELAY V_ACTIVE_TO_READ_WRITE_DELAY(1U) 275*d39a76e7Sxw 276*d39a76e7Sxw #define S_ACTIVE_TO_PRECHARGE_DELAY 19 277*d39a76e7Sxw #define M_ACTIVE_TO_PRECHARGE_DELAY 0x7 278*d39a76e7Sxw #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY) 279*d39a76e7Sxw #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY) 280*d39a76e7Sxw 281*d39a76e7Sxw #define S_WRITE_RECOVERY_DELAY 22 282*d39a76e7Sxw #define M_WRITE_RECOVERY_DELAY 0x3 283*d39a76e7Sxw #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY) 284*d39a76e7Sxw #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY) 285*d39a76e7Sxw 286*d39a76e7Sxw #define S_DENSITY 24 287*d39a76e7Sxw #define M_DENSITY 0x3 288*d39a76e7Sxw #define V_DENSITY(x) ((x) << S_DENSITY) 289*d39a76e7Sxw #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY) 290*d39a76e7Sxw 291*d39a76e7Sxw #define S_ORGANIZATION 26 292*d39a76e7Sxw #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION) 293*d39a76e7Sxw #define F_ORGANIZATION V_ORGANIZATION(1U) 294*d39a76e7Sxw 295*d39a76e7Sxw #define S_BANKS 27 296*d39a76e7Sxw #define V_BANKS(x) ((x) << S_BANKS) 297*d39a76e7Sxw #define F_BANKS V_BANKS(1U) 298*d39a76e7Sxw 299*d39a76e7Sxw #define S_UNREGISTERED 28 300*d39a76e7Sxw #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED) 301*d39a76e7Sxw #define F_UNREGISTERED V_UNREGISTERED(1U) 302*d39a76e7Sxw 303*d39a76e7Sxw #define S_MC3_WIDTH 29 304*d39a76e7Sxw #define M_MC3_WIDTH 0x3 305*d39a76e7Sxw #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH) 306*d39a76e7Sxw #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH) 307*d39a76e7Sxw 308*d39a76e7Sxw #define S_MC3_SLOW 31 309*d39a76e7Sxw #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW) 310*d39a76e7Sxw #define F_MC3_SLOW V_MC3_SLOW(1U) 311*d39a76e7Sxw 312*d39a76e7Sxw #define A_MC3_MODE 0x104 313*d39a76e7Sxw 314*d39a76e7Sxw #define S_MC3_MODE 0 315*d39a76e7Sxw #define M_MC3_MODE 0x3fff 316*d39a76e7Sxw #define V_MC3_MODE(x) ((x) << S_MC3_MODE) 317*d39a76e7Sxw #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE) 318*d39a76e7Sxw 319*d39a76e7Sxw #define S_BUSY 31 320*d39a76e7Sxw #define V_BUSY(x) ((x) << S_BUSY) 321*d39a76e7Sxw #define F_BUSY V_BUSY(1U) 322*d39a76e7Sxw 323*d39a76e7Sxw #define A_MC3_EXT_MODE 0x108 324*d39a76e7Sxw 325*d39a76e7Sxw #define S_MC3_EXTENDED_MODE 0 326*d39a76e7Sxw #define M_MC3_EXTENDED_MODE 0x3fff 327*d39a76e7Sxw #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE) 328*d39a76e7Sxw #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE) 329*d39a76e7Sxw 330*d39a76e7Sxw #define A_MC3_PRECHARG 0x10c 331*d39a76e7Sxw #define A_MC3_REFRESH 0x110 332*d39a76e7Sxw 333*d39a76e7Sxw #define S_REFRESH_ENABLE 0 334*d39a76e7Sxw #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE) 335*d39a76e7Sxw #define F_REFRESH_ENABLE V_REFRESH_ENABLE(1U) 336*d39a76e7Sxw 337*d39a76e7Sxw #define S_REFRESH_DIVISOR 1 338*d39a76e7Sxw #define M_REFRESH_DIVISOR 0x3fff 339*d39a76e7Sxw #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR) 340*d39a76e7Sxw #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR) 341*d39a76e7Sxw 342*d39a76e7Sxw #define A_MC3_STROBE 0x114 343*d39a76e7Sxw 344*d39a76e7Sxw #define S_MASTER_DLL_RESET 0 345*d39a76e7Sxw #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET) 346*d39a76e7Sxw #define F_MASTER_DLL_RESET V_MASTER_DLL_RESET(1U) 347*d39a76e7Sxw 348*d39a76e7Sxw #define S_MASTER_DLL_TAP_COUNT 1 349*d39a76e7Sxw #define M_MASTER_DLL_TAP_COUNT 0xff 350*d39a76e7Sxw #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT) 351*d39a76e7Sxw #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT) 352*d39a76e7Sxw 353*d39a76e7Sxw #define S_MASTER_DLL_LOCKED 9 354*d39a76e7Sxw #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED) 355*d39a76e7Sxw #define F_MASTER_DLL_LOCKED V_MASTER_DLL_LOCKED(1U) 356*d39a76e7Sxw 357*d39a76e7Sxw #define S_MASTER_DLL_MAX_TAP_COUNT 10 358*d39a76e7Sxw #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT) 359*d39a76e7Sxw #define F_MASTER_DLL_MAX_TAP_COUNT V_MASTER_DLL_MAX_TAP_COUNT(1U) 360*d39a76e7Sxw 361*d39a76e7Sxw #define S_MASTER_DLL_TAP_COUNT_OFFSET 11 362*d39a76e7Sxw #define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f 363*d39a76e7Sxw #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET) 364*d39a76e7Sxw #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET) 365*d39a76e7Sxw 366*d39a76e7Sxw #define S_SLAVE_DLL_RESET 11 367*d39a76e7Sxw #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET) 368*d39a76e7Sxw #define F_SLAVE_DLL_RESET V_SLAVE_DLL_RESET(1U) 369*d39a76e7Sxw 370*d39a76e7Sxw #define S_SLAVE_DLL_DELTA 12 371*d39a76e7Sxw #define M_SLAVE_DLL_DELTA 0xf 372*d39a76e7Sxw #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA) 373*d39a76e7Sxw #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA) 374*d39a76e7Sxw 375*d39a76e7Sxw #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 17 376*d39a76e7Sxw #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f 377*d39a76e7Sxw #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) 378*d39a76e7Sxw #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) 379*d39a76e7Sxw 380*d39a76e7Sxw #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE 23 381*d39a76e7Sxw #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE) 382*d39a76e7Sxw #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U) 383*d39a76e7Sxw 384*d39a76e7Sxw #define S_SLAVE_DELAY_LINE_TAP_COUNT 24 385*d39a76e7Sxw #define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f 386*d39a76e7Sxw #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT) 387*d39a76e7Sxw #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT) 388*d39a76e7Sxw 389*d39a76e7Sxw #define A_MC3_ECC_CNTL 0x118 390*d39a76e7Sxw 391*d39a76e7Sxw #define S_ECC_GENERATION_ENABLE 0 392*d39a76e7Sxw #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE) 393*d39a76e7Sxw #define F_ECC_GENERATION_ENABLE V_ECC_GENERATION_ENABLE(1U) 394*d39a76e7Sxw 395*d39a76e7Sxw #define S_ECC_CHECK_ENABLE 1 396*d39a76e7Sxw #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE) 397*d39a76e7Sxw #define F_ECC_CHECK_ENABLE V_ECC_CHECK_ENABLE(1U) 398*d39a76e7Sxw 399*d39a76e7Sxw #define S_CORRECTABLE_ERROR_COUNT 2 400*d39a76e7Sxw #define M_CORRECTABLE_ERROR_COUNT 0xff 401*d39a76e7Sxw #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT) 402*d39a76e7Sxw #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT) 403*d39a76e7Sxw 404*d39a76e7Sxw #define S_UNCORRECTABLE_ERROR_COUNT 10 405*d39a76e7Sxw #define M_UNCORRECTABLE_ERROR_COUNT 0xff 406*d39a76e7Sxw #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT) 407*d39a76e7Sxw #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT) 408*d39a76e7Sxw 409*d39a76e7Sxw #define A_MC3_CE_ADDR 0x11c 410*d39a76e7Sxw 411*d39a76e7Sxw #define S_MC3_CE_ADDR 4 412*d39a76e7Sxw #define M_MC3_CE_ADDR 0xfffffff 413*d39a76e7Sxw #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR) 414*d39a76e7Sxw #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR) 415*d39a76e7Sxw 416*d39a76e7Sxw #define A_MC3_CE_DATA0 0x120 417*d39a76e7Sxw #define A_MC3_CE_DATA1 0x124 418*d39a76e7Sxw #define A_MC3_CE_DATA2 0x128 419*d39a76e7Sxw #define A_MC3_CE_DATA3 0x12c 420*d39a76e7Sxw #define A_MC3_CE_DATA4 0x130 421*d39a76e7Sxw #define A_MC3_UE_ADDR 0x134 422*d39a76e7Sxw 423*d39a76e7Sxw #define S_MC3_UE_ADDR 4 424*d39a76e7Sxw #define M_MC3_UE_ADDR 0xfffffff 425*d39a76e7Sxw #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR) 426*d39a76e7Sxw #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR) 427*d39a76e7Sxw 428*d39a76e7Sxw #define A_MC3_UE_DATA0 0x138 429*d39a76e7Sxw #define A_MC3_UE_DATA1 0x13c 430*d39a76e7Sxw #define A_MC3_UE_DATA2 0x140 431*d39a76e7Sxw #define A_MC3_UE_DATA3 0x144 432*d39a76e7Sxw #define A_MC3_UE_DATA4 0x148 433*d39a76e7Sxw #define A_MC3_BD_ADDR 0x14c 434*d39a76e7Sxw #define A_MC3_BD_DATA0 0x150 435*d39a76e7Sxw #define A_MC3_BD_DATA1 0x154 436*d39a76e7Sxw #define A_MC3_BD_DATA2 0x158 437*d39a76e7Sxw #define A_MC3_BD_DATA3 0x15c 438*d39a76e7Sxw #define A_MC3_BD_DATA4 0x160 439*d39a76e7Sxw #define A_MC3_BD_OP 0x164 440*d39a76e7Sxw 441*d39a76e7Sxw #define S_BACK_DOOR_OPERATION 0 442*d39a76e7Sxw #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION) 443*d39a76e7Sxw #define F_BACK_DOOR_OPERATION V_BACK_DOOR_OPERATION(1U) 444*d39a76e7Sxw 445*d39a76e7Sxw #define A_MC3_BIST_ADDR_BEG 0x168 446*d39a76e7Sxw #define A_MC3_BIST_ADDR_END 0x16c 447*d39a76e7Sxw #define A_MC3_BIST_DATA 0x170 448*d39a76e7Sxw #define A_MC3_BIST_OP 0x174 449*d39a76e7Sxw 450*d39a76e7Sxw #define S_OP 0 451*d39a76e7Sxw #define V_OP(x) ((x) << S_OP) 452*d39a76e7Sxw #define F_OP V_OP(1U) 453*d39a76e7Sxw 454*d39a76e7Sxw #define S_DATA_PATTERN 1 455*d39a76e7Sxw #define M_DATA_PATTERN 0x3 456*d39a76e7Sxw #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN) 457*d39a76e7Sxw #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN) 458*d39a76e7Sxw 459*d39a76e7Sxw #define S_CONTINUOUS 3 460*d39a76e7Sxw #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS) 461*d39a76e7Sxw #define F_CONTINUOUS V_CONTINUOUS(1U) 462*d39a76e7Sxw 463*d39a76e7Sxw #define A_MC3_INT_ENABLE 0x178 464*d39a76e7Sxw 465*d39a76e7Sxw #define S_MC3_CORR_ERR 0 466*d39a76e7Sxw #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR) 467*d39a76e7Sxw #define F_MC3_CORR_ERR V_MC3_CORR_ERR(1U) 468*d39a76e7Sxw 469*d39a76e7Sxw #define S_MC3_UNCORR_ERR 1 470*d39a76e7Sxw #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR) 471*d39a76e7Sxw #define F_MC3_UNCORR_ERR V_MC3_UNCORR_ERR(1U) 472*d39a76e7Sxw 473*d39a76e7Sxw #define S_MC3_PARITY_ERR 2 474*d39a76e7Sxw #define M_MC3_PARITY_ERR 0xff 475*d39a76e7Sxw #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR) 476*d39a76e7Sxw #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR) 477*d39a76e7Sxw 478*d39a76e7Sxw #define S_MC3_ADDR_ERR 10 479*d39a76e7Sxw #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR) 480*d39a76e7Sxw #define F_MC3_ADDR_ERR V_MC3_ADDR_ERR(1U) 481*d39a76e7Sxw 482*d39a76e7Sxw #define A_MC3_INT_CAUSE 0x17c 483*d39a76e7Sxw 484*d39a76e7Sxw /* MC4 registers */ 485*d39a76e7Sxw #define A_MC4_CFG 0x180 486*d39a76e7Sxw 487*d39a76e7Sxw #define S_POWER_UP 0 488*d39a76e7Sxw #define V_POWER_UP(x) ((x) << S_POWER_UP) 489*d39a76e7Sxw #define F_POWER_UP V_POWER_UP(1U) 490*d39a76e7Sxw 491*d39a76e7Sxw #define S_MC4_BANK_CYCLE 8 492*d39a76e7Sxw #define M_MC4_BANK_CYCLE 0x7 493*d39a76e7Sxw #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE) 494*d39a76e7Sxw #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE) 495*d39a76e7Sxw 496*d39a76e7Sxw #define S_MC4_NARROW 24 497*d39a76e7Sxw #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW) 498*d39a76e7Sxw #define F_MC4_NARROW V_MC4_NARROW(1U) 499*d39a76e7Sxw 500*d39a76e7Sxw #define S_MC4_SLOW 25 501*d39a76e7Sxw #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW) 502*d39a76e7Sxw #define F_MC4_SLOW V_MC4_SLOW(1U) 503*d39a76e7Sxw 504*d39a76e7Sxw #define S_MC4A_WIDTH 24 505*d39a76e7Sxw #define M_MC4A_WIDTH 0x3 506*d39a76e7Sxw #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH) 507*d39a76e7Sxw #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH) 508*d39a76e7Sxw 509*d39a76e7Sxw #define S_MC4A_SLOW 26 510*d39a76e7Sxw #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW) 511*d39a76e7Sxw #define F_MC4A_SLOW V_MC4A_SLOW(1U) 512*d39a76e7Sxw 513*d39a76e7Sxw #define A_MC4_MODE 0x184 514*d39a76e7Sxw 515*d39a76e7Sxw #define S_MC4_MODE 0 516*d39a76e7Sxw #define M_MC4_MODE 0x7fff 517*d39a76e7Sxw #define V_MC4_MODE(x) ((x) << S_MC4_MODE) 518*d39a76e7Sxw #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE) 519*d39a76e7Sxw 520*d39a76e7Sxw #define A_MC4_EXT_MODE 0x188 521*d39a76e7Sxw 522*d39a76e7Sxw #define S_MC4_EXTENDED_MODE 0 523*d39a76e7Sxw #define M_MC4_EXTENDED_MODE 0x7fff 524*d39a76e7Sxw #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE) 525*d39a76e7Sxw #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE) 526*d39a76e7Sxw 527*d39a76e7Sxw #define A_MC4_REFRESH 0x190 528*d39a76e7Sxw #define A_MC4_STROBE 0x194 529*d39a76e7Sxw #define A_MC4_ECC_CNTL 0x198 530*d39a76e7Sxw #define A_MC4_CE_ADDR 0x19c 531*d39a76e7Sxw 532*d39a76e7Sxw #define S_MC4_CE_ADDR 4 533*d39a76e7Sxw #define M_MC4_CE_ADDR 0xffffff 534*d39a76e7Sxw #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR) 535*d39a76e7Sxw #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR) 536*d39a76e7Sxw 537*d39a76e7Sxw #define A_MC4_CE_DATA0 0x1a0 538*d39a76e7Sxw #define A_MC4_CE_DATA1 0x1a4 539*d39a76e7Sxw #define A_MC4_CE_DATA2 0x1a8 540*d39a76e7Sxw #define A_MC4_CE_DATA3 0x1ac 541*d39a76e7Sxw #define A_MC4_CE_DATA4 0x1b0 542*d39a76e7Sxw #define A_MC4_UE_ADDR 0x1b4 543*d39a76e7Sxw 544*d39a76e7Sxw #define S_MC4_UE_ADDR 4 545*d39a76e7Sxw #define M_MC4_UE_ADDR 0xffffff 546*d39a76e7Sxw #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR) 547*d39a76e7Sxw #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR) 548*d39a76e7Sxw 549*d39a76e7Sxw #define A_MC4_UE_DATA0 0x1b8 550*d39a76e7Sxw #define A_MC4_UE_DATA1 0x1bc 551*d39a76e7Sxw #define A_MC4_UE_DATA2 0x1c0 552*d39a76e7Sxw #define A_MC4_UE_DATA3 0x1c4 553*d39a76e7Sxw #define A_MC4_UE_DATA4 0x1c8 554*d39a76e7Sxw #define A_MC4_BD_ADDR 0x1cc 555*d39a76e7Sxw 556*d39a76e7Sxw #define S_MC4_BACK_DOOR_ADDR 0 557*d39a76e7Sxw #define M_MC4_BACK_DOOR_ADDR 0xfffffff 558*d39a76e7Sxw #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR) 559*d39a76e7Sxw #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR) 560*d39a76e7Sxw 561*d39a76e7Sxw #define A_MC4_BD_DATA0 0x1d0 562*d39a76e7Sxw #define A_MC4_BD_DATA1 0x1d4 563*d39a76e7Sxw #define A_MC4_BD_DATA2 0x1d8 564*d39a76e7Sxw #define A_MC4_BD_DATA3 0x1dc 565*d39a76e7Sxw #define A_MC4_BD_DATA4 0x1e0 566*d39a76e7Sxw #define A_MC4_BD_OP 0x1e4 567*d39a76e7Sxw 568*d39a76e7Sxw #define S_OPERATION 0 569*d39a76e7Sxw #define V_OPERATION(x) ((x) << S_OPERATION) 570*d39a76e7Sxw #define F_OPERATION V_OPERATION(1U) 571*d39a76e7Sxw 572*d39a76e7Sxw #define A_MC4_BIST_ADDR_BEG 0x1e8 573*d39a76e7Sxw #define A_MC4_BIST_ADDR_END 0x1ec 574*d39a76e7Sxw #define A_MC4_BIST_DATA 0x1f0 575*d39a76e7Sxw #define A_MC4_BIST_OP 0x1f4 576*d39a76e7Sxw #define A_MC4_INT_ENABLE 0x1f8 577*d39a76e7Sxw 578*d39a76e7Sxw #define S_MC4_CORR_ERR 0 579*d39a76e7Sxw #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR) 580*d39a76e7Sxw #define F_MC4_CORR_ERR V_MC4_CORR_ERR(1U) 581*d39a76e7Sxw 582*d39a76e7Sxw #define S_MC4_UNCORR_ERR 1 583*d39a76e7Sxw #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR) 584*d39a76e7Sxw #define F_MC4_UNCORR_ERR V_MC4_UNCORR_ERR(1U) 585*d39a76e7Sxw 586*d39a76e7Sxw #define S_MC4_ADDR_ERR 2 587*d39a76e7Sxw #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR) 588*d39a76e7Sxw #define F_MC4_ADDR_ERR V_MC4_ADDR_ERR(1U) 589*d39a76e7Sxw 590*d39a76e7Sxw #define A_MC4_INT_CAUSE 0x1fc 591*d39a76e7Sxw 592*d39a76e7Sxw /* TPI registers */ 593*d39a76e7Sxw #define A_TPI_ADDR 0x280 594*d39a76e7Sxw 595*d39a76e7Sxw #define S_TPI_ADDRESS 0 596*d39a76e7Sxw #define M_TPI_ADDRESS 0xffffff 597*d39a76e7Sxw #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS) 598*d39a76e7Sxw #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS) 599*d39a76e7Sxw 600*d39a76e7Sxw #define A_TPI_WR_DATA 0x284 601*d39a76e7Sxw #define A_TPI_RD_DATA 0x288 602*d39a76e7Sxw #define A_TPI_CSR 0x28c 603*d39a76e7Sxw 604*d39a76e7Sxw #define S_TPIWR 0 605*d39a76e7Sxw #define V_TPIWR(x) ((x) << S_TPIWR) 606*d39a76e7Sxw #define F_TPIWR V_TPIWR(1U) 607*d39a76e7Sxw 608*d39a76e7Sxw #define S_TPIRDY 1 609*d39a76e7Sxw #define V_TPIRDY(x) ((x) << S_TPIRDY) 610*d39a76e7Sxw #define F_TPIRDY V_TPIRDY(1U) 611*d39a76e7Sxw 612*d39a76e7Sxw #define S_INT_DIR 31 613*d39a76e7Sxw #define V_INT_DIR(x) ((x) << S_INT_DIR) 614*d39a76e7Sxw #define F_INT_DIR V_INT_DIR(1U) 615*d39a76e7Sxw 616*d39a76e7Sxw #define A_TPI_PAR 0x29c 617*d39a76e7Sxw 618*d39a76e7Sxw #define S_TPIPAR 0 619*d39a76e7Sxw #define M_TPIPAR 0x7f 620*d39a76e7Sxw #define V_TPIPAR(x) ((x) << S_TPIPAR) 621*d39a76e7Sxw #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR) 622*d39a76e7Sxw 623*d39a76e7Sxw 624*d39a76e7Sxw /* TP registers */ 625*d39a76e7Sxw #define A_TP_IN_CONFIG 0x300 626*d39a76e7Sxw 627*d39a76e7Sxw #define S_TP_IN_CSPI_TUNNEL 0 628*d39a76e7Sxw #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL) 629*d39a76e7Sxw #define F_TP_IN_CSPI_TUNNEL V_TP_IN_CSPI_TUNNEL(1U) 630*d39a76e7Sxw 631*d39a76e7Sxw #define S_TP_IN_CSPI_ETHERNET 1 632*d39a76e7Sxw #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET) 633*d39a76e7Sxw #define F_TP_IN_CSPI_ETHERNET V_TP_IN_CSPI_ETHERNET(1U) 634*d39a76e7Sxw 635*d39a76e7Sxw #define S_TP_IN_CSPI_CPL 3 636*d39a76e7Sxw #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL) 637*d39a76e7Sxw #define F_TP_IN_CSPI_CPL V_TP_IN_CSPI_CPL(1U) 638*d39a76e7Sxw 639*d39a76e7Sxw #define S_TP_IN_CSPI_POS 4 640*d39a76e7Sxw #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS) 641*d39a76e7Sxw #define F_TP_IN_CSPI_POS V_TP_IN_CSPI_POS(1U) 642*d39a76e7Sxw 643*d39a76e7Sxw #define S_TP_IN_CSPI_CHECK_IP_CSUM 5 644*d39a76e7Sxw #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM) 645*d39a76e7Sxw #define F_TP_IN_CSPI_CHECK_IP_CSUM V_TP_IN_CSPI_CHECK_IP_CSUM(1U) 646*d39a76e7Sxw 647*d39a76e7Sxw #define S_TP_IN_CSPI_CHECK_TCP_CSUM 6 648*d39a76e7Sxw #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM) 649*d39a76e7Sxw #define F_TP_IN_CSPI_CHECK_TCP_CSUM V_TP_IN_CSPI_CHECK_TCP_CSUM(1U) 650*d39a76e7Sxw 651*d39a76e7Sxw #define S_TP_IN_ESPI_TUNNEL 7 652*d39a76e7Sxw #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL) 653*d39a76e7Sxw #define F_TP_IN_ESPI_TUNNEL V_TP_IN_ESPI_TUNNEL(1U) 654*d39a76e7Sxw 655*d39a76e7Sxw #define S_TP_IN_ESPI_ETHERNET 8 656*d39a76e7Sxw #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET) 657*d39a76e7Sxw #define F_TP_IN_ESPI_ETHERNET V_TP_IN_ESPI_ETHERNET(1U) 658*d39a76e7Sxw 659*d39a76e7Sxw #define S_TP_IN_ESPI_CPL 10 660*d39a76e7Sxw #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL) 661*d39a76e7Sxw #define F_TP_IN_ESPI_CPL V_TP_IN_ESPI_CPL(1U) 662*d39a76e7Sxw 663*d39a76e7Sxw #define S_TP_IN_ESPI_POS 11 664*d39a76e7Sxw #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS) 665*d39a76e7Sxw #define F_TP_IN_ESPI_POS V_TP_IN_ESPI_POS(1U) 666*d39a76e7Sxw 667*d39a76e7Sxw #define S_TP_IN_ESPI_CHECK_IP_CSUM 12 668*d39a76e7Sxw #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM) 669*d39a76e7Sxw #define F_TP_IN_ESPI_CHECK_IP_CSUM V_TP_IN_ESPI_CHECK_IP_CSUM(1U) 670*d39a76e7Sxw 671*d39a76e7Sxw #define S_TP_IN_ESPI_CHECK_TCP_CSUM 13 672*d39a76e7Sxw #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM) 673*d39a76e7Sxw #define F_TP_IN_ESPI_CHECK_TCP_CSUM V_TP_IN_ESPI_CHECK_TCP_CSUM(1U) 674*d39a76e7Sxw 675*d39a76e7Sxw #define S_OFFLOAD_DISABLE 14 676*d39a76e7Sxw #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE) 677*d39a76e7Sxw #define F_OFFLOAD_DISABLE V_OFFLOAD_DISABLE(1U) 678*d39a76e7Sxw 679*d39a76e7Sxw #define A_TP_OUT_CONFIG 0x304 680*d39a76e7Sxw 681*d39a76e7Sxw #define S_TP_OUT_C_ETH 0 682*d39a76e7Sxw #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH) 683*d39a76e7Sxw #define F_TP_OUT_C_ETH V_TP_OUT_C_ETH(1U) 684*d39a76e7Sxw 685*d39a76e7Sxw #define S_TP_OUT_CSPI_CPL 2 686*d39a76e7Sxw #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL) 687*d39a76e7Sxw #define F_TP_OUT_CSPI_CPL V_TP_OUT_CSPI_CPL(1U) 688*d39a76e7Sxw 689*d39a76e7Sxw #define S_TP_OUT_CSPI_POS 3 690*d39a76e7Sxw #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS) 691*d39a76e7Sxw #define F_TP_OUT_CSPI_POS V_TP_OUT_CSPI_POS(1U) 692*d39a76e7Sxw 693*d39a76e7Sxw #define S_TP_OUT_CSPI_GENERATE_IP_CSUM 4 694*d39a76e7Sxw #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM) 695*d39a76e7Sxw #define F_TP_OUT_CSPI_GENERATE_IP_CSUM V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U) 696*d39a76e7Sxw 697*d39a76e7Sxw #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM 5 698*d39a76e7Sxw #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM) 699*d39a76e7Sxw #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U) 700*d39a76e7Sxw 701*d39a76e7Sxw #define S_TP_OUT_ESPI_ETHERNET 6 702*d39a76e7Sxw #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET) 703*d39a76e7Sxw #define F_TP_OUT_ESPI_ETHERNET V_TP_OUT_ESPI_ETHERNET(1U) 704*d39a76e7Sxw 705*d39a76e7Sxw #define S_TP_OUT_ESPI_TAG_ETHERNET 7 706*d39a76e7Sxw #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET) 707*d39a76e7Sxw #define F_TP_OUT_ESPI_TAG_ETHERNET V_TP_OUT_ESPI_TAG_ETHERNET(1U) 708*d39a76e7Sxw 709*d39a76e7Sxw #define S_TP_OUT_ESPI_CPL 8 710*d39a76e7Sxw #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL) 711*d39a76e7Sxw #define F_TP_OUT_ESPI_CPL V_TP_OUT_ESPI_CPL(1U) 712*d39a76e7Sxw 713*d39a76e7Sxw #define S_TP_OUT_ESPI_POS 9 714*d39a76e7Sxw #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS) 715*d39a76e7Sxw #define F_TP_OUT_ESPI_POS V_TP_OUT_ESPI_POS(1U) 716*d39a76e7Sxw 717*d39a76e7Sxw #define S_TP_OUT_ESPI_GENERATE_IP_CSUM 10 718*d39a76e7Sxw #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM) 719*d39a76e7Sxw #define F_TP_OUT_ESPI_GENERATE_IP_CSUM V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U) 720*d39a76e7Sxw 721*d39a76e7Sxw #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM 11 722*d39a76e7Sxw #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM) 723*d39a76e7Sxw #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U) 724*d39a76e7Sxw 725*d39a76e7Sxw #define A_TP_GLOBAL_CONFIG 0x308 726*d39a76e7Sxw 727*d39a76e7Sxw #define S_IP_TTL 0 728*d39a76e7Sxw #define M_IP_TTL 0xff 729*d39a76e7Sxw #define V_IP_TTL(x) ((x) << S_IP_TTL) 730*d39a76e7Sxw #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL) 731*d39a76e7Sxw 732*d39a76e7Sxw #define S_TCAM_SERVER_REGION_USAGE 8 733*d39a76e7Sxw #define M_TCAM_SERVER_REGION_USAGE 0x3 734*d39a76e7Sxw #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE) 735*d39a76e7Sxw #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE) 736*d39a76e7Sxw 737*d39a76e7Sxw #define S_QOS_MAPPING 10 738*d39a76e7Sxw #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING) 739*d39a76e7Sxw #define F_QOS_MAPPING V_QOS_MAPPING(1U) 740*d39a76e7Sxw 741*d39a76e7Sxw #define S_TCP_CSUM 11 742*d39a76e7Sxw #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM) 743*d39a76e7Sxw #define F_TCP_CSUM V_TCP_CSUM(1U) 744*d39a76e7Sxw 745*d39a76e7Sxw #define S_UDP_CSUM 12 746*d39a76e7Sxw #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM) 747*d39a76e7Sxw #define F_UDP_CSUM V_UDP_CSUM(1U) 748*d39a76e7Sxw 749*d39a76e7Sxw #define S_IP_CSUM 13 750*d39a76e7Sxw #define V_IP_CSUM(x) ((x) << S_IP_CSUM) 751*d39a76e7Sxw #define F_IP_CSUM V_IP_CSUM(1U) 752*d39a76e7Sxw 753*d39a76e7Sxw #define S_IP_ID_SPLIT 14 754*d39a76e7Sxw #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT) 755*d39a76e7Sxw #define F_IP_ID_SPLIT V_IP_ID_SPLIT(1U) 756*d39a76e7Sxw 757*d39a76e7Sxw #define S_PATH_MTU 15 758*d39a76e7Sxw #define V_PATH_MTU(x) ((x) << S_PATH_MTU) 759*d39a76e7Sxw #define F_PATH_MTU V_PATH_MTU(1U) 760*d39a76e7Sxw 761*d39a76e7Sxw #define S_5TUPLE_LOOKUP 17 762*d39a76e7Sxw #define M_5TUPLE_LOOKUP 0x3 763*d39a76e7Sxw #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP) 764*d39a76e7Sxw #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP) 765*d39a76e7Sxw 766*d39a76e7Sxw #define S_IP_FRAGMENT_DROP 19 767*d39a76e7Sxw #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP) 768*d39a76e7Sxw #define F_IP_FRAGMENT_DROP V_IP_FRAGMENT_DROP(1U) 769*d39a76e7Sxw 770*d39a76e7Sxw #define S_PING_DROP 20 771*d39a76e7Sxw #define V_PING_DROP(x) ((x) << S_PING_DROP) 772*d39a76e7Sxw #define F_PING_DROP V_PING_DROP(1U) 773*d39a76e7Sxw 774*d39a76e7Sxw #define S_PROTECT_MODE 21 775*d39a76e7Sxw #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE) 776*d39a76e7Sxw #define F_PROTECT_MODE V_PROTECT_MODE(1U) 777*d39a76e7Sxw 778*d39a76e7Sxw #define S_SYN_COOKIE_ALGORITHM 22 779*d39a76e7Sxw #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM) 780*d39a76e7Sxw #define F_SYN_COOKIE_ALGORITHM V_SYN_COOKIE_ALGORITHM(1U) 781*d39a76e7Sxw 782*d39a76e7Sxw #define S_ATTACK_FILTER 23 783*d39a76e7Sxw #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER) 784*d39a76e7Sxw #define F_ATTACK_FILTER V_ATTACK_FILTER(1U) 785*d39a76e7Sxw 786*d39a76e7Sxw #define S_INTERFACE_TYPE 24 787*d39a76e7Sxw #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE) 788*d39a76e7Sxw #define F_INTERFACE_TYPE V_INTERFACE_TYPE(1U) 789*d39a76e7Sxw 790*d39a76e7Sxw #define S_DISABLE_RX_FLOW_CONTROL 25 791*d39a76e7Sxw #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL) 792*d39a76e7Sxw #define F_DISABLE_RX_FLOW_CONTROL V_DISABLE_RX_FLOW_CONTROL(1U) 793*d39a76e7Sxw 794*d39a76e7Sxw #define S_SYN_COOKIE_PARAMETER 26 795*d39a76e7Sxw #define M_SYN_COOKIE_PARAMETER 0x3f 796*d39a76e7Sxw #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER) 797*d39a76e7Sxw #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER) 798*d39a76e7Sxw 799*d39a76e7Sxw #define A_TP_GLOBAL_RX_CREDITS 0x30c 800*d39a76e7Sxw #define A_TP_CM_SIZE 0x310 801*d39a76e7Sxw #define A_TP_CM_MM_BASE 0x314 802*d39a76e7Sxw 803*d39a76e7Sxw #define S_CM_MEMMGR_BASE 0 804*d39a76e7Sxw #define M_CM_MEMMGR_BASE 0xfffffff 805*d39a76e7Sxw #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE) 806*d39a76e7Sxw #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE) 807*d39a76e7Sxw 808*d39a76e7Sxw #define A_TP_CM_TIMER_BASE 0x318 809*d39a76e7Sxw 810*d39a76e7Sxw #define S_CM_TIMER_BASE 0 811*d39a76e7Sxw #define M_CM_TIMER_BASE 0xfffffff 812*d39a76e7Sxw #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE) 813*d39a76e7Sxw #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE) 814*d39a76e7Sxw 815*d39a76e7Sxw #define A_TP_PM_SIZE 0x31c 816*d39a76e7Sxw #define A_TP_PM_TX_BASE 0x320 817*d39a76e7Sxw #define A_TP_PM_DEFRAG_BASE 0x324 818*d39a76e7Sxw #define A_TP_PM_RX_BASE 0x328 819*d39a76e7Sxw #define A_TP_PM_RX_PG_SIZE 0x32c 820*d39a76e7Sxw #define A_TP_PM_RX_MAX_PGS 0x330 821*d39a76e7Sxw #define A_TP_PM_TX_PG_SIZE 0x334 822*d39a76e7Sxw #define A_TP_PM_TX_MAX_PGS 0x338 823*d39a76e7Sxw #define A_TP_TCP_OPTIONS 0x340 824*d39a76e7Sxw 825*d39a76e7Sxw #define S_TIMESTAMP 0 826*d39a76e7Sxw #define M_TIMESTAMP 0x3 827*d39a76e7Sxw #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP) 828*d39a76e7Sxw #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP) 829*d39a76e7Sxw 830*d39a76e7Sxw #define S_WINDOW_SCALE 2 831*d39a76e7Sxw #define M_WINDOW_SCALE 0x3 832*d39a76e7Sxw #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE) 833*d39a76e7Sxw #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE) 834*d39a76e7Sxw 835*d39a76e7Sxw #define S_SACK 4 836*d39a76e7Sxw #define M_SACK 0x3 837*d39a76e7Sxw #define V_SACK(x) ((x) << S_SACK) 838*d39a76e7Sxw #define G_SACK(x) (((x) >> S_SACK) & M_SACK) 839*d39a76e7Sxw 840*d39a76e7Sxw #define S_ECN 6 841*d39a76e7Sxw #define M_ECN 0x3 842*d39a76e7Sxw #define V_ECN(x) ((x) << S_ECN) 843*d39a76e7Sxw #define G_ECN(x) (((x) >> S_ECN) & M_ECN) 844*d39a76e7Sxw 845*d39a76e7Sxw #define S_SACK_ALGORITHM 8 846*d39a76e7Sxw #define M_SACK_ALGORITHM 0x3 847*d39a76e7Sxw #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM) 848*d39a76e7Sxw #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM) 849*d39a76e7Sxw 850*d39a76e7Sxw #define S_MSS 10 851*d39a76e7Sxw #define V_MSS(x) ((x) << S_MSS) 852*d39a76e7Sxw #define F_MSS V_MSS(1U) 853*d39a76e7Sxw 854*d39a76e7Sxw #define S_DEFAULT_PEER_MSS 16 855*d39a76e7Sxw #define M_DEFAULT_PEER_MSS 0xffff 856*d39a76e7Sxw #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS) 857*d39a76e7Sxw #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS) 858*d39a76e7Sxw 859*d39a76e7Sxw #define A_TP_DACK_CONFIG 0x344 860*d39a76e7Sxw 861*d39a76e7Sxw #define S_DACK_MODE 0 862*d39a76e7Sxw #define V_DACK_MODE(x) ((x) << S_DACK_MODE) 863*d39a76e7Sxw #define F_DACK_MODE V_DACK_MODE(1U) 864*d39a76e7Sxw 865*d39a76e7Sxw #define S_DACK_AUTO_MGMT 1 866*d39a76e7Sxw #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT) 867*d39a76e7Sxw #define F_DACK_AUTO_MGMT V_DACK_AUTO_MGMT(1U) 868*d39a76e7Sxw 869*d39a76e7Sxw #define S_DACK_AUTO_CAREFUL 2 870*d39a76e7Sxw #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL) 871*d39a76e7Sxw #define F_DACK_AUTO_CAREFUL V_DACK_AUTO_CAREFUL(1U) 872*d39a76e7Sxw 873*d39a76e7Sxw #define S_DACK_MSS_SELECTOR 3 874*d39a76e7Sxw #define M_DACK_MSS_SELECTOR 0x3 875*d39a76e7Sxw #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR) 876*d39a76e7Sxw #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR) 877*d39a76e7Sxw 878*d39a76e7Sxw #define S_DACK_BYTE_THRESHOLD 5 879*d39a76e7Sxw #define M_DACK_BYTE_THRESHOLD 0xfffff 880*d39a76e7Sxw #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD) 881*d39a76e7Sxw #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD) 882*d39a76e7Sxw 883*d39a76e7Sxw #define A_TP_PC_CONFIG 0x348 884*d39a76e7Sxw 885*d39a76e7Sxw #define S_TP_ACCESS_LATENCY 0 886*d39a76e7Sxw #define M_TP_ACCESS_LATENCY 0xf 887*d39a76e7Sxw #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY) 888*d39a76e7Sxw #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY) 889*d39a76e7Sxw 890*d39a76e7Sxw #define S_HELD_FIN_DISABLE 4 891*d39a76e7Sxw #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE) 892*d39a76e7Sxw #define F_HELD_FIN_DISABLE V_HELD_FIN_DISABLE(1U) 893*d39a76e7Sxw 894*d39a76e7Sxw #define S_DDP_FC_ENABLE 5 895*d39a76e7Sxw #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE) 896*d39a76e7Sxw #define F_DDP_FC_ENABLE V_DDP_FC_ENABLE(1U) 897*d39a76e7Sxw 898*d39a76e7Sxw #define S_RDMA_ERR_ENABLE 6 899*d39a76e7Sxw #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE) 900*d39a76e7Sxw #define F_RDMA_ERR_ENABLE V_RDMA_ERR_ENABLE(1U) 901*d39a76e7Sxw 902*d39a76e7Sxw #define S_FAST_PDU_DELIVERY 7 903*d39a76e7Sxw #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY) 904*d39a76e7Sxw #define F_FAST_PDU_DELIVERY V_FAST_PDU_DELIVERY(1U) 905*d39a76e7Sxw 906*d39a76e7Sxw #define S_CLEAR_FIN 8 907*d39a76e7Sxw #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN) 908*d39a76e7Sxw #define F_CLEAR_FIN V_CLEAR_FIN(1U) 909*d39a76e7Sxw 910*d39a76e7Sxw #define S_DIS_TX_FILL_WIN_PUSH 12 911*d39a76e7Sxw #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH) 912*d39a76e7Sxw #define F_DIS_TX_FILL_WIN_PUSH V_DIS_TX_FILL_WIN_PUSH(1U) 913*d39a76e7Sxw 914*d39a76e7Sxw #define S_TP_PC_REV 30 915*d39a76e7Sxw #define M_TP_PC_REV 0x3 916*d39a76e7Sxw #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV) 917*d39a76e7Sxw #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV) 918*d39a76e7Sxw 919*d39a76e7Sxw #define A_TP_BACKOFF0 0x350 920*d39a76e7Sxw 921*d39a76e7Sxw #define S_ELEMENT0 0 922*d39a76e7Sxw #define M_ELEMENT0 0xff 923*d39a76e7Sxw #define V_ELEMENT0(x) ((x) << S_ELEMENT0) 924*d39a76e7Sxw #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0) 925*d39a76e7Sxw 926*d39a76e7Sxw #define S_ELEMENT1 8 927*d39a76e7Sxw #define M_ELEMENT1 0xff 928*d39a76e7Sxw #define V_ELEMENT1(x) ((x) << S_ELEMENT1) 929*d39a76e7Sxw #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1) 930*d39a76e7Sxw 931*d39a76e7Sxw #define S_ELEMENT2 16 932*d39a76e7Sxw #define M_ELEMENT2 0xff 933*d39a76e7Sxw #define V_ELEMENT2(x) ((x) << S_ELEMENT2) 934*d39a76e7Sxw #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2) 935*d39a76e7Sxw 936*d39a76e7Sxw #define S_ELEMENT3 24 937*d39a76e7Sxw #define M_ELEMENT3 0xff 938*d39a76e7Sxw #define V_ELEMENT3(x) ((x) << S_ELEMENT3) 939*d39a76e7Sxw #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3) 940*d39a76e7Sxw 941*d39a76e7Sxw #define A_TP_BACKOFF1 0x354 942*d39a76e7Sxw #define A_TP_BACKOFF2 0x358 943*d39a76e7Sxw #define A_TP_BACKOFF3 0x35c 944*d39a76e7Sxw #define A_TP_PARA_REG0 0x360 945*d39a76e7Sxw 946*d39a76e7Sxw #define S_VAR_MULT 0 947*d39a76e7Sxw #define M_VAR_MULT 0xf 948*d39a76e7Sxw #define V_VAR_MULT(x) ((x) << S_VAR_MULT) 949*d39a76e7Sxw #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT) 950*d39a76e7Sxw 951*d39a76e7Sxw #define S_VAR_GAIN 4 952*d39a76e7Sxw #define M_VAR_GAIN 0xf 953*d39a76e7Sxw #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN) 954*d39a76e7Sxw #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN) 955*d39a76e7Sxw 956*d39a76e7Sxw #define S_SRTT_GAIN 8 957*d39a76e7Sxw #define M_SRTT_GAIN 0xf 958*d39a76e7Sxw #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN) 959*d39a76e7Sxw #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN) 960*d39a76e7Sxw 961*d39a76e7Sxw #define S_RTTVAR_INIT 12 962*d39a76e7Sxw #define M_RTTVAR_INIT 0xf 963*d39a76e7Sxw #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT) 964*d39a76e7Sxw #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT) 965*d39a76e7Sxw 966*d39a76e7Sxw #define S_DUP_THRESH 20 967*d39a76e7Sxw #define M_DUP_THRESH 0xf 968*d39a76e7Sxw #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH) 969*d39a76e7Sxw #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH) 970*d39a76e7Sxw 971*d39a76e7Sxw #define S_INIT_CONG_WIN 24 972*d39a76e7Sxw #define M_INIT_CONG_WIN 0x7 973*d39a76e7Sxw #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN) 974*d39a76e7Sxw #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN) 975*d39a76e7Sxw 976*d39a76e7Sxw #define A_TP_PARA_REG1 0x364 977*d39a76e7Sxw 978*d39a76e7Sxw #define S_INITIAL_SLOW_START_THRESHOLD 0 979*d39a76e7Sxw #define M_INITIAL_SLOW_START_THRESHOLD 0xffff 980*d39a76e7Sxw #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD) 981*d39a76e7Sxw #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD) 982*d39a76e7Sxw 983*d39a76e7Sxw #define S_RECEIVE_BUFFER_SIZE 16 984*d39a76e7Sxw #define M_RECEIVE_BUFFER_SIZE 0xffff 985*d39a76e7Sxw #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE) 986*d39a76e7Sxw #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE) 987*d39a76e7Sxw 988*d39a76e7Sxw #define A_TP_PARA_REG2 0x368 989*d39a76e7Sxw 990*d39a76e7Sxw #define S_RX_COALESCE_SIZE 0 991*d39a76e7Sxw #define M_RX_COALESCE_SIZE 0xffff 992*d39a76e7Sxw #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE) 993*d39a76e7Sxw #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE) 994*d39a76e7Sxw 995*d39a76e7Sxw #define S_MAX_RX_SIZE 16 996*d39a76e7Sxw #define M_MAX_RX_SIZE 0xffff 997*d39a76e7Sxw #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE) 998*d39a76e7Sxw #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE) 999*d39a76e7Sxw 1000*d39a76e7Sxw #define A_TP_PARA_REG3 0x36c 1001*d39a76e7Sxw 1002*d39a76e7Sxw #define S_RX_COALESCING_PSH_DELIVER 0 1003*d39a76e7Sxw #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER) 1004*d39a76e7Sxw #define F_RX_COALESCING_PSH_DELIVER V_RX_COALESCING_PSH_DELIVER(1U) 1005*d39a76e7Sxw 1006*d39a76e7Sxw #define S_RX_COALESCING_ENABLE 1 1007*d39a76e7Sxw #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE) 1008*d39a76e7Sxw #define F_RX_COALESCING_ENABLE V_RX_COALESCING_ENABLE(1U) 1009*d39a76e7Sxw 1010*d39a76e7Sxw #define S_TAHOE_ENABLE 2 1011*d39a76e7Sxw #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE) 1012*d39a76e7Sxw #define F_TAHOE_ENABLE V_TAHOE_ENABLE(1U) 1013*d39a76e7Sxw 1014*d39a76e7Sxw #define S_MAX_REORDER_FRAGMENTS 12 1015*d39a76e7Sxw #define M_MAX_REORDER_FRAGMENTS 0x7 1016*d39a76e7Sxw #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS) 1017*d39a76e7Sxw #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS) 1018*d39a76e7Sxw 1019*d39a76e7Sxw #define A_TP_TIMER_RESOLUTION 0x390 1020*d39a76e7Sxw 1021*d39a76e7Sxw #define S_DELAYED_ACK_TIMER_RESOLUTION 0 1022*d39a76e7Sxw #define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f 1023*d39a76e7Sxw #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION) 1024*d39a76e7Sxw #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION) 1025*d39a76e7Sxw 1026*d39a76e7Sxw #define S_GENERIC_TIMER_RESOLUTION 16 1027*d39a76e7Sxw #define M_GENERIC_TIMER_RESOLUTION 0x3f 1028*d39a76e7Sxw #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION) 1029*d39a76e7Sxw #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION) 1030*d39a76e7Sxw 1031*d39a76e7Sxw #define A_TP_2MSL 0x394 1032*d39a76e7Sxw 1033*d39a76e7Sxw #define S_2MSL 0 1034*d39a76e7Sxw #define M_2MSL 0x3fffffff 1035*d39a76e7Sxw #define V_2MSL(x) ((x) << S_2MSL) 1036*d39a76e7Sxw #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL) 1037*d39a76e7Sxw 1038*d39a76e7Sxw #define A_TP_RXT_MIN 0x398 1039*d39a76e7Sxw 1040*d39a76e7Sxw #define S_RETRANSMIT_TIMER_MIN 0 1041*d39a76e7Sxw #define M_RETRANSMIT_TIMER_MIN 0xffff 1042*d39a76e7Sxw #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN) 1043*d39a76e7Sxw #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN) 1044*d39a76e7Sxw 1045*d39a76e7Sxw #define A_TP_RXT_MAX 0x39c 1046*d39a76e7Sxw 1047*d39a76e7Sxw #define S_RETRANSMIT_TIMER_MAX 0 1048*d39a76e7Sxw #define M_RETRANSMIT_TIMER_MAX 0x3fffffff 1049*d39a76e7Sxw #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX) 1050*d39a76e7Sxw #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX) 1051*d39a76e7Sxw 1052*d39a76e7Sxw #define A_TP_PERS_MIN 0x3a0 1053*d39a76e7Sxw 1054*d39a76e7Sxw #define S_PERSIST_TIMER_MIN 0 1055*d39a76e7Sxw #define M_PERSIST_TIMER_MIN 0xffff 1056*d39a76e7Sxw #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN) 1057*d39a76e7Sxw #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN) 1058*d39a76e7Sxw 1059*d39a76e7Sxw #define A_TP_PERS_MAX 0x3a4 1060*d39a76e7Sxw 1061*d39a76e7Sxw #define S_PERSIST_TIMER_MAX 0 1062*d39a76e7Sxw #define M_PERSIST_TIMER_MAX 0x3fffffff 1063*d39a76e7Sxw #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX) 1064*d39a76e7Sxw #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX) 1065*d39a76e7Sxw 1066*d39a76e7Sxw #define A_TP_KEEP_IDLE 0x3ac 1067*d39a76e7Sxw 1068*d39a76e7Sxw #define S_KEEP_ALIVE_IDLE_TIME 0 1069*d39a76e7Sxw #define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff 1070*d39a76e7Sxw #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME) 1071*d39a76e7Sxw #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME) 1072*d39a76e7Sxw 1073*d39a76e7Sxw #define A_TP_KEEP_INTVL 0x3b0 1074*d39a76e7Sxw 1075*d39a76e7Sxw #define S_KEEP_ALIVE_INTERVAL_TIME 0 1076*d39a76e7Sxw #define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff 1077*d39a76e7Sxw #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME) 1078*d39a76e7Sxw #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME) 1079*d39a76e7Sxw 1080*d39a76e7Sxw #define A_TP_INIT_SRTT 0x3b4 1081*d39a76e7Sxw 1082*d39a76e7Sxw #define S_INITIAL_SRTT 0 1083*d39a76e7Sxw #define M_INITIAL_SRTT 0xffff 1084*d39a76e7Sxw #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT) 1085*d39a76e7Sxw #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT) 1086*d39a76e7Sxw 1087*d39a76e7Sxw #define A_TP_DACK_TIME 0x3b8 1088*d39a76e7Sxw 1089*d39a76e7Sxw #define S_DELAYED_ACK_TIME 0 1090*d39a76e7Sxw #define M_DELAYED_ACK_TIME 0x7ff 1091*d39a76e7Sxw #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME) 1092*d39a76e7Sxw #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME) 1093*d39a76e7Sxw 1094*d39a76e7Sxw #define A_TP_FINWAIT2_TIME 0x3bc 1095*d39a76e7Sxw 1096*d39a76e7Sxw #define S_FINWAIT2_TIME 0 1097*d39a76e7Sxw #define M_FINWAIT2_TIME 0x3fffffff 1098*d39a76e7Sxw #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME) 1099*d39a76e7Sxw #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME) 1100*d39a76e7Sxw 1101*d39a76e7Sxw #define A_TP_FAST_FINWAIT2_TIME 0x3c0 1102*d39a76e7Sxw 1103*d39a76e7Sxw #define S_FAST_FINWAIT2_TIME 0 1104*d39a76e7Sxw #define M_FAST_FINWAIT2_TIME 0x3fffffff 1105*d39a76e7Sxw #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME) 1106*d39a76e7Sxw #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME) 1107*d39a76e7Sxw 1108*d39a76e7Sxw #define A_TP_SHIFT_CNT 0x3c4 1109*d39a76e7Sxw 1110*d39a76e7Sxw #define S_KEEPALIVE_MAX 0 1111*d39a76e7Sxw #define M_KEEPALIVE_MAX 0xff 1112*d39a76e7Sxw #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX) 1113*d39a76e7Sxw #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX) 1114*d39a76e7Sxw 1115*d39a76e7Sxw #define S_WINDOWPROBE_MAX 8 1116*d39a76e7Sxw #define M_WINDOWPROBE_MAX 0xff 1117*d39a76e7Sxw #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX) 1118*d39a76e7Sxw #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX) 1119*d39a76e7Sxw 1120*d39a76e7Sxw #define S_RETRANSMISSION_MAX 16 1121*d39a76e7Sxw #define M_RETRANSMISSION_MAX 0xff 1122*d39a76e7Sxw #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX) 1123*d39a76e7Sxw #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX) 1124*d39a76e7Sxw 1125*d39a76e7Sxw #define S_SYN_MAX 24 1126*d39a76e7Sxw #define M_SYN_MAX 0xff 1127*d39a76e7Sxw #define V_SYN_MAX(x) ((x) << S_SYN_MAX) 1128*d39a76e7Sxw #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX) 1129*d39a76e7Sxw 1130*d39a76e7Sxw #define A_TP_QOS_REG0 0x3e0 1131*d39a76e7Sxw 1132*d39a76e7Sxw #define S_L3_VALUE 0 1133*d39a76e7Sxw #define M_L3_VALUE 0x3f 1134*d39a76e7Sxw #define V_L3_VALUE(x) ((x) << S_L3_VALUE) 1135*d39a76e7Sxw #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE) 1136*d39a76e7Sxw 1137*d39a76e7Sxw #define A_TP_QOS_REG1 0x3e4 1138*d39a76e7Sxw #define A_TP_QOS_REG2 0x3e8 1139*d39a76e7Sxw #define A_TP_QOS_REG3 0x3ec 1140*d39a76e7Sxw #define A_TP_QOS_REG4 0x3f0 1141*d39a76e7Sxw #define A_TP_QOS_REG5 0x3f4 1142*d39a76e7Sxw #define A_TP_QOS_REG6 0x3f8 1143*d39a76e7Sxw #define A_TP_QOS_REG7 0x3fc 1144*d39a76e7Sxw #define A_TP_MTU_REG0 0x404 1145*d39a76e7Sxw #define A_TP_MTU_REG1 0x408 1146*d39a76e7Sxw #define A_TP_MTU_REG2 0x40c 1147*d39a76e7Sxw #define A_TP_MTU_REG3 0x410 1148*d39a76e7Sxw #define A_TP_MTU_REG4 0x414 1149*d39a76e7Sxw #define A_TP_MTU_REG5 0x418 1150*d39a76e7Sxw #define A_TP_MTU_REG6 0x41c 1151*d39a76e7Sxw #define A_TP_MTU_REG7 0x420 1152*d39a76e7Sxw #define A_TP_RESET 0x44c 1153*d39a76e7Sxw 1154*d39a76e7Sxw #define S_TP_RESET 0 1155*d39a76e7Sxw #define V_TP_RESET(x) ((x) << S_TP_RESET) 1156*d39a76e7Sxw #define F_TP_RESET V_TP_RESET(1U) 1157*d39a76e7Sxw 1158*d39a76e7Sxw #define S_CM_MEMMGR_INIT 1 1159*d39a76e7Sxw #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT) 1160*d39a76e7Sxw #define F_CM_MEMMGR_INIT V_CM_MEMMGR_INIT(1U) 1161*d39a76e7Sxw 1162*d39a76e7Sxw #define A_TP_MIB_INDEX 0x450 1163*d39a76e7Sxw #define A_TP_MIB_DATA 0x454 1164*d39a76e7Sxw #define A_TP_SYNC_TIME_HI 0x458 1165*d39a76e7Sxw #define A_TP_SYNC_TIME_LO 0x45c 1166*d39a76e7Sxw #define A_TP_CM_MM_RX_FLST_BASE 0x460 1167*d39a76e7Sxw 1168*d39a76e7Sxw #define S_CM_MEMMGR_RX_FREE_LIST_BASE 0 1169*d39a76e7Sxw #define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff 1170*d39a76e7Sxw #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE) 1171*d39a76e7Sxw #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE) 1172*d39a76e7Sxw 1173*d39a76e7Sxw #define A_TP_CM_MM_TX_FLST_BASE 0x464 1174*d39a76e7Sxw 1175*d39a76e7Sxw #define S_CM_MEMMGR_TX_FREE_LIST_BASE 0 1176*d39a76e7Sxw #define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff 1177*d39a76e7Sxw #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE) 1178*d39a76e7Sxw #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE) 1179*d39a76e7Sxw 1180*d39a76e7Sxw #define A_TP_CM_MM_P_FLST_BASE 0x468 1181*d39a76e7Sxw 1182*d39a76e7Sxw #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0 1183*d39a76e7Sxw #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff 1184*d39a76e7Sxw #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) 1185*d39a76e7Sxw #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) 1186*d39a76e7Sxw 1187*d39a76e7Sxw #define A_TP_CM_MM_MAX_P 0x46c 1188*d39a76e7Sxw 1189*d39a76e7Sxw #define S_CM_MEMMGR_MAX_PSTRUCT 0 1190*d39a76e7Sxw #define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff 1191*d39a76e7Sxw #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT) 1192*d39a76e7Sxw #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT) 1193*d39a76e7Sxw 1194*d39a76e7Sxw #define A_TP_INT_ENABLE 0x470 1195*d39a76e7Sxw 1196*d39a76e7Sxw #define S_TX_FREE_LIST_EMPTY 0 1197*d39a76e7Sxw #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY) 1198*d39a76e7Sxw #define F_TX_FREE_LIST_EMPTY V_TX_FREE_LIST_EMPTY(1U) 1199*d39a76e7Sxw 1200*d39a76e7Sxw #define S_RX_FREE_LIST_EMPTY 1 1201*d39a76e7Sxw #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY) 1202*d39a76e7Sxw #define F_RX_FREE_LIST_EMPTY V_RX_FREE_LIST_EMPTY(1U) 1203*d39a76e7Sxw 1204*d39a76e7Sxw #define A_TP_INT_CAUSE 0x474 1205*d39a76e7Sxw #define A_TP_TIMER_SEPARATOR 0x4a4 1206*d39a76e7Sxw 1207*d39a76e7Sxw #define S_DISABLE_PAST_TIMER_INSERTION 0 1208*d39a76e7Sxw #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION) 1209*d39a76e7Sxw #define F_DISABLE_PAST_TIMER_INSERTION V_DISABLE_PAST_TIMER_INSERTION(1U) 1210*d39a76e7Sxw 1211*d39a76e7Sxw #define S_MODULATION_TIMER_SEPARATOR 1 1212*d39a76e7Sxw #define M_MODULATION_TIMER_SEPARATOR 0x7fff 1213*d39a76e7Sxw #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR) 1214*d39a76e7Sxw #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR) 1215*d39a76e7Sxw 1216*d39a76e7Sxw #define S_GLOBAL_TIMER_SEPARATOR 16 1217*d39a76e7Sxw #define M_GLOBAL_TIMER_SEPARATOR 0xffff 1218*d39a76e7Sxw #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR) 1219*d39a76e7Sxw #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR) 1220*d39a76e7Sxw 1221*d39a76e7Sxw #define A_TP_CM_FC_MODE 0x4b0 1222*d39a76e7Sxw #define A_TP_PC_CONGESTION_CNTL 0x4b4 1223*d39a76e7Sxw #define A_TP_TX_DROP_CONFIG 0x4b8 1224*d39a76e7Sxw 1225*d39a76e7Sxw #define S_ENABLE_TX_DROP 31 1226*d39a76e7Sxw #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP) 1227*d39a76e7Sxw #define F_ENABLE_TX_DROP V_ENABLE_TX_DROP(1U) 1228*d39a76e7Sxw 1229*d39a76e7Sxw #define S_ENABLE_TX_ERROR 30 1230*d39a76e7Sxw #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR) 1231*d39a76e7Sxw #define F_ENABLE_TX_ERROR V_ENABLE_TX_ERROR(1U) 1232*d39a76e7Sxw 1233*d39a76e7Sxw #define S_DROP_TICKS_CNT 4 1234*d39a76e7Sxw #define M_DROP_TICKS_CNT 0x3ffffff 1235*d39a76e7Sxw #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT) 1236*d39a76e7Sxw #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT) 1237*d39a76e7Sxw 1238*d39a76e7Sxw #define S_NUM_PKTS_DROPPED 0 1239*d39a76e7Sxw #define M_NUM_PKTS_DROPPED 0xf 1240*d39a76e7Sxw #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED) 1241*d39a76e7Sxw #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED) 1242*d39a76e7Sxw 1243*d39a76e7Sxw #define A_TP_TX_DROP_COUNT 0x4bc 1244*d39a76e7Sxw 1245*d39a76e7Sxw /* RAT registers */ 1246*d39a76e7Sxw #define A_RAT_ROUTE_CONTROL 0x580 1247*d39a76e7Sxw 1248*d39a76e7Sxw #define S_USE_ROUTE_TABLE 0 1249*d39a76e7Sxw #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE) 1250*d39a76e7Sxw #define F_USE_ROUTE_TABLE V_USE_ROUTE_TABLE(1U) 1251*d39a76e7Sxw 1252*d39a76e7Sxw #define S_ENABLE_CSPI 1 1253*d39a76e7Sxw #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI) 1254*d39a76e7Sxw #define F_ENABLE_CSPI V_ENABLE_CSPI(1U) 1255*d39a76e7Sxw 1256*d39a76e7Sxw #define S_ENABLE_PCIX 2 1257*d39a76e7Sxw #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX) 1258*d39a76e7Sxw #define F_ENABLE_PCIX V_ENABLE_PCIX(1U) 1259*d39a76e7Sxw 1260*d39a76e7Sxw #define A_RAT_ROUTE_TABLE_INDEX 0x584 1261*d39a76e7Sxw 1262*d39a76e7Sxw #define S_ROUTE_TABLE_INDEX 0 1263*d39a76e7Sxw #define M_ROUTE_TABLE_INDEX 0xf 1264*d39a76e7Sxw #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX) 1265*d39a76e7Sxw #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX) 1266*d39a76e7Sxw 1267*d39a76e7Sxw #define A_RAT_ROUTE_TABLE_DATA 0x588 1268*d39a76e7Sxw #define A_RAT_NO_ROUTE 0x58c 1269*d39a76e7Sxw 1270*d39a76e7Sxw #define S_CPL_OPCODE 0 1271*d39a76e7Sxw #define M_CPL_OPCODE 0xff 1272*d39a76e7Sxw #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 1273*d39a76e7Sxw #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE) 1274*d39a76e7Sxw 1275*d39a76e7Sxw #define A_RAT_INTR_ENABLE 0x590 1276*d39a76e7Sxw 1277*d39a76e7Sxw #define S_ZEROROUTEERROR 0 1278*d39a76e7Sxw #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR) 1279*d39a76e7Sxw #define F_ZEROROUTEERROR V_ZEROROUTEERROR(1U) 1280*d39a76e7Sxw 1281*d39a76e7Sxw #define S_CSPIFRAMINGERROR 1 1282*d39a76e7Sxw #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR) 1283*d39a76e7Sxw #define F_CSPIFRAMINGERROR V_CSPIFRAMINGERROR(1U) 1284*d39a76e7Sxw 1285*d39a76e7Sxw #define S_SGEFRAMINGERROR 2 1286*d39a76e7Sxw #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR) 1287*d39a76e7Sxw #define F_SGEFRAMINGERROR V_SGEFRAMINGERROR(1U) 1288*d39a76e7Sxw 1289*d39a76e7Sxw #define S_TPFRAMINGERROR 3 1290*d39a76e7Sxw #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR) 1291*d39a76e7Sxw #define F_TPFRAMINGERROR V_TPFRAMINGERROR(1U) 1292*d39a76e7Sxw 1293*d39a76e7Sxw #define A_RAT_INTR_CAUSE 0x594 1294*d39a76e7Sxw 1295*d39a76e7Sxw /* CSPI registers */ 1296*d39a76e7Sxw #define A_CSPI_RX_AE_WM 0x810 1297*d39a76e7Sxw #define A_CSPI_RX_AF_WM 0x814 1298*d39a76e7Sxw #define A_CSPI_CALENDAR_LEN 0x818 1299*d39a76e7Sxw 1300*d39a76e7Sxw #define S_CALENDARLENGTH 0 1301*d39a76e7Sxw #define M_CALENDARLENGTH 0xffff 1302*d39a76e7Sxw #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH) 1303*d39a76e7Sxw #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH) 1304*d39a76e7Sxw 1305*d39a76e7Sxw #define A_CSPI_FIFO_STATUS_ENABLE 0x820 1306*d39a76e7Sxw 1307*d39a76e7Sxw #define S_FIFOSTATUSENABLE 0 1308*d39a76e7Sxw #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE) 1309*d39a76e7Sxw #define F_FIFOSTATUSENABLE V_FIFOSTATUSENABLE(1U) 1310*d39a76e7Sxw 1311*d39a76e7Sxw #define A_CSPI_MAXBURST1_MAXBURST2 0x828 1312*d39a76e7Sxw 1313*d39a76e7Sxw #define S_MAXBURST1 0 1314*d39a76e7Sxw #define M_MAXBURST1 0xffff 1315*d39a76e7Sxw #define V_MAXBURST1(x) ((x) << S_MAXBURST1) 1316*d39a76e7Sxw #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1) 1317*d39a76e7Sxw 1318*d39a76e7Sxw #define S_MAXBURST2 16 1319*d39a76e7Sxw #define M_MAXBURST2 0xffff 1320*d39a76e7Sxw #define V_MAXBURST2(x) ((x) << S_MAXBURST2) 1321*d39a76e7Sxw #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2) 1322*d39a76e7Sxw 1323*d39a76e7Sxw #define A_CSPI_TRAIN 0x82c 1324*d39a76e7Sxw 1325*d39a76e7Sxw #define S_CSPI_TRAIN_ALPHA 0 1326*d39a76e7Sxw #define M_CSPI_TRAIN_ALPHA 0xffff 1327*d39a76e7Sxw #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA) 1328*d39a76e7Sxw #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA) 1329*d39a76e7Sxw 1330*d39a76e7Sxw #define S_CSPI_TRAIN_DATA_MAXT 16 1331*d39a76e7Sxw #define M_CSPI_TRAIN_DATA_MAXT 0xffff 1332*d39a76e7Sxw #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT) 1333*d39a76e7Sxw #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT) 1334*d39a76e7Sxw 1335*d39a76e7Sxw #define A_CSPI_INTR_STATUS 0x848 1336*d39a76e7Sxw 1337*d39a76e7Sxw #define S_DIP4ERR 0 1338*d39a76e7Sxw #define V_DIP4ERR(x) ((x) << S_DIP4ERR) 1339*d39a76e7Sxw #define F_DIP4ERR V_DIP4ERR(1U) 1340*d39a76e7Sxw 1341*d39a76e7Sxw #define S_RXDROP 1 1342*d39a76e7Sxw #define V_RXDROP(x) ((x) << S_RXDROP) 1343*d39a76e7Sxw #define F_RXDROP V_RXDROP(1U) 1344*d39a76e7Sxw 1345*d39a76e7Sxw #define S_TXDROP 2 1346*d39a76e7Sxw #define V_TXDROP(x) ((x) << S_TXDROP) 1347*d39a76e7Sxw #define F_TXDROP V_TXDROP(1U) 1348*d39a76e7Sxw 1349*d39a76e7Sxw #define S_RXOVERFLOW 3 1350*d39a76e7Sxw #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW) 1351*d39a76e7Sxw #define F_RXOVERFLOW V_RXOVERFLOW(1U) 1352*d39a76e7Sxw 1353*d39a76e7Sxw #define S_RAMPARITYERR 4 1354*d39a76e7Sxw #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR) 1355*d39a76e7Sxw #define F_RAMPARITYERR V_RAMPARITYERR(1U) 1356*d39a76e7Sxw 1357*d39a76e7Sxw #define A_CSPI_INTR_ENABLE 0x84c 1358*d39a76e7Sxw 1359*d39a76e7Sxw /* ESPI registers */ 1360*d39a76e7Sxw #define A_ESPI_SCH_TOKEN0 0x880 1361*d39a76e7Sxw 1362*d39a76e7Sxw #define S_SCHTOKEN0 0 1363*d39a76e7Sxw #define M_SCHTOKEN0 0xffff 1364*d39a76e7Sxw #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0) 1365*d39a76e7Sxw #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0) 1366*d39a76e7Sxw 1367*d39a76e7Sxw #define A_ESPI_SCH_TOKEN1 0x884 1368*d39a76e7Sxw 1369*d39a76e7Sxw #define S_SCHTOKEN1 0 1370*d39a76e7Sxw #define M_SCHTOKEN1 0xffff 1371*d39a76e7Sxw #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1) 1372*d39a76e7Sxw #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1) 1373*d39a76e7Sxw 1374*d39a76e7Sxw #define A_ESPI_SCH_TOKEN2 0x888 1375*d39a76e7Sxw 1376*d39a76e7Sxw #define S_SCHTOKEN2 0 1377*d39a76e7Sxw #define M_SCHTOKEN2 0xffff 1378*d39a76e7Sxw #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2) 1379*d39a76e7Sxw #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2) 1380*d39a76e7Sxw 1381*d39a76e7Sxw #define A_ESPI_SCH_TOKEN3 0x88c 1382*d39a76e7Sxw 1383*d39a76e7Sxw #define S_SCHTOKEN3 0 1384*d39a76e7Sxw #define M_SCHTOKEN3 0xffff 1385*d39a76e7Sxw #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3) 1386*d39a76e7Sxw #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3) 1387*d39a76e7Sxw 1388*d39a76e7Sxw #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890 1389*d39a76e7Sxw 1390*d39a76e7Sxw #define S_ALMOSTEMPTY 0 1391*d39a76e7Sxw #define M_ALMOSTEMPTY 0xffff 1392*d39a76e7Sxw #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY) 1393*d39a76e7Sxw #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY) 1394*d39a76e7Sxw 1395*d39a76e7Sxw #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894 1396*d39a76e7Sxw 1397*d39a76e7Sxw #define S_ALMOSTFULL 0 1398*d39a76e7Sxw #define M_ALMOSTFULL 0xffff 1399*d39a76e7Sxw #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL) 1400*d39a76e7Sxw #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL) 1401*d39a76e7Sxw 1402*d39a76e7Sxw #define A_ESPI_CALENDAR_LENGTH 0x898 1403*d39a76e7Sxw #define A_PORT_CONFIG 0x89c 1404*d39a76e7Sxw 1405*d39a76e7Sxw #define S_RX_NPORTS 0 1406*d39a76e7Sxw #define M_RX_NPORTS 0xff 1407*d39a76e7Sxw #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS) 1408*d39a76e7Sxw #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS) 1409*d39a76e7Sxw 1410*d39a76e7Sxw #define S_TX_NPORTS 8 1411*d39a76e7Sxw #define M_TX_NPORTS 0xff 1412*d39a76e7Sxw #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS) 1413*d39a76e7Sxw #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS) 1414*d39a76e7Sxw 1415*d39a76e7Sxw #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0 1416*d39a76e7Sxw 1417*d39a76e7Sxw #define S_RXSTATUSENABLE 0 1418*d39a76e7Sxw #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE) 1419*d39a76e7Sxw #define F_RXSTATUSENABLE V_RXSTATUSENABLE(1U) 1420*d39a76e7Sxw 1421*d39a76e7Sxw #define S_TXDROPENABLE 1 1422*d39a76e7Sxw #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE) 1423*d39a76e7Sxw #define F_TXDROPENABLE V_TXDROPENABLE(1U) 1424*d39a76e7Sxw 1425*d39a76e7Sxw #define S_RXENDIANMODE 2 1426*d39a76e7Sxw #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE) 1427*d39a76e7Sxw #define F_RXENDIANMODE V_RXENDIANMODE(1U) 1428*d39a76e7Sxw 1429*d39a76e7Sxw #define S_TXENDIANMODE 3 1430*d39a76e7Sxw #define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE) 1431*d39a76e7Sxw #define F_TXENDIANMODE V_TXENDIANMODE(1U) 1432*d39a76e7Sxw 1433*d39a76e7Sxw #define S_INTEL1010MODE 4 1434*d39a76e7Sxw #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE) 1435*d39a76e7Sxw #define F_INTEL1010MODE V_INTEL1010MODE(1U) 1436*d39a76e7Sxw 1437*d39a76e7Sxw #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8 1438*d39a76e7Sxw #define A_ESPI_TRAIN 0x8ac 1439*d39a76e7Sxw 1440*d39a76e7Sxw #define S_MAXTRAINALPHA 0 1441*d39a76e7Sxw #define M_MAXTRAINALPHA 0xffff 1442*d39a76e7Sxw #define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA) 1443*d39a76e7Sxw #define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA) 1444*d39a76e7Sxw 1445*d39a76e7Sxw #define S_MAXTRAINDATA 16 1446*d39a76e7Sxw #define M_MAXTRAINDATA 0xffff 1447*d39a76e7Sxw #define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA) 1448*d39a76e7Sxw #define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA) 1449*d39a76e7Sxw 1450*d39a76e7Sxw #define A_RAM_STATUS 0x8b0 1451*d39a76e7Sxw 1452*d39a76e7Sxw #define S_RXFIFOPARITYERROR 0 1453*d39a76e7Sxw #define M_RXFIFOPARITYERROR 0x3ff 1454*d39a76e7Sxw #define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR) 1455*d39a76e7Sxw #define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR) 1456*d39a76e7Sxw 1457*d39a76e7Sxw #define S_TXFIFOPARITYERROR 10 1458*d39a76e7Sxw #define M_TXFIFOPARITYERROR 0x3ff 1459*d39a76e7Sxw #define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR) 1460*d39a76e7Sxw #define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR) 1461*d39a76e7Sxw 1462*d39a76e7Sxw #define S_RXFIFOOVERFLOW 20 1463*d39a76e7Sxw #define M_RXFIFOOVERFLOW 0x3ff 1464*d39a76e7Sxw #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW) 1465*d39a76e7Sxw #define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW) 1466*d39a76e7Sxw 1467*d39a76e7Sxw #define A_TX_DROP_COUNT0 0x8b4 1468*d39a76e7Sxw 1469*d39a76e7Sxw #define S_TXPORT0DROPCNT 0 1470*d39a76e7Sxw #define M_TXPORT0DROPCNT 0xffff 1471*d39a76e7Sxw #define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT) 1472*d39a76e7Sxw #define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT) 1473*d39a76e7Sxw 1474*d39a76e7Sxw #define S_TXPORT1DROPCNT 16 1475*d39a76e7Sxw #define M_TXPORT1DROPCNT 0xffff 1476*d39a76e7Sxw #define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT) 1477*d39a76e7Sxw #define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT) 1478*d39a76e7Sxw 1479*d39a76e7Sxw #define A_TX_DROP_COUNT1 0x8b8 1480*d39a76e7Sxw 1481*d39a76e7Sxw #define S_TXPORT2DROPCNT 0 1482*d39a76e7Sxw #define M_TXPORT2DROPCNT 0xffff 1483*d39a76e7Sxw #define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT) 1484*d39a76e7Sxw #define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT) 1485*d39a76e7Sxw 1486*d39a76e7Sxw #define S_TXPORT3DROPCNT 16 1487*d39a76e7Sxw #define M_TXPORT3DROPCNT 0xffff 1488*d39a76e7Sxw #define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT) 1489*d39a76e7Sxw #define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT) 1490*d39a76e7Sxw 1491*d39a76e7Sxw #define A_RX_DROP_COUNT0 0x8bc 1492*d39a76e7Sxw 1493*d39a76e7Sxw #define S_RXPORT0DROPCNT 0 1494*d39a76e7Sxw #define M_RXPORT0DROPCNT 0xffff 1495*d39a76e7Sxw #define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT) 1496*d39a76e7Sxw #define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT) 1497*d39a76e7Sxw 1498*d39a76e7Sxw #define S_RXPORT1DROPCNT 16 1499*d39a76e7Sxw #define M_RXPORT1DROPCNT 0xffff 1500*d39a76e7Sxw #define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT) 1501*d39a76e7Sxw #define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT) 1502*d39a76e7Sxw 1503*d39a76e7Sxw #define A_RX_DROP_COUNT1 0x8c0 1504*d39a76e7Sxw 1505*d39a76e7Sxw #define S_RXPORT2DROPCNT 0 1506*d39a76e7Sxw #define M_RXPORT2DROPCNT 0xffff 1507*d39a76e7Sxw #define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT) 1508*d39a76e7Sxw #define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT) 1509*d39a76e7Sxw 1510*d39a76e7Sxw #define S_RXPORT3DROPCNT 16 1511*d39a76e7Sxw #define M_RXPORT3DROPCNT 0xffff 1512*d39a76e7Sxw #define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT) 1513*d39a76e7Sxw #define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT) 1514*d39a76e7Sxw 1515*d39a76e7Sxw #define A_DIP4_ERROR_COUNT 0x8c4 1516*d39a76e7Sxw 1517*d39a76e7Sxw #define S_DIP4ERRORCNT 0 1518*d39a76e7Sxw #define M_DIP4ERRORCNT 0xfff 1519*d39a76e7Sxw #define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT) 1520*d39a76e7Sxw #define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT) 1521*d39a76e7Sxw 1522*d39a76e7Sxw #define S_DIP4ERRORCNTSHADOW 12 1523*d39a76e7Sxw #define M_DIP4ERRORCNTSHADOW 0xfff 1524*d39a76e7Sxw #define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW) 1525*d39a76e7Sxw #define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW) 1526*d39a76e7Sxw 1527*d39a76e7Sxw #define S_TRICN_RX_TRAIN_ERR 24 1528*d39a76e7Sxw #define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR) 1529*d39a76e7Sxw #define F_TRICN_RX_TRAIN_ERR V_TRICN_RX_TRAIN_ERR(1U) 1530*d39a76e7Sxw 1531*d39a76e7Sxw #define S_TRICN_RX_TRAINING 25 1532*d39a76e7Sxw #define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING) 1533*d39a76e7Sxw #define F_TRICN_RX_TRAINING V_TRICN_RX_TRAINING(1U) 1534*d39a76e7Sxw 1535*d39a76e7Sxw #define S_TRICN_RX_TRAIN_OK 26 1536*d39a76e7Sxw #define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK) 1537*d39a76e7Sxw #define F_TRICN_RX_TRAIN_OK V_TRICN_RX_TRAIN_OK(1U) 1538*d39a76e7Sxw 1539*d39a76e7Sxw #define A_ESPI_INTR_STATUS 0x8c8 1540*d39a76e7Sxw 1541*d39a76e7Sxw #define S_DIP2PARITYERR 5 1542*d39a76e7Sxw #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR) 1543*d39a76e7Sxw #define F_DIP2PARITYERR V_DIP2PARITYERR(1U) 1544*d39a76e7Sxw 1545*d39a76e7Sxw #define A_ESPI_INTR_ENABLE 0x8cc 1546*d39a76e7Sxw #define A_RX_DROP_THRESHOLD 0x8d0 1547*d39a76e7Sxw #define A_ESPI_RX_RESET 0x8ec 1548*d39a76e7Sxw 1549*d39a76e7Sxw #define S_ESPI_RX_LNK_RST 0 1550*d39a76e7Sxw #define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST) 1551*d39a76e7Sxw #define F_ESPI_RX_LNK_RST V_ESPI_RX_LNK_RST(1U) 1552*d39a76e7Sxw 1553*d39a76e7Sxw #define S_ESPI_RX_CORE_RST 1 1554*d39a76e7Sxw #define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST) 1555*d39a76e7Sxw #define F_ESPI_RX_CORE_RST V_ESPI_RX_CORE_RST(1U) 1556*d39a76e7Sxw 1557*d39a76e7Sxw #define S_RX_CLK_STATUS 2 1558*d39a76e7Sxw #define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS) 1559*d39a76e7Sxw #define F_RX_CLK_STATUS V_RX_CLK_STATUS(1U) 1560*d39a76e7Sxw 1561*d39a76e7Sxw #define A_ESPI_MISC_CONTROL 0x8f0 1562*d39a76e7Sxw 1563*d39a76e7Sxw #define S_OUT_OF_SYNC_COUNT 0 1564*d39a76e7Sxw #define M_OUT_OF_SYNC_COUNT 0xf 1565*d39a76e7Sxw #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT) 1566*d39a76e7Sxw #define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT) 1567*d39a76e7Sxw 1568*d39a76e7Sxw #define S_DIP2_COUNT_MODE_ENABLE 4 1569*d39a76e7Sxw #define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE) 1570*d39a76e7Sxw #define F_DIP2_COUNT_MODE_ENABLE V_DIP2_COUNT_MODE_ENABLE(1U) 1571*d39a76e7Sxw 1572*d39a76e7Sxw #define S_DIP2_PARITY_ERR_THRES 5 1573*d39a76e7Sxw #define M_DIP2_PARITY_ERR_THRES 0xf 1574*d39a76e7Sxw #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES) 1575*d39a76e7Sxw #define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES) 1576*d39a76e7Sxw 1577*d39a76e7Sxw #define S_DIP4_THRES 9 1578*d39a76e7Sxw #define M_DIP4_THRES 0xfff 1579*d39a76e7Sxw #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES) 1580*d39a76e7Sxw #define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES) 1581*d39a76e7Sxw 1582*d39a76e7Sxw #define S_DIP4_THRES_ENABLE 21 1583*d39a76e7Sxw #define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE) 1584*d39a76e7Sxw #define F_DIP4_THRES_ENABLE V_DIP4_THRES_ENABLE(1U) 1585*d39a76e7Sxw 1586*d39a76e7Sxw #define S_FORCE_DISABLE_STATUS 22 1587*d39a76e7Sxw #define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS) 1588*d39a76e7Sxw #define F_FORCE_DISABLE_STATUS V_FORCE_DISABLE_STATUS(1U) 1589*d39a76e7Sxw 1590*d39a76e7Sxw #define S_DYNAMIC_DESKEW 23 1591*d39a76e7Sxw #define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW) 1592*d39a76e7Sxw #define F_DYNAMIC_DESKEW V_DYNAMIC_DESKEW(1U) 1593*d39a76e7Sxw 1594*d39a76e7Sxw #define S_MONITORED_PORT_NUM 25 1595*d39a76e7Sxw #define M_MONITORED_PORT_NUM 0x3 1596*d39a76e7Sxw #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM) 1597*d39a76e7Sxw #define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM) 1598*d39a76e7Sxw 1599*d39a76e7Sxw #define S_MONITORED_DIRECTION 27 1600*d39a76e7Sxw #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION) 1601*d39a76e7Sxw #define F_MONITORED_DIRECTION V_MONITORED_DIRECTION(1U) 1602*d39a76e7Sxw 1603*d39a76e7Sxw #define S_MONITORED_INTERFACE 28 1604*d39a76e7Sxw #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE) 1605*d39a76e7Sxw #define F_MONITORED_INTERFACE V_MONITORED_INTERFACE(1U) 1606*d39a76e7Sxw 1607*d39a76e7Sxw #define A_ESPI_DIP2_ERR_COUNT 0x8f4 1608*d39a76e7Sxw 1609*d39a76e7Sxw #define S_DIP2_ERR_CNT 0 1610*d39a76e7Sxw #define M_DIP2_ERR_CNT 0xf 1611*d39a76e7Sxw #define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT) 1612*d39a76e7Sxw #define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT) 1613*d39a76e7Sxw 1614*d39a76e7Sxw #define A_ESPI_CMD_ADDR 0x8f8 1615*d39a76e7Sxw 1616*d39a76e7Sxw #define S_WRITE_DATA 0 1617*d39a76e7Sxw #define M_WRITE_DATA 0xff 1618*d39a76e7Sxw #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA) 1619*d39a76e7Sxw #define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA) 1620*d39a76e7Sxw 1621*d39a76e7Sxw #define S_REGISTER_OFFSET 8 1622*d39a76e7Sxw #define M_REGISTER_OFFSET 0xf 1623*d39a76e7Sxw #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET) 1624*d39a76e7Sxw #define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET) 1625*d39a76e7Sxw 1626*d39a76e7Sxw #define S_CHANNEL_ADDR 12 1627*d39a76e7Sxw #define M_CHANNEL_ADDR 0xf 1628*d39a76e7Sxw #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR) 1629*d39a76e7Sxw #define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR) 1630*d39a76e7Sxw 1631*d39a76e7Sxw #define S_MODULE_ADDR 16 1632*d39a76e7Sxw #define M_MODULE_ADDR 0x3 1633*d39a76e7Sxw #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR) 1634*d39a76e7Sxw #define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR) 1635*d39a76e7Sxw 1636*d39a76e7Sxw #define S_BUNDLE_ADDR 20 1637*d39a76e7Sxw #define M_BUNDLE_ADDR 0x3 1638*d39a76e7Sxw #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR) 1639*d39a76e7Sxw #define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR) 1640*d39a76e7Sxw 1641*d39a76e7Sxw #define S_SPI4_COMMAND 24 1642*d39a76e7Sxw #define M_SPI4_COMMAND 0xff 1643*d39a76e7Sxw #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND) 1644*d39a76e7Sxw #define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND) 1645*d39a76e7Sxw 1646*d39a76e7Sxw #define A_ESPI_GOSTAT 0x8fc 1647*d39a76e7Sxw 1648*d39a76e7Sxw #define S_READ_DATA 0 1649*d39a76e7Sxw #define M_READ_DATA 0xff 1650*d39a76e7Sxw #define V_READ_DATA(x) ((x) << S_READ_DATA) 1651*d39a76e7Sxw #define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA) 1652*d39a76e7Sxw 1653*d39a76e7Sxw #define S_ESPI_CMD_BUSY 8 1654*d39a76e7Sxw #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY) 1655*d39a76e7Sxw #define F_ESPI_CMD_BUSY V_ESPI_CMD_BUSY(1U) 1656*d39a76e7Sxw 1657*d39a76e7Sxw #define S_ERROR_ACK 9 1658*d39a76e7Sxw #define V_ERROR_ACK(x) ((x) << S_ERROR_ACK) 1659*d39a76e7Sxw #define F_ERROR_ACK V_ERROR_ACK(1U) 1660*d39a76e7Sxw 1661*d39a76e7Sxw #define S_UNMAPPED_ERR 10 1662*d39a76e7Sxw #define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR) 1663*d39a76e7Sxw #define F_UNMAPPED_ERR V_UNMAPPED_ERR(1U) 1664*d39a76e7Sxw 1665*d39a76e7Sxw #define S_TRANSACTION_TIMER 16 1666*d39a76e7Sxw #define M_TRANSACTION_TIMER 0xff 1667*d39a76e7Sxw #define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER) 1668*d39a76e7Sxw #define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER) 1669*d39a76e7Sxw 1670*d39a76e7Sxw 1671*d39a76e7Sxw /* ULP registers */ 1672*d39a76e7Sxw #define A_ULP_ULIMIT 0x980 1673*d39a76e7Sxw #define A_ULP_TAGMASK 0x984 1674*d39a76e7Sxw #define A_ULP_HREG_INDEX 0x988 1675*d39a76e7Sxw #define A_ULP_HREG_DATA 0x98c 1676*d39a76e7Sxw #define A_ULP_INT_ENABLE 0x990 1677*d39a76e7Sxw #define A_ULP_INT_CAUSE 0x994 1678*d39a76e7Sxw 1679*d39a76e7Sxw #define S_HREG_PAR_ERR 0 1680*d39a76e7Sxw #define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR) 1681*d39a76e7Sxw #define F_HREG_PAR_ERR V_HREG_PAR_ERR(1U) 1682*d39a76e7Sxw 1683*d39a76e7Sxw #define S_EGRS_DATA_PAR_ERR 1 1684*d39a76e7Sxw #define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR) 1685*d39a76e7Sxw #define F_EGRS_DATA_PAR_ERR V_EGRS_DATA_PAR_ERR(1U) 1686*d39a76e7Sxw 1687*d39a76e7Sxw #define S_INGRS_DATA_PAR_ERR 2 1688*d39a76e7Sxw #define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR) 1689*d39a76e7Sxw #define F_INGRS_DATA_PAR_ERR V_INGRS_DATA_PAR_ERR(1U) 1690*d39a76e7Sxw 1691*d39a76e7Sxw #define S_PM_INTR 3 1692*d39a76e7Sxw #define V_PM_INTR(x) ((x) << S_PM_INTR) 1693*d39a76e7Sxw #define F_PM_INTR V_PM_INTR(1U) 1694*d39a76e7Sxw 1695*d39a76e7Sxw #define S_PM_E2C_SYNC_ERR 4 1696*d39a76e7Sxw #define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR) 1697*d39a76e7Sxw #define F_PM_E2C_SYNC_ERR V_PM_E2C_SYNC_ERR(1U) 1698*d39a76e7Sxw 1699*d39a76e7Sxw #define S_PM_C2E_SYNC_ERR 5 1700*d39a76e7Sxw #define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR) 1701*d39a76e7Sxw #define F_PM_C2E_SYNC_ERR V_PM_C2E_SYNC_ERR(1U) 1702*d39a76e7Sxw 1703*d39a76e7Sxw #define S_PM_E2C_EMPTY_ERR 6 1704*d39a76e7Sxw #define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR) 1705*d39a76e7Sxw #define F_PM_E2C_EMPTY_ERR V_PM_E2C_EMPTY_ERR(1U) 1706*d39a76e7Sxw 1707*d39a76e7Sxw #define S_PM_C2E_EMPTY_ERR 7 1708*d39a76e7Sxw #define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR) 1709*d39a76e7Sxw #define F_PM_C2E_EMPTY_ERR V_PM_C2E_EMPTY_ERR(1U) 1710*d39a76e7Sxw 1711*d39a76e7Sxw #define S_PM_PAR_ERR 8 1712*d39a76e7Sxw #define M_PM_PAR_ERR 0xffff 1713*d39a76e7Sxw #define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR) 1714*d39a76e7Sxw #define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR) 1715*d39a76e7Sxw 1716*d39a76e7Sxw #define S_PM_E2C_WRT_FULL 24 1717*d39a76e7Sxw #define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL) 1718*d39a76e7Sxw #define F_PM_E2C_WRT_FULL V_PM_E2C_WRT_FULL(1U) 1719*d39a76e7Sxw 1720*d39a76e7Sxw #define S_PM_C2E_WRT_FULL 25 1721*d39a76e7Sxw #define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL) 1722*d39a76e7Sxw #define F_PM_C2E_WRT_FULL V_PM_C2E_WRT_FULL(1U) 1723*d39a76e7Sxw 1724*d39a76e7Sxw #define A_ULP_PIO_CTRL 0x998 1725*d39a76e7Sxw 1726*d39a76e7Sxw /* PL registers */ 1727*d39a76e7Sxw #define A_PL_ENABLE 0xa00 1728*d39a76e7Sxw 1729*d39a76e7Sxw #define S_PL_INTR_SGE_ERR 0 1730*d39a76e7Sxw #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR) 1731*d39a76e7Sxw #define F_PL_INTR_SGE_ERR V_PL_INTR_SGE_ERR(1U) 1732*d39a76e7Sxw 1733*d39a76e7Sxw #define S_PL_INTR_SGE_DATA 1 1734*d39a76e7Sxw #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA) 1735*d39a76e7Sxw #define F_PL_INTR_SGE_DATA V_PL_INTR_SGE_DATA(1U) 1736*d39a76e7Sxw 1737*d39a76e7Sxw #define S_PL_INTR_MC3 2 1738*d39a76e7Sxw #define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3) 1739*d39a76e7Sxw #define F_PL_INTR_MC3 V_PL_INTR_MC3(1U) 1740*d39a76e7Sxw 1741*d39a76e7Sxw #define S_PL_INTR_MC4 3 1742*d39a76e7Sxw #define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4) 1743*d39a76e7Sxw #define F_PL_INTR_MC4 V_PL_INTR_MC4(1U) 1744*d39a76e7Sxw 1745*d39a76e7Sxw #define S_PL_INTR_MC5 4 1746*d39a76e7Sxw #define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5) 1747*d39a76e7Sxw #define F_PL_INTR_MC5 V_PL_INTR_MC5(1U) 1748*d39a76e7Sxw 1749*d39a76e7Sxw #define S_PL_INTR_RAT 5 1750*d39a76e7Sxw #define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT) 1751*d39a76e7Sxw #define F_PL_INTR_RAT V_PL_INTR_RAT(1U) 1752*d39a76e7Sxw 1753*d39a76e7Sxw #define S_PL_INTR_TP 6 1754*d39a76e7Sxw #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP) 1755*d39a76e7Sxw #define F_PL_INTR_TP V_PL_INTR_TP(1U) 1756*d39a76e7Sxw 1757*d39a76e7Sxw #define S_PL_INTR_ULP 7 1758*d39a76e7Sxw #define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP) 1759*d39a76e7Sxw #define F_PL_INTR_ULP V_PL_INTR_ULP(1U) 1760*d39a76e7Sxw 1761*d39a76e7Sxw #define S_PL_INTR_ESPI 8 1762*d39a76e7Sxw #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI) 1763*d39a76e7Sxw #define F_PL_INTR_ESPI V_PL_INTR_ESPI(1U) 1764*d39a76e7Sxw 1765*d39a76e7Sxw #define S_PL_INTR_CSPI 9 1766*d39a76e7Sxw #define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI) 1767*d39a76e7Sxw #define F_PL_INTR_CSPI V_PL_INTR_CSPI(1U) 1768*d39a76e7Sxw 1769*d39a76e7Sxw #define S_PL_INTR_PCIX 10 1770*d39a76e7Sxw #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX) 1771*d39a76e7Sxw #define F_PL_INTR_PCIX V_PL_INTR_PCIX(1U) 1772*d39a76e7Sxw 1773*d39a76e7Sxw #define S_PL_INTR_EXT 11 1774*d39a76e7Sxw #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT) 1775*d39a76e7Sxw #define F_PL_INTR_EXT V_PL_INTR_EXT(1U) 1776*d39a76e7Sxw 1777*d39a76e7Sxw #define A_PL_CAUSE 0xa04 1778*d39a76e7Sxw 1779*d39a76e7Sxw /* MC5 registers */ 1780*d39a76e7Sxw #define A_MC5_CONFIG 0xc04 1781*d39a76e7Sxw 1782*d39a76e7Sxw #define S_MODE 0 1783*d39a76e7Sxw #define V_MODE(x) ((x) << S_MODE) 1784*d39a76e7Sxw #define F_MODE V_MODE(1U) 1785*d39a76e7Sxw 1786*d39a76e7Sxw #define S_TCAM_RESET 1 1787*d39a76e7Sxw #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET) 1788*d39a76e7Sxw #define F_TCAM_RESET V_TCAM_RESET(1U) 1789*d39a76e7Sxw 1790*d39a76e7Sxw #define S_TCAM_READY 2 1791*d39a76e7Sxw #define V_TCAM_READY(x) ((x) << S_TCAM_READY) 1792*d39a76e7Sxw #define F_TCAM_READY V_TCAM_READY(1U) 1793*d39a76e7Sxw 1794*d39a76e7Sxw #define S_DBGI_ENABLE 4 1795*d39a76e7Sxw #define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE) 1796*d39a76e7Sxw #define F_DBGI_ENABLE V_DBGI_ENABLE(1U) 1797*d39a76e7Sxw 1798*d39a76e7Sxw #define S_M_BUS_ENABLE 5 1799*d39a76e7Sxw #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE) 1800*d39a76e7Sxw #define F_M_BUS_ENABLE V_M_BUS_ENABLE(1U) 1801*d39a76e7Sxw 1802*d39a76e7Sxw #define S_PARITY_ENABLE 6 1803*d39a76e7Sxw #define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE) 1804*d39a76e7Sxw #define F_PARITY_ENABLE V_PARITY_ENABLE(1U) 1805*d39a76e7Sxw 1806*d39a76e7Sxw #define S_SYN_ISSUE_MODE 7 1807*d39a76e7Sxw #define M_SYN_ISSUE_MODE 0x3 1808*d39a76e7Sxw #define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE) 1809*d39a76e7Sxw #define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE) 1810*d39a76e7Sxw 1811*d39a76e7Sxw #define S_BUILD 16 1812*d39a76e7Sxw #define V_BUILD(x) ((x) << S_BUILD) 1813*d39a76e7Sxw #define F_BUILD V_BUILD(1U) 1814*d39a76e7Sxw 1815*d39a76e7Sxw #define S_COMPRESSION_ENABLE 17 1816*d39a76e7Sxw #define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE) 1817*d39a76e7Sxw #define F_COMPRESSION_ENABLE V_COMPRESSION_ENABLE(1U) 1818*d39a76e7Sxw 1819*d39a76e7Sxw #define S_NUM_LIP 18 1820*d39a76e7Sxw #define M_NUM_LIP 0x3f 1821*d39a76e7Sxw #define V_NUM_LIP(x) ((x) << S_NUM_LIP) 1822*d39a76e7Sxw #define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP) 1823*d39a76e7Sxw 1824*d39a76e7Sxw #define S_TCAM_PART_CNT 24 1825*d39a76e7Sxw #define M_TCAM_PART_CNT 0x3 1826*d39a76e7Sxw #define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT) 1827*d39a76e7Sxw #define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT) 1828*d39a76e7Sxw 1829*d39a76e7Sxw #define S_TCAM_PART_TYPE 26 1830*d39a76e7Sxw #define M_TCAM_PART_TYPE 0x3 1831*d39a76e7Sxw #define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE) 1832*d39a76e7Sxw #define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE) 1833*d39a76e7Sxw 1834*d39a76e7Sxw #define S_TCAM_PART_SIZE 28 1835*d39a76e7Sxw #define M_TCAM_PART_SIZE 0x3 1836*d39a76e7Sxw #define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE) 1837*d39a76e7Sxw #define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE) 1838*d39a76e7Sxw 1839*d39a76e7Sxw #define S_TCAM_PART_TYPE_HI 30 1840*d39a76e7Sxw #define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI) 1841*d39a76e7Sxw #define F_TCAM_PART_TYPE_HI V_TCAM_PART_TYPE_HI(1U) 1842*d39a76e7Sxw 1843*d39a76e7Sxw #define A_MC5_SIZE 0xc08 1844*d39a76e7Sxw 1845*d39a76e7Sxw #define S_SIZE 0 1846*d39a76e7Sxw #define M_SIZE 0x3fffff 1847*d39a76e7Sxw #define V_SIZE(x) ((x) << S_SIZE) 1848*d39a76e7Sxw #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE) 1849*d39a76e7Sxw 1850*d39a76e7Sxw #define A_MC5_ROUTING_TABLE_INDEX 0xc0c 1851*d39a76e7Sxw 1852*d39a76e7Sxw #define S_START_OF_ROUTING_TABLE 0 1853*d39a76e7Sxw #define M_START_OF_ROUTING_TABLE 0x3fffff 1854*d39a76e7Sxw #define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE) 1855*d39a76e7Sxw #define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE) 1856*d39a76e7Sxw 1857*d39a76e7Sxw #define A_MC5_SERVER_INDEX 0xc14 1858*d39a76e7Sxw 1859*d39a76e7Sxw #define S_START_OF_SERVER_INDEX 0 1860*d39a76e7Sxw #define M_START_OF_SERVER_INDEX 0x3fffff 1861*d39a76e7Sxw #define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX) 1862*d39a76e7Sxw #define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX) 1863*d39a76e7Sxw 1864*d39a76e7Sxw #define A_MC5_LIP_RAM_ADDR 0xc18 1865*d39a76e7Sxw 1866*d39a76e7Sxw #define S_LOCAL_IP_RAM_ADDR 0 1867*d39a76e7Sxw #define M_LOCAL_IP_RAM_ADDR 0x3f 1868*d39a76e7Sxw #define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR) 1869*d39a76e7Sxw #define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR) 1870*d39a76e7Sxw 1871*d39a76e7Sxw #define S_RAM_WRITE_ENABLE 8 1872*d39a76e7Sxw #define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE) 1873*d39a76e7Sxw #define F_RAM_WRITE_ENABLE V_RAM_WRITE_ENABLE(1U) 1874*d39a76e7Sxw 1875*d39a76e7Sxw #define A_MC5_LIP_RAM_DATA 0xc1c 1876*d39a76e7Sxw #define A_MC5_RSP_LATENCY 0xc20 1877*d39a76e7Sxw 1878*d39a76e7Sxw #define S_SEARCH_RESPONSE_LATENCY 0 1879*d39a76e7Sxw #define M_SEARCH_RESPONSE_LATENCY 0x1f 1880*d39a76e7Sxw #define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY) 1881*d39a76e7Sxw #define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY) 1882*d39a76e7Sxw 1883*d39a76e7Sxw #define S_LEARN_RESPONSE_LATENCY 8 1884*d39a76e7Sxw #define M_LEARN_RESPONSE_LATENCY 0x1f 1885*d39a76e7Sxw #define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY) 1886*d39a76e7Sxw #define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY) 1887*d39a76e7Sxw 1888*d39a76e7Sxw #define A_MC5_PARITY_LATENCY 0xc24 1889*d39a76e7Sxw 1890*d39a76e7Sxw #define S_SRCHLAT 0 1891*d39a76e7Sxw #define M_SRCHLAT 0x1f 1892*d39a76e7Sxw #define V_SRCHLAT(x) ((x) << S_SRCHLAT) 1893*d39a76e7Sxw #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) 1894*d39a76e7Sxw 1895*d39a76e7Sxw #define S_PARLAT 8 1896*d39a76e7Sxw #define M_PARLAT 0x1f 1897*d39a76e7Sxw #define V_PARLAT(x) ((x) << S_PARLAT) 1898*d39a76e7Sxw #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) 1899*d39a76e7Sxw 1900*d39a76e7Sxw #define A_MC5_WR_LRN_VERIFY 0xc28 1901*d39a76e7Sxw 1902*d39a76e7Sxw #define S_POVEREN 0 1903*d39a76e7Sxw #define V_POVEREN(x) ((x) << S_POVEREN) 1904*d39a76e7Sxw #define F_POVEREN V_POVEREN(1U) 1905*d39a76e7Sxw 1906*d39a76e7Sxw #define S_LRNVEREN 1 1907*d39a76e7Sxw #define V_LRNVEREN(x) ((x) << S_LRNVEREN) 1908*d39a76e7Sxw #define F_LRNVEREN V_LRNVEREN(1U) 1909*d39a76e7Sxw 1910*d39a76e7Sxw #define S_VWVEREN 2 1911*d39a76e7Sxw #define V_VWVEREN(x) ((x) << S_VWVEREN) 1912*d39a76e7Sxw #define F_VWVEREN V_VWVEREN(1U) 1913*d39a76e7Sxw 1914*d39a76e7Sxw #define A_MC5_PART_ID_INDEX 0xc2c 1915*d39a76e7Sxw 1916*d39a76e7Sxw #define S_IDINDEX 0 1917*d39a76e7Sxw #define M_IDINDEX 0xf 1918*d39a76e7Sxw #define V_IDINDEX(x) ((x) << S_IDINDEX) 1919*d39a76e7Sxw #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) 1920*d39a76e7Sxw 1921*d39a76e7Sxw #define A_MC5_RESET_MAX 0xc30 1922*d39a76e7Sxw 1923*d39a76e7Sxw #define S_RSTMAX 0 1924*d39a76e7Sxw #define M_RSTMAX 0x1ff 1925*d39a76e7Sxw #define V_RSTMAX(x) ((x) << S_RSTMAX) 1926*d39a76e7Sxw #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) 1927*d39a76e7Sxw 1928*d39a76e7Sxw #define A_MC5_INT_ENABLE 0xc40 1929*d39a76e7Sxw 1930*d39a76e7Sxw #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0 1931*d39a76e7Sxw #define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR) 1932*d39a76e7Sxw #define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U) 1933*d39a76e7Sxw 1934*d39a76e7Sxw #define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR 1 1935*d39a76e7Sxw #define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR) 1936*d39a76e7Sxw #define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U) 1937*d39a76e7Sxw 1938*d39a76e7Sxw #define S_MC5_INT_HIT_IN_RT_REGION_ERR 2 1939*d39a76e7Sxw #define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR) 1940*d39a76e7Sxw #define F_MC5_INT_HIT_IN_RT_REGION_ERR V_MC5_INT_HIT_IN_RT_REGION_ERR(1U) 1941*d39a76e7Sxw 1942*d39a76e7Sxw #define S_MC5_INT_MISS_ERR 3 1943*d39a76e7Sxw #define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR) 1944*d39a76e7Sxw #define F_MC5_INT_MISS_ERR V_MC5_INT_MISS_ERR(1U) 1945*d39a76e7Sxw 1946*d39a76e7Sxw #define S_MC5_INT_LIP0_ERR 4 1947*d39a76e7Sxw #define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR) 1948*d39a76e7Sxw #define F_MC5_INT_LIP0_ERR V_MC5_INT_LIP0_ERR(1U) 1949*d39a76e7Sxw 1950*d39a76e7Sxw #define S_MC5_INT_LIP_MISS_ERR 5 1951*d39a76e7Sxw #define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR) 1952*d39a76e7Sxw #define F_MC5_INT_LIP_MISS_ERR V_MC5_INT_LIP_MISS_ERR(1U) 1953*d39a76e7Sxw 1954*d39a76e7Sxw #define S_MC5_INT_PARITY_ERR 6 1955*d39a76e7Sxw #define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR) 1956*d39a76e7Sxw #define F_MC5_INT_PARITY_ERR V_MC5_INT_PARITY_ERR(1U) 1957*d39a76e7Sxw 1958*d39a76e7Sxw #define S_MC5_INT_ACTIVE_REGION_FULL 7 1959*d39a76e7Sxw #define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL) 1960*d39a76e7Sxw #define F_MC5_INT_ACTIVE_REGION_FULL V_MC5_INT_ACTIVE_REGION_FULL(1U) 1961*d39a76e7Sxw 1962*d39a76e7Sxw #define S_MC5_INT_NFA_SRCH_ERR 8 1963*d39a76e7Sxw #define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR) 1964*d39a76e7Sxw #define F_MC5_INT_NFA_SRCH_ERR V_MC5_INT_NFA_SRCH_ERR(1U) 1965*d39a76e7Sxw 1966*d39a76e7Sxw #define S_MC5_INT_SYN_COOKIE 9 1967*d39a76e7Sxw #define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE) 1968*d39a76e7Sxw #define F_MC5_INT_SYN_COOKIE V_MC5_INT_SYN_COOKIE(1U) 1969*d39a76e7Sxw 1970*d39a76e7Sxw #define S_MC5_INT_SYN_COOKIE_BAD 10 1971*d39a76e7Sxw #define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD) 1972*d39a76e7Sxw #define F_MC5_INT_SYN_COOKIE_BAD V_MC5_INT_SYN_COOKIE_BAD(1U) 1973*d39a76e7Sxw 1974*d39a76e7Sxw #define S_MC5_INT_SYN_COOKIE_OFF 11 1975*d39a76e7Sxw #define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF) 1976*d39a76e7Sxw #define F_MC5_INT_SYN_COOKIE_OFF V_MC5_INT_SYN_COOKIE_OFF(1U) 1977*d39a76e7Sxw 1978*d39a76e7Sxw #define S_MC5_INT_UNKNOWN_CMD 15 1979*d39a76e7Sxw #define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD) 1980*d39a76e7Sxw #define F_MC5_INT_UNKNOWN_CMD V_MC5_INT_UNKNOWN_CMD(1U) 1981*d39a76e7Sxw 1982*d39a76e7Sxw #define S_MC5_INT_REQUESTQ_PARITY_ERR 16 1983*d39a76e7Sxw #define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR) 1984*d39a76e7Sxw #define F_MC5_INT_REQUESTQ_PARITY_ERR V_MC5_INT_REQUESTQ_PARITY_ERR(1U) 1985*d39a76e7Sxw 1986*d39a76e7Sxw #define S_MC5_INT_DISPATCHQ_PARITY_ERR 17 1987*d39a76e7Sxw #define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR) 1988*d39a76e7Sxw #define F_MC5_INT_DISPATCHQ_PARITY_ERR V_MC5_INT_DISPATCHQ_PARITY_ERR(1U) 1989*d39a76e7Sxw 1990*d39a76e7Sxw #define S_MC5_INT_DEL_ACT_EMPTY 18 1991*d39a76e7Sxw #define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY) 1992*d39a76e7Sxw #define F_MC5_INT_DEL_ACT_EMPTY V_MC5_INT_DEL_ACT_EMPTY(1U) 1993*d39a76e7Sxw 1994*d39a76e7Sxw #define A_MC5_INT_CAUSE 0xc44 1995*d39a76e7Sxw #define A_MC5_INT_TID 0xc48 1996*d39a76e7Sxw #define A_MC5_INT_PTID 0xc4c 1997*d39a76e7Sxw #define A_MC5_DBGI_CONFIG 0xc74 1998*d39a76e7Sxw #define A_MC5_DBGI_REQ_CMD 0xc78 1999*d39a76e7Sxw 2000*d39a76e7Sxw #define S_CMDMODE 0 2001*d39a76e7Sxw #define M_CMDMODE 0x7 2002*d39a76e7Sxw #define V_CMDMODE(x) ((x) << S_CMDMODE) 2003*d39a76e7Sxw #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) 2004*d39a76e7Sxw 2005*d39a76e7Sxw #define S_SADRSEL 4 2006*d39a76e7Sxw #define V_SADRSEL(x) ((x) << S_SADRSEL) 2007*d39a76e7Sxw #define F_SADRSEL V_SADRSEL(1U) 2008*d39a76e7Sxw 2009*d39a76e7Sxw #define S_WRITE_BURST_SIZE 22 2010*d39a76e7Sxw #define M_WRITE_BURST_SIZE 0x3ff 2011*d39a76e7Sxw #define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE) 2012*d39a76e7Sxw #define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE) 2013*d39a76e7Sxw 2014*d39a76e7Sxw #define A_MC5_DBGI_REQ_ADDR0 0xc7c 2015*d39a76e7Sxw #define A_MC5_DBGI_REQ_ADDR1 0xc80 2016*d39a76e7Sxw #define A_MC5_DBGI_REQ_ADDR2 0xc84 2017*d39a76e7Sxw #define A_MC5_DBGI_REQ_DATA0 0xc88 2018*d39a76e7Sxw #define A_MC5_DBGI_REQ_DATA1 0xc8c 2019*d39a76e7Sxw #define A_MC5_DBGI_REQ_DATA2 0xc90 2020*d39a76e7Sxw #define A_MC5_DBGI_REQ_DATA3 0xc94 2021*d39a76e7Sxw #define A_MC5_DBGI_REQ_DATA4 0xc98 2022*d39a76e7Sxw #define A_MC5_DBGI_REQ_MASK0 0xc9c 2023*d39a76e7Sxw #define A_MC5_DBGI_REQ_MASK1 0xca0 2024*d39a76e7Sxw #define A_MC5_DBGI_REQ_MASK2 0xca4 2025*d39a76e7Sxw #define A_MC5_DBGI_REQ_MASK3 0xca8 2026*d39a76e7Sxw #define A_MC5_DBGI_REQ_MASK4 0xcac 2027*d39a76e7Sxw #define A_MC5_DBGI_RSP_STATUS 0xcb0 2028*d39a76e7Sxw 2029*d39a76e7Sxw #define S_DBGI_RSP_VALID 0 2030*d39a76e7Sxw #define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID) 2031*d39a76e7Sxw #define F_DBGI_RSP_VALID V_DBGI_RSP_VALID(1U) 2032*d39a76e7Sxw 2033*d39a76e7Sxw #define S_DBGI_RSP_HIT 1 2034*d39a76e7Sxw #define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT) 2035*d39a76e7Sxw #define F_DBGI_RSP_HIT V_DBGI_RSP_HIT(1U) 2036*d39a76e7Sxw 2037*d39a76e7Sxw #define S_DBGI_RSP_ERR 2 2038*d39a76e7Sxw #define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR) 2039*d39a76e7Sxw #define F_DBGI_RSP_ERR V_DBGI_RSP_ERR(1U) 2040*d39a76e7Sxw 2041*d39a76e7Sxw #define S_DBGI_RSP_ERR_REASON 8 2042*d39a76e7Sxw #define M_DBGI_RSP_ERR_REASON 0x7 2043*d39a76e7Sxw #define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON) 2044*d39a76e7Sxw #define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON) 2045*d39a76e7Sxw 2046*d39a76e7Sxw #define A_MC5_DBGI_RSP_DATA0 0xcb4 2047*d39a76e7Sxw #define A_MC5_DBGI_RSP_DATA1 0xcb8 2048*d39a76e7Sxw #define A_MC5_DBGI_RSP_DATA2 0xcbc 2049*d39a76e7Sxw #define A_MC5_DBGI_RSP_DATA3 0xcc0 2050*d39a76e7Sxw #define A_MC5_DBGI_RSP_DATA4 0xcc4 2051*d39a76e7Sxw #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8 2052*d39a76e7Sxw #define A_MC5_POPEN_DATA_WR_CMD 0xccc 2053*d39a76e7Sxw #define A_MC5_POPEN_MASK_WR_CMD 0xcd0 2054*d39a76e7Sxw #define A_MC5_AOPEN_SRCH_CMD 0xcd4 2055*d39a76e7Sxw #define A_MC5_AOPEN_LRN_CMD 0xcd8 2056*d39a76e7Sxw #define A_MC5_SYN_SRCH_CMD 0xcdc 2057*d39a76e7Sxw #define A_MC5_SYN_LRN_CMD 0xce0 2058*d39a76e7Sxw #define A_MC5_ACK_SRCH_CMD 0xce4 2059*d39a76e7Sxw #define A_MC5_ACK_LRN_CMD 0xce8 2060*d39a76e7Sxw #define A_MC5_ILOOKUP_CMD 0xcec 2061*d39a76e7Sxw #define A_MC5_ELOOKUP_CMD 0xcf0 2062*d39a76e7Sxw #define A_MC5_DATA_WRITE_CMD 0xcf4 2063*d39a76e7Sxw #define A_MC5_DATA_READ_CMD 0xcf8 2064*d39a76e7Sxw #define A_MC5_MASK_WRITE_CMD 0xcfc 2065*d39a76e7Sxw 2066*d39a76e7Sxw /* PCICFG registers */ 2067*d39a76e7Sxw #define A_PCICFG_PM_CSR 0x44 2068*d39a76e7Sxw #define A_PCICFG_VPD_ADDR 0x4a 2069*d39a76e7Sxw 2070*d39a76e7Sxw #define S_VPD_ADDR 0 2071*d39a76e7Sxw #define M_VPD_ADDR 0x7fff 2072*d39a76e7Sxw #define V_VPD_ADDR(x) ((x) << S_VPD_ADDR) 2073*d39a76e7Sxw #define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR) 2074*d39a76e7Sxw 2075*d39a76e7Sxw #define S_VPD_OP_FLAG 15 2076*d39a76e7Sxw #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG) 2077*d39a76e7Sxw #define F_VPD_OP_FLAG V_VPD_OP_FLAG(1U) 2078*d39a76e7Sxw 2079*d39a76e7Sxw #define A_PCICFG_VPD_DATA 0x4c 2080*d39a76e7Sxw #define A_PCICFG_PCIX_CMD 0x60 2081*d39a76e7Sxw #define A_PCICFG_INTR_ENABLE 0xf4 2082*d39a76e7Sxw 2083*d39a76e7Sxw #define S_MASTER_PARITY_ERR 0 2084*d39a76e7Sxw #define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR) 2085*d39a76e7Sxw #define F_MASTER_PARITY_ERR V_MASTER_PARITY_ERR(1U) 2086*d39a76e7Sxw 2087*d39a76e7Sxw #define S_SIG_TARGET_ABORT 1 2088*d39a76e7Sxw #define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT) 2089*d39a76e7Sxw #define F_SIG_TARGET_ABORT V_SIG_TARGET_ABORT(1U) 2090*d39a76e7Sxw 2091*d39a76e7Sxw #define S_RCV_TARGET_ABORT 2 2092*d39a76e7Sxw #define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT) 2093*d39a76e7Sxw #define F_RCV_TARGET_ABORT V_RCV_TARGET_ABORT(1U) 2094*d39a76e7Sxw 2095*d39a76e7Sxw #define S_RCV_MASTER_ABORT 3 2096*d39a76e7Sxw #define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT) 2097*d39a76e7Sxw #define F_RCV_MASTER_ABORT V_RCV_MASTER_ABORT(1U) 2098*d39a76e7Sxw 2099*d39a76e7Sxw #define S_SIG_SYS_ERR 4 2100*d39a76e7Sxw #define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR) 2101*d39a76e7Sxw #define F_SIG_SYS_ERR V_SIG_SYS_ERR(1U) 2102*d39a76e7Sxw 2103*d39a76e7Sxw #define S_DET_PARITY_ERR 5 2104*d39a76e7Sxw #define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR) 2105*d39a76e7Sxw #define F_DET_PARITY_ERR V_DET_PARITY_ERR(1U) 2106*d39a76e7Sxw 2107*d39a76e7Sxw #define S_PIO_PARITY_ERR 6 2108*d39a76e7Sxw #define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR) 2109*d39a76e7Sxw #define F_PIO_PARITY_ERR V_PIO_PARITY_ERR(1U) 2110*d39a76e7Sxw 2111*d39a76e7Sxw #define S_WF_PARITY_ERR 7 2112*d39a76e7Sxw #define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR) 2113*d39a76e7Sxw #define F_WF_PARITY_ERR V_WF_PARITY_ERR(1U) 2114*d39a76e7Sxw 2115*d39a76e7Sxw #define S_RF_PARITY_ERR 8 2116*d39a76e7Sxw #define M_RF_PARITY_ERR 0x3 2117*d39a76e7Sxw #define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR) 2118*d39a76e7Sxw #define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR) 2119*d39a76e7Sxw 2120*d39a76e7Sxw #define S_CF_PARITY_ERR 10 2121*d39a76e7Sxw #define M_CF_PARITY_ERR 0x3 2122*d39a76e7Sxw #define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR) 2123*d39a76e7Sxw #define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR) 2124*d39a76e7Sxw 2125*d39a76e7Sxw #define A_PCICFG_INTR_CAUSE 0xf8 2126*d39a76e7Sxw #define A_PCICFG_MODE 0xfc 2127*d39a76e7Sxw 2128*d39a76e7Sxw #define S_PCI_MODE_64BIT 0 2129*d39a76e7Sxw #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT) 2130*d39a76e7Sxw #define F_PCI_MODE_64BIT V_PCI_MODE_64BIT(1U) 2131*d39a76e7Sxw 2132*d39a76e7Sxw #define S_PCI_MODE_66MHZ 1 2133*d39a76e7Sxw #define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ) 2134*d39a76e7Sxw #define F_PCI_MODE_66MHZ V_PCI_MODE_66MHZ(1U) 2135*d39a76e7Sxw 2136*d39a76e7Sxw #define S_PCI_MODE_PCIX_INITPAT 2 2137*d39a76e7Sxw #define M_PCI_MODE_PCIX_INITPAT 0x7 2138*d39a76e7Sxw #define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT) 2139*d39a76e7Sxw #define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT) 2140*d39a76e7Sxw 2141*d39a76e7Sxw #define S_PCI_MODE_PCIX 5 2142*d39a76e7Sxw #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX) 2143*d39a76e7Sxw #define F_PCI_MODE_PCIX V_PCI_MODE_PCIX(1U) 2144*d39a76e7Sxw 2145*d39a76e7Sxw #define S_PCI_MODE_CLK 6 2146*d39a76e7Sxw #define M_PCI_MODE_CLK 0x3 2147*d39a76e7Sxw #define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK) 2148*d39a76e7Sxw #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK) 2149*d39a76e7Sxw 2150