1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw #pragma ident "%Z%%M% %I% %E% SMI" /* mv88e1xxx.c */ 27*d39a76e7Sxw 28*d39a76e7Sxw #include "common.h" 29*d39a76e7Sxw #include "mv88e1xxx.h" 30*d39a76e7Sxw #include "cphy.h" 31*d39a76e7Sxw #include "elmer0.h" 32*d39a76e7Sxw 33*d39a76e7Sxw /* MV88E1XXX MDI crossover register values */ 34*d39a76e7Sxw #define CROSSOVER_MDI 0 35*d39a76e7Sxw #define CROSSOVER_MDIX 1 36*d39a76e7Sxw #define CROSSOVER_AUTO 3 37*d39a76e7Sxw 38*d39a76e7Sxw #define INTR_ENABLE_MASK 0x6CA0 39*d39a76e7Sxw 40*d39a76e7Sxw /* 41*d39a76e7Sxw * Set the bits given by 'bitval' in PHY register 'reg'. 42*d39a76e7Sxw */ 43*d39a76e7Sxw static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval) 44*d39a76e7Sxw { 45*d39a76e7Sxw u32 val; 46*d39a76e7Sxw 47*d39a76e7Sxw (void) simple_mdio_read(cphy, reg, &val); 48*d39a76e7Sxw (void) simple_mdio_write(cphy, reg, val | bitval); 49*d39a76e7Sxw } 50*d39a76e7Sxw 51*d39a76e7Sxw /* 52*d39a76e7Sxw * Clear the bits given by 'bitval' in PHY register 'reg'. 53*d39a76e7Sxw */ 54*d39a76e7Sxw static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval) 55*d39a76e7Sxw { 56*d39a76e7Sxw u32 val; 57*d39a76e7Sxw 58*d39a76e7Sxw (void) simple_mdio_read(cphy, reg, &val); 59*d39a76e7Sxw (void) simple_mdio_write(cphy, reg, val & ~bitval); 60*d39a76e7Sxw } 61*d39a76e7Sxw 62*d39a76e7Sxw /* 63*d39a76e7Sxw * NAME: phy_reset 64*d39a76e7Sxw * 65*d39a76e7Sxw * DESC: Reset the given PHY's port. NOTE: This is not a global 66*d39a76e7Sxw * chip reset. 67*d39a76e7Sxw * 68*d39a76e7Sxw * PARAMS: cphy - Pointer to PHY instance data. 69*d39a76e7Sxw * 70*d39a76e7Sxw * RETURN: 0 - Successfull reset. 71*d39a76e7Sxw * -1 - Timeout. 72*d39a76e7Sxw */ 73*d39a76e7Sxw /* ARGSUSED */ 74*d39a76e7Sxw static int mv88e1xxx_reset(struct cphy *cphy, int wait) 75*d39a76e7Sxw { 76*d39a76e7Sxw u32 ctl; 77*d39a76e7Sxw int time_out = 1000; 78*d39a76e7Sxw 79*d39a76e7Sxw mdio_set_bit(cphy, MII_BMCR, BMCR_RESET); 80*d39a76e7Sxw 81*d39a76e7Sxw do { 82*d39a76e7Sxw (void) simple_mdio_read(cphy, MII_BMCR, &ctl); 83*d39a76e7Sxw ctl &= BMCR_RESET; 84*d39a76e7Sxw if (ctl) 85*d39a76e7Sxw DELAY_US(1); 86*d39a76e7Sxw } while (ctl && --time_out); 87*d39a76e7Sxw 88*d39a76e7Sxw return ctl ? -1 : 0; 89*d39a76e7Sxw } 90*d39a76e7Sxw 91*d39a76e7Sxw static int mv88e1xxx_interrupt_enable(struct cphy *cphy) 92*d39a76e7Sxw { 93*d39a76e7Sxw /* Enable PHY interrupts. */ 94*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 95*d39a76e7Sxw INTR_ENABLE_MASK); 96*d39a76e7Sxw 97*d39a76e7Sxw /* Enable Marvell interrupts through Elmer0. */ 98*d39a76e7Sxw if (t1_is_asic(cphy->adapter)) { 99*d39a76e7Sxw u32 elmer; 100*d39a76e7Sxw 101*d39a76e7Sxw (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 102*d39a76e7Sxw elmer |= ELMER0_GP_BIT1; 103*d39a76e7Sxw if (is_T2(cphy->adapter)) { 104*d39a76e7Sxw elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; 105*d39a76e7Sxw } 106*d39a76e7Sxw (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 107*d39a76e7Sxw } 108*d39a76e7Sxw return 0; 109*d39a76e7Sxw } 110*d39a76e7Sxw 111*d39a76e7Sxw static int mv88e1xxx_interrupt_disable(struct cphy *cphy) 112*d39a76e7Sxw { 113*d39a76e7Sxw /* Disable all phy interrupts. */ 114*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0); 115*d39a76e7Sxw 116*d39a76e7Sxw /* Disable Marvell interrupts through Elmer0. */ 117*d39a76e7Sxw if (t1_is_asic(cphy->adapter)) { 118*d39a76e7Sxw u32 elmer; 119*d39a76e7Sxw 120*d39a76e7Sxw (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); 121*d39a76e7Sxw elmer &= ~ELMER0_GP_BIT1; 122*d39a76e7Sxw if (is_T2(cphy->adapter)) { 123*d39a76e7Sxw elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4); 124*d39a76e7Sxw } 125*d39a76e7Sxw (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); 126*d39a76e7Sxw } 127*d39a76e7Sxw return 0; 128*d39a76e7Sxw } 129*d39a76e7Sxw 130*d39a76e7Sxw static int mv88e1xxx_interrupt_clear(struct cphy *cphy) 131*d39a76e7Sxw { 132*d39a76e7Sxw u32 elmer; 133*d39a76e7Sxw 134*d39a76e7Sxw /* Clear PHY interrupts by reading the register. */ 135*d39a76e7Sxw (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer); 136*d39a76e7Sxw 137*d39a76e7Sxw /* Clear Marvell interrupts through Elmer0. */ 138*d39a76e7Sxw if (t1_is_asic(cphy->adapter)) { 139*d39a76e7Sxw (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer); 140*d39a76e7Sxw elmer |= ELMER0_GP_BIT1; 141*d39a76e7Sxw if (is_T2(cphy->adapter)) { 142*d39a76e7Sxw elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; 143*d39a76e7Sxw } 144*d39a76e7Sxw (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer); 145*d39a76e7Sxw } 146*d39a76e7Sxw return 0; 147*d39a76e7Sxw } 148*d39a76e7Sxw 149*d39a76e7Sxw /* 150*d39a76e7Sxw * Set the PHY speed and duplex. This also disables auto-negotiation, except 151*d39a76e7Sxw * for 1Gb/s, where auto-negotiation is mandatory. 152*d39a76e7Sxw */ 153*d39a76e7Sxw static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) 154*d39a76e7Sxw { 155*d39a76e7Sxw u32 ctl; 156*d39a76e7Sxw 157*d39a76e7Sxw (void) simple_mdio_read(phy, MII_BMCR, &ctl); 158*d39a76e7Sxw if (speed >= 0) { 159*d39a76e7Sxw ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); 160*d39a76e7Sxw if (speed == SPEED_100) 161*d39a76e7Sxw ctl |= BMCR_SPEED100; 162*d39a76e7Sxw else if (speed == SPEED_1000) 163*d39a76e7Sxw ctl |= BMCR_SPEED1000; 164*d39a76e7Sxw } 165*d39a76e7Sxw if (duplex >= 0) { 166*d39a76e7Sxw ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE); 167*d39a76e7Sxw if (duplex == DUPLEX_FULL) 168*d39a76e7Sxw ctl |= BMCR_FULLDPLX; 169*d39a76e7Sxw } 170*d39a76e7Sxw if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */ 171*d39a76e7Sxw ctl |= BMCR_ANENABLE; 172*d39a76e7Sxw (void) simple_mdio_write(phy, MII_BMCR, ctl); 173*d39a76e7Sxw return 0; 174*d39a76e7Sxw } 175*d39a76e7Sxw 176*d39a76e7Sxw static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover) 177*d39a76e7Sxw { 178*d39a76e7Sxw u32 data32; 179*d39a76e7Sxw 180*d39a76e7Sxw (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32); 181*d39a76e7Sxw data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE); 182*d39a76e7Sxw data32 |= V_PSCR_MDI_XOVER_MODE(crossover); 183*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32); 184*d39a76e7Sxw return 0; 185*d39a76e7Sxw } 186*d39a76e7Sxw 187*d39a76e7Sxw static int mv88e1xxx_autoneg_enable(struct cphy *cphy) 188*d39a76e7Sxw { 189*d39a76e7Sxw u32 ctl; 190*d39a76e7Sxw 191*d39a76e7Sxw (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO); 192*d39a76e7Sxw 193*d39a76e7Sxw (void) simple_mdio_read(cphy, MII_BMCR, &ctl); 194*d39a76e7Sxw /* restart autoneg for change to take effect */ 195*d39a76e7Sxw ctl |= BMCR_ANENABLE | BMCR_ANRESTART; 196*d39a76e7Sxw (void) simple_mdio_write(cphy, MII_BMCR, ctl); 197*d39a76e7Sxw return 0; 198*d39a76e7Sxw } 199*d39a76e7Sxw 200*d39a76e7Sxw static int mv88e1xxx_autoneg_disable(struct cphy *cphy) 201*d39a76e7Sxw { 202*d39a76e7Sxw u32 ctl; 203*d39a76e7Sxw 204*d39a76e7Sxw /* 205*d39a76e7Sxw * Crossover *must* be set to manual in order to disable auto-neg. 206*d39a76e7Sxw * The Alaska FAQs document highlights this point. 207*d39a76e7Sxw */ 208*d39a76e7Sxw (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI); 209*d39a76e7Sxw 210*d39a76e7Sxw /* 211*d39a76e7Sxw * Must include autoneg reset when disabling auto-neg. This 212*d39a76e7Sxw * is described in the Alaska FAQ document. 213*d39a76e7Sxw */ 214*d39a76e7Sxw (void) simple_mdio_read(cphy, MII_BMCR, &ctl); 215*d39a76e7Sxw ctl &= ~BMCR_ANENABLE; 216*d39a76e7Sxw (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); 217*d39a76e7Sxw return 0; 218*d39a76e7Sxw } 219*d39a76e7Sxw 220*d39a76e7Sxw static int mv88e1xxx_autoneg_restart(struct cphy *cphy) 221*d39a76e7Sxw { 222*d39a76e7Sxw mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART); 223*d39a76e7Sxw return 0; 224*d39a76e7Sxw } 225*d39a76e7Sxw 226*d39a76e7Sxw static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map) 227*d39a76e7Sxw { 228*d39a76e7Sxw u32 val = 0; 229*d39a76e7Sxw 230*d39a76e7Sxw if (advertise_map & 231*d39a76e7Sxw (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { 232*d39a76e7Sxw (void) simple_mdio_read(phy, MII_GBCR, &val); 233*d39a76e7Sxw val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL); 234*d39a76e7Sxw if (advertise_map & ADVERTISED_1000baseT_Half) 235*d39a76e7Sxw val |= GBCR_ADV_1000HALF; 236*d39a76e7Sxw if (advertise_map & ADVERTISED_1000baseT_Full) 237*d39a76e7Sxw val |= GBCR_ADV_1000FULL; 238*d39a76e7Sxw } 239*d39a76e7Sxw (void) simple_mdio_write(phy, MII_GBCR, val); 240*d39a76e7Sxw 241*d39a76e7Sxw val = 1; 242*d39a76e7Sxw if (advertise_map & ADVERTISED_10baseT_Half) 243*d39a76e7Sxw val |= ADVERTISE_10HALF; 244*d39a76e7Sxw if (advertise_map & ADVERTISED_10baseT_Full) 245*d39a76e7Sxw val |= ADVERTISE_10FULL; 246*d39a76e7Sxw if (advertise_map & ADVERTISED_100baseT_Half) 247*d39a76e7Sxw val |= ADVERTISE_100HALF; 248*d39a76e7Sxw if (advertise_map & ADVERTISED_100baseT_Full) 249*d39a76e7Sxw val |= ADVERTISE_100FULL; 250*d39a76e7Sxw if (advertise_map & ADVERTISED_PAUSE) 251*d39a76e7Sxw val |= ADVERTISE_PAUSE; 252*d39a76e7Sxw if (advertise_map & ADVERTISED_ASYM_PAUSE) 253*d39a76e7Sxw val |= ADVERTISE_PAUSE_ASYM; 254*d39a76e7Sxw (void) simple_mdio_write(phy, MII_ADVERTISE, val); 255*d39a76e7Sxw return 0; 256*d39a76e7Sxw } 257*d39a76e7Sxw 258*d39a76e7Sxw static int mv88e1xxx_set_loopback(struct cphy *cphy, int on) 259*d39a76e7Sxw { 260*d39a76e7Sxw if (on) 261*d39a76e7Sxw mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK); 262*d39a76e7Sxw else 263*d39a76e7Sxw mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK); 264*d39a76e7Sxw return 0; 265*d39a76e7Sxw } 266*d39a76e7Sxw 267*d39a76e7Sxw static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok, 268*d39a76e7Sxw int *speed, int *duplex, int *fc) 269*d39a76e7Sxw { 270*d39a76e7Sxw u32 status; 271*d39a76e7Sxw int sp = -1, dplx = -1, pause = 0; 272*d39a76e7Sxw 273*d39a76e7Sxw (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status); 274*d39a76e7Sxw if ((status & V_PSSR_STATUS_RESOLVED) != 0) { 275*d39a76e7Sxw if (status & V_PSSR_RX_PAUSE) 276*d39a76e7Sxw pause |= PAUSE_RX; 277*d39a76e7Sxw if (status & V_PSSR_TX_PAUSE) 278*d39a76e7Sxw pause |= PAUSE_TX; 279*d39a76e7Sxw dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; 280*d39a76e7Sxw sp = G_PSSR_SPEED(status); 281*d39a76e7Sxw if (sp == 0) 282*d39a76e7Sxw sp = SPEED_10; 283*d39a76e7Sxw else if (sp == 1) 284*d39a76e7Sxw sp = SPEED_100; 285*d39a76e7Sxw else 286*d39a76e7Sxw sp = SPEED_1000; 287*d39a76e7Sxw } 288*d39a76e7Sxw if (link_ok) 289*d39a76e7Sxw *link_ok = (status & V_PSSR_LINK) != 0; 290*d39a76e7Sxw if (speed) 291*d39a76e7Sxw *speed = sp; 292*d39a76e7Sxw if (duplex) 293*d39a76e7Sxw *duplex = dplx; 294*d39a76e7Sxw if (fc) 295*d39a76e7Sxw *fc = pause; 296*d39a76e7Sxw return 0; 297*d39a76e7Sxw } 298*d39a76e7Sxw 299*d39a76e7Sxw static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) 300*d39a76e7Sxw { 301*d39a76e7Sxw u32 val; 302*d39a76e7Sxw 303*d39a76e7Sxw (void) simple_mdio_read(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val); 304*d39a76e7Sxw 305*d39a76e7Sxw /* 306*d39a76e7Sxw * Set the downshift counter to 2 so we try to establish Gb link 307*d39a76e7Sxw * twice before downshifting. 308*d39a76e7Sxw */ 309*d39a76e7Sxw val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT)); 310*d39a76e7Sxw 311*d39a76e7Sxw if (downshift_enable) 312*d39a76e7Sxw val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2); 313*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val); 314*d39a76e7Sxw return 0; 315*d39a76e7Sxw } 316*d39a76e7Sxw 317*d39a76e7Sxw static int mv88e1xxx_interrupt_handler(struct cphy *cphy) 318*d39a76e7Sxw { 319*d39a76e7Sxw int cphy_cause = 0; 320*d39a76e7Sxw u32 status; 321*d39a76e7Sxw 322*d39a76e7Sxw /* 323*d39a76e7Sxw * Loop until cause reads zero. Need to handle bouncing interrupts. 324*d39a76e7Sxw */ 325*d39a76e7Sxw /*CONSTCOND*/ 326*d39a76e7Sxw while (1) { 327*d39a76e7Sxw u32 cause; 328*d39a76e7Sxw 329*d39a76e7Sxw (void) simple_mdio_read(cphy, MV88E1XXX_INTERRUPT_STATUS_REGISTER, 330*d39a76e7Sxw &cause); 331*d39a76e7Sxw cause &= INTR_ENABLE_MASK; 332*d39a76e7Sxw if (!cause) break; 333*d39a76e7Sxw 334*d39a76e7Sxw if (cause & MV88E1XXX_INTR_LINK_CHNG) { 335*d39a76e7Sxw (void) simple_mdio_read(cphy, 336*d39a76e7Sxw MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status); 337*d39a76e7Sxw 338*d39a76e7Sxw if (status & MV88E1XXX_INTR_LINK_CHNG) { 339*d39a76e7Sxw cphy->state |= PHY_LINK_UP; 340*d39a76e7Sxw } else { 341*d39a76e7Sxw cphy->state &= ~PHY_LINK_UP; 342*d39a76e7Sxw if (cphy->state & PHY_AUTONEG_EN) 343*d39a76e7Sxw cphy->state &= ~PHY_AUTONEG_RDY; 344*d39a76e7Sxw cphy_cause |= cphy_cause_link_change; 345*d39a76e7Sxw } 346*d39a76e7Sxw } 347*d39a76e7Sxw 348*d39a76e7Sxw if (cause & MV88E1XXX_INTR_AUTONEG_DONE) 349*d39a76e7Sxw cphy->state |= PHY_AUTONEG_RDY; 350*d39a76e7Sxw 351*d39a76e7Sxw if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) == 352*d39a76e7Sxw (PHY_LINK_UP | PHY_AUTONEG_RDY)) 353*d39a76e7Sxw cphy_cause |= cphy_cause_link_change; 354*d39a76e7Sxw } 355*d39a76e7Sxw return cphy_cause; 356*d39a76e7Sxw } 357*d39a76e7Sxw 358*d39a76e7Sxw static void mv88e1xxx_destroy(struct cphy *cphy) 359*d39a76e7Sxw { 360*d39a76e7Sxw t1_os_free((void *)cphy, sizeof(*cphy)); 361*d39a76e7Sxw } 362*d39a76e7Sxw 363*d39a76e7Sxw #ifdef C99_NOT_SUPPORTED 364*d39a76e7Sxw static struct cphy_ops mv88e1xxx_ops = { 365*d39a76e7Sxw mv88e1xxx_destroy, 366*d39a76e7Sxw mv88e1xxx_reset, 367*d39a76e7Sxw mv88e1xxx_interrupt_enable, 368*d39a76e7Sxw mv88e1xxx_interrupt_disable, 369*d39a76e7Sxw mv88e1xxx_interrupt_clear, 370*d39a76e7Sxw mv88e1xxx_interrupt_handler, 371*d39a76e7Sxw mv88e1xxx_autoneg_enable, 372*d39a76e7Sxw mv88e1xxx_autoneg_disable, 373*d39a76e7Sxw mv88e1xxx_autoneg_restart, 374*d39a76e7Sxw mv88e1xxx_advertise, 375*d39a76e7Sxw mv88e1xxx_set_loopback, 376*d39a76e7Sxw mv88e1xxx_set_speed_duplex, 377*d39a76e7Sxw mv88e1xxx_get_link_status, 378*d39a76e7Sxw }; 379*d39a76e7Sxw #else 380*d39a76e7Sxw static struct cphy_ops mv88e1xxx_ops = { 381*d39a76e7Sxw .destroy = mv88e1xxx_destroy, 382*d39a76e7Sxw .reset = mv88e1xxx_reset, 383*d39a76e7Sxw .interrupt_enable = mv88e1xxx_interrupt_enable, 384*d39a76e7Sxw .interrupt_disable = mv88e1xxx_interrupt_disable, 385*d39a76e7Sxw .interrupt_clear = mv88e1xxx_interrupt_clear, 386*d39a76e7Sxw .interrupt_handler = mv88e1xxx_interrupt_handler, 387*d39a76e7Sxw .autoneg_enable = mv88e1xxx_autoneg_enable, 388*d39a76e7Sxw .autoneg_disable = mv88e1xxx_autoneg_disable, 389*d39a76e7Sxw .autoneg_restart = mv88e1xxx_autoneg_restart, 390*d39a76e7Sxw .advertise = mv88e1xxx_advertise, 391*d39a76e7Sxw .set_loopback = mv88e1xxx_set_loopback, 392*d39a76e7Sxw .set_speed_duplex = mv88e1xxx_set_speed_duplex, 393*d39a76e7Sxw .get_link_status = mv88e1xxx_get_link_status, 394*d39a76e7Sxw }; 395*d39a76e7Sxw #endif 396*d39a76e7Sxw 397*d39a76e7Sxw static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr, 398*d39a76e7Sxw struct mdio_ops *mdio_ops) 399*d39a76e7Sxw { 400*d39a76e7Sxw struct cphy *cphy = t1_os_malloc_wait_zero(sizeof(*cphy)); 401*d39a76e7Sxw 402*d39a76e7Sxw if (!cphy) return NULL; 403*d39a76e7Sxw 404*d39a76e7Sxw cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops); 405*d39a76e7Sxw 406*d39a76e7Sxw /* Configure particular PHY's to run in a different mode. */ 407*d39a76e7Sxw if ((board_info(adapter)->caps & SUPPORTED_TP) && 408*d39a76e7Sxw board_info(adapter)->chip_phy == CHBT_PHY_88E1111) { 409*d39a76e7Sxw /* 410*d39a76e7Sxw * Configure the PHY transmitter as class A to reduce EMI. 411*d39a76e7Sxw */ 412*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB); 413*d39a76e7Sxw (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_REGISTER, 0x8004); 414*d39a76e7Sxw } 415*d39a76e7Sxw (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */ 416*d39a76e7Sxw 417*d39a76e7Sxw /* LED */ 418*d39a76e7Sxw if (is_T2(adapter)) { 419*d39a76e7Sxw (void) simple_mdio_write(cphy, 420*d39a76e7Sxw MV88E1XXX_LED_CONTROL_REGISTER, 0x1); 421*d39a76e7Sxw } 422*d39a76e7Sxw 423*d39a76e7Sxw return cphy; 424*d39a76e7Sxw } 425*d39a76e7Sxw 426*d39a76e7Sxw /* ARGSUSED */ 427*d39a76e7Sxw static int mv88e1xxx_phy_reset(adapter_t* adapter) 428*d39a76e7Sxw { 429*d39a76e7Sxw return 0; 430*d39a76e7Sxw } 431*d39a76e7Sxw 432*d39a76e7Sxw struct gphy t1_mv88e1xxx_ops = { 433*d39a76e7Sxw mv88e1xxx_phy_create, 434*d39a76e7Sxw mv88e1xxx_phy_reset 435*d39a76e7Sxw }; 436