1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw #pragma ident "%Z%%M% %I% %E% SMI" /* ixf1010.c */ 27*d39a76e7Sxw 28*d39a76e7Sxw #include "gmac.h" 29*d39a76e7Sxw #include "elmer0.h" 30*d39a76e7Sxw 31*d39a76e7Sxw /* Update fast changing statistics every 15 seconds */ 32*d39a76e7Sxw #define STATS_TICK_SECS 15 33*d39a76e7Sxw /* 30 minutes for full statistics update */ 34*d39a76e7Sxw #define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS) 35*d39a76e7Sxw 36*d39a76e7Sxw /* 37*d39a76e7Sxw * The IXF1010 can handle frames up to 16383 bytes but it's optimized for 38*d39a76e7Sxw * frames up to 9831 (0x2667) bytes, so we limit jumbo frame size to this. 39*d39a76e7Sxw * This length includes ethernet header and FCS. 40*d39a76e7Sxw */ 41*d39a76e7Sxw #define MAX_FRAME_SIZE 0x2667 42*d39a76e7Sxw 43*d39a76e7Sxw /* MAC registers */ 44*d39a76e7Sxw enum { 45*d39a76e7Sxw /* Per-port registers */ 46*d39a76e7Sxw REG_MACADDR_LOW = 0, 47*d39a76e7Sxw REG_MACADDR_HIGH = 0x4, 48*d39a76e7Sxw REG_FDFC_TYPE = 0xC, 49*d39a76e7Sxw REG_FC_TX_TIMER_VALUE = 0x1c, 50*d39a76e7Sxw REG_IPG_RX_TIME1 = 0x28, 51*d39a76e7Sxw REG_IPG_RX_TIME2 = 0x2c, 52*d39a76e7Sxw REG_IPG_TX_TIME = 0x30, 53*d39a76e7Sxw REG_PAUSE_THRES = 0x38, 54*d39a76e7Sxw REG_MAX_FRAME_SIZE = 0x3c, 55*d39a76e7Sxw REG_RGMII_SPEED = 0x40, 56*d39a76e7Sxw REG_FC_ENABLE = 0x48, 57*d39a76e7Sxw REG_DISCARD_CTRL_FRAMES = 0x54, 58*d39a76e7Sxw REG_DIVERSE_CONFIG = 0x60, 59*d39a76e7Sxw REG_RX_FILTER = 0x64, 60*d39a76e7Sxw REG_MC_ADDR_LOW = 0x68, 61*d39a76e7Sxw REG_MC_ADDR_HIGH = 0x6c, 62*d39a76e7Sxw 63*d39a76e7Sxw REG_RX_OCTETS_OK = 0x80, 64*d39a76e7Sxw REG_RX_OCTETS_BAD = 0x84, 65*d39a76e7Sxw REG_RX_UC_PKTS = 0x88, 66*d39a76e7Sxw REG_RX_MC_PKTS = 0x8c, 67*d39a76e7Sxw REG_RX_BC_PKTS = 0x90, 68*d39a76e7Sxw REG_RX_FCS_ERR = 0xb0, 69*d39a76e7Sxw REG_RX_TAGGED = 0xb4, 70*d39a76e7Sxw REG_RX_DATA_ERR = 0xb8, 71*d39a76e7Sxw REG_RX_ALIGN_ERR = 0xbc, 72*d39a76e7Sxw REG_RX_LONG_ERR = 0xc0, 73*d39a76e7Sxw REG_RX_JABBER_ERR = 0xc4, 74*d39a76e7Sxw REG_RX_PAUSE_FRAMES = 0xc8, 75*d39a76e7Sxw REG_RX_UNKNOWN_CTRL_FRAMES = 0xcc, 76*d39a76e7Sxw REG_RX_VERY_LONG_ERR = 0xd0, 77*d39a76e7Sxw REG_RX_RUNT_ERR = 0xd4, 78*d39a76e7Sxw REG_RX_SHORT_ERR = 0xd8, 79*d39a76e7Sxw REG_RX_SYMBOL_ERR = 0xe4, 80*d39a76e7Sxw 81*d39a76e7Sxw REG_TX_OCTETS_OK = 0x100, 82*d39a76e7Sxw REG_TX_OCTETS_BAD = 0x104, 83*d39a76e7Sxw REG_TX_UC_PKTS = 0x108, 84*d39a76e7Sxw REG_TX_MC_PKTS = 0x10c, 85*d39a76e7Sxw REG_TX_BC_PKTS = 0x110, 86*d39a76e7Sxw REG_TX_EXCESSIVE_LEN_DROP = 0x14c, 87*d39a76e7Sxw REG_TX_UNDERRUN = 0x150, 88*d39a76e7Sxw REG_TX_TAGGED = 0x154, 89*d39a76e7Sxw REG_TX_PAUSE_FRAMES = 0x15C, 90*d39a76e7Sxw 91*d39a76e7Sxw /* Global registers */ 92*d39a76e7Sxw REG_PORT_ENABLE = 0x1400, 93*d39a76e7Sxw 94*d39a76e7Sxw REG_JTAG_ID = 0x1430, 95*d39a76e7Sxw 96*d39a76e7Sxw RX_FIFO_HIGH_WATERMARK_BASE = 0x1600, 97*d39a76e7Sxw RX_FIFO_LOW_WATERMARK_BASE = 0x1628, 98*d39a76e7Sxw RX_FIFO_FRAMES_REMOVED_BASE = 0x1650, 99*d39a76e7Sxw 100*d39a76e7Sxw REG_RX_ERR_DROP = 0x167c, 101*d39a76e7Sxw REG_RX_FIFO_OVERFLOW_EVENT = 0x1680, 102*d39a76e7Sxw 103*d39a76e7Sxw TX_FIFO_HIGH_WATERMARK_BASE = 0x1800, 104*d39a76e7Sxw TX_FIFO_LOW_WATERMARK_BASE = 0x1828, 105*d39a76e7Sxw TX_FIFO_XFER_THRES_BASE = 0x1850, 106*d39a76e7Sxw 107*d39a76e7Sxw REG_TX_FIFO_OVERFLOW_EVENT = 0x1878, 108*d39a76e7Sxw REG_TX_FIFO_OOS_EVENT = 0x1884, 109*d39a76e7Sxw 110*d39a76e7Sxw TX_FIFO_FRAMES_REMOVED_BASE = 0x1888, 111*d39a76e7Sxw 112*d39a76e7Sxw REG_SPI_RX_BURST = 0x1c00, 113*d39a76e7Sxw REG_SPI_RX_TRAINING = 0x1c04, 114*d39a76e7Sxw REG_SPI_RX_CALENDAR = 0x1c08, 115*d39a76e7Sxw REG_SPI_TX_SYNC = 0x1c0c 116*d39a76e7Sxw }; 117*d39a76e7Sxw 118*d39a76e7Sxw enum { /* RMON registers */ 119*d39a76e7Sxw REG_RxOctetsTotalOK = 0x80, 120*d39a76e7Sxw REG_RxOctetsBad = 0x84, 121*d39a76e7Sxw REG_RxUCPkts = 0x88, 122*d39a76e7Sxw REG_RxMCPkts = 0x8c, 123*d39a76e7Sxw REG_RxBCPkts = 0x90, 124*d39a76e7Sxw REG_RxJumboPkts = 0xac, 125*d39a76e7Sxw REG_RxFCSErrors = 0xb0, 126*d39a76e7Sxw REG_RxDataErrors = 0xb8, 127*d39a76e7Sxw REG_RxAlignErrors = 0xbc, 128*d39a76e7Sxw REG_RxLongErrors = 0xc0, 129*d39a76e7Sxw REG_RxJabberErrors = 0xc4, 130*d39a76e7Sxw REG_RxPauseMacControlCounter = 0xc8, 131*d39a76e7Sxw REG_RxVeryLongErrors = 0xd0, 132*d39a76e7Sxw REG_RxRuntErrors = 0xd4, 133*d39a76e7Sxw REG_RxShortErrors = 0xd8, 134*d39a76e7Sxw REG_RxSequenceErrors = 0xe0, 135*d39a76e7Sxw REG_RxSymbolErrors = 0xe4, 136*d39a76e7Sxw 137*d39a76e7Sxw REG_TxOctetsTotalOK = 0x100, 138*d39a76e7Sxw REG_TxOctetsBad = 0x104, 139*d39a76e7Sxw REG_TxUCPkts = 0x108, 140*d39a76e7Sxw REG_TxMCPkts = 0x10c, 141*d39a76e7Sxw REG_TxBCPkts = 0x110, 142*d39a76e7Sxw REG_TxJumboPkts = 0x12C, 143*d39a76e7Sxw REG_TxTotalCollisions = 0x134, 144*d39a76e7Sxw REG_TxExcessiveLengthDrop = 0x14c, 145*d39a76e7Sxw REG_TxUnderrun = 0x150, 146*d39a76e7Sxw REG_TxCRCErrors = 0x158, 147*d39a76e7Sxw REG_TxPauseFrames = 0x15c 148*d39a76e7Sxw }; 149*d39a76e7Sxw 150*d39a76e7Sxw enum { 151*d39a76e7Sxw DIVERSE_CONFIG_PAD_ENABLE = 0x80, 152*d39a76e7Sxw DIVERSE_CONFIG_CRC_ADD = 0x40 153*d39a76e7Sxw }; 154*d39a76e7Sxw 155*d39a76e7Sxw #define MACREG_BASE 0 156*d39a76e7Sxw #define MACREG(mac, mac_reg) ((mac)->instance->mac_base + (mac_reg)) 157*d39a76e7Sxw 158*d39a76e7Sxw struct _cmac_instance { 159*d39a76e7Sxw u32 mac_base; 160*d39a76e7Sxw u32 index; 161*d39a76e7Sxw u32 version; 162*d39a76e7Sxw u32 ticks; 163*d39a76e7Sxw }; 164*d39a76e7Sxw 165*d39a76e7Sxw static void disable_port(struct cmac *mac) 166*d39a76e7Sxw { 167*d39a76e7Sxw u32 val; 168*d39a76e7Sxw 169*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, REG_PORT_ENABLE, &val); 170*d39a76e7Sxw val &= ~(1 << mac->instance->index); 171*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, REG_PORT_ENABLE, val); 172*d39a76e7Sxw } 173*d39a76e7Sxw 174*d39a76e7Sxw #define RMON_UPDATE(mac, name, stat_name) \ 175*d39a76e7Sxw (void) t1_tpi_read((mac)->adapter, MACREG(mac, REG_##name), &val); \ 176*d39a76e7Sxw (mac)->stats.stat_name += val; 177*d39a76e7Sxw 178*d39a76e7Sxw /* 179*d39a76e7Sxw * Read the current values of the RMON counters and add them to the cumulative 180*d39a76e7Sxw * port statistics. The HW RMON counters are cleared by this operation. 181*d39a76e7Sxw */ 182*d39a76e7Sxw static void port_stats_update(struct cmac *mac) 183*d39a76e7Sxw { 184*d39a76e7Sxw u32 val; 185*d39a76e7Sxw 186*d39a76e7Sxw /* Rx stats */ 187*d39a76e7Sxw RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK); 188*d39a76e7Sxw RMON_UPDATE(mac, RxOctetsBad, RxOctetsBad); 189*d39a76e7Sxw RMON_UPDATE(mac, RxUCPkts, RxUnicastFramesOK); 190*d39a76e7Sxw RMON_UPDATE(mac, RxMCPkts, RxMulticastFramesOK); 191*d39a76e7Sxw RMON_UPDATE(mac, RxBCPkts, RxBroadcastFramesOK); 192*d39a76e7Sxw RMON_UPDATE(mac, RxJumboPkts, RxJumboFramesOK); 193*d39a76e7Sxw RMON_UPDATE(mac, RxFCSErrors, RxFCSErrors); 194*d39a76e7Sxw RMON_UPDATE(mac, RxAlignErrors, RxAlignErrors); 195*d39a76e7Sxw RMON_UPDATE(mac, RxLongErrors, RxFrameTooLongErrors); 196*d39a76e7Sxw RMON_UPDATE(mac, RxVeryLongErrors, RxFrameTooLongErrors); 197*d39a76e7Sxw RMON_UPDATE(mac, RxPauseMacControlCounter, RxPauseFrames); 198*d39a76e7Sxw RMON_UPDATE(mac, RxDataErrors, RxDataErrors); 199*d39a76e7Sxw RMON_UPDATE(mac, RxJabberErrors, RxJabberErrors); 200*d39a76e7Sxw RMON_UPDATE(mac, RxRuntErrors, RxRuntErrors); 201*d39a76e7Sxw RMON_UPDATE(mac, RxShortErrors, RxRuntErrors); 202*d39a76e7Sxw RMON_UPDATE(mac, RxSequenceErrors, RxSequenceErrors); 203*d39a76e7Sxw RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors); 204*d39a76e7Sxw 205*d39a76e7Sxw /* Tx stats (skip collision stats as we are full-duplex only) */ 206*d39a76e7Sxw RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK); 207*d39a76e7Sxw RMON_UPDATE(mac, TxOctetsBad, TxOctetsBad); 208*d39a76e7Sxw RMON_UPDATE(mac, TxUCPkts, TxUnicastFramesOK); 209*d39a76e7Sxw RMON_UPDATE(mac, TxMCPkts, TxMulticastFramesOK); 210*d39a76e7Sxw RMON_UPDATE(mac, TxBCPkts, TxBroadcastFramesOK); 211*d39a76e7Sxw RMON_UPDATE(mac, TxJumboPkts, TxJumboFramesOK); 212*d39a76e7Sxw RMON_UPDATE(mac, TxPauseFrames, TxPauseFrames); 213*d39a76e7Sxw RMON_UPDATE(mac, TxExcessiveLengthDrop, TxLengthErrors); 214*d39a76e7Sxw RMON_UPDATE(mac, TxUnderrun, TxUnderrun); 215*d39a76e7Sxw RMON_UPDATE(mac, TxCRCErrors, TxFCSErrors); 216*d39a76e7Sxw } 217*d39a76e7Sxw 218*d39a76e7Sxw /* No-op interrupt operation as this MAC does not support interrupts */ 219*d39a76e7Sxw /* ARGSUSED */ 220*d39a76e7Sxw static int mac_intr_op(struct cmac *mac) 221*d39a76e7Sxw { 222*d39a76e7Sxw return 0; 223*d39a76e7Sxw } 224*d39a76e7Sxw 225*d39a76e7Sxw /* Expect MAC address to be in network byte order. */ 226*d39a76e7Sxw static int mac_set_address(struct cmac *mac, u8 addr[6]) 227*d39a76e7Sxw { 228*d39a76e7Sxw u32 addr_lo, addr_hi; 229*d39a76e7Sxw 230*d39a76e7Sxw addr_lo = addr[2]; 231*d39a76e7Sxw addr_lo = (addr_lo << 8) | addr[3]; 232*d39a76e7Sxw addr_lo = (addr_lo << 8) | addr[4]; 233*d39a76e7Sxw addr_lo = (addr_lo << 8) | addr[5]; 234*d39a76e7Sxw 235*d39a76e7Sxw addr_hi = addr[0]; 236*d39a76e7Sxw addr_hi = (addr_hi << 8) | addr[1]; 237*d39a76e7Sxw 238*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_LOW), addr_lo); 239*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), addr_hi); 240*d39a76e7Sxw return 0; 241*d39a76e7Sxw } 242*d39a76e7Sxw 243*d39a76e7Sxw static int mac_get_address(struct cmac *mac, u8 addr[6]) 244*d39a76e7Sxw { 245*d39a76e7Sxw u32 addr_lo, addr_hi; 246*d39a76e7Sxw 247*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_LOW), &addr_lo); 248*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_MACADDR_HIGH), &addr_hi); 249*d39a76e7Sxw 250*d39a76e7Sxw addr[0] = (u8) (addr_hi >> 8); 251*d39a76e7Sxw addr[1] = (u8) addr_hi; 252*d39a76e7Sxw addr[2] = (u8) (addr_lo >> 24); 253*d39a76e7Sxw addr[3] = (u8) (addr_lo >> 16); 254*d39a76e7Sxw addr[4] = (u8) (addr_lo >> 8); 255*d39a76e7Sxw addr[5] = (u8) addr_lo; 256*d39a76e7Sxw return 0; 257*d39a76e7Sxw } 258*d39a76e7Sxw 259*d39a76e7Sxw /* This is intended to reset a port, not the whole MAC */ 260*d39a76e7Sxw /* ARGSUSED */ 261*d39a76e7Sxw static int mac_reset(struct cmac *mac) 262*d39a76e7Sxw { 263*d39a76e7Sxw return 0; 264*d39a76e7Sxw } 265*d39a76e7Sxw 266*d39a76e7Sxw static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm) 267*d39a76e7Sxw { 268*d39a76e7Sxw u32 val, new_mode; 269*d39a76e7Sxw adapter_t *adapter = mac->adapter; 270*d39a76e7Sxw u32 addr_lo, addr_hi; 271*d39a76e7Sxw u8 *addr; 272*d39a76e7Sxw 273*d39a76e7Sxw (void) t1_tpi_read(adapter, MACREG(mac, REG_RX_FILTER), &val); 274*d39a76e7Sxw new_mode = val & ~7; 275*d39a76e7Sxw if (!t1_rx_mode_promisc(rm) && mac->instance->version > 0) 276*d39a76e7Sxw new_mode |= 1; /* only set if version > 0 due to erratum */ 277*d39a76e7Sxw if (!t1_rx_mode_promisc(rm) && !t1_rx_mode_allmulti(rm) 278*d39a76e7Sxw && t1_rx_mode_mc_cnt(rm) <= 1) 279*d39a76e7Sxw new_mode |= 2; 280*d39a76e7Sxw if (new_mode != val) 281*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), new_mode); 282*d39a76e7Sxw switch (t1_rx_mode_mc_cnt(rm)) { 283*d39a76e7Sxw case 0: 284*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), 0); 285*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), 0); 286*d39a76e7Sxw break; 287*d39a76e7Sxw case 1: 288*d39a76e7Sxw addr = t1_get_next_mcaddr(rm); 289*d39a76e7Sxw addr_lo = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | 290*d39a76e7Sxw addr[5]; 291*d39a76e7Sxw addr_hi = (addr[0] << 8) | addr[1]; 292*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_LOW), addr_lo); 293*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_MC_ADDR_HIGH), addr_hi); 294*d39a76e7Sxw break; 295*d39a76e7Sxw default: 296*d39a76e7Sxw break; 297*d39a76e7Sxw } 298*d39a76e7Sxw return 0; 299*d39a76e7Sxw } 300*d39a76e7Sxw 301*d39a76e7Sxw static int mac_set_mtu(struct cmac *mac, int mtu) 302*d39a76e7Sxw { 303*d39a76e7Sxw /* MAX_FRAME_SIZE inludes header + FCS, mtu doesn't */ 304*d39a76e7Sxw if (mtu > (MAX_FRAME_SIZE - 14 - 4)) return -EINVAL; 305*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_MAX_FRAME_SIZE), 306*d39a76e7Sxw mtu + 14 + 4); 307*d39a76e7Sxw return 0; 308*d39a76e7Sxw } 309*d39a76e7Sxw 310*d39a76e7Sxw static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 311*d39a76e7Sxw int fc) 312*d39a76e7Sxw { 313*d39a76e7Sxw u32 val; 314*d39a76e7Sxw 315*d39a76e7Sxw if (speed >= 0 && speed != SPEED_100 && speed != SPEED_1000) 316*d39a76e7Sxw return -1; 317*d39a76e7Sxw if (duplex >= 0 && duplex != DUPLEX_FULL) 318*d39a76e7Sxw return -1; 319*d39a76e7Sxw 320*d39a76e7Sxw if (speed >= 0) { 321*d39a76e7Sxw val = speed == SPEED_100 ? 1 : 2; 322*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_RGMII_SPEED), val); 323*d39a76e7Sxw } 324*d39a76e7Sxw 325*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val); 326*d39a76e7Sxw val &= ~3; 327*d39a76e7Sxw if (fc & PAUSE_RX) 328*d39a76e7Sxw val |= 1; 329*d39a76e7Sxw if (fc & PAUSE_TX) 330*d39a76e7Sxw val |= 2; 331*d39a76e7Sxw (void) t1_tpi_write(mac->adapter, MACREG(mac, REG_FC_ENABLE), val); 332*d39a76e7Sxw return 0; 333*d39a76e7Sxw } 334*d39a76e7Sxw 335*d39a76e7Sxw static int mac_get_speed_duplex_fc(struct cmac *mac, int *speed, int *duplex, 336*d39a76e7Sxw int *fc) 337*d39a76e7Sxw { 338*d39a76e7Sxw u32 val; 339*d39a76e7Sxw 340*d39a76e7Sxw if (duplex) 341*d39a76e7Sxw *duplex = DUPLEX_FULL; 342*d39a76e7Sxw if (speed) { 343*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_RGMII_SPEED), 344*d39a76e7Sxw &val); 345*d39a76e7Sxw *speed = (val & 2) ? SPEED_1000 : SPEED_100; 346*d39a76e7Sxw } 347*d39a76e7Sxw if (fc) { 348*d39a76e7Sxw (void) t1_tpi_read(mac->adapter, MACREG(mac, REG_FC_ENABLE), &val); 349*d39a76e7Sxw *fc = 0; 350*d39a76e7Sxw if (val & 1) 351*d39a76e7Sxw *fc |= PAUSE_RX; 352*d39a76e7Sxw if (val & 2) 353*d39a76e7Sxw *fc |= PAUSE_TX; 354*d39a76e7Sxw } 355*d39a76e7Sxw return 0; 356*d39a76e7Sxw } 357*d39a76e7Sxw 358*d39a76e7Sxw static void enable_port(struct cmac *mac) 359*d39a76e7Sxw { 360*d39a76e7Sxw u32 val; 361*d39a76e7Sxw u32 index = mac->instance->index; 362*d39a76e7Sxw adapter_t *adapter = mac->adapter; 363*d39a76e7Sxw 364*d39a76e7Sxw (void) t1_tpi_read(adapter, MACREG(mac, REG_DIVERSE_CONFIG), &val); 365*d39a76e7Sxw val |= DIVERSE_CONFIG_CRC_ADD | DIVERSE_CONFIG_PAD_ENABLE; 366*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_DIVERSE_CONFIG), val); 367*d39a76e7Sxw if (mac->instance->version > 0) 368*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 3); 369*d39a76e7Sxw else /* Don't enable unicast address filtering due to IXF1010 bug */ 370*d39a76e7Sxw (void) t1_tpi_write(adapter, MACREG(mac, REG_RX_FILTER), 2); 371*d39a76e7Sxw 372*d39a76e7Sxw (void) t1_tpi_read(adapter, REG_RX_ERR_DROP, &val); 373*d39a76e7Sxw val |= (1 << index); 374*d39a76e7Sxw (void) t1_tpi_write(adapter, REG_RX_ERR_DROP, val); 375*d39a76e7Sxw 376*d39a76e7Sxw /* 377*d39a76e7Sxw * Clear the port RMON registers by adding their current values to the 378*d39a76e7Sxw * cumulatice port stats and then clearing the stats. Really. 379*d39a76e7Sxw */ 380*d39a76e7Sxw port_stats_update(mac); 381*d39a76e7Sxw (void) memset(&mac->stats, 0, sizeof(struct cmac_statistics)); 382*d39a76e7Sxw mac->instance->ticks = 0; 383*d39a76e7Sxw 384*d39a76e7Sxw (void) t1_tpi_read(adapter, REG_PORT_ENABLE, &val); 385*d39a76e7Sxw val |= (1 << index); 386*d39a76e7Sxw (void) t1_tpi_write(adapter, REG_PORT_ENABLE, val); 387*d39a76e7Sxw 388*d39a76e7Sxw index <<= 2; 389*d39a76e7Sxw if (is_T2(adapter)) { 390*d39a76e7Sxw /* T204: set the Fifo water level & threshold */ 391*d39a76e7Sxw if (index) index <<= 2; 392*d39a76e7Sxw (void) t1_tpi_write(adapter, RX_FIFO_HIGH_WATERMARK_BASE + index, 0x740); 393*d39a76e7Sxw (void) t1_tpi_write(adapter, RX_FIFO_LOW_WATERMARK_BASE + index, 0x730); 394*d39a76e7Sxw (void) t1_tpi_write(adapter, TX_FIFO_HIGH_WATERMARK_BASE + index, 0x600); 395*d39a76e7Sxw (void) t1_tpi_write(adapter, TX_FIFO_LOW_WATERMARK_BASE + index, 0x1d0); 396*d39a76e7Sxw (void) t1_tpi_write(adapter, TX_FIFO_XFER_THRES_BASE + index, 0x1100); 397*d39a76e7Sxw } else { 398*d39a76e7Sxw /* 399*d39a76e7Sxw * Set the TX Fifo Threshold to 0x400 instead of 0x100 to work around 400*d39a76e7Sxw * Underrun problem. Intel has blessed this solution. 401*d39a76e7Sxw */ 402*d39a76e7Sxw (void) t1_tpi_write(adapter, 403*d39a76e7Sxw TX_FIFO_XFER_THRES_BASE + mac->instance->index * 4, 0x400); 404*d39a76e7Sxw } 405*d39a76e7Sxw } 406*d39a76e7Sxw 407*d39a76e7Sxw /* IXF1010 ports do not have separate enables for TX and RX */ 408*d39a76e7Sxw static int mac_enable(struct cmac *mac, int which) 409*d39a76e7Sxw { 410*d39a76e7Sxw if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX)) 411*d39a76e7Sxw enable_port(mac); 412*d39a76e7Sxw return 0; 413*d39a76e7Sxw } 414*d39a76e7Sxw 415*d39a76e7Sxw static int mac_disable(struct cmac *mac, int which) 416*d39a76e7Sxw { 417*d39a76e7Sxw if (which & (MAC_DIRECTION_RX | MAC_DIRECTION_TX)) 418*d39a76e7Sxw disable_port(mac); 419*d39a76e7Sxw return 0; 420*d39a76e7Sxw } 421*d39a76e7Sxw 422*d39a76e7Sxw /* 423*d39a76e7Sxw * This function is called periodically to accumulate the current values of the 424*d39a76e7Sxw * RMON counters into the port statistics. Since the counters are only 32 bits 425*d39a76e7Sxw * some of them can overflow in less than a minute at GigE speeds, so this 426*d39a76e7Sxw * function should be called every 30 seconds or so. 427*d39a76e7Sxw * 428*d39a76e7Sxw * To cut down on reading costs we update only the octet counters at each tick 429*d39a76e7Sxw * and do a full update at major ticks, which can be every 30 minutes or more. 430*d39a76e7Sxw */ 431*d39a76e7Sxw static const struct cmac_statistics *mac_update_statistics(struct cmac *mac, 432*d39a76e7Sxw int flag) 433*d39a76e7Sxw { 434*d39a76e7Sxw if (flag == MAC_STATS_UPDATE_FULL || 435*d39a76e7Sxw MAJOR_UPDATE_TICKS <= mac->instance->ticks) { 436*d39a76e7Sxw port_stats_update(mac); 437*d39a76e7Sxw mac->instance->ticks = 0; 438*d39a76e7Sxw } else { 439*d39a76e7Sxw u32 val; 440*d39a76e7Sxw 441*d39a76e7Sxw RMON_UPDATE(mac, RxOctetsTotalOK, RxOctetsOK); 442*d39a76e7Sxw RMON_UPDATE(mac, TxOctetsTotalOK, TxOctetsOK); 443*d39a76e7Sxw mac->instance->ticks++; 444*d39a76e7Sxw } 445*d39a76e7Sxw return &mac->stats; 446*d39a76e7Sxw } 447*d39a76e7Sxw 448*d39a76e7Sxw static void mac_destroy(struct cmac *mac) 449*d39a76e7Sxw { 450*d39a76e7Sxw t1_os_free((void *)mac, sizeof(*mac) + sizeof(cmac_instance)); 451*d39a76e7Sxw } 452*d39a76e7Sxw 453*d39a76e7Sxw #ifdef C99_NOT_SUPPORTED 454*d39a76e7Sxw static struct cmac_ops ixf1010_ops = { 455*d39a76e7Sxw mac_destroy, 456*d39a76e7Sxw mac_reset, 457*d39a76e7Sxw mac_intr_op, 458*d39a76e7Sxw mac_intr_op, 459*d39a76e7Sxw mac_intr_op, 460*d39a76e7Sxw NULL, 461*d39a76e7Sxw mac_enable, 462*d39a76e7Sxw mac_disable, 463*d39a76e7Sxw NULL, 464*d39a76e7Sxw NULL, 465*d39a76e7Sxw mac_set_mtu, 466*d39a76e7Sxw mac_set_rx_mode, 467*d39a76e7Sxw mac_set_speed_duplex_fc, 468*d39a76e7Sxw mac_get_speed_duplex_fc, 469*d39a76e7Sxw mac_update_statistics, 470*d39a76e7Sxw mac_get_address, 471*d39a76e7Sxw mac_set_address 472*d39a76e7Sxw }; 473*d39a76e7Sxw #else 474*d39a76e7Sxw static struct cmac_ops ixf1010_ops = { 475*d39a76e7Sxw .destroy = mac_destroy, 476*d39a76e7Sxw .reset = mac_reset, 477*d39a76e7Sxw .interrupt_enable = mac_intr_op, 478*d39a76e7Sxw .interrupt_disable = mac_intr_op, 479*d39a76e7Sxw .interrupt_clear = mac_intr_op, 480*d39a76e7Sxw .enable = mac_enable, 481*d39a76e7Sxw .disable = mac_disable, 482*d39a76e7Sxw .set_mtu = mac_set_mtu, 483*d39a76e7Sxw .set_rx_mode = mac_set_rx_mode, 484*d39a76e7Sxw .set_speed_duplex_fc = mac_set_speed_duplex_fc, 485*d39a76e7Sxw .get_speed_duplex_fc = mac_get_speed_duplex_fc, 486*d39a76e7Sxw .statistics_update = mac_update_statistics, 487*d39a76e7Sxw .macaddress_get = mac_get_address, 488*d39a76e7Sxw .macaddress_set = mac_set_address, 489*d39a76e7Sxw }; 490*d39a76e7Sxw #endif 491*d39a76e7Sxw 492*d39a76e7Sxw static int ixf1010_mac_reset(adapter_t *adapter) 493*d39a76e7Sxw { 494*d39a76e7Sxw u32 val; 495*d39a76e7Sxw 496*d39a76e7Sxw (void) t1_tpi_read(adapter, A_ELMER0_GPO, &val); 497*d39a76e7Sxw if ((val & 1) != 0) { 498*d39a76e7Sxw val &= ~1; 499*d39a76e7Sxw (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); 500*d39a76e7Sxw DELAY_US(2); 501*d39a76e7Sxw } 502*d39a76e7Sxw val |= 1; 503*d39a76e7Sxw (void) t1_tpi_write(adapter, A_ELMER0_GPO, val); 504*d39a76e7Sxw DELAY_US(2); 505*d39a76e7Sxw 506*d39a76e7Sxw (void) t1_tpi_write(adapter, REG_PORT_ENABLE, 0); 507*d39a76e7Sxw return 0; 508*d39a76e7Sxw } 509*d39a76e7Sxw 510*d39a76e7Sxw static struct cmac *ixf1010_mac_create(adapter_t *adapter, int index) 511*d39a76e7Sxw { 512*d39a76e7Sxw struct cmac *mac; 513*d39a76e7Sxw u32 val; 514*d39a76e7Sxw 515*d39a76e7Sxw if (index > 9) return NULL; 516*d39a76e7Sxw 517*d39a76e7Sxw mac = t1_os_malloc_wait_zero(sizeof(*mac) + sizeof(cmac_instance)); 518*d39a76e7Sxw if (!mac) return NULL; 519*d39a76e7Sxw 520*d39a76e7Sxw mac->ops = &ixf1010_ops; 521*d39a76e7Sxw mac->instance = (cmac_instance *)(mac + 1); 522*d39a76e7Sxw 523*d39a76e7Sxw mac->instance->mac_base = MACREG_BASE + (index * 0x200); 524*d39a76e7Sxw mac->instance->index = index; 525*d39a76e7Sxw mac->adapter = adapter; 526*d39a76e7Sxw mac->instance->ticks = 0; 527*d39a76e7Sxw 528*d39a76e7Sxw (void) t1_tpi_read(adapter, REG_JTAG_ID, &val); 529*d39a76e7Sxw mac->instance->version = val >> 28; 530*d39a76e7Sxw return mac; 531*d39a76e7Sxw } 532*d39a76e7Sxw 533*d39a76e7Sxw struct gmac t1_ixf1010_ops = { 534*d39a76e7Sxw STATS_TICK_SECS, 535*d39a76e7Sxw ixf1010_mac_create, 536*d39a76e7Sxw ixf1010_mac_reset 537*d39a76e7Sxw }; 538