1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw #ifndef CHELSIO_ELMER0_H 27*d39a76e7Sxw #define CHELSIO_ELMER0_H 28*d39a76e7Sxw 29*d39a76e7Sxw /* ELMER0 flavors */ 30*d39a76e7Sxw enum { 31*d39a76e7Sxw ELMER0_XC2S300E_6FT256_C, 32*d39a76e7Sxw ELMER0_XC2S100E_6TQ144_C 33*d39a76e7Sxw }; 34*d39a76e7Sxw 35*d39a76e7Sxw /* ELMER0 registers */ 36*d39a76e7Sxw #define A_ELMER0_VERSION 0x100000 37*d39a76e7Sxw #define A_ELMER0_PHY_CFG 0x100004 38*d39a76e7Sxw #define A_ELMER0_INT_ENABLE 0x100008 39*d39a76e7Sxw #define A_ELMER0_INT_CAUSE 0x10000c 40*d39a76e7Sxw #define A_ELMER0_GPI_CFG 0x100010 41*d39a76e7Sxw #define A_ELMER0_GPI_STAT 0x100014 42*d39a76e7Sxw #define A_ELMER0_GPO 0x100018 43*d39a76e7Sxw #define A_ELMER0_PORT0_MI1_CFG 0x400000 44*d39a76e7Sxw 45*d39a76e7Sxw #define S_MI1_MDI_ENABLE 0 46*d39a76e7Sxw #define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE) 47*d39a76e7Sxw #define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U) 48*d39a76e7Sxw 49*d39a76e7Sxw #define S_MI1_MDI_INVERT 1 50*d39a76e7Sxw #define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT) 51*d39a76e7Sxw #define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U) 52*d39a76e7Sxw 53*d39a76e7Sxw #define S_MI1_PREAMBLE_ENABLE 2 54*d39a76e7Sxw #define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE) 55*d39a76e7Sxw #define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U) 56*d39a76e7Sxw 57*d39a76e7Sxw #define S_MI1_SOF 3 58*d39a76e7Sxw #define M_MI1_SOF 0x3 59*d39a76e7Sxw #define V_MI1_SOF(x) ((x) << S_MI1_SOF) 60*d39a76e7Sxw #define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF) 61*d39a76e7Sxw 62*d39a76e7Sxw #define S_MI1_CLK_DIV 5 63*d39a76e7Sxw #define M_MI1_CLK_DIV 0xff 64*d39a76e7Sxw #define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV) 65*d39a76e7Sxw #define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV) 66*d39a76e7Sxw 67*d39a76e7Sxw #define A_ELMER0_PORT0_MI1_ADDR 0x400004 68*d39a76e7Sxw 69*d39a76e7Sxw #define S_MI1_REG_ADDR 0 70*d39a76e7Sxw #define M_MI1_REG_ADDR 0x1f 71*d39a76e7Sxw #define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR) 72*d39a76e7Sxw #define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR) 73*d39a76e7Sxw 74*d39a76e7Sxw #define S_MI1_PHY_ADDR 5 75*d39a76e7Sxw #define M_MI1_PHY_ADDR 0x1f 76*d39a76e7Sxw #define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR) 77*d39a76e7Sxw #define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR) 78*d39a76e7Sxw 79*d39a76e7Sxw #define A_ELMER0_PORT0_MI1_DATA 0x400008 80*d39a76e7Sxw 81*d39a76e7Sxw #define S_MI1_DATA 0 82*d39a76e7Sxw #define M_MI1_DATA 0xffff 83*d39a76e7Sxw #define V_MI1_DATA(x) ((x) << S_MI1_DATA) 84*d39a76e7Sxw #define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA) 85*d39a76e7Sxw 86*d39a76e7Sxw #define A_ELMER0_PORT0_MI1_OP 0x40000c 87*d39a76e7Sxw 88*d39a76e7Sxw #define S_MI1_OP 0 89*d39a76e7Sxw #define M_MI1_OP 0x3 90*d39a76e7Sxw #define V_MI1_OP(x) ((x) << S_MI1_OP) 91*d39a76e7Sxw #define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP) 92*d39a76e7Sxw 93*d39a76e7Sxw #define S_MI1_ADDR_AUTOINC 2 94*d39a76e7Sxw #define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC) 95*d39a76e7Sxw #define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U) 96*d39a76e7Sxw 97*d39a76e7Sxw #define S_MI1_OP_BUSY 31 98*d39a76e7Sxw #define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY) 99*d39a76e7Sxw #define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U) 100*d39a76e7Sxw 101*d39a76e7Sxw #define A_ELMER0_PORT1_MI1_CFG 0x500000 102*d39a76e7Sxw #define A_ELMER0_PORT1_MI1_ADDR 0x500004 103*d39a76e7Sxw #define A_ELMER0_PORT1_MI1_DATA 0x500008 104*d39a76e7Sxw #define A_ELMER0_PORT1_MI1_OP 0x50000c 105*d39a76e7Sxw #define A_ELMER0_PORT2_MI1_CFG 0x600000 106*d39a76e7Sxw #define A_ELMER0_PORT2_MI1_ADDR 0x600004 107*d39a76e7Sxw #define A_ELMER0_PORT2_MI1_DATA 0x600008 108*d39a76e7Sxw #define A_ELMER0_PORT2_MI1_OP 0x60000c 109*d39a76e7Sxw #define A_ELMER0_PORT3_MI1_CFG 0x700000 110*d39a76e7Sxw #define A_ELMER0_PORT3_MI1_ADDR 0x700004 111*d39a76e7Sxw #define A_ELMER0_PORT3_MI1_DATA 0x700008 112*d39a76e7Sxw #define A_ELMER0_PORT3_MI1_OP 0x70000c 113*d39a76e7Sxw 114*d39a76e7Sxw /* Simple bit definition for GPI and GP0 registers. */ 115*d39a76e7Sxw #define ELMER0_GP_BIT0 0x0001 116*d39a76e7Sxw #define ELMER0_GP_BIT1 0x0002 117*d39a76e7Sxw #define ELMER0_GP_BIT2 0x0004 118*d39a76e7Sxw #define ELMER0_GP_BIT3 0x0008 119*d39a76e7Sxw #define ELMER0_GP_BIT4 0x0010 120*d39a76e7Sxw #define ELMER0_GP_BIT5 0x0020 121*d39a76e7Sxw #define ELMER0_GP_BIT6 0x0040 122*d39a76e7Sxw #define ELMER0_GP_BIT7 0x0080 123*d39a76e7Sxw #define ELMER0_GP_BIT8 0x0100 124*d39a76e7Sxw #define ELMER0_GP_BIT9 0x0200 125*d39a76e7Sxw #define ELMER0_GP_BIT10 0x0400 126*d39a76e7Sxw #define ELMER0_GP_BIT11 0x0800 127*d39a76e7Sxw #define ELMER0_GP_BIT12 0x1000 128*d39a76e7Sxw #define ELMER0_GP_BIT13 0x2000 129*d39a76e7Sxw #define ELMER0_GP_BIT14 0x4000 130*d39a76e7Sxw #define ELMER0_GP_BIT15 0x8000 131*d39a76e7Sxw #define ELMER0_GP_BIT16 0x10000 132*d39a76e7Sxw #define ELMER0_GP_BIT17 0x20000 133*d39a76e7Sxw #define ELMER0_GP_BIT18 0x40000 134*d39a76e7Sxw #define ELMER0_GP_BIT19 0x80000 135*d39a76e7Sxw 136*d39a76e7Sxw #define MI1_OP_DIRECT_WRITE 1 137*d39a76e7Sxw #define MI1_OP_DIRECT_READ 2 138*d39a76e7Sxw 139*d39a76e7Sxw #define MI1_OP_INDIRECT_ADDRESS 0 140*d39a76e7Sxw #define MI1_OP_INDIRECT_WRITE 1 141*d39a76e7Sxw #define MI1_OP_INDIRECT_READ_INC 2 142*d39a76e7Sxw #define MI1_OP_INDIRECT_READ 3 143*d39a76e7Sxw 144*d39a76e7Sxw #endif 145