1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw #pragma ident "%Z%%M% %I% %E% SMI" /* cphy.h */ 27*d39a76e7Sxw 28*d39a76e7Sxw #ifndef CHELSIO_CPHY_H 29*d39a76e7Sxw #define CHELSIO_CPHY_H 30*d39a76e7Sxw 31*d39a76e7Sxw #include "common.h" 32*d39a76e7Sxw 33*d39a76e7Sxw struct mdio_ops { 34*d39a76e7Sxw void (*init)(adapter_t *adapter, const struct board_info *bi); 35*d39a76e7Sxw int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 36*d39a76e7Sxw int reg_addr, unsigned int *val); 37*d39a76e7Sxw int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 38*d39a76e7Sxw int reg_addr, unsigned int val); 39*d39a76e7Sxw }; 40*d39a76e7Sxw 41*d39a76e7Sxw /* PHY interrupt types */ 42*d39a76e7Sxw enum { 43*d39a76e7Sxw cphy_cause_link_change = 0x1, 44*d39a76e7Sxw cphy_cause_error = 0x2 45*d39a76e7Sxw }; 46*d39a76e7Sxw 47*d39a76e7Sxw enum { 48*d39a76e7Sxw PHY_LINK_UP = 0x1, 49*d39a76e7Sxw PHY_AUTONEG_RDY = 0x2, 50*d39a76e7Sxw PHY_AUTONEG_EN = 0x4 51*d39a76e7Sxw }; 52*d39a76e7Sxw 53*d39a76e7Sxw struct cphy; 54*d39a76e7Sxw 55*d39a76e7Sxw /* PHY operations */ 56*d39a76e7Sxw struct cphy_ops { 57*d39a76e7Sxw void (*destroy)(struct cphy *); 58*d39a76e7Sxw int (*reset)(struct cphy *, int wait); 59*d39a76e7Sxw 60*d39a76e7Sxw int (*interrupt_enable)(struct cphy *); 61*d39a76e7Sxw int (*interrupt_disable)(struct cphy *); 62*d39a76e7Sxw int (*interrupt_clear)(struct cphy *); 63*d39a76e7Sxw int (*interrupt_handler)(struct cphy *); 64*d39a76e7Sxw 65*d39a76e7Sxw int (*autoneg_enable)(struct cphy *); 66*d39a76e7Sxw int (*autoneg_disable)(struct cphy *); 67*d39a76e7Sxw int (*autoneg_restart)(struct cphy *); 68*d39a76e7Sxw 69*d39a76e7Sxw int (*advertise)(struct cphy *phy, unsigned int advertise_map); 70*d39a76e7Sxw int (*set_loopback)(struct cphy *, int on); 71*d39a76e7Sxw int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 72*d39a76e7Sxw int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 73*d39a76e7Sxw int *duplex, int *fc); 74*d39a76e7Sxw }; 75*d39a76e7Sxw 76*d39a76e7Sxw /* A PHY instance */ 77*d39a76e7Sxw struct cphy { 78*d39a76e7Sxw int addr; /* PHY address */ 79*d39a76e7Sxw int state; /* Link status state machine */ 80*d39a76e7Sxw adapter_t *adapter; /* associated adapter */ 81*d39a76e7Sxw 82*d39a76e7Sxw ch_cyclic_t phy_update_cyclic; 83*d39a76e7Sxw 84*d39a76e7Sxw u16 bmsr; 85*d39a76e7Sxw int count; 86*d39a76e7Sxw int act_count; 87*d39a76e7Sxw int act_on; 88*d39a76e7Sxw 89*d39a76e7Sxw u32 elmer_gpo; 90*d39a76e7Sxw 91*d39a76e7Sxw struct cphy_ops *ops; /* PHY operations */ 92*d39a76e7Sxw int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 93*d39a76e7Sxw int reg_addr, unsigned int *val); 94*d39a76e7Sxw int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 95*d39a76e7Sxw int reg_addr, unsigned int val); 96*d39a76e7Sxw struct cphy_instance *instance; 97*d39a76e7Sxw }; 98*d39a76e7Sxw 99*d39a76e7Sxw /* Convenience MDIO read/write wrappers */ 100*d39a76e7Sxw static inline int mdio_read(struct cphy *cphy, int mmd, int reg, 101*d39a76e7Sxw unsigned int *valp) 102*d39a76e7Sxw { 103*d39a76e7Sxw return cphy->mdio_read(cphy->adapter, cphy->addr, mmd, reg, valp); 104*d39a76e7Sxw } 105*d39a76e7Sxw 106*d39a76e7Sxw static inline int mdio_write(struct cphy *cphy, int mmd, int reg, 107*d39a76e7Sxw unsigned int val) 108*d39a76e7Sxw { 109*d39a76e7Sxw return cphy->mdio_write(cphy->adapter, cphy->addr, mmd, reg, val); 110*d39a76e7Sxw } 111*d39a76e7Sxw 112*d39a76e7Sxw static inline int simple_mdio_read(struct cphy *cphy, int reg, 113*d39a76e7Sxw unsigned int *valp) 114*d39a76e7Sxw { 115*d39a76e7Sxw return mdio_read(cphy, 0, reg, valp); 116*d39a76e7Sxw } 117*d39a76e7Sxw 118*d39a76e7Sxw static inline int simple_mdio_write(struct cphy *cphy, int reg, 119*d39a76e7Sxw unsigned int val) 120*d39a76e7Sxw { 121*d39a76e7Sxw return mdio_write(cphy, 0, reg, val); 122*d39a76e7Sxw } 123*d39a76e7Sxw 124*d39a76e7Sxw /* Convenience initializer */ 125*d39a76e7Sxw static inline void cphy_init(struct cphy *phy, adapter_t *adapter, 126*d39a76e7Sxw int phy_addr, struct cphy_ops *phy_ops, 127*d39a76e7Sxw struct mdio_ops *mdio_ops) 128*d39a76e7Sxw { 129*d39a76e7Sxw phy->adapter = adapter; 130*d39a76e7Sxw phy->addr = phy_addr; 131*d39a76e7Sxw phy->ops = phy_ops; 132*d39a76e7Sxw if (mdio_ops) { 133*d39a76e7Sxw phy->mdio_read = mdio_ops->read; 134*d39a76e7Sxw phy->mdio_write = mdio_ops->write; 135*d39a76e7Sxw } 136*d39a76e7Sxw } 137*d39a76e7Sxw 138*d39a76e7Sxw /* Operations of the PHY-instance factory */ 139*d39a76e7Sxw struct gphy { 140*d39a76e7Sxw /* Construct a PHY instance with the given PHY address */ 141*d39a76e7Sxw struct cphy *(*create)(adapter_t *adapter, int phy_addr, 142*d39a76e7Sxw struct mdio_ops *mdio_ops); 143*d39a76e7Sxw 144*d39a76e7Sxw /* 145*d39a76e7Sxw * Reset the PHY chip. This resets the whole PHY chip, not individual 146*d39a76e7Sxw * ports. 147*d39a76e7Sxw */ 148*d39a76e7Sxw int (*reset)(adapter_t *adapter); 149*d39a76e7Sxw }; 150*d39a76e7Sxw 151*d39a76e7Sxw extern struct gphy t1_my3126_ops; 152*d39a76e7Sxw extern struct gphy t1_mv88e1xxx_ops; 153*d39a76e7Sxw extern struct gphy t1_xpak_ops; 154*d39a76e7Sxw extern struct gphy t1_mv88x201x_ops; 155*d39a76e7Sxw extern struct gphy t1_dummy_phy_ops; 156*d39a76e7Sxw #endif 157