1*d39a76e7Sxw /* 2*d39a76e7Sxw * CDDL HEADER START 3*d39a76e7Sxw * 4*d39a76e7Sxw * The contents of this file are subject to the terms of the 5*d39a76e7Sxw * Common Development and Distribution License (the "License"). 6*d39a76e7Sxw * You may not use this file except in compliance with the License. 7*d39a76e7Sxw * 8*d39a76e7Sxw * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*d39a76e7Sxw * or http://www.opensolaris.org/os/licensing. 10*d39a76e7Sxw * See the License for the specific language governing permissions 11*d39a76e7Sxw * and limitations under the License. 12*d39a76e7Sxw * 13*d39a76e7Sxw * When distributing Covered Code, include this CDDL HEADER in each 14*d39a76e7Sxw * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*d39a76e7Sxw * If applicable, add the following below this CDDL HEADER, with the 16*d39a76e7Sxw * fields enclosed by brackets "[]" replaced with your own identifying 17*d39a76e7Sxw * information: Portions Copyright [yyyy] [name of copyright owner] 18*d39a76e7Sxw * 19*d39a76e7Sxw * CDDL HEADER END 20*d39a76e7Sxw */ 21*d39a76e7Sxw 22*d39a76e7Sxw /* 23*d39a76e7Sxw * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24*d39a76e7Sxw */ 25*d39a76e7Sxw 26*d39a76e7Sxw #ifndef CHELSIO_T1_COMPAT_H 27*d39a76e7Sxw #define CHELSIO_T1_COMPAT_H 28*d39a76e7Sxw 29*d39a76e7Sxw #ifndef ETH_ALEN 30*d39a76e7Sxw #define ETH_ALEN 6 31*d39a76e7Sxw #endif 32*d39a76e7Sxw 33*d39a76e7Sxw /* MAC and PHY link speeds */ 34*d39a76e7Sxw enum { SPEED_10, SPEED_100, SPEED_1000, SPEED_10000 }; 35*d39a76e7Sxw 36*d39a76e7Sxw /* MAC and PHY link duplex */ 37*d39a76e7Sxw enum { DUPLEX_HALF, DUPLEX_FULL }; 38*d39a76e7Sxw 39*d39a76e7Sxw /* Autonegotiation settings */ 40*d39a76e7Sxw enum { AUTONEG_DISABLE, AUTONEG_ENABLE }; 41*d39a76e7Sxw 42*d39a76e7Sxw #ifndef MII_BMCR 43*d39a76e7Sxw 44*d39a76e7Sxw /* Generic MII registers and register fields. */ 45*d39a76e7Sxw #define MII_BMCR 0x00 /* Basic mode control register */ 46*d39a76e7Sxw #define MII_BMSR 0x01 /* Basic mode status register */ 47*d39a76e7Sxw #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 48*d39a76e7Sxw #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 49*d39a76e7Sxw #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 50*d39a76e7Sxw #define MII_LPA 0x05 /* Link partner ability reg */ 51*d39a76e7Sxw 52*d39a76e7Sxw /* Basic mode control register. */ 53*d39a76e7Sxw #define BMCR_RESV 0x007f /* Unused... */ 54*d39a76e7Sxw #define BMCR_CTST 0x0080 /* Collision test */ 55*d39a76e7Sxw #define BMCR_FULLDPLX 0x0100 /* Full duplex */ 56*d39a76e7Sxw #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ 57*d39a76e7Sxw #define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ 58*d39a76e7Sxw #define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ 59*d39a76e7Sxw #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 60*d39a76e7Sxw #define BMCR_SPEED100 0x2000 /* Select 100Mbps */ 61*d39a76e7Sxw #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 62*d39a76e7Sxw #define BMCR_RESET 0x8000 /* Reset the DP83840 */ 63*d39a76e7Sxw 64*d39a76e7Sxw /* Basic mode status register. */ 65*d39a76e7Sxw #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 66*d39a76e7Sxw #define BMSR_JCD 0x0002 /* Jabber detected */ 67*d39a76e7Sxw #define BMSR_LSTATUS 0x0004 /* Link status */ 68*d39a76e7Sxw #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 69*d39a76e7Sxw #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 70*d39a76e7Sxw #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 71*d39a76e7Sxw #define BMSR_RESV 0x07c0 /* Unused... */ 72*d39a76e7Sxw #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 73*d39a76e7Sxw #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 74*d39a76e7Sxw #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 75*d39a76e7Sxw #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 76*d39a76e7Sxw #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 77*d39a76e7Sxw 78*d39a76e7Sxw /* Advertisement control register. */ 79*d39a76e7Sxw #define ADVERTISE_SLCT 0x001f /* Selector bits */ 80*d39a76e7Sxw #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 81*d39a76e7Sxw #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 82*d39a76e7Sxw #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 83*d39a76e7Sxw #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 84*d39a76e7Sxw #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 85*d39a76e7Sxw #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 86*d39a76e7Sxw #define ADVERTISE_RESV 0x1c00 /* Unused... */ 87*d39a76e7Sxw #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 88*d39a76e7Sxw #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ 89*d39a76e7Sxw #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 90*d39a76e7Sxw #endif 91*d39a76e7Sxw 92*d39a76e7Sxw /* MAC and PHY supported features */ 93*d39a76e7Sxw #define SUPPORTED_10baseT_Half (1 << 0) 94*d39a76e7Sxw #define SUPPORTED_10baseT_Full (1 << 1) 95*d39a76e7Sxw #define SUPPORTED_100baseT_Half (1 << 2) 96*d39a76e7Sxw #define SUPPORTED_100baseT_Full (1 << 3) 97*d39a76e7Sxw #define SUPPORTED_1000baseT_Half (1 << 4) 98*d39a76e7Sxw #define SUPPORTED_1000baseT_Full (1 << 5) 99*d39a76e7Sxw #define SUPPORTED_10000baseT_Full (1 << 6) 100*d39a76e7Sxw #define SUPPORTED_Autoneg (1 << 7) 101*d39a76e7Sxw #define SUPPORTED_TP (1 << 8) 102*d39a76e7Sxw #define SUPPORTED_FIBRE (1 << 9) 103*d39a76e7Sxw #define SUPPORTED_PAUSE (1 << 10) 104*d39a76e7Sxw #define SUPPORTED_LOOPBACK (1 << 11) 105*d39a76e7Sxw 106*d39a76e7Sxw /* Features advertised by PHY */ 107*d39a76e7Sxw #define ADVERTISED_10baseT_Half (1 << 0) 108*d39a76e7Sxw #define ADVERTISED_10baseT_Full (1 << 1) 109*d39a76e7Sxw #define ADVERTISED_100baseT_Half (1 << 2) 110*d39a76e7Sxw #define ADVERTISED_100baseT_Full (1 << 3) 111*d39a76e7Sxw #define ADVERTISED_1000baseT_Half (1 << 4) 112*d39a76e7Sxw #define ADVERTISED_1000baseT_Full (1 << 5) 113*d39a76e7Sxw #define ADVERTISED_10000baseT_Full (1 << 6) 114*d39a76e7Sxw #define ADVERTISED_Autoneg (1 << 7) 115*d39a76e7Sxw #define ADVERTISED_PAUSE (1 << 10) 116*d39a76e7Sxw #define ADVERTISED_ASYM_PAUSE (1 << 12) 117*d39a76e7Sxw 118*d39a76e7Sxw /* diagnostic message categories */ 119*d39a76e7Sxw enum { LINK = 1, INTR = 2, HW = 4 }; 120*d39a76e7Sxw 121*d39a76e7Sxw /* diagnostic message levels */ 122*d39a76e7Sxw /* enum { INFO, DEBUG }; */ 123*d39a76e7Sxw 124*d39a76e7Sxw #ifndef __devinit 125*d39a76e7Sxw #define __devinit 126*d39a76e7Sxw #endif 127*d39a76e7Sxw 128*d39a76e7Sxw #ifndef CH_DEVICE 129*d39a76e7Sxw struct pci_device_id { 130*d39a76e7Sxw unsigned short devid; 131*d39a76e7Sxw unsigned short ssid; 132*d39a76e7Sxw unsigned short board_info_index; 133*d39a76e7Sxw }; 134*d39a76e7Sxw 135*d39a76e7Sxw #define CH_DEVICE_COMMON(devid, ssid, idx) { devid, ssid, idx } 136*d39a76e7Sxw #define CH_DEVICE(devid, ssid, idx) CH_DEVICE_COMMON(devid, ssid, idx) 137*d39a76e7Sxw #endif 138*d39a76e7Sxw 139*d39a76e7Sxw #endif 140