1d14abf15SRobert Mustacchi #ifndef __shmem_h__ 2d14abf15SRobert Mustacchi #define __shmem_h__ 3d14abf15SRobert Mustacchi 4d14abf15SRobert Mustacchi #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 5d14abf15SRobert Mustacchi #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 6d14abf15SRobert Mustacchi #endif 7d14abf15SRobert Mustacchi 8d14abf15SRobert Mustacchi #define FUNC_0 0 9d14abf15SRobert Mustacchi #define FUNC_1 1 10d14abf15SRobert Mustacchi #define FUNC_2 2 11d14abf15SRobert Mustacchi #define FUNC_3 3 12d14abf15SRobert Mustacchi #define FUNC_4 4 13d14abf15SRobert Mustacchi #define FUNC_5 5 14d14abf15SRobert Mustacchi #define FUNC_6 6 15d14abf15SRobert Mustacchi #define FUNC_7 7 16d14abf15SRobert Mustacchi #define E1_FUNC_MAX 2 17d14abf15SRobert Mustacchi #define E1H_FUNC_MAX 8 18d14abf15SRobert Mustacchi #define E2_FUNC_MAX 4 /* per path */ 19d14abf15SRobert Mustacchi 20d14abf15SRobert Mustacchi #define VN_0 0 21d14abf15SRobert Mustacchi #define VN_1 1 22d14abf15SRobert Mustacchi #define VN_2 2 23d14abf15SRobert Mustacchi #define VN_3 3 24d14abf15SRobert Mustacchi #define E1VN_MAX 1 25d14abf15SRobert Mustacchi #define E1HVN_MAX 4 26d14abf15SRobert Mustacchi 27d14abf15SRobert Mustacchi #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 28d14abf15SRobert Mustacchi /* This value (in milliseconds) determines the frequency of the driver 29d14abf15SRobert Mustacchi * issuing the PULSE message code. The firmware monitors this periodic 30d14abf15SRobert Mustacchi * pulse to determine when to switch to an OS-absent mode. */ 31d14abf15SRobert Mustacchi #define DRV_PULSE_PERIOD_MS 250 32d14abf15SRobert Mustacchi 33d14abf15SRobert Mustacchi /* This value (in milliseconds) determines how long the driver should 34d14abf15SRobert Mustacchi * wait for an acknowledgement from the firmware before timing out. Once 35d14abf15SRobert Mustacchi * the firmware has timed out, the driver will assume there is no firmware 36d14abf15SRobert Mustacchi * running and there won't be any firmware-driver synchronization during a 37d14abf15SRobert Mustacchi * driver reset. */ 38d14abf15SRobert Mustacchi #define FW_ACK_TIME_OUT_MS 5000 39d14abf15SRobert Mustacchi 40d14abf15SRobert Mustacchi #define FW_ACK_POLL_TIME_MS 1 41d14abf15SRobert Mustacchi 42d14abf15SRobert Mustacchi #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 43d14abf15SRobert Mustacchi 44d14abf15SRobert Mustacchi #define MFW_TRACE_SIGNATURE 0x54524342 45d14abf15SRobert Mustacchi 46d14abf15SRobert Mustacchi /**************************************************************************** 47d14abf15SRobert Mustacchi * Driver <-> FW Mailbox * 48d14abf15SRobert Mustacchi ****************************************************************************/ 49d14abf15SRobert Mustacchi struct drv_port_mb { 50d14abf15SRobert Mustacchi 51d14abf15SRobert Mustacchi u32 link_status; 52d14abf15SRobert Mustacchi /* Driver should update this field on any link change event */ 53d14abf15SRobert Mustacchi 54d14abf15SRobert Mustacchi #define LINK_STATUS_NONE (0<<0) 55d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 56d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_UP 0x00000001 57d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 58d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 59d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 60d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 61d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 62d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 63d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 64d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 65d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 66d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 67d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 68d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 69d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 70d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 71d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 72d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 73d14abf15SRobert Mustacchi #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 74d14abf15SRobert Mustacchi 75d14abf15SRobert Mustacchi #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 76d14abf15SRobert Mustacchi #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 77d14abf15SRobert Mustacchi 78d14abf15SRobert Mustacchi #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 79d14abf15SRobert Mustacchi #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 80d14abf15SRobert Mustacchi #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 81d14abf15SRobert Mustacchi 82d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 83d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 84d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 85d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 86d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 87d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 88d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 89d14abf15SRobert Mustacchi 90d14abf15SRobert Mustacchi #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 91d14abf15SRobert Mustacchi #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 92d14abf15SRobert Mustacchi 93d14abf15SRobert Mustacchi #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 94d14abf15SRobert Mustacchi #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 95d14abf15SRobert Mustacchi 96d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 97d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 98d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 99d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 100d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 101d14abf15SRobert Mustacchi 102d14abf15SRobert Mustacchi #define LINK_STATUS_SERDES_LINK 0x00100000 103d14abf15SRobert Mustacchi 104d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 105d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 106d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 107d14abf15SRobert Mustacchi #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 108d14abf15SRobert Mustacchi 109d14abf15SRobert Mustacchi #define LINK_STATUS_PFC_ENABLED 0x20000000 110d14abf15SRobert Mustacchi 111d14abf15SRobert Mustacchi #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 112d14abf15SRobert Mustacchi #define LINK_STATUS_SFP_TX_FAULT 0x80000000 113d14abf15SRobert Mustacchi 114d14abf15SRobert Mustacchi u32 port_stx; 115d14abf15SRobert Mustacchi 116d14abf15SRobert Mustacchi u32 stat_nig_timer; 117d14abf15SRobert Mustacchi 118d14abf15SRobert Mustacchi /* MCP firmware does not use this field */ 119d14abf15SRobert Mustacchi u32 ext_phy_fw_version; 120d14abf15SRobert Mustacchi 121d14abf15SRobert Mustacchi }; 122d14abf15SRobert Mustacchi 123d14abf15SRobert Mustacchi 124d14abf15SRobert Mustacchi struct drv_func_mb { 125d14abf15SRobert Mustacchi 126d14abf15SRobert Mustacchi u32 drv_mb_header; 127d14abf15SRobert Mustacchi #define DRV_MSG_CODE_MASK 0xffff0000 128d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LOAD_REQ 0x10000000 129d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LOAD_DONE 0x11000000 130d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 131d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 132d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 133d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 134d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DCC_OK 0x30000000 135d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 136d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 137d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 138d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 139d14abf15SRobert Mustacchi #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 140d14abf15SRobert Mustacchi #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 141d14abf15SRobert Mustacchi #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 142d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 143d14abf15SRobert Mustacchi #define DRV_MSG_CODE_OEM_OK 0x00010000 144d14abf15SRobert Mustacchi #define DRV_MSG_CODE_OEM_FAILURE 0x00020000 145d14abf15SRobert Mustacchi #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000 146d14abf15SRobert Mustacchi #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000 147d14abf15SRobert Mustacchi /* 148d14abf15SRobert Mustacchi * The optic module verification command requires bootcode 149d14abf15SRobert Mustacchi * v5.0.6 or later, te specific optic module verification command 150d14abf15SRobert Mustacchi * requires bootcode v5.2.12 or later 151d14abf15SRobert Mustacchi */ 152d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 153d14abf15SRobert Mustacchi #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 154d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 155d14abf15SRobert Mustacchi #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 156d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 157d14abf15SRobert Mustacchi #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 158d14abf15SRobert Mustacchi #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 159d14abf15SRobert Mustacchi #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 160d14abf15SRobert Mustacchi #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 161d14abf15SRobert Mustacchi #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 162d14abf15SRobert Mustacchi 163d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 164d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 165d14abf15SRobert Mustacchi #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 166d14abf15SRobert Mustacchi 167d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 168d14abf15SRobert Mustacchi 169d14abf15SRobert Mustacchi #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 170d14abf15SRobert Mustacchi #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 171d14abf15SRobert Mustacchi #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 172d14abf15SRobert Mustacchi #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 173d14abf15SRobert Mustacchi #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 174d14abf15SRobert Mustacchi 175d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 176d14abf15SRobert Mustacchi #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 177d14abf15SRobert Mustacchi 178d14abf15SRobert Mustacchi #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 179d14abf15SRobert Mustacchi 180d14abf15SRobert Mustacchi #define DRV_MSG_CODE_RMMOD 0xdb000000 181d14abf15SRobert Mustacchi #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 182d14abf15SRobert Mustacchi 183d14abf15SRobert Mustacchi #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 184d14abf15SRobert Mustacchi #define REQ_BC_VER_4_SET_MF_BW 0x00060202 185d14abf15SRobert Mustacchi #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 186d14abf15SRobert Mustacchi 187d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 188d14abf15SRobert Mustacchi 189d14abf15SRobert Mustacchi #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 190d14abf15SRobert Mustacchi #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 191d14abf15SRobert Mustacchi 192d14abf15SRobert Mustacchi #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 193d14abf15SRobert Mustacchi #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 194d14abf15SRobert Mustacchi #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 195d14abf15SRobert Mustacchi #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 196d14abf15SRobert Mustacchi 197d14abf15SRobert Mustacchi #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 198d14abf15SRobert Mustacchi #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 199d14abf15SRobert Mustacchi 200d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000 201d14abf15SRobert Mustacchi 202d14abf15SRobert Mustacchi #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 203d14abf15SRobert Mustacchi 204d14abf15SRobert Mustacchi u32 drv_mb_param; 205d14abf15SRobert Mustacchi #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 206d14abf15SRobert Mustacchi #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 207d14abf15SRobert Mustacchi 208d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 209d14abf15SRobert Mustacchi #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 210d14abf15SRobert Mustacchi 211d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 212d14abf15SRobert Mustacchi #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 213d14abf15SRobert Mustacchi 214d14abf15SRobert Mustacchi #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 215d14abf15SRobert Mustacchi #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002 216d14abf15SRobert Mustacchi #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003 217d14abf15SRobert Mustacchi 218d14abf15SRobert Mustacchi u32 fw_mb_header; 219d14abf15SRobert Mustacchi #define FW_MSG_CODE_MASK 0xffff0000 220d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 221d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 222d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 223d14abf15SRobert Mustacchi /* Load common chip is supported from bc 6.0.0 */ 224d14abf15SRobert Mustacchi #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 225d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 226d14abf15SRobert Mustacchi 227d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 228d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 229d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 230d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 231d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 232d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 233d14abf15SRobert Mustacchi #define FW_MSG_CODE_DCC_DONE 0x30100000 234d14abf15SRobert Mustacchi #define FW_MSG_CODE_LLDP_DONE 0x40100000 235d14abf15SRobert Mustacchi #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 236d14abf15SRobert Mustacchi #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 237d14abf15SRobert Mustacchi #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 238d14abf15SRobert Mustacchi #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 239d14abf15SRobert Mustacchi #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 240d14abf15SRobert Mustacchi #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 241d14abf15SRobert Mustacchi #define FW_MSG_CODE_NO_KEY 0x80f00000 242d14abf15SRobert Mustacchi #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 243d14abf15SRobert Mustacchi #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 244d14abf15SRobert Mustacchi #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 245d14abf15SRobert Mustacchi #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 246d14abf15SRobert Mustacchi #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 247d14abf15SRobert Mustacchi #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 248d14abf15SRobert Mustacchi #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 249d14abf15SRobert Mustacchi #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 250d14abf15SRobert Mustacchi #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 251d14abf15SRobert Mustacchi #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 252d14abf15SRobert Mustacchi #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 253d14abf15SRobert Mustacchi 254d14abf15SRobert Mustacchi #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 255d14abf15SRobert Mustacchi #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 256d14abf15SRobert Mustacchi #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 257d14abf15SRobert Mustacchi #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 258d14abf15SRobert Mustacchi #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 259d14abf15SRobert Mustacchi 260d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 261d14abf15SRobert Mustacchi #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 262d14abf15SRobert Mustacchi 263d14abf15SRobert Mustacchi #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 264d14abf15SRobert Mustacchi 265d14abf15SRobert Mustacchi #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 266d14abf15SRobert Mustacchi 267d14abf15SRobert Mustacchi #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 268d14abf15SRobert Mustacchi #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 269d14abf15SRobert Mustacchi 270d14abf15SRobert Mustacchi #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 271d14abf15SRobert Mustacchi 272d14abf15SRobert Mustacchi #define FW_MSG_CODE_FLR_ACK 0x02000000 273d14abf15SRobert Mustacchi #define FW_MSG_CODE_FLR_NACK 0x02100000 274d14abf15SRobert Mustacchi 275d14abf15SRobert Mustacchi #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 276d14abf15SRobert Mustacchi #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 277d14abf15SRobert Mustacchi #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 278d14abf15SRobert Mustacchi #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 279d14abf15SRobert Mustacchi 280d14abf15SRobert Mustacchi #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 281d14abf15SRobert Mustacchi #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 282d14abf15SRobert Mustacchi 283d14abf15SRobert Mustacchi #define FW_MSG_CODE_OEM_ACK 0x00010000 284d14abf15SRobert Mustacchi #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000 285d14abf15SRobert Mustacchi 286d14abf15SRobert Mustacchi #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 287d14abf15SRobert Mustacchi 288d14abf15SRobert Mustacchi u32 fw_mb_param; 289d14abf15SRobert Mustacchi 290d14abf15SRobert Mustacchi #define FW_PARAM_INVALID_IMG 0xffffffff 291d14abf15SRobert Mustacchi 292d14abf15SRobert Mustacchi u32 drv_pulse_mb; 293d14abf15SRobert Mustacchi #define DRV_PULSE_SEQ_MASK 0x00007fff 294d14abf15SRobert Mustacchi #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 295d14abf15SRobert Mustacchi /* 296d14abf15SRobert Mustacchi * The system time is in the format of 297d14abf15SRobert Mustacchi * (year-2001)*12*32 + month*32 + day. 298d14abf15SRobert Mustacchi */ 299d14abf15SRobert Mustacchi #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 300d14abf15SRobert Mustacchi /* 301d14abf15SRobert Mustacchi * Indicate to the firmware not to go into the 302d14abf15SRobert Mustacchi * OS-absent when it is not getting driver pulse. 303d14abf15SRobert Mustacchi * This is used for debugging as well for PXE(MBA). 304d14abf15SRobert Mustacchi */ 305d14abf15SRobert Mustacchi 306d14abf15SRobert Mustacchi u32 mcp_pulse_mb; 307d14abf15SRobert Mustacchi #define MCP_PULSE_SEQ_MASK 0x00007fff 308d14abf15SRobert Mustacchi #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 309d14abf15SRobert Mustacchi /* Indicates to the driver not to assert due to lack 310d14abf15SRobert Mustacchi * of MCP response */ 311d14abf15SRobert Mustacchi #define MCP_EVENT_MASK 0xffff0000 312d14abf15SRobert Mustacchi #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 313d14abf15SRobert Mustacchi 314d14abf15SRobert Mustacchi u32 iscsi_boot_signature; 315d14abf15SRobert Mustacchi u32 iscsi_boot_block_offset; 316d14abf15SRobert Mustacchi 317d14abf15SRobert Mustacchi u32 drv_status; 318d14abf15SRobert Mustacchi #define DRV_STATUS_PMF 0x00000001 319d14abf15SRobert Mustacchi #define DRV_STATUS_VF_DISABLED 0x00000002 320d14abf15SRobert Mustacchi #define DRV_STATUS_SET_MF_BW 0x00000004 321d14abf15SRobert Mustacchi #define DRV_STATUS_LINK_EVENT 0x00000008 322d14abf15SRobert Mustacchi 323d14abf15SRobert Mustacchi #define DRV_STATUS_OEM_EVENT_MASK 0x00000070 324d14abf15SRobert Mustacchi #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010 325d14abf15SRobert Mustacchi #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020 326d14abf15SRobert Mustacchi 327d14abf15SRobert Mustacchi #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080 328d14abf15SRobert Mustacchi 329d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 330d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 331d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 332d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 333d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_RESERVED1 0x00000800 334d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 335d14abf15SRobert Mustacchi #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 336d14abf15SRobert Mustacchi 337d14abf15SRobert Mustacchi #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 338d14abf15SRobert Mustacchi #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 339d14abf15SRobert Mustacchi #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 340d14abf15SRobert Mustacchi #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 341d14abf15SRobert Mustacchi #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 342d14abf15SRobert Mustacchi #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 343d14abf15SRobert Mustacchi #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 344d14abf15SRobert Mustacchi 345d14abf15SRobert Mustacchi #define DRV_STATUS_DRV_INFO_REQ 0x04000000 346d14abf15SRobert Mustacchi 347d14abf15SRobert Mustacchi #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 348d14abf15SRobert Mustacchi 349d14abf15SRobert Mustacchi u32 virt_mac_upper; 350d14abf15SRobert Mustacchi #define VIRT_MAC_SIGN_MASK 0xffff0000 351d14abf15SRobert Mustacchi #define VIRT_MAC_SIGNATURE 0x564d0000 352d14abf15SRobert Mustacchi u32 virt_mac_lower; 353d14abf15SRobert Mustacchi 354d14abf15SRobert Mustacchi }; 355d14abf15SRobert Mustacchi 356d14abf15SRobert Mustacchi 357d14abf15SRobert Mustacchi /**************************************************************************** 358d14abf15SRobert Mustacchi * Management firmware state * 359d14abf15SRobert Mustacchi ****************************************************************************/ 360d14abf15SRobert Mustacchi /* Allocate 440 bytes for management firmware */ 361d14abf15SRobert Mustacchi #define MGMTFW_STATE_WORD_SIZE 110 362d14abf15SRobert Mustacchi 363d14abf15SRobert Mustacchi struct mgmtfw_state { 364d14abf15SRobert Mustacchi u32 opaque[MGMTFW_STATE_WORD_SIZE]; 365d14abf15SRobert Mustacchi }; 366d14abf15SRobert Mustacchi 367d14abf15SRobert Mustacchi 368d14abf15SRobert Mustacchi /**************************************************************************** 369d14abf15SRobert Mustacchi * Multi-Function configuration * 370d14abf15SRobert Mustacchi ****************************************************************************/ 371d14abf15SRobert Mustacchi struct shared_mf_cfg { 372d14abf15SRobert Mustacchi 373d14abf15SRobert Mustacchi u32 clp_mb; 374d14abf15SRobert Mustacchi #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 375d14abf15SRobert Mustacchi /* set by CLP */ 376d14abf15SRobert Mustacchi #define SHARED_MF_CLP_EXIT 0x00000001 377d14abf15SRobert Mustacchi /* set by MCP */ 378d14abf15SRobert Mustacchi #define SHARED_MF_CLP_EXIT_DONE 0x00010000 379d14abf15SRobert Mustacchi 380d14abf15SRobert Mustacchi }; 381d14abf15SRobert Mustacchi 382d14abf15SRobert Mustacchi struct port_mf_cfg { 383d14abf15SRobert Mustacchi 384d14abf15SRobert Mustacchi u32 dynamic_cfg; /* device control channel */ 385d14abf15SRobert Mustacchi #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 386d14abf15SRobert Mustacchi #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 387d14abf15SRobert Mustacchi #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 388d14abf15SRobert Mustacchi 389d14abf15SRobert Mustacchi u32 reserved[1]; 390d14abf15SRobert Mustacchi 391d14abf15SRobert Mustacchi }; 392d14abf15SRobert Mustacchi 393d14abf15SRobert Mustacchi struct func_mf_cfg { 394d14abf15SRobert Mustacchi 395d14abf15SRobert Mustacchi u32 config; 396d14abf15SRobert Mustacchi /* E/R/I/D */ 397d14abf15SRobert Mustacchi /* function 0 of each port cannot be hidden */ 398d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 399d14abf15SRobert Mustacchi 400d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 401d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 402d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 403d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 404d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 405d14abf15SRobert Mustacchi #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 406d14abf15SRobert Mustacchi FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 407d14abf15SRobert Mustacchi 408d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 409d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 410d14abf15SRobert Mustacchi 411d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 412d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 413d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 414d14abf15SRobert Mustacchi #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 415d14abf15SRobert Mustacchi 416d14abf15SRobert Mustacchi /* PRI */ 417d14abf15SRobert Mustacchi /* 0 - low priority, 3 - high priority */ 418d14abf15SRobert Mustacchi #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 419d14abf15SRobert Mustacchi #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 420d14abf15SRobert Mustacchi #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 421d14abf15SRobert Mustacchi 422d14abf15SRobert Mustacchi /* MINBW, MAXBW */ 423d14abf15SRobert Mustacchi /* value range - 0..100, increments in 100Mbps */ 424d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 425d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MIN_BW_SHIFT 16 426d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 427d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 428d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MAX_BW_SHIFT 24 429d14abf15SRobert Mustacchi #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 430d14abf15SRobert Mustacchi 431d14abf15SRobert Mustacchi u32 mac_upper; /* MAC */ 432d14abf15SRobert Mustacchi #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 433d14abf15SRobert Mustacchi #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 434d14abf15SRobert Mustacchi #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 435d14abf15SRobert Mustacchi u32 mac_lower; 436d14abf15SRobert Mustacchi #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 437d14abf15SRobert Mustacchi 438d14abf15SRobert Mustacchi u32 e1hov_tag; /* VNI */ 439d14abf15SRobert Mustacchi #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 440d14abf15SRobert Mustacchi #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 441d14abf15SRobert Mustacchi #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 442d14abf15SRobert Mustacchi 443d14abf15SRobert Mustacchi /* afex default VLAN ID - 12 bits */ 444d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 445d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 446d14abf15SRobert Mustacchi 447d14abf15SRobert Mustacchi u32 afex_config; 448d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 449d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 450d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 451d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 452d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 453d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 454d14abf15SRobert Mustacchi #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 455d14abf15SRobert Mustacchi 456d14abf15SRobert Mustacchi u32 pf_allocation; 457d14abf15SRobert Mustacchi /* number of vfs in function, if 0 - sriov disabled */ 458d14abf15SRobert Mustacchi #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 459d14abf15SRobert Mustacchi #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 460d14abf15SRobert Mustacchi }; 461d14abf15SRobert Mustacchi 462d14abf15SRobert Mustacchi enum mf_cfg_afex_vlan_mode { 463d14abf15SRobert Mustacchi FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 464d14abf15SRobert Mustacchi FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 465d14abf15SRobert Mustacchi FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 466d14abf15SRobert Mustacchi }; 467d14abf15SRobert Mustacchi 468d14abf15SRobert Mustacchi /* This structure is not applicable and should not be accessed on 57711 */ 469d14abf15SRobert Mustacchi struct func_ext_cfg { 470d14abf15SRobert Mustacchi u32 func_cfg; 471d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 472d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_SHIFT 0 473d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 474d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 475d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 476d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 477d14abf15SRobert Mustacchi #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 478d14abf15SRobert Mustacchi 479d14abf15SRobert Mustacchi u32 iscsi_mac_addr_upper; 480d14abf15SRobert Mustacchi u32 iscsi_mac_addr_lower; 481d14abf15SRobert Mustacchi 482d14abf15SRobert Mustacchi u32 fcoe_mac_addr_upper; 483d14abf15SRobert Mustacchi u32 fcoe_mac_addr_lower; 484d14abf15SRobert Mustacchi 485d14abf15SRobert Mustacchi u32 fcoe_wwn_port_name_upper; 486d14abf15SRobert Mustacchi u32 fcoe_wwn_port_name_lower; 487d14abf15SRobert Mustacchi 488d14abf15SRobert Mustacchi u32 fcoe_wwn_node_name_upper; 489d14abf15SRobert Mustacchi u32 fcoe_wwn_node_name_lower; 490d14abf15SRobert Mustacchi 491d14abf15SRobert Mustacchi u32 preserve_data; 492d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 493d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 494d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 495d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 496d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 497d14abf15SRobert Mustacchi #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 498d14abf15SRobert Mustacchi }; 499d14abf15SRobert Mustacchi 500d14abf15SRobert Mustacchi struct mf_cfg { 501d14abf15SRobert Mustacchi 502d14abf15SRobert Mustacchi struct shared_mf_cfg shared_mf_config; /* 0x4 */ 503d14abf15SRobert Mustacchi struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 504d14abf15SRobert Mustacchi /* 0x10*2=0x20 */ 505d14abf15SRobert Mustacchi /* for all chips, there are 8 mf functions */ 506d14abf15SRobert Mustacchi struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 507d14abf15SRobert Mustacchi /* 508d14abf15SRobert Mustacchi * Extended configuration per function - this array does not exist and 509d14abf15SRobert Mustacchi * should not be accessed on 57711 510d14abf15SRobert Mustacchi */ 511d14abf15SRobert Mustacchi struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 512d14abf15SRobert Mustacchi }; /* 0x224 */ 513d14abf15SRobert Mustacchi 514d14abf15SRobert Mustacchi /**************************************************************************** 515d14abf15SRobert Mustacchi * Shared Memory Region * 516d14abf15SRobert Mustacchi ****************************************************************************/ 517d14abf15SRobert Mustacchi struct shmem_region { /* SharedMem Offset (size) */ 518d14abf15SRobert Mustacchi 519d14abf15SRobert Mustacchi u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 520d14abf15SRobert Mustacchi #define SHR_MEM_FORMAT_REV_MASK 0xff000000 521d14abf15SRobert Mustacchi #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 522d14abf15SRobert Mustacchi /* validity bits */ 523d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 524d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_MB 0x00200000 525d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 526d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_RESERVED 0x00000007 527d14abf15SRobert Mustacchi /* One licensing bit should be set */ 528d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 529d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 530d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 531d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 532d14abf15SRobert Mustacchi /* Active MFW */ 533d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 534d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 535d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 536d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 537d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 538d14abf15SRobert Mustacchi #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 539d14abf15SRobert Mustacchi 540d14abf15SRobert Mustacchi struct shm_dev_info dev_info; /* 0x8 (0x438) */ 541d14abf15SRobert Mustacchi 542d14abf15SRobert Mustacchi license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 543d14abf15SRobert Mustacchi 544d14abf15SRobert Mustacchi /* FW information (for internal FW use) */ 545d14abf15SRobert Mustacchi u32 fw_info_fio_offset; /* 0x4a8 (0x4) */ 546d14abf15SRobert Mustacchi struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 547d14abf15SRobert Mustacchi 548d14abf15SRobert Mustacchi struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 549d14abf15SRobert Mustacchi 550d14abf15SRobert Mustacchi 551d14abf15SRobert Mustacchi #ifdef BMAPI 552d14abf15SRobert Mustacchi /* This is a variable length array */ 553d14abf15SRobert Mustacchi /* the number of function depends on the chip type */ 554d14abf15SRobert Mustacchi struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 555d14abf15SRobert Mustacchi #else 556d14abf15SRobert Mustacchi /* the number of function depends on the chip type */ 557d14abf15SRobert Mustacchi struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 558d14abf15SRobert Mustacchi #endif /* BMAPI */ 559d14abf15SRobert Mustacchi 560d14abf15SRobert Mustacchi }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 561d14abf15SRobert Mustacchi 562d14abf15SRobert Mustacchi /**************************************************************************** 563d14abf15SRobert Mustacchi * Shared Memory 2 Region * 564d14abf15SRobert Mustacchi ****************************************************************************/ 565d14abf15SRobert Mustacchi /* The fw_flr_ack is actually built in the following way: */ 566d14abf15SRobert Mustacchi /* 8 bit: PF ack */ 567d14abf15SRobert Mustacchi /* 64 bit: VF ack */ 568d14abf15SRobert Mustacchi /* 8 bit: ios_dis_ack */ 569d14abf15SRobert Mustacchi /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 570d14abf15SRobert Mustacchi /* u32. The fw must have the VF right after the PF since this is how it */ 571d14abf15SRobert Mustacchi /* access arrays(it expects always the VF to reside after the PF, and that */ 572d14abf15SRobert Mustacchi /* makes the calculation much easier for it. ) */ 573d14abf15SRobert Mustacchi /* In order to answer both limitations, and keep the struct small, the code */ 574d14abf15SRobert Mustacchi /* will abuse the structure defined here to achieve the actual partition */ 575d14abf15SRobert Mustacchi /* above */ 576d14abf15SRobert Mustacchi /****************************************************************************/ 577d14abf15SRobert Mustacchi struct fw_flr_ack { 578d14abf15SRobert Mustacchi u32 pf_ack; 579d14abf15SRobert Mustacchi u32 vf_ack; 580d14abf15SRobert Mustacchi u32 iov_dis_ack; 581d14abf15SRobert Mustacchi }; 582d14abf15SRobert Mustacchi 583d14abf15SRobert Mustacchi struct fw_flr_mb { 584d14abf15SRobert Mustacchi u32 aggint; 585d14abf15SRobert Mustacchi u32 opgen_addr; 586d14abf15SRobert Mustacchi struct fw_flr_ack ack; 587d14abf15SRobert Mustacchi }; 588d14abf15SRobert Mustacchi 589d14abf15SRobert Mustacchi struct eee_remote_vals { 590d14abf15SRobert Mustacchi u32 tx_tw; 591d14abf15SRobert Mustacchi u32 rx_tw; 592d14abf15SRobert Mustacchi }; 593d14abf15SRobert Mustacchi 594d14abf15SRobert Mustacchi /**** SUPPORT FOR SHMEM ARRRAYS *** 595d14abf15SRobert Mustacchi * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 596d14abf15SRobert Mustacchi * define arrays with storage types smaller then unsigned dwords. 597d14abf15SRobert Mustacchi * The macros below add generic support for SHMEM arrays with numeric elements 598d14abf15SRobert Mustacchi * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 599d14abf15SRobert Mustacchi * array with individual bit-filed elements accessed using shifts and masks. 600d14abf15SRobert Mustacchi * 601d14abf15SRobert Mustacchi */ 602d14abf15SRobert Mustacchi 603d14abf15SRobert Mustacchi /* eb is the bitwidth of a single element */ 604d14abf15SRobert Mustacchi #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 605d14abf15SRobert Mustacchi #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 606d14abf15SRobert Mustacchi 607d14abf15SRobert Mustacchi /* the bit-position macro allows the used to flip the order of the arrays 608d14abf15SRobert Mustacchi * elements on a per byte or word boundary. 609d14abf15SRobert Mustacchi * 610d14abf15SRobert Mustacchi * example: an array with 8 entries each 4 bit wide. This array will fit into 611d14abf15SRobert Mustacchi * a single dword. The diagrmas below show the array order of the nibbles. 612d14abf15SRobert Mustacchi * 613d14abf15SRobert Mustacchi * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 614d14abf15SRobert Mustacchi * 615d14abf15SRobert Mustacchi * | | | | 616d14abf15SRobert Mustacchi * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 617d14abf15SRobert Mustacchi * | | | | 618d14abf15SRobert Mustacchi * 619d14abf15SRobert Mustacchi * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 620d14abf15SRobert Mustacchi * 621d14abf15SRobert Mustacchi * | | | | 622d14abf15SRobert Mustacchi * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 623d14abf15SRobert Mustacchi * | | | | 624d14abf15SRobert Mustacchi * 625d14abf15SRobert Mustacchi * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 626d14abf15SRobert Mustacchi * 627d14abf15SRobert Mustacchi * | | | | 628d14abf15SRobert Mustacchi * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 629d14abf15SRobert Mustacchi * | | | | 630d14abf15SRobert Mustacchi */ 631d14abf15SRobert Mustacchi #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 632d14abf15SRobert Mustacchi ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 633d14abf15SRobert Mustacchi (((i)%((fb)/(eb))) * (eb))) 634d14abf15SRobert Mustacchi 635d14abf15SRobert Mustacchi #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 636d14abf15SRobert Mustacchi ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 637d14abf15SRobert Mustacchi SHMEM_ARRAY_MASK(eb)) 638d14abf15SRobert Mustacchi 639d14abf15SRobert Mustacchi #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 640d14abf15SRobert Mustacchi do { \ 641d14abf15SRobert Mustacchi a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 642d14abf15SRobert Mustacchi SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 643d14abf15SRobert Mustacchi a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 644d14abf15SRobert Mustacchi SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 645d14abf15SRobert Mustacchi } while (0) 646d14abf15SRobert Mustacchi 647d14abf15SRobert Mustacchi 648d14abf15SRobert Mustacchi 649d14abf15SRobert Mustacchi /****START OF DCBX STRUCTURES DECLARATIONS****/ 650d14abf15SRobert Mustacchi #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 651d14abf15SRobert Mustacchi #define DCBX_PRI_PG_BITWIDTH 4 652d14abf15SRobert Mustacchi #define DCBX_PRI_PG_FBITS 8 653d14abf15SRobert Mustacchi #define DCBX_PRI_PG_GET(a, i) \ 654d14abf15SRobert Mustacchi SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 655d14abf15SRobert Mustacchi #define DCBX_PRI_PG_SET(a, i, val) \ 656d14abf15SRobert Mustacchi SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 657d14abf15SRobert Mustacchi #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 658d14abf15SRobert Mustacchi #define DCBX_BW_PG_BITWIDTH 8 659d14abf15SRobert Mustacchi #define DCBX_PG_BW_GET(a, i) \ 660d14abf15SRobert Mustacchi SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 661d14abf15SRobert Mustacchi #define DCBX_PG_BW_SET(a, i, val) \ 662d14abf15SRobert Mustacchi SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 663d14abf15SRobert Mustacchi #define DCBX_STRICT_PRI_PG 15 664d14abf15SRobert Mustacchi #define DCBX_MAX_APP_PROTOCOL 16 665d14abf15SRobert Mustacchi #define DCBX_MAX_APP_LOCAL 32 666d14abf15SRobert Mustacchi #define FCOE_APP_IDX 0 667d14abf15SRobert Mustacchi #define ISCSI_APP_IDX 1 668d14abf15SRobert Mustacchi #define PREDEFINED_APP_IDX_MAX 2 669d14abf15SRobert Mustacchi 670d14abf15SRobert Mustacchi 671d14abf15SRobert Mustacchi /* Big/Little endian have the same representation. */ 672d14abf15SRobert Mustacchi struct dcbx_ets_feature { 673d14abf15SRobert Mustacchi /* 674d14abf15SRobert Mustacchi * For Admin MIB - is this feature supported by the 675d14abf15SRobert Mustacchi * driver | For Local MIB - should this feature be enabled. 676d14abf15SRobert Mustacchi */ 677d14abf15SRobert Mustacchi u32 enabled; 678d14abf15SRobert Mustacchi u32 pg_bw_tbl[2]; 679d14abf15SRobert Mustacchi u32 pri_pg_tbl[1]; 680d14abf15SRobert Mustacchi }; 681d14abf15SRobert Mustacchi 682d14abf15SRobert Mustacchi /* Driver structure in LE */ 683d14abf15SRobert Mustacchi struct dcbx_pfc_feature { 684d14abf15SRobert Mustacchi #ifdef __BIG_ENDIAN 685d14abf15SRobert Mustacchi u8 pri_en_bitmap; 686d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_0 0x01 687d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_1 0x02 688d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_2 0x04 689d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_3 0x08 690d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_4 0x10 691d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_5 0x20 692d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_6 0x40 693d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_7 0x80 694d14abf15SRobert Mustacchi u8 pfc_caps; 695d14abf15SRobert Mustacchi u8 reserved; 696d14abf15SRobert Mustacchi u8 enabled; 697d14abf15SRobert Mustacchi #elif defined(__LITTLE_ENDIAN) 698d14abf15SRobert Mustacchi u8 enabled; 699d14abf15SRobert Mustacchi u8 reserved; 700d14abf15SRobert Mustacchi u8 pfc_caps; 701d14abf15SRobert Mustacchi u8 pri_en_bitmap; 702d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_0 0x01 703d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_1 0x02 704d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_2 0x04 705d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_3 0x08 706d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_4 0x10 707d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_5 0x20 708d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_6 0x40 709d14abf15SRobert Mustacchi #define DCBX_PFC_PRI_7 0x80 710d14abf15SRobert Mustacchi #endif 711d14abf15SRobert Mustacchi }; 712d14abf15SRobert Mustacchi 713d14abf15SRobert Mustacchi struct dcbx_app_priority_entry { 714d14abf15SRobert Mustacchi #ifdef __BIG_ENDIAN 715d14abf15SRobert Mustacchi u16 app_id; 716d14abf15SRobert Mustacchi u8 pri_bitmap; 717d14abf15SRobert Mustacchi u8 appBitfield; 718d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_VALID 0x01 719d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_SF_MASK 0x30 720d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_SF_SHIFT 4 721d14abf15SRobert Mustacchi #define DCBX_APP_SF_ETH_TYPE 0x10 722d14abf15SRobert Mustacchi #define DCBX_APP_SF_PORT 0x20 723d14abf15SRobert Mustacchi #define DCBX_APP_PRI_0 0x01 724d14abf15SRobert Mustacchi #define DCBX_APP_PRI_1 0x02 725d14abf15SRobert Mustacchi #define DCBX_APP_PRI_2 0x04 726d14abf15SRobert Mustacchi #define DCBX_APP_PRI_3 0x08 727d14abf15SRobert Mustacchi #define DCBX_APP_PRI_4 0x10 728d14abf15SRobert Mustacchi #define DCBX_APP_PRI_5 0x20 729d14abf15SRobert Mustacchi #define DCBX_APP_PRI_6 0x40 730d14abf15SRobert Mustacchi #define DCBX_APP_PRI_7 0x80 731d14abf15SRobert Mustacchi #elif defined(__LITTLE_ENDIAN) 732d14abf15SRobert Mustacchi u8 appBitfield; 733d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_VALID 0x01 734d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_SF_MASK 0x30 735d14abf15SRobert Mustacchi #define DCBX_APP_ENTRY_SF_SHIFT 4 736d14abf15SRobert Mustacchi #define DCBX_APP_SF_ETH_TYPE 0x10 737d14abf15SRobert Mustacchi #define DCBX_APP_SF_PORT 0x20 738d14abf15SRobert Mustacchi u8 pri_bitmap; 739d14abf15SRobert Mustacchi u16 app_id; 740d14abf15SRobert Mustacchi #endif 741d14abf15SRobert Mustacchi }; 742d14abf15SRobert Mustacchi 743d14abf15SRobert Mustacchi 744d14abf15SRobert Mustacchi /* FW structure in BE */ 745d14abf15SRobert Mustacchi struct dcbx_app_priority_feature { 746d14abf15SRobert Mustacchi #ifdef __BIG_ENDIAN 747d14abf15SRobert Mustacchi u8 reserved; 748d14abf15SRobert Mustacchi u8 default_pri; 749d14abf15SRobert Mustacchi u8 tc_supported; 750d14abf15SRobert Mustacchi u8 enabled; 751d14abf15SRobert Mustacchi #elif defined(__LITTLE_ENDIAN) 752d14abf15SRobert Mustacchi u8 enabled; 753d14abf15SRobert Mustacchi u8 tc_supported; 754d14abf15SRobert Mustacchi u8 default_pri; 755d14abf15SRobert Mustacchi u8 reserved; 756d14abf15SRobert Mustacchi #endif 757d14abf15SRobert Mustacchi struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 758d14abf15SRobert Mustacchi }; 759d14abf15SRobert Mustacchi 760d14abf15SRobert Mustacchi /* FW structure in BE */ 761d14abf15SRobert Mustacchi struct dcbx_features { 762d14abf15SRobert Mustacchi /* PG feature */ 763d14abf15SRobert Mustacchi struct dcbx_ets_feature ets; 764d14abf15SRobert Mustacchi /* PFC feature */ 765d14abf15SRobert Mustacchi struct dcbx_pfc_feature pfc; 766d14abf15SRobert Mustacchi /* APP feature */ 767d14abf15SRobert Mustacchi struct dcbx_app_priority_feature app; 768d14abf15SRobert Mustacchi }; 769d14abf15SRobert Mustacchi 770d14abf15SRobert Mustacchi /* LLDP protocol parameters */ 771d14abf15SRobert Mustacchi /* FW structure in BE */ 772d14abf15SRobert Mustacchi struct lldp_params { 773d14abf15SRobert Mustacchi #ifdef __BIG_ENDIAN 774d14abf15SRobert Mustacchi u8 msg_fast_tx_interval; 775d14abf15SRobert Mustacchi u8 msg_tx_hold; 776d14abf15SRobert Mustacchi u8 msg_tx_interval; 777d14abf15SRobert Mustacchi u8 admin_status; 778d14abf15SRobert Mustacchi #define LLDP_TX_ONLY 0x01 779d14abf15SRobert Mustacchi #define LLDP_RX_ONLY 0x02 780d14abf15SRobert Mustacchi #define LLDP_TX_RX 0x03 781d14abf15SRobert Mustacchi #define LLDP_DISABLED 0x04 782d14abf15SRobert Mustacchi u8 reserved1; 783d14abf15SRobert Mustacchi u8 tx_fast; 784d14abf15SRobert Mustacchi u8 tx_crd_max; 785d14abf15SRobert Mustacchi u8 tx_crd; 786d14abf15SRobert Mustacchi #elif defined(__LITTLE_ENDIAN) 787d14abf15SRobert Mustacchi u8 admin_status; 788d14abf15SRobert Mustacchi #define LLDP_TX_ONLY 0x01 789d14abf15SRobert Mustacchi #define LLDP_RX_ONLY 0x02 790d14abf15SRobert Mustacchi #define LLDP_TX_RX 0x03 791d14abf15SRobert Mustacchi #define LLDP_DISABLED 0x04 792d14abf15SRobert Mustacchi u8 msg_tx_interval; 793d14abf15SRobert Mustacchi u8 msg_tx_hold; 794d14abf15SRobert Mustacchi u8 msg_fast_tx_interval; 795d14abf15SRobert Mustacchi u8 tx_crd; 796d14abf15SRobert Mustacchi u8 tx_crd_max; 797d14abf15SRobert Mustacchi u8 tx_fast; 798d14abf15SRobert Mustacchi u8 reserved1; 799d14abf15SRobert Mustacchi #endif 800d14abf15SRobert Mustacchi #define REM_CHASSIS_ID_STAT_LEN 4 801d14abf15SRobert Mustacchi #define REM_PORT_ID_STAT_LEN 4 802d14abf15SRobert Mustacchi /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 803d14abf15SRobert Mustacchi u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 804d14abf15SRobert Mustacchi /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 805d14abf15SRobert Mustacchi u32 peer_port_id[REM_PORT_ID_STAT_LEN]; 806d14abf15SRobert Mustacchi }; 807d14abf15SRobert Mustacchi 808d14abf15SRobert Mustacchi struct lldp_dcbx_stat { 809d14abf15SRobert Mustacchi #define LOCAL_CHASSIS_ID_STAT_LEN 2 810d14abf15SRobert Mustacchi #define LOCAL_PORT_ID_STAT_LEN 2 811d14abf15SRobert Mustacchi /* Holds local Chassis ID 8B payload of constant subtype 4. */ 812d14abf15SRobert Mustacchi u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 813d14abf15SRobert Mustacchi /* Holds local Port ID 8B payload of constant subtype 3. */ 814d14abf15SRobert Mustacchi u32 local_port_id[LOCAL_PORT_ID_STAT_LEN]; 815d14abf15SRobert Mustacchi /* Number of DCBX frames transmitted. */ 816d14abf15SRobert Mustacchi u32 num_tx_dcbx_pkts; 817d14abf15SRobert Mustacchi /* Number of DCBX frames received. */ 818d14abf15SRobert Mustacchi u32 num_rx_dcbx_pkts; 819d14abf15SRobert Mustacchi }; 820d14abf15SRobert Mustacchi 821d14abf15SRobert Mustacchi /* ADMIN MIB - DCBX local machine default configuration. */ 822d14abf15SRobert Mustacchi struct lldp_admin_mib { 823d14abf15SRobert Mustacchi u32 ver_cfg_flags; 824d14abf15SRobert Mustacchi #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 825d14abf15SRobert Mustacchi #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 826d14abf15SRobert Mustacchi #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 827d14abf15SRobert Mustacchi #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 828d14abf15SRobert Mustacchi #define DCBX_ETS_RECO_VALID 0x00000010 829d14abf15SRobert Mustacchi #define DCBX_ETS_WILLING 0x00000020 830d14abf15SRobert Mustacchi #define DCBX_PFC_WILLING 0x00000040 831d14abf15SRobert Mustacchi #define DCBX_APP_WILLING 0x00000080 832d14abf15SRobert Mustacchi #define DCBX_VERSION_CEE 0x00000100 833d14abf15SRobert Mustacchi #define DCBX_VERSION_IEEE 0x00000200 834d14abf15SRobert Mustacchi #define DCBX_DCBX_ENABLED 0x00000400 835d14abf15SRobert Mustacchi #define DCBX_CEE_VERSION_MASK 0x0000f000 836d14abf15SRobert Mustacchi #define DCBX_CEE_VERSION_SHIFT 12 837d14abf15SRobert Mustacchi #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 838d14abf15SRobert Mustacchi #define DCBX_CEE_MAX_VERSION_SHIFT 16 839d14abf15SRobert Mustacchi struct dcbx_features features; 840d14abf15SRobert Mustacchi }; 841d14abf15SRobert Mustacchi 842d14abf15SRobert Mustacchi /* REMOTE MIB - remote machine DCBX configuration. */ 843d14abf15SRobert Mustacchi struct lldp_remote_mib { 844d14abf15SRobert Mustacchi u32 prefix_seq_num; 845d14abf15SRobert Mustacchi u32 flags; 846d14abf15SRobert Mustacchi #define DCBX_ETS_TLV_RX 0x00000001 847d14abf15SRobert Mustacchi #define DCBX_PFC_TLV_RX 0x00000002 848d14abf15SRobert Mustacchi #define DCBX_APP_TLV_RX 0x00000004 849d14abf15SRobert Mustacchi #define DCBX_ETS_RX_ERROR 0x00000010 850d14abf15SRobert Mustacchi #define DCBX_PFC_RX_ERROR 0x00000020 851d14abf15SRobert Mustacchi #define DCBX_APP_RX_ERROR 0x00000040 852d14abf15SRobert Mustacchi #define DCBX_ETS_REM_WILLING 0x00000100 853d14abf15SRobert Mustacchi #define DCBX_PFC_REM_WILLING 0x00000200 854d14abf15SRobert Mustacchi #define DCBX_APP_REM_WILLING 0x00000400 855d14abf15SRobert Mustacchi #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 856d14abf15SRobert Mustacchi #define DCBX_REMOTE_MIB_VALID 0x00002000 857d14abf15SRobert Mustacchi struct dcbx_features features; 858d14abf15SRobert Mustacchi u32 suffix_seq_num; 859d14abf15SRobert Mustacchi }; 860d14abf15SRobert Mustacchi 861d14abf15SRobert Mustacchi /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 862d14abf15SRobert Mustacchi struct lldp_local_mib { 863d14abf15SRobert Mustacchi u32 prefix_seq_num; 864d14abf15SRobert Mustacchi /* Indicates if there is mismatch with negotiation results. */ 865d14abf15SRobert Mustacchi u32 error; 866d14abf15SRobert Mustacchi #define DCBX_LOCAL_ETS_ERROR 0x00000001 867d14abf15SRobert Mustacchi #define DCBX_LOCAL_PFC_ERROR 0x00000002 868d14abf15SRobert Mustacchi #define DCBX_LOCAL_APP_ERROR 0x00000004 869d14abf15SRobert Mustacchi #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 870d14abf15SRobert Mustacchi #define DCBX_LOCAL_APP_MISMATCH 0x00000020 871d14abf15SRobert Mustacchi #define DCBX_REMOTE_MIB_ERROR 0x00000040 872d14abf15SRobert Mustacchi #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 873d14abf15SRobert Mustacchi #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 874d14abf15SRobert Mustacchi #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 875d14abf15SRobert Mustacchi struct dcbx_features features; 876d14abf15SRobert Mustacchi u32 suffix_seq_num; 877d14abf15SRobert Mustacchi }; 878d14abf15SRobert Mustacchi 879d14abf15SRobert Mustacchi struct lldp_local_mib_ext { 880d14abf15SRobert Mustacchi u32 prefix_seq_num; 881d14abf15SRobert Mustacchi /* APP TLV extension - 16 more entries for negotiation results*/ 882d14abf15SRobert Mustacchi struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 883d14abf15SRobert Mustacchi u32 suffix_seq_num; 884d14abf15SRobert Mustacchi }; 885d14abf15SRobert Mustacchi /***END OF DCBX STRUCTURES DECLARATIONS***/ 886d14abf15SRobert Mustacchi 887d14abf15SRobert Mustacchi /***********************************************************/ 888d14abf15SRobert Mustacchi /* Elink section */ 889d14abf15SRobert Mustacchi /***********************************************************/ 890d14abf15SRobert Mustacchi #define SHMEM_LINK_CONFIG_SIZE 2 891d14abf15SRobert Mustacchi struct shmem_lfa { 892d14abf15SRobert Mustacchi u32 req_duplex; 893d14abf15SRobert Mustacchi #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 894d14abf15SRobert Mustacchi #define REQ_DUPLEX_PHY0_SHIFT 0 895d14abf15SRobert Mustacchi #define REQ_DUPLEX_PHY1_MASK 0xffff0000 896d14abf15SRobert Mustacchi #define REQ_DUPLEX_PHY1_SHIFT 16 897d14abf15SRobert Mustacchi u32 req_flow_ctrl; 898d14abf15SRobert Mustacchi #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 899d14abf15SRobert Mustacchi #define REQ_FLOW_CTRL_PHY0_SHIFT 0 900d14abf15SRobert Mustacchi #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 901d14abf15SRobert Mustacchi #define REQ_FLOW_CTRL_PHY1_SHIFT 16 902d14abf15SRobert Mustacchi u32 req_line_speed; /* Also determine AutoNeg */ 903d14abf15SRobert Mustacchi #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 904d14abf15SRobert Mustacchi #define REQ_LINE_SPD_PHY0_SHIFT 0 905d14abf15SRobert Mustacchi #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 906d14abf15SRobert Mustacchi #define REQ_LINE_SPD_PHY1_SHIFT 16 907d14abf15SRobert Mustacchi u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 908d14abf15SRobert Mustacchi u32 additional_config; 909d14abf15SRobert Mustacchi #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 910d14abf15SRobert Mustacchi #define REQ_FC_AUTO_ADV0_SHIFT 0 911d14abf15SRobert Mustacchi #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 912d14abf15SRobert Mustacchi u32 lfa_sts; 913d14abf15SRobert Mustacchi #define LFA_LINK_FLAP_REASON_OFFSET 0 914d14abf15SRobert Mustacchi #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 915d14abf15SRobert Mustacchi #define LFA_LINK_DOWN 0x1 916d14abf15SRobert Mustacchi #define LFA_LOOPBACK_ENABLED 0x2 917d14abf15SRobert Mustacchi #define LFA_DUPLEX_MISMATCH 0x3 918d14abf15SRobert Mustacchi #define LFA_MFW_IS_TOO_OLD 0x4 919d14abf15SRobert Mustacchi #define LFA_LINK_SPEED_MISMATCH 0x5 920d14abf15SRobert Mustacchi #define LFA_FLOW_CTRL_MISMATCH 0x6 921d14abf15SRobert Mustacchi #define LFA_SPEED_CAP_MISMATCH 0x7 922d14abf15SRobert Mustacchi #define LFA_DCC_LFA_DISABLED 0x8 923d14abf15SRobert Mustacchi #define LFA_EEE_MISMATCH 0x9 924d14abf15SRobert Mustacchi 925d14abf15SRobert Mustacchi #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 926d14abf15SRobert Mustacchi #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 927d14abf15SRobert Mustacchi 928d14abf15SRobert Mustacchi #define LINK_FLAP_COUNT_OFFSET 16 929d14abf15SRobert Mustacchi #define LINK_FLAP_COUNT_MASK 0x00ff0000 930d14abf15SRobert Mustacchi 931d14abf15SRobert Mustacchi #define LFA_FLAGS_MASK 0xff000000 932d14abf15SRobert Mustacchi #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 933d14abf15SRobert Mustacchi 934d14abf15SRobert Mustacchi }; 935d14abf15SRobert Mustacchi 936d14abf15SRobert Mustacchi /* 937d14abf15SRobert Mustacchi Used to suppoert NSCI get OS driver version 938d14abf15SRobert Mustacchi On driver load the version value will be set 939d14abf15SRobert Mustacchi On driver unload driver value of 0x0 will be set 940d14abf15SRobert Mustacchi */ 941d14abf15SRobert Mustacchi struct os_drv_ver{ 942d14abf15SRobert Mustacchi #define DRV_VER_NOT_LOADED 0 943d14abf15SRobert Mustacchi /*personalites orrder is importent */ 944d14abf15SRobert Mustacchi #define DRV_PERS_ETHERNET 0 945d14abf15SRobert Mustacchi #define DRV_PERS_ISCSI 1 946d14abf15SRobert Mustacchi #define DRV_PERS_FCOE 2 947d14abf15SRobert Mustacchi /*shmem2 struct is constatnt can't add more personalites here*/ 948d14abf15SRobert Mustacchi #define MAX_DRV_PERS 3 949d14abf15SRobert Mustacchi u32 versions[MAX_DRV_PERS]; 950d14abf15SRobert Mustacchi }; 951d14abf15SRobert Mustacchi 952d14abf15SRobert Mustacchi struct shmem2_region { 953d14abf15SRobert Mustacchi 954d14abf15SRobert Mustacchi u32 size; /* 0x0000 */ 955d14abf15SRobert Mustacchi 956d14abf15SRobert Mustacchi u32 dcc_support; /* 0x0004 */ 957d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_NONE 0x00000000 958d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 959d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 960d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 961d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 962d14abf15SRobert Mustacchi #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 963d14abf15SRobert Mustacchi 964d14abf15SRobert Mustacchi u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 965d14abf15SRobert Mustacchi /* 966d14abf15SRobert Mustacchi * For backwards compatibility, if the mf_cfg_addr does not exist 967d14abf15SRobert Mustacchi * (the size filed is smaller than 0xc) the mf_cfg resides at the 968d14abf15SRobert Mustacchi * end of struct shmem_region 969d14abf15SRobert Mustacchi */ 970d14abf15SRobert Mustacchi u32 mf_cfg_addr; /* 0x0010 */ 971d14abf15SRobert Mustacchi #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 972d14abf15SRobert Mustacchi 973d14abf15SRobert Mustacchi struct fw_flr_mb flr_mb; /* 0x0014 */ 974d14abf15SRobert Mustacchi u32 dcbx_lldp_params_offset; /* 0x0028 */ 975d14abf15SRobert Mustacchi #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 976d14abf15SRobert Mustacchi u32 dcbx_neg_res_offset; /* 0x002c */ 977d14abf15SRobert Mustacchi #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 978d14abf15SRobert Mustacchi u32 dcbx_remote_mib_offset; /* 0x0030 */ 979d14abf15SRobert Mustacchi #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 980d14abf15SRobert Mustacchi /* 981d14abf15SRobert Mustacchi * The other shmemX_base_addr holds the other path's shmem address 982d14abf15SRobert Mustacchi * required for example in case of common phy init, or for path1 to know 983d14abf15SRobert Mustacchi * the address of mcp debug trace which is located in offset from shmem 984d14abf15SRobert Mustacchi * of path0 985d14abf15SRobert Mustacchi */ 986d14abf15SRobert Mustacchi u32 other_shmem_base_addr; /* 0x0034 */ 987d14abf15SRobert Mustacchi u32 other_shmem2_base_addr; /* 0x0038 */ 988d14abf15SRobert Mustacchi /* 989d14abf15SRobert Mustacchi * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 990d14abf15SRobert Mustacchi * which were disabled/flred 991d14abf15SRobert Mustacchi */ 992d14abf15SRobert Mustacchi u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 993d14abf15SRobert Mustacchi 994d14abf15SRobert Mustacchi /* 995d14abf15SRobert Mustacchi * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 996d14abf15SRobert Mustacchi * VFs 997d14abf15SRobert Mustacchi */ 998d14abf15SRobert Mustacchi u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 999d14abf15SRobert Mustacchi 1000d14abf15SRobert Mustacchi u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 1001d14abf15SRobert Mustacchi #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 1002d14abf15SRobert Mustacchi 1003d14abf15SRobert Mustacchi /* 1004d14abf15SRobert Mustacchi * edebug_driver_if field is used to transfer messages between edebug 1005d14abf15SRobert Mustacchi * app to the driver through shmem2. 1006d14abf15SRobert Mustacchi * 1007d14abf15SRobert Mustacchi * message format: 1008d14abf15SRobert Mustacchi * bits 0-2 - function number / instance of driver to perform request 1009d14abf15SRobert Mustacchi * bits 3-5 - op code / is_ack? 1010d14abf15SRobert Mustacchi * bits 6-63 - data 1011d14abf15SRobert Mustacchi */ 1012d14abf15SRobert Mustacchi u32 edebug_driver_if[2]; /* 0x0068 */ 1013d14abf15SRobert Mustacchi #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 1014d14abf15SRobert Mustacchi #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 1015d14abf15SRobert Mustacchi #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 1016d14abf15SRobert Mustacchi 1017d14abf15SRobert Mustacchi u32 nvm_retain_bitmap_addr; /* 0x0070 */ 1018d14abf15SRobert Mustacchi 1019d14abf15SRobert Mustacchi /* afex support of that driver */ 1020d14abf15SRobert Mustacchi u32 afex_driver_support; /* 0x0074 */ 1021d14abf15SRobert Mustacchi #define SHMEM_AFEX_VERSION_MASK 0x100f 1022d14abf15SRobert Mustacchi #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 1023d14abf15SRobert Mustacchi #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 1024d14abf15SRobert Mustacchi 1025d14abf15SRobert Mustacchi /* driver receives addr in scratchpad to which it should respond */ 1026d14abf15SRobert Mustacchi u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 1027d14abf15SRobert Mustacchi 1028d14abf15SRobert Mustacchi /* 1029d14abf15SRobert Mustacchi * generic params from MCP to driver (value depends on the msg sent 1030d14abf15SRobert Mustacchi * to driver 1031d14abf15SRobert Mustacchi */ 1032d14abf15SRobert Mustacchi u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 1033d14abf15SRobert Mustacchi u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 1034d14abf15SRobert Mustacchi 1035d14abf15SRobert Mustacchi u32 swim_base_addr; /* 0x0108 */ 1036d14abf15SRobert Mustacchi u32 swim_funcs; 1037d14abf15SRobert Mustacchi u32 swim_main_cb; 1038d14abf15SRobert Mustacchi 1039d14abf15SRobert Mustacchi /* 1040d14abf15SRobert Mustacchi * bitmap notifying which VIF profiles stored in nvram are enabled by 1041d14abf15SRobert Mustacchi * switch 1042d14abf15SRobert Mustacchi */ 1043d14abf15SRobert Mustacchi u32 afex_profiles_enabled[2]; 1044d14abf15SRobert Mustacchi 1045d14abf15SRobert Mustacchi /* generic flags controlled by the driver */ 1046d14abf15SRobert Mustacchi u32 drv_flags; 1047d14abf15SRobert Mustacchi #define DRV_FLAGS_DCB_CONFIGURED 0x0 1048d14abf15SRobert Mustacchi #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 1049d14abf15SRobert Mustacchi #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 1050d14abf15SRobert Mustacchi 1051d14abf15SRobert Mustacchi #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 1052d14abf15SRobert Mustacchi (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 1053d14abf15SRobert Mustacchi (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 1054d14abf15SRobert Mustacchi /* Port offset*/ 1055d14abf15SRobert Mustacchi #define DRV_FLAGS_P0_OFFSET 0 1056d14abf15SRobert Mustacchi #define DRV_FLAGS_P1_OFFSET 16 1057d14abf15SRobert Mustacchi #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 1058d14abf15SRobert Mustacchi DRV_FLAGS_P0_OFFSET : \ 1059d14abf15SRobert Mustacchi DRV_FLAGS_P1_OFFSET) 1060d14abf15SRobert Mustacchi 1061d14abf15SRobert Mustacchi #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 1062d14abf15SRobert Mustacchi DRV_FLAGS_GET_PORT_OFFSET(_port)) 1063d14abf15SRobert Mustacchi 1064d14abf15SRobert Mustacchi #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 1065d14abf15SRobert Mustacchi (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 1066d14abf15SRobert Mustacchi 1067d14abf15SRobert Mustacchi /* pointer to extended dev_info shared data copied from nvm image */ 1068d14abf15SRobert Mustacchi u32 extended_dev_info_shared_addr; 1069d14abf15SRobert Mustacchi u32 ncsi_oem_data_addr; 1070d14abf15SRobert Mustacchi 1071d14abf15SRobert Mustacchi u32 sensor_data_addr; 1072d14abf15SRobert Mustacchi u32 buffer_block_addr; 1073d14abf15SRobert Mustacchi u32 sensor_data_req_update_interval; 1074d14abf15SRobert Mustacchi u32 temperature_in_half_celsius; 1075d14abf15SRobert Mustacchi u32 glob_struct_in_host; 1076d14abf15SRobert Mustacchi 1077d14abf15SRobert Mustacchi u32 dcbx_neg_res_ext_offset; 1078d14abf15SRobert Mustacchi #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 1079d14abf15SRobert Mustacchi 1080d14abf15SRobert Mustacchi u32 drv_capabilities_flag[E2_FUNC_MAX]; 1081d14abf15SRobert Mustacchi #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 1082d14abf15SRobert Mustacchi #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 1083d14abf15SRobert Mustacchi #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 1084d14abf15SRobert Mustacchi #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 1085d14abf15SRobert Mustacchi #define DRV_FLAGS_MTU_MASK 0xffff0000 1086d14abf15SRobert Mustacchi #define DRV_FLAGS_MTU_SHIFT 16 1087d14abf15SRobert Mustacchi 1088d14abf15SRobert Mustacchi u32 extended_dev_info_shared_cfg_size; 1089d14abf15SRobert Mustacchi 1090d14abf15SRobert Mustacchi u32 dcbx_en[PORT_MAX]; 1091d14abf15SRobert Mustacchi 1092d14abf15SRobert Mustacchi /* The offset points to the multi threaded meta structure */ 1093d14abf15SRobert Mustacchi u32 multi_thread_data_offset; 1094d14abf15SRobert Mustacchi 1095d14abf15SRobert Mustacchi /* address of DMAable host address holding values from the drivers */ 1096d14abf15SRobert Mustacchi u32 drv_info_host_addr_lo; 1097d14abf15SRobert Mustacchi u32 drv_info_host_addr_hi; 1098d14abf15SRobert Mustacchi 1099d14abf15SRobert Mustacchi /* general values written by the MFW (such as current version) */ 1100d14abf15SRobert Mustacchi u32 drv_info_control; 1101d14abf15SRobert Mustacchi #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 1102d14abf15SRobert Mustacchi #define DRV_INFO_CONTROL_VER_SHIFT 0 1103d14abf15SRobert Mustacchi #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 1104d14abf15SRobert Mustacchi #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 1105d14abf15SRobert Mustacchi u32 ibft_host_addr; /* initialized by option ROM */ 1106d14abf15SRobert Mustacchi 1107d14abf15SRobert Mustacchi struct eee_remote_vals eee_remote_vals[PORT_MAX]; 1108d14abf15SRobert Mustacchi u32 pf_allocation[E2_FUNC_MAX]; 1109d14abf15SRobert Mustacchi #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 1110d14abf15SRobert Mustacchi #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 1111d14abf15SRobert Mustacchi 1112d14abf15SRobert Mustacchi /* the status of EEE auto-negotiation 1113d14abf15SRobert Mustacchi * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 1114d14abf15SRobert Mustacchi * bits 19:16 the supported modes for EEE. 1115d14abf15SRobert Mustacchi * bits 23:20 the speeds advertised for EEE. 1116d14abf15SRobert Mustacchi * bits 27:24 the speeds the Link partner advertised for EEE. 1117d14abf15SRobert Mustacchi * The supported/adv. modes in bits 27:19 originate from the 1118d14abf15SRobert Mustacchi * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 1119d14abf15SRobert Mustacchi * bit 28 when 1'b1 EEE was requested. 1120d14abf15SRobert Mustacchi * bit 29 when 1'b1 tx lpi was requested. 1121d14abf15SRobert Mustacchi * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 1122d14abf15SRobert Mustacchi * 30:29 are 2'b11. 1123d14abf15SRobert Mustacchi * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 1124d14abf15SRobert Mustacchi * value. When 1'b1 those bits contains a value times 16 microseconds. 1125d14abf15SRobert Mustacchi */ 1126d14abf15SRobert Mustacchi u32 eee_status[PORT_MAX]; 1127d14abf15SRobert Mustacchi #define SHMEM_EEE_TIMER_MASK 0x0000ffff 1128d14abf15SRobert Mustacchi #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 1129d14abf15SRobert Mustacchi #define SHMEM_EEE_SUPPORTED_SHIFT 16 1130d14abf15SRobert Mustacchi #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 1131*cabd62a2SToomas Soome #define SHMEM_EEE_100M_ADV (1U<<0) 1132*cabd62a2SToomas Soome #define SHMEM_EEE_1G_ADV (1U<<1) 1133*cabd62a2SToomas Soome #define SHMEM_EEE_10G_ADV (1U<<2) 1134d14abf15SRobert Mustacchi #define SHMEM_EEE_ADV_STATUS_SHIFT 20 1135d14abf15SRobert Mustacchi #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 1136d14abf15SRobert Mustacchi #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 1137d14abf15SRobert Mustacchi #define SHMEM_EEE_REQUESTED_BIT 0x10000000 1138d14abf15SRobert Mustacchi #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 1139d14abf15SRobert Mustacchi #define SHMEM_EEE_ACTIVE_BIT 0x40000000 1140d14abf15SRobert Mustacchi #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 1141d14abf15SRobert Mustacchi 1142d14abf15SRobert Mustacchi u32 sizeof_port_stats; 1143d14abf15SRobert Mustacchi 1144d14abf15SRobert Mustacchi /* Link Flap Avoidance */ 1145d14abf15SRobert Mustacchi u32 lfa_host_addr[PORT_MAX]; 1146d14abf15SRobert Mustacchi 1147d14abf15SRobert Mustacchi /* External PHY temperature in deg C. */ 1148d14abf15SRobert Mustacchi u32 extphy_temps_in_celsius; 1149d14abf15SRobert Mustacchi #define EXTPHY1_TEMP_MASK 0x0000ffff 1150d14abf15SRobert Mustacchi #define EXTPHY1_TEMP_SHIFT 0 1151d14abf15SRobert Mustacchi 1152d14abf15SRobert Mustacchi u32 ocdata_info_addr; /* Offset 0x148 */ 1153d14abf15SRobert Mustacchi u32 drv_func_info_addr; /* Offset 0x14C */ 1154d14abf15SRobert Mustacchi u32 drv_func_info_size; /* Offset 0x150 */ 1155d14abf15SRobert Mustacchi u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 1156d14abf15SRobert Mustacchi #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001 1157d14abf15SRobert Mustacchi #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00 1158d14abf15SRobert Mustacchi #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8 1159d14abf15SRobert Mustacchi #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000 1160d14abf15SRobert Mustacchi #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000 1161d14abf15SRobert Mustacchi #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000 1162d14abf15SRobert Mustacchi 1163d14abf15SRobert Mustacchi u32 ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */ 1164d14abf15SRobert Mustacchi u32 fcode_ver; /* Offset 0x15c */ 1165d14abf15SRobert Mustacchi u32 link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */ 1166d14abf15SRobert Mustacchi #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */ 1167d14abf15SRobert Mustacchi /* driver version for each personality*/ 1168d14abf15SRobert Mustacchi struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */ 1169d14abf15SRobert Mustacchi 1170d14abf15SRobert Mustacchi /* Flag to the driver that PF's drv_info_host_addr buffer was read */ 1171d14abf15SRobert Mustacchi u32 mfw_drv_indication; 1172d14abf15SRobert Mustacchi 1173d14abf15SRobert Mustacchi /* We use inidcation for each PF (0..3) */ 1174d14abf15SRobert Mustacchi #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_) 1175d14abf15SRobert Mustacchi }; 1176d14abf15SRobert Mustacchi 1177d14abf15SRobert Mustacchi #endif 1178