1*d14abf15SRobert Mustacchi #ifndef MAX_DRV_INFO_H
2*d14abf15SRobert Mustacchi #define MAX_DRV_INFO_H
3*d14abf15SRobert Mustacchi 
4*d14abf15SRobert Mustacchi #define PORT_0              0
5*d14abf15SRobert Mustacchi #define PORT_1              1
6*d14abf15SRobert Mustacchi #define PORT_MAX            2
7*d14abf15SRobert Mustacchi #define NVM_PATH_MAX        2
8*d14abf15SRobert Mustacchi 
9*d14abf15SRobert Mustacchi /* FCoE capabilities required from the driver */
10*d14abf15SRobert Mustacchi struct fcoe_capabilities {
11*d14abf15SRobert Mustacchi 	u32 capability1;
12*d14abf15SRobert Mustacchi 	/* Maximum number of I/Os per connection */
13*d14abf15SRobert Mustacchi 	#define FCOE_IOS_PER_CONNECTION_MASK    0x0000ffff
14*d14abf15SRobert Mustacchi 	#define FCOE_IOS_PER_CONNECTION_SHIFT   0
15*d14abf15SRobert Mustacchi 	/* Maximum number of Logins per port */
16*d14abf15SRobert Mustacchi 	#define FCOE_LOGINS_PER_PORT_MASK       0xffff0000
17*d14abf15SRobert Mustacchi 	#define FCOE_LOGINS_PER_PORT_SHIFT   16
18*d14abf15SRobert Mustacchi 
19*d14abf15SRobert Mustacchi 	u32 capability2;
20*d14abf15SRobert Mustacchi 	/* Maximum number of exchanges */
21*d14abf15SRobert Mustacchi 	#define FCOE_NUMBER_OF_EXCHANGES_MASK   0x0000ffff
22*d14abf15SRobert Mustacchi 	#define FCOE_NUMBER_OF_EXCHANGES_SHIFT  0
23*d14abf15SRobert Mustacchi 	/* Maximum NPIV WWN per port */
24*d14abf15SRobert Mustacchi 	#define FCOE_NPIV_WWN_PER_PORT_MASK     0xffff0000
25*d14abf15SRobert Mustacchi 	#define FCOE_NPIV_WWN_PER_PORT_SHIFT    16
26*d14abf15SRobert Mustacchi 
27*d14abf15SRobert Mustacchi 	u32 capability3;
28*d14abf15SRobert Mustacchi 	/* Maximum number of targets supported */
29*d14abf15SRobert Mustacchi 	#define FCOE_TARGETS_SUPPORTED_MASK     0x0000ffff
30*d14abf15SRobert Mustacchi 	#define FCOE_TARGETS_SUPPORTED_SHIFT    0
31*d14abf15SRobert Mustacchi 	/* Maximum number of outstanding commands across all connections */
32*d14abf15SRobert Mustacchi 	#define FCOE_OUTSTANDING_COMMANDS_MASK  0xffff0000
33*d14abf15SRobert Mustacchi 	#define FCOE_OUTSTANDING_COMMANDS_SHIFT 16
34*d14abf15SRobert Mustacchi 
35*d14abf15SRobert Mustacchi 	u32 capability4;
36*d14abf15SRobert Mustacchi 	#define FCOE_CAPABILITY4_STATEFUL       		0x00000001
37*d14abf15SRobert Mustacchi 	#define FCOE_CAPABILITY4_STATELESS      		0x00000002
38*d14abf15SRobert Mustacchi 	#define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID   	0x00000004
39*d14abf15SRobert Mustacchi };
40*d14abf15SRobert Mustacchi 
41*d14abf15SRobert Mustacchi struct glob_ncsi_oem_data
42*d14abf15SRobert Mustacchi {
43*d14abf15SRobert Mustacchi 	u32 driver_version;
44*d14abf15SRobert Mustacchi 	u32 unused[3];
45*d14abf15SRobert Mustacchi 	struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX];
46*d14abf15SRobert Mustacchi };
47*d14abf15SRobert Mustacchi 
48*d14abf15SRobert Mustacchi /* current drv_info version */
49*d14abf15SRobert Mustacchi #define DRV_INFO_CUR_VER 2
50*d14abf15SRobert Mustacchi 
51*d14abf15SRobert Mustacchi /* drv_info op codes supported */
52*d14abf15SRobert Mustacchi enum drv_info_opcode {
53*d14abf15SRobert Mustacchi 	ETH_STATS_OPCODE,
54*d14abf15SRobert Mustacchi 	FCOE_STATS_OPCODE,
55*d14abf15SRobert Mustacchi 	ISCSI_STATS_OPCODE
56*d14abf15SRobert Mustacchi };
57*d14abf15SRobert Mustacchi 
58*d14abf15SRobert Mustacchi #define ETH_STAT_INFO_VERSION_LEN	12
59*d14abf15SRobert Mustacchi /*  Per PCI Function Ethernet Statistics required from the driver */
60*d14abf15SRobert Mustacchi struct eth_stats_info {
61*d14abf15SRobert Mustacchi 	/* Function's Driver Version. padded to 12 */
62*d14abf15SRobert Mustacchi 	u8 version[ETH_STAT_INFO_VERSION_LEN];
63*d14abf15SRobert Mustacchi 	/* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
64*d14abf15SRobert Mustacchi 	u8 mac_local[8];
65*d14abf15SRobert Mustacchi 	u8 mac_add1[8];		/* Additional Programmed MAC Addr 1. */
66*d14abf15SRobert Mustacchi 	u8 mac_add2[8];		/* Additional Programmed MAC Addr 2. */
67*d14abf15SRobert Mustacchi 	u32 mtu_size;		/* MTU Size. Note   : Negotiated MTU */
68*d14abf15SRobert Mustacchi 	u32 feature_flags;	/* Feature_Flags. */
69*d14abf15SRobert Mustacchi #define FEATURE_ETH_CHKSUM_OFFLOAD_MASK		0x01
70*d14abf15SRobert Mustacchi #define FEATURE_ETH_LSO_MASK			0x02
71*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_MASK		0x1C
72*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_SHIFT		2
73*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_NONE		(0x0 << 2)
74*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_PXE		(0x1 << 2)
75*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_ISCSI		(0x2 << 2)
76*d14abf15SRobert Mustacchi #define FEATURE_ETH_BOOTMODE_FCOE		(0x3 << 2)
77*d14abf15SRobert Mustacchi #define FEATURE_ETH_TOE_MASK			0x20
78*d14abf15SRobert Mustacchi 	u32 lso_max_size;	/* LSO MaxOffloadSize. */
79*d14abf15SRobert Mustacchi 	u32 lso_min_seg_cnt;	/* LSO MinSegmentCount. */
80*d14abf15SRobert Mustacchi 	/* Num Offloaded Connections TCP_IPv4. */
81*d14abf15SRobert Mustacchi 	u32 ipv4_ofld_cnt;
82*d14abf15SRobert Mustacchi 	/* Num Offloaded Connections TCP_IPv6. */
83*d14abf15SRobert Mustacchi 	u32 ipv6_ofld_cnt;
84*d14abf15SRobert Mustacchi 	u32 promiscuous_mode;	/* Promiscuous Mode. non-zero true */
85*d14abf15SRobert Mustacchi 	u32 txq_size;		/* TX Descriptors Queue Size */
86*d14abf15SRobert Mustacchi 	u32 rxq_size;		/* RX Descriptors Queue Size */
87*d14abf15SRobert Mustacchi 	/* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
88*d14abf15SRobert Mustacchi 	u32 txq_avg_depth;
89*d14abf15SRobert Mustacchi 	/* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
90*d14abf15SRobert Mustacchi 	u32 rxq_avg_depth;
91*d14abf15SRobert Mustacchi 	/* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
92*d14abf15SRobert Mustacchi 	u32 iov_offload;
93*d14abf15SRobert Mustacchi 	/* Number of NetQueue/VMQ Config'd. */
94*d14abf15SRobert Mustacchi 	u32 netq_cnt;
95*d14abf15SRobert Mustacchi 	u32 vf_cnt;		/* Num VF assigned to this PF. */
96*d14abf15SRobert Mustacchi };
97*d14abf15SRobert Mustacchi 
98*d14abf15SRobert Mustacchi /*  Per PCI Function FCOE Statistics required from the driver */
99*d14abf15SRobert Mustacchi struct fcoe_stats_info {
100*d14abf15SRobert Mustacchi 	u8 version[12];		/* Function's Driver Version. */
101*d14abf15SRobert Mustacchi 	u8 mac_local[8];	/* Locally Admin Addr. */
102*d14abf15SRobert Mustacchi 	u8 mac_add1[8];		/* Additional Programmed MAC Addr 1. */
103*d14abf15SRobert Mustacchi 	u8 mac_add2[8];		/* Additional Programmed MAC Addr 2. */
104*d14abf15SRobert Mustacchi 	/* QoS Priority (per 802.1p). 0-7255 */
105*d14abf15SRobert Mustacchi 	u32 qos_priority;
106*d14abf15SRobert Mustacchi 	u32 txq_size;		/* FCoE TX Descriptors Queue Size. */
107*d14abf15SRobert Mustacchi 	u32 rxq_size;		/* FCoE RX Descriptors Queue Size. */
108*d14abf15SRobert Mustacchi 	/* FCoE TX Descriptor Queue Avg Depth. */
109*d14abf15SRobert Mustacchi 	u32 txq_avg_depth;
110*d14abf15SRobert Mustacchi 	/* FCoE RX Descriptors Queue Avg Depth. */
111*d14abf15SRobert Mustacchi 	u32 rxq_avg_depth;
112*d14abf15SRobert Mustacchi 	u32 rx_frames_lo;	/* FCoE RX Frames received. */
113*d14abf15SRobert Mustacchi 	u32 rx_frames_hi;	/* FCoE RX Frames received. */
114*d14abf15SRobert Mustacchi 	u32 rx_bytes_lo;	/* FCoE RX Bytes received. */
115*d14abf15SRobert Mustacchi 	u32 rx_bytes_hi;	/* FCoE RX Bytes received. */
116*d14abf15SRobert Mustacchi 	u32 tx_frames_lo;	/* FCoE TX Frames sent. */
117*d14abf15SRobert Mustacchi 	u32 tx_frames_hi;	/* FCoE TX Frames sent. */
118*d14abf15SRobert Mustacchi 	u32 tx_bytes_lo;	/* FCoE TX Bytes sent. */
119*d14abf15SRobert Mustacchi 	u32 tx_bytes_hi;	/* FCoE TX Bytes sent. */
120*d14abf15SRobert Mustacchi 	u32 rx_fcs_errors;	/* number of receive packets with FCS errors */
121*d14abf15SRobert Mustacchi 	u32 rx_fc_crc_errors;	/* number of FC frames with CRC errors*/
122*d14abf15SRobert Mustacchi 	u32 fip_login_failures;	/* number of FCoE/FIP Login failures */
123*d14abf15SRobert Mustacchi };
124*d14abf15SRobert Mustacchi 
125*d14abf15SRobert Mustacchi /* Per PCI  Function iSCSI Statistics required from the driver*/
126*d14abf15SRobert Mustacchi struct iscsi_stats_info {
127*d14abf15SRobert Mustacchi 	u8 version[12];		/* Function's Driver Version. */
128*d14abf15SRobert Mustacchi 	u8 mac_local[8];	/* Locally Admin iSCSI MAC Addr. */
129*d14abf15SRobert Mustacchi 	u8 mac_add1[8];		/* Additional Programmed MAC Addr 1. */
130*d14abf15SRobert Mustacchi 	/* QoS Priority (per 802.1p). 0-7255 */
131*d14abf15SRobert Mustacchi 	u32 qos_priority;
132*d14abf15SRobert Mustacchi 
133*d14abf15SRobert Mustacchi 	u8 initiator_name[64];	/* iSCSI Boot Initiator Node name. */
134*d14abf15SRobert Mustacchi 
135*d14abf15SRobert Mustacchi 	u8 ww_port_name[64];	/* iSCSI World wide port name */
136*d14abf15SRobert Mustacchi 
137*d14abf15SRobert Mustacchi 	u8 boot_target_name[64];/* iSCSI Boot Target Name. */
138*d14abf15SRobert Mustacchi 
139*d14abf15SRobert Mustacchi 	u8 boot_target_ip[16];	/* iSCSI Boot Target IP. */
140*d14abf15SRobert Mustacchi 	u32 boot_target_portal;	/* iSCSI Boot Target Portal. */
141*d14abf15SRobert Mustacchi 	u8 boot_init_ip[16];	/* iSCSI Boot Initiator IP Address. */
142*d14abf15SRobert Mustacchi 	u32 max_frame_size;	/* Max Frame Size. bytes */
143*d14abf15SRobert Mustacchi 	u32 txq_size;		/* PDU TX Descriptors Queue Size. */
144*d14abf15SRobert Mustacchi 	u32 rxq_size;		/* PDU RX Descriptors Queue Size. */
145*d14abf15SRobert Mustacchi 
146*d14abf15SRobert Mustacchi 	u32 txq_avg_depth;	/*PDU TX Descriptor Queue Avg Depth. */
147*d14abf15SRobert Mustacchi 	u32 rxq_avg_depth;	/*PDU RX Descriptors Queue Avg Depth. */
148*d14abf15SRobert Mustacchi 	u32 rx_pdus_lo;		/* iSCSI PDUs received. */
149*d14abf15SRobert Mustacchi 	u32 rx_pdus_hi;		/* iSCSI PDUs received. */
150*d14abf15SRobert Mustacchi 
151*d14abf15SRobert Mustacchi 	u32 rx_bytes_lo;	/* iSCSI RX Bytes received. */
152*d14abf15SRobert Mustacchi 	u32 rx_bytes_hi;	/* iSCSI RX Bytes received. */
153*d14abf15SRobert Mustacchi 	u32 tx_pdus_lo;		/* iSCSI PDUs sent. */
154*d14abf15SRobert Mustacchi 	u32 tx_pdus_hi;		/* iSCSI PDUs sent. */
155*d14abf15SRobert Mustacchi 
156*d14abf15SRobert Mustacchi 	u32 tx_bytes_lo;	/* iSCSI PDU TX Bytes sent. */
157*d14abf15SRobert Mustacchi 	u32 tx_bytes_hi;	/* iSCSI PDU TX Bytes sent. */
158*d14abf15SRobert Mustacchi 	u32 pcp_prior_map_tbl;	/*C-PCP to S-PCP Priority MapTable.
159*d14abf15SRobert Mustacchi 				9 nibbles, the position of each nibble
160*d14abf15SRobert Mustacchi 				represents the C-PCP value, the value
161*d14abf15SRobert Mustacchi 				of the nibble = S-PCP value.*/
162*d14abf15SRobert Mustacchi };
163*d14abf15SRobert Mustacchi 
164*d14abf15SRobert Mustacchi union drv_info_to_mcp {
165*d14abf15SRobert Mustacchi 	struct eth_stats_info		ether_stat;
166*d14abf15SRobert Mustacchi 	struct fcoe_stats_info		fcoe_stat;
167*d14abf15SRobert Mustacchi 	struct iscsi_stats_info		iscsi_stat;
168*d14abf15SRobert Mustacchi };
169*d14abf15SRobert Mustacchi 
170*d14abf15SRobert Mustacchi #endif /* MAX_DRV_INFO_H*/
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