1*d14abf15SRobert Mustacchi #ifndef _DBUS_ST_H 2*d14abf15SRobert Mustacchi #define _DBUS_ST_H 3*d14abf15SRobert Mustacchi 4*d14abf15SRobert Mustacchi #include "bcmtype.h" 5*d14abf15SRobert Mustacchi 6*d14abf15SRobert Mustacchi 7*d14abf15SRobert Mustacchi typedef struct _dbg_reg_write 8*d14abf15SRobert Mustacchi { 9*d14abf15SRobert Mustacchi u32_t addr; 10*d14abf15SRobert Mustacchi u32_t value; 11*d14abf15SRobert Mustacchi } dbg_reg_write; 12*d14abf15SRobert Mustacchi 13*d14abf15SRobert Mustacchi 14*d14abf15SRobert Mustacchi typedef struct _dbg_register_set_write 15*d14abf15SRobert Mustacchi { 16*d14abf15SRobert Mustacchi dbg_reg_write *p_reg; 17*d14abf15SRobert Mustacchi u32_t count; 18*d14abf15SRobert Mustacchi } dbg_register_set_write; 19*d14abf15SRobert Mustacchi 20*d14abf15SRobert Mustacchi 21*d14abf15SRobert Mustacchi typedef struct _dbg_reg_group 22*d14abf15SRobert Mustacchi { 23*d14abf15SRobert Mustacchi dbg_register_set_write dbgCfg; 24*d14abf15SRobert Mustacchi dbg_register_set_write dbgOn; 25*d14abf15SRobert Mustacchi dbg_register_set_write dbgOff; 26*d14abf15SRobert Mustacchi dbg_register_set_write dbgFlush; 27*d14abf15SRobert Mustacchi } dbg_reg_group; 28*d14abf15SRobert Mustacchi 29*d14abf15SRobert Mustacchi 30*d14abf15SRobert Mustacchi typedef struct _dbg_driver_end_read_regs 31*d14abf15SRobert Mustacchi { 32*d14abf15SRobert Mustacchi u32_t dbg_block_on; 33*d14abf15SRobert Mustacchi u32_t intr_buffer_read_ptr; 34*d14abf15SRobert Mustacchi u32_t intr_buffer_wr_ptr; 35*d14abf15SRobert Mustacchi u32_t ext_buffer_wr_ptr_lsb; 36*d14abf15SRobert Mustacchi u32_t ext_buffer_wr_ptr_msb; 37*d14abf15SRobert Mustacchi u32_t dbg_ovl_on_ext_buffer; 38*d14abf15SRobert Mustacchi u32_t dbg_wrap_ext; 39*d14abf15SRobert Mustacchi } dbg_driver_end_read_regs; 40*d14abf15SRobert Mustacchi 41*d14abf15SRobert Mustacchi 42*d14abf15SRobert Mustacchi typedef struct _dbg_driver_fill_regs 43*d14abf15SRobert Mustacchi { 44*d14abf15SRobert Mustacchi u32_t ext_buffer_start_addr_lsb; 45*d14abf15SRobert Mustacchi u32_t ext_buffer_start_addr_msb; 46*d14abf15SRobert Mustacchi u32_t ext_buffer_size; // in 256 byte blocks 47*d14abf15SRobert Mustacchi u32_t pci_func_num; // not for E1 48*d14abf15SRobert Mustacchi } dbg_driver_fill_regs; 49*d14abf15SRobert Mustacchi 50*d14abf15SRobert Mustacchi 51*d14abf15SRobert Mustacchi typedef struct _dbg_general_info 52*d14abf15SRobert Mustacchi { 53*d14abf15SRobert Mustacchi u32_t timestamp; 54*d14abf15SRobert Mustacchi u32_t chip_num; 55*d14abf15SRobert Mustacchi u32_t chosen_config; 56*d14abf15SRobert Mustacchi u32_t path_num; 57*d14abf15SRobert Mustacchi } dbg_general_info; 58*d14abf15SRobert Mustacchi 59*d14abf15SRobert Mustacchi 60*d14abf15SRobert Mustacchi typedef struct _dbg_dump_hdr 61*d14abf15SRobert Mustacchi { 62*d14abf15SRobert Mustacchi u32_t header_length; // will hold sizeof(dbg_dump_hdr) 63*d14abf15SRobert Mustacchi dbg_general_info info; 64*d14abf15SRobert Mustacchi dbg_driver_fill_regs driver_filled_info; 65*d14abf15SRobert Mustacchi dbg_driver_end_read_regs driver_read_regs; 66*d14abf15SRobert Mustacchi } dbg_dump_hdr; 67*d14abf15SRobert Mustacchi 68*d14abf15SRobert Mustacchi 69*d14abf15SRobert Mustacchi #define DBG_E1 0 70*d14abf15SRobert Mustacchi #define DBG_E1H 1 71*d14abf15SRobert Mustacchi #define DBG_E2 2 72*d14abf15SRobert Mustacchi #define DBG_E3 4 73*d14abf15SRobert Mustacchi extern dbg_general_info dbg_bus_general_info_E1; 74*d14abf15SRobert Mustacchi extern dbg_driver_fill_regs dbg_bus_driver_fill_regs_E1; 75*d14abf15SRobert Mustacchi extern dbg_driver_end_read_regs dbg_bus_driver_end_read_regs_E1; 76*d14abf15SRobert Mustacchi extern dbg_reg_write dbg_bus_all_regs_E1[]; 77*d14abf15SRobert Mustacchi extern dbg_reg_group dbg_bus_configs_E1[6]; 78*d14abf15SRobert Mustacchi 79*d14abf15SRobert Mustacchi extern dbg_general_info dbg_bus_general_info_E1H; 80*d14abf15SRobert Mustacchi extern dbg_driver_fill_regs dbg_bus_driver_fill_regs_E1H; 81*d14abf15SRobert Mustacchi extern dbg_driver_end_read_regs dbg_bus_driver_end_read_regs_E1H; 82*d14abf15SRobert Mustacchi extern dbg_reg_write dbg_bus_all_regs_E1H[]; 83*d14abf15SRobert Mustacchi extern dbg_reg_group dbg_bus_configs_E1H[25]; 84*d14abf15SRobert Mustacchi 85*d14abf15SRobert Mustacchi extern dbg_general_info dbg_bus_general_info_E2; 86*d14abf15SRobert Mustacchi extern dbg_driver_fill_regs dbg_bus_driver_fill_regs_E2; 87*d14abf15SRobert Mustacchi extern dbg_driver_end_read_regs dbg_bus_driver_end_read_regs_E2; 88*d14abf15SRobert Mustacchi extern dbg_reg_write dbg_bus_all_regs_E2[]; 89*d14abf15SRobert Mustacchi extern dbg_reg_group dbg_bus_configs_E2[25]; 90*d14abf15SRobert Mustacchi 91*d14abf15SRobert Mustacchi extern dbg_general_info dbg_bus_general_info_E3; 92*d14abf15SRobert Mustacchi extern dbg_driver_fill_regs dbg_bus_driver_fill_regs_E3; 93*d14abf15SRobert Mustacchi extern dbg_driver_end_read_regs dbg_bus_driver_end_read_regs_E3; 94*d14abf15SRobert Mustacchi extern dbg_reg_write dbg_bus_all_regs_E3[]; 95*d14abf15SRobert Mustacchi extern dbg_reg_group dbg_bus_configs_E3[34]; 96*d14abf15SRobert Mustacchi 97*d14abf15SRobert Mustacchi 98*d14abf15SRobert Mustacchi 99*d14abf15SRobert Mustacchi #endif //_DBUS_ST_H 100