1d14abf15SRobert Mustacchi 2d14abf15SRobert Mustacchi 3d14abf15SRobert Mustacchi #ifndef __ELINK_H 4d14abf15SRobert Mustacchi #define __ELINK_H 5d14abf15SRobert Mustacchi 6d14abf15SRobert Mustacchi #if defined(_VBD_) 7d14abf15SRobert Mustacchi #include <SAL.h> 8d14abf15SRobert Mustacchi #include "debug.h" 9d14abf15SRobert Mustacchi #endif 10d14abf15SRobert Mustacchi 11d14abf15SRobert Mustacchi #ifndef _In_ 12d14abf15SRobert Mustacchi #define _In_ 13d14abf15SRobert Mustacchi #endif 14d14abf15SRobert Mustacchi #ifndef _Out_ 15d14abf15SRobert Mustacchi #define _Out_ 16d14abf15SRobert Mustacchi #endif 17d14abf15SRobert Mustacchi 18d14abf15SRobert Mustacchi /***********************************************************/ 19d14abf15SRobert Mustacchi /* CLC Call backs functions */ 20d14abf15SRobert Mustacchi /***********************************************************/ 21d14abf15SRobert Mustacchi /* CLC device structure */ 22d14abf15SRobert Mustacchi struct elink_dev; 23d14abf15SRobert Mustacchi 24d14abf15SRobert Mustacchi extern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr); 25d14abf15SRobert Mustacchi extern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val); 26d14abf15SRobert Mustacchi /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/ 27d14abf15SRobert Mustacchi extern void elink_cb_reg_wb_write(struct elink_dev *cb, u32 offset, 28d14abf15SRobert Mustacchi u32 *wb_write, u16 len); 29d14abf15SRobert Mustacchi extern void elink_cb_reg_wb_read(struct elink_dev *cb, u32 offset, 30d14abf15SRobert Mustacchi u32 *wb_write, u16 len); 31d14abf15SRobert Mustacchi 32d14abf15SRobert Mustacchi /* mode - 0( LOW ) /1(HIGH)*/ 33d14abf15SRobert Mustacchi extern u8 elink_cb_gpio_write(struct elink_dev *cb, 34d14abf15SRobert Mustacchi u16 gpio_num, 35d14abf15SRobert Mustacchi u8 mode, u8 port); 36d14abf15SRobert Mustacchi extern u8 elink_cb_gpio_mult_write(struct elink_dev *cb, 37d14abf15SRobert Mustacchi u8 pins, 38d14abf15SRobert Mustacchi u8 mode); 39d14abf15SRobert Mustacchi 40d14abf15SRobert Mustacchi extern u32 elink_cb_gpio_read(struct elink_dev *cb, u16 gpio_num, u8 port); 41d14abf15SRobert Mustacchi extern u8 elink_cb_gpio_int_write(struct elink_dev *cb, 42d14abf15SRobert Mustacchi u16 gpio_num, 43d14abf15SRobert Mustacchi u8 mode, u8 port); 44d14abf15SRobert Mustacchi 45d14abf15SRobert Mustacchi extern u32 elink_cb_fw_command(struct elink_dev *cb, u32 command, u32 param); 46d14abf15SRobert Mustacchi 47d14abf15SRobert Mustacchi /* Delay */ 48d14abf15SRobert Mustacchi extern void elink_cb_udelay(struct elink_dev *cb, u32 microsecond); 49d14abf15SRobert Mustacchi 50d14abf15SRobert Mustacchi /* This function is called every 1024 bytes downloading of phy firmware. 51d14abf15SRobert Mustacchi Driver can use it to print to screen indication for download progress */ 52d14abf15SRobert Mustacchi extern void elink_cb_download_progress(struct elink_dev *cb, u32 cur, u32 total); 53d14abf15SRobert Mustacchi 54d14abf15SRobert Mustacchi /* Each log type has its own parameters */ 55d14abf15SRobert Mustacchi typedef enum elink_log_id { 56d14abf15SRobert Mustacchi ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* u8 port, const char* vendor_name, const char* vendor_pn */ 57d14abf15SRobert Mustacchi ELINK_LOG_ID_OVER_CURRENT = 1, /* u8 port */ 58d14abf15SRobert Mustacchi ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* u8 port */ 59d14abf15SRobert Mustacchi ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */ 60d14abf15SRobert Mustacchi ELINK_LOG_ID_NON_10G_MODULE = 4, /* u8 port */ 61d14abf15SRobert Mustacchi }elink_log_id_t; 62d14abf15SRobert Mustacchi 63d14abf15SRobert Mustacchi typedef enum elink_status { 64d14abf15SRobert Mustacchi ELINK_STATUS_OK = 0, 65d14abf15SRobert Mustacchi ELINK_STATUS_ERROR, 66d14abf15SRobert Mustacchi ELINK_STATUS_TIMEOUT, 67d14abf15SRobert Mustacchi ELINK_STATUS_NO_LINK, 68d14abf15SRobert Mustacchi ELINK_STATUS_INVALID_IMAGE, 69d14abf15SRobert Mustacchi ELINK_OP_NOT_SUPPORTED = 122 70d14abf15SRobert Mustacchi } elink_status_t; 71d14abf15SRobert Mustacchi #ifndef EDEBUG 72d14abf15SRobert Mustacchi extern void elink_cb_event_log(struct elink_dev *cb, const elink_log_id_t log_id, ...); 73d14abf15SRobert Mustacchi #endif 74d14abf15SRobert Mustacchi extern void elink_cb_load_warpcore_microcode(void); 75d14abf15SRobert Mustacchi 76d14abf15SRobert Mustacchi extern u8 elink_cb_path_id(struct elink_dev *cb); 77d14abf15SRobert Mustacchi 78d14abf15SRobert Mustacchi extern void elink_cb_notify_link_changed(struct elink_dev *cb); 79d14abf15SRobert Mustacchi 80d14abf15SRobert Mustacchi #define ELINK_EVENT_LOG_LEVEL_ERROR 1 81d14abf15SRobert Mustacchi #define ELINK_EVENT_LOG_LEVEL_WARNING 2 82d14abf15SRobert Mustacchi #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1 83d14abf15SRobert Mustacchi #define ELINK_EVENT_ID_SFP_POWER_FAULT 2 84d14abf15SRobert Mustacchi 85d14abf15SRobert Mustacchi #ifndef ARRAY_SIZE 86d14abf15SRobert Mustacchi #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 87d14abf15SRobert Mustacchi #endif 88d14abf15SRobert Mustacchi /* Debug prints */ 89d14abf15SRobert Mustacchi #ifdef ELINK_DEBUG 90d14abf15SRobert Mustacchi 91d14abf15SRobert Mustacchi #if defined(_VBD_) 92d14abf15SRobert Mustacchi #define ELINK_DEBUG_P0(cb, fmt) DbgMessage(cb, WARNelink, fmt) 93d14abf15SRobert Mustacchi #define ELINK_DEBUG_P1(cb, fmt, arg1) DbgMessage(cb, WARNelink, fmt, arg1) 94d14abf15SRobert Mustacchi #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) DbgMessage(cb, WARNelink, fmt, arg1, arg2) 95d14abf15SRobert Mustacchi #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \ 96d14abf15SRobert Mustacchi DbgMessage(cb, WARNelink, fmt, arg1, arg2, arg3) 97d14abf15SRobert Mustacchi #else 98d14abf15SRobert Mustacchi extern void elink_cb_dbg(struct elink_dev *cb, _In_ char *fmt); 99d14abf15SRobert Mustacchi extern void elink_cb_dbg1(struct elink_dev *cb, _In_ char *fmt, u32 arg1); 100d14abf15SRobert Mustacchi extern void elink_cb_dbg2(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2); 101d14abf15SRobert Mustacchi extern void elink_cb_dbg3(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2, 102d14abf15SRobert Mustacchi u32 arg3); 103d14abf15SRobert Mustacchi 104d14abf15SRobert Mustacchi #define ELINK_DEBUG_P0(cb, fmt) elink_cb_dbg(cb, fmt) 105d14abf15SRobert Mustacchi #define ELINK_DEBUG_P1(cb, fmt, arg1) elink_cb_dbg1(cb, fmt, arg1) 106d14abf15SRobert Mustacchi #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) elink_cb_dbg2(cb, fmt, arg1, arg2) 107d14abf15SRobert Mustacchi #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \ 108d14abf15SRobert Mustacchi elink_cb_dbg3(cb, fmt, arg1, arg2, arg3) 109d14abf15SRobert Mustacchi #endif // _VBD_ 110d14abf15SRobert Mustacchi 111d14abf15SRobert Mustacchi #else 112d14abf15SRobert Mustacchi #define ELINK_DEBUG_P0(cb, fmt) 113d14abf15SRobert Mustacchi #define ELINK_DEBUG_P1(cb, fmt, arg1) 114d14abf15SRobert Mustacchi #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2) 115d14abf15SRobert Mustacchi #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) 116d14abf15SRobert Mustacchi #endif 117d14abf15SRobert Mustacchi 118d14abf15SRobert Mustacchi /***********************************************************/ 119d14abf15SRobert Mustacchi /* Defines */ 120d14abf15SRobert Mustacchi /***********************************************************/ 121d14abf15SRobert Mustacchi #define ELINK_DEFAULT_PHY_DEV_ADDR 3 122d14abf15SRobert Mustacchi #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5 123d14abf15SRobert Mustacchi 124d14abf15SRobert Mustacchi 125d14abf15SRobert Mustacchi #ifndef DUPLEX_FULL 126d14abf15SRobert Mustacchi #define DUPLEX_FULL 1 127d14abf15SRobert Mustacchi #endif 128d14abf15SRobert Mustacchi #ifndef DUPLEX_HALF 129d14abf15SRobert Mustacchi #define DUPLEX_HALF 2 130d14abf15SRobert Mustacchi #endif 131d14abf15SRobert Mustacchi 132d14abf15SRobert Mustacchi #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO 133d14abf15SRobert Mustacchi #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX 134d14abf15SRobert Mustacchi #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX 135d14abf15SRobert Mustacchi #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH 136d14abf15SRobert Mustacchi #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE 137d14abf15SRobert Mustacchi 138d14abf15SRobert Mustacchi #define ELINK_NET_SERDES_IF_XFI 1 139d14abf15SRobert Mustacchi #define ELINK_NET_SERDES_IF_SFI 2 140d14abf15SRobert Mustacchi #define ELINK_NET_SERDES_IF_KR 3 141d14abf15SRobert Mustacchi #define ELINK_NET_SERDES_IF_DXGXS 4 142d14abf15SRobert Mustacchi 143d14abf15SRobert Mustacchi #define ELINK_SPEED_AUTO_NEG 0 144d14abf15SRobert Mustacchi #define ELINK_SPEED_10 10 145d14abf15SRobert Mustacchi #define ELINK_SPEED_100 100 146d14abf15SRobert Mustacchi #define ELINK_SPEED_1000 1000 147d14abf15SRobert Mustacchi #define ELINK_SPEED_2500 2500 148d14abf15SRobert Mustacchi #define ELINK_SPEED_10000 10000 149d14abf15SRobert Mustacchi #define ELINK_SPEED_20000 20000 150d14abf15SRobert Mustacchi 151d14abf15SRobert Mustacchi #define ELINK_I2C_DEV_ADDR_A0 0xa0 152d14abf15SRobert Mustacchi #define ELINK_I2C_DEV_ADDR_A2 0xa2 153d14abf15SRobert Mustacchi 154d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_PAGE_SIZE 16 155d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14 156d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16 157d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25 158d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3 159d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28 160d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_PART_NO_SIZE 16 161d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38 162d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_REVISION_SIZE 4 163d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44 164d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_SERIAL_SIZE 16 165d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */ 166d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_DATE_SIZE 6 167d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c 168d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1 169d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2) 170d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 171d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1 172d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR 0x60 173d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE 16 174d14abf15SRobert Mustacchi 175d14abf15SRobert Mustacchi 176d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e 177d14abf15SRobert Mustacchi #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f 178d14abf15SRobert Mustacchi 179d14abf15SRobert Mustacchi #define ELINK_PWR_FLT_ERR_MSG_LEN 250 180d14abf15SRobert Mustacchi 181d14abf15SRobert Mustacchi #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \ 182d14abf15SRobert Mustacchi ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) 183d14abf15SRobert Mustacchi #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \ 184d14abf15SRobert Mustacchi (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \ 185d14abf15SRobert Mustacchi PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT) 186d14abf15SRobert Mustacchi #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \ 187d14abf15SRobert Mustacchi ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) 188d14abf15SRobert Mustacchi 189d14abf15SRobert Mustacchi /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */ 190d14abf15SRobert Mustacchi #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1) 191d14abf15SRobert Mustacchi /* Single Media board contains single external phy */ 192d14abf15SRobert Mustacchi #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2) 193d14abf15SRobert Mustacchi /* Dual Media board contains two external phy with different media */ 194d14abf15SRobert Mustacchi #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3) 195d14abf15SRobert Mustacchi 196d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF 197d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00 198d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000 199d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16 200d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \ 201d14abf15SRobert Mustacchi ELINK_FW_PARAM_PHY_ADDR_MASK) 202d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \ 203d14abf15SRobert Mustacchi ELINK_FW_PARAM_PHY_TYPE_MASK) 204d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \ 205d14abf15SRobert Mustacchi ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \ 206d14abf15SRobert Mustacchi ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 207d14abf15SRobert Mustacchi #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \ 208d14abf15SRobert Mustacchi (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET) 209d14abf15SRobert Mustacchi 210d14abf15SRobert Mustacchi 211d14abf15SRobert Mustacchi #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170 212d14abf15SRobert Mustacchi #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250 213d14abf15SRobert Mustacchi 214d14abf15SRobert Mustacchi #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b)) 215d14abf15SRobert Mustacchi 216d14abf15SRobert Mustacchi #define ELINK_BMAC_CONTROL_RX_ENABLE 2 217d14abf15SRobert Mustacchi /***********************************************************/ 218d14abf15SRobert Mustacchi /* Structs */ 219d14abf15SRobert Mustacchi /***********************************************************/ 220d14abf15SRobert Mustacchi #define ELINK_INT_PHY 0 221d14abf15SRobert Mustacchi #define ELINK_EXT_PHY1 1 222d14abf15SRobert Mustacchi #define ELINK_EXT_PHY2 2 223d14abf15SRobert Mustacchi #define ELINK_MAX_PHYS 3 224d14abf15SRobert Mustacchi 225d14abf15SRobert Mustacchi /* Same configuration is shared between the XGXS and the first external phy */ 226d14abf15SRobert Mustacchi #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1) 227d14abf15SRobert Mustacchi #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \ 228d14abf15SRobert Mustacchi 0 : (_phy_idx - 1)) 229d14abf15SRobert Mustacchi /***********************************************************/ 230d14abf15SRobert Mustacchi /* elink_phy struct */ 231d14abf15SRobert Mustacchi /* Defines the required arguments and function per phy */ 232d14abf15SRobert Mustacchi /***********************************************************/ 233d14abf15SRobert Mustacchi struct elink_vars; 234d14abf15SRobert Mustacchi struct elink_params; 235d14abf15SRobert Mustacchi struct elink_phy; 236d14abf15SRobert Mustacchi 237ca19b857SToomas Soome typedef elink_status_t (*config_init_t)(struct elink_phy *phy, 238ca19b857SToomas Soome struct elink_params *params, struct elink_vars *vars); 239ca19b857SToomas Soome typedef elink_status_t (*read_status_t)(struct elink_phy *phy, 240ca19b857SToomas Soome struct elink_params *params, struct elink_vars *vars); 241d14abf15SRobert Mustacchi typedef void (*link_reset_t)(struct elink_phy *phy, 242d14abf15SRobert Mustacchi struct elink_params *params); 243d14abf15SRobert Mustacchi typedef void (*config_loopback_t)(struct elink_phy *phy, 244d14abf15SRobert Mustacchi struct elink_params *params); 245ca19b857SToomas Soome typedef elink_status_t (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len); 246d14abf15SRobert Mustacchi typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params); 247d14abf15SRobert Mustacchi typedef void (*set_link_led_t)(struct elink_phy *phy, 248d14abf15SRobert Mustacchi struct elink_params *params, u8 mode); 249d14abf15SRobert Mustacchi typedef void (*phy_specific_func_t)(struct elink_phy *phy, 250d14abf15SRobert Mustacchi struct elink_params *params, u32 action); 251d14abf15SRobert Mustacchi struct elink_reg_set { 252d14abf15SRobert Mustacchi u8 devad; 253d14abf15SRobert Mustacchi u16 reg; 254d14abf15SRobert Mustacchi u16 val; 255d14abf15SRobert Mustacchi }; 256d14abf15SRobert Mustacchi 257d14abf15SRobert Mustacchi struct elink_phy { 258d14abf15SRobert Mustacchi u32 type; 259d14abf15SRobert Mustacchi 260d14abf15SRobert Mustacchi /* Loaded during init */ 261d14abf15SRobert Mustacchi u8 addr; 262d14abf15SRobert Mustacchi u8 def_md_devad; 263d14abf15SRobert Mustacchi u16 flags; 264d14abf15SRobert Mustacchi /* No Over-Current detection */ 265d14abf15SRobert Mustacchi #define ELINK_FLAGS_NOC (1<<1) 266d14abf15SRobert Mustacchi /* Fan failure detection required */ 267d14abf15SRobert Mustacchi #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2) 268d14abf15SRobert Mustacchi /* Initialize first the XGXS and only then the phy itself */ 269d14abf15SRobert Mustacchi #define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3) 270d14abf15SRobert Mustacchi #define ELINK_FLAGS_WC_DUAL_MODE (1<<4) 271d14abf15SRobert Mustacchi #define ELINK_FLAGS_4_PORT_MODE (1<<5) 272d14abf15SRobert Mustacchi #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6) 273d14abf15SRobert Mustacchi #define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7) 274d14abf15SRobert Mustacchi #define ELINK_FLAGS_MDC_MDIO_WA (1<<8) 275d14abf15SRobert Mustacchi #define ELINK_FLAGS_DUMMY_READ (1<<9) 276d14abf15SRobert Mustacchi #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10) 277d14abf15SRobert Mustacchi #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11) 278d14abf15SRobert Mustacchi #define ELINK_FLAGS_TX_ERROR_CHECK (1<<12) 279d14abf15SRobert Mustacchi #define ELINK_FLAGS_EEE (1<<13) 280d14abf15SRobert Mustacchi #define ELINK_FLAGS_TEMPERATURE (1<<14) 281d14abf15SRobert Mustacchi #define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15) 282d14abf15SRobert Mustacchi 283d14abf15SRobert Mustacchi /* preemphasis values for the rx side */ 284d14abf15SRobert Mustacchi u16 rx_preemphasis[4]; 285d14abf15SRobert Mustacchi 286d14abf15SRobert Mustacchi /* preemphasis values for the tx side */ 287d14abf15SRobert Mustacchi u16 tx_preemphasis[4]; 288d14abf15SRobert Mustacchi 289d14abf15SRobert Mustacchi /* EMAC address for access MDIO */ 290d14abf15SRobert Mustacchi u32 mdio_ctrl; 291d14abf15SRobert Mustacchi 292d14abf15SRobert Mustacchi u32 supported; 293d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_10baseT_Half (1<<0) 294d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_10baseT_Full (1<<1) 295d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_100baseT_Half (1<<2) 296d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_100baseT_Full (1<<3) 297d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_1000baseT_Full (1<<4) 298d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_2500baseX_Full (1<<5) 299d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_10000baseT_Full (1<<6) 300d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_TP (1<<7) 301d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_FIBRE (1<<8) 302d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_Autoneg (1<<9) 303d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_Pause (1<<10) 304d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_Asym_Pause (1<<11) 305d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21) 306d14abf15SRobert Mustacchi #define ELINK_SUPPORTED_20000baseKR2_Full (1<<22) 307d14abf15SRobert Mustacchi 308d14abf15SRobert Mustacchi u32 media_type; 309d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_UNSPECIFIED 0x0 310d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1 311d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_XFP_FIBER 0x2 312d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_DA_TWINAX 0x3 313d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_BASE_T 0x4 314d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5 315d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_KR 0xf0 316d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_CX4 0xf1 317d14abf15SRobert Mustacchi #define ELINK_ETH_PHY_NOT_PRESENT 0xff 318d14abf15SRobert Mustacchi 319*b01ab2deSRobert Mustacchi u32 sfp_media; 320*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_UNKNOWN 0x00 321*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_DAC 0x01 322*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_ACC 0x02 323*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_1GBASE_T 0x03 324*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_1GBASE_SX 0x04 325*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_1GBASE_LX 0x05 326*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_1GBASE_CX 0x06 327*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_10GBASE_SR 0x07 328*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_10GBASE_LR 0x09 329*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_10GBASE_LRM 0x09 330*b01ab2deSRobert Mustacchi #define ELINK_ETH_SFP_10GBASE_ER 0x0a 331*b01ab2deSRobert Mustacchi 332d14abf15SRobert Mustacchi /* The address in which version is located*/ 333d14abf15SRobert Mustacchi u32 ver_addr; 334d14abf15SRobert Mustacchi 335d14abf15SRobert Mustacchi u16 req_flow_ctrl; 336d14abf15SRobert Mustacchi 337d14abf15SRobert Mustacchi u16 req_line_speed; 338d14abf15SRobert Mustacchi 339d14abf15SRobert Mustacchi u32 speed_cap_mask; 340d14abf15SRobert Mustacchi 341d14abf15SRobert Mustacchi u16 req_duplex; 342d14abf15SRobert Mustacchi u16 rsrv; 343d14abf15SRobert Mustacchi /* Called per phy/port init, and it configures LASI, speed, autoneg, 344d14abf15SRobert Mustacchi duplex, flow control negotiation, etc. */ 345d14abf15SRobert Mustacchi config_init_t config_init; 346d14abf15SRobert Mustacchi 347d14abf15SRobert Mustacchi /* Called due to interrupt. It determines the link, speed */ 348d14abf15SRobert Mustacchi read_status_t read_status; 349d14abf15SRobert Mustacchi 350d14abf15SRobert Mustacchi /* Called when driver is unloading. Should reset the phy */ 351d14abf15SRobert Mustacchi link_reset_t link_reset; 352d14abf15SRobert Mustacchi 353d14abf15SRobert Mustacchi /* Set the loopback configuration for the phy */ 354d14abf15SRobert Mustacchi config_loopback_t config_loopback; 355d14abf15SRobert Mustacchi 356d14abf15SRobert Mustacchi /* Format the given raw number into str up to len */ 357d14abf15SRobert Mustacchi format_fw_ver_t format_fw_ver; 358d14abf15SRobert Mustacchi 359d14abf15SRobert Mustacchi /* Reset the phy (both ports) */ 360d14abf15SRobert Mustacchi hw_reset_t hw_reset; 361d14abf15SRobert Mustacchi 362d14abf15SRobert Mustacchi /* Set link led mode (on/off/oper)*/ 363d14abf15SRobert Mustacchi set_link_led_t set_link_led; 364d14abf15SRobert Mustacchi 365d14abf15SRobert Mustacchi /* PHY Specific tasks */ 366d14abf15SRobert Mustacchi phy_specific_func_t phy_specific_func; 367d14abf15SRobert Mustacchi #define ELINK_DISABLE_TX 1 368d14abf15SRobert Mustacchi #define ELINK_ENABLE_TX 2 369d14abf15SRobert Mustacchi #define ELINK_PHY_INIT 3 370d14abf15SRobert Mustacchi }; 371d14abf15SRobert Mustacchi 372d14abf15SRobert Mustacchi /* Inputs parameters to the CLC */ 373d14abf15SRobert Mustacchi struct elink_params { 374d14abf15SRobert Mustacchi 375d14abf15SRobert Mustacchi u8 port; 376d14abf15SRobert Mustacchi 377d14abf15SRobert Mustacchi /* Default / User Configuration */ 378d14abf15SRobert Mustacchi u8 loopback_mode; 379d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_NONE 0 380d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_EMAC 1 381d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_BMAC 2 382d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_XGXS 3 383d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_EXT_PHY 4 384d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_EXT 5 385d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_UMAC 6 386d14abf15SRobert Mustacchi #define ELINK_LOOPBACK_XMAC 7 387d14abf15SRobert Mustacchi 388d14abf15SRobert Mustacchi /* Device parameters */ 389d14abf15SRobert Mustacchi u8 mac_addr[6]; 390d14abf15SRobert Mustacchi 391d14abf15SRobert Mustacchi u16 req_duplex[ELINK_LINK_CONFIG_SIZE]; 392d14abf15SRobert Mustacchi u16 req_flow_ctrl[ELINK_LINK_CONFIG_SIZE]; 393d14abf15SRobert Mustacchi 394d14abf15SRobert Mustacchi u16 req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */ 395d14abf15SRobert Mustacchi 396d14abf15SRobert Mustacchi /* shmem parameters */ 397d14abf15SRobert Mustacchi u32 shmem_base; 398d14abf15SRobert Mustacchi u32 shmem2_base; 399d14abf15SRobert Mustacchi u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE]; 400d14abf15SRobert Mustacchi u32 switch_cfg; 401d14abf15SRobert Mustacchi #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH 402d14abf15SRobert Mustacchi #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH 403d14abf15SRobert Mustacchi #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 404d14abf15SRobert Mustacchi 405d14abf15SRobert Mustacchi u32 lane_config; 406d14abf15SRobert Mustacchi 407d14abf15SRobert Mustacchi /* Phy register parameter */ 408d14abf15SRobert Mustacchi u32 chip_id; 409d14abf15SRobert Mustacchi 410d14abf15SRobert Mustacchi /* features */ 411d14abf15SRobert Mustacchi u32 feature_config_flags; 412d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 413d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1) 414d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2) 415d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3) 416d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4) 417d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5) 418d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6) 419d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7) 420d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8) 421d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9) 422d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10) 423d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11) 424d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12) 425d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13) 426d14abf15SRobert Mustacchi #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14) 427d14abf15SRobert Mustacchi 428d14abf15SRobert Mustacchi /* Will be populated during common init */ 429d14abf15SRobert Mustacchi struct elink_phy phy[ELINK_MAX_PHYS]; 430d14abf15SRobert Mustacchi 431d14abf15SRobert Mustacchi /* Will be populated during common init */ 432d14abf15SRobert Mustacchi u8 num_phys; 433d14abf15SRobert Mustacchi 434d14abf15SRobert Mustacchi u8 rsrv; 435d14abf15SRobert Mustacchi 436d14abf15SRobert Mustacchi /* Used to configure the EEE Tx LPI timer, has several modes of 437d14abf15SRobert Mustacchi * operation, according to bits 29:28 - 438d14abf15SRobert Mustacchi * 2'b00: Timer will be configured by nvram, output will be the value 439d14abf15SRobert Mustacchi * from nvram. 440d14abf15SRobert Mustacchi * 2'b01: Timer will be configured by nvram, output will be in 441d14abf15SRobert Mustacchi * microseconds. 442d14abf15SRobert Mustacchi * 2'b10: bits 1:0 contain an nvram value which will be used instead 443d14abf15SRobert Mustacchi * of the one located in the nvram. Output will be that value. 444d14abf15SRobert Mustacchi * 2'b11: bits 19:0 contain the idle timer in microseconds; output 445d14abf15SRobert Mustacchi * will be in microseconds. 446d14abf15SRobert Mustacchi * Bits 31:30 should be 2'b11 in order for EEE to be enabled. 447d14abf15SRobert Mustacchi */ 448d14abf15SRobert Mustacchi u32 eee_mode; 449d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00) 450d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100) 451d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000) 452d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_NVRAM_MASK (0x3) 453d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_TIMER_MASK (0xfffff) 454d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_OUTPUT_TIME (1<<28) 455d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29) 456d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_ENABLE_LPI (1<<30) 457d14abf15SRobert Mustacchi #define ELINK_EEE_MODE_ADV_LPI (1<<31) 458d14abf15SRobert Mustacchi 459d14abf15SRobert Mustacchi u16 hw_led_mode; /* part of the hw_config read from the shmem */ 460d14abf15SRobert Mustacchi u32 multi_phy_config; 461d14abf15SRobert Mustacchi 462d14abf15SRobert Mustacchi /* Device pointer passed to all callback functions */ 463d14abf15SRobert Mustacchi struct elink_dev *cb; 464d14abf15SRobert Mustacchi u16 req_fc_auto_adv; /* Should be set to TX / BOTH when 465d14abf15SRobert Mustacchi req_flow_ctrl is set to AUTO */ 466d14abf15SRobert Mustacchi u16 link_flags; 467d14abf15SRobert Mustacchi #define ELINK_LINK_FLAGS_INT_DISABLED (1<<0) 468d14abf15SRobert Mustacchi #define ELINK_PHY_INITIALIZED (1<<1) 469d14abf15SRobert Mustacchi u32 lfa_base; 470d14abf15SRobert Mustacchi 471d14abf15SRobert Mustacchi /* The same definitions as the shmem2 parameter */ 472d14abf15SRobert Mustacchi u32 link_attr_sync; 473d14abf15SRobert Mustacchi }; 474d14abf15SRobert Mustacchi 475d14abf15SRobert Mustacchi /* Output parameters */ 476d14abf15SRobert Mustacchi struct elink_vars { 477d14abf15SRobert Mustacchi u8 phy_flags; 478d14abf15SRobert Mustacchi #define PHY_XGXS_FLAG (1<<0) 479d14abf15SRobert Mustacchi #define PHY_SGMII_FLAG (1<<1) 480d14abf15SRobert Mustacchi #define PHY_PHYSICAL_LINK_FLAG (1<<2) 481d14abf15SRobert Mustacchi #define PHY_HALF_OPEN_CONN_FLAG (1<<3) 482d14abf15SRobert Mustacchi #define PHY_OVER_CURRENT_FLAG (1<<4) 483d14abf15SRobert Mustacchi #define PHY_SFP_TX_FAULT_FLAG (1<<5) 484d14abf15SRobert Mustacchi 485d14abf15SRobert Mustacchi u8 mac_type; 486d14abf15SRobert Mustacchi #define ELINK_MAC_TYPE_NONE 0 487d14abf15SRobert Mustacchi #define ELINK_MAC_TYPE_EMAC 1 488d14abf15SRobert Mustacchi #define ELINK_MAC_TYPE_BMAC 2 489d14abf15SRobert Mustacchi #define ELINK_MAC_TYPE_UMAC 3 490d14abf15SRobert Mustacchi #define ELINK_MAC_TYPE_XMAC 4 491d14abf15SRobert Mustacchi 492d14abf15SRobert Mustacchi u8 phy_link_up; /* internal phy link indication */ 493d14abf15SRobert Mustacchi u8 link_up; 494d14abf15SRobert Mustacchi 495d14abf15SRobert Mustacchi u16 line_speed; 496d14abf15SRobert Mustacchi u16 duplex; 497d14abf15SRobert Mustacchi 498d14abf15SRobert Mustacchi u16 flow_ctrl; 499d14abf15SRobert Mustacchi u16 ieee_fc; 500d14abf15SRobert Mustacchi 501d14abf15SRobert Mustacchi /* The same definitions as the shmem parameter */ 502d14abf15SRobert Mustacchi u32 link_status; 503d14abf15SRobert Mustacchi u32 eee_status; 504d14abf15SRobert Mustacchi u8 fault_detected; 505d14abf15SRobert Mustacchi u8 check_kr2_recovery_cnt; 506d14abf15SRobert Mustacchi #define ELINK_CHECK_KR2_RECOVERY_CNT 5 507d14abf15SRobert Mustacchi u16 periodic_flags; 508d14abf15SRobert Mustacchi #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001 509d14abf15SRobert Mustacchi 510d14abf15SRobert Mustacchi u32 aeu_int_mask; 511d14abf15SRobert Mustacchi u8 rx_tx_asic_rst; 512d14abf15SRobert Mustacchi u8 turn_to_run_wc_rt; 513d14abf15SRobert Mustacchi u16 rsrv2; 514d14abf15SRobert Mustacchi 515d14abf15SRobert Mustacchi }; 516d14abf15SRobert Mustacchi 517d14abf15SRobert Mustacchi /***********************************************************/ 518d14abf15SRobert Mustacchi /* Functions */ 519d14abf15SRobert Mustacchi /***********************************************************/ 520d14abf15SRobert Mustacchi elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars); 521d14abf15SRobert Mustacchi 522d14abf15SRobert Mustacchi #ifndef EXCLUDE_LINK_RESET 523d14abf15SRobert Mustacchi /* Reset the link. Should be called when driver or interface goes down 524d14abf15SRobert Mustacchi Before calling phy firmware upgrade, the reset_ext_phy should be set 525d14abf15SRobert Mustacchi to 0 */ 526d14abf15SRobert Mustacchi elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 527d14abf15SRobert Mustacchi u8 reset_ext_phy); 528d14abf15SRobert Mustacchi #endif 529d14abf15SRobert Mustacchi elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars); 530d14abf15SRobert Mustacchi /* elink_link_update should be called upon link interrupt */ 531d14abf15SRobert Mustacchi elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars); 532d14abf15SRobert Mustacchi 533d14abf15SRobert Mustacchi /* use the following phy functions to read/write from external_phy 534d14abf15SRobert Mustacchi In order to use it to read/write internal phy registers, use 535d14abf15SRobert Mustacchi ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as 536d14abf15SRobert Mustacchi the register */ 537d14abf15SRobert Mustacchi elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr, 538d14abf15SRobert Mustacchi u8 devad, u16 reg, u16 *ret_val); 539d14abf15SRobert Mustacchi 540d14abf15SRobert Mustacchi elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr, 541d14abf15SRobert Mustacchi u8 devad, u16 reg, u16 val); 542d14abf15SRobert Mustacchi 543d14abf15SRobert Mustacchi /* Reads the link_status from the shmem, 544d14abf15SRobert Mustacchi and update the link vars accordingly */ 545d14abf15SRobert Mustacchi void elink_link_status_update(struct elink_params *input, 546d14abf15SRobert Mustacchi struct elink_vars *output); 547d14abf15SRobert Mustacchi #ifdef ELINK_ENHANCEMENTS 548d14abf15SRobert Mustacchi /* returns string representing the fw_version of the external phy */ 549d14abf15SRobert Mustacchi elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version, 550d14abf15SRobert Mustacchi u16 len); 551d14abf15SRobert Mustacchi #endif 552d14abf15SRobert Mustacchi 553d14abf15SRobert Mustacchi /* Set/Unset the led 554d14abf15SRobert Mustacchi Basically, the CLC takes care of the led for the link, but in case one needs 555d14abf15SRobert Mustacchi to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to 556d14abf15SRobert Mustacchi blink the led, and ELINK_LED_MODE_OFF to set the led off.*/ 557d14abf15SRobert Mustacchi elink_status_t elink_set_led(struct elink_params *params, 558d14abf15SRobert Mustacchi struct elink_vars *vars, u8 mode, u32 speed); 559d14abf15SRobert Mustacchi #define ELINK_LED_MODE_OFF 0 560d14abf15SRobert Mustacchi #define ELINK_LED_MODE_ON 1 561d14abf15SRobert Mustacchi #define ELINK_LED_MODE_OPER 2 562d14abf15SRobert Mustacchi #define ELINK_LED_MODE_FRONT_PANEL_OFF 3 563d14abf15SRobert Mustacchi 564d14abf15SRobert Mustacchi #ifdef ELINK_ENHANCEMENTS 565d14abf15SRobert Mustacchi /* elink_handle_module_detect_int should be called upon module detection 566d14abf15SRobert Mustacchi interrupt */ 567d14abf15SRobert Mustacchi void elink_handle_module_detect_int(struct elink_params *params); 568d14abf15SRobert Mustacchi 569d14abf15SRobert Mustacchi /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up, 570d14abf15SRobert Mustacchi otherwise link is down*/ 571d14abf15SRobert Mustacchi elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 572d14abf15SRobert Mustacchi u8 is_serdes); 573d14abf15SRobert Mustacchi 574d14abf15SRobert Mustacchi #endif 575d14abf15SRobert Mustacchi 576d14abf15SRobert Mustacchi /* One-time initialization for external phy after power up */ 577d14abf15SRobert Mustacchi elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[], 578d14abf15SRobert Mustacchi u32 shmem2_base_path[], u32 chip_id, u8 one_port_enabled); 579d14abf15SRobert Mustacchi 580d14abf15SRobert Mustacchi /* Reset the external PHY using GPIO */ 581d14abf15SRobert Mustacchi void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port); 582d14abf15SRobert Mustacchi 583d14abf15SRobert Mustacchi #ifdef ELINK_ENHANCEMENTS 584d14abf15SRobert Mustacchi /* Reset the external of SFX7101 */ 585d14abf15SRobert Mustacchi void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy); 586d14abf15SRobert Mustacchi #endif 587d14abf15SRobert Mustacchi 588d14abf15SRobert Mustacchi /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */ 589d14abf15SRobert Mustacchi elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 590d14abf15SRobert Mustacchi struct elink_params *params, u8 dev_addr, 591d14abf15SRobert Mustacchi u16 addr, u16 byte_cnt, u8 *o_buf); 592d14abf15SRobert Mustacchi 593d14abf15SRobert Mustacchi void elink_hw_reset_phy(struct elink_params *params); 594d14abf15SRobert Mustacchi 595d14abf15SRobert Mustacchi /* Check swap bit and adjust PHY order */ 596d14abf15SRobert Mustacchi u32 elink_phy_selection(struct elink_params *params); 597d14abf15SRobert Mustacchi 598d14abf15SRobert Mustacchi #ifndef EXCLUDE_COMMON_INIT 599d14abf15SRobert Mustacchi /* Probe the phys on board, and populate them in "params" */ 600d14abf15SRobert Mustacchi elink_status_t elink_phy_probe(struct elink_params *params); 601d14abf15SRobert Mustacchi 602d14abf15SRobert Mustacchi /* Checks if fan failure detection is required on one of the phys on board */ 603d14abf15SRobert Mustacchi u8 elink_fan_failure_det_req(struct elink_dev *cb, u32 shmem_base, 604d14abf15SRobert Mustacchi u32 shmem2_base, u8 port); 605d14abf15SRobert Mustacchi 606d14abf15SRobert Mustacchi /* Open / close the gate between the NIG and the BRB */ 607d14abf15SRobert Mustacchi void elink_set_rx_filter(struct elink_params *params, u8 en); 608d14abf15SRobert Mustacchi #endif /* EXCLUDE_COMMON_INIT */ 609d14abf15SRobert Mustacchi 610d14abf15SRobert Mustacchi /* DCBX structs */ 611d14abf15SRobert Mustacchi 612d14abf15SRobert Mustacchi /* Number of maximum COS per chip */ 613d14abf15SRobert Mustacchi #define ELINK_DCBX_E2E3_MAX_NUM_COS (2) 614d14abf15SRobert Mustacchi #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6) 615d14abf15SRobert Mustacchi #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3) 616d14abf15SRobert Mustacchi #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \ 617d14abf15SRobert Mustacchi ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \ 618d14abf15SRobert Mustacchi ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1)) 619d14abf15SRobert Mustacchi 620d14abf15SRobert Mustacchi #define ELINK_DCBX_MAX_NUM_COS ( \ 621d14abf15SRobert Mustacchi ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \ 622d14abf15SRobert Mustacchi ELINK_DCBX_E2E3_MAX_NUM_COS)) 623d14abf15SRobert Mustacchi 624d14abf15SRobert Mustacchi /* PFC port configuration params */ 625d14abf15SRobert Mustacchi struct elink_nig_brb_pfc_port_params { 626d14abf15SRobert Mustacchi /* NIG */ 627d14abf15SRobert Mustacchi u32 pause_enable; 628d14abf15SRobert Mustacchi u32 llfc_out_en; 629d14abf15SRobert Mustacchi u32 llfc_enable; 630d14abf15SRobert Mustacchi u32 pkt_priority_to_cos; 631d14abf15SRobert Mustacchi u8 num_of_rx_cos_priority_mask; 632d14abf15SRobert Mustacchi u32 rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS]; 633d14abf15SRobert Mustacchi u32 llfc_high_priority_classes; 634d14abf15SRobert Mustacchi u32 llfc_low_priority_classes; 635d14abf15SRobert Mustacchi }; 636d14abf15SRobert Mustacchi 637d14abf15SRobert Mustacchi 638d14abf15SRobert Mustacchi /* ETS port configuration params */ 639d14abf15SRobert Mustacchi struct elink_ets_bw_params { 640d14abf15SRobert Mustacchi u8 bw; 641d14abf15SRobert Mustacchi }; 642d14abf15SRobert Mustacchi 643d14abf15SRobert Mustacchi struct elink_ets_sp_params { 644d14abf15SRobert Mustacchi /** 645d14abf15SRobert Mustacchi * valid values are 0 - 5. 0 is highest strict priority. 646d14abf15SRobert Mustacchi * There can't be two COS's with the same pri. 647d14abf15SRobert Mustacchi */ 648d14abf15SRobert Mustacchi u8 pri; 649d14abf15SRobert Mustacchi }; 650d14abf15SRobert Mustacchi 651d14abf15SRobert Mustacchi enum elink_cos_state { 652d14abf15SRobert Mustacchi elink_cos_state_strict = 0, 653d14abf15SRobert Mustacchi elink_cos_state_bw = 1, 654d14abf15SRobert Mustacchi }; 655d14abf15SRobert Mustacchi 656d14abf15SRobert Mustacchi struct elink_ets_cos_params { 657d14abf15SRobert Mustacchi enum elink_cos_state state ; 658d14abf15SRobert Mustacchi union { 659d14abf15SRobert Mustacchi struct elink_ets_bw_params bw_params; 660d14abf15SRobert Mustacchi struct elink_ets_sp_params sp_params; 661d14abf15SRobert Mustacchi } params; 662d14abf15SRobert Mustacchi }; 663d14abf15SRobert Mustacchi 664d14abf15SRobert Mustacchi struct elink_ets_params { 665d14abf15SRobert Mustacchi u8 num_of_cos; /* Number of valid COS entries*/ 666d14abf15SRobert Mustacchi struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS]; 667d14abf15SRobert Mustacchi }; 668d14abf15SRobert Mustacchi 669d14abf15SRobert Mustacchi /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB 670d14abf15SRobert Mustacchi * when link is already up 671d14abf15SRobert Mustacchi */ 672d14abf15SRobert Mustacchi elink_status_t elink_update_pfc(struct elink_params *params, 673d14abf15SRobert Mustacchi struct elink_vars *vars, 674d14abf15SRobert Mustacchi struct elink_nig_brb_pfc_port_params *pfc_params); 675d14abf15SRobert Mustacchi 676d14abf15SRobert Mustacchi 677d14abf15SRobert Mustacchi /* Used to configure the ETS to disable */ 678d14abf15SRobert Mustacchi elink_status_t elink_ets_disabled(struct elink_params *params, 679d14abf15SRobert Mustacchi struct elink_vars *vars); 680d14abf15SRobert Mustacchi 681d14abf15SRobert Mustacchi /* Used to configure the ETS to BW limited */ 682d14abf15SRobert Mustacchi void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw, 683d14abf15SRobert Mustacchi const u32 cos1_bw); 684d14abf15SRobert Mustacchi 685d14abf15SRobert Mustacchi /* Used to configure the ETS to strict */ 686d14abf15SRobert Mustacchi elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos); 687d14abf15SRobert Mustacchi 688d14abf15SRobert Mustacchi 689d14abf15SRobert Mustacchi /* Configure the COS to ETS according to BW and SP settings.*/ 690d14abf15SRobert Mustacchi elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 691d14abf15SRobert Mustacchi const struct elink_vars *vars, 692d14abf15SRobert Mustacchi struct elink_ets_params *ets_params); 693d14abf15SRobert Mustacchi /* Read pfc statistic*/ 694d14abf15SRobert Mustacchi #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 695d14abf15SRobert Mustacchi void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 696d14abf15SRobert Mustacchi u32 pfc_frames_sent[2], 697d14abf15SRobert Mustacchi u32 pfc_frames_received[2]); 698d14abf15SRobert Mustacchi #endif 699d14abf15SRobert Mustacchi void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars, 700d14abf15SRobert Mustacchi u32 chip_id, u32 shmem_base, u32 shmem2_base, 701d14abf15SRobert Mustacchi u8 port); 702d14abf15SRobert Mustacchi #ifndef BNX2X_ADD /* ! BNX2X_ADD */ 703d14abf15SRobert Mustacchi elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 704d14abf15SRobert Mustacchi struct elink_params *params); 705d14abf15SRobert Mustacchi #endif 706d14abf15SRobert Mustacchi 707d14abf15SRobert Mustacchi void elink_period_func(struct elink_params *params, struct elink_vars *vars); 708d14abf15SRobert Mustacchi 709d14abf15SRobert Mustacchi #ifndef BNX2X_ADD /* ! BNX2X_ADD */ 710d14abf15SRobert Mustacchi elink_status_t elink_check_half_open_conn(struct elink_params *params, 711d14abf15SRobert Mustacchi struct elink_vars *vars, u8 notify); 712d14abf15SRobert Mustacchi #endif 713d14abf15SRobert Mustacchi 714d14abf15SRobert Mustacchi void elink_enable_pmd_tx(struct elink_params *params); 715d14abf15SRobert Mustacchi 716d14abf15SRobert Mustacchi #ifndef EXCLUDE_FROM_BNX2X 717d14abf15SRobert Mustacchi elink_status_t elink_pre_init_phy(struct elink_dev *cb, 718d14abf15SRobert Mustacchi u32 shmem_base, 719d14abf15SRobert Mustacchi u32 shmem2_base, 720d14abf15SRobert Mustacchi u32 chip_id, 721d14abf15SRobert Mustacchi u8 port); 722d14abf15SRobert Mustacchi elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf); 723d14abf15SRobert Mustacchi 724d14abf15SRobert Mustacchi #endif /* EXCLUDE_FROM_BNX2X */ 725d14abf15SRobert Mustacchi #ifdef ELINK_AUX_POWER 726d14abf15SRobert Mustacchi void elink_adjust_phy_func_ptr(struct elink_params *params); 727d14abf15SRobert Mustacchi 728d14abf15SRobert Mustacchi elink_status_t elink_get_phy_temperature(struct elink_params *params, 729d14abf15SRobert Mustacchi u32 *temp_reading, u8 path, u8 port); 730d14abf15SRobert Mustacchi 731d14abf15SRobert Mustacchi u8 elink_phy_is_temperature_support(struct elink_params *params); 732d14abf15SRobert Mustacchi void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val); 733d14abf15SRobert Mustacchi int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val); 734d14abf15SRobert Mustacchi int elink_warpcore_get_sigdet(struct elink_phy *phy, 735d14abf15SRobert Mustacchi struct elink_params *params); 736d14abf15SRobert Mustacchi void elink_force_link(struct elink_params *params, int enable); 737d14abf15SRobert Mustacchi #endif 738d14abf15SRobert Mustacchi 739d14abf15SRobert Mustacchi #endif /* __ELINK_H */ 740d14abf15SRobert Mustacchi 741