1*d14abf15SRobert Mustacchi /* 2*d14abf15SRobert Mustacchi ******************************************************************************** 3*d14abf15SRobert Mustacchi * $Id: //servers/main/nx2/577xx/hsi/microcode/rdma/headers/rdma_constants.h#39 $ 4*d14abf15SRobert Mustacchi ******************************************************************************** 5*d14abf15SRobert Mustacchi * $Name: $ 6*d14abf15SRobert Mustacchi ******************************************************************************** 7*d14abf15SRobert Mustacchi * $Date: 2007/11/13 $ 8*d14abf15SRobert Mustacchi ******************************************************************************** 9*d14abf15SRobert Mustacchi * $Revision: #39 $ 10*d14abf15SRobert Mustacchi ******************************************************************************** 11*d14abf15SRobert Mustacchi * $Author: yaronu $ 12*d14abf15SRobert Mustacchi ******************************************************************************** 13*d14abf15SRobert Mustacchi * $Log: rdma_constants.h,v $ 14*d14abf15SRobert Mustacchi * Revision 1.37 2007/06/13 11:46:43 yanivr 15*d14abf15SRobert Mustacchi * Add support for RDMA classifier in favor of the Eth 16*d14abf15SRobert Mustacchi * 17*d14abf15SRobert Mustacchi * Revision 1.36 2007/05/31 14:38:45 yanivr 18*d14abf15SRobert Mustacchi * Enhance PCS request/PCS response scheme 19*d14abf15SRobert Mustacchi * 20*d14abf15SRobert Mustacchi * Revision 1.35 2007/05/30 13:35:11 yanivr 21*d14abf15SRobert Mustacchi * Enable L5cm Passive Connection Establishment 22*d14abf15SRobert Mustacchi * 23*d14abf15SRobert Mustacchi * Revision 1.34 2007/04/29 14:58:29 yanivr 24*d14abf15SRobert Mustacchi * Add RDMA_ASYNC_EVENT_PCS_RESPONSE1_SUCCEEDED, RDMA_ASYNC_EVENT_PCS_RESPONSE2_SUCCEEDED, RDMA_ASYNC_EVENT_PCS_RESPONSE3_SUCCEEDED 25*d14abf15SRobert Mustacchi * 26*d14abf15SRobert Mustacchi * Revision 1.33 2007/04/29 12:57:26 yanivr 27*d14abf15SRobert Mustacchi * Add RDMA_RAMROD_CMD_ID_CLOSE_PHY_PORT defines 28*d14abf15SRobert Mustacchi * 29*d14abf15SRobert Mustacchi * Revision 1.32 2007/04/18 18:57:45 yanivr 30*d14abf15SRobert Mustacchi * Add support for L5cm passive side connection establishment 31*d14abf15SRobert Mustacchi * 32*d14abf15SRobert Mustacchi * Revision 1.31 2007/02/22 18:19:11 yanivr 33*d14abf15SRobert Mustacchi * Move common connection establishments ramrods to L5cm 34*d14abf15SRobert Mustacchi * 35*d14abf15SRobert Mustacchi * Revision 1.30 2006/09/19 06:14:39 edreayc 36*d14abf15SRobert Mustacchi * Insert RDMA Error reporting & Invalidation process 37*d14abf15SRobert Mustacchi * 38*d14abf15SRobert Mustacchi * Revision 1.29 2006/08/28 06:32:40 yanivr 39*d14abf15SRobert Mustacchi * Add RDMA_ASYNC_EVENT_UPDATE_ULP_SUCCEEDED event 40*d14abf15SRobert Mustacchi * 41*d14abf15SRobert Mustacchi * Revision 1.28 2006/08/27 15:43:24 yaronu 42*d14abf15SRobert Mustacchi * - removed old include of rdma_eqe struct from rdma_constants 43*d14abf15SRobert Mustacchi * - removed old includes to rdma event report files 44*d14abf15SRobert Mustacchi * - added include to rdma event report structs where needed 45*d14abf15SRobert Mustacchi * 46*d14abf15SRobert Mustacchi * Revision 1.27 2006/08/27 15:18:26 yuvalk 47*d14abf15SRobert Mustacchi * Rdma, Error reporting, Rx 48*d14abf15SRobert Mustacchi * 49*d14abf15SRobert Mustacchi * Revision 1.26 2006/08/22 15:38:05 yuvalk 50*d14abf15SRobert Mustacchi * Rdma - Ustorm, Tstorm Error reporting fixes 51*d14abf15SRobert Mustacchi * 52*d14abf15SRobert Mustacchi * Revision 1.25 2006/08/21 15:39:12 yuvalk 53*d14abf15SRobert Mustacchi * Rdma - added completion code defines for completion errors 54*d14abf15SRobert Mustacchi * 55*d14abf15SRobert Mustacchi * Revision 1.24 2006/08/20 17:00:35 yuvalk 56*d14abf15SRobert Mustacchi * Rdma, Ustorm, Tstorm, Error reporting 57*d14abf15SRobert Mustacchi * 58*d14abf15SRobert Mustacchi * Revision 1.23 2006/08/17 14:39:25 yanivr 59*d14abf15SRobert Mustacchi * Resupport ramrod RDMA_RxLlpSlowPath.cpp 60*d14abf15SRobert Mustacchi * 61*d14abf15SRobert Mustacchi * Revision 1.22 2006/08/13 08:34:49 yaronu 62*d14abf15SRobert Mustacchi * Added some event code constants 63*d14abf15SRobert Mustacchi * 64*d14abf15SRobert Mustacchi * Revision 1.21 2006/07/30 08:42:04 yaronu 65*d14abf15SRobert Mustacchi * renamed SEND_MPA SP command ID to LLP_SEND 66*d14abf15SRobert Mustacchi * 67*d14abf15SRobert Mustacchi * Revision 1.20 2006/07/12 09:51:14 yaronu 68*d14abf15SRobert Mustacchi * Added new slow path command IDs and event codes 69*d14abf15SRobert Mustacchi * 70*d14abf15SRobert Mustacchi * Revision 1.19 2006/06/08 06:27:44 yuvalk 71*d14abf15SRobert Mustacchi * Rdma - 72*d14abf15SRobert Mustacchi * Tstorm - some minor changes to better suite ASM code writting 73*d14abf15SRobert Mustacchi * everest.fmt - added Rdma Xstorm slowPath handler 74*d14abf15SRobert Mustacchi * microcode.vcproj - marked ASM files as excluded from build 75*d14abf15SRobert Mustacchi * 76*d14abf15SRobert Mustacchi * Revision 1.18 2006/05/16 16:25:51 yaronu 77*d14abf15SRobert Mustacchi * - modified rdma slow path handlers for easier translation into ASM 78*d14abf15SRobert Mustacchi * - add function execution counter in rdma driversim 79*d14abf15SRobert Mustacchi * 80*d14abf15SRobert Mustacchi * Revision 1.17 2006/05/15 11:44:21 yuvalk 81*d14abf15SRobert Mustacchi * Rdma - changed "rh" prefix in all rdma hsi structs to be "rdma" 82*d14abf15SRobert Mustacchi * 83*d14abf15SRobert Mustacchi * Revision 1.16 2006/05/11 16:05:06 yaronu 84*d14abf15SRobert Mustacchi * - extended Tstorm slow path handler 85*d14abf15SRobert Mustacchi * - added new Ustorm and Cstorm slow path handlers 86*d14abf15SRobert Mustacchi * - modified output message argument of Cstorm event report handler 87*d14abf15SRobert Mustacchi * 88*d14abf15SRobert Mustacchi * Revision 1.15 2006/05/09 09:38:47 yaronu 89*d14abf15SRobert Mustacchi * updates to event report handlers and driversim after debugging events with terminate messages 90*d14abf15SRobert Mustacchi * 91*d14abf15SRobert Mustacchi * Revision 1.14 2006/05/02 08:07:06 ofirh 92*d14abf15SRobert Mustacchi * HSI changes before microcode and driver entering lab 93*d14abf15SRobert Mustacchi * 94*d14abf15SRobert Mustacchi * Revision 1.13 2006/04/27 16:19:16 yaronu 95*d14abf15SRobert Mustacchi * - updated driversim event handling 96*d14abf15SRobert Mustacchi * - created event report handler in Ustorm 97*d14abf15SRobert Mustacchi * - moved MAX_RAMROD_PER_PORT to hsi 98*d14abf15SRobert Mustacchi * 99*d14abf15SRobert Mustacchi * Revision 1.12 2006/04/25 07:59:45 yaronu 100*d14abf15SRobert Mustacchi * added completion event type 101*d14abf15SRobert Mustacchi * 102*d14abf15SRobert Mustacchi * Revision 1.11 2006/04/24 13:34:53 yaronu 103*d14abf15SRobert Mustacchi * event reporting handler updates 104*d14abf15SRobert Mustacchi * 105*d14abf15SRobert Mustacchi * Revision 1.10 2006/04/23 10:02:26 ofirh 106*d14abf15SRobert Mustacchi * tree change - phase 3 107*d14abf15SRobert Mustacchi * 108*d14abf15SRobert Mustacchi * Revision 1.9 2006/04/16 13:00:04 yaronu 109*d14abf15SRobert Mustacchi * added rdma event processing constants 110*d14abf15SRobert Mustacchi * 111*d14abf15SRobert Mustacchi * Revision 1.8 2006/04/05 08:25:37 yaronu 112*d14abf15SRobert Mustacchi * added handler for rdma error reporting 113*d14abf15SRobert Mustacchi * 114*d14abf15SRobert Mustacchi * Revision 1.7 2006/03/21 13:53:31 yuvalk 115*d14abf15SRobert Mustacchi * Rdma - 116*d14abf15SRobert Mustacchi * uRdmaSend.cpp - Send Received flow implemented and partially tested 117*d14abf15SRobert Mustacchi * uRdmaWriteReadResp - fixed bug when ddpLen == pbeSize 118*d14abf15SRobert Mustacchi * 119*d14abf15SRobert Mustacchi * Revision 1.6 2006/03/09 08:32:08 vitalyo 120*d14abf15SRobert Mustacchi * Started implementing data integrity mechanism 121*d14abf15SRobert Mustacchi * 122*d14abf15SRobert Mustacchi * Revision 1.5 2006/03/06 10:28:57 vitalyo 123*d14abf15SRobert Mustacchi * Adding functionality to test engine module 124*d14abf15SRobert Mustacchi * Adding modify to rts implementation 125*d14abf15SRobert Mustacchi * 126*d14abf15SRobert Mustacchi * Revision 1.4 2006/02/22 09:27:59 yuvalk 127*d14abf15SRobert Mustacchi * Rdma- 128*d14abf15SRobert Mustacchi * RdmaCommon.cpp - StagLoad - first run on code. some bug fixes 129*d14abf15SRobert Mustacchi * uRdmaWriteReadResp.cpp - some minor changes 130*d14abf15SRobert Mustacchi * 131*d14abf15SRobert Mustacchi * Revision 1.3 2006/02/20 09:41:06 yuvalk 132*d14abf15SRobert Mustacchi * Rdma - first run on uRdmaWriteReadResp.cpp 133*d14abf15SRobert Mustacchi * bring up of UstormRdmaSurroundingsRuntime.xml 134*d14abf15SRobert Mustacchi * RamAccessHeader - fixed bug in RAM_ADDR macro 135*d14abf15SRobert Mustacchi * 136*d14abf15SRobert Mustacchi * Revision 1.2 2006/02/13 08:47:18 yuvalk 137*d14abf15SRobert Mustacchi * Rdma - 138*d14abf15SRobert Mustacchi * uRdmaWriteReadResp.cpp 139*d14abf15SRobert Mustacchi * - calling loadPbl function, using 6 PBEs 140*d14abf15SRobert Mustacchi * - change in cache coherency entry structure 141*d14abf15SRobert Mustacchi * 142*d14abf15SRobert Mustacchi * Revision 1.1 2006/02/08 10:39:29 shmulikr 143*d14abf15SRobert Mustacchi * Microcode Hsi include files 144*d14abf15SRobert Mustacchi * 145*d14abf15SRobert Mustacchi ******************************************************************************** 146*d14abf15SRobert Mustacchi */ 147*d14abf15SRobert Mustacchi #ifndef __RDMA_CONSTANTS_H_ 148*d14abf15SRobert Mustacchi #define __RDMA_CONSTANTS_H_ 149*d14abf15SRobert Mustacchi 150*d14abf15SRobert Mustacchi /** 151*d14abf15SRobert Mustacchi * This file defines HSI constants for the RDMA flows 152*d14abf15SRobert Mustacchi */ 153*d14abf15SRobert Mustacchi 154*d14abf15SRobert Mustacchi #include "microcode_constants.h" 155*d14abf15SRobert Mustacchi 156*d14abf15SRobert Mustacchi /* SQ WQE operations */ 157*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_INTERNAL (1 << 7) 158*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_INLINE (1 << 6) 159*d14abf15SRobert Mustacchi 160*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_WRITE (0) 161*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_WRITE_INLINE (EVEREST_SQ_WQE_OP_WRITE | EVEREST_SQ_WQE_OP_INLINE) 162*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_READ (1) 163*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_READ_INVAL_LOCAL (EVEREST_SQ_WQE_OP_READ | EVEREST_SQ_WQE_OP_INTERNAL) 164*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_READ_RESP (2) /* not a WQE opcode - reserved for network opcode only */ 165*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND (3) 166*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_INVAL (4) 167*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_SE (5) 168*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_SE_INVAL (6) 169*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_INLINE (EVEREST_SQ_WQE_OP_SEND | EVEREST_SQ_WQE_OP_INLINE) 170*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_INVAL_INLINE (EVEREST_SQ_WQE_OP_SEND_INVAL | EVEREST_SQ_WQE_OP_INLINE) 171*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_SE_INLINE (EVEREST_SQ_WQE_OP_SEND_SE | EVEREST_SQ_WQE_OP_INLINE) 172*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_SEND_SE_INVAL_INLINE (EVEREST_SQ_WQE_OP_SEND_SE_INVAL | EVEREST_SQ_WQE_OP_INLINE) 173*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_TERMINATE (7) 174*d14abf15SRobert Mustacchi 175*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_BIND_MEM_WINDOW ((8) | EVEREST_SQ_WQE_OP_INTERNAL) 176*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_FAST_MEM_REGISTER ((9) | EVEREST_SQ_WQE_OP_INTERNAL) 177*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_OP_INVAL_LOCAL ((10) | EVEREST_SQ_WQE_OP_INTERNAL) 178*d14abf15SRobert Mustacchi #define EVEREST_SQ_WQE_INVALID_OPCODE (0xFF) 179*d14abf15SRobert Mustacchi 180*d14abf15SRobert Mustacchi /* DDP and RDMAP versions */ 181*d14abf15SRobert Mustacchi #define RDMA_RDMAP_DDP_VERSION_RDMAC (0) /* RDMAP and DDP versions must have the same value hence use the same "define" */ 182*d14abf15SRobert Mustacchi #define RDMA_RDMAP_DDP_VERSION_IETF (1) /* RDMAP and DDP versions must have the same value hence use the same "define" */ 183*d14abf15SRobert Mustacchi 184*d14abf15SRobert Mustacchi /* MPA Markers */ 185*d14abf15SRobert Mustacchi #define RDMA_MPA_USE_MARKERS_FLAG (0x8000) 186*d14abf15SRobert Mustacchi 187*d14abf15SRobert Mustacchi /* CQE constants */ 188*d14abf15SRobert Mustacchi #define RDMA_CQE_TYPE_NON_AGGR (1) 189*d14abf15SRobert Mustacchi #define RDMA_CQE_STATUS_OK (0) 190*d14abf15SRobert Mustacchi 191*d14abf15SRobert Mustacchi /* RQ WQE constants */ 192*d14abf15SRobert Mustacchi #define RDMA_RQ_WQE_SHIFT (6) 193*d14abf15SRobert Mustacchi #define RDMA_RQ_WQE_SGL_SIZE_SMALL (2) /* number of SGES in 64 byte WQE */ 194*d14abf15SRobert Mustacchi #define RDMA_RQ_WQE_SGL_SIZE_BIG (6) /* number of SGES in 128 byte WQE */ 195*d14abf15SRobert Mustacchi 196*d14abf15SRobert Mustacchi /* Slow path commands */ 197*d14abf15SRobert Mustacchi #define RDMA_RAMROD_CMD_ID_SEND_MPA (14) 198*d14abf15SRobert Mustacchi #define RDMA_RAMROD_CMD_ID_UPDATE_ULP (15) 199*d14abf15SRobert Mustacchi #define RDMA_RAMROD_CMD_ID_CLOSE_PHY_PORT (16) 200*d14abf15SRobert Mustacchi 201*d14abf15SRobert Mustacchi /* Terminate message constants */ 202*d14abf15SRobert Mustacchi #define RDMA_MAX_TERMINATE_MESSAGE_SIZE (52) // in bytes 203*d14abf15SRobert Mustacchi 204*d14abf15SRobert Mustacchi 205*d14abf15SRobert Mustacchi #define RDMA_FWD_MODE_L2 (0) 206*d14abf15SRobert Mustacchi #define RDMA_FWD_MODE_RDMA (1) 207*d14abf15SRobert Mustacchi /* Event reporting constants */ 208*d14abf15SRobert Mustacchi 209*d14abf15SRobert Mustacchi // number of elements in the EQ that are reserved for slow path completions, catastrophic error 210*d14abf15SRobert Mustacchi // in case the EQ is (almost) full, and an end of page element 211*d14abf15SRobert Mustacchi #define RESERVED_EQ_ELEMENTS (MAX_RAMRODS_PER_PORT + 2) 212*d14abf15SRobert Mustacchi 213*d14abf15SRobert Mustacchi // Event types 214*d14abf15SRobert Mustacchi #define RDMA_EVENT_TYPE_ASYNC (0) 215*d14abf15SRobert Mustacchi #define RDMA_EVENT_TYPE_ERROR (1) 216*d14abf15SRobert Mustacchi #define RDMA_EVENT_TYPE_TERMINATE_MESSAGE (2) 217*d14abf15SRobert Mustacchi #define RDMA_EVENT_TYPE_SLOW_PATH_COMPLETION (3) 218*d14abf15SRobert Mustacchi 219*d14abf15SRobert Mustacchi // Source types 220*d14abf15SRobert Mustacchi #define RDMA_SOURCE_TYPE_RNIC (0) 221*d14abf15SRobert Mustacchi #define RDMA_SOURCE_TYPE_QP (1) 222*d14abf15SRobert Mustacchi #define RDMA_SOURCE_TYPE_CQ (2) 223*d14abf15SRobert Mustacchi #define RDMA_SOURCE_TYPE_SRQ (3) 224*d14abf15SRobert Mustacchi 225*d14abf15SRobert Mustacchi // Queue types 226*d14abf15SRobert Mustacchi #define RDMA_QUEUE_TYPE_NONE (0) 227*d14abf15SRobert Mustacchi #define RDMA_QUEUE_TYPE_SQ (1) 228*d14abf15SRobert Mustacchi #define RDMA_QUEUE_TYPE_RQ (2) 229*d14abf15SRobert Mustacchi #define RDMA_QUEUE_TYPE_IRQ (3) 230*d14abf15SRobert Mustacchi #define RDMA_QUEUE_TYPE_SRQ (4) 231*d14abf15SRobert Mustacchi 232*d14abf15SRobert Mustacchi // Asynchronous event types - from Verbs 233*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_CLOSE_COMPLETE (0) 234*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_TERMINATE_MESSAGE_RECEIVED (1) 235*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_CONNECTION_RESET (2) 236*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_CONNECTION_LOST (3) 237*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_INTEGRITY_INVALID_SEGMENT_SIZE (4) 238*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_INTEGRITY_INVALID_CRC (5) 239*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LLP_INTEGRITY_BAD_FPDU (6) 240*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_INVALID_DDP_VERSION (7) 241*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_INVALID_RDMA_VERSION (8) 242*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_UNEXPECTED_OPCODE (9) 243*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_INVALID_DDP_QUEUE_NUMBER (10) 244*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_READ_REQUEST_DISABLED (11) 245*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_WRITE_OR_READ_RESPONSE_DISABLED (12) 246*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_INVALID_READ_REQUEST (13) 247*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_REMOTE_NO_L_BIT (14) 248*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PROTECTION_INVALID_STAG (15) 249*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PROTECTION_TAGGED_BOUNDS_VIOLATION (16) 250*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PROTECTION_TAGGED_ACCESS_VIOLATION (17) 251*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PROTECTION_TAGGED_INVALID_PD (18) 252*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PROTECTION_WRAP_ERROR (19) 253*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_BAD_CLOSE (20) 254*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_BAD_LLP_CLOSE (21) 255*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RQ_PROTECTION_INVALID_MSN_RANGE (22) 256*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RQ_PROTECTION_INVALID_MSN_GAP (23) 257*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_TOO_MANY_READ_REQUEST (24) 258*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_INVALID_MSN_GAP (25) 259*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_INVALID_MSN_RANGE (26) 260*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_INVALID_STAG (27) 261*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_TAGGED_BOUNDS_VIOLATION (28) 262*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_TAGGED_ACCESS_VIOLATION (29) 263*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_TAGGED_INVALID_PD (30) 264*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_IRQ_PROTECTION_WRAP_ERROR (31) 265*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SQ_COMPLETION_CQ_OVERFLOW (32) 266*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RQ_COMPLETION_CQ_OPERATION_ERROR (33) 267*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SRQ_ERROR_ON_QP (34) 268*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LOCAL_QP_CATASTROPHIC_ERROR (35) 269*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CQ_OVERFLOW (36) 270*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CQ_OPERATION_ERROR (37) 271*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SRQ_LIMIT_REACHED (38) 272*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RQ_LIMIT_REACHED (39) 273*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SRQ_CATASTROPHIC_ERROR (40) 274*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RNIC_CATASTROPHIC_ERROR (41) 275*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_COMPLETION (42) 276*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SLOW_PATH_COMPLETION_SUCCEEDED (43) 277*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SLOW_PATH_COMPLETION_FAILED (44) 278*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CONNECTION_LIMIT_REACHED (45) 279*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_ADD_NEW_CONNECTION_SUCCEEDED (46) 280*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CONNECT_SUCCEEDED (47) 281*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_SEND_MPA_SUCCEEDED (48) 282*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CONNECT_COMPLETE_SUCCEEDED (49) 283*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CONNECT_COMPLETE_FAILED (50) 284*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RECEIVED_MPA_SUCCEEDED (51) 285*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_UPDATE_ULP_SUCCEEDED (52) 286*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_REQUEST1 (53) // SYN RECEIVED 287*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_REQUEST2 (54) // Final-Ack received with MPA request 288*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_REQUEST3 (55) // Final-Ack received with DDP segment 289*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_REQUEST4 (56) // send segment through the forward channel 290*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_RESPONSE1_SUCCEEDED (57) 291*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_RESPONSE2_SUCCEEDED (58) 292*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_RESPONSE3_SUCCEEDED (59) 293*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_RESPONSE4_SUCCEEDED (60) 294*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_PCS_RESPONSE_FAILED (61) 295*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_INIT_SEED_SUCCEEDED (62) 296*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_UPDATE_SEED_SUCCEEDED (63) 297*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_CLOSE_PHY_PORT_SUCCEEDED (64) 298*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERROR (65) 299*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_REGION_STAG (66) // bind/FR 300*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_WINDOW_STAG (67) // bind//FR 301*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_BASE_AND_BOUNDS_VIOLATION (68) //Bind 302*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_RIGHTS_ACCESS_VIOLATION (69) //Bind 303*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_STAG_NOT_IN_INVALID_STATE (70) // fast-register, bind 304*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_MR_NOT_IN_VALID_STATE (71) // fast-register, bind 305*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_PD_ID (72) // fast-register, bind //used 306*d14abf15SRobert Mustacchi 307*d14abf15SRobert Mustacchi 308*d14abf15SRobert Mustacchi // Asyncronous event types <--> Completion status codes (Everest specific) 309*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_QP_CATASTROPHIC_ERROR (254) 310*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_REMOTE_TERMINATION_ERROR (253) 311*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_STAG (252) 312*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_ACCESS_VIOLATION (251) 313*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_PD (250) 314*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_WRAP_ERROR (249) 315*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALIDATE_STAG_PD_OR_ACCESS_RIGHTS_ERROR (248) 316*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_ZERO_ORD (247) 317*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_QP_NOT_IN_PRIVILEGED_MODE (246) // fast-register 318*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_PAGE_SIZE (245) // fast-register 319*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_PHYSICAL_BUFFER_SIZE (244) // fast-register 320*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_PHYSICAL_BUFFER_LIST_ENTRY (243) // fast-register 321*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_FBO (242) // fast-register 322*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_FR_LENGTH (241) // fast-register 323*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_ACCESS_RIGHTS (240) // fast-register 324*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_PHYSICAL_BUFFER_LIST_TOO_LONG (239) // fast-register 325*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_VA (238) // fast-register 326*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_LENGTH (237) 327*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_TRYING_TO_BIND_AND_QP_DOESNT_SUPPORT_BIND (236) // bind 328*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_MR_DOESNT_HAVE_BIND_MW_PREEMPTION (235) // bind 329*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_STAG_KEY_DOESNT_MATCH (234) // bind 330*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_MR_IS_ZERO_BASED (233) //bind 331*d14abf15SRobert Mustacchi 332*d14abf15SRobert Mustacchi #define RDMA_COMPLETION_CODE_INVALID_WQE (232) 333*d14abf15SRobert Mustacchi 334*d14abf15SRobert Mustacchi // Everest specific async events 335*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_RQ_EMPTY (85) 336*d14abf15SRobert Mustacchi 337*d14abf15SRobert Mustacchi 338*d14abf15SRobert Mustacchi #define RDMA_ASYNC_EVENT_INVALID_EVENT (0xFF) 339*d14abf15SRobert Mustacchi 340*d14abf15SRobert Mustacchi 341*d14abf15SRobert Mustacchi // Terminate codes 342*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_CLOSE_COMPLETE (0) 343*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_TERMINATE_MESSAGE_RECEIVED (0) 344*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_CONNECTION_RESET (0) 345*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_CONNECTION_LOST (0) 346*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_INTEGRITY_INVALID_SEGMENT_SIZE (0x1000) 347*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_INTEGRITY_INVALID_CRC (0x0202) 348*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LLP_INTEGRITY_BAD_FPDU (0x0203) 349*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_INVALID_DDP_VERSION (0x1206) 350*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_INVALID_RDMA_VERSION (0x0205) 351*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_UNEXPECTED_OPCODE (0x0206) 352*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_INVALID_DDP_QUEUE_NUMBER (0x1201) 353*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_READ_REQUEST_DISABLED (0x1201) 354*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_WRITE_OR_READ_RESPONSE_DISABLED (0) 355*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_INVALID_READ_REQUEST (0) 356*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_REMOTE_NO_L_BIT (0x0207) 357*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_PROTECTION_INVALID_STAG (0x1100) 358*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_PROTECTION_TAGGED_BOUNDS_VIOLATION (0x1101) 359*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_PROTECTION_TAGGED_ACCESS_VIOLATION (0x1102) 360*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_PROTECTION_TAGGED_INVALID_PD (0x1102) 361*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_PROTECTION_WRAP_ERROR (0x1103) 362*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_BAD_CLOSE (0) 363*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_BAD_LLP_CLOSE (0x0207) 364*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_PROTECTION_INVALID_MSN_RANGE (0x1202) 365*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_PROTECTION_INVALID_MSN_GAP (0x1202) 366*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_TOO_MANY_READ_REQUEST (0x1203) 367*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_INVALID_MSN_GAP (0x1203) 368*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_INVALID_MSN_RANGE (0x1203) 369*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_INVALID_STAG (0x0100) 370*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_TAGGED_BOUNDS_VIOLATION (0x0101) 371*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_TAGGED_ACCESS_VIOLATION (0x0102) 372*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_TAGGED_INVALID_PD (0x0103) 373*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_IRQ_PROTECTION_WRAP_ERROR (0x0104) 374*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_SQ_COMPLETION_CQ_OVERFLOW (0x0207) 375*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_COMPLETION_CQ_OPERATION_ERROR (0x0207) 376*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_SRQ_ERROR_ON_QP (0x0207) 377*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LOCAL_QP_CATASTROPHIC_ERROR (0x0207) 378*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_LOCAL_CATASTROPHIC_ERROR (0x0) 379*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_CQ_OVERFLOW (0) 380*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_CQ_OPERATION_ERROR (0) 381*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_SRQ_LIMIT_REACHED (0) 382*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_LIMIT_REACHED (0) 383*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_SRQ_CATASTROPHIC_ERROR (0) 384*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RNIC_CATASTROPHIC_ERROR (0x0208) 385*d14abf15SRobert Mustacchi // Terminate codes for RQ completion errors 386*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_WQE_ERROR 0 387*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_INVALIDATE_STAG_INVALID (0x0100) 388*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_INVALIDATE_STAG_ACCESS_RIGHTS (0x0102) 389*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_INVALIDATE_STAG_INVALID_PD_ID (0x0103) 390*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_INVALIDATE_STAG_NOT_BOUND_TO_QP (0x0103) 391*d14abf15SRobert Mustacchi #define RDMA_TERM_CODE_RQ_INVALIDATE_MR_STAG_HAD_BOUND_MW (0x0103) 392*d14abf15SRobert Mustacchi 393*d14abf15SRobert Mustacchi // Terminate message control fields 394*d14abf15SRobert Mustacchi // Layer name mask 395*d14abf15SRobert Mustacchi #define RDMA_TERM_LAYER_MASK(termErrCode) (((termErrCode) >> 12) & 0xf) 396*d14abf15SRobert Mustacchi // Error type mask 397*d14abf15SRobert Mustacchi #define RDMA_TERM_ERR_TYPE_MASK(termErrCode) (((termErrCode) >> 8) & 0xf) 398*d14abf15SRobert Mustacchi // Error code mask 399*d14abf15SRobert Mustacchi #define RDMA_TERM_ERR_CODE_MASK(termErrCode) ((termErrCode) & 0xff) 400*d14abf15SRobert Mustacchi 401*d14abf15SRobert Mustacchi 402*d14abf15SRobert Mustacchi #endif //__RDMA_CONSTANTS_H_ 403