1d14abf15SRobert Mustacchi #include "lm5710.h"
2d14abf15SRobert Mustacchi #include "command.h"
3d14abf15SRobert Mustacchi
4d14abf15SRobert Mustacchi /* Zeros all attn_bits/ack back to the start, along with the state and the original mask of AEU lines
5d14abf15SRobert Mustacchi *
6d14abf15SRobert Mustacchi * Parameters:
7d14abf15SRobert Mustacchi * pdev - this is the LM device
8d14abf15SRobert Mustacchi */
dbg_zero_all_attn(lm_device_t * pdev)9d14abf15SRobert Mustacchi static void dbg_zero_all_attn(lm_device_t *pdev)
10d14abf15SRobert Mustacchi {
11d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
12*9b622488SToomas Soome
13d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_zero_all_attn() inside!\n");
14d14abf15SRobert Mustacchi
15d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
16d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
17d14abf15SRobert Mustacchi
18d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits = 0;
19d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_ack = 0;
20d14abf15SRobert Mustacchi pdev->vars.aeu_mask_attn_func = 0x303;
21d14abf15SRobert Mustacchi pdev->vars.attn_state = 0;
22d14abf15SRobert Mustacchi }
23d14abf15SRobert Mustacchi
24d14abf15SRobert Mustacchi /* modifies attn_bits to '1' asserted state
25d14abf15SRobert Mustacchi *
26d14abf15SRobert Mustacchi * Parameters:
27d14abf15SRobert Mustacchi * pdev - this is the LM device
28d14abf15SRobert Mustacchi * lines_to_assert - lines which goes up (asserted)
29d14abf15SRobert Mustacchi */
dbg_assert_attn_lines(lm_device_t * pdev,u16_t lines_to_assert)30d14abf15SRobert Mustacchi static void dbg_assert_attn_lines(lm_device_t *pdev, u16_t lines_to_assert)
31d14abf15SRobert Mustacchi {
32d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
33*9b622488SToomas Soome
34d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_assert_attn_lines() inside! lines_to_assert:0x%x\n", lines_to_assert);
35d14abf15SRobert Mustacchi
36d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
37d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
38d14abf15SRobert Mustacchi DbgBreakIf(mm_le32_to_cpu(def_sb->atten_status_block.attn_bits) & lines_to_assert);
39d14abf15SRobert Mustacchi
40d14abf15SRobert Mustacchi /*
41d14abf15SRobert Mustacchi attns bits line_to_assert
42d14abf15SRobert Mustacchi 1 1 -> ERROR
43d14abf15SRobert Mustacchi 1 0 -> 1
44d14abf15SRobert Mustacchi 0 0 -> 0
45d14abf15SRobert Mustacchi 0 1 -> 1
46d14abf15SRobert Mustacchi */
47d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits |= mm_cpu_to_le32(lines_to_assert);
48d14abf15SRobert Mustacchi }
49d14abf15SRobert Mustacchi
50d14abf15SRobert Mustacchi /* modifies attn_bits to '0' deasserted state
51d14abf15SRobert Mustacchi *
52d14abf15SRobert Mustacchi * Parameters:
53d14abf15SRobert Mustacchi * pdev - this is the LM device
54d14abf15SRobert Mustacchi * lines_to_deassert - lines which goes down (deasserted)
55d14abf15SRobert Mustacchi */
dbg_deassert_attn_lines(lm_device_t * pdev,u16_t lines_to_deassert)56d14abf15SRobert Mustacchi static void dbg_deassert_attn_lines(lm_device_t *pdev, u16_t lines_to_deassert)
57d14abf15SRobert Mustacchi {
58d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
59*9b622488SToomas Soome
60d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_deassert_attn_lines() inside! lines_to_deassert:0x%x\n", lines_to_deassert);
61d14abf15SRobert Mustacchi
62d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
63d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
64d14abf15SRobert Mustacchi DbgBreakIf(~mm_le32_to_cpu(def_sb->atten_status_block.attn_bits) & lines_to_deassert);
65d14abf15SRobert Mustacchi /*
66d14abf15SRobert Mustacchi attns bits line_to_deassert
67d14abf15SRobert Mustacchi 1 1 -> 0
68d14abf15SRobert Mustacchi 1 0 -> 1
69d14abf15SRobert Mustacchi 0 0 -> 0
70d14abf15SRobert Mustacchi 0 1 -> ERROR
71d14abf15SRobert Mustacchi */
72d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits ^= mm_cpu_to_le32(lines_to_deassert);
73d14abf15SRobert Mustacchi }
74d14abf15SRobert Mustacchi
75d14abf15SRobert Mustacchi /* modifies attn_ack to '1' asserted state
76d14abf15SRobert Mustacchi *
77d14abf15SRobert Mustacchi * Parameters:
78d14abf15SRobert Mustacchi * pdev - this is the LM device
79d14abf15SRobert Mustacchi * assert_lines_to_ack - lines for which we simulate a write of '1' to the attn_ack (asserted)
80d14abf15SRobert Mustacchi */
dbg_ack_assert_attn_lines(lm_device_t * pdev,u16_t assert_lines_to_ack)81d14abf15SRobert Mustacchi static void dbg_ack_assert_attn_lines(lm_device_t *pdev, u16_t assert_lines_to_ack)
82d14abf15SRobert Mustacchi {
83d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
84*9b622488SToomas Soome
85d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_ack_assert_attn_lines() inside! assert_lines_to_ack:0x%x\n", assert_lines_to_ack);
86d14abf15SRobert Mustacchi
87d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
88d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
89d14abf15SRobert Mustacchi DbgBreakIf(mm_le32_to_cpu(def_sb->atten_status_block.attn_bits_ack) & assert_lines_to_ack);
90d14abf15SRobert Mustacchi /*
91d14abf15SRobert Mustacchi attns bits ack assert_lines_to_ack
92d14abf15SRobert Mustacchi 1 1 -> ERROR
93d14abf15SRobert Mustacchi 1 0 -> 1
94d14abf15SRobert Mustacchi 0 0 -> 0
95d14abf15SRobert Mustacchi 0 1 -> 1
96d14abf15SRobert Mustacchi */
97d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_ack ^= mm_cpu_to_le32(assert_lines_to_ack);
98d14abf15SRobert Mustacchi }
99d14abf15SRobert Mustacchi
100d14abf15SRobert Mustacchi /* modifies attn_ack to '0' deasserted state
101d14abf15SRobert Mustacchi *
102d14abf15SRobert Mustacchi * Parameters:
103d14abf15SRobert Mustacchi * pdev - this is the LM device
104d14abf15SRobert Mustacchi * deassert_lines_to_ack - lines for which we simulate a write of '0' to the attn_ack (deasserted)
105d14abf15SRobert Mustacchi */
106d14abf15SRobert Mustacchi /*
107d14abf15SRobert Mustacchi static void dbg_ack_deassert_attn_lines(lm_device_t *pdev, u16_t deassert_lines_to_ack)
108d14abf15SRobert Mustacchi {
109d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
110*9b622488SToomas Soome
111d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_ack_deassert_attn_lines() inside! deassert_lines_to_ack:0x%x\n", deassert_lines_to_ack);
112d14abf15SRobert Mustacchi
113d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
114d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
115d14abf15SRobert Mustacchi DbgBreakIf(~def_sb->atten_status_block.attn_bits_ack & deassert_lines_to_ack);
116d14abf15SRobert Mustacchi
117d14abf15SRobert Mustacchi //attns bits ack deassert_lines_to_ack
118d14abf15SRobert Mustacchi // 1 1 -> 0
119d14abf15SRobert Mustacchi // 1 0 -> 1
120d14abf15SRobert Mustacchi // 0 0 -> 0
121d14abf15SRobert Mustacchi // 0 1 -> ERROR
122d14abf15SRobert Mustacchi
123d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_ack ^= deassert_lines_to_ack;
124d14abf15SRobert Mustacchi }
125d14abf15SRobert Mustacchi */
126d14abf15SRobert Mustacchi
dbg_change_sb_index(lm_device_t * pdev,u8_t rss_id)127d14abf15SRobert Mustacchi static void dbg_change_sb_index(lm_device_t *pdev, u8_t rss_id)
128d14abf15SRobert Mustacchi {
129d14abf15SRobert Mustacchi volatile struct host_status_block *rss_sb = NULL;
130d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
131*9b622488SToomas Soome
132d14abf15SRobert Mustacchi DbgBreakIf(!pdev || rss_id > MAX_RSS_CHAINS);
133d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_change_sb_index() inside!\n");
134d14abf15SRobert Mustacchi //this is the default status block
135d14abf15SRobert Mustacchi if(rss_id == DEF_STATUS_BLOCK_INDEX)
136d14abf15SRobert Mustacchi {
137d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
138d14abf15SRobert Mustacchi DbgBreakIf(!def_sb);
139d14abf15SRobert Mustacchi //increment the status index of all storms for this status block
140d14abf15SRobert Mustacchi def_sb->c_def_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->c_def_status_block.status_block_index) + 1);
141d14abf15SRobert Mustacchi def_sb->u_def_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->u_def_status_block.status_block_index) + 1);
142d14abf15SRobert Mustacchi def_sb->x_def_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->x_def_status_block.status_block_index) + 1);
143d14abf15SRobert Mustacchi def_sb->t_def_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->t_def_status_block.status_block_index) + 1);
144d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->atten_status_block.attn_bits_index) + 1);
145d14abf15SRobert Mustacchi
146d14abf15SRobert Mustacchi DbgMessage6(pdev, INFORMi, "dbg_change_sb_index():sb#%d indices are now: c_def_prod_idx:%d, u_def_prod_idx:%d, x_def_prod_idx:%d, t_def_prod_idx:%d\n",
147d14abf15SRobert Mustacchi rss_id,
148d14abf15SRobert Mustacchi mm_le16_to_cpu(def_sb->c_def_status_block.status_block_index),
149*9b622488SToomas Soome mm_le16_to_cpu(def_sb->u_def_status_block.status_block_index),
150d14abf15SRobert Mustacchi mm_le16_to_cpu(def_sb->x_def_status_block.status_block_index),
151d14abf15SRobert Mustacchi mm_le16_to_cpu(def_sb->t_def_status_block.status_block_index),
152d14abf15SRobert Mustacchi mm_le16_to_cpu(def_sb->atten_status_block.attn_bits_index));
153d14abf15SRobert Mustacchi }
154d14abf15SRobert Mustacchi //it is one of the non-default status block
155d14abf15SRobert Mustacchi else
156d14abf15SRobert Mustacchi {
157d14abf15SRobert Mustacchi rss_sb = lm_get_status_block(pdev, rss_id);
158d14abf15SRobert Mustacchi DbgBreakIf(!rss_sb);
159d14abf15SRobert Mustacchi //increment the status index of all storms for this status block
160d14abf15SRobert Mustacchi rss_sb->c_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(rss_sb->c_status_block.status_block_index) + 1);
161d14abf15SRobert Mustacchi rss_sb->u_status_block.status_block_index = mm_cpu_to_le16(mm_le16_to_cpu(rss_sb->u_status_block.status_block_index) + 1);
162d14abf15SRobert Mustacchi
163d14abf15SRobert Mustacchi DbgMessage3(pdev, INFORMi, "dbg_change_sb_index():sb#%d indices are now: c_rss_prod_idx:%d, u_rss_prod_idx:%d\n",
164d14abf15SRobert Mustacchi rss_id,
165d14abf15SRobert Mustacchi mm_le16_to_cpu(rss_sb->c_status_block.status_block_index),
166d14abf15SRobert Mustacchi mm_le16_to_cpu(rss_sb->u_status_block.status_block_index));
167d14abf15SRobert Mustacchi }
168d14abf15SRobert Mustacchi }
169d14abf15SRobert Mustacchi
170*9b622488SToomas Soome /* UM calls this in case there was a change in the default status block.
171*9b622488SToomas Soome * This function does the work of the DPC.
172d14abf15SRobert Mustacchi * Parameters:
173d14abf15SRobert Mustacchi * pdev - this is the LM device
174d14abf15SRobert Mustacchi * sb_idx - this is the index where the status block lies in the array under the lm_device
175d14abf15SRobert Mustacchi */
dbg_def_sb_dpc(lm_device_t * pdev)176d14abf15SRobert Mustacchi static void dbg_def_sb_dpc(lm_device_t *pdev)
177d14abf15SRobert Mustacchi {
178d14abf15SRobert Mustacchi u8_t is_updated = 0;
179d14abf15SRobert Mustacchi u32_t cnt = 0;
180d14abf15SRobert Mustacchi //Attntion vars
181d14abf15SRobert Mustacchi u32_t total_activ_to_ack = 0;
182d14abf15SRobert Mustacchi u32_t cnt_acks = 0;
183d14abf15SRobert Mustacchi u32_t activity_flg = 0;
184d14abf15SRobert Mustacchi u16_t lcl_attn_bits = 0;
185d14abf15SRobert Mustacchi u16_t lcl_attn_ack = 0;
186d14abf15SRobert Mustacchi u16_t asserted_proc_grps = 0;
187d14abf15SRobert Mustacchi u16_t deasserted_proc_grps = 0;
188d14abf15SRobert Mustacchi u32_t dpc_loop_cnt = 1; //hard-coded! part of the UM device params.
189d14abf15SRobert Mustacchi
190d14abf15SRobert Mustacchi DbgBreakIf(!pdev);
191d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_def_sb_dpc(): inside!\n");
192*9b622488SToomas Soome
193d14abf15SRobert Mustacchi //check if the default status block has changed, thus have a new status index.
194d14abf15SRobert Mustacchi //it is possible that even here, there is no difference in the index due to hw queues races(the DMA op is delayed)so bail out.
195d14abf15SRobert Mustacchi if ((is_updated = lm_is_def_sb_updated(pdev)) == 0)
196d14abf15SRobert Mustacchi {
197d14abf15SRobert Mustacchi //Agreed with Shay that we don't need to ack the index in case it matches the local copy, just enable ints
198d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_def_sb_dpc(): no change in status index so get out!\n");
199*9b622488SToomas Soome lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, TSTORM_ID, DEF_SB_INDEX_OF_TSTORM(pdev), IGU_INT_ENABLE, 0);
200*9b622488SToomas Soome
201d14abf15SRobert Mustacchi
202d14abf15SRobert Mustacchi return;
203d14abf15SRobert Mustacchi }
204d14abf15SRobert Mustacchi for(cnt = 0; cnt < dpc_loop_cnt; cnt++)
205d14abf15SRobert Mustacchi {
206d14abf15SRobert Mustacchi //update the local copy of indices with the newly fresh indices values just read from the default status block
207d14abf15SRobert Mustacchi lm_update_hc_indices(pdev, DEF_STATUS_BLOCK_INDEX, &activity_flg);
208d14abf15SRobert Mustacchi
209d14abf15SRobert Mustacchi DbgBreakIf(!(activity_flg & LM_DEF_EVENT_MASK));
210d14abf15SRobert Mustacchi
211d14abf15SRobert Mustacchi total_activ_to_ack |= activity_flg;
212d14abf15SRobert Mustacchi
213*9b622488SToomas Soome //attn bits handling
214d14abf15SRobert Mustacchi if (activity_flg & LM_DEF_ATTN_ACTIVE)
215d14abf15SRobert Mustacchi {
216d14abf15SRobert Mustacchi lcl_attn_bits = 0;
217d14abf15SRobert Mustacchi lcl_attn_ack = 0;
218d14abf15SRobert Mustacchi lm_get_attn_info(pdev, &lcl_attn_bits, &lcl_attn_ack);
219d14abf15SRobert Mustacchi
220d14abf15SRobert Mustacchi GET_ATTN_CHNG_GROUPS(pdev, lcl_attn_bits, lcl_attn_ack, &asserted_proc_grps, &deasserted_proc_grps);
221d14abf15SRobert Mustacchi
222d14abf15SRobert Mustacchi DbgMessage2(pdev, INFORMi, "dbg_def_sb_dpc(): asserted_proc_grps:0x%x, deasserted_proc_grps:0x%x\n", asserted_proc_grps, deasserted_proc_grps);
223d14abf15SRobert Mustacchi
224d14abf15SRobert Mustacchi if (asserted_proc_grps)
225d14abf15SRobert Mustacchi lm_handle_assertion_processing(pdev, asserted_proc_grps);
226d14abf15SRobert Mustacchi
227d14abf15SRobert Mustacchi if (deasserted_proc_grps)
228d14abf15SRobert Mustacchi lm_handle_deassertion_processing(pdev, deasserted_proc_grps);
229d14abf15SRobert Mustacchi }
230d14abf15SRobert Mustacchi
231d14abf15SRobert Mustacchi if (activity_flg & LM_DEF_USTORM_ACTIVE)
232d14abf15SRobert Mustacchi {
233d14abf15SRobert Mustacchi //TODO: USTORM protocol indices processing processing
234d14abf15SRobert Mustacchi }
235d14abf15SRobert Mustacchi if (activity_flg & LM_DEF_CSTORM_ACTIVE)
236d14abf15SRobert Mustacchi {
237d14abf15SRobert Mustacchi //TODO: CSTORM protocol indices processing processing
238d14abf15SRobert Mustacchi }
239d14abf15SRobert Mustacchi activity_flg = 0;
240d14abf15SRobert Mustacchi //if no change beneath our legs, get out.
241d14abf15SRobert Mustacchi if ((is_updated = lm_is_def_sb_updated(pdev)) == 0)
242d14abf15SRobert Mustacchi {
243d14abf15SRobert Mustacchi break;
244d14abf15SRobert Mustacchi }
245d14abf15SRobert Mustacchi }
246d14abf15SRobert Mustacchi //optimization to ack only the relevant parts to chip, and the last one must enable ints.
247d14abf15SRobert Mustacchi cnt_acks = count_bits(total_activ_to_ack);
248d14abf15SRobert Mustacchi
249d14abf15SRobert Mustacchi DbgMessage2(pdev, INFORMi, "um_bdrv_def_dpc(): cnt_acks:%d, total_activ_to_ack:0x%x\n", cnt_acks, total_activ_to_ack);
250d14abf15SRobert Mustacchi
251d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_DEF_ATTN_ACTIVE)
252*9b622488SToomas Soome lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, ATTENTION_ID, DEF_SB_INDEX_OF_ATTN(pdev), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
253d14abf15SRobert Mustacchi
254d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_DEF_USTORM_ACTIVE)
255d14abf15SRobert Mustacchi lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, USTORM_ID, DEF_SB_INDEX_OF_USTORM(pdev), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
256d14abf15SRobert Mustacchi
257d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_DEF_CSTORM_ACTIVE)
258*9b622488SToomas Soome lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, CSTORM_ID, DEF_SB_INDEX_OF_CSTORM(pdev), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
259d14abf15SRobert Mustacchi
260d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_DEF_XSTORM_ACTIVE)
261*9b622488SToomas Soome lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, XSTORM_ID, DEF_SB_INDEX_OF_XSTORM(pdev), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
262d14abf15SRobert Mustacchi
263d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_DEF_TSTORM_ACTIVE)
264*9b622488SToomas Soome lm_int_ack_sb(pdev, DEF_STATUS_BLOCK_INDEX, TSTORM_ID, DEF_SB_INDEX_OF_TSTORM(pdev), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
265d14abf15SRobert Mustacchi
266d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_def_sb_dpc(): FINISH _______________________________________________\n");
267d14abf15SRobert Mustacchi }
268d14abf15SRobert Mustacchi
269*9b622488SToomas Soome /* UM calls this in case there was a change in the status block.
270*9b622488SToomas Soome * This function does the work of the DPC.
271d14abf15SRobert Mustacchi * Parameters:
272d14abf15SRobert Mustacchi * pdev - this is the LM device
273d14abf15SRobert Mustacchi * sb_idx - this is the index where the status block lies in the array under the lm_device
274d14abf15SRobert Mustacchi */
dbg_sb_dpc(lm_device_t * pdev,u8_t rss_id)275d14abf15SRobert Mustacchi static void dbg_sb_dpc(lm_device_t *pdev, u8_t rss_id)
276d14abf15SRobert Mustacchi {
277d14abf15SRobert Mustacchi u8_t is_updated = 0;
278d14abf15SRobert Mustacchi u32_t activity_flg = 0;
279d14abf15SRobert Mustacchi u32_t total_activ_to_ack = 0;
280d14abf15SRobert Mustacchi u32_t cnt_acks = 0;
281d14abf15SRobert Mustacchi u32_t cnt = 0;
282d14abf15SRobert Mustacchi u32_t dpc_loop_cnt = 1; //hardcoded! - part of original UM device params.
283d14abf15SRobert Mustacchi
284d14abf15SRobert Mustacchi DbgBreakIf(!pdev);
285d14abf15SRobert Mustacchi DbgBreakIf(rss_id >= MAX_RSS_CHAINS);
286d14abf15SRobert Mustacchi
287d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_sb_dpc(): handling RSS status block #%d\n", rss_id);
288d14abf15SRobert Mustacchi
289d14abf15SRobert Mustacchi //check if the non-default status block has changed, thus have a new status index.
290d14abf15SRobert Mustacchi //it is possible that even here, there is no difference in the index due to hw queues races(the DMA op is delayed)so bail out.
291d14abf15SRobert Mustacchi if ((is_updated = lm_is_sb_updated(pdev, rss_id)) == 0)
292d14abf15SRobert Mustacchi {
293d14abf15SRobert Mustacchi //Agreed with Shay that we don't need to ack the index in case it matches the local copy, just enable ints
294d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "handle_sb(): no change is status index so get out!\n");
295d14abf15SRobert Mustacchi lm_int_ack_sb(pdev, rss_id, CSTORM_ID, SB_INDEX_OF_CSTORM(pdev,rss_id), IGU_INT_ENABLE, 0);
296d14abf15SRobert Mustacchi
297d14abf15SRobert Mustacchi return;
298d14abf15SRobert Mustacchi }
299d14abf15SRobert Mustacchi for(cnt = 0; cnt < dpc_loop_cnt; cnt++)
300d14abf15SRobert Mustacchi {
301d14abf15SRobert Mustacchi //update the local copy of indices with the newly fresh indices values just read from the status block
302d14abf15SRobert Mustacchi lm_update_hc_indices(pdev, rss_id, &activity_flg);
303d14abf15SRobert Mustacchi
304d14abf15SRobert Mustacchi DbgBreakIf(!(activity_flg & LM_NON_DEF_EVENT_MASK));
305d14abf15SRobert Mustacchi
306d14abf15SRobert Mustacchi total_activ_to_ack |= activity_flg;
307d14abf15SRobert Mustacchi
308d14abf15SRobert Mustacchi if (activity_flg & LM_NON_DEF_USTORM_ACTIVE)
309d14abf15SRobert Mustacchi {
310d14abf15SRobert Mustacchi //Check for Rx completions
311*9b622488SToomas Soome if (lm_is_rx_completion(pdev, rss_id))
312d14abf15SRobert Mustacchi {
313d14abf15SRobert Mustacchi //Call here service_rx_intr(pdev, rss_id);
314d14abf15SRobert Mustacchi }
315d14abf15SRobert Mustacchi }
316d14abf15SRobert Mustacchi
317d14abf15SRobert Mustacchi if (activity_flg & LM_NON_DEF_CSTORM_ACTIVE)
318d14abf15SRobert Mustacchi {
319d14abf15SRobert Mustacchi //Check for Tx completions
320*9b622488SToomas Soome if (lm_is_tx_completion(pdev, rss_id))
321d14abf15SRobert Mustacchi {
322d14abf15SRobert Mustacchi //Call here service_tx_intr(pdev, rss_id);
323d14abf15SRobert Mustacchi }
324d14abf15SRobert Mustacchi }
325d14abf15SRobert Mustacchi activity_flg = 0;
326d14abf15SRobert Mustacchi //check whether the status block has been change meanwhile, if so, lets process again
327d14abf15SRobert Mustacchi if ((is_updated = lm_is_sb_updated(pdev, rss_id)) == 0)
328d14abf15SRobert Mustacchi {
329d14abf15SRobert Mustacchi break;
330d14abf15SRobert Mustacchi }
331d14abf15SRobert Mustacchi }
332d14abf15SRobert Mustacchi //optimization to ack only the relevant parts to chip, and the last one must enable ints.
333d14abf15SRobert Mustacchi cnt_acks = count_bits(total_activ_to_ack);
334d14abf15SRobert Mustacchi DbgMessage2(pdev, INFORMi, "dbg_sb_dpc(): cnt_acks:%d, total_activ_to_ack:0x%x\n", cnt_acks, total_activ_to_ack);
335d14abf15SRobert Mustacchi
336d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_NON_DEF_USTORM_ACTIVE)
337d14abf15SRobert Mustacchi lm_int_ack_sb(pdev, rss_id, USTORM_ID, SB_INDEX_OF_USTORM(pdev,rss_id), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
338d14abf15SRobert Mustacchi
339d14abf15SRobert Mustacchi if (total_activ_to_ack & LM_NON_DEF_CSTORM_ACTIVE)
340d14abf15SRobert Mustacchi lm_int_ack_sb(pdev, rss_id, CSTORM_ID, SB_INDEX_OF_CSTORM(pdev,rss_id), --cnt_acks ? IGU_INT_NOP : IGU_INT_ENABLE, 1);
341d14abf15SRobert Mustacchi
342d14abf15SRobert Mustacchi //after all fast-path processing done, call this to enable posting pending requests to the SQ
343d14abf15SRobert Mustacchi lm_sq_post_pending(pdev);
344d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "handle_sb(): FINISH _______________________________________________\n");
345d14abf15SRobert Mustacchi }
346d14abf15SRobert Mustacchi
dbg_isr(lm_device_t * pdev,u32_t intr_status)347d14abf15SRobert Mustacchi static u8_t dbg_isr(lm_device_t *pdev, u32_t intr_status)
348d14abf15SRobert Mustacchi {
349d14abf15SRobert Mustacchi u8_t intr_recognized;
350d14abf15SRobert Mustacchi u8_t rss_id = 0;
351d14abf15SRobert Mustacchi
352d14abf15SRobert Mustacchi intr_recognized = FALSE;
353*9b622488SToomas Soome
354d14abf15SRobert Mustacchi DbgBreakIf(!pdev);
355d14abf15SRobert Mustacchi DbgMessage(pdev, INFORMi, "dbg_isr() inside!\n");
356d14abf15SRobert Mustacchi
357*9b622488SToomas Soome //get the relevant status blocks for which we need to schedule the appropriate DPC
358d14abf15SRobert Mustacchi //please note this implicitly de-asserts the interrupt line, which must not be forgotten to be enabled via the DPC
359d14abf15SRobert Mustacchi //the LSB(bit 0) describes the default status blocks and bit 1-16 describe the RSS non-default status blocks.
360*9b622488SToomas Soome //In case RSS not supported, everything will arrive on RSS 0, that means that lm_get_interrupt_status()
361d14abf15SRobert Mustacchi //will return on the maximum bit0 and bit1 toggled in that case.
362d14abf15SRobert Mustacchi
363d14abf15SRobert Mustacchi //intr_status = lm_get_interrupt_status(pdev);
364d14abf15SRobert Mustacchi
365d14abf15SRobert Mustacchi //this is not our interrupt so bail out!
366*9b622488SToomas Soome if (!intr_status)
367d14abf15SRobert Mustacchi {
368d14abf15SRobert Mustacchi return intr_recognized;
369d14abf15SRobert Mustacchi }
370d14abf15SRobert Mustacchi
371d14abf15SRobert Mustacchi //TODO: In Windows, must assure that there is only one DPC running!
372d14abf15SRobert Mustacchi //TODO: Get the CPU number on which this ISR is running (needed for RSS)
373d14abf15SRobert Mustacchi
374*9b622488SToomas Soome //go over all the status blocks updates we received from reading the single ISR/multiple DPCs register,
375d14abf15SRobert Mustacchi //and queue the corresponding DPCs for them.
376*9b622488SToomas Soome //Currently, RSS is not supported, but still, a scenario might occur where we need to queue both the fast-path DPC as well as
377d14abf15SRobert Mustacchi //the slow-path DPC
378d14abf15SRobert Mustacchi while(intr_status)
379d14abf15SRobert Mustacchi {
380d14abf15SRobert Mustacchi if(intr_status & 1)
381d14abf15SRobert Mustacchi {
382d14abf15SRobert Mustacchi //this means that there is a change in the default sb, so queue the relevant DPC of the default sb.
383d14abf15SRobert Mustacchi if (rss_id == 0)
384d14abf15SRobert Mustacchi {
385*9b622488SToomas Soome //This is the interface for Xdiag. In Windows, this will be the function which will get queued
386d14abf15SRobert Mustacchi //within the DPC object.
387d14abf15SRobert Mustacchi dbg_def_sb_dpc(pdev);
388d14abf15SRobert Mustacchi }
389d14abf15SRobert Mustacchi
390d14abf15SRobert Mustacchi //take care of the non-default sb according to RSS.
391d14abf15SRobert Mustacchi else
392d14abf15SRobert Mustacchi {
393*9b622488SToomas Soome //(rss_id - 1) is used since the non-default sbs are located in lm_device at indices 0-15
394d14abf15SRobert Mustacchi dbg_sb_dpc(pdev, rss_id - 1);
395d14abf15SRobert Mustacchi }
396d14abf15SRobert Mustacchi }
397d14abf15SRobert Mustacchi
398d14abf15SRobert Mustacchi intr_status >>= 1;
399d14abf15SRobert Mustacchi rss_id++;
400d14abf15SRobert Mustacchi }
401d14abf15SRobert Mustacchi
402d14abf15SRobert Mustacchi intr_recognized = TRUE;
403d14abf15SRobert Mustacchi
404d14abf15SRobert Mustacchi DbgMessage1(pdev, INFORMi, "dbg_isr(): intr_recognized is:%s\n", intr_recognized ? "TRUE" : "FALSE");
405*9b622488SToomas Soome
406d14abf15SRobert Mustacchi return intr_recognized;
407d14abf15SRobert Mustacchi } /* dbg_isr */
408d14abf15SRobert Mustacchi
409d14abf15SRobert Mustacchi
dbg_sb_ints_test_suite(lm_device_t * pdev)410d14abf15SRobert Mustacchi void dbg_sb_ints_test_suite(lm_device_t *pdev)
411d14abf15SRobert Mustacchi {
412d14abf15SRobert Mustacchi u8_t index;
413d14abf15SRobert Mustacchi volatile struct host_def_status_block *def_sb = NULL;
414d14abf15SRobert Mustacchi def_sb = lm_get_default_status_block(pdev);
415d14abf15SRobert Mustacchi
416d14abf15SRobert Mustacchi //This part is dedicated to checking the entire status block mechanism and Interrupts API.
417*9b622488SToomas Soome //The test should change the default/non-default status block parameters and print as debug information
418d14abf15SRobert Mustacchi //the whole status block fields.
419*9b622488SToomas Soome
420d14abf15SRobert Mustacchi //print entire info of all status blocks!
421d14abf15SRobert Mustacchi print_sb_info(pdev);
422*9b622488SToomas Soome
423d14abf15SRobert Mustacchi //handle default status block (=DPC of status block) - nothing should happen yet!
424d14abf15SRobert Mustacchi dbg_def_sb_dpc(pdev);
425*9b622488SToomas Soome
426d14abf15SRobert Mustacchi //handle all rss non-default status blocks - nothing should happen yet
427d14abf15SRobert Mustacchi for(index = 0; index < MAX_RSS_CHAINS; index++)
428d14abf15SRobert Mustacchi {
429d14abf15SRobert Mustacchi dbg_sb_dpc(pdev, index);
430d14abf15SRobert Mustacchi }
431*9b622488SToomas Soome
432d14abf15SRobert Mustacchi //now it's time to change the status index of "some" of the status block as if there
433d14abf15SRobert Mustacchi //was a change regarding them
434d14abf15SRobert Mustacchi for(index = 0; index <= MAX_RSS_CHAINS; index++)
435d14abf15SRobert Mustacchi {
436d14abf15SRobert Mustacchi //do update only for odd index status blocks and the default status block
437d14abf15SRobert Mustacchi if((index % 2) || (index == MAX_RSS_CHAINS))
438d14abf15SRobert Mustacchi {
439d14abf15SRobert Mustacchi dbg_change_sb_index(pdev, index);
440d14abf15SRobert Mustacchi }
441d14abf15SRobert Mustacchi }
442d14abf15SRobert Mustacchi //assert groups: 0,1
443d14abf15SRobert Mustacchi dbg_assert_attn_lines(pdev, 0x3);
444*9b622488SToomas Soome
445d14abf15SRobert Mustacchi //This part is hardcoded for simulating a change on the default status block(0) and RSS sb: 1,3,5,7,9,11,13,15
446d14abf15SRobert Mustacchi dbg_isr(pdev, 0x15555);
447d14abf15SRobert Mustacchi
448d14abf15SRobert Mustacchi //now we have for groups 0,1:
449*9b622488SToomas Soome // attn_bits: 1 1
450d14abf15SRobert Mustacchi // attn_ack: 0 0
451d14abf15SRobert Mustacchi // mask: 0 0
452*9b622488SToomas Soome // state: 1 1
453d14abf15SRobert Mustacchi
454d14abf15SRobert Mustacchi //simulate as if the chip wrote 1 1 to the attn_ack
455d14abf15SRobert Mustacchi dbg_ack_assert_attn_lines(pdev, 0x3);
456d14abf15SRobert Mustacchi
457d14abf15SRobert Mustacchi //now we have for groups 0,1:
458*9b622488SToomas Soome // attn_bits: 1 1
459d14abf15SRobert Mustacchi // attn_ack: 1 1
460d14abf15SRobert Mustacchi // mask: 0 0
461*9b622488SToomas Soome // state: 1 1
462d14abf15SRobert Mustacchi
463d14abf15SRobert Mustacchi //simulate as if due to the mask of the AEU line, 0 has arrived at the line and written by chip to attn_bits
464d14abf15SRobert Mustacchi dbg_deassert_attn_lines(pdev, 0x3);
465d14abf15SRobert Mustacchi
466d14abf15SRobert Mustacchi //now we have for groups 0,1:
467*9b622488SToomas Soome // attn_bits: 0 0
468d14abf15SRobert Mustacchi // attn_ack: 1 1
469d14abf15SRobert Mustacchi // mask: 0 0
470*9b622488SToomas Soome // state: 1 1
471d14abf15SRobert Mustacchi
472d14abf15SRobert Mustacchi //simulate an increment of the attn producer by chip due to change in attn bits/attn_ack from monitored state.
473d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->atten_status_block.attn_bits_index) + 1) ;
474d14abf15SRobert Mustacchi
475d14abf15SRobert Mustacchi //Call the dbg ISR routine to simulate lines de-asserted at the default sb DPC only!
476d14abf15SRobert Mustacchi dbg_isr(pdev, 0x1);
477d14abf15SRobert Mustacchi
478d14abf15SRobert Mustacchi //Set everything back to zero to start all over again!
479d14abf15SRobert Mustacchi dbg_zero_all_attn(pdev);
480d14abf15SRobert Mustacchi
481d14abf15SRobert Mustacchi // ************************** Create an unacceptable state! ***************************
482d14abf15SRobert Mustacchi
483d14abf15SRobert Mustacchi //assert groups: 0,1
484d14abf15SRobert Mustacchi dbg_assert_attn_lines(pdev, 0x3);
485d14abf15SRobert Mustacchi
486d14abf15SRobert Mustacchi //simulate as if the chip wrote 1 1 to the attn_ack
487d14abf15SRobert Mustacchi dbg_ack_assert_attn_lines(pdev, 0x3);
488d14abf15SRobert Mustacchi
489d14abf15SRobert Mustacchi //now we have for groups 0,1:
490*9b622488SToomas Soome // attn_bits: 1 1
491d14abf15SRobert Mustacchi // attn_ack: 1 1
492d14abf15SRobert Mustacchi // mask: 0 0
493*9b622488SToomas Soome // state: 0 0
494d14abf15SRobert Mustacchi
495d14abf15SRobert Mustacchi def_sb->atten_status_block.attn_bits_index = mm_cpu_to_le16(mm_le16_to_cpu(def_sb->atten_status_block.attn_bits_index) + 1);
496d14abf15SRobert Mustacchi
497d14abf15SRobert Mustacchi dbg_isr(pdev, 0x1);
498d14abf15SRobert Mustacchi }
499