1 #ifdef __LINUX 2 #include <linux/kernel.h> 3 #include <linux/types.h> 4 #include <asm/byteorder.h> 5 #endif 6 #ifdef USER_LINUX 7 #include <stdio.h> 8 #include <unistd.h> 9 #include <sys/types.h> 10 #include <sys/socket.h> 11 #include <netinet/in.h> 12 #include <arpa/inet.h> 13 #include <sys/ioctl.h> 14 #include <net/if.h> 15 #include <linux/sockios.h> 16 #include <string.h> 17 #include <malloc.h> 18 #endif 19 #ifdef __FreeBSD__ 20 #include <sys/types.h> 21 #endif 22 #include "bcmtype.h" 23 #ifdef EDEBUG 24 #include "edebug_types.h" 25 #endif 26 #include "clc.h" 27 #include "grc_addr.h" 28 #include "bigmac_addresses.h" 29 #include "emac_reg_driver.h" 30 #include "misc_bits.h" 31 #include "57712_reg.h" 32 #include "clc_reg.h" 33 #include "dev_info.h" 34 #include "license.h" 35 #include "shmem.h" 36 #include "aeu_inputs.h" 37 38 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy, 39 struct elink_params *params, 40 u8 dev_addr, u16 addr, u8 byte_cnt, 41 u8 *o_buf, u8); 42 /********************************************************/ 43 #define ELINK_ETH_HLEN 14 44 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 45 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) 46 #define ELINK_ETH_MIN_PACKET_SIZE 60 47 #define ELINK_ETH_MAX_PACKET_SIZE 1500 48 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 49 #define ELINK_MDIO_ACCESS_TIMEOUT 1000 50 #define WC_LANE_MAX 4 51 #define I2C_SWITCH_WIDTH 2 52 #define I2C_BSC0 0 53 #define I2C_BSC1 1 54 #define I2C_WA_RETRY_CNT 3 55 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 56 #define MCPR_IMC_COMMAND_READ_OP 1 57 #define MCPR_IMC_COMMAND_WRITE_OP 2 58 59 /* LED Blink rate that will achieve ~15.9Hz */ 60 #define LED_BLINK_RATE_VAL_E3 354 61 #define LED_BLINK_RATE_VAL_E1X_E2 480 62 /***********************************************************/ 63 /* Macros */ 64 /***********************************************************/ 65 #define MSLEEP(cb, ms) elink_cb_udelay(cb, 1000*ms) 66 #define USLEEP(cb, us) elink_cb_udelay(cb, us) 67 #define REG_RD(cb, reg) elink_cb_reg_read(cb, reg) 68 #define REG_WR(cb, reg, val) elink_cb_reg_write(cb, reg, val) 69 #define EMAC_RD(cb, reg) REG_RD(cb, emac_base + reg) 70 #define EMAC_WR(cb, reg, val) REG_WR(cb, emac_base + reg, val) 71 #define REG_WR_DMAE(cb, offset, wb_data, len) \ 72 elink_cb_reg_wb_write(cb, offset, wb_data, len) 73 #define REG_RD_DMAE(cb, offset, wb_data, len) \ 74 elink_cb_reg_wb_read(cb, offset, wb_data, len) 75 #define PATH_ID(cb) elink_cb_path_id(cb) 76 77 #define ELINK_SET_GPIO elink_cb_gpio_write 78 #define ELINK_SET_MULT_GPIO elink_cb_gpio_mult_write 79 #define ELINK_GET_GPIO elink_cb_gpio_read 80 #define ELINK_SET_GPIO_INT elink_cb_gpio_int_write 81 82 #ifndef OFFSETOF 83 #define OFFSETOF(_s, _m) ((u32) ((u8 *)(&((_s *) 0)->_m) - \ 84 (u8 *)((u8 *) 0))) 85 #endif 86 87 #define CHIP_REV_SHIFT 12 88 #define CHIP_REV_MASK (0xF<<CHIP_REV_SHIFT) 89 #define CHIP_REV(_chip_id) ((_chip_id) & CHIP_REV_MASK) 90 91 #define CHIP_REV_Ax (0x0<<CHIP_REV_SHIFT) 92 #define CHIP_REV_Bx (0x1<<CHIP_REV_SHIFT) 93 #define CHIP_REV_IS_SLOW(_chip_id) \ 94 (CHIP_REV(_chip_id) > 0x00005000) 95 #define CHIP_REV_IS_FPGA(_chip_id) \ 96 (CHIP_REV_IS_SLOW(_chip_id)&& \ 97 (CHIP_REV(_chip_id) & 0x00001000)) 98 #define CHIP_REV_IS_EMUL(_chip_id) \ 99 (CHIP_REV_IS_SLOW(_chip_id)&& \ 100 !(CHIP_REV(_chip_id) & 0x00001000)) 101 102 #define CHIP_NUM(_chip_id) (_chip_id >> 16) 103 #define CHIP_NUM_57710 0x164e 104 #define CHIP_NUM_57711 0x164f 105 #define CHIP_NUM_57711E 0x1650 106 #define CHIP_NUM_57712 0x1662 107 #define CHIP_NUM_57712E 0x1663 108 #define CHIP_NUM_57713 0x1651 109 #define CHIP_NUM_57713E 0x1652 110 #define CHIP_NUM_57840_OBSOLETE 0x168d 111 #define CHIP_NUM_57840_4_10 0x16a1 112 #define CHIP_NUM_57840_2_20 0x16a2 113 #define CHIP_NUM_57810 0x168e 114 #define CHIP_NUM_57800 0x168a 115 #define CHIP_NUM_57811 0x163d 116 #define CHIP_NUM_57811_MF 0x163e 117 #define CHIP_IS_E1(_chip_id) (CHIP_NUM(_chip_id) == \ 118 CHIP_NUM_57710) 119 #define CHIP_IS_E1X(_chip_id) ((CHIP_NUM(_chip_id) == \ 120 CHIP_NUM_57710) || \ 121 (CHIP_NUM(_chip_id) == \ 122 CHIP_NUM_57711) || \ 123 (CHIP_NUM(_chip_id) == \ 124 CHIP_NUM_57711E)) 125 126 #define CHIP_IS_E2(_chip_id) ((CHIP_NUM(_chip_id) == \ 127 CHIP_NUM_57712) || \ 128 (CHIP_NUM(_chip_id) == \ 129 CHIP_NUM_57712E) || \ 130 (CHIP_NUM(_chip_id) == \ 131 CHIP_NUM_57713) || \ 132 (CHIP_NUM(_chip_id) == \ 133 CHIP_NUM_57713E)) 134 135 #define CHIP_IS_57711(_chip_id) (CHIP_NUM(_chip_id) == \ 136 CHIP_NUM_57711) 137 #define CHIP_IS_57711E(_chip_id) (CHIP_NUM(_chip_id) == \ 138 CHIP_NUM_57711E) 139 #define DO_CHIP_IS_E3(_chip_family) ((_chip_family == 0x1630) || \ 140 (_chip_family == 0x1680) || \ 141 (_chip_family == 0x16a0)) 142 #define CHIP_IS_E3(_chip_id) (DO_CHIP_IS_E3(((CHIP_NUM(_chip_id)) & 0xfff0))) 143 144 145 /* For EMUL: Ax=0xE, Bx=0xC, Cx=0xA. For FPGA: Ax=0xF, Bx=0xD, 146 * Cx=0xB. 147 */ 148 #define CHIP_REV_SIM(_p) (((0xF - (CHIP_REV(_p) >> CHIP_REV_SHIFT)) \ 149 >>1) << CHIP_REV_SHIFT) 150 151 #define CHIP_IS_E3B0(_p) (CHIP_IS_E3(_p) && \ 152 ((CHIP_REV(_p) == CHIP_REV_Bx) || \ 153 (CHIP_REV_SIM(_p) == CHIP_REV_Bx))) 154 155 #define CHIP_IS_E3A0(_p) (CHIP_IS_E3(_p) && \ 156 ((CHIP_REV(_p) == CHIP_REV_Ax) || \ 157 (CHIP_REV_SIM(_p) == CHIP_REV_Ax))) 158 159 #define ELINK_USES_WARPCORE(_chip_id) (CHIP_IS_E3(_chip_id)) 160 161 #define SHMEM2_RD(cb, shmem2_base, _field) \ 162 REG_RD(cb, shmem2_base + \ 163 OFFSETOF(struct shmem2_region, \ 164 _field)) 165 166 #define SHMEM2_HAS(cb, shmem2_base, field) (shmem2_base && \ 167 (SHMEM2_RD(cb, shmem2_base, size) > \ 168 OFFSETOF(struct shmem2_region, field))) 169 #ifndef NULL 170 #define NULL ((void *) 0) 171 #endif 172 173 /***********************************************************/ 174 /* Shortcut definitions */ 175 /***********************************************************/ 176 177 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 178 179 #define ELINK_NIG_STATUS_EMAC0_MI_INT \ 180 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 181 #define ELINK_NIG_STATUS_XGXS0_LINK10G \ 182 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 183 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ 184 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 185 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 186 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 187 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ 188 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 189 #define ELINK_NIG_MASK_MI_INT \ 190 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 191 #define ELINK_NIG_MASK_XGXS0_LINK10G \ 192 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 193 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ 194 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 195 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ 196 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 197 198 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ 199 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 200 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 201 202 #define ELINK_XGXS_RESET_BITS \ 203 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 204 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 205 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 206 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 207 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 208 209 #define ELINK_SERDES_RESET_BITS \ 210 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 211 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 212 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 213 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 214 215 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 216 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 217 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 218 #define ELINK_AUTONEG_PARALLEL \ 219 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 220 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ 221 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 222 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 223 224 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 225 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 226 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 227 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 228 #define ELINK_GP_STATUS_SPEED_MASK \ 229 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 230 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 231 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 232 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 233 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 234 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 235 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 236 #define ELINK_GP_STATUS_10G_HIG \ 237 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 238 #define ELINK_GP_STATUS_10G_CX4 \ 239 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 240 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 241 #define ELINK_GP_STATUS_10G_KX4 \ 242 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 243 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 244 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 245 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 246 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 247 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 248 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 249 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 250 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 251 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 252 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 253 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 254 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 255 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 256 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 257 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 258 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 259 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 260 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 261 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 262 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 263 264 #define ELINK_LINK_UPDATE_MASK \ 265 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 266 LINK_STATUS_LINK_UP | \ 267 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 268 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 269 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 270 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 271 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 272 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 273 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 274 275 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 276 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0 277 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 278 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 279 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 280 281 282 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3 283 #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4) 284 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5) 285 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6) 286 287 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6 288 #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0) 289 #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1) 290 #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2) 291 #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3) 292 293 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 294 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 295 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 296 297 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 298 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 299 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 300 301 #define ELINK_EDC_MODE_LINEAR 0x0022 302 #define ELINK_EDC_MODE_LIMITING 0x0044 303 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 304 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 305 306 /* ETS defines*/ 307 #define DCBX_INVALID_COS (0xFF) 308 309 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 310 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 311 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 312 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 313 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) 314 315 #define ELINK_MAX_PACKET_SIZE (9700) 316 #ifdef INCLUDE_WARPCORE_UC_LOAD 317 #define ELINK_WC_UC_TIMEOUT 1000 318 #define ELINK_WC_RDY_TIMEOUT_MSEC 100 319 #endif 320 #define MAX_KR_LINK_RETRY 4 321 322 /**********************************************************/ 323 /* INTERFACE */ 324 /**********************************************************/ 325 326 #define CL22_WR_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 327 elink_cl45_write(_cb, _phy, \ 328 (_phy)->def_md_devad, \ 329 (_bank + (_addr & 0xf)), \ 330 _val) 331 332 #define CL22_RD_OVER_CL45(_cb, _phy, _bank, _addr, _val) \ 333 elink_cl45_read(_cb, _phy, \ 334 (_phy)->def_md_devad, \ 335 (_bank + (_addr & 0xf)), \ 336 _val) 337 338 #ifdef BNX2X_ADD /* BNX2X_ADD */ 339 static int elink_check_half_open_conn(struct elink_params *params, 340 struct elink_vars *vars, u8 notify); 341 static int elink_sfp_module_detection(struct elink_phy *phy, 342 struct elink_params *params); 343 #endif 344 345 static u32 elink_bits_en(struct elink_dev *cb, u32 reg, u32 bits) 346 { 347 u32 val = REG_RD(cb, reg); 348 349 val |= bits; 350 REG_WR(cb, reg, val); 351 return val; 352 } 353 354 static u32 elink_bits_dis(struct elink_dev *cb, u32 reg, u32 bits) 355 { 356 u32 val = REG_RD(cb, reg); 357 358 val &= ~bits; 359 REG_WR(cb, reg, val); 360 return val; 361 } 362 363 /* 364 * elink_check_lfa - This function checks if link reinitialization is required, 365 * or link flap can be avoided. 366 * 367 * @params: link parameters 368 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 369 * condition code. 370 */ 371 #ifndef EXCLUDE_NON_COMMON_INIT 372 static int elink_check_lfa(struct elink_params *params) 373 { 374 u32 link_status, cfg_idx, lfa_mask, cfg_size; 375 u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 376 u32 saved_val, req_val, eee_status; 377 struct elink_dev *cb = params->cb; 378 379 additional_config = 380 REG_RD(cb, params->lfa_base + 381 OFFSETOF(struct shmem_lfa, additional_config)); 382 383 /* NOTE: must be first condition checked - 384 * to verify DCC bit is cleared in any case! 385 */ 386 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 387 ELINK_DEBUG_P0(cb, "No LFA due to DCC flap after clp exit\n"); 388 REG_WR(cb, params->lfa_base + 389 OFFSETOF(struct shmem_lfa, additional_config), 390 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 391 return LFA_DCC_LFA_DISABLED; 392 } 393 394 /* Verify that link is up */ 395 link_status = REG_RD(cb, params->shmem_base + 396 OFFSETOF(struct shmem_region, 397 port_mb[params->port].link_status)); 398 if (!(link_status & LINK_STATUS_LINK_UP)) 399 return LFA_LINK_DOWN; 400 401 /* if loaded after BOOT from SAN, don't flap the link in any case and 402 * rely on link set by preboot driver 403 */ 404 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) 405 return 0; 406 407 /* Verify that loopback mode is not set */ 408 if (params->loopback_mode) 409 return LFA_LOOPBACK_ENABLED; 410 411 /* Verify that MFW supports LFA */ 412 if (!params->lfa_base) 413 return LFA_MFW_IS_TOO_OLD; 414 415 if (params->num_phys == 3) { 416 cfg_size = 2; 417 lfa_mask = 0xffffffff; 418 } else { 419 cfg_size = 1; 420 lfa_mask = 0xffff; 421 } 422 423 /* Compare Duplex */ 424 saved_val = REG_RD(cb, params->lfa_base + 425 OFFSETOF(struct shmem_lfa, req_duplex)); 426 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 427 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 428 ELINK_DEBUG_P2(cb, "Duplex mismatch %x vs. %x\n", 429 (saved_val & lfa_mask), (req_val & lfa_mask)); 430 return LFA_DUPLEX_MISMATCH; 431 } 432 /* Compare Flow Control */ 433 saved_val = REG_RD(cb, params->lfa_base + 434 OFFSETOF(struct shmem_lfa, req_flow_ctrl)); 435 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 436 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 437 ELINK_DEBUG_P2(cb, "Flow control mismatch %x vs. %x\n", 438 (saved_val & lfa_mask), (req_val & lfa_mask)); 439 return LFA_FLOW_CTRL_MISMATCH; 440 } 441 /* Compare Link Speed */ 442 saved_val = REG_RD(cb, params->lfa_base + 443 OFFSETOF(struct shmem_lfa, req_line_speed)); 444 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 445 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 446 ELINK_DEBUG_P2(cb, "Link speed mismatch %x vs. %x\n", 447 (saved_val & lfa_mask), (req_val & lfa_mask)); 448 return LFA_LINK_SPEED_MISMATCH; 449 } 450 451 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 452 cur_speed_cap_mask = REG_RD(cb, params->lfa_base + 453 OFFSETOF(struct shmem_lfa, 454 speed_cap_mask[cfg_idx])); 455 456 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 457 ELINK_DEBUG_P2(cb, "Speed Cap mismatch %x vs. %x\n", 458 cur_speed_cap_mask, 459 params->speed_cap_mask[cfg_idx]); 460 return LFA_SPEED_CAP_MISMATCH; 461 } 462 } 463 464 cur_req_fc_auto_adv = 465 REG_RD(cb, params->lfa_base + 466 OFFSETOF(struct shmem_lfa, additional_config)) & 467 REQ_FC_AUTO_ADV_MASK; 468 469 if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 470 ELINK_DEBUG_P2(cb, "Flow Ctrl AN mismatch %x vs. %x\n", 471 cur_req_fc_auto_adv, params->req_fc_auto_adv); 472 return LFA_FLOW_CTRL_MISMATCH; 473 } 474 475 eee_status = REG_RD(cb, params->shmem2_base + 476 OFFSETOF(struct shmem2_region, 477 eee_status[params->port])); 478 479 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 480 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || 481 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 482 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { 483 ELINK_DEBUG_P2(cb, "EEE mismatch %x vs. %x\n", params->eee_mode, 484 eee_status); 485 return LFA_EEE_MISMATCH; 486 } 487 488 /* LFA conditions are met */ 489 return 0; 490 } 491 #endif 492 /******************************************************************/ 493 /* EPIO/GPIO section */ 494 /******************************************************************/ 495 #if (!defined EXCLUDE_WARPCORE) 496 static void elink_get_epio(struct elink_dev *cb, u32 epio_pin, u32 *en) 497 { 498 u32 epio_mask, gp_oenable; 499 *en = 0; 500 /* Sanity check */ 501 if (epio_pin > 31) { 502 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to get\n", epio_pin); 503 return; 504 } 505 506 epio_mask = 1 << epio_pin; 507 /* Set this EPIO to output */ 508 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 509 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 510 511 *en = (REG_RD(cb, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 512 } 513 static void elink_set_epio(struct elink_dev *cb, u32 epio_pin, u32 en) 514 { 515 u32 epio_mask, gp_output, gp_oenable; 516 517 /* Sanity check */ 518 if (epio_pin > 31) { 519 ELINK_DEBUG_P1(cb, "Invalid EPIO pin %d to set\n", epio_pin); 520 return; 521 } 522 ELINK_DEBUG_P2(cb, "Setting EPIO pin %d to %d\n", epio_pin, en); 523 epio_mask = 1 << epio_pin; 524 /* Set this EPIO to output */ 525 gp_output = REG_RD(cb, MCP_REG_MCPR_GP_OUTPUTS); 526 if (en) 527 gp_output |= epio_mask; 528 else 529 gp_output &= ~epio_mask; 530 531 REG_WR(cb, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 532 533 /* Set the value for this EPIO */ 534 gp_oenable = REG_RD(cb, MCP_REG_MCPR_GP_OENABLE); 535 REG_WR(cb, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 536 } 537 538 static void elink_set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 539 { 540 if (pin_cfg == PIN_CFG_NA) 541 return; 542 if (pin_cfg >= PIN_CFG_EPIO0) { 543 elink_set_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 544 } else { 545 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 546 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 547 ELINK_SET_GPIO(cb, gpio_num, (u8)val, gpio_port); 548 } 549 } 550 551 static u32 elink_get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 552 { 553 if (pin_cfg == PIN_CFG_NA) 554 return ELINK_STATUS_ERROR; 555 if (pin_cfg >= PIN_CFG_EPIO0) { 556 elink_get_epio(cb, pin_cfg - PIN_CFG_EPIO0, val); 557 } else { 558 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 559 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 560 *val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 561 } 562 return ELINK_STATUS_OK; 563 564 } 565 #endif /* (!defined EXCLUDE_WARPCORE) */ 566 /******************************************************************/ 567 /* ETS section */ 568 /******************************************************************/ 569 #ifdef ELINK_ENHANCEMENTS 570 static void elink_ets_e2e3a0_disabled(struct elink_params *params) 571 { 572 /* ETS disabled configuration*/ 573 struct elink_dev *cb = params->cb; 574 575 ELINK_DEBUG_P0(cb, "ETS E2E3 disabled configuration\n"); 576 577 /* mapping between entry priority to client number (0,1,2 -debug and 578 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 579 * 3bits client num. 580 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 581 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 582 */ 583 584 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 585 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 586 * as strict. Bits 0,1,2 - debug and management entries, 3 - 587 * COS0 entry, 4 - COS1 entry. 588 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 589 * bit4 bit3 bit2 bit1 bit0 590 * MCP and debug are strict 591 */ 592 593 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 594 /* defines which entries (clients) are subjected to WFQ arbitration */ 595 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 596 /* For strict priority entries defines the number of consecutive 597 * slots for the highest priority. 598 */ 599 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 600 /* mapping between the CREDIT_WEIGHT registers and actual client 601 * numbers 602 */ 603 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 604 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 605 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 606 607 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 608 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 609 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 610 /* ETS mode disable */ 611 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 612 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 613 * weight for COS0/COS1. 614 */ 615 REG_WR(cb, PBF_REG_COS0_WEIGHT, 0x2710); 616 REG_WR(cb, PBF_REG_COS1_WEIGHT, 0x2710); 617 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 618 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 0x989680); 619 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 0x989680); 620 /* Defines the number of consecutive slots for the strict priority */ 621 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 622 } 623 /****************************************************************************** 624 * Description: 625 * Getting min_w_val will be set according to line speed . 626 *. 627 ******************************************************************************/ 628 static u32 elink_ets_get_min_w_val_nig(const struct elink_vars *vars) 629 { 630 u32 min_w_val = 0; 631 /* Calculate min_w_val.*/ 632 if (vars->link_up) { 633 if (vars->line_speed == ELINK_SPEED_20000) 634 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 635 else 636 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 637 } else 638 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 639 /* If the link isn't up (static configuration for example ) The 640 * link will be according to 20GBPS. 641 */ 642 return min_w_val; 643 } 644 /****************************************************************************** 645 * Description: 646 * Getting credit upper bound form min_w_val. 647 *. 648 ******************************************************************************/ 649 static u32 elink_ets_get_credit_upper_bound(const u32 min_w_val) 650 { 651 const u32 credit_upper_bound = (u32)ELINK_MAXVAL((150 * min_w_val), 652 ELINK_MAX_PACKET_SIZE); 653 return credit_upper_bound; 654 } 655 /****************************************************************************** 656 * Description: 657 * Set credit upper bound for NIG. 658 *. 659 ******************************************************************************/ 660 static void elink_ets_e3b0_set_credit_upper_bound_nig( 661 const struct elink_params *params, 662 const u32 min_w_val) 663 { 664 struct elink_dev *cb = params->cb; 665 const u8 port = params->port; 666 const u32 credit_upper_bound = 667 elink_ets_get_credit_upper_bound(min_w_val); 668 669 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 670 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 671 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 672 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 673 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 674 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 675 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 676 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 677 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 678 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 679 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 680 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 681 682 if (!port) { 683 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 684 credit_upper_bound); 685 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 686 credit_upper_bound); 687 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 688 credit_upper_bound); 689 } 690 } 691 /****************************************************************************** 692 * Description: 693 * Will return the NIG ETS registers to init values.Except 694 * credit_upper_bound. 695 * That isn't used in this configuration (No WFQ is enabled) and will be 696 * configured acording to spec 697 *. 698 ******************************************************************************/ 699 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params, 700 const struct elink_vars *vars) 701 { 702 struct elink_dev *cb = params->cb; 703 const u8 port = params->port; 704 const u32 min_w_val = elink_ets_get_min_w_val_nig(vars); 705 /* Mapping between entry priority to client number (0,1,2 -debug and 706 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 707 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 708 * reset value or init tool 709 */ 710 if (port) { 711 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 712 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 713 } else { 714 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 715 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 716 } 717 /* For strict priority entries defines the number of consecutive 718 * slots for the highest priority. 719 */ 720 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 721 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 722 /* Mapping between the CREDIT_WEIGHT registers and actual client 723 * numbers 724 */ 725 if (port) { 726 /*Port 1 has 6 COS*/ 727 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 728 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 729 } else { 730 /*Port 0 has 9 COS*/ 731 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 732 0x43210876); 733 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 734 } 735 736 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 737 * as strict. Bits 0,1,2 - debug and management entries, 3 - 738 * COS0 entry, 4 - COS1 entry. 739 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 740 * bit4 bit3 bit2 bit1 bit0 741 * MCP and debug are strict 742 */ 743 if (port) 744 REG_WR(cb, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 745 else 746 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 747 /* defines which entries (clients) are subjected to WFQ arbitration */ 748 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 749 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 750 751 /* Please notice the register address are note continuous and a 752 * for here is note appropriate.In 2 port mode port0 only COS0-5 753 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 754 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 755 * are never used for WFQ 756 */ 757 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 758 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 759 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 760 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 761 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 762 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 763 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 764 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 765 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 766 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 767 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 768 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 769 if (!port) { 770 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 771 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 772 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 773 } 774 775 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 776 } 777 /****************************************************************************** 778 * Description: 779 * Set credit upper bound for PBF. 780 *. 781 ******************************************************************************/ 782 static void elink_ets_e3b0_set_credit_upper_bound_pbf( 783 const struct elink_params *params, 784 const u32 min_w_val) 785 { 786 struct elink_dev *cb = params->cb; 787 const u32 credit_upper_bound = 788 elink_ets_get_credit_upper_bound(min_w_val); 789 const u8 port = params->port; 790 u32 base_upper_bound = 0; 791 u8 max_cos = 0; 792 u8 i = 0; 793 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 794 * port mode port1 has COS0-2 that can be used for WFQ. 795 */ 796 if (!port) { 797 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 798 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 799 } else { 800 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 801 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 802 } 803 804 for (i = 0; i < max_cos; i++) 805 REG_WR(cb, base_upper_bound + (i << 2), credit_upper_bound); 806 } 807 808 /****************************************************************************** 809 * Description: 810 * Will return the PBF ETS registers to init values.Except 811 * credit_upper_bound. 812 * That isn't used in this configuration (No WFQ is enabled) and will be 813 * configured acording to spec 814 *. 815 ******************************************************************************/ 816 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params) 817 { 818 struct elink_dev *cb = params->cb; 819 const u8 port = params->port; 820 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 821 u8 i = 0; 822 u32 base_weight = 0; 823 u8 max_cos = 0; 824 825 /* Mapping between entry priority to client number 0 - COS0 826 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 827 * TODO_ETS - Should be done by reset value or init tool 828 */ 829 if (port) 830 /* 0x688 (|011|0 10|00 1|000) */ 831 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 832 else 833 /* (10 1|100 |011|0 10|00 1|000) */ 834 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 835 836 /* TODO_ETS - Should be done by reset value or init tool */ 837 if (port) 838 /* 0x688 (|011|0 10|00 1|000)*/ 839 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 840 else 841 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 842 REG_WR(cb, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 843 844 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 845 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 846 847 848 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 849 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 850 851 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 852 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 853 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 854 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 855 */ 856 if (!port) { 857 base_weight = PBF_REG_COS0_WEIGHT_P0; 858 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 859 } else { 860 base_weight = PBF_REG_COS0_WEIGHT_P1; 861 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 862 } 863 864 for (i = 0; i < max_cos; i++) 865 REG_WR(cb, base_weight + (0x4 * i), 0); 866 867 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 868 } 869 /****************************************************************************** 870 * Description: 871 * E3B0 disable will return basicly the values to init values. 872 *. 873 ******************************************************************************/ 874 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params, 875 const struct elink_vars *vars) 876 { 877 struct elink_dev *cb = params->cb; 878 879 if (!CHIP_IS_E3B0(params->chip_id)) { 880 ELINK_DEBUG_P0(cb, 881 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 882 return ELINK_STATUS_ERROR; 883 } 884 885 elink_ets_e3b0_nig_disabled(params, vars); 886 887 elink_ets_e3b0_pbf_disabled(params); 888 889 return ELINK_STATUS_OK; 890 } 891 892 /****************************************************************************** 893 * Description: 894 * Disable will return basicly the values to init values. 895 * 896 ******************************************************************************/ 897 elink_status_t elink_ets_disabled(struct elink_params *params, 898 struct elink_vars *vars) 899 { 900 struct elink_dev *cb = params->cb; 901 elink_status_t elink_status = ELINK_STATUS_OK; 902 903 if ((CHIP_IS_E2(params->chip_id)) || (CHIP_IS_E3A0(params->chip_id))) 904 elink_ets_e2e3a0_disabled(params); 905 else if (CHIP_IS_E3B0(params->chip_id)) 906 elink_status = elink_ets_e3b0_disabled(params, vars); 907 else { 908 ELINK_DEBUG_P0(cb, "elink_ets_disabled - chip not supported\n"); 909 return ELINK_STATUS_ERROR; 910 } 911 912 return elink_status; 913 } 914 915 /****************************************************************************** 916 * Description 917 * Set the COS mappimg to SP and BW until this point all the COS are not 918 * set as SP or BW. 919 ******************************************************************************/ 920 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params, 921 const struct elink_ets_params *ets_params, 922 const u8 cos_sp_bitmap, 923 const u8 cos_bw_bitmap) 924 { 925 struct elink_dev *cb = params->cb; 926 const u8 port = params->port; 927 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 928 const u8 pbf_cli_sp_bitmap = cos_sp_bitmap; 929 const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 930 const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 931 932 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 933 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 934 935 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 936 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 937 938 REG_WR(cb, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 939 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 940 nig_cli_subject2wfq_bitmap); 941 942 REG_WR(cb, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 943 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 944 pbf_cli_subject2wfq_bitmap); 945 946 return ELINK_STATUS_OK; 947 } 948 949 /****************************************************************************** 950 * Description: 951 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 952 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 953 ******************************************************************************/ 954 static elink_status_t elink_ets_e3b0_set_cos_bw(struct elink_dev *cb, 955 const u8 cos_entry, 956 const u32 min_w_val_nig, 957 const u32 min_w_val_pbf, 958 const u16 total_bw, 959 const u8 bw, 960 const u8 port) 961 { 962 u32 nig_reg_adress_crd_weight = 0; 963 u32 pbf_reg_adress_crd_weight = 0; 964 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 965 const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 966 const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 967 968 switch (cos_entry) { 969 case 0: 970 nig_reg_adress_crd_weight = 971 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 972 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 973 pbf_reg_adress_crd_weight = (port) ? 974 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 975 break; 976 case 1: 977 nig_reg_adress_crd_weight = (port) ? 978 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 979 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 980 pbf_reg_adress_crd_weight = (port) ? 981 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 982 break; 983 case 2: 984 nig_reg_adress_crd_weight = (port) ? 985 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 986 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 987 988 pbf_reg_adress_crd_weight = (port) ? 989 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 990 break; 991 case 3: 992 if (port) 993 return ELINK_STATUS_ERROR; 994 nig_reg_adress_crd_weight = 995 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 996 pbf_reg_adress_crd_weight = 997 PBF_REG_COS3_WEIGHT_P0; 998 break; 999 case 4: 1000 if (port) 1001 return ELINK_STATUS_ERROR; 1002 nig_reg_adress_crd_weight = 1003 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 1004 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 1005 break; 1006 case 5: 1007 if (port) 1008 return ELINK_STATUS_ERROR; 1009 nig_reg_adress_crd_weight = 1010 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 1011 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 1012 break; 1013 } 1014 1015 REG_WR(cb, nig_reg_adress_crd_weight, cos_bw_nig); 1016 1017 REG_WR(cb, pbf_reg_adress_crd_weight, cos_bw_pbf); 1018 1019 return ELINK_STATUS_OK; 1020 } 1021 /****************************************************************************** 1022 * Description: 1023 * Calculate the total BW.A value of 0 isn't legal. 1024 * 1025 ******************************************************************************/ 1026 static elink_status_t elink_ets_e3b0_get_total_bw( 1027 const struct elink_params *params, 1028 struct elink_ets_params *ets_params, 1029 u16 *total_bw) 1030 { 1031 struct elink_dev *cb = params->cb; 1032 u8 cos_idx = 0; 1033 u8 is_bw_cos_exist = 0; 1034 1035 *total_bw = 0 ; 1036 /* Calculate total BW requested */ 1037 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 1038 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { 1039 is_bw_cos_exist = 1; 1040 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 1041 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config BW" 1042 "was set to 0\n"); 1043 /* This is to prevent a state when ramrods 1044 * can't be sent 1045 */ 1046 ets_params->cos[cos_idx].params.bw_params.bw 1047 = 1; 1048 } 1049 *total_bw += 1050 ets_params->cos[cos_idx].params.bw_params.bw; 1051 } 1052 } 1053 1054 /* Check total BW is valid */ 1055 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 1056 if (*total_bw == 0) { 1057 ELINK_DEBUG_P0(cb, 1058 "elink_ets_E3B0_config total BW shouldn't be 0\n"); 1059 return ELINK_STATUS_ERROR; 1060 } 1061 ELINK_DEBUG_P0(cb, 1062 "elink_ets_E3B0_config total BW should be 100\n"); 1063 /* We can handle a case whre the BW isn't 100 this can happen 1064 * if the TC are joined. 1065 */ 1066 } 1067 return ELINK_STATUS_OK; 1068 } 1069 1070 /****************************************************************************** 1071 * Description: 1072 * Invalidate all the sp_pri_to_cos. 1073 * 1074 ******************************************************************************/ 1075 static void elink_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 1076 { 1077 u8 pri = 0; 1078 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++) 1079 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 1080 } 1081 /****************************************************************************** 1082 * Description: 1083 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1084 * according to sp_pri_to_cos. 1085 * 1086 ******************************************************************************/ 1087 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params, 1088 u8 *sp_pri_to_cos, const u8 pri, 1089 const u8 cos_entry) 1090 { 1091 struct elink_dev *cb = params->cb; 1092 const u8 port = params->port; 1093 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1094 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1095 1096 if (pri >= max_num_of_cos) { 1097 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1098 "parameter Illegal strict priority\n"); 1099 return ELINK_STATUS_ERROR; 1100 } 1101 1102 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 1103 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1104 "parameter There can't be two COS's with " 1105 "the same strict pri\n"); 1106 return ELINK_STATUS_ERROR; 1107 } 1108 1109 sp_pri_to_cos[pri] = cos_entry; 1110 return ELINK_STATUS_OK; 1111 1112 } 1113 1114 /****************************************************************************** 1115 * Description: 1116 * Returns the correct value according to COS and priority in 1117 * the sp_pri_cli register. 1118 * 1119 ******************************************************************************/ 1120 static u64 elink_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 1121 const u8 pri_set, 1122 const u8 pri_offset, 1123 const u8 entry_size) 1124 { 1125 u64 pri_cli_nig = 0; 1126 pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size * 1127 (pri_set + pri_offset)); 1128 1129 return pri_cli_nig; 1130 } 1131 /****************************************************************************** 1132 * Description: 1133 * Returns the correct value according to COS and priority in the 1134 * sp_pri_cli register for NIG. 1135 * 1136 ******************************************************************************/ 1137 static u64 elink_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 1138 { 1139 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1140 const u8 nig_cos_offset = 3; 1141 const u8 nig_pri_offset = 3; 1142 1143 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1144 nig_pri_offset, 4); 1145 1146 } 1147 /****************************************************************************** 1148 * Description: 1149 * Returns the correct value according to COS and priority in the 1150 * sp_pri_cli register for PBF. 1151 * 1152 ******************************************************************************/ 1153 static u64 elink_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 1154 { 1155 const u8 pbf_cos_offset = 0; 1156 const u8 pbf_pri_offset = 0; 1157 1158 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1159 pbf_pri_offset, 3); 1160 1161 } 1162 1163 /****************************************************************************** 1164 * Description: 1165 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1166 * according to sp_pri_to_cos.(which COS has higher priority) 1167 * 1168 ******************************************************************************/ 1169 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params, 1170 u8 *sp_pri_to_cos) 1171 { 1172 struct elink_dev *cb = params->cb; 1173 u8 i = 0; 1174 const u8 port = params->port; 1175 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1176 u64 pri_cli_nig = 0x210; 1177 u32 pri_cli_pbf = 0x0; 1178 u8 pri_set = 0; 1179 u8 pri_bitmask = 0; 1180 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1181 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1182 1183 u8 cos_bit_to_set = (1 << max_num_of_cos) - 1; 1184 1185 /* Set all the strict priority first */ 1186 for (i = 0; i < max_num_of_cos; i++) { 1187 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1188 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) { 1189 ELINK_DEBUG_P0(cb, 1190 "elink_ets_e3b0_sp_set_pri_cli_reg " 1191 "invalid cos entry\n"); 1192 return ELINK_STATUS_ERROR; 1193 } 1194 1195 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1196 sp_pri_to_cos[i], pri_set); 1197 1198 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1199 sp_pri_to_cos[i], pri_set); 1200 pri_bitmask = 1 << sp_pri_to_cos[i]; 1201 /* COS is used remove it from bitmap.*/ 1202 if (!(pri_bitmask & cos_bit_to_set)) { 1203 ELINK_DEBUG_P0(cb, 1204 "elink_ets_e3b0_sp_set_pri_cli_reg " 1205 "invalid There can't be two COS's with" 1206 " the same strict pri\n"); 1207 return ELINK_STATUS_ERROR; 1208 } 1209 cos_bit_to_set &= ~pri_bitmask; 1210 pri_set++; 1211 } 1212 } 1213 1214 /* Set all the Non strict priority i= COS*/ 1215 for (i = 0; i < max_num_of_cos; i++) { 1216 pri_bitmask = 1 << i; 1217 /* Check if COS was already used for SP */ 1218 if (pri_bitmask & cos_bit_to_set) { 1219 /* COS wasn't used for SP */ 1220 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1221 i, pri_set); 1222 1223 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1224 i, pri_set); 1225 /* COS is used remove it from bitmap.*/ 1226 cos_bit_to_set &= ~pri_bitmask; 1227 pri_set++; 1228 } 1229 } 1230 1231 if (pri_set != max_num_of_cos) { 1232 ELINK_DEBUG_P0(cb, "elink_ets_e3b0_sp_set_pri_cli_reg not all " 1233 "entries were set\n"); 1234 return ELINK_STATUS_ERROR; 1235 } 1236 1237 if (port) { 1238 /* Only 6 usable clients*/ 1239 REG_WR(cb, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1240 (u32)pri_cli_nig); 1241 1242 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1243 } else { 1244 /* Only 9 usable clients*/ 1245 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig); 1246 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); 1247 1248 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1249 pri_cli_nig_lsb); 1250 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1251 pri_cli_nig_msb); 1252 1253 REG_WR(cb, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1254 } 1255 return ELINK_STATUS_OK; 1256 } 1257 1258 /****************************************************************************** 1259 * Description: 1260 * Configure the COS to ETS according to BW and SP settings. 1261 ******************************************************************************/ 1262 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 1263 const struct elink_vars *vars, 1264 struct elink_ets_params *ets_params) 1265 { 1266 struct elink_dev *cb = params->cb; 1267 elink_status_t elink_status = ELINK_STATUS_OK; 1268 const u8 port = params->port; 1269 u16 total_bw = 0; 1270 const u32 min_w_val_nig = elink_ets_get_min_w_val_nig(vars); 1271 const u32 min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 1272 u8 cos_bw_bitmap = 0; 1273 u8 cos_sp_bitmap = 0; 1274 u8 sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0}; 1275 const u8 max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1276 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1277 u8 cos_entry = 0; 1278 1279 if (!CHIP_IS_E3B0(params->chip_id)) { 1280 ELINK_DEBUG_P0(cb, 1281 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 1282 return ELINK_STATUS_ERROR; 1283 } 1284 1285 if ((ets_params->num_of_cos > max_num_of_cos)) { 1286 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config the number of COS " 1287 "isn't supported\n"); 1288 return ELINK_STATUS_ERROR; 1289 } 1290 1291 /* Prepare sp strict priority parameters*/ 1292 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1293 1294 /* Prepare BW parameters*/ 1295 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params, 1296 &total_bw); 1297 if (elink_status != ELINK_STATUS_OK) { 1298 ELINK_DEBUG_P0(cb, 1299 "elink_ets_E3B0_config get_total_bw failed\n"); 1300 return ELINK_STATUS_ERROR; 1301 } 1302 1303 /* Upper bound is set according to current link speed (min_w_val 1304 * should be the same for upper bound and COS credit val). 1305 */ 1306 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1307 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1308 1309 1310 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1311 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { 1312 cos_bw_bitmap |= (1 << cos_entry); 1313 /* The function also sets the BW in HW(not the mappin 1314 * yet) 1315 */ 1316 elink_status = elink_ets_e3b0_set_cos_bw( 1317 cb, cos_entry, min_w_val_nig, min_w_val_pbf, 1318 total_bw, 1319 ets_params->cos[cos_entry].params.bw_params.bw, 1320 port); 1321 } else if (elink_cos_state_strict == 1322 ets_params->cos[cos_entry].state){ 1323 cos_sp_bitmap |= (1 << cos_entry); 1324 1325 elink_status = elink_ets_e3b0_sp_pri_to_cos_set( 1326 params, 1327 sp_pri_to_cos, 1328 ets_params->cos[cos_entry].params.sp_params.pri, 1329 cos_entry); 1330 1331 } else { 1332 ELINK_DEBUG_P0(cb, 1333 "elink_ets_e3b0_config cos state not valid\n"); 1334 return ELINK_STATUS_ERROR; 1335 } 1336 if (elink_status != ELINK_STATUS_OK) { 1337 ELINK_DEBUG_P0(cb, 1338 "elink_ets_e3b0_config set cos bw failed\n"); 1339 return elink_status; 1340 } 1341 } 1342 1343 /* Set SP register (which COS has higher priority) */ 1344 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params, 1345 sp_pri_to_cos); 1346 1347 if (elink_status != ELINK_STATUS_OK) { 1348 ELINK_DEBUG_P0(cb, 1349 "elink_ets_E3B0_config set_pri_cli_reg failed\n"); 1350 return elink_status; 1351 } 1352 1353 /* Set client mapping of BW and strict */ 1354 elink_status = elink_ets_e3b0_cli_map(params, ets_params, 1355 cos_sp_bitmap, 1356 cos_bw_bitmap); 1357 1358 if (elink_status != ELINK_STATUS_OK) { 1359 ELINK_DEBUG_P0(cb, "elink_ets_E3B0_config SP failed\n"); 1360 return elink_status; 1361 } 1362 return ELINK_STATUS_OK; 1363 } 1364 static void elink_ets_bw_limit_common(const struct elink_params *params) 1365 { 1366 /* ETS disabled configuration */ 1367 struct elink_dev *cb = params->cb; 1368 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1369 /* Defines which entries (clients) are subjected to WFQ arbitration 1370 * COS0 0x8 1371 * COS1 0x10 1372 */ 1373 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1374 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1375 * client numbers (WEIGHT_0 does not actually have to represent 1376 * client 0) 1377 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1378 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1379 */ 1380 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1381 1382 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1383 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1384 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1385 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1386 1387 /* ETS mode enabled*/ 1388 REG_WR(cb, PBF_REG_ETS_ENABLED, 1); 1389 1390 /* Defines the number of consecutive slots for the strict priority */ 1391 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1392 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1393 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1394 * entry, 4 - COS1 entry. 1395 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1396 * bit4 bit3 bit2 bit1 bit0 1397 * MCP and debug are strict 1398 */ 1399 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1400 1401 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1402 REG_WR(cb, PBF_REG_COS0_UPPER_BOUND, 1403 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1404 REG_WR(cb, PBF_REG_COS1_UPPER_BOUND, 1405 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1406 } 1407 1408 void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw, 1409 const u32 cos1_bw) 1410 { 1411 /* ETS disabled configuration*/ 1412 struct elink_dev *cb = params->cb; 1413 const u32 total_bw = cos0_bw + cos1_bw; 1414 u32 cos0_credit_weight = 0; 1415 u32 cos1_credit_weight = 0; 1416 1417 ELINK_DEBUG_P0(cb, "ETS enabled BW limit configuration\n"); 1418 1419 if ((!total_bw) || 1420 (!cos0_bw) || 1421 (!cos1_bw)) { 1422 ELINK_DEBUG_P0(cb, "Total BW can't be zero\n"); 1423 return; 1424 } 1425 1426 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1427 total_bw; 1428 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 1429 total_bw; 1430 1431 elink_ets_bw_limit_common(params); 1432 1433 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 1434 REG_WR(cb, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 1435 1436 REG_WR(cb, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 1437 REG_WR(cb, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 1438 } 1439 1440 elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos) 1441 { 1442 /* ETS disabled configuration*/ 1443 struct elink_dev *cb = params->cb; 1444 u32 val = 0; 1445 1446 ELINK_DEBUG_P0(cb, "ETS enabled strict configuration\n"); 1447 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1448 * as strict. Bits 0,1,2 - debug and management entries, 1449 * 3 - COS0 entry, 4 - COS1 entry. 1450 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1451 * bit4 bit3 bit2 bit1 bit0 1452 * MCP and debug are strict 1453 */ 1454 REG_WR(cb, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1455 /* For strict priority entries defines the number of consecutive slots 1456 * for the highest priority. 1457 */ 1458 REG_WR(cb, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1459 /* ETS mode disable */ 1460 REG_WR(cb, PBF_REG_ETS_ENABLED, 0); 1461 /* Defines the number of consecutive slots for the strict priority */ 1462 REG_WR(cb, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 1463 1464 /* Defines the number of consecutive slots for the strict priority */ 1465 REG_WR(cb, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1466 1467 /* Mapping between entry priority to client number (0,1,2 -debug and 1468 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1469 * 3bits client num. 1470 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1471 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 1472 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 1473 */ 1474 val = (!strict_cos) ? 0x2318 : 0x22E0; 1475 REG_WR(cb, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 1476 1477 return ELINK_STATUS_OK; 1478 } 1479 #endif /* ELINK_ENHANCEMENTS */ 1480 1481 /******************************************************************/ 1482 /* PFC section */ 1483 /******************************************************************/ 1484 #ifndef EXCLUDE_NON_COMMON_INIT 1485 #ifndef EXCLUDE_WARPCORE 1486 static void elink_update_pfc_xmac(struct elink_params *params, 1487 struct elink_vars *vars, 1488 u8 is_lb) 1489 { 1490 struct elink_dev *cb = params->cb; 1491 u32 xmac_base; 1492 u32 pause_val, pfc0_val, pfc1_val; 1493 1494 /* XMAC base adrr */ 1495 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1496 1497 /* Initialize pause and pfc registers */ 1498 pause_val = 0x18000; 1499 pfc0_val = 0xFFFF8000; 1500 pfc1_val = 0x2; 1501 1502 /* No PFC support */ 1503 if (!(params->feature_config_flags & 1504 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 1505 1506 /* RX flow control - Process pause frame in receive direction 1507 */ 1508 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 1509 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1510 1511 /* TX flow control - Send pause packet when buffer is full */ 1512 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 1513 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1514 } else {/* PFC support */ 1515 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 1516 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 1517 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 1518 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 1519 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1520 /* Write pause and PFC registers */ 1521 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1522 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1523 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1524 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 1525 1526 } 1527 1528 /* Write pause and PFC registers */ 1529 REG_WR(cb, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 1530 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 1531 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 1532 1533 1534 /* Set MAC address for source TX Pause/PFC frames */ 1535 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_LO, 1536 ((params->mac_addr[2] << 24) | 1537 (params->mac_addr[3] << 16) | 1538 (params->mac_addr[4] << 8) | 1539 (params->mac_addr[5]))); 1540 REG_WR(cb, xmac_base + XMAC_REG_CTRL_SA_HI, 1541 ((params->mac_addr[0] << 8) | 1542 (params->mac_addr[1]))); 1543 1544 USLEEP(cb, 30); 1545 } 1546 1547 #endif // EXCLUDE_WARPCORE 1548 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 1549 #ifdef ELINK_ENHANCEMENTS 1550 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 1551 static void elink_emac_get_pfc_stat(struct elink_params *params, 1552 u32 pfc_frames_sent[2], 1553 u32 pfc_frames_received[2]) 1554 { 1555 /* Read pfc statistic */ 1556 struct elink_dev *cb = params->cb; 1557 u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1558 u32 val_xon = 0; 1559 u32 val_xoff = 0; 1560 1561 ELINK_DEBUG_P0(cb, "pfc statistic read from EMAC\n"); 1562 1563 /* PFC received frames */ 1564 val_xoff = REG_RD(cb, emac_base + 1565 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 1566 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 1567 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 1568 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 1569 1570 pfc_frames_received[0] = val_xon + val_xoff; 1571 1572 /* PFC received sent */ 1573 val_xoff = REG_RD(cb, emac_base + 1574 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 1575 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 1576 val_xon = REG_RD(cb, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 1577 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 1578 1579 pfc_frames_sent[0] = val_xon + val_xoff; 1580 } 1581 1582 /* Read pfc statistic*/ 1583 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 1584 u32 pfc_frames_sent[2], 1585 u32 pfc_frames_received[2]) 1586 { 1587 /* Read pfc statistic */ 1588 struct elink_dev *cb = params->cb; 1589 1590 ELINK_DEBUG_P0(cb, "pfc statistic\n"); 1591 1592 if (!vars->link_up) 1593 return; 1594 1595 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { 1596 ELINK_DEBUG_P0(cb, "About to read PFC stats from EMAC\n"); 1597 elink_emac_get_pfc_stat(params, pfc_frames_sent, 1598 pfc_frames_received); 1599 } 1600 } 1601 #endif /* ! BNX2X_UPSTREAM */ 1602 #endif /* ELINK_ENHANCEMENTS */ 1603 /******************************************************************/ 1604 /* MAC/PBF section */ 1605 /******************************************************************/ 1606 static void elink_set_mdio_clk(struct elink_dev *cb, u32 chip_id, 1607 u32 emac_base) 1608 { 1609 u32 new_mode, cur_mode; 1610 u32 clc_cnt; 1611 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 1612 * (a value of 49==0x31) and make sure that the AUTO poll is off 1613 */ 1614 cur_mode = REG_RD(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE); 1615 1616 if (ELINK_USES_WARPCORE(chip_id)) 1617 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1618 else 1619 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 1620 1621 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 1622 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 1623 return; 1624 1625 new_mode = cur_mode & 1626 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 1627 new_mode |= clc_cnt; 1628 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 1629 1630 ELINK_DEBUG_P2(cb, "Changing emac_mode from 0x%x to 0x%x\n", 1631 cur_mode, new_mode); 1632 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 1633 USLEEP(cb, 40); 1634 } 1635 1636 #ifndef EXCLUDE_WARPCORE 1637 static u8 elink_is_4_port_mode(struct elink_dev *cb) 1638 { 1639 u32 port4mode_ovwr_val; 1640 /* Check 4-port override enabled */ 1641 port4mode_ovwr_val = REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR); 1642 if (port4mode_ovwr_val & (1<<0)) { 1643 /* Return 4-port mode override value */ 1644 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 1645 } 1646 /* Return 4-port mode from input pin */ 1647 return (u8)REG_RD(cb, MISC_REG_PORT4MODE_EN); 1648 } 1649 #endif 1650 1651 #ifndef EXCLUDE_NON_COMMON_INIT 1652 static void elink_set_mdio_emac_per_phy(struct elink_dev *cb, 1653 struct elink_params *params) 1654 { 1655 u8 phy_index; 1656 1657 /* Set mdio clock per phy */ 1658 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 1659 phy_index++) 1660 elink_set_mdio_clk(cb, params->chip_id, 1661 params->phy[phy_index].mdio_ctrl); 1662 } 1663 1664 static void elink_emac_init(struct elink_params *params, 1665 struct elink_vars *vars) 1666 { 1667 /* reset and unreset the emac core */ 1668 struct elink_dev *cb = params->cb; 1669 u8 port = params->port; 1670 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 1671 u32 val; 1672 u16 timeout; 1673 1674 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1675 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1676 USLEEP(cb, 5); 1677 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1678 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 1679 1680 /* init emac - use read-modify-write */ 1681 /* self clear reset */ 1682 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1683 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 1684 1685 timeout = 200; 1686 do { 1687 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 1688 ELINK_DEBUG_P1(cb, "EMAC reset reg is %u\n", val); 1689 if (!timeout) { 1690 ELINK_DEBUG_P0(cb, "EMAC timeout!\n"); 1691 return; 1692 } 1693 timeout--; 1694 } while (val & EMAC_MODE_RESET); 1695 1696 elink_set_mdio_emac_per_phy(cb, params); 1697 /* Set mac address */ 1698 val = ((params->mac_addr[0] << 8) | 1699 params->mac_addr[1]); 1700 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH, val); 1701 1702 val = ((params->mac_addr[2] << 24) | 1703 (params->mac_addr[3] << 16) | 1704 (params->mac_addr[4] << 8) | 1705 params->mac_addr[5]); 1706 EMAC_WR(cb, EMAC_REG_EMAC_MAC_MATCH + 4, val); 1707 } 1708 1709 #ifndef EXCLUDE_WARPCORE 1710 static void elink_set_xumac_nig(struct elink_params *params, 1711 u16 tx_pause_en, 1712 u8 enable) 1713 { 1714 struct elink_dev *cb = params->cb; 1715 1716 REG_WR(cb, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 1717 enable); 1718 REG_WR(cb, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 1719 enable); 1720 REG_WR(cb, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 1721 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1722 } 1723 1724 static void elink_set_umac_rxtx(struct elink_params *params, u8 en) 1725 { 1726 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1727 u32 val; 1728 struct elink_dev *cb = params->cb; 1729 if (!(REG_RD(cb, MISC_REG_RESET_REG_2) & 1730 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 1731 return; 1732 val = REG_RD(cb, umac_base + UMAC_REG_COMMAND_CONFIG); 1733 if (en) 1734 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 1735 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1736 else 1737 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 1738 UMAC_COMMAND_CONFIG_REG_RX_ENA); 1739 /* Disable RX and TX */ 1740 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1741 } 1742 1743 static void elink_umac_enable(struct elink_params *params, 1744 struct elink_vars *vars, u8 lb) 1745 { 1746 u32 val; 1747 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 1748 struct elink_dev *cb = params->cb; 1749 /* Reset UMAC */ 1750 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1751 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1752 MSLEEP(cb, 1); 1753 1754 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1755 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 1756 1757 ELINK_DEBUG_P0(cb, "enabling UMAC\n"); 1758 1759 /* This register opens the gate for the UMAC despite its name */ 1760 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1761 1762 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 1763 UMAC_COMMAND_CONFIG_REG_PAD_EN | 1764 UMAC_COMMAND_CONFIG_REG_SW_RESET | 1765 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 1766 switch (vars->line_speed) { 1767 case ELINK_SPEED_10: 1768 val |= (0<<2); 1769 break; 1770 case ELINK_SPEED_100: 1771 val |= (1<<2); 1772 break; 1773 case ELINK_SPEED_1000: 1774 val |= (2<<2); 1775 break; 1776 case ELINK_SPEED_2500: 1777 val |= (3<<2); 1778 break; 1779 default: 1780 ELINK_DEBUG_P1(cb, "Invalid speed for UMAC %d\n", 1781 vars->line_speed); 1782 break; 1783 } 1784 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 1785 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 1786 1787 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 1788 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 1789 1790 if (vars->duplex == DUPLEX_HALF) 1791 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 1792 1793 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1794 USLEEP(cb, 50); 1795 1796 /* Configure UMAC for EEE */ 1797 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1798 ELINK_DEBUG_P0(cb, "configured UMAC for EEE\n"); 1799 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 1800 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 1801 REG_WR(cb, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 1802 } else { 1803 REG_WR(cb, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 1804 } 1805 1806 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 1807 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR0, 1808 ((params->mac_addr[2] << 24) | 1809 (params->mac_addr[3] << 16) | 1810 (params->mac_addr[4] << 8) | 1811 (params->mac_addr[5]))); 1812 REG_WR(cb, umac_base + UMAC_REG_MAC_ADDR1, 1813 ((params->mac_addr[0] << 8) | 1814 (params->mac_addr[1]))); 1815 1816 /* Enable RX and TX */ 1817 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 1818 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 1819 UMAC_COMMAND_CONFIG_REG_RX_ENA; 1820 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1821 USLEEP(cb, 50); 1822 1823 /* Remove SW Reset */ 1824 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 1825 1826 /* Check loopback mode */ 1827 if (lb) 1828 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1829 REG_WR(cb, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1830 1831 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 1832 * length used by the MAC receive logic to check frames. 1833 */ 1834 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 1835 elink_set_xumac_nig(params, 1836 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1837 vars->mac_type = ELINK_MAC_TYPE_UMAC; 1838 1839 } 1840 1841 /* Define the XMAC mode */ 1842 static void elink_xmac_init(struct elink_params *params, u32 max_speed) 1843 { 1844 struct elink_dev *cb = params->cb; 1845 u32 is_port4mode = elink_is_4_port_mode(cb); 1846 1847 /* In 4-port mode, need to set the mode only once, so if XMAC is 1848 * already out of reset, it means the mode has already been set, 1849 * and it must not* reset the XMAC again, since it controls both 1850 * ports of the path 1851 */ 1852 1853 if (((CHIP_NUM(params->chip_id) == CHIP_NUM_57840_4_10) || 1854 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_2_20) || 1855 (CHIP_NUM(params->chip_id) == CHIP_NUM_57840_OBSOLETE)) && 1856 is_port4mode && 1857 (REG_RD(cb, MISC_REG_RESET_REG_2) & 1858 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1859 ELINK_DEBUG_P0(cb, 1860 "XMAC already out of reset in 4-port mode\n"); 1861 return; 1862 } 1863 1864 /* Hard reset */ 1865 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1866 MISC_REGISTERS_RESET_REG_2_XMAC); 1867 MSLEEP(cb, 1); 1868 1869 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1870 MISC_REGISTERS_RESET_REG_2_XMAC); 1871 if (is_port4mode) { 1872 ELINK_DEBUG_P0(cb, "Init XMAC to 2 ports x 10G per path\n"); 1873 1874 /* Set the number of ports on the system side to up to 2 */ 1875 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1876 1877 /* Set the number of ports on the Warp Core to 10G */ 1878 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1879 } else { 1880 /* Set the number of ports on the system side to 1 */ 1881 REG_WR(cb, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1882 if (max_speed == ELINK_SPEED_10000) { 1883 ELINK_DEBUG_P0(cb, 1884 "Init XMAC to 10G x 1 port per path\n"); 1885 /* Set the number of ports on the Warp Core to 10G */ 1886 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1887 } else { 1888 ELINK_DEBUG_P0(cb, 1889 "Init XMAC to 20G x 2 ports per path\n"); 1890 /* Set the number of ports on the Warp Core to 20G */ 1891 REG_WR(cb, MISC_REG_XMAC_PHY_PORT_MODE, 1); 1892 } 1893 } 1894 /* Soft reset */ 1895 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 1896 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1897 MSLEEP(cb, 1); 1898 1899 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 1900 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 1901 1902 } 1903 1904 static void elink_set_xmac_rxtx(struct elink_params *params, u8 en) 1905 { 1906 u8 port = params->port; 1907 struct elink_dev *cb = params->cb; 1908 u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1909 u32 val; 1910 1911 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 1912 MISC_REGISTERS_RESET_REG_2_XMAC) { 1913 /* Send an indication to change the state in the NIG back to XON 1914 * Clearing this bit enables the next set of this bit to get 1915 * rising edge 1916 */ 1917 pfc_ctrl = REG_RD(cb, xmac_base + XMAC_REG_PFC_CTRL_HI); 1918 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1919 (pfc_ctrl & ~(1<<1))); 1920 REG_WR(cb, xmac_base + XMAC_REG_PFC_CTRL_HI, 1921 (pfc_ctrl | (1<<1))); 1922 ELINK_DEBUG_P1(cb, "Disable XMAC on port %x\n", port); 1923 val = REG_RD(cb, xmac_base + XMAC_REG_CTRL); 1924 if (en) 1925 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1926 else 1927 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 1928 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1929 } 1930 } 1931 1932 static elink_status_t elink_xmac_enable(struct elink_params *params, 1933 struct elink_vars *vars, u8 lb) 1934 { 1935 u32 val, xmac_base; 1936 struct elink_dev *cb = params->cb; 1937 ELINK_DEBUG_P0(cb, "enabling XMAC\n"); 1938 1939 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1940 1941 elink_xmac_init(params, vars->line_speed); 1942 1943 /* This register determines on which events the MAC will assert 1944 * error on the i/f to the NIG along w/ EOP. 1945 */ 1946 1947 /* This register tells the NIG whether to send traffic to UMAC 1948 * or XMAC 1949 */ 1950 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1951 1952 /* When XMAC is in XLGMII mode, disable sending idles for fault 1953 * detection. 1954 */ 1955 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { 1956 REG_WR(cb, xmac_base + XMAC_REG_RX_LSS_CTRL, 1957 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 1958 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 1959 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 1960 REG_WR(cb, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 1961 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 1962 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 1963 } 1964 /* Set Max packet size */ 1965 REG_WR(cb, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 1966 1967 /* CRC append for Tx packets */ 1968 REG_WR(cb, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 1969 1970 /* update PFC */ 1971 elink_update_pfc_xmac(params, vars, 0); 1972 1973 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 1974 ELINK_DEBUG_P0(cb, "Setting XMAC for EEE\n"); 1975 REG_WR(cb, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 1976 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 1977 } else { 1978 REG_WR(cb, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 1979 } 1980 1981 /* Enable TX and RX */ 1982 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 1983 1984 /* Set MAC in XLGMII mode for dual-mode */ 1985 if ((vars->line_speed == ELINK_SPEED_20000) && 1986 (params->phy[ELINK_INT_PHY].supported & 1987 ELINK_SUPPORTED_20000baseKR2_Full)) 1988 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 1989 1990 /* Check loopback mode */ 1991 if (lb) 1992 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 1993 REG_WR(cb, xmac_base + XMAC_REG_CTRL, val); 1994 elink_set_xumac_nig(params, 1995 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 1996 1997 vars->mac_type = ELINK_MAC_TYPE_XMAC; 1998 1999 return ELINK_STATUS_OK; 2000 } 2001 #endif // EXCLUDE_WARPCORE 2002 2003 #ifndef EXCLUDE_EMAC 2004 static elink_status_t elink_emac_enable(struct elink_params *params, 2005 struct elink_vars *vars, u8 lb) 2006 { 2007 struct elink_dev *cb = params->cb; 2008 u8 port = params->port; 2009 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2010 u32 val; 2011 2012 ELINK_DEBUG_P0(cb, "enabling EMAC\n"); 2013 2014 /* Disable BMAC */ 2015 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2016 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2017 2018 /* enable emac and not bmac */ 2019 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 2020 2021 #ifdef ELINK_INCLUDE_EMUL 2022 /* for paladium */ 2023 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2024 /* Use lane 1 (of lanes 0-3) */ 2025 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2026 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2027 } 2028 /* for fpga */ 2029 else 2030 #endif 2031 #ifdef ELINK_INCLUDE_FPGA 2032 if (CHIP_REV_IS_FPGA(params->chip_id)) { 2033 /* Use lane 1 (of lanes 0-3) */ 2034 ELINK_DEBUG_P0(cb, "elink_emac_enable: Setting FPGA\n"); 2035 2036 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2037 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2038 } else 2039 #endif 2040 /* ASIC */ 2041 if (vars->phy_flags & PHY_XGXS_FLAG) { 2042 u32 ser_lane = ((params->lane_config & 2043 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 2044 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 2045 2046 ELINK_DEBUG_P0(cb, "XGXS\n"); 2047 /* select the master lanes (out of 0-3) */ 2048 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 2049 /* select XGXS */ 2050 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2051 2052 } else { /* SerDes */ 2053 ELINK_DEBUG_P0(cb, "SerDes\n"); 2054 /* select SerDes */ 2055 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2056 } 2057 2058 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2059 EMAC_RX_MODE_RESET); 2060 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2061 EMAC_TX_MODE_RESET); 2062 2063 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2064 if (CHIP_REV_IS_SLOW(params->chip_id)) { 2065 /* config GMII mode */ 2066 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2067 EMAC_WR(cb, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); 2068 } else { /* ASIC */ 2069 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)*/ 2070 /* pause enable/disable */ 2071 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_RX_MODE, 2072 EMAC_RX_MODE_FLOW_EN); 2073 2074 elink_bits_dis(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2075 (EMAC_TX_MODE_EXT_PAUSE_EN | 2076 EMAC_TX_MODE_FLOW_EN)); 2077 if (!(params->feature_config_flags & 2078 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 2079 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 2080 elink_bits_en(cb, emac_base + 2081 EMAC_REG_EMAC_RX_MODE, 2082 EMAC_RX_MODE_FLOW_EN); 2083 2084 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 2085 elink_bits_en(cb, emac_base + 2086 EMAC_REG_EMAC_TX_MODE, 2087 (EMAC_TX_MODE_EXT_PAUSE_EN | 2088 EMAC_TX_MODE_FLOW_EN)); 2089 } else 2090 elink_bits_en(cb, emac_base + EMAC_REG_EMAC_TX_MODE, 2091 EMAC_TX_MODE_FLOW_EN); 2092 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2093 } 2094 #endif /* defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) */ 2095 2096 /* KEEP_VLAN_TAG, promiscuous */ 2097 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_RX_MODE); 2098 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 2099 2100 /* Setting this bit causes MAC control frames (except for pause 2101 * frames) to be passed on for processing. This setting has no 2102 * affect on the operation of the pause frames. This bit effects 2103 * all packets regardless of RX Parser packet sorting logic. 2104 * Turn the PFC off to make sure we are in Xon state before 2105 * enabling it. 2106 */ 2107 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 0); 2108 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2109 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2110 /* Enable PFC again */ 2111 EMAC_WR(cb, EMAC_REG_RX_PFC_MODE, 2112 EMAC_REG_RX_PFC_MODE_RX_EN | 2113 EMAC_REG_RX_PFC_MODE_TX_EN | 2114 EMAC_REG_RX_PFC_MODE_PRIORITIES); 2115 2116 EMAC_WR(cb, EMAC_REG_RX_PFC_PARAM, 2117 ((0x0101 << 2118 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 2119 (0x00ff << 2120 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 2121 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 2122 } 2123 EMAC_WR(cb, EMAC_REG_EMAC_RX_MODE, val); 2124 2125 /* Set Loopback */ 2126 val = REG_RD(cb, emac_base + EMAC_REG_EMAC_MODE); 2127 if (lb) 2128 val |= 0x810; 2129 else 2130 val &= ~0x810; 2131 EMAC_WR(cb, EMAC_REG_EMAC_MODE, val); 2132 2133 /* Enable emac */ 2134 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 1); 2135 2136 #ifndef ELINK_AUX_POWER 2137 /* Enable emac for jumbo packets */ 2138 EMAC_WR(cb, EMAC_REG_EMAC_RX_MTU_SIZE, 2139 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 2140 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD))); 2141 #endif 2142 2143 /* Strip CRC */ 2144 REG_WR(cb, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 2145 2146 /* Disable the NIG in/out to the bmac */ 2147 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 2148 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 2149 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 2150 2151 /* Enable the NIG in/out to the emac */ 2152 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 2153 val = 0; 2154 if ((params->feature_config_flags & 2155 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2156 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2157 val = 1; 2158 2159 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 2160 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 2161 2162 #ifdef ELINK_INCLUDE_EMUL 2163 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2164 /* Take the BigMac out of reset */ 2165 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2166 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2167 2168 /* Enable access for bmac registers */ 2169 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2170 } else 2171 #endif /* ELINK_INCLUDE_EMUL */ 2172 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 2173 2174 vars->mac_type = ELINK_MAC_TYPE_EMAC; 2175 return ELINK_STATUS_OK; 2176 } 2177 2178 #endif //EXCLUDE_EMAC 2179 #ifndef EXCLUDE_BMAC1 2180 static void elink_update_pfc_bmac1(struct elink_params *params, 2181 struct elink_vars *vars) 2182 { 2183 u32 wb_data[2]; 2184 struct elink_dev *cb = params->cb; 2185 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2186 NIG_REG_INGRESS_BMAC0_MEM; 2187 2188 u32 val = 0x14; 2189 if ((!(params->feature_config_flags & 2190 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2191 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2192 /* Enable BigMAC to react on received Pause packets */ 2193 val |= (1<<5); 2194 wb_data[0] = val; 2195 wb_data[1] = 0; 2196 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 2197 2198 /* TX control */ 2199 val = 0xc0; 2200 if (!(params->feature_config_flags & 2201 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2202 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2203 val |= 0x800000; 2204 wb_data[0] = val; 2205 wb_data[1] = 0; 2206 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 2207 } 2208 #endif // EXCLUDE_BMAC1 2209 2210 #ifndef EXCLUDE_BMAC2 2211 static void elink_update_pfc_bmac2(struct elink_params *params, 2212 struct elink_vars *vars, 2213 u8 is_lb) 2214 { 2215 /* Set rx control: Strip CRC and enable BigMAC to relay 2216 * control packets to the system as well 2217 */ 2218 u32 wb_data[2]; 2219 struct elink_dev *cb = params->cb; 2220 u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2221 NIG_REG_INGRESS_BMAC0_MEM; 2222 u32 val = 0x14; 2223 2224 if ((!(params->feature_config_flags & 2225 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2226 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2227 /* Enable BigMAC to react on received Pause packets */ 2228 val |= (1<<5); 2229 wb_data[0] = val; 2230 wb_data[1] = 0; 2231 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 2232 USLEEP(cb, 30); 2233 2234 /* Tx control */ 2235 val = 0xc0; 2236 if (!(params->feature_config_flags & 2237 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2238 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2239 val |= 0x800000; 2240 wb_data[0] = val; 2241 wb_data[1] = 0; 2242 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2243 2244 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2245 ELINK_DEBUG_P0(cb, "PFC is enabled\n"); 2246 /* Enable PFC RX & TX & STATS and set 8 COS */ 2247 wb_data[0] = 0x0; 2248 wb_data[0] |= (1<<0); /* RX */ 2249 wb_data[0] |= (1<<1); /* TX */ 2250 wb_data[0] |= (1<<2); /* Force initial Xon */ 2251 wb_data[0] |= (1<<3); /* 8 cos */ 2252 wb_data[0] |= (1<<5); /* STATS */ 2253 wb_data[1] = 0; 2254 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2255 wb_data, 2); 2256 /* Clear the force Xon */ 2257 wb_data[0] &= ~(1<<2); 2258 } else { 2259 ELINK_DEBUG_P0(cb, "PFC is disabled\n"); 2260 /* Disable PFC RX & TX & STATS and set 8 COS */ 2261 wb_data[0] = 0x8; 2262 wb_data[1] = 0; 2263 } 2264 2265 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2266 2267 /* Set Time (based unit is 512 bit time) between automatic 2268 * re-sending of PP packets amd enable automatic re-send of 2269 * Per-Priroity Packet as long as pp_gen is asserted and 2270 * pp_disable is low. 2271 */ 2272 val = 0x8000; 2273 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2274 val |= (1<<16); /* enable automatic re-send */ 2275 2276 wb_data[0] = val; 2277 wb_data[1] = 0; 2278 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2279 wb_data, 2); 2280 2281 /* mac control */ 2282 val = 0x3; /* Enable RX and TX */ 2283 if (is_lb) { 2284 val |= 0x4; /* Local loopback */ 2285 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2286 } 2287 /* When PFC enabled, Pass pause frames towards the NIG. */ 2288 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2289 val |= ((1<<6)|(1<<5)); 2290 2291 wb_data[0] = val; 2292 wb_data[1] = 0; 2293 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2294 } 2295 #endif // EXCLUDE_BMAC2 2296 #endif // EXCLUDE_NON_COMMON_INIT 2297 #ifdef ELINK_ENHANCEMENTS 2298 2299 /****************************************************************************** 2300 * Description: 2301 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2302 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2303 ******************************************************************************/ 2304 static elink_status_t elink_pfc_nig_rx_priority_mask(struct elink_dev *cb, 2305 u8 cos_entry, 2306 u32 priority_mask, u8 port) 2307 { 2308 u32 nig_reg_rx_priority_mask_add = 0; 2309 2310 switch (cos_entry) { 2311 case 0: 2312 nig_reg_rx_priority_mask_add = (port) ? 2313 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2314 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2315 break; 2316 case 1: 2317 nig_reg_rx_priority_mask_add = (port) ? 2318 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2319 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2320 break; 2321 case 2: 2322 nig_reg_rx_priority_mask_add = (port) ? 2323 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2324 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2325 break; 2326 case 3: 2327 if (port) 2328 return ELINK_STATUS_ERROR; 2329 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2330 break; 2331 case 4: 2332 if (port) 2333 return ELINK_STATUS_ERROR; 2334 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2335 break; 2336 case 5: 2337 if (port) 2338 return ELINK_STATUS_ERROR; 2339 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2340 break; 2341 } 2342 2343 REG_WR(cb, nig_reg_rx_priority_mask_add, priority_mask); 2344 2345 return ELINK_STATUS_OK; 2346 } 2347 #endif // ELINK_ENHANCEMENTS 2348 #ifndef EXCLUDE_NON_COMMON_INIT 2349 static void elink_update_mng(struct elink_params *params, u32 link_status) 2350 { 2351 struct elink_dev *cb = params->cb; 2352 2353 REG_WR(cb, params->shmem_base + 2354 OFFSETOF(struct shmem_region, 2355 port_mb[params->port].link_status), link_status); 2356 } 2357 2358 #ifdef ELINK_ENHANCEMENTS 2359 static void elink_update_pfc_nig(struct elink_params *params, 2360 struct elink_vars *vars, 2361 struct elink_nig_brb_pfc_port_params *nig_params) 2362 { 2363 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2364 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2365 u32 pkt_priority_to_cos = 0; 2366 struct elink_dev *cb = params->cb; 2367 u8 port = params->port; 2368 2369 int set_pfc = params->feature_config_flags & 2370 ELINK_FEATURE_CONFIG_PFC_ENABLED; 2371 ELINK_DEBUG_P0(cb, "updating pfc nig parameters\n"); 2372 2373 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2374 * MAC control frames (that are not pause packets) 2375 * will be forwarded to the XCM. 2376 */ 2377 xcm_mask = REG_RD(cb, port ? NIG_REG_LLH1_XCM_MASK : 2378 NIG_REG_LLH0_XCM_MASK); 2379 /* NIG params will override non PFC params, since it's possible to 2380 * do transition from PFC to SAFC 2381 */ 2382 if (set_pfc) { 2383 pause_enable = 0; 2384 llfc_out_en = 0; 2385 llfc_enable = 0; 2386 if (CHIP_IS_E3(params->chip_id)) 2387 ppp_enable = 0; 2388 else 2389 ppp_enable = 1; 2390 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2391 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2392 xcm_out_en = 0; 2393 hwpfc_enable = 1; 2394 } else { 2395 if (nig_params) { 2396 llfc_out_en = nig_params->llfc_out_en; 2397 llfc_enable = nig_params->llfc_enable; 2398 pause_enable = nig_params->pause_enable; 2399 } else /* Default non PFC mode - PAUSE */ 2400 pause_enable = 1; 2401 2402 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2403 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2404 xcm_out_en = 1; 2405 } 2406 2407 if (CHIP_IS_E3(params->chip_id)) 2408 REG_WR(cb, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2409 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2410 REG_WR(cb, port ? NIG_REG_LLFC_OUT_EN_1 : 2411 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2412 REG_WR(cb, port ? NIG_REG_LLFC_ENABLE_1 : 2413 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2414 REG_WR(cb, port ? NIG_REG_PAUSE_ENABLE_1 : 2415 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2416 2417 REG_WR(cb, port ? NIG_REG_PPP_ENABLE_1 : 2418 NIG_REG_PPP_ENABLE_0, ppp_enable); 2419 2420 REG_WR(cb, port ? NIG_REG_LLH1_XCM_MASK : 2421 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2422 2423 REG_WR(cb, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2424 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2425 2426 /* Output enable for RX_XCM # IF */ 2427 REG_WR(cb, port ? NIG_REG_XCM1_OUT_EN : 2428 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2429 2430 /* HW PFC TX enable */ 2431 REG_WR(cb, port ? NIG_REG_P1_HWPFC_ENABLE : 2432 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2433 2434 if (nig_params) { 2435 u8 i = 0; 2436 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2437 2438 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2439 elink_pfc_nig_rx_priority_mask(cb, i, 2440 nig_params->rx_cos_priority_mask[i], port); 2441 2442 REG_WR(cb, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2443 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 2444 nig_params->llfc_high_priority_classes); 2445 2446 REG_WR(cb, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 2447 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 2448 nig_params->llfc_low_priority_classes); 2449 } 2450 REG_WR(cb, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 2451 NIG_REG_P0_PKT_PRIORITY_TO_COS, 2452 pkt_priority_to_cos); 2453 } 2454 2455 elink_status_t elink_update_pfc(struct elink_params *params, 2456 struct elink_vars *vars, 2457 struct elink_nig_brb_pfc_port_params *pfc_params) 2458 { 2459 /* The PFC and pause are orthogonal to one another, meaning when 2460 * PFC is enabled, the pause are disabled, and when PFC is 2461 * disabled, pause are set according to the pause result. 2462 */ 2463 u32 val; 2464 struct elink_dev *cb = params->cb; 2465 u8 bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); 2466 2467 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2468 vars->link_status |= LINK_STATUS_PFC_ENABLED; 2469 else 2470 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 2471 2472 elink_update_mng(params, vars->link_status); 2473 2474 /* Update NIG params */ 2475 elink_update_pfc_nig(params, vars, pfc_params); 2476 2477 if (!vars->link_up) 2478 return ELINK_STATUS_OK; 2479 2480 ELINK_DEBUG_P0(cb, "About to update PFC in BMAC\n"); 2481 2482 if (CHIP_IS_E3(params->chip_id)) { 2483 if (vars->mac_type == ELINK_MAC_TYPE_XMAC) 2484 elink_update_pfc_xmac(params, vars, 0); 2485 } else { 2486 val = REG_RD(cb, MISC_REG_RESET_REG_2); 2487 if ((val & 2488 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 2489 == 0) { 2490 ELINK_DEBUG_P0(cb, "About to update PFC in EMAC\n"); 2491 elink_emac_enable(params, vars, 0); 2492 return ELINK_STATUS_OK; 2493 } 2494 if (CHIP_IS_E2(params->chip_id)) 2495 elink_update_pfc_bmac2(params, vars, bmac_loopback); 2496 else 2497 elink_update_pfc_bmac1(params, vars); 2498 2499 val = 0; 2500 if ((params->feature_config_flags & 2501 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2502 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2503 val = 1; 2504 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 2505 } 2506 return ELINK_STATUS_OK; 2507 } 2508 2509 #endif /* ELINK_ENHANCEMENTS */ 2510 #ifndef EXCLUDE_BMAC1 2511 static elink_status_t elink_bmac1_enable(struct elink_params *params, 2512 struct elink_vars *vars, 2513 u8 is_lb) 2514 { 2515 struct elink_dev *cb = params->cb; 2516 u8 port = params->port; 2517 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2518 NIG_REG_INGRESS_BMAC0_MEM; 2519 u32 wb_data[2]; 2520 u32 val; 2521 2522 ELINK_DEBUG_P0(cb, "Enabling BigMAC1\n"); 2523 2524 /* XGXS control */ 2525 wb_data[0] = 0x3c; 2526 wb_data[1] = 0; 2527 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 2528 wb_data, 2); 2529 2530 /* TX MAC SA */ 2531 wb_data[0] = ((params->mac_addr[2] << 24) | 2532 (params->mac_addr[3] << 16) | 2533 (params->mac_addr[4] << 8) | 2534 params->mac_addr[5]); 2535 wb_data[1] = ((params->mac_addr[0] << 8) | 2536 params->mac_addr[1]); 2537 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 2538 2539 /* MAC control */ 2540 val = 0x3; 2541 if (is_lb) { 2542 val |= 0x4; 2543 ELINK_DEBUG_P0(cb, "enable bmac loopback\n"); 2544 } 2545 wb_data[0] = val; 2546 wb_data[1] = 0; 2547 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 2548 2549 /* Set rx mtu */ 2550 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2551 wb_data[1] = 0; 2552 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 2553 2554 elink_update_pfc_bmac1(params, vars); 2555 2556 /* Set tx mtu */ 2557 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2558 wb_data[1] = 0; 2559 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 2560 2561 /* Set cnt max size */ 2562 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2563 wb_data[1] = 0; 2564 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2565 2566 /* Configure SAFC */ 2567 wb_data[0] = 0x1000200; 2568 wb_data[1] = 0; 2569 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 2570 wb_data, 2); 2571 #ifdef ELINK_INCLUDE_EMUL 2572 /* Fix for emulation */ 2573 if (CHIP_REV_IS_EMUL(params->chip_id)) { 2574 wb_data[0] = 0xf000; 2575 wb_data[1] = 0; 2576 REG_WR_DMAE(cb, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, 2577 wb_data, 2); 2578 } 2579 #endif /* ELINK_INCLUDE_EMUL */ 2580 2581 return ELINK_STATUS_OK; 2582 } 2583 #endif /* EXCLUDE_BMAC1 */ 2584 2585 #ifndef EXCLUDE_BMAC2 2586 static elink_status_t elink_bmac2_enable(struct elink_params *params, 2587 struct elink_vars *vars, 2588 u8 is_lb) 2589 { 2590 struct elink_dev *cb = params->cb; 2591 u8 port = params->port; 2592 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2593 NIG_REG_INGRESS_BMAC0_MEM; 2594 u32 wb_data[2]; 2595 2596 ELINK_DEBUG_P0(cb, "Enabling BigMAC2\n"); 2597 2598 wb_data[0] = 0; 2599 wb_data[1] = 0; 2600 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2601 USLEEP(cb, 30); 2602 2603 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 2604 wb_data[0] = 0x3c; 2605 wb_data[1] = 0; 2606 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 2607 wb_data, 2); 2608 2609 USLEEP(cb, 30); 2610 2611 /* TX MAC SA */ 2612 wb_data[0] = ((params->mac_addr[2] << 24) | 2613 (params->mac_addr[3] << 16) | 2614 (params->mac_addr[4] << 8) | 2615 params->mac_addr[5]); 2616 wb_data[1] = ((params->mac_addr[0] << 8) | 2617 params->mac_addr[1]); 2618 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 2619 wb_data, 2); 2620 2621 USLEEP(cb, 30); 2622 2623 /* Configure SAFC */ 2624 wb_data[0] = 0x1000200; 2625 wb_data[1] = 0; 2626 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 2627 wb_data, 2); 2628 USLEEP(cb, 30); 2629 2630 /* Set RX MTU */ 2631 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2632 wb_data[1] = 0; 2633 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 2634 USLEEP(cb, 30); 2635 2636 /* Set TX MTU */ 2637 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 2638 wb_data[1] = 0; 2639 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 2640 USLEEP(cb, 30); 2641 /* Set cnt max size */ 2642 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; 2643 wb_data[1] = 0; 2644 REG_WR_DMAE(cb, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 2645 USLEEP(cb, 30); 2646 elink_update_pfc_bmac2(params, vars, is_lb); 2647 2648 return ELINK_STATUS_OK; 2649 } 2650 #endif /* EXCLUDE_BMAC2 */ 2651 2652 #if !defined(EXCLUDE_BMAC2) 2653 static elink_status_t elink_bmac_enable(struct elink_params *params, 2654 struct elink_vars *vars, 2655 u8 is_lb, u8 reset_bmac) 2656 { 2657 elink_status_t rc = ELINK_STATUS_OK; 2658 u8 port = params->port; 2659 struct elink_dev *cb = params->cb; 2660 u32 val; 2661 /* Reset and unreset the BigMac */ 2662 if (reset_bmac) { 2663 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2664 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2665 MSLEEP(cb, 1); 2666 } 2667 2668 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2669 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2670 2671 /* Enable access for bmac registers */ 2672 REG_WR(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2673 2674 /* Enable BMAC according to BMAC type*/ 2675 #ifdef ELINK_ENHANCEMENTS 2676 if (CHIP_IS_E2(params->chip_id)) 2677 #endif 2678 #ifndef EXCLUDE_BMAC2 2679 rc = elink_bmac2_enable(params, vars, is_lb); 2680 #endif 2681 #ifdef ELINK_ENHANCEMENTS 2682 else 2683 #endif 2684 #ifndef EXCLUDE_BMAC1 2685 rc = elink_bmac1_enable(params, vars, is_lb); 2686 #endif 2687 REG_WR(cb, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 2688 REG_WR(cb, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 2689 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 2690 val = 0; 2691 if ((params->feature_config_flags & 2692 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2693 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2694 val = 1; 2695 REG_WR(cb, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 2696 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 2697 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 2698 REG_WR(cb, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 2699 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 2700 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 2701 2702 vars->mac_type = ELINK_MAC_TYPE_BMAC; 2703 return rc; 2704 } 2705 #endif /* #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2706 2707 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 2708 static void elink_set_bmac_rx(struct elink_dev *cb, u32 chip_id, u8 port, u8 en) 2709 { 2710 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 2711 NIG_REG_INGRESS_BMAC0_MEM; 2712 u32 wb_data[2]; 2713 u32 nig_bmac_enable = REG_RD(cb, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 2714 2715 if (CHIP_IS_E2(chip_id)) 2716 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 2717 else 2718 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 2719 /* Only if the bmac is out of reset */ 2720 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 2721 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 2722 nig_bmac_enable) { 2723 /* Clear Rx Enable bit in BMAC_CONTROL register */ 2724 REG_RD_DMAE(cb, bmac_addr, wb_data, 2); 2725 if (en) 2726 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; 2727 else 2728 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 2729 REG_WR_DMAE(cb, bmac_addr, wb_data, 2); 2730 MSLEEP(cb, 1); 2731 } 2732 } 2733 #endif /* !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) */ 2734 #endif // EXCLUDE_NON_COMMON_INIT 2735 2736 #ifndef ELINK_AUX_POWER 2737 static elink_status_t elink_pbf_update(struct elink_params *params, u32 flow_ctrl, 2738 u32 line_speed) 2739 { 2740 struct elink_dev *cb = params->cb; 2741 u8 port = params->port; 2742 u32 init_crd, crd; 2743 u32 count = 1000; 2744 2745 /* Disable port */ 2746 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 2747 2748 /* Wait for init credit */ 2749 init_crd = REG_RD(cb, PBF_REG_P0_INIT_CRD + port*4); 2750 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2751 ELINK_DEBUG_P2(cb, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 2752 2753 while ((init_crd != crd) && count) { 2754 MSLEEP(cb, 5); 2755 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2756 count--; 2757 } 2758 crd = REG_RD(cb, PBF_REG_P0_CREDIT + port*8); 2759 if (init_crd != crd) { 2760 ELINK_DEBUG_P2(cb, "BUG! init_crd 0x%x != crd 0x%x\n", 2761 init_crd, crd); 2762 return ELINK_STATUS_ERROR; 2763 } 2764 2765 if (flow_ctrl & ELINK_FLOW_CTRL_RX || 2766 line_speed == ELINK_SPEED_10 || 2767 line_speed == ELINK_SPEED_100 || 2768 line_speed == ELINK_SPEED_1000 || 2769 line_speed == ELINK_SPEED_2500) { 2770 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 2771 /* Update threshold */ 2772 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, 0); 2773 /* Update init credit */ 2774 init_crd = 778; /* (800-18-4) */ 2775 2776 } else { 2777 u32 thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + 2778 ELINK_ETH_OVREHEAD)/16; 2779 REG_WR(cb, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 2780 /* Update threshold */ 2781 REG_WR(cb, PBF_REG_P0_ARB_THRSH + port*4, thresh); 2782 /* Update init credit */ 2783 switch (line_speed) { 2784 case ELINK_SPEED_10000: 2785 init_crd = thresh + 553 - 22; 2786 break; 2787 default: 2788 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 2789 line_speed); 2790 return ELINK_STATUS_ERROR; 2791 } 2792 } 2793 REG_WR(cb, PBF_REG_P0_INIT_CRD + port*4, init_crd); 2794 ELINK_DEBUG_P2(cb, "PBF updated to speed %d credit %d\n", 2795 line_speed, init_crd); 2796 2797 /* Probe the credit changes */ 2798 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x1); 2799 MSLEEP(cb, 5); 2800 REG_WR(cb, PBF_REG_INIT_P0 + port*4, 0x0); 2801 2802 /* Enable port */ 2803 REG_WR(cb, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 2804 return ELINK_STATUS_OK; 2805 } 2806 #endif /* ELINK_AUX_POWER */ 2807 2808 #ifndef EXCLUDE_COMMON_INIT 2809 /** 2810 * elink_get_emac_base - retrive emac base address 2811 * 2812 * @bp: driver handle 2813 * @mdc_mdio_access: access type 2814 * @port: port id 2815 * 2816 * This function selects the MDC/MDIO access (through emac0 or 2817 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 2818 * phy has a default access mode, which could also be overridden 2819 * by nvram configuration. This parameter, whether this is the 2820 * default phy configuration, or the nvram overrun 2821 * configuration, is passed here as mdc_mdio_access and selects 2822 * the emac_base for the CL45 read/writes operations 2823 */ 2824 static u32 elink_get_emac_base(struct elink_dev *cb, 2825 u32 mdc_mdio_access, u8 port) 2826 { 2827 u32 emac_base = 0; 2828 switch (mdc_mdio_access) { 2829 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 2830 break; 2831 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 2832 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2833 emac_base = GRCBASE_EMAC1; 2834 else 2835 emac_base = GRCBASE_EMAC0; 2836 break; 2837 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 2838 if (REG_RD(cb, NIG_REG_PORT_SWAP)) 2839 emac_base = GRCBASE_EMAC0; 2840 else 2841 emac_base = GRCBASE_EMAC1; 2842 break; 2843 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 2844 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2845 break; 2846 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 2847 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 2848 break; 2849 default: 2850 break; 2851 } 2852 return emac_base; 2853 2854 } 2855 #endif /* EXCLUDE_COMMON_INIT */ 2856 2857 /******************************************************************/ 2858 /* CL22 access functions */ 2859 /******************************************************************/ 2860 #ifndef EXCLUDE_NON_COMMON_INIT 2861 #ifndef EXCLUDE_BCM54618SE 2862 static elink_status_t elink_cl22_write(struct elink_dev *cb, 2863 struct elink_phy *phy, 2864 u16 reg, u16 val) 2865 { 2866 u32 tmp, mode; 2867 u8 i; 2868 elink_status_t rc = ELINK_STATUS_OK; 2869 /* Switch to CL22 */ 2870 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2871 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2872 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2873 2874 /* Address */ 2875 tmp = ((phy->addr << 21) | (reg << 16) | val | 2876 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 2877 EMAC_MDIO_COMM_START_BUSY); 2878 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 2879 2880 for (i = 0; i < 50; i++) { 2881 USLEEP(cb, 10); 2882 2883 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2884 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 2885 USLEEP(cb, 5); 2886 break; 2887 } 2888 } 2889 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 2890 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 2891 rc = ELINK_STATUS_TIMEOUT; 2892 } 2893 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2894 return rc; 2895 } 2896 2897 static elink_status_t elink_cl22_read(struct elink_dev *cb, 2898 struct elink_phy *phy, 2899 u16 reg, u16 *ret_val) 2900 { 2901 u32 val, mode; 2902 u16 i; 2903 elink_status_t rc = ELINK_STATUS_OK; 2904 2905 /* Switch to CL22 */ 2906 mode = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 2907 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 2908 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 2909 2910 /* Address */ 2911 val = ((phy->addr << 21) | (reg << 16) | 2912 EMAC_MDIO_COMM_COMMAND_READ_22 | 2913 EMAC_MDIO_COMM_START_BUSY); 2914 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2915 2916 for (i = 0; i < 50; i++) { 2917 USLEEP(cb, 10); 2918 2919 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2920 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2921 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2922 USLEEP(cb, 5); 2923 break; 2924 } 2925 } 2926 if (val & EMAC_MDIO_COMM_START_BUSY) { 2927 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2928 2929 *ret_val = 0; 2930 rc = ELINK_STATUS_TIMEOUT; 2931 } 2932 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 2933 return rc; 2934 } 2935 #endif 2936 #endif /* EXCLUDE_NON_COMMON_INIT */ 2937 2938 /******************************************************************/ 2939 /* CL45 access functions */ 2940 /******************************************************************/ 2941 static elink_status_t elink_cl45_read(struct elink_dev *cb, struct elink_phy *phy, 2942 u8 devad, u16 reg, u16 *ret_val) 2943 { 2944 u32 val; 2945 u16 i; 2946 elink_status_t rc = ELINK_STATUS_OK; 2947 #ifndef ELINK_AUX_POWER 2948 u32 chip_id; 2949 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 2950 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 2951 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 2952 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 2953 } 2954 #endif /* ELINK_AUX_POWER */ 2955 2956 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 2957 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 2958 EMAC_MDIO_STATUS_10MB); 2959 /* Address */ 2960 val = ((phy->addr << 21) | (devad << 16) | reg | 2961 EMAC_MDIO_COMM_COMMAND_ADDRESS | 2962 EMAC_MDIO_COMM_START_BUSY); 2963 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2964 2965 for (i = 0; i < 50; i++) { 2966 USLEEP(cb, 10); 2967 2968 val = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 2969 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2970 USLEEP(cb, 5); 2971 break; 2972 } 2973 } 2974 if (val & EMAC_MDIO_COMM_START_BUSY) { 2975 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2976 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 2977 2978 *ret_val = 0; 2979 rc = ELINK_STATUS_TIMEOUT; 2980 } else { 2981 /* Data */ 2982 val = ((phy->addr << 21) | (devad << 16) | 2983 EMAC_MDIO_COMM_COMMAND_READ_45 | 2984 EMAC_MDIO_COMM_START_BUSY); 2985 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 2986 2987 for (i = 0; i < 50; i++) { 2988 USLEEP(cb, 10); 2989 2990 val = REG_RD(cb, phy->mdio_ctrl + 2991 EMAC_REG_EMAC_MDIO_COMM); 2992 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 2993 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA); 2994 break; 2995 } 2996 } 2997 if (val & EMAC_MDIO_COMM_START_BUSY) { 2998 ELINK_DEBUG_P0(cb, "read phy register failed\n"); 2999 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3000 3001 *ret_val = 0; 3002 rc = ELINK_STATUS_TIMEOUT; 3003 } 3004 } 3005 /* Work around for E3 A0 */ 3006 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3007 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3008 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3009 u16 temp_val; 3010 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3011 } 3012 } 3013 3014 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3015 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3016 EMAC_MDIO_STATUS_10MB); 3017 return rc; 3018 } 3019 3020 static elink_status_t elink_cl45_write(struct elink_dev *cb, struct elink_phy *phy, 3021 u8 devad, u16 reg, u16 val) 3022 { 3023 u32 tmp; 3024 u8 i; 3025 elink_status_t rc = ELINK_STATUS_OK; 3026 #ifndef ELINK_AUX_POWER 3027 u32 chip_id; 3028 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 3029 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 3030 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 3031 elink_set_mdio_clk(cb, chip_id, phy->mdio_ctrl); 3032 } 3033 #endif /* ELINK_AUX_POWER */ 3034 3035 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3036 elink_bits_en(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3037 EMAC_MDIO_STATUS_10MB); 3038 3039 /* Address */ 3040 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3041 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3042 EMAC_MDIO_COMM_START_BUSY); 3043 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3044 3045 for (i = 0; i < 50; i++) { 3046 USLEEP(cb, 10); 3047 3048 tmp = REG_RD(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3049 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3050 USLEEP(cb, 5); 3051 break; 3052 } 3053 } 3054 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3055 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3056 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3057 3058 rc = ELINK_STATUS_TIMEOUT; 3059 } else { 3060 /* Data */ 3061 tmp = ((phy->addr << 21) | (devad << 16) | val | 3062 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 3063 EMAC_MDIO_COMM_START_BUSY); 3064 REG_WR(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3065 3066 for (i = 0; i < 50; i++) { 3067 USLEEP(cb, 10); 3068 3069 tmp = REG_RD(cb, phy->mdio_ctrl + 3070 EMAC_REG_EMAC_MDIO_COMM); 3071 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3072 USLEEP(cb, 5); 3073 break; 3074 } 3075 } 3076 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3077 ELINK_DEBUG_P0(cb, "write phy register failed\n"); 3078 elink_cb_event_log(cb, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3079 3080 rc = ELINK_STATUS_TIMEOUT; 3081 } 3082 } 3083 /* Work around for E3 A0 */ 3084 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3085 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3086 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3087 u16 temp_val; 3088 elink_cl45_read(cb, phy, devad, 0xf, &temp_val); 3089 } 3090 } 3091 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3092 elink_bits_dis(cb, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3093 EMAC_MDIO_STATUS_10MB); 3094 return rc; 3095 } 3096 3097 /******************************************************************/ 3098 /* EEE section */ 3099 /******************************************************************/ 3100 #ifndef EXCLUDE_NON_COMMON_INIT 3101 #ifndef EXCLUDE_WARPCORE 3102 static u8 elink_eee_has_cap(struct elink_params *params) 3103 { 3104 struct elink_dev *cb = params->cb; 3105 3106 if (REG_RD(cb, params->shmem2_base) <= 3107 OFFSETOF(struct shmem2_region, eee_status[params->port])) 3108 return 0; 3109 3110 return 1; 3111 } 3112 3113 static elink_status_t elink_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer) 3114 { 3115 switch (nvram_mode) { 3116 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 3117 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; 3118 break; 3119 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 3120 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; 3121 break; 3122 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 3123 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; 3124 break; 3125 default: 3126 *idle_timer = 0; 3127 break; 3128 } 3129 3130 return ELINK_STATUS_OK; 3131 } 3132 3133 static elink_status_t elink_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode) 3134 { 3135 switch (idle_timer) { 3136 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: 3137 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 3138 break; 3139 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: 3140 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 3141 break; 3142 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: 3143 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 3144 break; 3145 default: 3146 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 3147 break; 3148 } 3149 3150 return ELINK_STATUS_OK; 3151 } 3152 3153 static u32 elink_eee_calc_timer(struct elink_params *params) 3154 { 3155 u32 eee_mode, eee_idle; 3156 struct elink_dev *cb = params->cb; 3157 3158 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { 3159 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3160 /* time value in eee_mode --> used directly*/ 3161 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; 3162 } else { 3163 /* hsi value in eee_mode --> time */ 3164 if (elink_eee_nvram_to_time(params->eee_mode & 3165 ELINK_EEE_MODE_NVRAM_MASK, 3166 &eee_idle)) 3167 return 0; 3168 } 3169 } else { 3170 /* hsi values in nvram --> time*/ 3171 eee_mode = ((REG_RD(cb, params->shmem_base + 3172 OFFSETOF(struct shmem_region, dev_info. 3173 port_feature_config[params->port]. 3174 eee_power_mode)) & 3175 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 3176 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 3177 3178 if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) 3179 return 0; 3180 } 3181 3182 return eee_idle; 3183 } 3184 3185 static elink_status_t elink_eee_set_timers(struct elink_params *params, 3186 struct elink_vars *vars) 3187 { 3188 u32 eee_idle = 0, eee_mode; 3189 struct elink_dev *cb = params->cb; 3190 3191 eee_idle = elink_eee_calc_timer(params); 3192 3193 if (eee_idle) { 3194 REG_WR(cb, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 3195 eee_idle); 3196 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && 3197 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && 3198 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { 3199 ELINK_DEBUG_P0(cb, "Error: Tx LPI is enabled with timer 0\n"); 3200 return ELINK_STATUS_ERROR; 3201 } 3202 3203 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 3204 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3205 /* eee_idle in 1u --> eee_status in 16u */ 3206 eee_idle >>= 4; 3207 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 3208 SHMEM_EEE_TIME_OUTPUT_BIT; 3209 } else { 3210 if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) 3211 return ELINK_STATUS_ERROR; 3212 vars->eee_status |= eee_mode; 3213 } 3214 3215 return ELINK_STATUS_OK; 3216 } 3217 3218 static elink_status_t elink_eee_initial_config(struct elink_params *params, 3219 struct elink_vars *vars, u8 mode) 3220 { 3221 vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 3222 3223 /* Propogate params' bits --> vars (for migration exposure) */ 3224 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) 3225 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 3226 else 3227 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 3228 3229 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) 3230 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 3231 else 3232 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 3233 3234 return elink_eee_set_timers(params, vars); 3235 } 3236 3237 static elink_status_t elink_eee_disable(struct elink_phy *phy, 3238 struct elink_params *params, 3239 struct elink_vars *vars) 3240 { 3241 struct elink_dev *cb = params->cb; 3242 3243 /* Make Certain LPI is disabled */ 3244 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 3245 3246 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 3247 3248 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3249 3250 return ELINK_STATUS_OK; 3251 } 3252 3253 static elink_status_t elink_eee_advertise(struct elink_phy *phy, 3254 struct elink_params *params, 3255 struct elink_vars *vars, u8 modes) 3256 { 3257 struct elink_dev *cb = params->cb; 3258 u16 val = 0; 3259 3260 /* Mask events preventing LPI generation */ 3261 REG_WR(cb, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 3262 3263 if (modes & SHMEM_EEE_10G_ADV) { 3264 ELINK_DEBUG_P0(cb, "Advertise 10GBase-T EEE\n"); 3265 val |= 0x8; 3266 } 3267 if (modes & SHMEM_EEE_1G_ADV) { 3268 ELINK_DEBUG_P0(cb, "Advertise 1GBase-T EEE\n"); 3269 val |= 0x4; 3270 } 3271 3272 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 3273 3274 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3275 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 3276 3277 return ELINK_STATUS_OK; 3278 } 3279 3280 static void elink_update_mng_eee(struct elink_params *params, u32 eee_status) 3281 { 3282 struct elink_dev *cb = params->cb; 3283 3284 if (elink_eee_has_cap(params)) 3285 REG_WR(cb, params->shmem2_base + 3286 OFFSETOF(struct shmem2_region, 3287 eee_status[params->port]), eee_status); 3288 } 3289 3290 static void elink_eee_an_resolve(struct elink_phy *phy, 3291 struct elink_params *params, 3292 struct elink_vars *vars) 3293 { 3294 struct elink_dev *cb = params->cb; 3295 u16 adv = 0, lp = 0; 3296 u32 lp_adv = 0; 3297 u8 neg = 0; 3298 3299 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3300 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3301 3302 if (lp & 0x2) { 3303 lp_adv |= SHMEM_EEE_100M_ADV; 3304 if (adv & 0x2) { 3305 if (vars->line_speed == ELINK_SPEED_100) 3306 neg = 1; 3307 ELINK_DEBUG_P0(cb, "EEE negotiated - 100M\n"); 3308 } 3309 } 3310 if (lp & 0x14) { 3311 lp_adv |= SHMEM_EEE_1G_ADV; 3312 if (adv & 0x14) { 3313 if (vars->line_speed == ELINK_SPEED_1000) 3314 neg = 1; 3315 ELINK_DEBUG_P0(cb, "EEE negotiated - 1G\n"); 3316 } 3317 } 3318 if (lp & 0x68) { 3319 lp_adv |= SHMEM_EEE_10G_ADV; 3320 if (adv & 0x68) { 3321 if (vars->line_speed == ELINK_SPEED_10000) 3322 neg = 1; 3323 ELINK_DEBUG_P0(cb, "EEE negotiated - 10G\n"); 3324 } 3325 } 3326 3327 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3328 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3329 3330 if (neg) { 3331 ELINK_DEBUG_P0(cb, "EEE is active\n"); 3332 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3333 } 3334 } 3335 3336 /******************************************************************/ 3337 /* BSC access functions from E3 */ 3338 /******************************************************************/ 3339 static void elink_bsc_module_sel(struct elink_params *params) 3340 { 3341 int idx; 3342 u32 board_cfg, sfp_ctrl; 3343 u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3344 struct elink_dev *cb = params->cb; 3345 u8 port = params->port; 3346 /* Read I2C output PINs */ 3347 board_cfg = REG_RD(cb, params->shmem_base + 3348 OFFSETOF(struct shmem_region, 3349 dev_info.shared_hw_config.board)); 3350 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3351 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3352 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3353 3354 /* Read I2C output value */ 3355 sfp_ctrl = REG_RD(cb, params->shmem_base + 3356 OFFSETOF(struct shmem_region, 3357 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3358 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3359 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3360 ELINK_DEBUG_P0(cb, "Setting BSC switch\n"); 3361 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3362 elink_set_cfg_pin(cb, i2c_pins[idx], i2c_val[idx]); 3363 } 3364 3365 static elink_status_t elink_bsc_read(struct elink_params *params, 3366 struct elink_dev *cb, 3367 u8 sl_devid, 3368 u16 sl_addr, 3369 u8 lc_addr, 3370 u8 xfer_cnt, 3371 u32 *data_array) 3372 { 3373 u32 val, i; 3374 elink_status_t rc = ELINK_STATUS_OK; 3375 3376 if (xfer_cnt > 16) { 3377 ELINK_DEBUG_P1(cb, "invalid xfer_cnt %d. Max is 16 bytes\n", 3378 xfer_cnt); 3379 return ELINK_STATUS_ERROR; 3380 } 3381 if (params) 3382 elink_bsc_module_sel(params); 3383 3384 xfer_cnt = 16 - lc_addr; 3385 3386 /* Enable the engine */ 3387 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3388 val |= MCPR_IMC_COMMAND_ENABLE; 3389 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3390 3391 /* Program slave device ID */ 3392 val = (sl_devid << 16) | sl_addr; 3393 REG_WR(cb, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3394 3395 /* Start xfer with 0 byte to update the address pointer ???*/ 3396 val = (MCPR_IMC_COMMAND_ENABLE) | 3397 (MCPR_IMC_COMMAND_WRITE_OP << 3398 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3399 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3400 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3401 3402 /* Poll for completion */ 3403 i = 0; 3404 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3405 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3406 USLEEP(cb, 10); 3407 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3408 if (i++ > 1000) { 3409 ELINK_DEBUG_P1(cb, "wr 0 byte timed out after %d try\n", 3410 i); 3411 rc = ELINK_STATUS_TIMEOUT; 3412 break; 3413 } 3414 } 3415 if (rc == ELINK_STATUS_TIMEOUT) 3416 return rc; 3417 3418 /* Start xfer with read op */ 3419 val = (MCPR_IMC_COMMAND_ENABLE) | 3420 (MCPR_IMC_COMMAND_READ_OP << 3421 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3422 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3423 (xfer_cnt); 3424 REG_WR(cb, MCP_REG_MCPR_IMC_COMMAND, val); 3425 3426 /* Poll for completion */ 3427 i = 0; 3428 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3429 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3430 USLEEP(cb, 10); 3431 val = REG_RD(cb, MCP_REG_MCPR_IMC_COMMAND); 3432 if (i++ > 1000) { 3433 ELINK_DEBUG_P1(cb, "rd op timed out after %d try\n", i); 3434 rc = ELINK_STATUS_TIMEOUT; 3435 break; 3436 } 3437 } 3438 if (rc == ELINK_STATUS_TIMEOUT) 3439 return rc; 3440 3441 for (i = (lc_addr >> 2); i < 4; i++) { 3442 data_array[i] = REG_RD(cb, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3443 #ifdef BIG_ENDIAN 3444 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3445 ((data_array[i] & 0x0000ff00) << 8) | 3446 ((data_array[i] & 0x00ff0000) >> 8) | 3447 ((data_array[i] & 0xff000000) >> 24); 3448 #endif 3449 } 3450 return rc; 3451 } 3452 3453 #endif /* EXCLUDE_WARPCORE */ 3454 #endif /* EXCLUDE_NON_COMMON_INIT */ 3455 #if !defined(EXCLUDE_NON_COMMON_INIT) || defined(INCLUDE_WARPCORE_UC_LOAD) 3456 static void elink_cl45_read_or_write(struct elink_dev *cb, struct elink_phy *phy, 3457 u8 devad, u16 reg, u16 or_val) 3458 { 3459 u16 val; 3460 elink_cl45_read(cb, phy, devad, reg, &val); 3461 elink_cl45_write(cb, phy, devad, reg, val | or_val); 3462 } 3463 3464 static void elink_cl45_read_and_write(struct elink_dev *cb, 3465 struct elink_phy *phy, 3466 u8 devad, u16 reg, u16 and_val) 3467 { 3468 u16 val; 3469 elink_cl45_read(cb, phy, devad, reg, &val); 3470 elink_cl45_write(cb, phy, devad, reg, val & and_val); 3471 } 3472 #endif 3473 3474 #ifdef ELINK_ENHANCEMENTS 3475 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr, 3476 u8 devad, u16 reg, u16 *ret_val) 3477 { 3478 u8 phy_index; 3479 /* Probe for the phy according to the given phy_addr, and execute 3480 * the read request on it 3481 */ 3482 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3483 if (params->phy[phy_index].addr == phy_addr) { 3484 return elink_cl45_read(params->cb, 3485 ¶ms->phy[phy_index], devad, 3486 reg, ret_val); 3487 } 3488 } 3489 return ELINK_STATUS_ERROR; 3490 } 3491 3492 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr, 3493 u8 devad, u16 reg, u16 val) 3494 { 3495 u8 phy_index; 3496 /* Probe for the phy according to the given phy_addr, and execute 3497 * the write request on it 3498 */ 3499 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3500 if (params->phy[phy_index].addr == phy_addr) { 3501 return elink_cl45_write(params->cb, 3502 ¶ms->phy[phy_index], devad, 3503 reg, val); 3504 } 3505 } 3506 return ELINK_STATUS_ERROR; 3507 } 3508 #endif // ELINK_ENHANCEMENTS 3509 3510 #if (!defined EXCLUDE_NON_COMMON_INIT) || (!defined EXCLUDE_WARPCORE) 3511 static u8 elink_get_warpcore_lane(struct elink_phy *phy, 3512 struct elink_params *params) 3513 { 3514 u8 lane = 0; 3515 #ifndef EXCLUDE_WARPCORE 3516 struct elink_dev *cb = params->cb; 3517 u32 path_swap, path_swap_ovr; 3518 u8 path, port; 3519 3520 path = PATH_ID(cb); 3521 port = params->port; 3522 3523 if (elink_is_4_port_mode(cb)) { 3524 u32 port_swap, port_swap_ovr; 3525 3526 /* Figure out path swap value */ 3527 path_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3528 if (path_swap_ovr & 0x1) 3529 path_swap = (path_swap_ovr & 0x2); 3530 else 3531 path_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PATH_SWAP); 3532 3533 if (path_swap) 3534 path = path ^ 1; 3535 3536 /* Figure out port swap value */ 3537 port_swap_ovr = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3538 if (port_swap_ovr & 0x1) 3539 port_swap = (port_swap_ovr & 0x2); 3540 else 3541 port_swap = REG_RD(cb, MISC_REG_FOUR_PORT_PORT_SWAP); 3542 3543 if (port_swap) 3544 port = port ^ 1; 3545 3546 lane = (port<<1) + path; 3547 } else { /* Two port mode - no port swap */ 3548 3549 /* Figure out path swap value */ 3550 path_swap_ovr = 3551 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3552 if (path_swap_ovr & 0x1) { 3553 path_swap = (path_swap_ovr & 0x2); 3554 } else { 3555 path_swap = 3556 REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 3557 } 3558 if (path_swap) 3559 path = path ^ 1; 3560 3561 lane = path << 1 ; 3562 } 3563 #endif /* #ifndef EXCLUDE_WARPCORE */ 3564 return lane; 3565 } 3566 3567 3568 static void elink_set_aer_mmd(struct elink_params *params, 3569 struct elink_phy *phy) 3570 { 3571 u32 ser_lane; 3572 u16 offset, aer_val; 3573 struct elink_dev *cb = params->cb; 3574 ser_lane = ((params->lane_config & 3575 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 3576 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 3577 3578 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 3579 (phy->addr + ser_lane) : 0; 3580 3581 if (ELINK_USES_WARPCORE(params->chip_id)) { 3582 aer_val = elink_get_warpcore_lane(phy, params); 3583 /* In Dual-lane mode, two lanes are joined together, 3584 * so in order to configure them, the AER broadcast method is 3585 * used here. 3586 * 0x200 is the broadcast address for lanes 0,1 3587 * 0x201 is the broadcast address for lanes 2,3 3588 */ 3589 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 3590 aer_val = (aer_val >> 1) | 0x200; 3591 } else if (CHIP_IS_E2(params->chip_id)) 3592 aer_val = 0x3800 + offset - 1; 3593 else 3594 aer_val = 0x3800 + offset; 3595 3596 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 3597 MDIO_AER_BLOCK_AER_REG, aer_val); 3598 3599 } 3600 #endif 3601 #ifndef EXCLUDE_SERDES 3602 3603 /******************************************************************/ 3604 /* Internal phy section */ 3605 /******************************************************************/ 3606 3607 static void elink_set_serdes_access(struct elink_dev *cb, u8 port) 3608 { 3609 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3610 3611 /* Set Clause 22 */ 3612 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 3613 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 3614 USLEEP(cb, 500); 3615 REG_WR(cb, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 3616 USLEEP(cb, 500); 3617 /* Set Clause 45 */ 3618 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 3619 } 3620 3621 static void elink_serdes_deassert(struct elink_dev *cb, u8 port) 3622 { 3623 u32 val; 3624 3625 ELINK_DEBUG_P0(cb, "elink_serdes_deassert\n"); 3626 3627 val = ELINK_SERDES_RESET_BITS << (port*16); 3628 3629 /* Reset and unreset the SerDes/XGXS */ 3630 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3631 USLEEP(cb, 500); 3632 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3633 3634 elink_set_serdes_access(cb, port); 3635 3636 REG_WR(cb, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 3637 ELINK_DEFAULT_PHY_DEV_ADDR); 3638 } 3639 #endif /* #ifndef EXCLUDE_SERDES */ 3640 3641 #ifndef EXCLUDE_NON_COMMON_INIT 3642 #ifndef EXCLUDE_XGXS 3643 static void elink_xgxs_specific_func(struct elink_phy *phy, 3644 struct elink_params *params, 3645 u32 action) 3646 { 3647 struct elink_dev *cb = params->cb; 3648 switch (action) { 3649 case ELINK_PHY_INIT: 3650 /* Set correct devad */ 3651 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 3652 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 3653 phy->def_md_devad); 3654 break; 3655 } 3656 } 3657 3658 static void elink_xgxs_deassert(struct elink_params *params) 3659 { 3660 struct elink_dev *cb = params->cb; 3661 u8 port; 3662 u32 val; 3663 ELINK_DEBUG_P0(cb, "elink_xgxs_deassert\n"); 3664 port = params->port; 3665 3666 val = ELINK_XGXS_RESET_BITS << (port*16); 3667 3668 /* Reset and unreset the SerDes/XGXS */ 3669 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 3670 USLEEP(cb, 500); 3671 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 3672 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, 3673 ELINK_PHY_INIT); 3674 } 3675 #endif // EXCLUDE_XGXS 3676 3677 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, 3678 struct elink_params *params, u16 *ieee_fc) 3679 { 3680 #ifdef ELINK_DEBUG 3681 struct elink_dev *cb = params->cb; 3682 #endif 3683 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3684 /* Resolve pause mode and advertisement Please refer to Table 3685 * 28B-3 of the 802.3ab-1999 spec 3686 */ 3687 3688 switch (phy->req_flow_ctrl) { 3689 case ELINK_FLOW_CTRL_AUTO: 3690 switch (params->req_fc_auto_adv) { 3691 case ELINK_FLOW_CTRL_BOTH: 3692 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3693 break; 3694 case ELINK_FLOW_CTRL_RX: 3695 case ELINK_FLOW_CTRL_TX: 3696 *ieee_fc |= 3697 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3698 break; 3699 default: 3700 break; 3701 } 3702 break; 3703 case ELINK_FLOW_CTRL_TX: 3704 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 3705 break; 3706 3707 case ELINK_FLOW_CTRL_RX: 3708 case ELINK_FLOW_CTRL_BOTH: 3709 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 3710 break; 3711 3712 case ELINK_FLOW_CTRL_NONE: 3713 default: 3714 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 3715 break; 3716 } 3717 ELINK_DEBUG_P1(cb, "ieee_fc = 0x%x\n", *ieee_fc); 3718 } 3719 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 3720 3721 static void set_phy_vars(struct elink_params *params, 3722 struct elink_vars *vars) 3723 { 3724 #ifdef ELINK_DEBUG 3725 struct elink_dev *cb = params->cb; 3726 #endif 3727 u8 actual_phy_idx, phy_index, link_cfg_idx; 3728 u8 phy_config_swapped = params->multi_phy_config & 3729 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 3730 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 3731 phy_index++) { 3732 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); 3733 actual_phy_idx = phy_index; 3734 if (phy_config_swapped) { 3735 if (phy_index == ELINK_EXT_PHY1) 3736 actual_phy_idx = ELINK_EXT_PHY2; 3737 else if (phy_index == ELINK_EXT_PHY2) 3738 actual_phy_idx = ELINK_EXT_PHY1; 3739 } 3740 params->phy[actual_phy_idx].req_flow_ctrl = 3741 params->req_flow_ctrl[link_cfg_idx]; 3742 3743 params->phy[actual_phy_idx].req_line_speed = 3744 params->req_line_speed[link_cfg_idx]; 3745 3746 params->phy[actual_phy_idx].speed_cap_mask = 3747 params->speed_cap_mask[link_cfg_idx]; 3748 3749 params->phy[actual_phy_idx].req_duplex = 3750 params->req_duplex[link_cfg_idx]; 3751 3752 if (params->req_line_speed[link_cfg_idx] == 3753 ELINK_SPEED_AUTO_NEG) 3754 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 3755 3756 ELINK_DEBUG_P3(cb, "req_flow_ctrl %x, req_line_speed %x," 3757 " speed_cap_mask %x\n", 3758 params->phy[actual_phy_idx].req_flow_ctrl, 3759 params->phy[actual_phy_idx].req_line_speed, 3760 params->phy[actual_phy_idx].speed_cap_mask); 3761 } 3762 } 3763 3764 #ifndef EXCLUDE_NON_COMMON_INIT 3765 static void elink_ext_phy_set_pause(struct elink_params *params, 3766 struct elink_phy *phy, 3767 struct elink_vars *vars) 3768 { 3769 u16 val; 3770 struct elink_dev *cb = params->cb; 3771 /* Read modify write pause advertizing */ 3772 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 3773 3774 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3775 3776 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 3777 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 3778 if ((vars->ieee_fc & 3779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 3780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 3781 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 3782 } 3783 if ((vars->ieee_fc & 3784 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3785 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3786 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 3787 } 3788 ELINK_DEBUG_P1(cb, "Ext phy AN advertize 0x%x\n", val); 3789 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 3790 } 3791 3792 static void elink_pause_resolve(struct elink_vars *vars, u32 pause_result) 3793 { /* LD LP */ 3794 switch (pause_result) { /* ASYM P ASYM P */ 3795 case 0xb: /* 1 0 1 1 */ 3796 vars->flow_ctrl = ELINK_FLOW_CTRL_TX; 3797 break; 3798 3799 case 0xe: /* 1 1 1 0 */ 3800 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; 3801 break; 3802 3803 case 0x5: /* 0 1 0 1 */ 3804 case 0x7: /* 0 1 1 1 */ 3805 case 0xd: /* 1 1 0 1 */ 3806 case 0xf: /* 1 1 1 1 */ 3807 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; 3808 break; 3809 3810 default: 3811 break; 3812 } 3813 if (pause_result & (1<<0)) 3814 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3815 if (pause_result & (1<<1)) 3816 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3817 3818 } 3819 3820 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, 3821 struct elink_params *params, 3822 struct elink_vars *vars) 3823 { 3824 u16 ld_pause; /* local */ 3825 u16 lp_pause; /* link partner */ 3826 u16 pause_result; 3827 struct elink_dev *cb = params->cb; 3828 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 3829 #ifndef EXCLUDE_BCM54618SE 3830 elink_cl22_read(cb, phy, 0x4, &ld_pause); 3831 elink_cl22_read(cb, phy, 0x5, &lp_pause); 3832 #endif 3833 } else if (CHIP_IS_E3(params->chip_id) && 3834 ELINK_SINGLE_MEDIA_DIRECT(params)) { 3835 u8 lane = elink_get_warpcore_lane(phy, params); 3836 u16 gp_status, gp_mask; 3837 elink_cl45_read(cb, phy, 3838 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 3839 &gp_status); 3840 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 3841 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 3842 lane; 3843 if ((gp_status & gp_mask) == gp_mask) { 3844 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3845 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3846 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3847 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3848 } else { 3849 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3850 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 3851 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 3852 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 3853 ld_pause = ((ld_pause & 3854 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3855 << 3); 3856 lp_pause = ((lp_pause & 3857 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 3858 << 3); 3859 } 3860 } else { 3861 elink_cl45_read(cb, phy, 3862 MDIO_AN_DEVAD, 3863 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 3864 elink_cl45_read(cb, phy, 3865 MDIO_AN_DEVAD, 3866 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 3867 } 3868 pause_result = (ld_pause & 3869 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 3870 pause_result |= (lp_pause & 3871 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 3872 ELINK_DEBUG_P1(cb, "Ext PHY pause result 0x%x\n", pause_result); 3873 elink_pause_resolve(vars, pause_result); 3874 3875 } 3876 3877 static u8 elink_ext_phy_resolve_fc(struct elink_phy *phy, 3878 struct elink_params *params, 3879 struct elink_vars *vars) 3880 { 3881 u8 ret = 0; 3882 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 3883 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 3884 /* Update the advertised flow-controled of LD/LP in AN */ 3885 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 3886 elink_ext_phy_update_adv_fc(phy, params, vars); 3887 /* But set the flow-control result as the requested one */ 3888 vars->flow_ctrl = phy->req_flow_ctrl; 3889 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 3890 vars->flow_ctrl = params->req_fc_auto_adv; 3891 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 3892 ret = 1; 3893 elink_ext_phy_update_adv_fc(phy, params, vars); 3894 } 3895 return ret; 3896 } 3897 #endif // EXCLUDE_NON_COMMON_INIT 3898 /******************************************************************/ 3899 /* Warpcore section */ 3900 /******************************************************************/ 3901 /* The init_internal_warpcore should mirror the xgxs, 3902 * i.e. reset the lane (if needed), set aer for the 3903 * init configuration, and set/clear SGMII flag. Internal 3904 * phy init is done purely in phy_init stage. 3905 */ 3906 #define WC_TX_DRIVER(post2, idriver, ipre) \ 3907 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 3908 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 3909 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 3910 3911 #define WC_TX_FIR(post, main, pre) \ 3912 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 3913 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 3914 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 3915 3916 #ifndef EXCLUDE_WARPCORE 3917 #ifndef EXCLUDE_NON_COMMON_INIT 3918 static void elink_update_link_attr(struct elink_params *params, u32 link_attr) 3919 { 3920 struct elink_dev *cb = params->cb; 3921 3922 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 3923 REG_WR(cb, params->shmem2_base + 3924 OFFSETOF(struct shmem2_region, 3925 link_attr_sync[params->port]), link_attr); 3926 } 3927 3928 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, 3929 struct elink_params *params, 3930 struct elink_vars *vars) 3931 { 3932 struct elink_dev *cb = params->cb; 3933 u16 i; 3934 static struct elink_reg_set reg_set[] = { 3935 /* Step 1 - Program the TX/RX alignment markers */ 3936 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 3937 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 3938 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 3939 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 3940 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 3941 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 3942 /* Step 2 - Configure the NP registers */ 3943 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 3944 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 3945 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 3946 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 3947 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 3948 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 3949 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 3950 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 3951 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 3952 }; 3953 ELINK_DEBUG_P0(cb, "Enabling 20G-KR2\n"); 3954 3955 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 3956 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 3957 3958 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3959 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3960 reg_set[i].val); 3961 3962 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 3963 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 3964 elink_update_link_attr(params, params->link_attr_sync); 3965 } 3966 3967 static void elink_disable_kr2(struct elink_params *params, 3968 struct elink_vars *vars, 3969 struct elink_phy *phy) 3970 { 3971 struct elink_dev *cb = params->cb; 3972 int i; 3973 static struct elink_reg_set reg_set[] = { 3974 /* Step 1 - Program the TX/RX alignment markers */ 3975 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 3976 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 3977 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 3978 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 3979 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 3980 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 3981 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 3982 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 3983 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 3984 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 3985 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 3986 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 3987 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 3988 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 3989 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 3990 }; 3991 ELINK_DEBUG_P0(cb, "Disabling 20G-KR2\n"); 3992 3993 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 3994 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 3995 reg_set[i].val); 3996 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 3997 elink_update_link_attr(params, params->link_attr_sync); 3998 3999 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; 4000 } 4001 4002 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, 4003 struct elink_params *params) 4004 { 4005 struct elink_dev *cb = params->cb; 4006 4007 ELINK_DEBUG_P0(cb, "Configure WC for LPI pass through\n"); 4008 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4009 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 4010 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4011 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 4012 } 4013 4014 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, 4015 struct elink_params *params) 4016 { 4017 /* Restart autoneg on the leading lane only */ 4018 struct elink_dev *cb = params->cb; 4019 u16 lane = elink_get_warpcore_lane(phy, params); 4020 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4021 MDIO_AER_BLOCK_AER_REG, lane); 4022 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4023 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4024 4025 /* Restore AER */ 4026 elink_set_aer_mmd(params, phy); 4027 } 4028 4029 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, 4030 struct elink_params *params, 4031 struct elink_vars *vars) { 4032 u16 lane, i, cl72_ctrl, an_adv = 0, val; 4033 u32 wc_lane_config; 4034 struct elink_dev *cb = params->cb; 4035 static struct elink_reg_set reg_set[] = { 4036 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4037 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 4038 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 4039 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 4040 /* Disable Autoneg: re-enable it after adv is done. */ 4041 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 4042 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 4043 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 4044 }; 4045 ELINK_DEBUG_P0(cb, "Enable Auto Negotiation for KR\n"); 4046 /* Set to default registers that may be overriden by 10G force */ 4047 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4048 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4049 reg_set[i].val); 4050 4051 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4052 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 4053 cl72_ctrl &= 0x08ff; 4054 cl72_ctrl |= 0x3800; 4055 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4056 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 4057 4058 /* Check adding advertisement for 1G KX */ 4059 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4060 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 4061 (vars->line_speed == ELINK_SPEED_1000)) { 4062 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 4063 an_adv |= (1<<5); 4064 4065 /* Enable CL37 1G Parallel Detect */ 4066 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, addr, 0x1); 4067 ELINK_DEBUG_P0(cb, "Advertize 1G\n"); 4068 } 4069 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4070 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 4071 (vars->line_speed == ELINK_SPEED_10000)) { 4072 /* Check adding advertisement for 10G KR */ 4073 an_adv |= (1<<7); 4074 /* Enable 10G Parallel Detect */ 4075 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4076 MDIO_AER_BLOCK_AER_REG, 0); 4077 4078 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4079 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 4080 elink_set_aer_mmd(params, phy); 4081 ELINK_DEBUG_P0(cb, "Advertize 10G\n"); 4082 } 4083 4084 /* Set Transmit PMD settings */ 4085 lane = elink_get_warpcore_lane(phy, params); 4086 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4087 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4088 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4089 /* Configure the next lane if dual mode */ 4090 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4091 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4092 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 4093 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4094 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4095 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 4096 0x03f0); 4097 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4098 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 4099 0x03f0); 4100 4101 /* Advertised speeds */ 4102 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4103 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 4104 4105 /* Advertised and set FEC (Forward Error Correction) */ 4106 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4107 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 4108 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 4109 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 4110 4111 /* Enable CL37 BAM */ 4112 if (REG_RD(cb, params->shmem_base + 4113 OFFSETOF(struct shmem_region, dev_info. 4114 port_hw_config[params->port].default_cfg)) & 4115 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 4116 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4117 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 4118 1); 4119 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 4120 } 4121 4122 /* Advertise pause */ 4123 elink_ext_phy_set_pause(params, phy, vars); 4124 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 4125 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4126 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 4127 4128 /* Over 1G - AN local device user page 1 */ 4129 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4130 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 4131 4132 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 4133 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 4134 (phy->req_line_speed == ELINK_SPEED_20000)) { 4135 4136 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4137 MDIO_AER_BLOCK_AER_REG, lane); 4138 4139 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4140 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 4141 (1<<11)); 4142 4143 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4144 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 4145 elink_set_aer_mmd(params, phy); 4146 4147 elink_warpcore_enable_AN_KR2(phy, params, vars); 4148 } else { 4149 /* Enable Auto-Detect to support 1G over CL37 as well */ 4150 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4151 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); 4152 wc_lane_config = REG_RD(cb, params->shmem_base + 4153 OFFSETOF(struct shmem_region, dev_info. 4154 shared_hw_config.wc_lane_config)); 4155 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4156 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); 4157 /* Force cl48 sync_status LOW to avoid getting stuck in CL73 4158 * parallel-detect loop when CL73 and CL37 are enabled. 4159 */ 4160 val |= 1 << 11; 4161 4162 /* Restore Polarity settings in case it was run over by 4163 * previous link owner 4164 */ 4165 if (wc_lane_config & 4166 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) 4167 val |= 3 << 2; 4168 else 4169 val &= ~(3 << 2); 4170 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4171 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), 4172 val); 4173 4174 elink_disable_kr2(params, vars, phy); 4175 } 4176 4177 /* Enable Autoneg: only on the main lane */ 4178 elink_warpcore_restart_AN_KR(phy, params); 4179 } 4180 4181 static void elink_warpcore_set_10G_KR(struct elink_phy *phy, 4182 struct elink_params *params, 4183 struct elink_vars *vars) 4184 { 4185 struct elink_dev *cb = params->cb; 4186 u16 val16, i, lane; 4187 static struct elink_reg_set reg_set[] = { 4188 /* Disable Autoneg */ 4189 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4190 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 4191 0x3f00}, 4192 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 4193 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 4194 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 4195 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 4196 /* Leave cl72 training enable, needed for KR */ 4197 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 4198 }; 4199 4200 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4201 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 4202 reg_set[i].val); 4203 4204 lane = elink_get_warpcore_lane(phy, params); 4205 /* Global registers */ 4206 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4207 MDIO_AER_BLOCK_AER_REG, 0); 4208 /* Disable CL36 PCS Tx */ 4209 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4210 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4211 val16 &= ~(0x0011 << lane); 4212 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4213 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4214 4215 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4216 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4217 val16 |= (0x0303 << (lane << 1)); 4218 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4219 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4220 /* Restore AER */ 4221 elink_set_aer_mmd(params, phy); 4222 /* Set speed via PMA/PMD register */ 4223 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4224 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 4225 4226 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 4227 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 4228 4229 /* Enable encoded forced speed */ 4230 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4231 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 4232 4233 /* Turn TX scramble payload only the 64/66 scrambler */ 4234 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4235 MDIO_WC_REG_TX66_CONTROL, 0x9); 4236 4237 /* Turn RX scramble payload only the 64/66 scrambler */ 4238 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4239 MDIO_WC_REG_RX66_CONTROL, 0xF9); 4240 4241 /* Set and clear loopback to cause a reset to 64/66 decoder */ 4242 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4243 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 4244 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4245 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 4246 4247 } 4248 4249 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, 4250 struct elink_params *params, 4251 u8 is_xfi) 4252 { 4253 struct elink_dev *cb = params->cb; 4254 u16 misc1_val, tap_val, tx_driver_val, lane, val; 4255 u32 cfg_tap_val, tx_drv_brdct, tx_equal; 4256 4257 /* Hold rxSeqStart */ 4258 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4259 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 4260 4261 /* Hold tx_fifo_reset */ 4262 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4263 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 4264 4265 /* Disable CL73 AN */ 4266 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 4267 4268 /* Disable 100FX Enable and Auto-Detect */ 4269 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4270 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 4271 4272 /* Disable 100FX Idle detect */ 4273 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4274 MDIO_WC_REG_FX100_CTRL3, 0x0080); 4275 4276 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 4277 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4278 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 4279 4280 /* Turn off auto-detect & fiber mode */ 4281 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4282 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4283 0xFFEE); 4284 4285 /* Set filter_force_link, disable_false_link and parallel_detect */ 4286 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4287 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 4288 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4289 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4290 ((val | 0x0006) & 0xFFFE)); 4291 4292 /* Set XFI / SFI */ 4293 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4294 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 4295 4296 misc1_val &= ~(0x1f); 4297 4298 if (is_xfi) { 4299 misc1_val |= 0x5; 4300 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4301 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 4302 } else { 4303 cfg_tap_val = REG_RD(cb, params->shmem_base + 4304 OFFSETOF(struct shmem_region, dev_info. 4305 port_hw_config[params->port]. 4306 sfi_tap_values)); 4307 4308 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4309 4310 tx_drv_brdct = (cfg_tap_val & 4311 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4312 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4313 4314 misc1_val |= 0x9; 4315 4316 /* TAP values are controlled by nvram, if value there isn't 0 */ 4317 if (tx_equal) 4318 tap_val = (u16)tx_equal; 4319 else 4320 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4321 4322 if (tx_drv_brdct) 4323 tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct, 4324 0x06); 4325 else 4326 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4327 } 4328 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4329 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4330 4331 /* Set Transmit PMD settings */ 4332 lane = elink_get_warpcore_lane(phy, params); 4333 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4334 MDIO_WC_REG_TX_FIR_TAP, 4335 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4336 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4337 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4338 tx_driver_val); 4339 4340 /* Enable fiber mode, enable and invert sig_det */ 4341 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4342 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4343 4344 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4345 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4346 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4347 4348 elink_warpcore_set_lpi_passthrough(phy, params); 4349 4350 /* 10G XFI Full Duplex */ 4351 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4352 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4353 4354 /* Release tx_fifo_reset */ 4355 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4356 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4357 0xFFFE); 4358 /* Release rxSeqStart */ 4359 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4360 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4361 } 4362 #endif //EXCLUDE_NON_COMMON_INIT 4363 4364 #ifndef ELINK_AUX_POWER 4365 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, 4366 struct elink_params *params) 4367 { 4368 u16 val; 4369 struct elink_dev *cb = params->cb; 4370 /* Set global registers, so set AER lane to 0 */ 4371 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4372 MDIO_AER_BLOCK_AER_REG, 0); 4373 4374 /* Disable sequencer */ 4375 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4376 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4377 4378 elink_set_aer_mmd(params, phy); 4379 4380 elink_cl45_read_and_write(cb, phy, MDIO_PMA_DEVAD, 4381 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4382 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4383 MDIO_AN_REG_CTRL, 0); 4384 /* Turn off CL73 */ 4385 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4386 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4387 val &= ~(1<<5); 4388 val |= (1<<6); 4389 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4390 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4391 4392 /* Set 20G KR2 force speed */ 4393 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4394 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4395 4396 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4397 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4398 4399 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4400 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4401 val &= ~(3<<14); 4402 val |= (1<<15); 4403 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4404 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4405 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4406 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4407 4408 /* Enable sequencer (over lane 0) */ 4409 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4410 MDIO_AER_BLOCK_AER_REG, 0); 4411 4412 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4413 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4414 4415 elink_set_aer_mmd(params, phy); 4416 } 4417 #endif 4418 4419 #ifndef EXCLUDE_COMMON_INIT 4420 static void elink_warpcore_set_20G_DXGXS(struct elink_dev *cb, 4421 struct elink_phy *phy, 4422 u16 lane) 4423 { 4424 /* Rx0 anaRxControl1G */ 4425 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4426 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4427 4428 /* Rx2 anaRxControl1G */ 4429 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4430 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4431 4432 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4433 MDIO_WC_REG_RX66_SCW0, 0xE070); 4434 4435 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4436 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4437 4438 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4439 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4440 4441 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4442 MDIO_WC_REG_RX66_SCW3, 0x8090); 4443 4444 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4445 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4446 4447 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4448 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4449 4450 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4451 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4452 4453 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4454 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4455 4456 /* Serdes Digital Misc1 */ 4457 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4458 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4459 4460 /* Serdes Digital4 Misc3 */ 4461 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4462 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4463 4464 /* Set Transmit PMD settings */ 4465 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4466 MDIO_WC_REG_TX_FIR_TAP, 4467 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4468 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4469 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4470 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4471 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4472 } 4473 #endif 4474 4475 #ifndef EXCLUDE_NON_COMMON_INIT 4476 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, 4477 struct elink_params *params, 4478 u8 fiber_mode, 4479 u8 always_autoneg) 4480 { 4481 struct elink_dev *cb = params->cb; 4482 u16 val16, digctrl_kx1, digctrl_kx2; 4483 4484 /* Clear XFI clock comp in non-10G single lane mode. */ 4485 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4486 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4487 4488 elink_warpcore_set_lpi_passthrough(phy, params); 4489 4490 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 4491 /* SGMII Autoneg */ 4492 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4493 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4494 0x1000); 4495 ELINK_DEBUG_P0(cb, "set SGMII AUTONEG\n"); 4496 } else { 4497 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4498 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4499 val16 &= 0xcebf; 4500 switch (phy->req_line_speed) { 4501 case ELINK_SPEED_10: 4502 break; 4503 case ELINK_SPEED_100: 4504 val16 |= 0x2000; 4505 break; 4506 case ELINK_SPEED_1000: 4507 val16 |= 0x0040; 4508 break; 4509 default: 4510 ELINK_DEBUG_P1(cb, 4511 "Speed not supported: 0x%x\n", phy->req_line_speed); 4512 return; 4513 } 4514 4515 if (phy->req_duplex == DUPLEX_FULL) 4516 val16 |= 0x0100; 4517 4518 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4519 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4520 4521 ELINK_DEBUG_P1(cb, "set SGMII force speed %d\n", 4522 phy->req_line_speed); 4523 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4524 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4525 ELINK_DEBUG_P1(cb, " (readback) %x\n", val16); 4526 } 4527 4528 /* SGMII Slave mode and disable signal detect */ 4529 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4530 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4531 if (fiber_mode) 4532 digctrl_kx1 = 1; 4533 else 4534 digctrl_kx1 &= 0xff4a; 4535 4536 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4537 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4538 digctrl_kx1); 4539 4540 /* Turn off parallel detect */ 4541 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4542 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4543 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4544 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4545 (digctrl_kx2 & ~(1<<2))); 4546 4547 /* Re-enable parallel detect */ 4548 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4549 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4550 (digctrl_kx2 | (1<<2))); 4551 4552 /* Enable autodet */ 4553 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4554 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4555 (digctrl_kx1 | 0x10)); 4556 } 4557 4558 #endif //EXCLUDE_NON_COMMON_INIT 4559 4560 static void elink_warpcore_reset_lane(struct elink_dev *cb, 4561 struct elink_phy *phy, 4562 u8 reset) 4563 { 4564 u16 val; 4565 /* Take lane out of reset after configuration is finished */ 4566 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4567 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4568 if (reset) 4569 val |= 0xC000; 4570 else 4571 val &= 0x3FFF; 4572 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4573 MDIO_WC_REG_DIGITAL5_MISC6, val); 4574 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4575 MDIO_WC_REG_DIGITAL5_MISC6, &val); 4576 } 4577 4578 #ifndef EXCLUDE_NON_COMMON_INIT 4579 /* Clear SFI/XFI link settings registers */ 4580 static void elink_warpcore_clear_regs(struct elink_phy *phy, 4581 struct elink_params *params, 4582 u16 lane) 4583 { 4584 struct elink_dev *cb = params->cb; 4585 u16 i; 4586 static struct elink_reg_set wc_regs[] = { 4587 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 4588 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 4589 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 4590 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 4591 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4592 0x0195}, 4593 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4594 0x0007}, 4595 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4596 0x0002}, 4597 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 4598 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 4599 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 4600 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 4601 }; 4602 /* Set XFI clock comp as default. */ 4603 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4604 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 4605 4606 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 4607 elink_cl45_write(cb, phy, wc_regs[i].devad, wc_regs[i].reg, 4608 wc_regs[i].val); 4609 4610 lane = elink_get_warpcore_lane(phy, params); 4611 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4612 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 4613 4614 } 4615 4616 static elink_status_t elink_get_mod_abs_int_cfg(struct elink_dev *cb, 4617 u32 chip_id, 4618 u32 shmem_base, u8 port, 4619 u8 *gpio_num, u8 *gpio_port) 4620 { 4621 u32 cfg_pin; 4622 *gpio_num = 0; 4623 *gpio_port = 0; 4624 if (CHIP_IS_E3(chip_id)) { 4625 cfg_pin = (REG_RD(cb, shmem_base + 4626 OFFSETOF(struct shmem_region, 4627 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4628 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4629 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4630 4631 /* Should not happen. This function called upon interrupt 4632 * triggered by GPIO ( since EPIO can only generate interrupts 4633 * to MCP). 4634 * So if this function was called and none of the GPIOs was set, 4635 * it means the shit hit the fan. 4636 */ 4637 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 4638 (cfg_pin > PIN_CFG_GPIO3_P1)) { 4639 ELINK_DEBUG_P1(cb, 4640 "No cfg pin %x for module detect indication\n", 4641 cfg_pin); 4642 return ELINK_STATUS_ERROR; 4643 } 4644 4645 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 4646 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 4647 } else { 4648 *gpio_num = MISC_REGISTERS_GPIO_3; 4649 *gpio_port = port; 4650 } 4651 4652 return ELINK_STATUS_OK; 4653 } 4654 4655 static int elink_is_sfp_module_plugged(struct elink_phy *phy, 4656 struct elink_params *params) 4657 { 4658 struct elink_dev *cb = params->cb; 4659 u8 gpio_num, gpio_port; 4660 u32 gpio_val; 4661 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, 4662 params->shmem_base, params->port, 4663 &gpio_num, &gpio_port) != ELINK_STATUS_OK) 4664 return 0; 4665 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 4666 4667 /* Call the handling function in case module is detected */ 4668 if (gpio_val == 0) 4669 return 1; 4670 else 4671 return 0; 4672 } 4673 int elink_warpcore_get_sigdet(struct elink_phy *phy, 4674 struct elink_params *params) 4675 { 4676 u16 gp2_status_reg0, lane; 4677 struct elink_dev *cb = params->cb; 4678 4679 lane = elink_get_warpcore_lane(phy, params); 4680 4681 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 4682 &gp2_status_reg0); 4683 4684 return (gp2_status_reg0 >> (8+lane)) & 0x1; 4685 } 4686 4687 #ifndef ELINK_AUX_POWER 4688 static void elink_warpcore_config_runtime(struct elink_phy *phy, 4689 struct elink_params *params, 4690 struct elink_vars *vars) 4691 { 4692 struct elink_dev *cb = params->cb; 4693 u32 serdes_net_if; 4694 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 4695 4696 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 4697 4698 if (!vars->turn_to_run_wc_rt) 4699 return; 4700 4701 if (vars->rx_tx_asic_rst) { 4702 u16 lane = elink_get_warpcore_lane(phy, params); 4703 serdes_net_if = (REG_RD(cb, params->shmem_base + 4704 OFFSETOF(struct shmem_region, dev_info. 4705 port_hw_config[params->port].default_cfg)) & 4706 PORT_HW_CFG_NET_SERDES_IF_MASK); 4707 4708 switch (serdes_net_if) { 4709 case PORT_HW_CFG_NET_SERDES_IF_KR: 4710 /* Do we get link yet? */ 4711 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 0x81d1, 4712 &gp_status1); 4713 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 4714 /*10G KR*/ 4715 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 4716 4717 if (lnkup_kr || lnkup) { 4718 vars->rx_tx_asic_rst = 0; 4719 } else { 4720 /* Reset the lane to see if link comes up.*/ 4721 elink_warpcore_reset_lane(cb, phy, 1); 4722 elink_warpcore_reset_lane(cb, phy, 0); 4723 4724 /* Restart Autoneg */ 4725 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 4726 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4727 4728 vars->rx_tx_asic_rst--; 4729 ELINK_DEBUG_P1(cb, "0x%x retry left\n", 4730 vars->rx_tx_asic_rst); 4731 } 4732 break; 4733 4734 default: 4735 break; 4736 } 4737 4738 } /*params->rx_tx_asic_rst*/ 4739 4740 } 4741 #endif 4742 static void elink_warpcore_config_sfi(struct elink_phy *phy, 4743 struct elink_params *params) 4744 { 4745 u16 lane = elink_get_warpcore_lane(phy, params); 4746 #ifdef ELINK_DEBUG 4747 struct elink_dev *cb = params->cb; 4748 #endif 4749 elink_warpcore_clear_regs(phy, params, lane); 4750 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == 4751 ELINK_SPEED_10000) && 4752 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { 4753 ELINK_DEBUG_P0(cb, "Setting 10G SFI\n"); 4754 elink_warpcore_set_10G_XFI(phy, params, 0); 4755 } else { 4756 ELINK_DEBUG_P0(cb, "Setting 1G Fiber\n"); 4757 elink_warpcore_set_sgmii_speed(phy, params, 1, 0); 4758 } 4759 } 4760 4761 static void elink_sfp_e3_set_transmitter(struct elink_params *params, 4762 struct elink_phy *phy, 4763 u8 tx_en) 4764 { 4765 struct elink_dev *cb = params->cb; 4766 u32 cfg_pin; 4767 u8 port = params->port; 4768 4769 cfg_pin = REG_RD(cb, params->shmem_base + 4770 OFFSETOF(struct shmem_region, 4771 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 4772 PORT_HW_CFG_E3_TX_LASER_MASK; 4773 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 4774 ELINK_DEBUG_P1(cb, "Setting WC TX to %d\n", tx_en); 4775 4776 /* For 20G, the expected pin to be used is 3 pins after the current */ 4777 elink_set_cfg_pin(cb, cfg_pin, tx_en ^ 1); 4778 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 4779 elink_set_cfg_pin(cb, cfg_pin + 3, tx_en ^ 1); 4780 } 4781 4782 static elink_status_t 4783 elink_warpcore_config_init(struct elink_phy *phy, struct elink_params *params, 4784 struct elink_vars *vars) 4785 { 4786 struct elink_dev *cb = params->cb; 4787 u32 serdes_net_if; 4788 u8 fiber_mode; 4789 u16 lane = elink_get_warpcore_lane(phy, params); 4790 serdes_net_if = (REG_RD(cb, params->shmem_base + 4791 OFFSETOF(struct shmem_region, dev_info. 4792 port_hw_config[params->port].default_cfg)) & 4793 PORT_HW_CFG_NET_SERDES_IF_MASK); 4794 ELINK_DEBUG_P2(cb, "Begin Warpcore init, link_speed %d, " 4795 "serdes_net_if = 0x%x\n", 4796 vars->line_speed, serdes_net_if); 4797 elink_set_aer_mmd(params, phy); 4798 elink_warpcore_reset_lane(cb, phy, 1); 4799 vars->phy_flags |= PHY_XGXS_FLAG; 4800 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 4801 (phy->req_line_speed && 4802 ((phy->req_line_speed == ELINK_SPEED_100) || 4803 (phy->req_line_speed == ELINK_SPEED_10)))) { 4804 vars->phy_flags |= PHY_SGMII_FLAG; 4805 ELINK_DEBUG_P0(cb, "Setting SGMII mode\n"); 4806 elink_warpcore_clear_regs(phy, params, lane); 4807 elink_warpcore_set_sgmii_speed(phy, params, 0, 1); 4808 } else { 4809 switch (serdes_net_if) { 4810 case PORT_HW_CFG_NET_SERDES_IF_KR: 4811 /* Enable KR Auto Neg */ 4812 if (params->loopback_mode != ELINK_LOOPBACK_EXT) 4813 elink_warpcore_enable_AN_KR(phy, params, vars); 4814 else { 4815 ELINK_DEBUG_P0(cb, "Setting KR 10G-Force\n"); 4816 elink_warpcore_set_10G_KR(phy, params, vars); 4817 } 4818 break; 4819 4820 case PORT_HW_CFG_NET_SERDES_IF_XFI: 4821 elink_warpcore_clear_regs(phy, params, lane); 4822 if (vars->line_speed == ELINK_SPEED_10000) { 4823 ELINK_DEBUG_P0(cb, "Setting 10G XFI\n"); 4824 elink_warpcore_set_10G_XFI(phy, params, 1); 4825 } else { 4826 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 4827 ELINK_DEBUG_P0(cb, "1G Fiber\n"); 4828 fiber_mode = 1; 4829 } else { 4830 ELINK_DEBUG_P0(cb, "10/100/1G SGMII\n"); 4831 fiber_mode = 0; 4832 } 4833 elink_warpcore_set_sgmii_speed(phy, 4834 params, 4835 fiber_mode, 4836 0); 4837 } 4838 4839 break; 4840 4841 case PORT_HW_CFG_NET_SERDES_IF_SFI: 4842 /* Issue Module detection if module is plugged, or 4843 * enabled transmitter to avoid current leakage in case 4844 * no module is connected 4845 */ 4846 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || 4847 (params->loopback_mode == ELINK_LOOPBACK_EXT)) { 4848 if (elink_is_sfp_module_plugged(phy, params)) 4849 elink_sfp_module_detection(phy, params); 4850 else 4851 elink_sfp_e3_set_transmitter(params, 4852 phy, 1); 4853 } 4854 4855 elink_warpcore_config_sfi(phy, params); 4856 break; 4857 4858 #ifndef ELINK_AUX_POWER 4859 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 4860 if (vars->line_speed != ELINK_SPEED_20000) { 4861 ELINK_DEBUG_P0(cb, "Speed not supported yet\n"); 4862 return (ELINK_STATUS_ERROR); 4863 } 4864 ELINK_DEBUG_P0(cb, "Setting 20G DXGXS\n"); 4865 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 4866 /* Issue Module detection */ 4867 4868 elink_sfp_module_detection(phy, params); 4869 break; 4870 #endif 4871 case PORT_HW_CFG_NET_SERDES_IF_KR2: 4872 if (!params->loopback_mode) { 4873 elink_warpcore_enable_AN_KR(phy, params, vars); 4874 } else { 4875 #ifndef ELINK_AUX_POWER 4876 ELINK_DEBUG_P0(cb, "Setting KR 20G-Force\n"); 4877 elink_warpcore_set_20G_force_KR2(phy, params); 4878 #endif 4879 } 4880 break; 4881 default: 4882 ELINK_DEBUG_P1(cb, 4883 "Unsupported Serdes Net Interface 0x%x\n", 4884 serdes_net_if); 4885 return (ELINK_STATUS_ERROR); 4886 } 4887 } 4888 4889 /* Take lane out of reset after configuration is finished */ 4890 elink_warpcore_reset_lane(cb, phy, 0); 4891 ELINK_DEBUG_P0(cb, "Exit config init\n"); 4892 return (ELINK_STATUS_OK); 4893 } 4894 4895 static void elink_warpcore_link_reset(struct elink_phy *phy, 4896 struct elink_params *params) 4897 { 4898 #ifndef EXCLUDE_LINK_RESET 4899 struct elink_dev *cb = params->cb; 4900 u16 val16, lane; 4901 elink_sfp_e3_set_transmitter(params, phy, 0); 4902 elink_set_mdio_emac_per_phy(cb, params); 4903 elink_set_aer_mmd(params, phy); 4904 /* Global register */ 4905 elink_warpcore_reset_lane(cb, phy, 1); 4906 4907 /* Clear loopback settings (if any) */ 4908 /* 10G & 20G */ 4909 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4910 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 4911 4912 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4913 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 4914 4915 /* Update those 1-copy registers */ 4916 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4917 MDIO_AER_BLOCK_AER_REG, 0); 4918 /* Enable 1G MDIO (1-copy) */ 4919 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4920 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4921 ~0x10); 4922 4923 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 4924 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 4925 lane = elink_get_warpcore_lane(phy, params); 4926 /* Disable CL36 PCS Tx */ 4927 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4928 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4929 val16 |= (0x11 << lane); 4930 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4931 val16 |= (0x22 << lane); 4932 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4933 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4934 4935 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4936 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4937 val16 &= ~(0x0303 << (lane << 1)); 4938 val16 |= (0x0101 << (lane << 1)); 4939 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { 4940 val16 &= ~(0x0c0c << (lane << 1)); 4941 val16 |= (0x0404 << (lane << 1)); 4942 } 4943 4944 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4945 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4946 /* Restore AER */ 4947 elink_set_aer_mmd(params, phy); 4948 #endif 4949 4950 } 4951 4952 static void elink_set_warpcore_loopback(struct elink_phy *phy, 4953 struct elink_params *params) 4954 { 4955 #ifdef ELINK_INCLUDE_LOOPBACK 4956 struct elink_dev *cb = params->cb; 4957 u16 val16; 4958 u32 lane; 4959 ELINK_DEBUG_P2(cb, "Setting Warpcore loopback type %x, speed %d\n", 4960 params->loopback_mode, phy->req_line_speed); 4961 4962 if (phy->req_line_speed < ELINK_SPEED_10000 || 4963 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 4964 /* 10/100/1000/20G-KR2 */ 4965 4966 /* Update those 1-copy registers */ 4967 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 4968 MDIO_AER_BLOCK_AER_REG, 0); 4969 /* Enable 1G MDIO (1-copy) */ 4970 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4971 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4972 0x10); 4973 /* Set 1G loopback based on lane (1-copy) */ 4974 lane = elink_get_warpcore_lane(phy, params); 4975 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 4976 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 4977 val16 |= (1<<lane); 4978 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4979 val16 |= (2<<lane); 4980 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 4981 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 4982 val16); 4983 4984 /* Switch back to 4-copy registers */ 4985 elink_set_aer_mmd(params, phy); 4986 } else { 4987 /* 10G / 20G-DXGXS */ 4988 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4989 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4990 0x4000); 4991 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 4992 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 4993 } 4994 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 4995 } 4996 #endif // EXCLUDE_NON_COMMON_INIT 4997 #endif // #ifndef EXCLUDE_WARPCORE 4998 4999 #ifdef INCLUDE_WARPCORE_UC_LOAD 5000 static void elink_warpcore_powerdown_secondport_lanes(struct elink_dev *cb, 5001 struct elink_phy *phy) 5002 { 5003 u16 path_swap_ovr, path_swap, i; 5004 u8 power_down_lanes[4]; 5005 5006 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5007 MDIO_WC_REG_XGXSBLK1_LANETEST0, 0); 5008 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5009 MDIO_WC_REG_XGXS_X2_CONTROL2, 0x29FB); 5010 5011 /* Figure out path swap value */ 5012 path_swap_ovr = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 5013 if (path_swap_ovr & 0x1) 5014 path_swap = (path_swap_ovr & 0x2); 5015 else 5016 path_swap = REG_RD(cb, MISC_REG_TWO_PORT_PATH_SWAP); 5017 5018 /* Find which lanes to power down according to path swap value */ 5019 if (path_swap) { 5020 power_down_lanes[0] = 1; 5021 power_down_lanes[1] = 1; 5022 power_down_lanes[2] = 0; 5023 power_down_lanes[3] = 1; 5024 } else { 5025 power_down_lanes[0] = 0; 5026 power_down_lanes[1] = 1; 5027 power_down_lanes[2] = 1; 5028 power_down_lanes[3] = 1; 5029 } 5030 5031 /* Go through lanes which should be powered down */ 5032 for (i = 0; i < 4; i++) { 5033 if (power_down_lanes[i]) { 5034 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5035 MDIO_WC_REG_XGXSBLK1_LANECTRL3, 5036 (1 << i) | (1 << (4+i)) | 5037 (1 << 11)); 5038 5039 elink_cl45_read_and_write( 5040 cb, phy, MDIO_WC_DEVAD, 5041 MDIO_WC_REG_XGXSBLK1_LANECTRL0, 5042 ~((u16)((1 << i) | (1 << (4+i))))); 5043 } 5044 } 5045 } 5046 #endif //INCLUDE_WARPCORE_UC_LOAD 5047 5048 #ifdef INCLUDE_WARPCORE_UC_LOAD 5049 /** 5050 * elink_warpcore_sequencer 5051 * 5052 * @param cb 5053 * @param phy 5054 * @param enable - sequencer 5055 * 5056 * @return u32 5057 * 5058 * Before starting any of the specific speed/protocol flow, 5059 * there's need disable the sequencer and once all 5060 * configurations are made the sequencer will be enabled again. 5061 * That way it is guaranteed that improper link won't be 5062 * established during the init phase. 5063 */ 5064 static void elink_warpcore_sequencer(struct elink_dev *cb, 5065 struct elink_phy *phy, 5066 u8 enable){ 5067 5068 u16 val16; 5069 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5070 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, &val16); 5071 if(enable) 5072 val16 |= 0x2000; 5073 else 5074 val16 &= 0xDFFF; 5075 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5076 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, val16); 5077 } 5078 5079 static void elink_warpcore_set_lane_swap(struct elink_dev *cb, 5080 struct elink_phy *phy, 5081 u32 wc_lane_config) 5082 { 5083 u16 rx_lane_swap, tx_lane_swap, val16; 5084 rx_lane_swap = ((wc_lane_config & 5085 SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5086 SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5087 5088 tx_lane_swap = ((wc_lane_config & 5089 SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5090 SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5091 5092 /* Rx Lanes */ 5093 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5094 MDIO_WC_REG_XGXS_RX_LN_SWAP1, &val16); 5095 val16 &= 0xFF00; 5096 val16 |= rx_lane_swap; 5097 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5098 MDIO_WC_REG_XGXS_RX_LN_SWAP1, val16); 5099 5100 /* Tx Lanes */ 5101 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5102 MDIO_WC_REG_XGXS_TX_LN_SWAP1, &val16); 5103 val16 &= 0xFF00; 5104 val16 |= tx_lane_swap; 5105 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5106 MDIO_WC_REG_XGXS_TX_LN_SWAP1, val16); 5107 } 5108 5109 static void elink_warpcore_set_lane_polarity(struct elink_dev *cb, 5110 struct elink_phy *phy, 5111 u32 wc_lane_config) 5112 { 5113 /* Set RX polarity on all lanes; flip and enable the flip. */ 5114 if (wc_lane_config & SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED) 5115 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5116 MDIO_WC_REG_RX0_PCI_CTRL, (3<<2)); 5117 if (wc_lane_config & SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED) 5118 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5119 MDIO_WC_REG_RX1_PCI_CTRL, (3<<2)); 5120 if (wc_lane_config & SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED) 5121 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5122 MDIO_WC_REG_RX2_PCI_CTRL, (3<<2)); 5123 if (wc_lane_config & SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED) 5124 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5125 MDIO_WC_REG_RX3_PCI_CTRL, (3<<2)); 5126 /* Set TX polarity on all lanes */ 5127 if (wc_lane_config & SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED) 5128 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5129 MDIO_WC_REG_TX0_ANA_CTRL0, (1<<5)); 5130 if (wc_lane_config & SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED) 5131 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5132 MDIO_WC_REG_TX1_ANA_CTRL0, (1<<5)); 5133 if (wc_lane_config & SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED) 5134 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5135 MDIO_WC_REG_TX2_ANA_CTRL0, (1<<5)); 5136 if (wc_lane_config & SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED) 5137 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5138 MDIO_WC_REG_TX3_ANA_CTRL0, (1<<5)); 5139 } 5140 5141 static elink_status_t elink_reset_warpcore(struct elink_dev *cb) 5142 { 5143 u16 time; 5144 u32 pll_lock; 5145 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 5146 5147 REG_WR(cb, MISC_REG_WC0_RESET, 0xE); 5148 MSLEEP(cb, 1); 5149 REG_WR(cb, MISC_REG_WC0_RESET, 0xF); 5150 5151 for(time = 0; time < ELINK_MDIO_ACCESS_TIMEOUT; time++) { 5152 MSLEEP(cb, 1); 5153 pll_lock = REG_RD(cb, MISC_REG_WC0_PLL_LOCK); 5154 if (pll_lock & 0x1) { 5155 /* Flush all TX fifo */ 5156 REG_WR(cb, MISC_REG_WC0_RESET, 0x3FF); 5157 break; 5158 } 5159 } 5160 if (time == ELINK_MDIO_ACCESS_TIMEOUT) { 5161 ELINK_DEBUG_P0(cb, "BUG! WARPCORE is still in reset!\n"); 5162 return ELINK_STATUS_ERROR; 5163 } 5164 5165 return ELINK_STATUS_OK; 5166 } 5167 5168 5169 static void elink_warpcore_set_quad_mode(struct elink_dev *cb, 5170 struct elink_phy *phy) 5171 { 5172 u16 lane, val; 5173 /* Need to set lanes 0..3 */ 5174 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5175 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5176 MDIO_AER_BLOCK_AER_REG, lane); 5177 /* Reset Asic lane */ 5178 elink_warpcore_reset_lane(cb, phy, 1); 5179 // This access is required only for version 0xd101 of the WC FW 5180 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5181 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5182 &val); 5183 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5184 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5185 (val & 0xfe07) | 0x78); 5186 5187 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5188 MDIO_WC_REG_DSC_SMC, 0x8000); 5189 5190 /* Set on clock compensation in WC */ 5191 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5192 MDIO_WC_REG_RX66_CONTROL, 0x7415); 5193 5194 /* Set on clock compensation in WC 5195 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5196 * that clock comensation in cl48 modes is enabled during 5197 * multi-port modes, and disabled during single port modes. 5198 */ 5199 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5200 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5201 0x8091); 5202 } 5203 } 5204 5205 static void elink_warpcore_set_dual_mode(struct elink_dev *cb, 5206 struct elink_phy *phy, 5207 u32 shmem_base) 5208 { 5209 u16 lane, val; 5210 u32 serdes_net_if; 5211 for (lane = 0; lane < WC_LANE_MAX; lane++) { 5212 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5213 MDIO_AER_BLOCK_AER_REG, lane); 5214 5215 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5216 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5217 &val); 5218 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5219 MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL, 5220 (val & 0xfe07) | 0x50); 5221 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5222 MDIO_WC_REG_CL49_USERB0_CTRL, 5223 (3<<6)); 5224 5225 /* Set on clock compensation in WC 5226 * For WC/B0 programming register 0x8104 to value 0x8091 insures 5227 * that clock comensation in cl48 modes is enabled during 5228 * multi-port modes, and disabled during single port modes. 5229 */ 5230 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5231 MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G, 5232 0x8091); 5233 /* In dual port mode XFI compensation should be disabled by 5234 * setting 0x83C0[14:13] to 2'b00 for each port. 5235 */ 5236 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5237 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 5238 5239 /* This access is required only for version 0xd101 of the 5240 * WC FW 5241 */ 5242 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5243 MDIO_WC_REG_DSC_SMC, 0x8000); 5244 } 5245 5246 serdes_net_if = (REG_RD(cb, shmem_base + 5247 OFFSETOF(struct shmem_region, dev_info. 5248 port_hw_config[0].default_cfg)) & 5249 PORT_HW_CFG_NET_SERDES_IF_MASK); 5250 5251 /* Configure both ports to 20G to enable clock working on both ports */ 5252 for (lane = 0x200; lane <= 0x201; lane++) { 5253 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5254 MDIO_AER_BLOCK_AER_REG, lane); 5255 elink_warpcore_reset_lane(cb, phy, 1); 5256 if (serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_DXGXS) 5257 elink_warpcore_set_20G_DXGXS(cb, phy, lane); 5258 } 5259 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5260 MDIO_WC_REG_RX1_PCI_CTRL, (1<<11)); 5261 elink_cl45_read_or_write(cb, phy, MDIO_WC_DEVAD, 5262 MDIO_WC_REG_RX3_PCI_CTRL, (1<<11)); 5263 } 5264 5265 static elink_status_t elink_warpcore_load_uc(struct elink_dev *cb, 5266 struct elink_phy *phy) 5267 { 5268 u16 val, cnt; 5269 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 5270 MDIO_AER_BLOCK_AER_REG, 0); 5271 5272 /* Enable External memory access */ 5273 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5274 MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP, 0x0000); 5275 5276 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5277 MDIO_WC_REG_MICROBLK_CMD3, 0x0407); 5278 5279 /* Initialize ram memory prior to programming it */ 5280 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5281 MDIO_WC_REG_MICROBLK_CMD, 0x8000); 5282 5283 /* Wait for completion of memory initialization */ 5284 for (cnt = 0; cnt < ELINK_WC_UC_TIMEOUT; cnt++) { 5285 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5286 MDIO_WC_REG_MICROBLK_DL_STATUS , &val); 5287 if (val & 0x8000) 5288 break; 5289 USLEEP(cb, 1); 5290 } 5291 if (cnt >= ELINK_WC_UC_TIMEOUT) 5292 return ELINK_STATUS_TIMEOUT; 5293 5294 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, MDIO_WC_REG_UC_INFO_B1_CRC, 0); 5295 5296 /* Load Warpcore microcode for E3 and after */ 5297 elink_cb_load_warpcore_microcode(); 5298 5299 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5300 MDIO_WC_REG_MICROBLK_CMD3, 0x0404); 5301 5302 /* Turn off read_for_cmd bit, check for FW setting this later. */ 5303 elink_cl45_read_and_write(cb, phy, MDIO_WC_DEVAD, 5304 MDIO_WC_REG_DSC1B0_UC_CTRL, 5305 ~MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD); 5306 5307 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 5308 MDIO_WC_REG_MICROBLK_CMD, 0x0810); 5309 for (cnt = 0; cnt < ELINK_WC_RDY_TIMEOUT_MSEC; cnt++) { 5310 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 5311 MDIO_WC_REG_DSC1B0_UC_CTRL, &val); 5312 if (val & MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD) 5313 break; 5314 MSLEEP(cb, 1); 5315 } 5316 if (cnt >= ELINK_WC_RDY_TIMEOUT_MSEC) 5317 return ELINK_STATUS_TIMEOUT; 5318 5319 return ELINK_STATUS_OK; 5320 } 5321 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 5322 5323 static void elink_sync_link(struct elink_params *params, 5324 struct elink_vars *vars) 5325 { 5326 #ifdef ELINK_DEBUG 5327 struct elink_dev *cb = params->cb; 5328 #endif 5329 u8 link_10g_plus; 5330 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5331 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 5332 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 5333 if (vars->link_up) { 5334 ELINK_DEBUG_P0(cb, "phy link up\n"); 5335 5336 vars->phy_link_up = 1; 5337 vars->duplex = DUPLEX_FULL; 5338 switch (vars->link_status & 5339 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 5340 case ELINK_LINK_10THD: 5341 vars->duplex = DUPLEX_HALF; 5342 /* Fall thru */ 5343 case ELINK_LINK_10TFD: 5344 vars->line_speed = ELINK_SPEED_10; 5345 break; 5346 5347 case ELINK_LINK_100TXHD: 5348 vars->duplex = DUPLEX_HALF; 5349 /* Fall thru */ 5350 case ELINK_LINK_100T4: 5351 case ELINK_LINK_100TXFD: 5352 vars->line_speed = ELINK_SPEED_100; 5353 break; 5354 5355 case ELINK_LINK_1000THD: 5356 vars->duplex = DUPLEX_HALF; 5357 /* Fall thru */ 5358 case ELINK_LINK_1000TFD: 5359 vars->line_speed = ELINK_SPEED_1000; 5360 break; 5361 5362 case ELINK_LINK_2500THD: 5363 vars->duplex = DUPLEX_HALF; 5364 /* Fall thru */ 5365 case ELINK_LINK_2500TFD: 5366 vars->line_speed = ELINK_SPEED_2500; 5367 break; 5368 5369 case ELINK_LINK_10GTFD: 5370 vars->line_speed = ELINK_SPEED_10000; 5371 break; 5372 case ELINK_LINK_20GTFD: 5373 vars->line_speed = ELINK_SPEED_20000; 5374 break; 5375 default: 5376 break; 5377 } 5378 vars->flow_ctrl = 0; 5379 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 5380 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; 5381 5382 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 5383 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; 5384 5385 if (!vars->flow_ctrl) 5386 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5387 5388 if (vars->line_speed && 5389 ((vars->line_speed == ELINK_SPEED_10) || 5390 (vars->line_speed == ELINK_SPEED_100))) { 5391 vars->phy_flags |= PHY_SGMII_FLAG; 5392 } else { 5393 vars->phy_flags &= ~PHY_SGMII_FLAG; 5394 } 5395 #ifndef EXCLUDE_WARPCORE 5396 if (vars->line_speed && 5397 ELINK_USES_WARPCORE(params->chip_id) && 5398 (vars->line_speed == ELINK_SPEED_1000)) 5399 vars->phy_flags |= PHY_SGMII_FLAG; 5400 #endif /* #ifndef EXCLUDE_WARPCORE */ 5401 /* Anything 10 and over uses the bmac */ 5402 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 5403 5404 if (link_10g_plus) { 5405 if (ELINK_USES_WARPCORE(params->chip_id)) 5406 vars->mac_type = ELINK_MAC_TYPE_XMAC; 5407 else 5408 vars->mac_type = ELINK_MAC_TYPE_BMAC; 5409 } else { 5410 if (ELINK_USES_WARPCORE(params->chip_id)) 5411 vars->mac_type = ELINK_MAC_TYPE_UMAC; 5412 else 5413 vars->mac_type = ELINK_MAC_TYPE_EMAC; 5414 } 5415 } else { /* Link down */ 5416 ELINK_DEBUG_P0(cb, "phy link down\n"); 5417 5418 vars->phy_link_up = 0; 5419 5420 vars->line_speed = 0; 5421 vars->duplex = DUPLEX_FULL; 5422 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5423 5424 /* Indicate no mac active */ 5425 vars->mac_type = ELINK_MAC_TYPE_NONE; 5426 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5427 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 5428 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 5429 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 5430 } 5431 } 5432 5433 void elink_link_status_update(struct elink_params *params, 5434 struct elink_vars *vars) 5435 { 5436 struct elink_dev *cb = params->cb; 5437 u8 port = params->port; 5438 u32 sync_offset, media_types; 5439 /* Update PHY configuration */ 5440 set_phy_vars(params, vars); 5441 5442 vars->link_status = REG_RD(cb, params->shmem_base + 5443 OFFSETOF(struct shmem_region, 5444 port_mb[port].link_status)); 5445 5446 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 5447 if (params->loopback_mode != ELINK_LOOPBACK_NONE && 5448 params->loopback_mode != ELINK_LOOPBACK_EXT) 5449 vars->link_status |= LINK_STATUS_LINK_UP; 5450 5451 #ifndef EXCLUDE_NON_COMMON_INIT 5452 #ifndef EXCLUDE_WARPCORE 5453 if (elink_eee_has_cap(params)) 5454 vars->eee_status = REG_RD(cb, params->shmem2_base + 5455 OFFSETOF(struct shmem2_region, 5456 eee_status[params->port])); 5457 #endif 5458 #endif 5459 5460 vars->phy_flags = PHY_XGXS_FLAG; 5461 elink_sync_link(params, vars); 5462 /* Sync media type */ 5463 sync_offset = params->shmem_base + 5464 OFFSETOF(struct shmem_region, 5465 dev_info.port_hw_config[port].media_type); 5466 media_types = REG_RD(cb, sync_offset); 5467 5468 params->phy[ELINK_INT_PHY].media_type = 5469 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 5470 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 5471 params->phy[ELINK_EXT_PHY1].media_type = 5472 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 5473 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 5474 params->phy[ELINK_EXT_PHY2].media_type = 5475 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 5476 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 5477 ELINK_DEBUG_P1(cb, "media_types = 0x%x\n", media_types); 5478 5479 /* Sync AEU offset */ 5480 sync_offset = params->shmem_base + 5481 OFFSETOF(struct shmem_region, 5482 dev_info.port_hw_config[port].aeu_int_mask); 5483 5484 vars->aeu_int_mask = REG_RD(cb, sync_offset); 5485 5486 /* Sync PFC status */ 5487 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 5488 params->feature_config_flags |= 5489 ELINK_FEATURE_CONFIG_PFC_ENABLED; 5490 else 5491 params->feature_config_flags &= 5492 ~ELINK_FEATURE_CONFIG_PFC_ENABLED; 5493 5494 if (SHMEM2_HAS(cb, params->shmem2_base, link_attr_sync)) 5495 params->link_attr_sync = SHMEM2_RD(cb, params->shmem2_base, 5496 link_attr_sync[params->port]); 5497 5498 ELINK_DEBUG_P3(cb, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 5499 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 5500 ELINK_DEBUG_P3(cb, "line_speed %x duplex %x flow_ctrl 0x%x\n", 5501 vars->line_speed, vars->duplex, vars->flow_ctrl); 5502 } 5503 5504 #ifndef EXCLUDE_NON_COMMON_INIT 5505 #ifndef EXCLUDE_XGXS 5506 static void elink_set_master_ln(struct elink_params *params, 5507 struct elink_phy *phy) 5508 { 5509 struct elink_dev *cb = params->cb; 5510 u16 new_master_ln, ser_lane; 5511 ser_lane = ((params->lane_config & 5512 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5513 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5514 5515 /* Set the master_ln for AN */ 5516 CL22_RD_OVER_CL45(cb, phy, 5517 MDIO_REG_BANK_XGXS_BLOCK2, 5518 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5519 &new_master_ln); 5520 5521 CL22_WR_OVER_CL45(cb, phy, 5522 MDIO_REG_BANK_XGXS_BLOCK2 , 5523 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5524 (new_master_ln | ser_lane)); 5525 } 5526 5527 static elink_status_t elink_reset_unicore(struct elink_params *params, 5528 struct elink_phy *phy, 5529 u8 set_serdes) 5530 { 5531 struct elink_dev *cb = params->cb; 5532 u16 mii_control; 5533 u16 i; 5534 CL22_RD_OVER_CL45(cb, phy, 5535 MDIO_REG_BANK_COMBO_IEEE0, 5536 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 5537 5538 /* Reset the unicore */ 5539 CL22_WR_OVER_CL45(cb, phy, 5540 MDIO_REG_BANK_COMBO_IEEE0, 5541 MDIO_COMBO_IEEE0_MII_CONTROL, 5542 (mii_control | 5543 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 5544 #ifndef EXCLUDE_SERDES 5545 if (set_serdes) 5546 elink_set_serdes_access(cb, params->port); 5547 #endif /* EXCLUDE_SERDES */ 5548 5549 /* Wait for the reset to self clear */ 5550 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { 5551 USLEEP(cb, 5); 5552 5553 /* The reset erased the previous bank value */ 5554 CL22_RD_OVER_CL45(cb, phy, 5555 MDIO_REG_BANK_COMBO_IEEE0, 5556 MDIO_COMBO_IEEE0_MII_CONTROL, 5557 &mii_control); 5558 5559 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 5560 USLEEP(cb, 5); 5561 return ELINK_STATUS_OK; 5562 } 5563 } 5564 5565 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 5566 // " Port %d\n", 5567 5568 ELINK_DEBUG_P0(cb, "BUG! XGXS is still in reset!\n"); 5569 return ELINK_STATUS_ERROR; 5570 5571 } 5572 5573 static void elink_set_swap_lanes(struct elink_params *params, 5574 struct elink_phy *phy) 5575 { 5576 struct elink_dev *cb = params->cb; 5577 /* Each two bits represents a lane number: 5578 * No swap is 0123 => 0x1b no need to enable the swap 5579 */ 5580 u16 rx_lane_swap, tx_lane_swap; 5581 5582 rx_lane_swap = ((params->lane_config & 5583 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5584 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5585 tx_lane_swap = ((params->lane_config & 5586 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5587 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5588 5589 if (rx_lane_swap != 0x1b) { 5590 CL22_WR_OVER_CL45(cb, phy, 5591 MDIO_REG_BANK_XGXS_BLOCK2, 5592 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 5593 (rx_lane_swap | 5594 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 5595 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 5596 } else { 5597 CL22_WR_OVER_CL45(cb, phy, 5598 MDIO_REG_BANK_XGXS_BLOCK2, 5599 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 5600 } 5601 5602 if (tx_lane_swap != 0x1b) { 5603 CL22_WR_OVER_CL45(cb, phy, 5604 MDIO_REG_BANK_XGXS_BLOCK2, 5605 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 5606 (tx_lane_swap | 5607 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 5608 } else { 5609 CL22_WR_OVER_CL45(cb, phy, 5610 MDIO_REG_BANK_XGXS_BLOCK2, 5611 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 5612 } 5613 } 5614 5615 static void elink_set_parallel_detection(struct elink_phy *phy, 5616 struct elink_params *params) 5617 { 5618 struct elink_dev *cb = params->cb; 5619 u16 control2; 5620 CL22_RD_OVER_CL45(cb, phy, 5621 MDIO_REG_BANK_SERDES_DIGITAL, 5622 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5623 &control2); 5624 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5625 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5626 else 5627 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5628 ELINK_DEBUG_P2(cb, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 5629 phy->speed_cap_mask, control2); 5630 CL22_WR_OVER_CL45(cb, phy, 5631 MDIO_REG_BANK_SERDES_DIGITAL, 5632 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5633 control2); 5634 5635 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 5636 (phy->speed_cap_mask & 5637 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5638 ELINK_DEBUG_P0(cb, "XGXS\n"); 5639 5640 CL22_WR_OVER_CL45(cb, phy, 5641 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5642 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5643 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5644 5645 CL22_RD_OVER_CL45(cb, phy, 5646 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5647 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5648 &control2); 5649 5650 5651 control2 |= 5652 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5653 5654 CL22_WR_OVER_CL45(cb, phy, 5655 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5656 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5657 control2); 5658 5659 /* Disable parallel detection of HiG */ 5660 CL22_WR_OVER_CL45(cb, phy, 5661 MDIO_REG_BANK_XGXS_BLOCK2, 5662 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5663 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5664 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5665 } 5666 } 5667 5668 static void elink_set_autoneg(struct elink_phy *phy, 5669 struct elink_params *params, 5670 struct elink_vars *vars, 5671 u8 enable_cl73) 5672 { 5673 struct elink_dev *cb = params->cb; 5674 u16 reg_val; 5675 5676 /* CL37 Autoneg */ 5677 CL22_RD_OVER_CL45(cb, phy, 5678 MDIO_REG_BANK_COMBO_IEEE0, 5679 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5680 5681 /* CL37 Autoneg Enabled */ 5682 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5683 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5684 else /* CL37 Autoneg Disabled */ 5685 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5686 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5687 5688 CL22_WR_OVER_CL45(cb, phy, 5689 MDIO_REG_BANK_COMBO_IEEE0, 5690 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5691 5692 /* Enable/Disable Autodetection */ 5693 5694 CL22_RD_OVER_CL45(cb, phy, 5695 MDIO_REG_BANK_SERDES_DIGITAL, 5696 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5697 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5698 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5699 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5700 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5701 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5702 else 5703 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5704 5705 CL22_WR_OVER_CL45(cb, phy, 5706 MDIO_REG_BANK_SERDES_DIGITAL, 5707 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5708 5709 /* Enable TetonII and BAM autoneg */ 5710 CL22_RD_OVER_CL45(cb, phy, 5711 MDIO_REG_BANK_BAM_NEXT_PAGE, 5712 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5713 ®_val); 5714 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { 5715 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5716 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5717 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5718 } else { 5719 /* TetonII and BAM Autoneg Disabled */ 5720 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5722 } 5723 CL22_WR_OVER_CL45(cb, phy, 5724 MDIO_REG_BANK_BAM_NEXT_PAGE, 5725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5726 reg_val); 5727 5728 if (enable_cl73) { 5729 /* Enable Cl73 FSM status bits */ 5730 CL22_WR_OVER_CL45(cb, phy, 5731 MDIO_REG_BANK_CL73_USERB0, 5732 MDIO_CL73_USERB0_CL73_UCTRL, 5733 0xe); 5734 5735 /* Enable BAM Station Manager*/ 5736 CL22_WR_OVER_CL45(cb, phy, 5737 MDIO_REG_BANK_CL73_USERB0, 5738 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5739 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5740 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5741 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5742 5743 /* Advertise CL73 link speeds */ 5744 CL22_RD_OVER_CL45(cb, phy, 5745 MDIO_REG_BANK_CL73_IEEEB1, 5746 MDIO_CL73_IEEEB1_AN_ADV2, 5747 ®_val); 5748 if (phy->speed_cap_mask & 5749 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5750 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5751 if (phy->speed_cap_mask & 5752 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5753 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5754 5755 CL22_WR_OVER_CL45(cb, phy, 5756 MDIO_REG_BANK_CL73_IEEEB1, 5757 MDIO_CL73_IEEEB1_AN_ADV2, 5758 reg_val); 5759 5760 /* CL73 Autoneg Enabled */ 5761 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5762 5763 } else /* CL73 Autoneg Disabled */ 5764 reg_val = 0; 5765 5766 CL22_WR_OVER_CL45(cb, phy, 5767 MDIO_REG_BANK_CL73_IEEEB0, 5768 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5769 } 5770 5771 /* Program SerDes, forced speed */ 5772 static void elink_program_serdes(struct elink_phy *phy, 5773 struct elink_params *params, 5774 struct elink_vars *vars) 5775 { 5776 struct elink_dev *cb = params->cb; 5777 u16 reg_val; 5778 5779 /* Program duplex, disable autoneg and sgmii*/ 5780 CL22_RD_OVER_CL45(cb, phy, 5781 MDIO_REG_BANK_COMBO_IEEE0, 5782 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5783 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5784 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5785 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5786 if (phy->req_duplex == DUPLEX_FULL) 5787 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5788 CL22_WR_OVER_CL45(cb, phy, 5789 MDIO_REG_BANK_COMBO_IEEE0, 5790 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5791 5792 /* Program speed 5793 * - needed only if the speed is greater than 1G (2.5G or 10G) 5794 */ 5795 CL22_RD_OVER_CL45(cb, phy, 5796 MDIO_REG_BANK_SERDES_DIGITAL, 5797 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5798 /* Clearing the speed value before setting the right speed */ 5799 ELINK_DEBUG_P1(cb, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5800 5801 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5802 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5803 5804 if (!((vars->line_speed == ELINK_SPEED_1000) || 5805 (vars->line_speed == ELINK_SPEED_100) || 5806 (vars->line_speed == ELINK_SPEED_10))) { 5807 5808 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5809 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5810 if (vars->line_speed == ELINK_SPEED_10000) 5811 reg_val |= 5812 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5813 } 5814 5815 CL22_WR_OVER_CL45(cb, phy, 5816 MDIO_REG_BANK_SERDES_DIGITAL, 5817 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5818 5819 } 5820 5821 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, 5822 struct elink_params *params) 5823 { 5824 struct elink_dev *cb = params->cb; 5825 u16 val = 0; 5826 5827 /* Set extended capabilities */ 5828 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5829 val |= MDIO_OVER_1G_UP1_2_5G; 5830 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5831 val |= MDIO_OVER_1G_UP1_10G; 5832 CL22_WR_OVER_CL45(cb, phy, 5833 MDIO_REG_BANK_OVER_1G, 5834 MDIO_OVER_1G_UP1, val); 5835 5836 CL22_WR_OVER_CL45(cb, phy, 5837 MDIO_REG_BANK_OVER_1G, 5838 MDIO_OVER_1G_UP3, 0x400); 5839 } 5840 5841 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, 5842 struct elink_params *params, 5843 u16 ieee_fc) 5844 { 5845 struct elink_dev *cb = params->cb; 5846 u16 val; 5847 /* For AN, we are always publishing full duplex */ 5848 5849 CL22_WR_OVER_CL45(cb, phy, 5850 MDIO_REG_BANK_COMBO_IEEE0, 5851 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5852 CL22_RD_OVER_CL45(cb, phy, 5853 MDIO_REG_BANK_CL73_IEEEB1, 5854 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5855 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5856 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5857 CL22_WR_OVER_CL45(cb, phy, 5858 MDIO_REG_BANK_CL73_IEEEB1, 5859 MDIO_CL73_IEEEB1_AN_ADV1, val); 5860 } 5861 5862 static void elink_restart_autoneg(struct elink_phy *phy, 5863 struct elink_params *params, 5864 u8 enable_cl73) 5865 { 5866 struct elink_dev *cb = params->cb; 5867 u16 mii_control; 5868 5869 ELINK_DEBUG_P0(cb, "elink_restart_autoneg\n"); 5870 /* Enable and restart BAM/CL37 aneg */ 5871 5872 if (enable_cl73) { 5873 CL22_RD_OVER_CL45(cb, phy, 5874 MDIO_REG_BANK_CL73_IEEEB0, 5875 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5876 &mii_control); 5877 5878 CL22_WR_OVER_CL45(cb, phy, 5879 MDIO_REG_BANK_CL73_IEEEB0, 5880 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5881 (mii_control | 5882 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5883 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5884 } else { 5885 5886 CL22_RD_OVER_CL45(cb, phy, 5887 MDIO_REG_BANK_COMBO_IEEE0, 5888 MDIO_COMBO_IEEE0_MII_CONTROL, 5889 &mii_control); 5890 ELINK_DEBUG_P1(cb, 5891 "elink_restart_autoneg mii_control before = 0x%x\n", 5892 mii_control); 5893 CL22_WR_OVER_CL45(cb, phy, 5894 MDIO_REG_BANK_COMBO_IEEE0, 5895 MDIO_COMBO_IEEE0_MII_CONTROL, 5896 (mii_control | 5897 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5898 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 5899 } 5900 } 5901 5902 static void elink_initialize_sgmii_process(struct elink_phy *phy, 5903 struct elink_params *params, 5904 struct elink_vars *vars) 5905 { 5906 struct elink_dev *cb = params->cb; 5907 u16 control1; 5908 5909 /* In SGMII mode, the unicore is always slave */ 5910 5911 CL22_RD_OVER_CL45(cb, phy, 5912 MDIO_REG_BANK_SERDES_DIGITAL, 5913 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5914 &control1); 5915 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 5916 /* Set sgmii mode (and not fiber) */ 5917 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 5918 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 5919 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 5920 CL22_WR_OVER_CL45(cb, phy, 5921 MDIO_REG_BANK_SERDES_DIGITAL, 5922 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 5923 control1); 5924 5925 /* If forced speed */ 5926 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { 5927 /* Set speed, disable autoneg */ 5928 u16 mii_control; 5929 5930 CL22_RD_OVER_CL45(cb, phy, 5931 MDIO_REG_BANK_COMBO_IEEE0, 5932 MDIO_COMBO_IEEE0_MII_CONTROL, 5933 &mii_control); 5934 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5935 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 5936 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 5937 5938 switch (vars->line_speed) { 5939 case ELINK_SPEED_100: 5940 mii_control |= 5941 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 5942 break; 5943 case ELINK_SPEED_1000: 5944 mii_control |= 5945 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 5946 break; 5947 case ELINK_SPEED_10: 5948 /* There is nothing to set for 10M */ 5949 break; 5950 default: 5951 /* Invalid speed for SGMII */ 5952 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 5953 vars->line_speed); 5954 break; 5955 } 5956 5957 /* Setting the full duplex */ 5958 if (phy->req_duplex == DUPLEX_FULL) 5959 mii_control |= 5960 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5961 CL22_WR_OVER_CL45(cb, phy, 5962 MDIO_REG_BANK_COMBO_IEEE0, 5963 MDIO_COMBO_IEEE0_MII_CONTROL, 5964 mii_control); 5965 5966 } else { /* AN mode */ 5967 /* Enable and restart AN */ 5968 elink_restart_autoneg(phy, params, 0); 5969 } 5970 } 5971 5972 /* Link management 5973 */ 5974 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, 5975 struct elink_params *params) 5976 { 5977 struct elink_dev *cb = params->cb; 5978 u16 pd_10g, status2_1000x; 5979 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 5980 return ELINK_STATUS_OK; 5981 CL22_RD_OVER_CL45(cb, phy, 5982 MDIO_REG_BANK_SERDES_DIGITAL, 5983 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5984 &status2_1000x); 5985 CL22_RD_OVER_CL45(cb, phy, 5986 MDIO_REG_BANK_SERDES_DIGITAL, 5987 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 5988 &status2_1000x); 5989 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 5990 ELINK_DEBUG_P1(cb, "1G parallel detect link on port %d\n", 5991 params->port); 5992 return 1; 5993 } 5994 5995 CL22_RD_OVER_CL45(cb, phy, 5996 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5997 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 5998 &pd_10g); 5999 6000 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 6001 ELINK_DEBUG_P1(cb, "10G parallel detect link on port %d\n", 6002 params->port); 6003 return 1; 6004 } 6005 return ELINK_STATUS_OK; 6006 } 6007 6008 static void elink_update_adv_fc(struct elink_phy *phy, 6009 struct elink_params *params, 6010 struct elink_vars *vars, 6011 u32 gp_status) 6012 { 6013 u16 ld_pause; /* local driver */ 6014 u16 lp_pause; /* link partner */ 6015 u16 pause_result; 6016 struct elink_dev *cb = params->cb; 6017 if ((gp_status & 6018 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6019 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 6020 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6021 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 6022 6023 CL22_RD_OVER_CL45(cb, phy, 6024 MDIO_REG_BANK_CL73_IEEEB1, 6025 MDIO_CL73_IEEEB1_AN_ADV1, 6026 &ld_pause); 6027 CL22_RD_OVER_CL45(cb, phy, 6028 MDIO_REG_BANK_CL73_IEEEB1, 6029 MDIO_CL73_IEEEB1_AN_LP_ADV1, 6030 &lp_pause); 6031 pause_result = (ld_pause & 6032 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 6033 pause_result |= (lp_pause & 6034 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 6035 ELINK_DEBUG_P1(cb, "pause_result CL73 0x%x\n", pause_result); 6036 } else { 6037 CL22_RD_OVER_CL45(cb, phy, 6038 MDIO_REG_BANK_COMBO_IEEE0, 6039 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 6040 &ld_pause); 6041 CL22_RD_OVER_CL45(cb, phy, 6042 MDIO_REG_BANK_COMBO_IEEE0, 6043 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 6044 &lp_pause); 6045 pause_result = (ld_pause & 6046 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 6047 pause_result |= (lp_pause & 6048 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 6049 ELINK_DEBUG_P1(cb, "pause_result CL37 0x%x\n", pause_result); 6050 } 6051 elink_pause_resolve(vars, pause_result); 6052 6053 } 6054 6055 static void elink_flow_ctrl_resolve(struct elink_phy *phy, 6056 struct elink_params *params, 6057 struct elink_vars *vars, 6058 u32 gp_status) 6059 { 6060 #ifdef ELINK_DEBUG 6061 struct elink_dev *cb = params->cb; 6062 #endif 6063 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6064 6065 /* Resolve from gp_status in case of AN complete and not sgmii */ 6066 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 6067 /* Update the advertised flow-controled of LD/LP in AN */ 6068 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6069 elink_update_adv_fc(phy, params, vars, gp_status); 6070 /* But set the flow-control result as the requested one */ 6071 vars->flow_ctrl = phy->req_flow_ctrl; 6072 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 6073 vars->flow_ctrl = params->req_fc_auto_adv; 6074 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && 6075 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 6076 if (elink_direct_parallel_detect_used(phy, params)) { 6077 vars->flow_ctrl = params->req_fc_auto_adv; 6078 return; 6079 } 6080 elink_update_adv_fc(phy, params, vars, gp_status); 6081 } 6082 ELINK_DEBUG_P1(cb, "flow_ctrl 0x%x\n", vars->flow_ctrl); 6083 } 6084 6085 static void elink_check_fallback_to_cl37(struct elink_phy *phy, 6086 struct elink_params *params) 6087 { 6088 struct elink_dev *cb = params->cb; 6089 u16 rx_status, ustat_val, cl37_fsm_received; 6090 ELINK_DEBUG_P0(cb, "elink_check_fallback_to_cl37\n"); 6091 /* Step 1: Make sure signal is detected */ 6092 CL22_RD_OVER_CL45(cb, phy, 6093 MDIO_REG_BANK_RX0, 6094 MDIO_RX0_RX_STATUS, 6095 &rx_status); 6096 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 6097 (MDIO_RX0_RX_STATUS_SIGDET)) { 6098 ELINK_DEBUG_P1(cb, "Signal is not detected. Restoring CL73." 6099 "rx_status(0x80b0) = 0x%x\n", rx_status); 6100 CL22_WR_OVER_CL45(cb, phy, 6101 MDIO_REG_BANK_CL73_IEEEB0, 6102 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6103 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 6104 return; 6105 } 6106 /* Step 2: Check CL73 state machine */ 6107 CL22_RD_OVER_CL45(cb, phy, 6108 MDIO_REG_BANK_CL73_USERB0, 6109 MDIO_CL73_USERB0_CL73_USTAT1, 6110 &ustat_val); 6111 if ((ustat_val & 6112 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6113 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 6114 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6115 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 6116 ELINK_DEBUG_P1(cb, "CL73 state-machine is not stable. " 6117 "ustat_val(0x8371) = 0x%x\n", ustat_val); 6118 return; 6119 } 6120 /* Step 3: Check CL37 Message Pages received to indicate LP 6121 * supports only CL37 6122 */ 6123 CL22_RD_OVER_CL45(cb, phy, 6124 MDIO_REG_BANK_REMOTE_PHY, 6125 MDIO_REMOTE_PHY_MISC_RX_STATUS, 6126 &cl37_fsm_received); 6127 if ((cl37_fsm_received & 6128 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6129 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 6130 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6131 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 6132 ELINK_DEBUG_P1(cb, "No CL37 FSM were received. " 6133 "misc_rx_status(0x8330) = 0x%x\n", 6134 cl37_fsm_received); 6135 return; 6136 } 6137 /* The combined cl37/cl73 fsm state information indicating that 6138 * we are connected to a device which does not support cl73, but 6139 * does support cl37 BAM. In this case we disable cl73 and 6140 * restart cl37 auto-neg 6141 */ 6142 6143 /* Disable CL73 */ 6144 CL22_WR_OVER_CL45(cb, phy, 6145 MDIO_REG_BANK_CL73_IEEEB0, 6146 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6147 0); 6148 /* Restart CL37 autoneg */ 6149 elink_restart_autoneg(phy, params, 0); 6150 ELINK_DEBUG_P0(cb, "Disabling CL73, and restarting CL37 autoneg\n"); 6151 } 6152 6153 static void elink_xgxs_an_resolve(struct elink_phy *phy, 6154 struct elink_params *params, 6155 struct elink_vars *vars, 6156 u32 gp_status) 6157 { 6158 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) 6159 vars->link_status |= 6160 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6161 6162 if (elink_direct_parallel_detect_used(phy, params)) 6163 vars->link_status |= 6164 LINK_STATUS_PARALLEL_DETECTION_USED; 6165 } 6166 #endif /* EXCLUDE_XGXS */ 6167 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, 6168 struct elink_params *params, 6169 struct elink_vars *vars, 6170 u16 is_link_up, 6171 u16 speed_mask, 6172 u16 is_duplex) 6173 { 6174 #ifdef ELINK_DEBUG 6175 struct elink_dev *cb = params->cb; 6176 #endif 6177 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6178 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 6179 if (is_link_up) { 6180 ELINK_DEBUG_P0(cb, "phy link up\n"); 6181 6182 vars->phy_link_up = 1; 6183 vars->link_status |= LINK_STATUS_LINK_UP; 6184 6185 switch (speed_mask) { 6186 case ELINK_GP_STATUS_10M: 6187 vars->line_speed = ELINK_SPEED_10; 6188 if (is_duplex == DUPLEX_FULL) 6189 vars->link_status |= ELINK_LINK_10TFD; 6190 else 6191 vars->link_status |= ELINK_LINK_10THD; 6192 break; 6193 6194 case ELINK_GP_STATUS_100M: 6195 vars->line_speed = ELINK_SPEED_100; 6196 if (is_duplex == DUPLEX_FULL) 6197 vars->link_status |= ELINK_LINK_100TXFD; 6198 else 6199 vars->link_status |= ELINK_LINK_100TXHD; 6200 break; 6201 6202 case ELINK_GP_STATUS_1G: 6203 case ELINK_GP_STATUS_1G_KX: 6204 vars->line_speed = ELINK_SPEED_1000; 6205 if (is_duplex == DUPLEX_FULL) 6206 vars->link_status |= ELINK_LINK_1000TFD; 6207 else 6208 vars->link_status |= ELINK_LINK_1000THD; 6209 break; 6210 6211 case ELINK_GP_STATUS_2_5G: 6212 vars->line_speed = ELINK_SPEED_2500; 6213 if (is_duplex == DUPLEX_FULL) 6214 vars->link_status |= ELINK_LINK_2500TFD; 6215 else 6216 vars->link_status |= ELINK_LINK_2500THD; 6217 break; 6218 6219 case ELINK_GP_STATUS_5G: 6220 case ELINK_GP_STATUS_6G: 6221 ELINK_DEBUG_P1(cb, 6222 "link speed unsupported gp_status 0x%x\n", 6223 speed_mask); 6224 return ELINK_STATUS_ERROR; 6225 6226 case ELINK_GP_STATUS_10G_KX4: 6227 case ELINK_GP_STATUS_10G_HIG: 6228 case ELINK_GP_STATUS_10G_CX4: 6229 case ELINK_GP_STATUS_10G_KR: 6230 case ELINK_GP_STATUS_10G_SFI: 6231 case ELINK_GP_STATUS_10G_XFI: 6232 vars->line_speed = ELINK_SPEED_10000; 6233 vars->link_status |= ELINK_LINK_10GTFD; 6234 break; 6235 case ELINK_GP_STATUS_20G_DXGXS: 6236 case ELINK_GP_STATUS_20G_KR2: 6237 vars->line_speed = ELINK_SPEED_20000; 6238 vars->link_status |= ELINK_LINK_20GTFD; 6239 break; 6240 default: 6241 ELINK_DEBUG_P1(cb, 6242 "link speed unsupported gp_status 0x%x\n", 6243 speed_mask); 6244 return ELINK_STATUS_ERROR; 6245 } 6246 } else { /* link_down */ 6247 ELINK_DEBUG_P0(cb, "phy link down\n"); 6248 6249 vars->phy_link_up = 0; 6250 6251 vars->duplex = DUPLEX_FULL; 6252 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6253 vars->mac_type = ELINK_MAC_TYPE_NONE; 6254 } 6255 ELINK_DEBUG_P2(cb, " phy_link_up %x line_speed %d\n", 6256 vars->phy_link_up, vars->line_speed); 6257 return ELINK_STATUS_OK; 6258 } 6259 6260 #ifndef EXCLUDE_XGXS 6261 static elink_status_t 6262 elink_link_settings_status(struct elink_phy *phy, struct elink_params *params, 6263 struct elink_vars *vars) 6264 { 6265 struct elink_dev *cb = params->cb; 6266 6267 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 6268 elink_status_t rc = ELINK_STATUS_OK; 6269 6270 /* Read gp_status */ 6271 CL22_RD_OVER_CL45(cb, phy, 6272 MDIO_REG_BANK_GP_STATUS, 6273 MDIO_GP_STATUS_TOP_AN_STATUS1, 6274 &gp_status); 6275 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 6276 duplex = DUPLEX_FULL; 6277 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 6278 link_up = 1; 6279 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; 6280 ELINK_DEBUG_P3(cb, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 6281 gp_status, link_up, speed_mask); 6282 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 6283 duplex); 6284 if (rc == ELINK_STATUS_ERROR) 6285 return rc; 6286 6287 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 6288 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 6289 vars->duplex = duplex; 6290 elink_flow_ctrl_resolve(phy, params, vars, gp_status); 6291 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6292 elink_xgxs_an_resolve(phy, params, vars, 6293 gp_status); 6294 } 6295 } else { /* Link_down */ 6296 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 6297 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6298 /* Check signal is detected */ 6299 elink_check_fallback_to_cl37(phy, params); 6300 } 6301 } 6302 6303 /* Read LP advertised speeds*/ 6304 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6305 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 6306 u16 val; 6307 6308 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_CL73_IEEEB1, 6309 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 6310 6311 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6312 vars->link_status |= 6313 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6314 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6315 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6316 vars->link_status |= 6317 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6318 6319 CL22_RD_OVER_CL45(cb, phy, MDIO_REG_BANK_OVER_1G, 6320 MDIO_OVER_1G_LP_UP1, &val); 6321 6322 if (val & MDIO_OVER_1G_UP1_2_5G) 6323 vars->link_status |= 6324 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6325 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6326 vars->link_status |= 6327 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6328 } 6329 6330 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6331 vars->duplex, vars->flow_ctrl, vars->link_status); 6332 return rc; 6333 } 6334 #endif // EXCLUDE_XGXS 6335 6336 #ifndef EXCLUDE_WARPCORE 6337 static elink_status_t 6338 elink_warpcore_read_status(struct elink_phy *phy, struct elink_params *params, 6339 struct elink_vars *vars) 6340 { 6341 struct elink_dev *cb = params->cb; 6342 u8 lane; 6343 u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 6344 elink_status_t rc = ELINK_STATUS_OK; 6345 lane = elink_get_warpcore_lane(phy, params); 6346 /* Read gp_status */ 6347 if ((params->loopback_mode) && 6348 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { 6349 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6350 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6351 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6352 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6353 link_up &= 0x1; 6354 } else if ((phy->req_line_speed > ELINK_SPEED_10000) && 6355 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { 6356 u16 temp_link_up; 6357 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6358 1, &temp_link_up); 6359 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6360 1, &link_up); 6361 ELINK_DEBUG_P2(cb, "PCS RX link status = 0x%x-->0x%x\n", 6362 temp_link_up, link_up); 6363 link_up &= (1<<2); 6364 if (link_up) 6365 elink_ext_phy_resolve_fc(phy, params, vars); 6366 } else { 6367 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6368 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6369 &gp_status1); 6370 ELINK_DEBUG_P1(cb, "0x81d1 = 0x%x\n", gp_status1); 6371 /* Check for either KR, 1G, or AN up. */ 6372 link_up = ((gp_status1 >> 8) | 6373 (gp_status1 >> 12) | 6374 (gp_status1)) & 6375 (1 << lane); 6376 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 6377 u16 an_link; 6378 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6379 MDIO_AN_REG_STATUS, &an_link); 6380 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6381 MDIO_AN_REG_STATUS, &an_link); 6382 link_up |= (an_link & (1<<2)); 6383 } 6384 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { 6385 u16 pd, gp_status4; 6386 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 6387 /* Check Autoneg complete */ 6388 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6389 MDIO_WC_REG_GP2_STATUS_GP_2_4, 6390 &gp_status4); 6391 if (gp_status4 & ((1<<12)<<lane)) 6392 vars->link_status |= 6393 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6394 6395 /* Check parallel detect used */ 6396 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6397 MDIO_WC_REG_PAR_DET_10G_STATUS, 6398 &pd); 6399 if (pd & (1<<15)) 6400 vars->link_status |= 6401 LINK_STATUS_PARALLEL_DETECTION_USED; 6402 } 6403 elink_ext_phy_resolve_fc(phy, params, vars); 6404 vars->duplex = duplex; 6405 } 6406 } 6407 6408 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 6409 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6410 u16 val; 6411 6412 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 6413 MDIO_AN_REG_LP_AUTO_NEG2, &val); 6414 6415 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6416 vars->link_status |= 6417 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6418 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6419 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6420 vars->link_status |= 6421 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6422 6423 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6424 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 6425 6426 if (val & MDIO_OVER_1G_UP1_2_5G) 6427 vars->link_status |= 6428 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6429 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6430 vars->link_status |= 6431 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6432 6433 } 6434 6435 6436 if (lane < 2) { 6437 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6438 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 6439 } else { 6440 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 6441 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 6442 } 6443 ELINK_DEBUG_P2(cb, "lane %d gp_speed 0x%x\n", lane, gp_speed); 6444 6445 if ((lane & 1) == 0) 6446 gp_speed <<= 8; 6447 gp_speed &= 0x3f00; 6448 link_up = !!link_up; 6449 6450 /* Reset the TX FIFO to fix SGMII issue */ 6451 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 6452 duplex); 6453 6454 /* In case of KR link down, start up the recovering procedure */ 6455 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && 6456 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) 6457 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 6458 6459 ELINK_DEBUG_P3(cb, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6460 vars->duplex, vars->flow_ctrl, vars->link_status); 6461 return rc; 6462 } 6463 #endif /* #ifndef EXCLUDE_WARPCORE */ 6464 #ifndef EXCLUDE_XGXS 6465 static void elink_set_gmii_tx_driver(struct elink_params *params) 6466 { 6467 struct elink_dev *cb = params->cb; 6468 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 6469 u16 lp_up2; 6470 u16 tx_driver; 6471 u16 bank; 6472 6473 /* Read precomp */ 6474 CL22_RD_OVER_CL45(cb, phy, 6475 MDIO_REG_BANK_OVER_1G, 6476 MDIO_OVER_1G_LP_UP2, &lp_up2); 6477 6478 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 6479 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 6480 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 6481 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 6482 6483 if (lp_up2 == 0) 6484 return; 6485 6486 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 6487 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 6488 CL22_RD_OVER_CL45(cb, phy, 6489 bank, 6490 MDIO_TX0_TX_DRIVER, &tx_driver); 6491 6492 /* Replace tx_driver bits [15:12] */ 6493 if (lp_up2 != 6494 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 6495 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 6496 tx_driver |= lp_up2; 6497 CL22_WR_OVER_CL45(cb, phy, 6498 bank, 6499 MDIO_TX0_TX_DRIVER, tx_driver); 6500 } 6501 } 6502 } 6503 6504 static elink_status_t elink_emac_program(struct elink_params *params, 6505 struct elink_vars *vars) 6506 { 6507 struct elink_dev *cb = params->cb; 6508 u8 port = params->port; 6509 u16 mode = 0; 6510 6511 ELINK_DEBUG_P0(cb, "setting link speed & duplex\n"); 6512 elink_bits_dis(cb, GRCBASE_EMAC0 + port*0x400 + 6513 EMAC_REG_EMAC_MODE, 6514 (EMAC_MODE_25G_MODE | 6515 EMAC_MODE_PORT_MII_10M | 6516 EMAC_MODE_HALF_DUPLEX)); 6517 switch (vars->line_speed) { 6518 case ELINK_SPEED_10: 6519 mode |= EMAC_MODE_PORT_MII_10M; 6520 break; 6521 6522 case ELINK_SPEED_100: 6523 mode |= EMAC_MODE_PORT_MII; 6524 break; 6525 6526 case ELINK_SPEED_1000: 6527 mode |= EMAC_MODE_PORT_GMII; 6528 break; 6529 6530 case ELINK_SPEED_2500: 6531 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 6532 break; 6533 6534 default: 6535 /* 10G not valid for EMAC */ 6536 ELINK_DEBUG_P1(cb, "Invalid line_speed 0x%x\n", 6537 vars->line_speed); 6538 return ELINK_STATUS_ERROR; 6539 } 6540 6541 if (vars->duplex == DUPLEX_HALF) 6542 mode |= EMAC_MODE_HALF_DUPLEX; 6543 elink_bits_en(cb, 6544 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 6545 mode); 6546 6547 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 6548 return ELINK_STATUS_OK; 6549 } 6550 6551 static void elink_set_preemphasis(struct elink_phy *phy, 6552 struct elink_params *params) 6553 { 6554 6555 u16 bank, i = 0; 6556 struct elink_dev *cb = params->cb; 6557 6558 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 6559 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 6560 CL22_WR_OVER_CL45(cb, phy, 6561 bank, 6562 MDIO_RX0_RX_EQ_BOOST, 6563 phy->rx_preemphasis[i]); 6564 } 6565 6566 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 6567 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 6568 CL22_WR_OVER_CL45(cb, phy, 6569 bank, 6570 MDIO_TX0_TX_DRIVER, 6571 phy->tx_preemphasis[i]); 6572 } 6573 } 6574 6575 static elink_status_t 6576 elink_xgxs_config_init(struct elink_phy *phy, struct elink_params *params, 6577 struct elink_vars *vars) 6578 { 6579 #ifdef ELINK_DEBUG 6580 struct elink_dev *cb = params->cb; 6581 #endif 6582 u8 enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || 6583 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 6584 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 6585 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6586 (params->feature_config_flags & 6587 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 6588 elink_set_preemphasis(phy, params); 6589 6590 /* Forced speed requested? */ 6591 if (vars->line_speed != ELINK_SPEED_AUTO_NEG || 6592 (ELINK_SINGLE_MEDIA_DIRECT(params) && 6593 params->loopback_mode == ELINK_LOOPBACK_EXT)) { 6594 ELINK_DEBUG_P0(cb, "not SGMII, no AN\n"); 6595 6596 /* Disable autoneg */ 6597 elink_set_autoneg(phy, params, vars, 0); 6598 6599 /* Program speed and duplex */ 6600 elink_program_serdes(phy, params, vars); 6601 6602 } else { /* AN_mode */ 6603 ELINK_DEBUG_P0(cb, "not SGMII, AN\n"); 6604 6605 /* AN enabled */ 6606 elink_set_brcm_cl37_advertisement(phy, params); 6607 6608 /* Program duplex & pause advertisement (for aneg) */ 6609 elink_set_ieee_aneg_advertisement(phy, params, 6610 vars->ieee_fc); 6611 6612 /* Enable autoneg */ 6613 elink_set_autoneg(phy, params, vars, enable_cl73); 6614 6615 /* Enable and restart AN */ 6616 elink_restart_autoneg(phy, params, enable_cl73); 6617 } 6618 6619 } else { /* SGMII mode */ 6620 ELINK_DEBUG_P0(cb, "SGMII\n"); 6621 6622 elink_initialize_sgmii_process(phy, params, vars); 6623 } 6624 return (ELINK_STATUS_OK); 6625 } 6626 6627 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, 6628 struct elink_params *params, 6629 struct elink_vars *vars) 6630 { 6631 elink_status_t rc; 6632 vars->phy_flags |= PHY_XGXS_FLAG; 6633 if ((phy->req_line_speed && 6634 ((phy->req_line_speed == ELINK_SPEED_100) || 6635 (phy->req_line_speed == ELINK_SPEED_10))) || 6636 (!phy->req_line_speed && 6637 (phy->speed_cap_mask >= 6638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 6639 (phy->speed_cap_mask < 6640 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 6641 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 6642 vars->phy_flags |= PHY_SGMII_FLAG; 6643 else 6644 vars->phy_flags &= ~PHY_SGMII_FLAG; 6645 6646 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6647 elink_set_aer_mmd(params, phy); 6648 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6649 elink_set_master_ln(params, phy); 6650 6651 rc = elink_reset_unicore(params, phy, 0); 6652 /* Reset the SerDes and wait for reset bit return low */ 6653 if (rc != ELINK_STATUS_OK) 6654 return rc; 6655 6656 elink_set_aer_mmd(params, phy); 6657 /* Setting the masterLn_def again after the reset */ 6658 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6659 elink_set_master_ln(params, phy); 6660 elink_set_swap_lanes(params, phy); 6661 } 6662 6663 return rc; 6664 } 6665 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 6666 #endif /* EXCLUDE_XGXS */ 6667 6668 #ifndef EXCLUDE_NON_COMMON_INIT 6669 #ifndef ELINK_EMUL_ONLY 6670 static u16 elink_wait_reset_complete(struct elink_dev *cb, 6671 struct elink_phy *phy, 6672 struct elink_params *params) 6673 { 6674 u16 cnt, ctrl; 6675 /* Wait for soft reset to get cleared up to 1 sec */ 6676 for (cnt = 0; cnt < 1000; cnt++) { 6677 #ifndef EXCLUDE_BCM54618SE 6678 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6679 elink_cl22_read(cb, phy, 6680 MDIO_PMA_REG_CTRL, &ctrl); 6681 else 6682 #endif 6683 elink_cl45_read(cb, phy, 6684 MDIO_PMA_DEVAD, 6685 MDIO_PMA_REG_CTRL, &ctrl); 6686 if (!(ctrl & (1<<15))) 6687 break; 6688 MSLEEP(cb, 1); 6689 } 6690 6691 if (cnt == 1000) 6692 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 6693 // " Port %d\n", 6694 6695 ELINK_DEBUG_P2(cb, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6696 return cnt; 6697 } 6698 #endif /* ELINK_EMUL_ONLY */ 6699 6700 static void elink_link_int_enable(struct elink_params *params) 6701 { 6702 u8 port = params->port; 6703 u32 mask; 6704 struct elink_dev *cb = params->cb; 6705 6706 /* Setting the status to report on link up for either XGXS or SerDes */ 6707 if (CHIP_IS_E3(params->chip_id)) { 6708 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; 6709 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) 6710 mask |= ELINK_NIG_MASK_MI_INT; 6711 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6712 mask = (ELINK_NIG_MASK_XGXS0_LINK10G | 6713 ELINK_NIG_MASK_XGXS0_LINK_STATUS); 6714 ELINK_DEBUG_P0(cb, "enabled XGXS interrupt\n"); 6715 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6716 params->phy[ELINK_INT_PHY].type != 6717 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6718 mask |= ELINK_NIG_MASK_MI_INT; 6719 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6720 } 6721 6722 } else { /* SerDes */ 6723 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; 6724 ELINK_DEBUG_P0(cb, "enabled SerDes interrupt\n"); 6725 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6726 params->phy[ELINK_INT_PHY].type != 6727 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6728 mask |= ELINK_NIG_MASK_MI_INT; 6729 ELINK_DEBUG_P0(cb, "enabled external phy int\n"); 6730 } 6731 } 6732 elink_bits_en(cb, 6733 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6734 mask); 6735 6736 ELINK_DEBUG_P3(cb, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6737 (params->switch_cfg == ELINK_SWITCH_CFG_10G), 6738 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6739 ELINK_DEBUG_P3(cb, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6740 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6741 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6742 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6743 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 6744 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6745 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6746 } 6747 6748 static void elink_rearm_latch_signal(struct elink_dev *cb, u8 port, 6749 u8 exp_mi_int) 6750 { 6751 u32 latch_status = 0; 6752 6753 /* Disable the MI INT ( external phy int ) by writing 1 to the 6754 * status register. Link down indication is high-active-signal, 6755 * so in this case we need to write the status to clear the XOR 6756 */ 6757 /* Read Latched signals */ 6758 latch_status = REG_RD(cb, 6759 NIG_REG_LATCH_STATUS_0 + port*8); 6760 ELINK_DEBUG_P1(cb, "latch_status = 0x%x\n", latch_status); 6761 /* Handle only those with latched-signal=up.*/ 6762 if (exp_mi_int) 6763 elink_bits_en(cb, 6764 NIG_REG_STATUS_INTERRUPT_PORT0 6765 + port*4, 6766 ELINK_NIG_STATUS_EMAC0_MI_INT); 6767 else 6768 elink_bits_dis(cb, 6769 NIG_REG_STATUS_INTERRUPT_PORT0 6770 + port*4, 6771 ELINK_NIG_STATUS_EMAC0_MI_INT); 6772 6773 if (latch_status & 1) { 6774 6775 /* For all latched-signal=up : Re-Arm Latch signals */ 6776 REG_WR(cb, NIG_REG_LATCH_STATUS_0 + port*8, 6777 (latch_status & 0xfffe) | (latch_status & 1)); 6778 } 6779 /* For all latched-signal=up,Write original_signal to status */ 6780 } 6781 6782 static void elink_link_int_ack(struct elink_params *params, 6783 struct elink_vars *vars, u8 is_10g_plus) 6784 { 6785 struct elink_dev *cb = params->cb; 6786 u8 port = params->port; 6787 u32 mask; 6788 /* First reset all status we assume only one line will be 6789 * change at a time 6790 */ 6791 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6792 (ELINK_NIG_STATUS_XGXS0_LINK10G | 6793 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 6794 ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); 6795 if (vars->phy_link_up) { 6796 if (ELINK_USES_WARPCORE(params->chip_id)) 6797 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; 6798 else { 6799 if (is_10g_plus) 6800 mask = ELINK_NIG_STATUS_XGXS0_LINK10G; 6801 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6802 /* Disable the link interrupt by writing 1 to 6803 * the relevant lane in the status register 6804 */ 6805 u32 ser_lane = 6806 ((params->lane_config & 6807 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6808 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6809 mask = ((1 << ser_lane) << 6810 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6811 } else 6812 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; 6813 } 6814 ELINK_DEBUG_P1(cb, "Ack link up interrupt with mask 0x%x\n", 6815 mask); 6816 elink_bits_en(cb, 6817 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6818 mask); 6819 } 6820 } 6821 6822 #if !defined(ELINK_EMUL_ONLY) && (!defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6)) 6823 static elink_status_t 6824 elink_format_ver(u32 num, u8 *str, u16 *len) 6825 { 6826 #ifdef ELINK_ENHANCEMENTS 6827 u8 *str_ptr = str; 6828 u32 mask = 0xf0000000; 6829 u8 shift = 8*4; 6830 u8 digit; 6831 u8 remove_leading_zeros = 1; 6832 if (*len < 10) { 6833 /* Need more than 10chars for this format */ 6834 *str_ptr = '\0'; 6835 (*len)--; 6836 return ELINK_STATUS_ERROR; 6837 } 6838 while (shift > 0) { 6839 6840 shift -= 4; 6841 digit = ((num & mask) >> shift); 6842 if (digit == 0 && remove_leading_zeros) { 6843 mask = mask >> 4; 6844 continue; 6845 } else if (digit < 0xa) 6846 *str_ptr = digit + '0'; 6847 else 6848 *str_ptr = digit - 0xa + 'a'; 6849 remove_leading_zeros = 0; 6850 str_ptr++; 6851 (*len)--; 6852 mask = mask >> 4; 6853 if (shift == 4*4) { 6854 *str_ptr = '.'; 6855 str_ptr++; 6856 (*len)--; 6857 remove_leading_zeros = 1; 6858 } 6859 } 6860 #endif /* ELINK_ENHANCEMENTS */ 6861 return ELINK_STATUS_OK; 6862 } 6863 #endif /* ELINK_EMUL_ONLY */ 6864 6865 6866 #ifndef EXCLUDE_BCM8705 6867 static elink_status_t 6868 elink_null_format_ver(u32 spirom_ver, u8 *str, u16 *len) 6869 { 6870 #ifdef ELINK_ENHANCEMENTS 6871 str[0] = '\0'; 6872 (*len)--; 6873 #endif // ELINK_ENHANCEMENTS 6874 return ELINK_STATUS_OK; 6875 } 6876 #endif // EXCLUDE_BCM8705 6877 6878 #ifdef ELINK_ENHANCEMENTS 6879 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version, 6880 u16 len) 6881 { 6882 struct elink_dev *cb; 6883 u32 spirom_ver = 0; 6884 elink_status_t status = ELINK_STATUS_OK; 6885 u8 *ver_p = version; 6886 u16 remain_len = len; 6887 if (version == NULL || params == NULL) 6888 return ELINK_STATUS_ERROR; 6889 cb = params->cb; 6890 6891 /* Extract first external phy*/ 6892 version[0] = '\0'; 6893 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY1].ver_addr); 6894 6895 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { 6896 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, 6897 ver_p, 6898 &remain_len); 6899 ver_p += (len - remain_len); 6900 } 6901 if ((params->num_phys == ELINK_MAX_PHYS) && 6902 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { 6903 spirom_ver = REG_RD(cb, params->phy[ELINK_EXT_PHY2].ver_addr); 6904 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { 6905 *ver_p = '/'; 6906 ver_p++; 6907 remain_len--; 6908 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( 6909 spirom_ver, 6910 ver_p, 6911 &remain_len); 6912 ver_p = version + (len - remain_len); 6913 } 6914 } 6915 *ver_p = '\0'; 6916 return status; 6917 } 6918 #endif // ELINK_ENHANCEMENTS 6919 6920 #ifndef EXCLUDE_XGXS 6921 static void elink_set_xgxs_loopback(struct elink_phy *phy, 6922 struct elink_params *params) 6923 { 6924 #ifdef ELINK_INCLUDE_LOOPBACK 6925 u8 port = params->port; 6926 struct elink_dev *cb = params->cb; 6927 6928 if (phy->req_line_speed != ELINK_SPEED_1000) { 6929 u32 md_devad = 0; 6930 6931 ELINK_DEBUG_P0(cb, "XGXS 10G loopback enable\n"); 6932 6933 if (!CHIP_IS_E3(params->chip_id)) { 6934 /* Change the uni_phy_addr in the nig */ 6935 md_devad = REG_RD(cb, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 6936 port*0x18)); 6937 6938 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6939 0x5); 6940 } 6941 6942 elink_cl45_write(cb, phy, 6943 5, 6944 (MDIO_REG_BANK_AER_BLOCK + 6945 (MDIO_AER_BLOCK_AER_REG & 0xf)), 6946 0x2800); 6947 6948 elink_cl45_write(cb, phy, 6949 5, 6950 (MDIO_REG_BANK_CL73_IEEEB0 + 6951 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 6952 0x6041); 6953 MSLEEP(cb, 200); 6954 /* Set aer mmd back */ 6955 elink_set_aer_mmd(params, phy); 6956 6957 if (!CHIP_IS_E3(params->chip_id)) { 6958 /* And md_devad */ 6959 REG_WR(cb, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 6960 md_devad); 6961 } 6962 } else { 6963 u16 mii_ctrl; 6964 ELINK_DEBUG_P0(cb, "XGXS 1G loopback enable\n"); 6965 elink_cl45_read(cb, phy, 5, 6966 (MDIO_REG_BANK_COMBO_IEEE0 + 6967 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6968 &mii_ctrl); 6969 elink_cl45_write(cb, phy, 5, 6970 (MDIO_REG_BANK_COMBO_IEEE0 + 6971 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 6972 mii_ctrl | 6973 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 6974 } 6975 #endif // ELINK_INCLUDE_LOOPBACK 6976 } 6977 #endif /* EXCLUDE_XGXS */ 6978 6979 elink_status_t elink_set_led(struct elink_params *params, 6980 struct elink_vars *vars, u8 mode, u32 speed) 6981 { 6982 u8 port = params->port; 6983 u16 hw_led_mode = params->hw_led_mode; 6984 elink_status_t rc = ELINK_STATUS_OK; 6985 u8 phy_idx; 6986 u32 tmp; 6987 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 6988 struct elink_dev *cb = params->cb; 6989 ELINK_DEBUG_P2(cb, "elink_set_led: port %x, mode %d\n", port, mode); 6990 ELINK_DEBUG_P2(cb, "speed 0x%x, hw_led_mode 0x%x\n", 6991 speed, hw_led_mode); 6992 /* In case */ 6993 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 6994 if (params->phy[phy_idx].set_link_led) { 6995 params->phy[phy_idx].set_link_led( 6996 ¶ms->phy[phy_idx], params, mode); 6997 } 6998 } 6999 #ifdef ELINK_INCLUDE_EMUL 7000 if (params->feature_config_flags & 7001 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) 7002 return rc; 7003 #endif 7004 7005 switch (mode) { 7006 case ELINK_LED_MODE_FRONT_PANEL_OFF: 7007 case ELINK_LED_MODE_OFF: 7008 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 0); 7009 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7010 SHARED_HW_CFG_LED_MAC1); 7011 7012 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7013 if (params->phy[ELINK_EXT_PHY1].type == 7014 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 7015 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 7016 EMAC_LED_100MB_OVERRIDE | 7017 EMAC_LED_10MB_OVERRIDE); 7018 else 7019 tmp |= EMAC_LED_OVERRIDE; 7020 7021 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp); 7022 break; 7023 7024 case ELINK_LED_MODE_OPER: 7025 /* For all other phys, OPER mode is same as ON, so in case 7026 * link is down, do nothing 7027 */ 7028 if (!vars->link_up) 7029 break; 7030 /* FALLTHROUGH */ 7031 case ELINK_LED_MODE_ON: 7032 if (((params->phy[ELINK_EXT_PHY1].type == 7033 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 7034 (params->phy[ELINK_EXT_PHY1].type == 7035 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 7036 CHIP_IS_E2(params->chip_id) && params->num_phys == 2) { 7037 /* This is a work-around for E2+8727 Configurations */ 7038 if (mode == ELINK_LED_MODE_ON || 7039 speed == ELINK_SPEED_10000){ 7040 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7041 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7042 7043 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7044 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7045 (tmp | EMAC_LED_OVERRIDE)); 7046 /* Return here without enabling traffic 7047 * LED blink and setting rate in ON mode. 7048 * In oper mode, enabling LED blink 7049 * and setting rate is needed. 7050 */ 7051 if (mode == ELINK_LED_MODE_ON) 7052 return rc; 7053 } 7054 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 7055 /* This is a work-around for HW issue found when link 7056 * is up in CL73 7057 */ 7058 if ((!CHIP_IS_E3(params->chip_id)) || 7059 (CHIP_IS_E3(params->chip_id) && 7060 mode == ELINK_LED_MODE_ON)) 7061 REG_WR(cb, NIG_REG_LED_10G_P0 + port*4, 1); 7062 7063 if (CHIP_IS_E1X(params->chip_id) || 7064 CHIP_IS_E2(params->chip_id) || 7065 (mode == ELINK_LED_MODE_ON)) 7066 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7067 else 7068 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7069 hw_led_mode); 7070 } else if ((params->phy[ELINK_EXT_PHY1].type == 7071 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 7072 (mode == ELINK_LED_MODE_ON)) { 7073 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 0); 7074 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7075 EMAC_WR(cb, EMAC_REG_EMAC_LED, tmp | 7076 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 7077 /* Break here; otherwise, it'll disable the 7078 * intended override. 7079 */ 7080 break; 7081 } else { 7082 u32 nig_led_mode = ((params->hw_led_mode << 7083 SHARED_HW_CFG_LED_MODE_SHIFT) == 7084 SHARED_HW_CFG_LED_EXTPHY2) ? 7085 (SHARED_HW_CFG_LED_PHY1 >> 7086 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 7087 REG_WR(cb, NIG_REG_LED_MODE_P0 + port*4, 7088 nig_led_mode); 7089 } 7090 7091 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 7092 /* Set blinking rate to ~15.9Hz */ 7093 if (CHIP_IS_E3(params->chip_id)) 7094 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7095 LED_BLINK_RATE_VAL_E3); 7096 else 7097 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7098 LED_BLINK_RATE_VAL_E1X_E2); 7099 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 7100 port*4, 1); 7101 tmp = EMAC_RD(cb, EMAC_REG_EMAC_LED); 7102 EMAC_WR(cb, EMAC_REG_EMAC_LED, 7103 (tmp & (~EMAC_LED_OVERRIDE))); 7104 7105 #ifndef ELINK_AUX_POWER 7106 if (CHIP_IS_E1(params->chip_id) && 7107 ((speed == ELINK_SPEED_2500) || 7108 (speed == ELINK_SPEED_1000) || 7109 (speed == ELINK_SPEED_100) || 7110 (speed == ELINK_SPEED_10))) { 7111 /* For speeds less than 10G LED scheme is different */ 7112 REG_WR(cb, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 7113 + port*4, 1); 7114 REG_WR(cb, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 7115 port*4, 0); 7116 REG_WR(cb, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 7117 port*4, 1); 7118 } 7119 #endif // ELINK_AUX_POWER 7120 break; 7121 7122 default: 7123 rc = ELINK_STATUS_ERROR; 7124 ELINK_DEBUG_P1(cb, "elink_set_led: Invalid led mode %d\n", 7125 mode); 7126 break; 7127 } 7128 return rc; 7129 7130 } 7131 7132 #endif // EXCLUDE_NON_COMMON_INIT 7133 #ifdef ELINK_ENHANCEMENTS 7134 /* This function comes to reflect the actual link state read DIRECTLY from the 7135 * HW 7136 */ 7137 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 7138 u8 is_serdes) 7139 { 7140 struct elink_dev *cb = params->cb; 7141 u16 gp_status = 0, phy_index = 0; 7142 u8 ext_phy_link_up = 0, serdes_phy_type; 7143 struct elink_vars temp_vars; 7144 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 7145 #ifdef ELINK_INCLUDE_FPGA 7146 if (CHIP_REV_IS_FPGA(params->chip_id)) 7147 return ELINK_STATUS_OK; 7148 #endif /* ELINK_INCLUDE_FPGA */ 7149 #ifdef ELINK_INCLUDE_EMUL 7150 if (CHIP_REV_IS_EMUL(params->chip_id)) 7151 return ELINK_STATUS_OK; 7152 #endif /* ELINK_INCLUDE_EMUL */ 7153 7154 if (CHIP_IS_E3(params->chip_id)) { 7155 u16 link_up; 7156 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] 7157 > ELINK_SPEED_10000) { 7158 /* Check 20G link */ 7159 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7160 1, &link_up); 7161 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7162 1, &link_up); 7163 link_up &= (1<<2); 7164 } else { 7165 /* Check 10G link and below*/ 7166 u8 lane = elink_get_warpcore_lane(int_phy, params); 7167 elink_cl45_read(cb, int_phy, MDIO_WC_DEVAD, 7168 MDIO_WC_REG_GP2_STATUS_GP_2_1, 7169 &gp_status); 7170 gp_status = ((gp_status >> 8) & 0xf) | 7171 ((gp_status >> 12) & 0xf); 7172 link_up = gp_status & (1 << lane); 7173 } 7174 if (!link_up) 7175 return ELINK_STATUS_NO_LINK; 7176 } else { 7177 CL22_RD_OVER_CL45(cb, int_phy, 7178 MDIO_REG_BANK_GP_STATUS, 7179 MDIO_GP_STATUS_TOP_AN_STATUS1, 7180 &gp_status); 7181 /* Link is up only if both local phy and external phy are up */ 7182 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 7183 return ELINK_STATUS_NO_LINK; 7184 } 7185 /* In XGXS loopback mode, do not check external PHY */ 7186 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) 7187 return ELINK_STATUS_OK; 7188 7189 switch (params->num_phys) { 7190 case 1: 7191 /* No external PHY */ 7192 return ELINK_STATUS_OK; 7193 case 2: 7194 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( 7195 ¶ms->phy[ELINK_EXT_PHY1], 7196 params, &temp_vars); 7197 break; 7198 case 3: /* Dual Media */ 7199 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7200 phy_index++) { 7201 serdes_phy_type = ((params->phy[phy_index].media_type == 7202 ELINK_ETH_PHY_SFPP_10G_FIBER) || 7203 (params->phy[phy_index].media_type == 7204 ELINK_ETH_PHY_SFP_1G_FIBER) || 7205 (params->phy[phy_index].media_type == 7206 ELINK_ETH_PHY_XFP_FIBER) || 7207 (params->phy[phy_index].media_type == 7208 ELINK_ETH_PHY_DA_TWINAX)); 7209 7210 if (is_serdes != serdes_phy_type) 7211 continue; 7212 if (params->phy[phy_index].read_status) { 7213 ext_phy_link_up |= 7214 params->phy[phy_index].read_status( 7215 ¶ms->phy[phy_index], 7216 params, &temp_vars); 7217 } 7218 } 7219 break; 7220 } 7221 if (ext_phy_link_up) 7222 return ELINK_STATUS_OK; 7223 return ELINK_STATUS_NO_LINK; 7224 } 7225 #endif // ELINK_ENHANCEMENT 7226 7227 #ifndef EXCLUDE_NON_COMMON_INIT 7228 static elink_status_t elink_link_initialize(struct elink_params *params, 7229 struct elink_vars *vars) 7230 { 7231 u8 phy_index, non_ext_phy; 7232 struct elink_dev *cb = params->cb; 7233 /* In case of external phy existence, the line speed would be the 7234 * line speed linked up by the external phy. In case it is direct 7235 * only, then the line_speed during initialization will be 7236 * equal to the req_line_speed 7237 */ 7238 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7239 7240 /* Initialize the internal phy in case this is a direct board 7241 * (no external phys), or this board has external phy which requires 7242 * to first. 7243 */ 7244 #ifndef EXCLUDE_XGXS 7245 if (!ELINK_USES_WARPCORE(params->chip_id)) 7246 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); 7247 #endif // EXCLUDE_XGXS 7248 /* init ext phy and enable link state int */ 7249 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || 7250 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 7251 7252 if (non_ext_phy || 7253 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || 7254 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { 7255 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 7256 #ifndef EXCLUDE_XGXS 7257 if (vars->line_speed == ELINK_SPEED_AUTO_NEG && 7258 (CHIP_IS_E1X(params->chip_id) || 7259 CHIP_IS_E2(params->chip_id))) 7260 elink_set_parallel_detection(phy, params); 7261 #endif // EXCLUDE_XGXS 7262 if (params->phy[ELINK_INT_PHY].config_init) 7263 params->phy[ELINK_INT_PHY].config_init(phy, params, vars); 7264 } 7265 7266 /* Re-read this value in case it was changed inside config_init due to 7267 * limitations of optic module 7268 */ 7269 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7270 7271 /* Init external phy*/ 7272 if (non_ext_phy) { 7273 if (params->phy[ELINK_INT_PHY].supported & 7274 ELINK_SUPPORTED_FIBRE) 7275 vars->link_status |= LINK_STATUS_SERDES_LINK; 7276 } else { 7277 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7278 phy_index++) { 7279 /* No need to initialize second phy in case of first 7280 * phy only selection. In case of second phy, we do 7281 * need to initialize the first phy, since they are 7282 * connected. 7283 */ 7284 if (params->phy[phy_index].supported & 7285 ELINK_SUPPORTED_FIBRE) 7286 vars->link_status |= LINK_STATUS_SERDES_LINK; 7287 7288 if (phy_index == ELINK_EXT_PHY2 && 7289 (elink_phy_selection(params) == 7290 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 7291 ELINK_DEBUG_P0(cb, 7292 "Not initializing second phy\n"); 7293 continue; 7294 } 7295 params->phy[phy_index].config_init( 7296 ¶ms->phy[phy_index], 7297 params, vars); 7298 } 7299 } 7300 /* Reset the interrupt indication after phy was initialized */ 7301 elink_bits_dis(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + 7302 params->port*4, 7303 (ELINK_NIG_STATUS_XGXS0_LINK10G | 7304 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 7305 ELINK_NIG_STATUS_SERDES0_LINK_STATUS | 7306 ELINK_NIG_MASK_MI_INT)); 7307 return ELINK_STATUS_OK; 7308 } 7309 7310 #ifndef EXCLUDE_XGXS 7311 static void elink_int_link_reset(struct elink_phy *phy, 7312 struct elink_params *params) 7313 { 7314 #ifndef EXCLUDE_LINK_RESET 7315 /* Reset the SerDes/XGXS */ 7316 REG_WR(params->cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 7317 (0x1ff << (params->port*16))); 7318 #endif // EXCLUDE_LINK_RESET 7319 } 7320 #endif // EXCLUDE_XGXS 7321 7322 #if (!defined ELINK_EMUL_ONLY) && ((!defined EXCLUDE_BCM87x6) || (!defined EXCLUDE_SFX7101) || (!defined EXCLUDE_BCM8705)) 7323 static void elink_common_ext_link_reset(struct elink_phy *phy, 7324 struct elink_params *params) 7325 { 7326 #ifndef EXCLUDE_LINK_RESET 7327 struct elink_dev *cb = params->cb; 7328 u8 gpio_port; 7329 /* HW reset */ 7330 if (CHIP_IS_E2(params->chip_id)) 7331 gpio_port = PATH_ID(cb); 7332 else 7333 gpio_port = params->port; 7334 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7335 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7336 gpio_port); 7337 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 7338 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7339 gpio_port); 7340 ELINK_DEBUG_P0(cb, "reset external PHY\n"); 7341 #endif /* EXCLUDE_LINK_RESET */ 7342 } 7343 #endif /* ELINK_EMUL_ONLY */ 7344 7345 static elink_status_t elink_update_link_down(struct elink_params *params, 7346 struct elink_vars *vars) 7347 { 7348 struct elink_dev *cb = params->cb; 7349 u8 port = params->port; 7350 7351 ELINK_DEBUG_P1(cb, "Port %x: Link is down\n", port); 7352 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 7353 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 7354 /* Indicate no mac active */ 7355 vars->mac_type = ELINK_MAC_TYPE_NONE; 7356 7357 /* Update shared memory */ 7358 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7359 vars->line_speed = 0; 7360 elink_update_mng(params, vars->link_status); 7361 7362 /* Activate nig drain */ 7363 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 7364 7365 /* Disable emac */ 7366 if (!CHIP_IS_E3(params->chip_id)) 7367 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7368 7369 MSLEEP(cb, 10); 7370 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7371 /* Reset BigMac/Xmac */ 7372 if (CHIP_IS_E1X(params->chip_id) || 7373 CHIP_IS_E2(params->chip_id)) 7374 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 7375 #endif // #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 7376 7377 #ifndef EXCLUDE_WARPCORE 7378 if (CHIP_IS_E3(params->chip_id)) { 7379 /* Prevent LPI Generation by chip */ 7380 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 7381 0); 7382 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 7383 0); 7384 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 7385 SHMEM_EEE_ACTIVE_BIT); 7386 7387 elink_update_mng_eee(params, vars->eee_status); 7388 elink_set_xmac_rxtx(params, 0); 7389 elink_set_umac_rxtx(params, 0); 7390 } 7391 #endif // EXCLUDE_WARPCORE 7392 7393 return ELINK_STATUS_OK; 7394 } 7395 7396 static elink_status_t elink_update_link_up(struct elink_params *params, 7397 struct elink_vars *vars, 7398 u8 link_10g) 7399 { 7400 struct elink_dev *cb = params->cb; 7401 u8 phy_idx, port = params->port; 7402 elink_status_t rc = ELINK_STATUS_OK; 7403 7404 vars->link_status |= (LINK_STATUS_LINK_UP | 7405 LINK_STATUS_PHYSICAL_LINK_FLAG); 7406 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 7407 7408 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 7409 vars->link_status |= 7410 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 7411 7412 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 7413 vars->link_status |= 7414 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 7415 #ifndef EXCLUDE_WARPCORE 7416 if (ELINK_USES_WARPCORE(params->chip_id)) { 7417 if (link_10g) { 7418 if (elink_xmac_enable(params, vars, 0) == 7419 ELINK_STATUS_NO_LINK) { 7420 ELINK_DEBUG_P0(cb, "Found errors on XMAC\n"); 7421 vars->link_up = 0; 7422 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7423 vars->link_status &= ~LINK_STATUS_LINK_UP; 7424 } 7425 } else 7426 elink_umac_enable(params, vars, 0); 7427 elink_set_led(params, vars, 7428 ELINK_LED_MODE_OPER, vars->line_speed); 7429 7430 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 7431 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 7432 ELINK_DEBUG_P0(cb, "Enabling LPI assertion\n"); 7433 REG_WR(cb, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 7434 (params->port << 2), 1); 7435 REG_WR(cb, MISC_REG_CPMU_LP_DR_ENABLE, 1); 7436 REG_WR(cb, MISC_REG_CPMU_LP_MASK_ENT_P0 + 7437 (params->port << 2), 0xfc20); 7438 } 7439 } 7440 #endif // EXCLUDE_WARPCORE 7441 #ifndef EXCLUDE_XGXS 7442 if ((CHIP_IS_E1X(params->chip_id) || 7443 CHIP_IS_E2(params->chip_id))) { 7444 if (link_10g) { 7445 if (elink_bmac_enable(params, vars, 0, 1) == 7446 ELINK_STATUS_NO_LINK) { 7447 ELINK_DEBUG_P0(cb, "Found errors on BMAC\n"); 7448 vars->link_up = 0; 7449 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7450 vars->link_status &= ~LINK_STATUS_LINK_UP; 7451 } 7452 7453 elink_set_led(params, vars, 7454 ELINK_LED_MODE_OPER, ELINK_SPEED_10000); 7455 } else { 7456 rc = elink_emac_program(params, vars); 7457 elink_emac_enable(params, vars, 0); 7458 7459 /* AN complete? */ 7460 if ((vars->link_status & 7461 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 7462 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 7463 ELINK_SINGLE_MEDIA_DIRECT(params)) 7464 elink_set_gmii_tx_driver(params); 7465 } 7466 } 7467 #endif // EXCLUDE_XGXS 7468 7469 #ifndef ELINK_AUX_POWER 7470 /* PBF - link up */ 7471 if (CHIP_IS_E1X(params->chip_id)) 7472 rc |= elink_pbf_update(params, vars->flow_ctrl, 7473 vars->line_speed); 7474 #endif /* ELINK_AUX_POWER */ 7475 7476 /* Disable drain */ 7477 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 7478 7479 /* Update shared memory */ 7480 elink_update_mng(params, vars->link_status); 7481 #ifndef EXCLUDE_WARPCORE 7482 elink_update_mng_eee(params, vars->eee_status); 7483 #endif /* #ifndef EXCLUDE_WARPCORE */ 7484 /* Check remote fault */ 7485 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 7486 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 7487 elink_check_half_open_conn(params, vars, 0); 7488 break; 7489 } 7490 } 7491 MSLEEP(cb, 20); 7492 return rc; 7493 } 7494 7495 static void elink_chng_link_count(struct elink_params *params, u8 clear) 7496 { 7497 struct elink_dev *cb = params->cb; 7498 u32 addr, val; 7499 7500 /* Verify the link_change_count is supported by the MFW */ 7501 if (!(SHMEM2_HAS(cb, params->shmem2_base, link_change_count))) 7502 return; 7503 7504 addr = params->shmem2_base + 7505 OFFSETOF(struct shmem2_region, link_change_count[params->port]); 7506 if (clear) 7507 val = 0; 7508 else 7509 val = REG_RD(cb, addr) + 1; 7510 REG_WR(cb, addr, val); 7511 } 7512 7513 /* The elink_link_update function should be called upon link 7514 * interrupt. 7515 * Link is considered up as follows: 7516 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 7517 * to be up 7518 * - SINGLE_MEDIA - The link between the 577xx and the external 7519 * phy (XGXS) need to up as well as the external link of the 7520 * phy (PHY_EXT1) 7521 * - DUAL_MEDIA - The link between the 577xx and the first 7522 * external phy needs to be up, and at least one of the 2 7523 * external phy link must be up. 7524 */ 7525 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars) 7526 { 7527 struct elink_dev *cb = params->cb; 7528 struct elink_vars phy_vars[ELINK_MAX_PHYS]; 7529 u8 port = params->port; 7530 u8 link_10g_plus, phy_index; 7531 u32 prev_link_status = vars->link_status; 7532 u8 ext_phy_link_up = 0, cur_link_up; 7533 elink_status_t rc = ELINK_STATUS_OK; 7534 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 7535 u8 active_external_phy = ELINK_INT_PHY; 7536 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 7537 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7538 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 7539 phy_index++) { 7540 phy_vars[phy_index].flow_ctrl = 0; 7541 phy_vars[phy_index].link_status = 0; 7542 phy_vars[phy_index].line_speed = 0; 7543 phy_vars[phy_index].duplex = DUPLEX_FULL; 7544 phy_vars[phy_index].phy_link_up = 0; 7545 phy_vars[phy_index].link_up = 0; 7546 phy_vars[phy_index].fault_detected = 0; 7547 /* different consideration, since vars holds inner state */ 7548 phy_vars[phy_index].eee_status = vars->eee_status; 7549 } 7550 7551 if (ELINK_USES_WARPCORE(params->chip_id)) 7552 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); 7553 7554 ELINK_DEBUG_P3(cb, "port %x, XGXS?%x, int_status 0x%x\n", 7555 port, (vars->phy_flags & PHY_XGXS_FLAG), 7556 REG_RD(cb, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 7557 7558 ELINK_DEBUG_P3(cb, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 7559 REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 7560 REG_RD(cb, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0, 7561 REG_RD(cb, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 7562 7563 ELINK_DEBUG_P2(cb, " 10G %x, XGXS_LINK %x\n", 7564 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 7565 REG_RD(cb, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 7566 7567 /* Disable emac */ 7568 if (!CHIP_IS_E3(params->chip_id)) 7569 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7570 7571 /* Step 1: 7572 * Check external link change only for external phys, and apply 7573 * priority selection between them in case the link on both phys 7574 * is up. Note that instead of the common vars, a temporary 7575 * vars argument is used since each phy may have different link/ 7576 * speed/duplex result 7577 */ 7578 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7579 phy_index++) { 7580 struct elink_phy *phy = ¶ms->phy[phy_index]; 7581 if (!phy->read_status) 7582 continue; 7583 /* Read link status and params of this ext phy */ 7584 cur_link_up = phy->read_status(phy, params, 7585 &phy_vars[phy_index]); 7586 if (cur_link_up) { 7587 ELINK_DEBUG_P1(cb, "phy in index %d link is up\n", 7588 phy_index); 7589 } else { 7590 ELINK_DEBUG_P1(cb, "phy in index %d link is down\n", 7591 phy_index); 7592 continue; 7593 } 7594 7595 if (!ext_phy_link_up) { 7596 ext_phy_link_up = 1; 7597 active_external_phy = phy_index; 7598 } else { 7599 switch (elink_phy_selection(params)) { 7600 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 7601 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 7602 /* In this option, the first PHY makes sure to pass the 7603 * traffic through itself only. 7604 * Its not clear how to reset the link on the second phy 7605 */ 7606 active_external_phy = ELINK_EXT_PHY1; 7607 break; 7608 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 7609 /* In this option, the first PHY makes sure to pass the 7610 * traffic through the second PHY. 7611 */ 7612 active_external_phy = ELINK_EXT_PHY2; 7613 break; 7614 default: 7615 /* Link indication on both PHYs with the following cases 7616 * is invalid: 7617 * - FIRST_PHY means that second phy wasn't initialized, 7618 * hence its link is expected to be down 7619 * - SECOND_PHY means that first phy should not be able 7620 * to link up by itself (using configuration) 7621 * - DEFAULT should be overriden during initialiazation 7622 */ 7623 ELINK_DEBUG_P1(cb, "Invalid link indication" 7624 "mpc=0x%x. DISABLING LINK !!!\n", 7625 params->multi_phy_config); 7626 ext_phy_link_up = 0; 7627 break; 7628 } 7629 } 7630 } 7631 prev_line_speed = vars->line_speed; 7632 /* Step 2: 7633 * Read the status of the internal phy. In case of 7634 * DIRECT_SINGLE_MEDIA board, this link is the external link, 7635 * otherwise this is the link between the 577xx and the first 7636 * external phy 7637 */ 7638 if (params->phy[ELINK_INT_PHY].read_status) 7639 params->phy[ELINK_INT_PHY].read_status( 7640 ¶ms->phy[ELINK_INT_PHY], 7641 params, vars); 7642 /* The INT_PHY flow control reside in the vars. This include the 7643 * case where the speed or flow control are not set to AUTO. 7644 * Otherwise, the active external phy flow control result is set 7645 * to the vars. The ext_phy_line_speed is needed to check if the 7646 * speed is different between the internal phy and external phy. 7647 * This case may be result of intermediate link speed change. 7648 */ 7649 if (active_external_phy > ELINK_INT_PHY) { 7650 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 7651 /* Link speed is taken from the XGXS. AN and FC result from 7652 * the external phy. 7653 */ 7654 vars->link_status |= phy_vars[active_external_phy].link_status; 7655 7656 /* if active_external_phy is first PHY and link is up - disable 7657 * disable TX on second external PHY 7658 */ 7659 if (active_external_phy == ELINK_EXT_PHY1) { 7660 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { 7661 ELINK_DEBUG_P0(cb, 7662 "Disabling TX on EXT_PHY2\n"); 7663 params->phy[ELINK_EXT_PHY2].phy_specific_func( 7664 ¶ms->phy[ELINK_EXT_PHY2], 7665 params, ELINK_DISABLE_TX); 7666 } 7667 } 7668 7669 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 7670 vars->duplex = phy_vars[active_external_phy].duplex; 7671 if (params->phy[active_external_phy].supported & 7672 ELINK_SUPPORTED_FIBRE) 7673 vars->link_status |= LINK_STATUS_SERDES_LINK; 7674 else 7675 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 7676 7677 vars->eee_status = phy_vars[active_external_phy].eee_status; 7678 7679 ELINK_DEBUG_P1(cb, "Active external phy selected: %x\n", 7680 active_external_phy); 7681 } 7682 7683 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7684 phy_index++) { 7685 if (params->phy[phy_index].flags & 7686 ELINK_FLAGS_REARM_LATCH_SIGNAL) { 7687 elink_rearm_latch_signal(cb, port, 7688 phy_index == 7689 active_external_phy); 7690 break; 7691 } 7692 } 7693 ELINK_DEBUG_P3(cb, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 7694 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 7695 vars->link_status, ext_phy_line_speed); 7696 /* Upon link speed change set the NIG into drain mode. Comes to 7697 * deals with possible FIFO glitch due to clk change when speed 7698 * is decreased without link down indicator 7699 */ 7700 7701 if (vars->phy_link_up) { 7702 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 7703 (ext_phy_line_speed != vars->line_speed)) { 7704 ELINK_DEBUG_P2(cb, "Internal link speed %d is" 7705 " different than the external" 7706 " link speed %d\n", vars->line_speed, 7707 ext_phy_line_speed); 7708 vars->phy_link_up = 0; 7709 } else if (prev_line_speed != vars->line_speed) { 7710 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 7711 0); 7712 MSLEEP(cb, 1); 7713 } 7714 } 7715 7716 /* Anything 10 and over uses the bmac */ 7717 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 7718 7719 elink_link_int_ack(params, vars, link_10g_plus); 7720 7721 /* In case external phy link is up, and internal link is down 7722 * (not initialized yet probably after link initialization, it 7723 * needs to be initialized. 7724 * Note that after link down-up as result of cable plug, the xgxs 7725 * link would probably become up again without the need 7726 * initialize it 7727 */ 7728 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { 7729 ELINK_DEBUG_P3(cb, "ext_phy_link_up = %d, int_link_up = %d," 7730 " init_preceding = %d\n", ext_phy_link_up, 7731 vars->phy_link_up, 7732 params->phy[ELINK_EXT_PHY1].flags & 7733 ELINK_FLAGS_INIT_XGXS_FIRST); 7734 if (!(params->phy[ELINK_EXT_PHY1].flags & 7735 ELINK_FLAGS_INIT_XGXS_FIRST) 7736 && ext_phy_link_up && !vars->phy_link_up) { 7737 vars->line_speed = ext_phy_line_speed; 7738 if (vars->line_speed < ELINK_SPEED_1000) 7739 vars->phy_flags |= PHY_SGMII_FLAG; 7740 else 7741 vars->phy_flags &= ~PHY_SGMII_FLAG; 7742 7743 if (params->phy[ELINK_INT_PHY].config_init) 7744 params->phy[ELINK_INT_PHY].config_init( 7745 ¶ms->phy[ELINK_INT_PHY], params, 7746 vars); 7747 } 7748 } 7749 /* Link is up only if both local phy and external phy (in case of 7750 * non-direct board) are up and no fault detected on active PHY. 7751 */ 7752 vars->link_up = (vars->phy_link_up && 7753 (ext_phy_link_up || 7754 ELINK_SINGLE_MEDIA_DIRECT(params)) && 7755 (phy_vars[active_external_phy].fault_detected == 0)); 7756 7757 /* Update the PFC configuration in case it was changed */ 7758 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 7759 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7760 else 7761 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7762 7763 if (vars->link_up) 7764 rc = elink_update_link_up(params, vars, link_10g_plus); 7765 else 7766 rc = elink_update_link_down(params, vars); 7767 7768 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP) 7769 elink_chng_link_count(params, 0); 7770 7771 #ifndef ELINK_AUX_POWER 7772 /* Update MCP link status was changed */ 7773 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7774 elink_cb_fw_command(cb, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7775 #endif // ELINK_AUX_POWER 7776 7777 return rc; 7778 } 7779 7780 #endif // EXCLUDE_NON_COMMON_INIT 7781 #ifndef ELINK_EMUL_ONLY 7782 /*****************************************************************************/ 7783 /* External Phy section */ 7784 /*****************************************************************************/ 7785 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port) 7786 { 7787 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7788 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7789 MSLEEP(cb, 1); 7790 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 7791 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7792 } 7793 7794 #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) || !defined(EXCLUDE_BCM8705) || !defined(EXCLUDE_BCM87x6) 7795 static void elink_save_spirom_version(struct elink_dev *cb, u8 port, 7796 u32 spirom_ver, u32 ver_addr) 7797 { 7798 ELINK_DEBUG_P3(cb, "FW version 0x%x:0x%x for port %d\n", 7799 (u16)(spirom_ver>>16), (u16)spirom_ver, port); 7800 7801 if (ver_addr) 7802 REG_WR(cb, ver_addr, spirom_ver); 7803 } 7804 7805 #if (!defined EXCLUDE_XGXS) && (!defined EXCLUDE_COMMON_INIT) 7806 static void elink_save_bcm_spirom_ver(struct elink_dev *cb, 7807 struct elink_phy *phy, 7808 u8 port) 7809 { 7810 u16 fw_ver1, fw_ver2; 7811 7812 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7813 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7814 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 7815 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7816 elink_save_spirom_version(cb, port, (u32)(fw_ver1<<16 | fw_ver2), 7817 phy->ver_addr); 7818 } 7819 #endif // EXCLUDE_XGXS 7820 7821 #ifndef EXCLUDE_NON_COMMON_INIT 7822 static void elink_ext_phy_10G_an_resolve(struct elink_dev *cb, 7823 struct elink_phy *phy, 7824 struct elink_vars *vars) 7825 { 7826 u16 val; 7827 elink_cl45_read(cb, phy, 7828 MDIO_AN_DEVAD, 7829 MDIO_AN_REG_STATUS, &val); 7830 elink_cl45_read(cb, phy, 7831 MDIO_AN_DEVAD, 7832 MDIO_AN_REG_STATUS, &val); 7833 if (val & (1<<5)) 7834 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7835 if ((val & (1<<0)) == 0) 7836 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7837 } 7838 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 7839 #endif // #if !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) || !defined(EXCLUDE_SFX7101) 7840 7841 /******************************************************************/ 7842 /* common BCM8073/BCM8727 PHY SECTION */ 7843 /******************************************************************/ 7844 #ifndef EXCLUDE_BCM8727_BCM8073 7845 #ifndef EXCLUDE_NON_COMMON_INIT 7846 static void elink_8073_resolve_fc(struct elink_phy *phy, 7847 struct elink_params *params, 7848 struct elink_vars *vars) 7849 { 7850 struct elink_dev *cb = params->cb; 7851 if (phy->req_line_speed == ELINK_SPEED_10 || 7852 phy->req_line_speed == ELINK_SPEED_100) { 7853 vars->flow_ctrl = phy->req_flow_ctrl; 7854 return; 7855 } 7856 7857 if (elink_ext_phy_resolve_fc(phy, params, vars) && 7858 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { 7859 u16 pause_result; 7860 u16 ld_pause; /* local */ 7861 u16 lp_pause; /* link partner */ 7862 elink_cl45_read(cb, phy, 7863 MDIO_AN_DEVAD, 7864 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7865 7866 elink_cl45_read(cb, phy, 7867 MDIO_AN_DEVAD, 7868 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7869 pause_result = (ld_pause & 7870 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7871 pause_result |= (lp_pause & 7872 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7873 7874 elink_pause_resolve(vars, pause_result); 7875 ELINK_DEBUG_P1(cb, "Ext PHY CL37 pause result 0x%x\n", 7876 pause_result); 7877 } 7878 } 7879 #endif // EXCLUDE_NON_COMMON_INIT 7880 #ifndef EXCLUDE_COMMON_INIT 7881 static elink_status_t elink_8073_8727_external_rom_boot(struct elink_dev *cb, 7882 struct elink_phy *phy, 7883 u8 port) 7884 { 7885 u32 count = 0; 7886 u16 fw_ver1, fw_msgout; 7887 elink_status_t rc = ELINK_STATUS_OK; 7888 7889 /* Boot port from external ROM */ 7890 /* EDC grst */ 7891 elink_cl45_write(cb, phy, 7892 MDIO_PMA_DEVAD, 7893 MDIO_PMA_REG_GEN_CTRL, 7894 0x0001); 7895 7896 /* Ucode reboot and rst */ 7897 elink_cl45_write(cb, phy, 7898 MDIO_PMA_DEVAD, 7899 MDIO_PMA_REG_GEN_CTRL, 7900 0x008c); 7901 7902 elink_cl45_write(cb, phy, 7903 MDIO_PMA_DEVAD, 7904 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7905 7906 /* Reset internal microprocessor */ 7907 elink_cl45_write(cb, phy, 7908 MDIO_PMA_DEVAD, 7909 MDIO_PMA_REG_GEN_CTRL, 7910 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7911 7912 /* Release srst bit */ 7913 elink_cl45_write(cb, phy, 7914 MDIO_PMA_DEVAD, 7915 MDIO_PMA_REG_GEN_CTRL, 7916 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7917 7918 /* Delay 100ms per the PHY specifications */ 7919 MSLEEP(cb, 100); 7920 7921 /* 8073 sometimes taking longer to download */ 7922 do { 7923 count++; 7924 if (count > 300) { 7925 ELINK_DEBUG_P2(cb, 7926 "elink_8073_8727_external_rom_boot port %x:" 7927 "Download failed. fw version = 0x%x\n", 7928 port, fw_ver1); 7929 rc = ELINK_STATUS_ERROR; 7930 break; 7931 } 7932 7933 elink_cl45_read(cb, phy, 7934 MDIO_PMA_DEVAD, 7935 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7936 elink_cl45_read(cb, phy, 7937 MDIO_PMA_DEVAD, 7938 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7939 7940 MSLEEP(cb, 1); 7941 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7942 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7943 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7944 7945 /* Clear ser_boot_ctl bit */ 7946 elink_cl45_write(cb, phy, 7947 MDIO_PMA_DEVAD, 7948 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7949 elink_save_bcm_spirom_ver(cb, phy, port); 7950 7951 ELINK_DEBUG_P2(cb, 7952 "elink_8073_8727_external_rom_boot port %x:" 7953 "Download complete. fw version = 0x%x\n", 7954 port, fw_ver1); 7955 7956 return rc; 7957 } 7958 #endif // EXCLUDE_COMMON_INIT 7959 7960 /******************************************************************/ 7961 /* BCM8073 PHY SECTION */ 7962 /******************************************************************/ 7963 #ifndef EXCLUDE_NON_COMMON_INIT 7964 static elink_status_t elink_8073_is_snr_needed(struct elink_dev *cb, struct elink_phy *phy) 7965 { 7966 /* This is only required for 8073A1, version 102 only */ 7967 u16 val; 7968 7969 /* Read 8073 HW revision*/ 7970 elink_cl45_read(cb, phy, 7971 MDIO_PMA_DEVAD, 7972 MDIO_PMA_REG_8073_CHIP_REV, &val); 7973 7974 if (val != 1) { 7975 /* No need to workaround in 8073 A1 */ 7976 return ELINK_STATUS_OK; 7977 } 7978 7979 elink_cl45_read(cb, phy, 7980 MDIO_PMA_DEVAD, 7981 MDIO_PMA_REG_ROM_VER2, &val); 7982 7983 /* SNR should be applied only for version 0x102 */ 7984 if (val != 0x102) 7985 return ELINK_STATUS_OK; 7986 7987 return 1; 7988 } 7989 7990 static elink_status_t elink_8073_xaui_wa(struct elink_dev *cb, struct elink_phy *phy) 7991 { 7992 u16 val, cnt, cnt1 ; 7993 7994 elink_cl45_read(cb, phy, 7995 MDIO_PMA_DEVAD, 7996 MDIO_PMA_REG_8073_CHIP_REV, &val); 7997 7998 if (val > 0) { 7999 /* No need to workaround in 8073 A1 */ 8000 return ELINK_STATUS_OK; 8001 } 8002 /* XAUI workaround in 8073 A0: */ 8003 8004 /* After loading the boot ROM and restarting Autoneg, poll 8005 * Dev1, Reg $C820: 8006 */ 8007 8008 for (cnt = 0; cnt < 1000; cnt++) { 8009 elink_cl45_read(cb, phy, 8010 MDIO_PMA_DEVAD, 8011 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8012 &val); 8013 /* If bit [14] = 0 or bit [13] = 0, continue on with 8014 * system initialization (XAUI work-around not required, as 8015 * these bits indicate 2.5G or 1G link up). 8016 */ 8017 if (!(val & (1<<14)) || !(val & (1<<13))) { 8018 ELINK_DEBUG_P0(cb, "XAUI work-around not required\n"); 8019 return ELINK_STATUS_OK; 8020 } else if (!(val & (1<<15))) { 8021 ELINK_DEBUG_P0(cb, "bit 15 went off\n"); 8022 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 8023 * MSB (bit15) goes to 1 (indicating that the XAUI 8024 * workaround has completed), then continue on with 8025 * system initialization. 8026 */ 8027 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 8028 elink_cl45_read(cb, phy, 8029 MDIO_PMA_DEVAD, 8030 MDIO_PMA_REG_8073_XAUI_WA, &val); 8031 if (val & (1<<15)) { 8032 ELINK_DEBUG_P0(cb, 8033 "XAUI workaround has completed\n"); 8034 return ELINK_STATUS_OK; 8035 } 8036 MSLEEP(cb, 3); 8037 } 8038 break; 8039 } 8040 MSLEEP(cb, 3); 8041 } 8042 ELINK_DEBUG_P0(cb, "Warning: XAUI work-around timeout !!!\n"); 8043 return ELINK_STATUS_ERROR; 8044 } 8045 8046 #ifdef ELINK_INCLUDE_LOOPBACK 8047 static void elink_807x_force_10G(struct elink_dev *cb, struct elink_phy *phy) 8048 { 8049 /* Force KR or KX */ 8050 elink_cl45_write(cb, phy, 8051 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8052 elink_cl45_write(cb, phy, 8053 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 8054 elink_cl45_write(cb, phy, 8055 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 8056 elink_cl45_write(cb, phy, 8057 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 8058 } 8059 #endif // ELINK_INCLUDE_LOOPBACK 8060 8061 static void elink_8073_set_pause_cl37(struct elink_params *params, 8062 struct elink_phy *phy, 8063 struct elink_vars *vars) 8064 { 8065 u16 cl37_val; 8066 struct elink_dev *cb = params->cb; 8067 elink_cl45_read(cb, phy, 8068 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 8069 8070 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8071 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 8072 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 8073 if ((vars->ieee_fc & 8074 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 8075 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 8076 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 8077 } 8078 if ((vars->ieee_fc & 8079 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 8080 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 8081 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 8082 } 8083 if ((vars->ieee_fc & 8084 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 8085 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 8086 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8087 } 8088 ELINK_DEBUG_P1(cb, 8089 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 8090 8091 elink_cl45_write(cb, phy, 8092 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 8093 #ifndef ELINK_AUX_POWER 8094 MSLEEP(cb, 500); 8095 #endif // ELINK_AUX_POWER 8096 } 8097 8098 static void elink_8073_specific_func(struct elink_phy *phy, 8099 struct elink_params *params, 8100 u32 action) 8101 { 8102 struct elink_dev *cb = params->cb; 8103 switch (action) { 8104 case ELINK_PHY_INIT: 8105 /* Enable LASI */ 8106 elink_cl45_write(cb, phy, 8107 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 8108 elink_cl45_write(cb, phy, 8109 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 8110 break; 8111 } 8112 } 8113 8114 static elink_status_t elink_8073_config_init(struct elink_phy *phy, 8115 struct elink_params *params, 8116 struct elink_vars *vars) 8117 { 8118 struct elink_dev *cb = params->cb; 8119 u16 val = 0, tmp1; 8120 u8 gpio_port; 8121 ELINK_DEBUG_P0(cb, "Init 8073\n"); 8122 8123 if (CHIP_IS_E2(params->chip_id)) 8124 gpio_port = PATH_ID(cb); 8125 else 8126 gpio_port = params->port; 8127 /* Restore normal power mode*/ 8128 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8129 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8130 8131 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 8132 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8133 8134 elink_8073_specific_func(phy, params, ELINK_PHY_INIT); 8135 elink_8073_set_pause_cl37(params, phy, vars); 8136 8137 elink_cl45_read(cb, phy, 8138 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8139 8140 elink_cl45_read(cb, phy, 8141 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8142 8143 ELINK_DEBUG_P1(cb, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 8144 8145 /* Swap polarity if required - Must be done only in non-1G mode */ 8146 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8147 /* Configure the 8073 to swap _P and _N of the KR lines */ 8148 ELINK_DEBUG_P0(cb, "Swapping polarity for the 8073\n"); 8149 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 8150 elink_cl45_read(cb, phy, 8151 MDIO_PMA_DEVAD, 8152 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 8153 elink_cl45_write(cb, phy, 8154 MDIO_PMA_DEVAD, 8155 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 8156 (val | (3<<9))); 8157 } 8158 8159 8160 /* Enable CL37 BAM */ 8161 if (REG_RD(cb, params->shmem_base + 8162 OFFSETOF(struct shmem_region, dev_info. 8163 port_hw_config[params->port].default_cfg)) & 8164 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 8165 8166 elink_cl45_read(cb, phy, 8167 MDIO_AN_DEVAD, 8168 MDIO_AN_REG_8073_BAM, &val); 8169 elink_cl45_write(cb, phy, 8170 MDIO_AN_DEVAD, 8171 MDIO_AN_REG_8073_BAM, val | 1); 8172 ELINK_DEBUG_P0(cb, "Enable CL37 BAM on KR\n"); 8173 } 8174 #ifdef ELINK_INCLUDE_LOOPBACK 8175 if (params->loopback_mode == ELINK_LOOPBACK_EXT) { 8176 elink_807x_force_10G(cb, phy); 8177 ELINK_DEBUG_P0(cb, "Forced speed 10G on 807X\n"); 8178 return ELINK_STATUS_OK; 8179 } else { 8180 elink_cl45_write(cb, phy, 8181 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 8182 } 8183 #endif // ELINK_INCLUDE_LOOPBACK 8184 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { 8185 if (phy->req_line_speed == ELINK_SPEED_10000) { 8186 val = (1<<7); 8187 } else if (phy->req_line_speed == ELINK_SPEED_2500) { 8188 val = (1<<5); 8189 /* Note that 2.5G works only when used with 1G 8190 * advertisement 8191 */ 8192 } else 8193 val = (1<<5); 8194 } else { 8195 val = 0; 8196 if (phy->speed_cap_mask & 8197 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 8198 val |= (1<<7); 8199 8200 /* Note that 2.5G works only when used with 1G advertisement */ 8201 if (phy->speed_cap_mask & 8202 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 8203 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8204 val |= (1<<5); 8205 ELINK_DEBUG_P1(cb, "807x autoneg val = 0x%x\n", val); 8206 } 8207 8208 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 8209 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 8210 8211 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 8212 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || 8213 (phy->req_line_speed == ELINK_SPEED_2500)) { 8214 u16 phy_ver; 8215 /* Allow 2.5G for A1 and above */ 8216 elink_cl45_read(cb, phy, 8217 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 8218 &phy_ver); 8219 ELINK_DEBUG_P0(cb, "Add 2.5G\n"); 8220 if (phy_ver > 0) 8221 tmp1 |= 1; 8222 else 8223 tmp1 &= 0xfffe; 8224 } else { 8225 ELINK_DEBUG_P0(cb, "Disable 2.5G\n"); 8226 tmp1 &= 0xfffe; 8227 } 8228 8229 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 8230 /* Add support for CL37 (passive mode) II */ 8231 8232 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 8233 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 8234 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 8235 0x20 : 0x40))); 8236 8237 /* Add support for CL37 (passive mode) III */ 8238 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8239 8240 /* The SNR will improve about 2db by changing BW and FEE main 8241 * tap. Rest commands are executed after link is up 8242 * Change FFE main cursor to 5 in EDC register 8243 */ 8244 if (elink_8073_is_snr_needed(cb, phy)) 8245 elink_cl45_write(cb, phy, 8246 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 8247 0xFB0C); 8248 8249 /* Enable FEC (Forware Error Correction) Request in the AN */ 8250 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 8251 tmp1 |= (1<<15); 8252 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 8253 8254 elink_ext_phy_set_pause(params, phy, vars); 8255 8256 /* Restart autoneg */ 8257 MSLEEP(cb, 500); 8258 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8259 ELINK_DEBUG_P2(cb, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 8260 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 8261 return ELINK_STATUS_OK; 8262 } 8263 8264 static elink_status_t 8265 elink_8073_read_status(struct elink_phy *phy, struct elink_params *params, 8266 struct elink_vars *vars) 8267 { 8268 struct elink_dev *cb = params->cb; 8269 u8 link_up = 0; 8270 u16 val1, val2; 8271 u16 link_status = 0; 8272 u16 an1000_status = 0; 8273 8274 elink_cl45_read(cb, phy, 8275 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8276 8277 ELINK_DEBUG_P1(cb, "8703 LASI status 0x%x\n", val1); 8278 8279 /* Clear the interrupt LASI status register */ 8280 elink_cl45_read(cb, phy, 8281 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8282 elink_cl45_read(cb, phy, 8283 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 8284 ELINK_DEBUG_P2(cb, "807x PCS status 0x%x->0x%x\n", val2, val1); 8285 /* Clear MSG-OUT */ 8286 elink_cl45_read(cb, phy, 8287 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 8288 8289 /* Check the LASI */ 8290 elink_cl45_read(cb, phy, 8291 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8292 8293 ELINK_DEBUG_P1(cb, "KR 0x9003 0x%x\n", val2); 8294 8295 /* Check the link status */ 8296 elink_cl45_read(cb, phy, 8297 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8298 ELINK_DEBUG_P1(cb, "KR PCS status 0x%x\n", val2); 8299 8300 elink_cl45_read(cb, phy, 8301 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8302 elink_cl45_read(cb, phy, 8303 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8304 link_up = ((val1 & 4) == 4); 8305 ELINK_DEBUG_P1(cb, "PMA_REG_STATUS=0x%x\n", val1); 8306 8307 if (link_up && 8308 ((phy->req_line_speed != ELINK_SPEED_10000))) { 8309 if (elink_8073_xaui_wa(cb, phy) != 0) 8310 return 0; 8311 } 8312 elink_cl45_read(cb, phy, 8313 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8314 elink_cl45_read(cb, phy, 8315 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8316 8317 /* Check the link status on 1.1.2 */ 8318 elink_cl45_read(cb, phy, 8319 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8320 elink_cl45_read(cb, phy, 8321 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8322 ELINK_DEBUG_P3(cb, "KR PMA status 0x%x->0x%x," 8323 "an_link_status=0x%x\n", val2, val1, an1000_status); 8324 8325 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 8326 if (link_up && elink_8073_is_snr_needed(cb, phy)) { 8327 /* The SNR will improve about 2dbby changing the BW and FEE main 8328 * tap. The 1st write to change FFE main tap is set before 8329 * restart AN. Change PLL Bandwidth in EDC register 8330 */ 8331 elink_cl45_write(cb, phy, 8332 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 8333 0x26BC); 8334 8335 /* Change CDR Bandwidth in EDC register */ 8336 elink_cl45_write(cb, phy, 8337 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 8338 0x0333); 8339 } 8340 elink_cl45_read(cb, phy, 8341 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8342 &link_status); 8343 8344 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 8345 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 8346 link_up = 1; 8347 vars->line_speed = ELINK_SPEED_10000; 8348 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 8349 params->port); 8350 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 8351 link_up = 1; 8352 vars->line_speed = ELINK_SPEED_2500; 8353 ELINK_DEBUG_P1(cb, "port %x: External link up in 2.5G\n", 8354 params->port); 8355 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 8356 link_up = 1; 8357 vars->line_speed = ELINK_SPEED_1000; 8358 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 8359 params->port); 8360 } else { 8361 link_up = 0; 8362 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 8363 params->port); 8364 } 8365 8366 if (link_up) { 8367 /* Swap polarity if required */ 8368 if (params->lane_config & 8369 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8370 /* Configure the 8073 to swap P and N of the KR lines */ 8371 elink_cl45_read(cb, phy, 8372 MDIO_XS_DEVAD, 8373 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 8374 /* Set bit 3 to invert Rx in 1G mode and clear this bit 8375 * when it`s in 10G mode. 8376 */ 8377 if (vars->line_speed == ELINK_SPEED_1000) { 8378 ELINK_DEBUG_P0(cb, "Swapping 1G polarity for" 8379 "the 8073\n"); 8380 val1 |= (1<<3); 8381 } else 8382 val1 &= ~(1<<3); 8383 8384 elink_cl45_write(cb, phy, 8385 MDIO_XS_DEVAD, 8386 MDIO_XS_REG_8073_RX_CTRL_PCIE, 8387 val1); 8388 } 8389 elink_ext_phy_10G_an_resolve(cb, phy, vars); 8390 elink_8073_resolve_fc(phy, params, vars); 8391 vars->duplex = DUPLEX_FULL; 8392 } 8393 8394 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 8395 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 8396 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 8397 8398 if (val1 & (1<<5)) 8399 vars->link_status |= 8400 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 8401 if (val1 & (1<<7)) 8402 vars->link_status |= 8403 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 8404 } 8405 8406 return link_up; 8407 } 8408 8409 static void elink_8073_link_reset(struct elink_phy *phy, 8410 struct elink_params *params) 8411 { 8412 #ifndef EXCLUDE_LINK_RESET 8413 struct elink_dev *cb = params->cb; 8414 u8 gpio_port; 8415 if (CHIP_IS_E2(params->chip_id)) 8416 gpio_port = PATH_ID(cb); 8417 else 8418 gpio_port = params->port; 8419 ELINK_DEBUG_P1(cb, "Setting 8073 port %d into low power mode\n", 8420 gpio_port); 8421 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8422 MISC_REGISTERS_GPIO_OUTPUT_LOW, 8423 gpio_port); 8424 #endif // EXCLUDE_LINK_RESET 8425 } 8426 #endif // EXCLUDE_NON_COMMON_INIT 8427 #endif // EXCLUDE_BCM8727_BCM8073 8428 8429 /******************************************************************/ 8430 /* BCM8705 PHY SECTION */ 8431 /******************************************************************/ 8432 #ifndef EXCLUDE_BCM8705 8433 static elink_status_t elink_8705_config_init(struct elink_phy *phy, 8434 struct elink_params *params, 8435 struct elink_vars *vars) 8436 { 8437 struct elink_dev *cb = params->cb; 8438 ELINK_DEBUG_P0(cb, "init 8705\n"); 8439 /* Restore normal power mode*/ 8440 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 8441 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8442 /* HW reset */ 8443 elink_ext_phy_hw_reset(cb, params->port); 8444 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8445 elink_wait_reset_complete(cb, phy, params); 8446 8447 elink_cl45_write(cb, phy, 8448 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 8449 elink_cl45_write(cb, phy, 8450 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 8451 elink_cl45_write(cb, phy, 8452 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 8453 elink_cl45_write(cb, phy, 8454 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 8455 /* BCM8705 doesn't have microcode, hence the 0 */ 8456 elink_save_spirom_version(cb, params->port, params->shmem_base, 0); 8457 return ELINK_STATUS_OK; 8458 } 8459 8460 static elink_status_t 8461 elink_8705_read_status(struct elink_phy *phy, struct elink_params *params, 8462 struct elink_vars *vars) 8463 { 8464 u8 link_up = 0; 8465 u16 val1, rx_sd; 8466 struct elink_dev *cb = params->cb; 8467 ELINK_DEBUG_P0(cb, "read status 8705\n"); 8468 elink_cl45_read(cb, phy, 8469 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8470 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8471 8472 elink_cl45_read(cb, phy, 8473 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8474 ELINK_DEBUG_P1(cb, "8705 LASI status 0x%x\n", val1); 8475 8476 elink_cl45_read(cb, phy, 8477 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8478 8479 elink_cl45_read(cb, phy, 8480 MDIO_PMA_DEVAD, 0xc809, &val1); 8481 elink_cl45_read(cb, phy, 8482 MDIO_PMA_DEVAD, 0xc809, &val1); 8483 8484 ELINK_DEBUG_P1(cb, "8705 1.c809 val=0x%x\n", val1); 8485 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 8486 if (link_up) { 8487 vars->line_speed = ELINK_SPEED_10000; 8488 elink_ext_phy_resolve_fc(phy, params, vars); 8489 } 8490 return link_up; 8491 } 8492 8493 #endif /* EXCLUDE_BCM8705 */ 8494 /******************************************************************/ 8495 /* SFP+ module Section */ 8496 /******************************************************************/ 8497 #ifndef EXCLUDE_NON_COMMON_INIT 8498 #ifndef EXCLUDE_BCM8727_BCM8073 8499 static void elink_set_disable_pmd_transmit(struct elink_params *params, 8500 struct elink_phy *phy, 8501 u8 pmd_dis) 8502 { 8503 struct elink_dev *cb = params->cb; 8504 /* Disable transmitter only for bootcodes which can enable it afterwards 8505 * (for D3 link) 8506 */ 8507 if (pmd_dis) { 8508 if (params->feature_config_flags & 8509 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { 8510 ELINK_DEBUG_P0(cb, "Disabling PMD transmitter\n"); 8511 } else { 8512 ELINK_DEBUG_P0(cb, "NOT disabling PMD transmitter\n"); 8513 return; 8514 } 8515 } else 8516 ELINK_DEBUG_P0(cb, "Enabling PMD transmitter\n"); 8517 elink_cl45_write(cb, phy, 8518 MDIO_PMA_DEVAD, 8519 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 8520 } 8521 #endif // EXCLUDE_BCM8727_BCM8073 8522 8523 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8524 static u8 elink_get_gpio_port(struct elink_params *params) 8525 { 8526 u8 gpio_port; 8527 u32 swap_val, swap_override; 8528 struct elink_dev *cb = params->cb; 8529 if (CHIP_IS_E2(params->chip_id)) 8530 gpio_port = PATH_ID(cb); 8531 else 8532 gpio_port = params->port; 8533 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 8534 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 8535 return gpio_port ^ (swap_val && swap_override); 8536 } 8537 8538 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, 8539 struct elink_phy *phy, 8540 u8 tx_en) 8541 { 8542 u16 val; 8543 u8 port = params->port; 8544 struct elink_dev *cb = params->cb; 8545 u32 tx_en_mode; 8546 8547 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 8548 tx_en_mode = REG_RD(cb, params->shmem_base + 8549 OFFSETOF(struct shmem_region, 8550 dev_info.port_hw_config[port].sfp_ctrl)) & 8551 PORT_HW_CFG_TX_LASER_MASK; 8552 ELINK_DEBUG_P3(cb, "Setting transmitter tx_en=%x for port %x " 8553 "mode = %x\n", tx_en, port, tx_en_mode); 8554 switch (tx_en_mode) { 8555 case PORT_HW_CFG_TX_LASER_MDIO: 8556 8557 elink_cl45_read(cb, phy, 8558 MDIO_PMA_DEVAD, 8559 MDIO_PMA_REG_PHY_IDENTIFIER, 8560 &val); 8561 8562 if (tx_en) 8563 val &= ~(1<<15); 8564 else 8565 val |= (1<<15); 8566 8567 elink_cl45_write(cb, phy, 8568 MDIO_PMA_DEVAD, 8569 MDIO_PMA_REG_PHY_IDENTIFIER, 8570 val); 8571 break; 8572 case PORT_HW_CFG_TX_LASER_GPIO0: 8573 case PORT_HW_CFG_TX_LASER_GPIO1: 8574 case PORT_HW_CFG_TX_LASER_GPIO2: 8575 case PORT_HW_CFG_TX_LASER_GPIO3: 8576 { 8577 u16 gpio_pin; 8578 u8 gpio_port, gpio_mode; 8579 if (tx_en) 8580 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 8581 else 8582 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 8583 8584 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 8585 gpio_port = elink_get_gpio_port(params); 8586 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 8587 break; 8588 } 8589 default: 8590 ELINK_DEBUG_P1(cb, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 8591 break; 8592 } 8593 } 8594 #endif /* !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) */ 8595 8596 static void elink_sfp_set_transmitter(struct elink_params *params, 8597 struct elink_phy *phy, 8598 u8 tx_en) 8599 { 8600 #ifdef ELINK_ENHANCEMENTS 8601 struct elink_dev *cb = params->cb; 8602 ELINK_DEBUG_P1(cb, "Setting SFP+ transmitter to %d\n", tx_en); 8603 #endif // ELINK_ENHANCEMENTS 8604 #ifndef EXCLUDE_WARPCORE 8605 if (CHIP_IS_E3(params->chip_id)) 8606 elink_sfp_e3_set_transmitter(params, phy, tx_en); 8607 #endif // EXCLUDE_WARPCORE 8608 #ifdef ELINK_ENHANCEMENTS 8609 else 8610 #endif // ELINK_ENHANCEMENTS 8611 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 8612 elink_sfp_e1e2_set_transmitter(params, phy, tx_en); 8613 #endif 8614 } 8615 8616 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, 8617 struct elink_params *params, 8618 u8 dev_addr, u16 addr, u8 byte_cnt, 8619 u8 *o_buf, u8 is_init) 8620 { 8621 #ifndef EXCLUDE_BCM87x6 8622 struct elink_dev *cb = params->cb; 8623 u16 val = 0; 8624 u16 i; 8625 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8626 ELINK_DEBUG_P0(cb, 8627 "Reading from eeprom is limited to 0xf\n"); 8628 return ELINK_STATUS_ERROR; 8629 } 8630 /* Set the read command byte count */ 8631 elink_cl45_write(cb, phy, 8632 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8633 (byte_cnt | (dev_addr << 8))); 8634 8635 /* Set the read command address */ 8636 elink_cl45_write(cb, phy, 8637 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8638 addr); 8639 8640 /* Activate read command */ 8641 elink_cl45_write(cb, phy, 8642 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8643 0x2c0f); 8644 8645 /* Wait up to 500us for command complete status */ 8646 for (i = 0; i < 100; i++) { 8647 elink_cl45_read(cb, phy, 8648 MDIO_PMA_DEVAD, 8649 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8650 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8651 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8652 break; 8653 USLEEP(cb, 5); 8654 } 8655 8656 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8657 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8658 ELINK_DEBUG_P1(cb, 8659 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8660 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8661 return ELINK_STATUS_ERROR; 8662 } 8663 8664 /* Read the buffer */ 8665 for (i = 0; i < byte_cnt; i++) { 8666 elink_cl45_read(cb, phy, 8667 MDIO_PMA_DEVAD, 8668 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 8669 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 8670 } 8671 8672 for (i = 0; i < 100; i++) { 8673 elink_cl45_read(cb, phy, 8674 MDIO_PMA_DEVAD, 8675 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8676 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8677 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8678 return ELINK_STATUS_OK; 8679 MSLEEP(cb, 1); 8680 } 8681 #endif // EXCLUDE_BCM87x6 8682 return ELINK_STATUS_ERROR; 8683 } 8684 8685 #ifndef EXCLUDE_WARPCORE 8686 #ifndef EXCLUDE_NON_COMMON_INIT 8687 static void elink_warpcore_power_module(struct elink_params *params, 8688 u8 power) 8689 { 8690 u32 pin_cfg; 8691 struct elink_dev *cb = params->cb; 8692 8693 pin_cfg = (REG_RD(cb, params->shmem_base + 8694 OFFSETOF(struct shmem_region, 8695 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 8696 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 8697 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 8698 8699 if (pin_cfg == PIN_CFG_NA) 8700 return; 8701 ELINK_DEBUG_P2(cb, "Setting SFP+ module power to %d using pin cfg %d\n", 8702 power, pin_cfg); 8703 /* Low ==> corresponding SFP+ module is powered 8704 * high ==> the SFP+ module is powered down 8705 */ 8706 elink_set_cfg_pin(cb, pin_cfg, power ^ 1); 8707 } 8708 #endif 8709 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy, 8710 struct elink_params *params, 8711 u8 dev_addr, 8712 u16 addr, u8 byte_cnt, 8713 u8 *o_buf, u8 is_init) 8714 { 8715 elink_status_t rc = ELINK_STATUS_OK; 8716 u8 i, j = 0, cnt = 0; 8717 u32 data_array[4]; 8718 u16 addr32; 8719 struct elink_dev *cb = params->cb; 8720 8721 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8722 ELINK_DEBUG_P0(cb, 8723 "Reading from eeprom is limited to 16 bytes\n"); 8724 return ELINK_STATUS_ERROR; 8725 } 8726 8727 /* 4 byte aligned address */ 8728 addr32 = addr & (~0x3); 8729 do { 8730 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 8731 elink_warpcore_power_module(params, 0); 8732 /* Note that 100us are not enough here */ 8733 MSLEEP(cb, 1); 8734 elink_warpcore_power_module(params, 1); 8735 } 8736 rc = elink_bsc_read(params, cb, dev_addr, addr32, 0, byte_cnt, 8737 data_array); 8738 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); 8739 8740 if (rc == ELINK_STATUS_OK) { 8741 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 8742 o_buf[j] = *((u8 *)data_array + i); 8743 j++; 8744 } 8745 } 8746 8747 return rc; 8748 } 8749 #endif /* EXCLUDE_WARPCORE */ 8750 8751 #ifndef EXCLUDE_BCM8727_BCM8073 8752 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, 8753 struct elink_params *params, 8754 u8 dev_addr, u16 addr, u8 byte_cnt, 8755 u8 *o_buf, u8 is_init) 8756 { 8757 struct elink_dev *cb = params->cb; 8758 u16 val, i; 8759 8760 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8761 ELINK_DEBUG_P0(cb, 8762 "Reading from eeprom is limited to 0xf\n"); 8763 return ELINK_STATUS_ERROR; 8764 } 8765 8766 /* Set 2-wire transfer rate of SFP+ module EEPROM 8767 * to 100Khz since some DACs(direct attached cables) do 8768 * not work at 400Khz. 8769 */ 8770 elink_cl45_write(cb, phy, 8771 MDIO_PMA_DEVAD, 8772 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8773 ((dev_addr << 8) | 1)); 8774 8775 /* Need to read from 1.8000 to clear it */ 8776 elink_cl45_read(cb, phy, 8777 MDIO_PMA_DEVAD, 8778 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8779 &val); 8780 8781 /* Set the read command byte count */ 8782 elink_cl45_write(cb, phy, 8783 MDIO_PMA_DEVAD, 8784 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8785 ((byte_cnt < 2) ? 2 : byte_cnt)); 8786 8787 /* Set the read command address */ 8788 elink_cl45_write(cb, phy, 8789 MDIO_PMA_DEVAD, 8790 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8791 addr); 8792 /* Set the destination address */ 8793 elink_cl45_write(cb, phy, 8794 MDIO_PMA_DEVAD, 8795 0x8004, 8796 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8797 8798 /* Activate read command */ 8799 elink_cl45_write(cb, phy, 8800 MDIO_PMA_DEVAD, 8801 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8802 0x8002); 8803 /* Wait appropriate time for two-wire command to finish before 8804 * polling the status register 8805 */ 8806 MSLEEP(cb, 1); 8807 8808 /* Wait up to 500us for command complete status */ 8809 for (i = 0; i < 100; i++) { 8810 elink_cl45_read(cb, phy, 8811 MDIO_PMA_DEVAD, 8812 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8813 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8814 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8815 break; 8816 USLEEP(cb, 5); 8817 } 8818 8819 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8820 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8821 ELINK_DEBUG_P1(cb, 8822 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8823 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8824 return ELINK_STATUS_TIMEOUT; 8825 } 8826 8827 /* Read the buffer */ 8828 for (i = 0; i < byte_cnt; i++) { 8829 elink_cl45_read(cb, phy, 8830 MDIO_PMA_DEVAD, 8831 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8832 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8833 } 8834 8835 for (i = 0; i < 100; i++) { 8836 elink_cl45_read(cb, phy, 8837 MDIO_PMA_DEVAD, 8838 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8839 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8840 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8841 return ELINK_STATUS_OK; 8842 MSLEEP(cb, 1); 8843 } 8844 8845 return ELINK_STATUS_ERROR; 8846 } 8847 #endif /* EXCLUDE_BCM8727_BCM8073 */ 8848 #endif /* #ifndef EXCLUDE_NON_COMMON_INIT */ 8849 #endif /* ELINK_EMUL_ONLY */ 8850 #ifndef EXCLUDE_FROM_BNX2X 8851 elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf) 8852 { 8853 u8 i, checksum = 0; 8854 for (i = 0; i < ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE; i++) 8855 checksum += sfp_a2_buf[i]; 8856 if (checksum == sfp_a2_buf[ELINK_SFP_EEPROM_A2_CC_DMI_ADDR]) 8857 return ELINK_STATUS_OK; 8858 8859 return ELINK_STATUS_ERROR; 8860 } 8861 #endif 8862 #ifndef EXCLUDE_NON_COMMON_INIT 8863 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 8864 struct elink_params *params, u8 dev_addr, 8865 u16 addr, u16 byte_cnt, u8 *o_buf) 8866 { 8867 elink_status_t rc = 0; 8868 #ifdef ELINK_DEBUG 8869 struct elink_dev *cb = params->cb; 8870 #endif 8871 u8 xfer_size; 8872 u8 *user_data = o_buf; 8873 read_sfp_module_eeprom_func_p read_func; 8874 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8875 ELINK_DEBUG_P1(cb, "invalid dev_addr 0x%x\n", dev_addr); 8876 return ELINK_STATUS_ERROR; 8877 } 8878 8879 #ifndef ELINK_EMUL_ONLY 8880 switch (phy->type) { 8881 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8882 read_func = elink_8726_read_sfp_module_eeprom; 8883 break; 8884 #ifndef EXCLUDE_BCM8727_BCM8073 8885 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8886 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8887 read_func = elink_8727_read_sfp_module_eeprom; 8888 break; 8889 #endif 8890 #ifndef EXCLUDE_WARPCORE 8891 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8892 read_func = elink_warpcore_read_sfp_module_eeprom; 8893 break; 8894 #endif /* EXCLUDE_WARPCORE */ 8895 default: 8896 return ELINK_OP_NOT_SUPPORTED; 8897 } 8898 8899 while (!rc && (byte_cnt > 0)) { 8900 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? 8901 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; 8902 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8903 user_data, 0); 8904 byte_cnt -= xfer_size; 8905 user_data += xfer_size; 8906 addr += xfer_size; 8907 } 8908 #endif /* ELINK_EMUL_ONLY */ 8909 return rc; 8910 } 8911 #endif // EXCLUDE_NON_COMMON_INIT 8912 #ifndef ELINK_EMUL_ONLY 8913 8914 #ifndef EXCLUDE_NON_COMMON_INIT 8915 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) 8916 static elink_status_t elink_get_edc_mode(struct elink_phy *phy, 8917 struct elink_params *params, 8918 u16 *edc_mode) 8919 { 8920 struct elink_dev *cb = params->cb; 8921 u32 sync_offset = 0, phy_idx, media_types; 8922 u8 val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; 8923 *edc_mode = ELINK_EDC_MODE_LIMITING; 8924 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; 8925 /* First check for copper cable */ 8926 if (elink_read_sfp_module_eeprom(phy, 8927 params, 8928 ELINK_I2C_DEV_ADDR_A0, 8929 0, 8930 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1, 8931 (u8 *)val) != 0) { 8932 ELINK_DEBUG_P0(cb, "Failed to read from SFP+ module EEPROM\n"); 8933 return ELINK_STATUS_ERROR; 8934 } 8935 #ifndef EXCLUDE_WARPCORE 8936 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK; 8937 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] << 8938 LINK_SFP_EEPROM_COMP_CODE_SHIFT; 8939 elink_update_link_attr(params, params->link_attr_sync); 8940 #endif 8941 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) { 8942 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: 8943 { 8944 u8 copper_module_type; 8945 phy->media_type = ELINK_ETH_PHY_DA_TWINAX; 8946 /* Check if its active cable (includes SFP+ module) 8947 * of passive cable 8948 */ 8949 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR]; 8950 if (copper_module_type & 8951 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8952 ELINK_DEBUG_P0(cb, "Active Copper cable detected\n"); 8953 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8954 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; 8955 else 8956 check_limiting_mode = 1; 8957 } else { 8958 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC; 8959 /* Even in case PASSIVE_DAC indication is not set, 8960 * treat it as a passive DAC cable, since some cables 8961 * don't have this indication. 8962 */ 8963 if (copper_module_type & 8964 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8965 ELINK_DEBUG_P0(cb, 8966 "Passive Copper cable detected\n"); 8967 } else { 8968 ELINK_DEBUG_P0(cb, 8969 "Unknown copper-cable-type\n"); 8970 } 8971 } 8972 break; 8973 } 8974 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN: 8975 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: 8976 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: 8977 check_limiting_mode = 1; 8978 /* Module is considered as 1G in case it's NOT compliant with 8979 * any 10G ethernet protocol. 8980 */ 8981 if ((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] & 8982 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK | 8983 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK | 8984 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) { 8985 ELINK_DEBUG_P0(cb, "1G SFP module detected\n"); 8986 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; 8987 if (phy->req_line_speed != ELINK_SPEED_1000) { 8988 #ifndef ELINK_AUX_POWER 8989 u8 gport = params->port; 8990 #endif 8991 phy->req_line_speed = ELINK_SPEED_1000; 8992 #ifndef ELINK_AUX_POWER 8993 if (!CHIP_IS_E1X(params->chip_id)) { 8994 gport = PATH_ID(cb) + 8995 (params->port << 1); 8996 } 8997 elink_cb_event_log(cb, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." 8998 // " Current SFP module in port %d is not" 8999 // " compliant with 10G Ethernet\n", 9000 #endif 9001 } 9002 9003 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] & 9004 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) { 9005 /* Some 1G-baseT modules will not link up, 9006 * unless TX_EN is toggled with long delay in 9007 * between. 9008 */ 9009 elink_sfp_set_transmitter(params, phy, 0); 9010 MSLEEP(cb, 40); 9011 elink_sfp_set_transmitter(params, phy, 1); 9012 } 9013 } else { 9014 int idx, cfg_idx = 0; 9015 ELINK_DEBUG_P0(cb, "10G Optic module detected\n"); 9016 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { 9017 if (params->phy[idx].type == phy->type) { 9018 cfg_idx = ELINK_LINK_CONFIG_IDX(idx); 9019 break; 9020 } 9021 } 9022 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 9023 phy->req_line_speed = params->req_line_speed[cfg_idx]; 9024 } 9025 break; 9026 default: 9027 ELINK_DEBUG_P1(cb, "Unable to determine module type 0x%x !!!\n", 9028 val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]); 9029 return ELINK_STATUS_ERROR; 9030 } 9031 sync_offset = params->shmem_base + 9032 OFFSETOF(struct shmem_region, 9033 dev_info.port_hw_config[params->port].media_type); 9034 media_types = REG_RD(cb, sync_offset); 9035 /* Update media type for non-PMF sync */ 9036 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 9037 if (&(params->phy[phy_idx]) == phy) { 9038 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 9039 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9040 media_types |= ((phy->media_type & 9041 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 9042 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 9043 break; 9044 } 9045 } 9046 REG_WR(cb, sync_offset, media_types); 9047 if (check_limiting_mode) { 9048 u8 options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; 9049 if (elink_read_sfp_module_eeprom(phy, 9050 params, 9051 ELINK_I2C_DEV_ADDR_A0, 9052 ELINK_SFP_EEPROM_OPTIONS_ADDR, 9053 ELINK_SFP_EEPROM_OPTIONS_SIZE, 9054 options) != 0) { 9055 ELINK_DEBUG_P0(cb, 9056 "Failed to read Option field from module EEPROM\n"); 9057 return ELINK_STATUS_ERROR; 9058 } 9059 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 9060 *edc_mode = ELINK_EDC_MODE_LINEAR; 9061 else 9062 *edc_mode = ELINK_EDC_MODE_LIMITING; 9063 } 9064 ELINK_DEBUG_P1(cb, "EDC mode is set to 0x%x\n", *edc_mode); 9065 return ELINK_STATUS_OK; 9066 } 9067 #ifdef ELINK_ENHANCEMENTS 9068 /* This function read the relevant field from the module (SFP+), and verify it 9069 * is compliant with this board 9070 */ 9071 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, 9072 struct elink_params *params) 9073 { 9074 struct elink_dev *cb = params->cb; 9075 u32 val, cmd; 9076 u32 fw_resp, fw_cmd_param; 9077 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1]; 9078 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1]; 9079 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; 9080 val = REG_RD(cb, params->shmem_base + 9081 OFFSETOF(struct shmem_region, dev_info. 9082 port_feature_config[params->port].config)); 9083 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9084 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 9085 ELINK_DEBUG_P0(cb, "NOT enforcing module verification\n"); 9086 return ELINK_STATUS_OK; 9087 } 9088 9089 if (params->feature_config_flags & 9090 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 9091 /* Use specific phy request */ 9092 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 9093 } else if (params->feature_config_flags & 9094 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 9095 /* Use first phy request only in case of non-dual media*/ 9096 if (ELINK_DUAL_MEDIA(params)) { 9097 ELINK_DEBUG_P0(cb, 9098 "FW does not support OPT MDL verification\n"); 9099 return ELINK_STATUS_ERROR; 9100 } 9101 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 9102 } else { 9103 /* No support in OPT MDL detection */ 9104 ELINK_DEBUG_P0(cb, 9105 "FW does not support OPT MDL verification\n"); 9106 return ELINK_STATUS_ERROR; 9107 } 9108 9109 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 9110 fw_resp = elink_cb_fw_command(cb, cmd, fw_cmd_param); 9111 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 9112 ELINK_DEBUG_P0(cb, "Approved module\n"); 9113 return ELINK_STATUS_OK; 9114 } 9115 9116 /* Format the warning message */ 9117 if (elink_read_sfp_module_eeprom(phy, 9118 params, 9119 ELINK_I2C_DEV_ADDR_A0, 9120 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, 9121 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, 9122 (u8 *)vendor_name)) 9123 vendor_name[0] = '\0'; 9124 else 9125 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 9126 if (elink_read_sfp_module_eeprom(phy, 9127 params, 9128 ELINK_I2C_DEV_ADDR_A0, 9129 ELINK_SFP_EEPROM_PART_NO_ADDR, 9130 ELINK_SFP_EEPROM_PART_NO_SIZE, 9131 (u8 *)vendor_pn)) 9132 vendor_pn[0] = '\0'; 9133 else 9134 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; 9135 9136 elink_cb_event_log(cb, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," 9137 // " Port %d from %s part number %s\n", 9138 9139 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 9140 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 9141 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; 9142 return ELINK_STATUS_ERROR; 9143 } 9144 #endif /* ELINK_ENHANCEMENTS */ 9145 9146 #ifndef EXCLUDE_BCM8727_BCM8073 9147 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy, 9148 struct elink_params *params) 9149 9150 { 9151 u8 val; 9152 elink_status_t rc; 9153 struct elink_dev *cb = params->cb; 9154 u16 timeout; 9155 /* Initialization time after hot-plug may take up to 300ms for 9156 * some phys type ( e.g. JDSU ) 9157 */ 9158 9159 for (timeout = 0; timeout < 60; timeout++) { 9160 #ifndef EXCLUDE_WARPCORE 9161 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9162 rc = elink_warpcore_read_sfp_module_eeprom( 9163 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val, 9164 1); 9165 else 9166 #endif 9167 rc = elink_read_sfp_module_eeprom(phy, params, 9168 ELINK_I2C_DEV_ADDR_A0, 9169 1, 1, &val); 9170 if (rc == 0) { 9171 ELINK_DEBUG_P1(cb, 9172 "SFP+ module initialization took %d ms\n", 9173 timeout * 5); 9174 return ELINK_STATUS_OK; 9175 } 9176 MSLEEP(cb, 5); 9177 } 9178 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 9179 1, 1, &val); 9180 return rc; 9181 } 9182 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9183 #endif /* #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) || !defined(EXCLUDE_WARPCORE) */ 9184 9185 #ifndef EXCLUDE_BCM8727_BCM8073 9186 static void elink_8727_power_module(struct elink_dev *cb, 9187 struct elink_phy *phy, 9188 u8 is_power_up) { 9189 /* Make sure GPIOs are not using for LED mode */ 9190 u16 val; 9191 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 9192 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 9193 * output 9194 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 9195 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 9196 * where the 1st bit is the over-current(only input), and 2nd bit is 9197 * for power( only output ) 9198 * 9199 * In case of NOC feature is disabled and power is up, set GPIO control 9200 * as input to enable listening of over-current indication 9201 */ 9202 if (phy->flags & ELINK_FLAGS_NOC) 9203 return; 9204 if (is_power_up) 9205 val = (1<<4); 9206 else 9207 /* Set GPIO control to OUTPUT, and set the power bit 9208 * to according to the is_power_up 9209 */ 9210 val = (1<<1); 9211 9212 elink_cl45_write(cb, phy, 9213 MDIO_PMA_DEVAD, 9214 MDIO_PMA_REG_8727_GPIO_CTRL, 9215 val); 9216 } 9217 #endif /* EXCLUDE_BCM8727_BCM8073 */ 9218 9219 #ifndef EXCLUDE_BCM87x6 9220 static elink_status_t elink_8726_set_limiting_mode(struct elink_dev *cb, 9221 struct elink_phy *phy, 9222 u16 edc_mode) 9223 { 9224 u16 cur_limiting_mode; 9225 9226 elink_cl45_read(cb, phy, 9227 MDIO_PMA_DEVAD, 9228 MDIO_PMA_REG_ROM_VER2, 9229 &cur_limiting_mode); 9230 ELINK_DEBUG_P1(cb, "Current Limiting mode is 0x%x\n", 9231 cur_limiting_mode); 9232 9233 if (edc_mode == ELINK_EDC_MODE_LIMITING) { 9234 ELINK_DEBUG_P0(cb, "Setting LIMITING MODE\n"); 9235 elink_cl45_write(cb, phy, 9236 MDIO_PMA_DEVAD, 9237 MDIO_PMA_REG_ROM_VER2, 9238 ELINK_EDC_MODE_LIMITING); 9239 } else { /* LRM mode ( default )*/ 9240 9241 ELINK_DEBUG_P0(cb, "Setting LRM MODE\n"); 9242 9243 /* Changing to LRM mode takes quite few seconds. So do it only 9244 * if current mode is limiting (default is LRM) 9245 */ 9246 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) 9247 return ELINK_STATUS_OK; 9248 9249 elink_cl45_write(cb, phy, 9250 MDIO_PMA_DEVAD, 9251 MDIO_PMA_REG_LRM_MODE, 9252 0); 9253 elink_cl45_write(cb, phy, 9254 MDIO_PMA_DEVAD, 9255 MDIO_PMA_REG_ROM_VER2, 9256 0x128); 9257 elink_cl45_write(cb, phy, 9258 MDIO_PMA_DEVAD, 9259 MDIO_PMA_REG_MISC_CTRL0, 9260 0x4008); 9261 elink_cl45_write(cb, phy, 9262 MDIO_PMA_DEVAD, 9263 MDIO_PMA_REG_LRM_MODE, 9264 0xaaaa); 9265 } 9266 return ELINK_STATUS_OK; 9267 } 9268 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9269 9270 #ifndef EXCLUDE_BCM8727_BCM8073 9271 static elink_status_t elink_8727_set_limiting_mode(struct elink_dev *cb, 9272 struct elink_phy *phy, 9273 u16 edc_mode) 9274 { 9275 u16 phy_identifier; 9276 u16 rom_ver2_val; 9277 elink_cl45_read(cb, phy, 9278 MDIO_PMA_DEVAD, 9279 MDIO_PMA_REG_PHY_IDENTIFIER, 9280 &phy_identifier); 9281 9282 elink_cl45_write(cb, phy, 9283 MDIO_PMA_DEVAD, 9284 MDIO_PMA_REG_PHY_IDENTIFIER, 9285 (phy_identifier & ~(1<<9))); 9286 9287 elink_cl45_read(cb, phy, 9288 MDIO_PMA_DEVAD, 9289 MDIO_PMA_REG_ROM_VER2, 9290 &rom_ver2_val); 9291 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 9292 elink_cl45_write(cb, phy, 9293 MDIO_PMA_DEVAD, 9294 MDIO_PMA_REG_ROM_VER2, 9295 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 9296 9297 elink_cl45_write(cb, phy, 9298 MDIO_PMA_DEVAD, 9299 MDIO_PMA_REG_PHY_IDENTIFIER, 9300 (phy_identifier | (1<<9))); 9301 9302 return ELINK_STATUS_OK; 9303 } 9304 9305 static void elink_8727_specific_func(struct elink_phy *phy, 9306 struct elink_params *params, 9307 u32 action) 9308 { 9309 struct elink_dev *cb = params->cb; 9310 u16 val; 9311 switch (action) { 9312 case ELINK_DISABLE_TX: 9313 elink_sfp_set_transmitter(params, phy, 0); 9314 break; 9315 case ELINK_ENABLE_TX: 9316 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) 9317 elink_sfp_set_transmitter(params, phy, 1); 9318 break; 9319 case ELINK_PHY_INIT: 9320 elink_cl45_write(cb, phy, 9321 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9322 (1<<2) | (1<<5)); 9323 elink_cl45_write(cb, phy, 9324 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9325 0); 9326 elink_cl45_write(cb, phy, 9327 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 9328 /* Make MOD_ABS give interrupt on change */ 9329 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9330 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9331 &val); 9332 val |= (1<<12); 9333 if (phy->flags & ELINK_FLAGS_NOC) 9334 val |= (3<<5); 9335 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 9336 * status which reflect SFP+ module over-current 9337 */ 9338 if (!(phy->flags & ELINK_FLAGS_NOC)) 9339 val &= 0xff8f; /* Reset bits 4-6 */ 9340 elink_cl45_write(cb, phy, 9341 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9342 val); 9343 break; 9344 default: 9345 ELINK_DEBUG_P1(cb, "Function 0x%x not supported by 8727\n", 9346 action); 9347 return; 9348 } 9349 } 9350 9351 #ifdef ELINK_ENHANCEMENTS 9352 static void elink_set_e1e2_module_fault_led(struct elink_params *params, 9353 u8 gpio_mode) 9354 { 9355 struct elink_dev *cb = params->cb; 9356 9357 u32 fault_led_gpio = REG_RD(cb, params->shmem_base + 9358 OFFSETOF(struct shmem_region, 9359 dev_info.port_hw_config[params->port].sfp_ctrl)) & 9360 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 9361 switch (fault_led_gpio) { 9362 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 9363 return; 9364 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 9365 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 9366 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 9367 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 9368 { 9369 u8 gpio_port = elink_get_gpio_port(params); 9370 u16 gpio_pin = fault_led_gpio - 9371 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 9372 ELINK_DEBUG_P3(cb, "Set fault module-detected led " 9373 "pin %x port %x mode %x\n", 9374 gpio_pin, gpio_port, gpio_mode); 9375 ELINK_SET_GPIO(cb, gpio_pin, gpio_mode, gpio_port); 9376 } 9377 break; 9378 default: 9379 ELINK_DEBUG_P1(cb, "Error: Invalid fault led mode 0x%x\n", 9380 fault_led_gpio); 9381 } 9382 } 9383 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9384 #endif // EXCLUDE_BCM8727_BCM8073 9385 #endif // EXCLUDE_NON_COMMON_INIT 9386 9387 #ifdef ELINK_ENHANCEMENTS 9388 static void elink_set_e3_module_fault_led(struct elink_params *params, 9389 u8 gpio_mode) 9390 { 9391 u32 pin_cfg; 9392 u8 port = params->port; 9393 struct elink_dev *cb = params->cb; 9394 pin_cfg = (REG_RD(cb, params->shmem_base + 9395 OFFSETOF(struct shmem_region, 9396 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 9397 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 9398 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 9399 ELINK_DEBUG_P2(cb, "Setting Fault LED to %d using pin cfg %d\n", 9400 gpio_mode, pin_cfg); 9401 elink_set_cfg_pin(cb, pin_cfg, gpio_mode); 9402 } 9403 9404 static void elink_set_sfp_module_fault_led(struct elink_params *params, 9405 u8 gpio_mode) 9406 { 9407 struct elink_dev *cb = params->cb; 9408 ELINK_DEBUG_P1(cb, "Setting SFP+ module fault LED to %d\n", gpio_mode); 9409 if (CHIP_IS_E3(params->chip_id)) { 9410 /* Low ==> if SFP+ module is supported otherwise 9411 * High ==> if SFP+ module is not on the approved vendor list 9412 */ 9413 elink_set_e3_module_fault_led(params, gpio_mode); 9414 } else 9415 elink_set_e1e2_module_fault_led(params, gpio_mode); 9416 } 9417 #endif /* #ifdef ELINK_ENHANCEMENTS */ 9418 9419 #ifndef EXCLUDE_WARPCORE 9420 #ifndef EXCLUDE_NON_COMMON_INIT 9421 static void elink_warpcore_hw_reset(struct elink_phy *phy, 9422 struct elink_params *params) 9423 { 9424 struct elink_dev *cb = params->cb; 9425 elink_warpcore_power_module(params, 0); 9426 /* Put Warpcore in low power mode */ 9427 REG_WR(cb, MISC_REG_WC0_RESET, 0x0c0e); 9428 9429 /* Put LCPLL in low power mode */ 9430 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 1); 9431 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 9432 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 9433 } 9434 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 9435 #endif // #ifndef EXCLUDE_WARPCORE 9436 9437 #ifndef EXCLUDE_NON_COMMON_INIT 9438 static void elink_power_sfp_module(struct elink_params *params, 9439 struct elink_phy *phy, 9440 u8 power) 9441 { 9442 #ifdef ELINK_DEBUG 9443 struct elink_dev *cb = params->cb; 9444 #endif /* ELINK_DEBUG */ 9445 ELINK_DEBUG_P1(cb, "Setting SFP+ power to %x\n", power); 9446 9447 switch (phy->type) { 9448 #ifndef EXCLUDE_BCM8727_BCM8073 9449 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9450 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9451 elink_8727_power_module(params->cb, phy, power); 9452 break; 9453 #endif // EXCLUDE_BCM8727_BCM8073 9454 #ifndef EXCLUDE_WARPCORE 9455 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9456 elink_warpcore_power_module(params, power); 9457 break; 9458 #endif // EXCLUDE_WARPCORE 9459 default: 9460 break; 9461 } 9462 } 9463 #ifndef EXCLUDE_WARPCORE 9464 static void elink_warpcore_set_limiting_mode(struct elink_params *params, 9465 struct elink_phy *phy, 9466 u16 edc_mode) 9467 { 9468 u16 val = 0; 9469 u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9470 struct elink_dev *cb = params->cb; 9471 9472 u8 lane = elink_get_warpcore_lane(phy, params); 9473 /* This is a global register which controls all lanes */ 9474 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9475 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9476 val &= ~(0xf << (lane << 2)); 9477 9478 switch (edc_mode) { 9479 case ELINK_EDC_MODE_LINEAR: 9480 case ELINK_EDC_MODE_LIMITING: 9481 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9482 break; 9483 case ELINK_EDC_MODE_PASSIVE_DAC: 9484 case ELINK_EDC_MODE_ACTIVE_DAC: 9485 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 9486 break; 9487 default: 9488 break; 9489 } 9490 9491 val |= (mode << (lane << 2)); 9492 elink_cl45_write(cb, phy, MDIO_WC_DEVAD, 9493 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 9494 /* A must read */ 9495 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 9496 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9497 9498 /* Restart microcode to re-read the new mode */ 9499 elink_warpcore_reset_lane(cb, phy, 1); 9500 elink_warpcore_reset_lane(cb, phy, 0); 9501 9502 } 9503 #endif // EXCLUDE_WARPCORE 9504 9505 static void elink_set_limiting_mode(struct elink_params *params, 9506 struct elink_phy *phy, 9507 u16 edc_mode) 9508 { 9509 switch (phy->type) { 9510 #ifndef EXCLUDE_BCM87x6 9511 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 9512 elink_8726_set_limiting_mode(params->cb, phy, edc_mode); 9513 break; 9514 #endif /* #ifndef EXCLUDE_BCM87x6 */ 9515 #ifndef EXCLUDE_BCM8727_BCM8073 9516 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9517 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9518 elink_8727_set_limiting_mode(params->cb, phy, edc_mode); 9519 break; 9520 #endif // EXCLUDE_BCM8727_BCM8073 9521 #ifndef EXCLUDE_WARPCORE 9522 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9523 elink_warpcore_set_limiting_mode(params, phy, edc_mode); 9524 break; 9525 #endif // EXCLUDE_WARPCORE 9526 } 9527 } 9528 9529 elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 9530 struct elink_params *params) 9531 { 9532 struct elink_dev *cb = params->cb; 9533 u16 edc_mode; 9534 elink_status_t rc = ELINK_STATUS_OK; 9535 9536 u32 val = REG_RD(cb, params->shmem_base + 9537 OFFSETOF(struct shmem_region, dev_info. 9538 port_feature_config[params->port].config)); 9539 /* Enabled transmitter by default */ 9540 elink_sfp_set_transmitter(params, phy, 1); 9541 ELINK_DEBUG_P1(cb, "SFP+ module plugged in/out detected on port %d\n", 9542 params->port); 9543 /* Power up module */ 9544 elink_power_sfp_module(params, phy, 1); 9545 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { 9546 ELINK_DEBUG_P0(cb, "Failed to get valid module type\n"); 9547 return ELINK_STATUS_ERROR; 9548 #ifdef ELINK_ENHANCEMENTS 9549 } else if (elink_verify_sfp_module(phy, params) != 0) { 9550 /* Check SFP+ module compatibility */ 9551 ELINK_DEBUG_P0(cb, "Module verification failed!!\n"); 9552 rc = ELINK_STATUS_ERROR; 9553 /* Turn on fault module-detected led */ 9554 elink_set_sfp_module_fault_led(params, 9555 MISC_REGISTERS_GPIO_HIGH); 9556 9557 /* Check if need to power down the SFP+ module */ 9558 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9559 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 9560 ELINK_DEBUG_P0(cb, "Shutdown SFP+ module!!\n"); 9561 elink_power_sfp_module(params, phy, 0); 9562 return rc; 9563 } 9564 } else { 9565 /* Turn off fault module-detected led */ 9566 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 9567 #endif // ELINK_ENHANCEMENTS 9568 } 9569 9570 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 9571 * is done automatically 9572 */ 9573 elink_set_limiting_mode(params, phy, edc_mode); 9574 9575 /* Disable transmit for this module if the module is not approved, and 9576 * laser needs to be disabled. 9577 */ 9578 if ((rc != 0) && 9579 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9580 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 9581 elink_sfp_set_transmitter(params, phy, 0); 9582 9583 return rc; 9584 } 9585 #endif // EXCLUDE_NON_COMMON_INIT 9586 9587 #ifdef ELINK_ENHANCEMENTS 9588 void elink_handle_module_detect_int(struct elink_params *params) 9589 { 9590 struct elink_dev *cb = params->cb; 9591 struct elink_phy *phy; 9592 u32 gpio_val; 9593 u8 gpio_num, gpio_port; 9594 if (CHIP_IS_E3(params->chip_id)) { 9595 phy = ¶ms->phy[ELINK_INT_PHY]; 9596 /* Always enable TX laser,will be disabled in case of fault */ 9597 elink_sfp_set_transmitter(params, phy, 1); 9598 } else { 9599 phy = ¶ms->phy[ELINK_EXT_PHY1]; 9600 } 9601 if (elink_get_mod_abs_int_cfg(cb, params->chip_id, params->shmem_base, 9602 params->port, &gpio_num, &gpio_port) == 9603 ELINK_STATUS_ERROR) { 9604 ELINK_DEBUG_P0(cb, "Failed to get MOD_ABS interrupt config\n"); 9605 return; 9606 } 9607 9608 /* Set valid module led off */ 9609 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 9610 9611 /* Get current gpio val reflecting module plugged in / out*/ 9612 gpio_val = ELINK_GET_GPIO(cb, gpio_num, gpio_port); 9613 9614 /* Call the handling function in case module is detected */ 9615 if (gpio_val == 0) { 9616 #ifdef ELINK_AUX_POWER 9617 phy->flags |= ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9618 #endif 9619 elink_set_mdio_emac_per_phy(cb, params); 9620 elink_set_aer_mmd(params, phy); 9621 9622 elink_power_sfp_module(params, phy, 1); 9623 ELINK_SET_GPIO_INT(cb, gpio_num, 9624 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 9625 gpio_port); 9626 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { 9627 elink_sfp_module_detection(phy, params); 9628 if (CHIP_IS_E3(params->chip_id)) { 9629 u16 rx_tx_in_reset; 9630 /* In case WC is out of reset, reconfigure the 9631 * link speed while taking into account 1G 9632 * module limitation. 9633 */ 9634 elink_cl45_read(cb, phy, 9635 MDIO_WC_DEVAD, 9636 MDIO_WC_REG_DIGITAL5_MISC6, 9637 &rx_tx_in_reset); 9638 if ((!rx_tx_in_reset) && 9639 (params->link_flags & 9640 ELINK_PHY_INITIALIZED)) { 9641 elink_warpcore_reset_lane(cb, phy, 1); 9642 elink_warpcore_config_sfi(phy, params); 9643 elink_warpcore_reset_lane(cb, phy, 0); 9644 } 9645 } 9646 } else { 9647 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 9648 } 9649 } else { 9650 #ifdef ELINK_AUX_POWER 9651 phy->flags &= ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 9652 #endif 9653 ELINK_SET_GPIO_INT(cb, gpio_num, 9654 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 9655 gpio_port); 9656 /* Module was plugged out. 9657 * Disable transmit for this module 9658 */ 9659 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 9660 } 9661 } 9662 #endif // ELINK_ENHANCEMENTS 9663 9664 /******************************************************************/ 9665 /* Used by 8706 and 8727 */ 9666 /******************************************************************/ 9667 #ifndef EXCLUDE_NON_COMMON_INIT 9668 #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073) 9669 static void elink_sfp_mask_fault(struct elink_dev *cb, 9670 struct elink_phy *phy, 9671 u16 alarm_status_offset, 9672 u16 alarm_ctrl_offset) 9673 { 9674 u16 alarm_status, val; 9675 elink_cl45_read(cb, phy, 9676 MDIO_PMA_DEVAD, alarm_status_offset, 9677 &alarm_status); 9678 elink_cl45_read(cb, phy, 9679 MDIO_PMA_DEVAD, alarm_status_offset, 9680 &alarm_status); 9681 /* Mask or enable the fault event. */ 9682 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 9683 if (alarm_status & (1<<0)) 9684 val &= ~(1<<0); 9685 else 9686 val |= (1<<0); 9687 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 9688 } 9689 #endif // #if !defined(EXCLUDE_BCM87x6) || !defined(EXCLUDE_BCM8727_BCM8073 9690 /******************************************************************/ 9691 /* common BCM8706/BCM8726 PHY SECTION */ 9692 /******************************************************************/ 9693 #ifndef EXCLUDE_BCM87x6 9694 static u8 elink_8706_8726_read_status(struct elink_phy *phy, 9695 struct elink_params *params, 9696 struct elink_vars *vars) 9697 { 9698 u8 link_up = 0; 9699 u16 val1, val2, rx_sd, pcs_status; 9700 struct elink_dev *cb = params->cb; 9701 ELINK_DEBUG_P0(cb, "XGXS 8706/8726\n"); 9702 /* Clear RX Alarm*/ 9703 elink_cl45_read(cb, phy, 9704 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 9705 9706 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 9707 MDIO_PMA_LASI_TXCTRL); 9708 9709 /* Clear LASI indication*/ 9710 elink_cl45_read(cb, phy, 9711 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9712 elink_cl45_read(cb, phy, 9713 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 9714 ELINK_DEBUG_P2(cb, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 9715 9716 elink_cl45_read(cb, phy, 9717 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 9718 elink_cl45_read(cb, phy, 9719 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 9720 elink_cl45_read(cb, phy, 9721 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9722 elink_cl45_read(cb, phy, 9723 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9724 9725 ELINK_DEBUG_P3(cb, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 9726 " link_status 0x%x\n", rx_sd, pcs_status, val2); 9727 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 9728 * are set, or if the autoneg bit 1 is set 9729 */ 9730 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 9731 if (link_up) { 9732 if (val2 & (1<<1)) 9733 vars->line_speed = ELINK_SPEED_1000; 9734 else 9735 vars->line_speed = ELINK_SPEED_10000; 9736 elink_ext_phy_resolve_fc(phy, params, vars); 9737 vars->duplex = DUPLEX_FULL; 9738 } 9739 9740 /* Capture 10G link fault. Read twice to clear stale value. */ 9741 if (vars->line_speed == ELINK_SPEED_10000) { 9742 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9743 MDIO_PMA_LASI_TXSTAT, &val1); 9744 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 9745 MDIO_PMA_LASI_TXSTAT, &val1); 9746 if (val1 & (1<<0)) 9747 vars->fault_detected = 1; 9748 } 9749 9750 return link_up; 9751 } 9752 9753 /******************************************************************/ 9754 /* BCM8706 PHY SECTION */ 9755 /******************************************************************/ 9756 static elink_status_t 9757 elink_8706_config_init(struct elink_phy *phy, struct elink_params *params, 9758 struct elink_vars *vars) 9759 { 9760 u32 tx_en_mode; 9761 u16 cnt, val, tmp1; 9762 struct elink_dev *cb = params->cb; 9763 9764 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 9765 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9766 /* HW reset */ 9767 elink_ext_phy_hw_reset(cb, params->port); 9768 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 9769 elink_wait_reset_complete(cb, phy, params); 9770 9771 /* Wait until fw is loaded */ 9772 for (cnt = 0; cnt < 100; cnt++) { 9773 elink_cl45_read(cb, phy, 9774 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 9775 if (val) 9776 break; 9777 MSLEEP(cb, 10); 9778 } 9779 ELINK_DEBUG_P1(cb, "XGXS 8706 is initialized after %d ms\n", cnt); 9780 if ((params->feature_config_flags & 9781 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9782 u8 i; 9783 u16 reg; 9784 for (i = 0; i < 4; i++) { 9785 reg = MDIO_XS_8706_REG_BANK_RX0 + 9786 i*(MDIO_XS_8706_REG_BANK_RX1 - 9787 MDIO_XS_8706_REG_BANK_RX0); 9788 elink_cl45_read(cb, phy, MDIO_XS_DEVAD, reg, &val); 9789 /* Clear first 3 bits of the control */ 9790 val &= ~0x7; 9791 /* Set control bits according to configuration */ 9792 val |= (phy->rx_preemphasis[i] & 0x7); 9793 ELINK_DEBUG_P2(cb, "Setting RX Equalizer to BCM8706" 9794 " reg 0x%x <-- val 0x%x\n", reg, val); 9795 elink_cl45_write(cb, phy, MDIO_XS_DEVAD, reg, val); 9796 } 9797 } 9798 /* Force speed */ 9799 if (phy->req_line_speed == ELINK_SPEED_10000) { 9800 ELINK_DEBUG_P0(cb, "XGXS 8706 force 10Gbps\n"); 9801 9802 elink_cl45_write(cb, phy, 9803 MDIO_PMA_DEVAD, 9804 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 9805 elink_cl45_write(cb, phy, 9806 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9807 0); 9808 /* Arm LASI for link and Tx fault. */ 9809 elink_cl45_write(cb, phy, 9810 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 9811 } else { 9812 /* Force 1Gbps using autoneg with 1G advertisement */ 9813 9814 /* Allow CL37 through CL73 */ 9815 ELINK_DEBUG_P0(cb, "XGXS 8706 AutoNeg\n"); 9816 elink_cl45_write(cb, phy, 9817 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9818 9819 /* Enable Full-Duplex advertisement on CL37 */ 9820 elink_cl45_write(cb, phy, 9821 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 9822 /* Enable CL37 AN */ 9823 elink_cl45_write(cb, phy, 9824 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9825 /* 1G support */ 9826 elink_cl45_write(cb, phy, 9827 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 9828 9829 /* Enable clause 73 AN */ 9830 elink_cl45_write(cb, phy, 9831 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9832 elink_cl45_write(cb, phy, 9833 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9834 0x0400); 9835 elink_cl45_write(cb, phy, 9836 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9837 0x0004); 9838 } 9839 elink_save_bcm_spirom_ver(cb, phy, params->port); 9840 9841 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9842 * power mode, if TX Laser is disabled 9843 */ 9844 9845 tx_en_mode = REG_RD(cb, params->shmem_base + 9846 OFFSETOF(struct shmem_region, 9847 dev_info.port_hw_config[params->port].sfp_ctrl)) 9848 & PORT_HW_CFG_TX_LASER_MASK; 9849 9850 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9851 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 9852 elink_cl45_read(cb, phy, 9853 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 9854 tmp1 |= 0x1; 9855 elink_cl45_write(cb, phy, 9856 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 9857 } 9858 9859 return ELINK_STATUS_OK; 9860 } 9861 9862 static elink_status_t 9863 elink_8706_read_status(struct elink_phy *phy, struct elink_params *params, 9864 struct elink_vars *vars) 9865 { 9866 return elink_8706_8726_read_status(phy, params, vars); 9867 } 9868 9869 /******************************************************************/ 9870 /* BCM8726 PHY SECTION */ 9871 /******************************************************************/ 9872 static void elink_8726_config_loopback(struct elink_phy *phy, 9873 struct elink_params *params) 9874 { 9875 struct elink_dev *cb = params->cb; 9876 ELINK_DEBUG_P0(cb, "PMA/PMD ext_phy_loopback: 8726\n"); 9877 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9878 } 9879 9880 static void elink_8726_external_rom_boot(struct elink_phy *phy, 9881 struct elink_params *params) 9882 { 9883 struct elink_dev *cb = params->cb; 9884 /* Need to wait 100ms after reset */ 9885 MSLEEP(cb, 100); 9886 9887 /* Micro controller re-boot */ 9888 elink_cl45_write(cb, phy, 9889 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9890 9891 /* Set soft reset */ 9892 elink_cl45_write(cb, phy, 9893 MDIO_PMA_DEVAD, 9894 MDIO_PMA_REG_GEN_CTRL, 9895 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9896 9897 elink_cl45_write(cb, phy, 9898 MDIO_PMA_DEVAD, 9899 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9900 9901 elink_cl45_write(cb, phy, 9902 MDIO_PMA_DEVAD, 9903 MDIO_PMA_REG_GEN_CTRL, 9904 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9905 9906 /* Wait for 150ms for microcode load */ 9907 MSLEEP(cb, 150); 9908 9909 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9910 elink_cl45_write(cb, phy, 9911 MDIO_PMA_DEVAD, 9912 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9913 9914 MSLEEP(cb, 200); 9915 elink_save_bcm_spirom_ver(cb, phy, params->port); 9916 } 9917 9918 static elink_status_t 9919 elink_8726_read_status(struct elink_phy *phy, struct elink_params *params, 9920 struct elink_vars *vars) 9921 { 9922 struct elink_dev *cb = params->cb; 9923 u16 val1; 9924 u8 link_up = elink_8706_8726_read_status(phy, params, vars); 9925 if (link_up) { 9926 elink_cl45_read(cb, phy, 9927 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9928 &val1); 9929 if (val1 & (1<<15)) { 9930 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 9931 link_up = 0; 9932 vars->line_speed = 0; 9933 } 9934 } 9935 return link_up; 9936 } 9937 9938 9939 static elink_status_t 9940 elink_8726_config_init(struct elink_phy *phy, struct elink_params *params, 9941 struct elink_vars *vars) 9942 { 9943 struct elink_dev *cb = params->cb; 9944 ELINK_DEBUG_P0(cb, "Initializing BCM8726\n"); 9945 9946 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9947 elink_wait_reset_complete(cb, phy, params); 9948 9949 elink_8726_external_rom_boot(phy, params); 9950 9951 /* Need to call module detected on initialization since the module 9952 * detection triggered by actual module insertion might occur before 9953 * driver is loaded, and when driver is loaded, it reset all 9954 * registers, including the transmitter 9955 */ 9956 elink_sfp_module_detection(phy, params); 9957 9958 if (phy->req_line_speed == ELINK_SPEED_1000) { 9959 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 9960 elink_cl45_write(cb, phy, 9961 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9962 elink_cl45_write(cb, phy, 9963 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9964 elink_cl45_write(cb, phy, 9965 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9966 elink_cl45_write(cb, phy, 9967 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9968 0x400); 9969 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 9970 (phy->speed_cap_mask & 9971 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9972 ((phy->speed_cap_mask & 9973 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9974 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9975 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 9976 /* Set Flow control */ 9977 elink_ext_phy_set_pause(params, phy, vars); 9978 elink_cl45_write(cb, phy, 9979 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9980 elink_cl45_write(cb, phy, 9981 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9982 elink_cl45_write(cb, phy, 9983 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9984 elink_cl45_write(cb, phy, 9985 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9986 elink_cl45_write(cb, phy, 9987 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9988 /* Enable RX-ALARM control to receive interrupt for 1G speed 9989 * change 9990 */ 9991 elink_cl45_write(cb, phy, 9992 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9993 elink_cl45_write(cb, phy, 9994 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9995 0x400); 9996 9997 } else { /* Default 10G. Set only LASI control */ 9998 elink_cl45_write(cb, phy, 9999 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 10000 } 10001 10002 /* Set TX PreEmphasis if needed */ 10003 if ((params->feature_config_flags & 10004 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10005 ELINK_DEBUG_P2(cb, 10006 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10007 phy->tx_preemphasis[0], 10008 phy->tx_preemphasis[1]); 10009 elink_cl45_write(cb, phy, 10010 MDIO_PMA_DEVAD, 10011 MDIO_PMA_REG_8726_TX_CTRL1, 10012 phy->tx_preemphasis[0]); 10013 10014 elink_cl45_write(cb, phy, 10015 MDIO_PMA_DEVAD, 10016 MDIO_PMA_REG_8726_TX_CTRL2, 10017 phy->tx_preemphasis[1]); 10018 } 10019 10020 return ELINK_STATUS_OK; 10021 10022 } 10023 10024 static void elink_8726_link_reset(struct elink_phy *phy, 10025 struct elink_params *params) 10026 { 10027 #ifndef EXCLUDE_LINK_RESET 10028 struct elink_dev *cb = params->cb; 10029 ELINK_DEBUG_P1(cb, "elink_8726_link_reset port %d\n", params->port); 10030 /* Set serial boot control for external load */ 10031 elink_cl45_write(cb, phy, 10032 MDIO_PMA_DEVAD, 10033 MDIO_PMA_REG_GEN_CTRL, 0x0001); 10034 #endif // EXCLUDE_LINK_RESET 10035 } 10036 #endif /* #ifndef EXCLUDE_BCM87x6 */ 10037 10038 /******************************************************************/ 10039 /* BCM8727 PHY SECTION */ 10040 /******************************************************************/ 10041 10042 #ifndef EXCLUDE_BCM8727_BCM8073 10043 static void elink_8727_set_link_led(struct elink_phy *phy, 10044 struct elink_params *params, u8 mode) 10045 { 10046 struct elink_dev *cb = params->cb; 10047 u16 led_mode_bitmask = 0; 10048 u16 gpio_pins_bitmask = 0; 10049 u16 val; 10050 /* Only NOC flavor requires to set the LED specifically */ 10051 if (!(phy->flags & ELINK_FLAGS_NOC)) 10052 return; 10053 switch (mode) { 10054 case ELINK_LED_MODE_FRONT_PANEL_OFF: 10055 case ELINK_LED_MODE_OFF: 10056 led_mode_bitmask = 0; 10057 gpio_pins_bitmask = 0x03; 10058 break; 10059 case ELINK_LED_MODE_ON: 10060 led_mode_bitmask = 0; 10061 gpio_pins_bitmask = 0x02; 10062 break; 10063 case ELINK_LED_MODE_OPER: 10064 led_mode_bitmask = 0x60; 10065 gpio_pins_bitmask = 0x11; 10066 break; 10067 } 10068 elink_cl45_read(cb, phy, 10069 MDIO_PMA_DEVAD, 10070 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10071 &val); 10072 val &= 0xff8f; 10073 val |= led_mode_bitmask; 10074 elink_cl45_write(cb, phy, 10075 MDIO_PMA_DEVAD, 10076 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 10077 val); 10078 elink_cl45_read(cb, phy, 10079 MDIO_PMA_DEVAD, 10080 MDIO_PMA_REG_8727_GPIO_CTRL, 10081 &val); 10082 val &= 0xffe0; 10083 val |= gpio_pins_bitmask; 10084 elink_cl45_write(cb, phy, 10085 MDIO_PMA_DEVAD, 10086 MDIO_PMA_REG_8727_GPIO_CTRL, 10087 val); 10088 } 10089 static void elink_8727_hw_reset(struct elink_phy *phy, 10090 struct elink_params *params) { 10091 u32 swap_val, swap_override; 10092 u8 port; 10093 /* The PHY reset is controlled by GPIO 1. Fake the port number 10094 * to cancel the swap done in set_gpio() 10095 */ 10096 struct elink_dev *cb = params->cb; 10097 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 10098 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 10099 port = (swap_val && swap_override) ^ 1; 10100 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_1, 10101 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 10102 } 10103 10104 static void elink_8727_config_speed(struct elink_phy *phy, 10105 struct elink_params *params) 10106 { 10107 struct elink_dev *cb = params->cb; 10108 u16 tmp1, val; 10109 /* Set option 1G speed */ 10110 if ((phy->req_line_speed == ELINK_SPEED_1000) || 10111 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { 10112 ELINK_DEBUG_P0(cb, "Setting 1G force\n"); 10113 elink_cl45_write(cb, phy, 10114 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 10115 elink_cl45_write(cb, phy, 10116 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 10117 elink_cl45_read(cb, phy, 10118 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 10119 ELINK_DEBUG_P1(cb, "1.7 = 0x%x\n", tmp1); 10120 /* Power down the XAUI until link is up in case of dual-media 10121 * and 1G 10122 */ 10123 if (ELINK_DUAL_MEDIA(params)) { 10124 elink_cl45_read(cb, phy, 10125 MDIO_PMA_DEVAD, 10126 MDIO_PMA_REG_8727_PCS_GP, &val); 10127 val |= (3<<10); 10128 elink_cl45_write(cb, phy, 10129 MDIO_PMA_DEVAD, 10130 MDIO_PMA_REG_8727_PCS_GP, val); 10131 } 10132 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10133 ((phy->speed_cap_mask & 10134 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 10135 ((phy->speed_cap_mask & 10136 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 10137 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 10138 10139 ELINK_DEBUG_P0(cb, "Setting 1G clause37\n"); 10140 elink_cl45_write(cb, phy, 10141 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 10142 elink_cl45_write(cb, phy, 10143 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 10144 } else { 10145 /* Since the 8727 has only single reset pin, need to set the 10G 10146 * registers although it is default 10147 */ 10148 elink_cl45_write(cb, phy, 10149 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 10150 0x0020); 10151 elink_cl45_write(cb, phy, 10152 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 10153 elink_cl45_write(cb, phy, 10154 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 10155 elink_cl45_write(cb, phy, 10156 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 10157 0x0008); 10158 } 10159 } 10160 10161 static elink_status_t 10162 elink_8727_config_init(struct elink_phy *phy, struct elink_params *params, 10163 struct elink_vars *vars) 10164 { 10165 u32 tx_en_mode; 10166 u16 tmp1, mod_abs, tmp2; 10167 struct elink_dev *cb = params->cb; 10168 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 10169 10170 elink_wait_reset_complete(cb, phy, params); 10171 10172 ELINK_DEBUG_P0(cb, "Initializing BCM8727\n"); 10173 10174 elink_8727_specific_func(phy, params, ELINK_PHY_INIT); 10175 /* Initially configure MOD_ABS to interrupt when module is 10176 * presence( bit 8) 10177 */ 10178 elink_cl45_read(cb, phy, 10179 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10180 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 10181 * When the EDC is off it locks onto a reference clock and avoids 10182 * becoming 'lost' 10183 */ 10184 mod_abs &= ~(1<<8); 10185 if (!(phy->flags & ELINK_FLAGS_NOC)) 10186 mod_abs &= ~(1<<9); 10187 elink_cl45_write(cb, phy, 10188 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10189 10190 /* Enable/Disable PHY transmitter output */ 10191 elink_set_disable_pmd_transmit(params, phy, 0); 10192 10193 elink_8727_power_module(cb, phy, 1); 10194 10195 elink_cl45_read(cb, phy, 10196 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 10197 10198 elink_cl45_read(cb, phy, 10199 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 10200 10201 elink_8727_config_speed(phy, params); 10202 10203 10204 /* Set TX PreEmphasis if needed */ 10205 if ((params->feature_config_flags & 10206 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10207 ELINK_DEBUG_P2(cb, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10208 phy->tx_preemphasis[0], 10209 phy->tx_preemphasis[1]); 10210 elink_cl45_write(cb, phy, 10211 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 10212 phy->tx_preemphasis[0]); 10213 10214 elink_cl45_write(cb, phy, 10215 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 10216 phy->tx_preemphasis[1]); 10217 } 10218 10219 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 10220 * power mode, if TX Laser is disabled 10221 */ 10222 tx_en_mode = REG_RD(cb, params->shmem_base + 10223 OFFSETOF(struct shmem_region, 10224 dev_info.port_hw_config[params->port].sfp_ctrl)) 10225 & PORT_HW_CFG_TX_LASER_MASK; 10226 10227 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 10228 10229 ELINK_DEBUG_P0(cb, "Enabling TXONOFF_PWRDN_DIS\n"); 10230 elink_cl45_read(cb, phy, 10231 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 10232 tmp2 |= 0x1000; 10233 tmp2 &= 0xFFEF; 10234 elink_cl45_write(cb, phy, 10235 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 10236 elink_cl45_read(cb, phy, 10237 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10238 &tmp2); 10239 elink_cl45_write(cb, phy, 10240 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10241 (tmp2 & 0x7fff)); 10242 } 10243 10244 return ELINK_STATUS_OK; 10245 } 10246 10247 static void elink_8727_handle_mod_abs(struct elink_phy *phy, 10248 struct elink_params *params) 10249 { 10250 struct elink_dev *cb = params->cb; 10251 u16 mod_abs, rx_alarm_status; 10252 u32 val = REG_RD(cb, params->shmem_base + 10253 OFFSETOF(struct shmem_region, dev_info. 10254 port_feature_config[params->port]. 10255 config)); 10256 elink_cl45_read(cb, phy, 10257 MDIO_PMA_DEVAD, 10258 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10259 if (mod_abs & (1<<8)) { 10260 10261 /* Module is absent */ 10262 ELINK_DEBUG_P0(cb, 10263 "MOD_ABS indication show module is absent\n"); 10264 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 10265 /* 1. Set mod_abs to detect next module 10266 * presence event 10267 * 2. Set EDC off by setting OPTXLOS signal input to low 10268 * (bit 9). 10269 * When the EDC is off it locks onto a reference clock and 10270 * avoids becoming 'lost'. 10271 */ 10272 mod_abs &= ~(1<<8); 10273 if (!(phy->flags & ELINK_FLAGS_NOC)) 10274 mod_abs &= ~(1<<9); 10275 elink_cl45_write(cb, phy, 10276 MDIO_PMA_DEVAD, 10277 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10278 10279 /* Clear RX alarm since it stays up as long as 10280 * the mod_abs wasn't changed 10281 */ 10282 elink_cl45_read(cb, phy, 10283 MDIO_PMA_DEVAD, 10284 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10285 10286 } else { 10287 /* Module is present */ 10288 ELINK_DEBUG_P0(cb, 10289 "MOD_ABS indication show module is present\n"); 10290 /* First disable transmitter, and if the module is ok, the 10291 * module_detection will enable it 10292 * 1. Set mod_abs to detect next module absent event ( bit 8) 10293 * 2. Restore the default polarity of the OPRXLOS signal and 10294 * this signal will then correctly indicate the presence or 10295 * absence of the Rx signal. (bit 9) 10296 */ 10297 mod_abs |= (1<<8); 10298 if (!(phy->flags & ELINK_FLAGS_NOC)) 10299 mod_abs |= (1<<9); 10300 elink_cl45_write(cb, phy, 10301 MDIO_PMA_DEVAD, 10302 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10303 10304 /* Clear RX alarm since it stays up as long as the mod_abs 10305 * wasn't changed. This is need to be done before calling the 10306 * module detection, otherwise it will clear* the link update 10307 * alarm 10308 */ 10309 elink_cl45_read(cb, phy, 10310 MDIO_PMA_DEVAD, 10311 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10312 10313 10314 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 10315 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 10316 elink_sfp_set_transmitter(params, phy, 0); 10317 10318 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) 10319 elink_sfp_module_detection(phy, params); 10320 else 10321 ELINK_DEBUG_P0(cb, "SFP+ module is not initialized\n"); 10322 10323 /* Reconfigure link speed based on module type limitations */ 10324 elink_8727_config_speed(phy, params); 10325 } 10326 10327 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", 10328 rx_alarm_status); 10329 /* No need to check link status in case of module plugged in/out */ 10330 } 10331 10332 static elink_status_t 10333 elink_8727_read_status(struct elink_phy *phy, struct elink_params *params, 10334 struct elink_vars *vars) 10335 { 10336 struct elink_dev *cb = params->cb; 10337 u8 link_up = 0; 10338 u16 link_status = 0; 10339 u16 rx_alarm_status, lasi_ctrl, val1; 10340 10341 /* If PHY is not initialized, do not check link status */ 10342 elink_cl45_read(cb, phy, 10343 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 10344 &lasi_ctrl); 10345 if (!lasi_ctrl) 10346 return 0; 10347 10348 /* Check the LASI on Rx */ 10349 elink_cl45_read(cb, phy, 10350 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 10351 &rx_alarm_status); 10352 vars->line_speed = 0; 10353 ELINK_DEBUG_P1(cb, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 10354 10355 elink_sfp_mask_fault(cb, phy, MDIO_PMA_LASI_TXSTAT, 10356 MDIO_PMA_LASI_TXCTRL); 10357 10358 elink_cl45_read(cb, phy, 10359 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10360 10361 ELINK_DEBUG_P1(cb, "8727 LASI status 0x%x\n", val1); 10362 10363 /* Clear MSG-OUT */ 10364 elink_cl45_read(cb, phy, 10365 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 10366 10367 /* If a module is present and there is need to check 10368 * for over current 10369 */ 10370 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 10371 /* Check over-current using 8727 GPIO0 input*/ 10372 elink_cl45_read(cb, phy, 10373 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 10374 &val1); 10375 10376 if ((val1 & (1<<8)) == 0) { 10377 #ifndef ELINK_AUX_POWER 10378 u8 oc_port = params->port; 10379 if (!CHIP_IS_E1X(params->chip_id)) 10380 oc_port = PATH_ID(cb) + (params->port << 1); 10381 ELINK_DEBUG_P1(cb, 10382 "8727 Power fault has been detected on port %d\n", 10383 oc_port); 10384 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " 10385 // "been detected and the power to " 10386 // "that SFP+ module has been removed " 10387 // "to prevent failure of the card. " 10388 // "Please remove the SFP+ module and " 10389 // "restart the system to clear this " 10390 // "error.\n", 10391 #endif 10392 /* Disable all RX_ALARMs except for mod_abs */ 10393 elink_cl45_write(cb, phy, 10394 MDIO_PMA_DEVAD, 10395 MDIO_PMA_LASI_RXCTRL, (1<<5)); 10396 10397 elink_cl45_read(cb, phy, 10398 MDIO_PMA_DEVAD, 10399 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 10400 /* Wait for module_absent_event */ 10401 val1 |= (1<<8); 10402 elink_cl45_write(cb, phy, 10403 MDIO_PMA_DEVAD, 10404 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 10405 /* Clear RX alarm */ 10406 elink_cl45_read(cb, phy, 10407 MDIO_PMA_DEVAD, 10408 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10409 elink_8727_power_module(params->cb, phy, 0); 10410 return 0; 10411 } 10412 } /* Over current check */ 10413 10414 /* When module absent bit is set, check module */ 10415 if (rx_alarm_status & (1<<5)) { 10416 elink_8727_handle_mod_abs(phy, params); 10417 /* Enable all mod_abs and link detection bits */ 10418 elink_cl45_write(cb, phy, 10419 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10420 ((1<<5) | (1<<2))); 10421 } 10422 10423 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 10424 ELINK_DEBUG_P0(cb, "Enabling 8727 TX laser\n"); 10425 elink_sfp_set_transmitter(params, phy, 1); 10426 } else { 10427 ELINK_DEBUG_P0(cb, "Tx is disabled\n"); 10428 return 0; 10429 } 10430 10431 elink_cl45_read(cb, phy, 10432 MDIO_PMA_DEVAD, 10433 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 10434 10435 /* Bits 0..2 --> speed detected, 10436 * Bits 13..15--> link is down 10437 */ 10438 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 10439 link_up = 1; 10440 vars->line_speed = ELINK_SPEED_10000; 10441 ELINK_DEBUG_P1(cb, "port %x: External link up in 10G\n", 10442 params->port); 10443 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 10444 link_up = 1; 10445 vars->line_speed = ELINK_SPEED_1000; 10446 ELINK_DEBUG_P1(cb, "port %x: External link up in 1G\n", 10447 params->port); 10448 } else { 10449 link_up = 0; 10450 ELINK_DEBUG_P1(cb, "port %x: External link is down\n", 10451 params->port); 10452 } 10453 10454 /* Capture 10G link fault. */ 10455 if (vars->line_speed == ELINK_SPEED_10000) { 10456 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10457 MDIO_PMA_LASI_TXSTAT, &val1); 10458 10459 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 10460 MDIO_PMA_LASI_TXSTAT, &val1); 10461 10462 if (val1 & (1<<0)) { 10463 vars->fault_detected = 1; 10464 } 10465 } 10466 10467 if (link_up) { 10468 elink_ext_phy_resolve_fc(phy, params, vars); 10469 vars->duplex = DUPLEX_FULL; 10470 ELINK_DEBUG_P1(cb, "duplex = 0x%x\n", vars->duplex); 10471 } 10472 10473 if ((ELINK_DUAL_MEDIA(params)) && 10474 (phy->req_line_speed == ELINK_SPEED_1000)) { 10475 elink_cl45_read(cb, phy, 10476 MDIO_PMA_DEVAD, 10477 MDIO_PMA_REG_8727_PCS_GP, &val1); 10478 /* In case of dual-media board and 1G, power up the XAUI side, 10479 * otherwise power it down. For 10G it is done automatically 10480 */ 10481 if (link_up) 10482 val1 &= ~(3<<10); 10483 else 10484 val1 |= (3<<10); 10485 elink_cl45_write(cb, phy, 10486 MDIO_PMA_DEVAD, 10487 MDIO_PMA_REG_8727_PCS_GP, val1); 10488 } 10489 return link_up; 10490 } 10491 10492 static void elink_8727_link_reset(struct elink_phy *phy, 10493 struct elink_params *params) 10494 { 10495 #ifndef EXCLUDE_LINK_RESET 10496 struct elink_dev *cb = params->cb; 10497 10498 /* Enable/Disable PHY transmitter output */ 10499 elink_set_disable_pmd_transmit(params, phy, 1); 10500 10501 /* Disable Transmitter */ 10502 elink_sfp_set_transmitter(params, phy, 0); 10503 /* Clear LASI */ 10504 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 10505 10506 #endif // EXCLUDE_LINK_RESET 10507 } 10508 #endif /* EXCLUDE_BCM8727_BCM8073 */ 10509 #endif // EXCLUDE_NON_COMMON_INIT 10510 10511 /******************************************************************/ 10512 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 10513 /******************************************************************/ 10514 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10515 static void elink_save_848xx_spirom_version(struct elink_phy *phy, 10516 struct elink_dev *cb, 10517 u8 port) 10518 { 10519 #ifndef EXCLUDE_BCM8481 10520 u16 val, fw_ver2, cnt, i; 10521 static struct elink_reg_set reg_set[] = { 10522 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 10523 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 10524 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 10525 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 10526 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 10527 }; 10528 #endif 10529 u16 fw_ver1; 10530 10531 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10532 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10533 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 10534 elink_save_spirom_version(cb, port, fw_ver1 & 0xfff, 10535 phy->ver_addr); 10536 } else { 10537 #ifndef EXCLUDE_BCM8481 10538 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 10539 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 10540 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10541 elink_cl45_write(cb, phy, reg_set[i].devad, 10542 reg_set[i].reg, reg_set[i].val); 10543 10544 for (cnt = 0; cnt < 100; cnt++) { 10545 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10546 if (val & 1) 10547 break; 10548 USLEEP(cb, 5); 10549 } 10550 if (cnt == 100) { 10551 ELINK_DEBUG_P0(cb, "Unable to read 848xx " 10552 "phy fw version(1)\n"); 10553 elink_save_spirom_version(cb, port, 0, 10554 phy->ver_addr); 10555 return; 10556 } 10557 10558 10559 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 10560 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 10561 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 10562 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 10563 for (cnt = 0; cnt < 100; cnt++) { 10564 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10565 if (val & 1) 10566 break; 10567 USLEEP(cb, 5); 10568 } 10569 if (cnt == 100) { 10570 ELINK_DEBUG_P0(cb, "Unable to read 848xx phy fw " 10571 "version(2)\n"); 10572 elink_save_spirom_version(cb, port, 0, 10573 phy->ver_addr); 10574 return; 10575 } 10576 10577 /* lower 16 bits of the register SPI_FW_STATUS */ 10578 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 10579 /* upper 16 bits of register SPI_FW_STATUS */ 10580 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 10581 10582 elink_save_spirom_version(cb, port, (fw_ver2<<16) | fw_ver1, 10583 phy->ver_addr); 10584 #endif /* EXCLUDE_BCM8481 */ 10585 } 10586 10587 } 10588 #ifndef EXCLUDE_NON_COMMON_INIT 10589 static void elink_848xx_set_led(struct elink_dev *cb, 10590 struct elink_phy *phy) 10591 { 10592 u16 val, offset, i; 10593 static struct elink_reg_set reg_set[] = { 10594 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 10595 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 10596 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 10597 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 10598 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 10599 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 10600 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 10601 }; 10602 /* PHYC_CTL_LED_CTL */ 10603 elink_cl45_read(cb, phy, 10604 MDIO_PMA_DEVAD, 10605 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 10606 val &= 0xFE00; 10607 val |= 0x0092; 10608 10609 elink_cl45_write(cb, phy, 10610 MDIO_PMA_DEVAD, 10611 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 10612 10613 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10614 elink_cl45_write(cb, phy, reg_set[i].devad, reg_set[i].reg, 10615 reg_set[i].val); 10616 10617 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10618 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10619 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 10620 else 10621 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 10622 10623 /* stretch_en for LED3*/ 10624 elink_cl45_read_or_write(cb, phy, 10625 MDIO_PMA_DEVAD, offset, 10626 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 10627 } 10628 10629 static void elink_848xx_specific_func(struct elink_phy *phy, 10630 struct elink_params *params, 10631 u32 action) 10632 { 10633 struct elink_dev *cb = params->cb; 10634 switch (action) { 10635 case ELINK_PHY_INIT: 10636 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10637 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10638 /* Save spirom version */ 10639 elink_save_848xx_spirom_version(phy, cb, params->port); 10640 } 10641 /* This phy uses the NIG latch mechanism since link indication 10642 * arrives through its LED4 and not via its LASI signal, so we 10643 * get steady signal instead of clear on read 10644 */ 10645 elink_bits_en(cb, NIG_REG_LATCH_BC_0 + params->port*4, 10646 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 10647 10648 elink_848xx_set_led(cb, phy); 10649 break; 10650 } 10651 } 10652 10653 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, 10654 struct elink_params *params, 10655 struct elink_vars *vars) 10656 { 10657 struct elink_dev *cb = params->cb; 10658 u16 autoneg_val, an_1000_val, an_10_100_val; 10659 10660 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); 10661 elink_cl45_write(cb, phy, 10662 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 10663 10664 /* set 1000 speed advertisement */ 10665 elink_cl45_read(cb, phy, 10666 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10667 &an_1000_val); 10668 10669 elink_ext_phy_set_pause(params, phy, vars); 10670 elink_cl45_read(cb, phy, 10671 MDIO_AN_DEVAD, 10672 MDIO_AN_REG_8481_LEGACY_AN_ADV, 10673 &an_10_100_val); 10674 elink_cl45_read(cb, phy, 10675 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10676 &autoneg_val); 10677 /* Disable forced speed */ 10678 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10679 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 10680 10681 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10682 (phy->speed_cap_mask & 10683 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10684 (phy->req_line_speed == ELINK_SPEED_1000)) { 10685 an_1000_val |= (1<<8); 10686 autoneg_val |= (1<<9 | 1<<12); 10687 if (phy->req_duplex == DUPLEX_FULL) 10688 an_1000_val |= (1<<9); 10689 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 10690 } else 10691 an_1000_val &= ~((1<<8) | (1<<9)); 10692 10693 elink_cl45_write(cb, phy, 10694 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10695 an_1000_val); 10696 10697 /* Set 10/100 speed advertisement */ 10698 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 10699 if (phy->speed_cap_mask & 10700 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10701 /* Enable autoneg and restart autoneg for legacy speeds 10702 */ 10703 autoneg_val |= (1<<9 | 1<<12); 10704 an_10_100_val |= (1<<8); 10705 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 10706 } 10707 10708 if (phy->speed_cap_mask & 10709 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10710 /* Enable autoneg and restart autoneg for legacy speeds 10711 */ 10712 autoneg_val |= (1<<9 | 1<<12); 10713 an_10_100_val |= (1<<7); 10714 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 10715 } 10716 10717 if ((phy->speed_cap_mask & 10718 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 10719 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { 10720 an_10_100_val |= (1<<6); 10721 autoneg_val |= (1<<9 | 1<<12); 10722 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 10723 } 10724 10725 if ((phy->speed_cap_mask & 10726 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 10727 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { 10728 an_10_100_val |= (1<<5); 10729 autoneg_val |= (1<<9 | 1<<12); 10730 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 10731 } 10732 } 10733 10734 /* Only 10/100 are allowed to work in FORCE mode */ 10735 if ((phy->req_line_speed == ELINK_SPEED_100) && 10736 (phy->supported & 10737 (ELINK_SUPPORTED_100baseT_Half | 10738 ELINK_SUPPORTED_100baseT_Full))) { 10739 autoneg_val |= (1<<13); 10740 /* Enabled AUTO-MDIX when autoneg is disabled */ 10741 elink_cl45_write(cb, phy, 10742 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10743 (1<<15 | 1<<9 | 7<<0)); 10744 /* The PHY needs this set even for forced link. */ 10745 an_10_100_val |= (1<<8) | (1<<7); 10746 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 10747 } 10748 if ((phy->req_line_speed == ELINK_SPEED_10) && 10749 (phy->supported & 10750 (ELINK_SUPPORTED_10baseT_Half | 10751 ELINK_SUPPORTED_10baseT_Full))) { 10752 /* Enabled AUTO-MDIX when autoneg is disabled */ 10753 elink_cl45_write(cb, phy, 10754 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10755 (1<<15 | 1<<9 | 7<<0)); 10756 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 10757 } 10758 10759 elink_cl45_write(cb, phy, 10760 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 10761 an_10_100_val); 10762 10763 if (phy->req_duplex == DUPLEX_FULL) 10764 autoneg_val |= (1<<8); 10765 10766 /* Always write this if this is not 84833/4. 10767 * For 84833/4, write it only when it's a forced speed. 10768 */ 10769 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10770 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 10771 ((autoneg_val & (1<<12)) == 0)) 10772 elink_cl45_write(cb, phy, 10773 MDIO_AN_DEVAD, 10774 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 10775 10776 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10777 (phy->speed_cap_mask & 10778 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 10779 (phy->req_line_speed == ELINK_SPEED_10000)) { 10780 ELINK_DEBUG_P0(cb, "Advertising 10G\n"); 10781 /* Restart autoneg for 10G*/ 10782 10783 elink_cl45_read_or_write( 10784 cb, phy, 10785 MDIO_AN_DEVAD, 10786 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10787 0x1000); 10788 elink_cl45_write(cb, phy, 10789 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 10790 0x3200); 10791 } else 10792 elink_cl45_write(cb, phy, 10793 MDIO_AN_DEVAD, 10794 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10795 1); 10796 10797 return ELINK_STATUS_OK; 10798 } 10799 #endif // EXCLUDE_NON_COMMON_INIT 10800 #endif // #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 10801 10802 #ifndef EXCLUDE_BCM8481 10803 #ifndef EXCLUDE_NON_COMMON_INIT 10804 static elink_status_t 10805 elink_8481_config_init(struct elink_phy *phy, struct elink_params *params, 10806 struct elink_vars *vars) 10807 { 10808 struct elink_dev *cb = params->cb; 10809 /* Restore normal power mode*/ 10810 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 10811 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10812 10813 /* HW reset */ 10814 elink_ext_phy_hw_reset(cb, params->port); 10815 elink_wait_reset_complete(cb, phy, params); 10816 10817 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 10818 return elink_848xx_cmn_config_init(phy, params, vars); 10819 } 10820 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 10821 #endif // EXCLUDE_BCM8481 10822 10823 #ifndef EXCLUDE_BCM84833 10824 #define PHY84833_CMDHDLR_WAIT 300 10825 #define PHY84833_CMDHDLR_MAX_ARGS 5 10826 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, 10827 struct elink_params *params, u16 fw_cmd, 10828 u16 cmd_args[], int argc) 10829 { 10830 int idx; 10831 u16 val; 10832 struct elink_dev *cb = params->cb; 10833 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10834 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10835 MDIO_84833_CMD_HDLR_STATUS, 10836 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10837 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10838 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10839 MDIO_84833_CMD_HDLR_STATUS, &val); 10840 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10841 break; 10842 MSLEEP(cb, 1); 10843 } 10844 if (idx >= PHY84833_CMDHDLR_WAIT) { 10845 ELINK_DEBUG_P0(cb, "FW cmd: FW not ready.\n"); 10846 return ELINK_STATUS_ERROR; 10847 } 10848 10849 /* Prepare argument(s) and issue command */ 10850 for (idx = 0; idx < argc; idx++) { 10851 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10852 MDIO_84833_CMD_HDLR_DATA1 + idx, 10853 cmd_args[idx]); 10854 } 10855 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10856 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 10857 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10858 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10859 MDIO_84833_CMD_HDLR_STATUS, &val); 10860 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10861 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10862 break; 10863 MSLEEP(cb, 1); 10864 } 10865 if ((idx >= PHY84833_CMDHDLR_WAIT) || 10866 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10867 ELINK_DEBUG_P0(cb, "FW cmd failed.\n"); 10868 return ELINK_STATUS_ERROR; 10869 } 10870 /* Gather returning data */ 10871 for (idx = 0; idx < argc; idx++) { 10872 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 10873 MDIO_84833_CMD_HDLR_DATA1 + idx, 10874 &cmd_args[idx]); 10875 } 10876 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 10877 MDIO_84833_CMD_HDLR_STATUS, 10878 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10879 return ELINK_STATUS_OK; 10880 } 10881 10882 #ifndef EXCLUDE_NON_COMMON_INIT 10883 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, 10884 struct elink_params *params, 10885 struct elink_vars *vars) 10886 { 10887 u32 pair_swap; 10888 u16 data[PHY84833_CMDHDLR_MAX_ARGS]; 10889 elink_status_t status; 10890 struct elink_dev *cb = params->cb; 10891 10892 /* Check for configuration. */ 10893 pair_swap = REG_RD(cb, params->shmem_base + 10894 OFFSETOF(struct shmem_region, 10895 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10896 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10897 10898 if (pair_swap == 0) 10899 return ELINK_STATUS_OK; 10900 10901 /* Only the second argument is used for this command */ 10902 data[1] = (u16)pair_swap; 10903 10904 status = elink_84833_cmd_hdlr(phy, params, 10905 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 10906 if (status == ELINK_STATUS_OK) 10907 ELINK_DEBUG_P1(cb, "Pairswap OK, val=0x%x\n", data[1]); 10908 10909 return status; 10910 } 10911 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 10912 10913 static u8 elink_84833_get_reset_gpios(struct elink_dev *cb, 10914 u32 shmem_base_path[], 10915 u32 chip_id) 10916 { 10917 u32 reset_pin[2]; 10918 u32 idx; 10919 u8 reset_gpios; 10920 if (CHIP_IS_E3(chip_id)) { 10921 /* Assume that these will be GPIOs, not EPIOs. */ 10922 for (idx = 0; idx < 2; idx++) { 10923 /* Map config param to register bit. */ 10924 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 10925 OFFSETOF(struct shmem_region, 10926 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10927 reset_pin[idx] = (reset_pin[idx] & 10928 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10929 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10930 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10931 reset_pin[idx] = (1 << reset_pin[idx]); 10932 } 10933 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10934 } else { 10935 /* E2, look from diff place of shmem. */ 10936 for (idx = 0; idx < 2; idx++) { 10937 reset_pin[idx] = REG_RD(cb, shmem_base_path[idx] + 10938 OFFSETOF(struct shmem_region, 10939 dev_info.port_hw_config[0].default_cfg)); 10940 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10941 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10942 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10943 reset_pin[idx] = (1 << reset_pin[idx]); 10944 } 10945 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); 10946 } 10947 10948 return reset_gpios; 10949 } 10950 10951 #ifndef EXCLUDE_NON_COMMON_INIT 10952 static void 10953 elink_84833_hw_reset_phy(struct elink_phy *phy, 10954 struct elink_params *params) 10955 { 10956 struct elink_dev *cb = params->cb; 10957 u8 reset_gpios; 10958 u32 other_shmem_base_addr = REG_RD(cb, params->shmem2_base + 10959 OFFSETOF(struct shmem2_region, 10960 other_shmem_base_addr)); 10961 10962 u32 shmem_base_path[2]; 10963 10964 /* Work around for 84833 LED failure inside RESET status */ 10965 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 10966 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10967 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10968 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 10969 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10970 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10971 10972 shmem_base_path[0] = params->shmem_base; 10973 shmem_base_path[1] = other_shmem_base_addr; 10974 10975 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, 10976 params->chip_id); 10977 10978 #ifndef EDEBUG 10979 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10980 USLEEP(cb, 10); 10981 ELINK_DEBUG_P1(cb, "84833 hw reset on pin values 0x%x\n", 10982 reset_gpios); 10983 #endif // EDEBUG 10984 } 10985 #endif // EXCLUDE_NON_COMMON_INIT 10986 #endif // #ifndef EXCLUDE_BCM84833 10987 10988 #ifndef EXCLUDE_NON_COMMON_INIT 10989 #ifndef EXCLUDE_WARPCORE 10990 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, 10991 struct elink_params *params, 10992 struct elink_vars *vars) 10993 { 10994 elink_status_t rc; 10995 #if defined(ELINK_DEBUG) 10996 struct elink_dev *cb = params->cb; 10997 #endif 10998 u16 cmd_args = 0; 10999 11000 ELINK_DEBUG_P0(cb, "Don't Advertise 10GBase-T EEE\n"); 11001 11002 /* Prevent Phy from working in EEE and advertising it */ 11003 rc = elink_84833_cmd_hdlr(phy, params, 11004 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11005 if (rc != ELINK_STATUS_OK) { 11006 ELINK_DEBUG_P0(cb, "EEE disable failed.\n"); 11007 return rc; 11008 } 11009 11010 return elink_eee_disable(phy, params, vars); 11011 } 11012 11013 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, 11014 struct elink_params *params, 11015 struct elink_vars *vars) 11016 { 11017 elink_status_t rc; 11018 #ifdef ELINK_DEBUG 11019 struct elink_dev *cb = params->cb; 11020 #endif 11021 u16 cmd_args = 1; 11022 11023 rc = elink_84833_cmd_hdlr(phy, params, 11024 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 11025 if (rc != ELINK_STATUS_OK) { 11026 ELINK_DEBUG_P0(cb, "EEE enable failed.\n"); 11027 return rc; 11028 } 11029 11030 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 11031 } 11032 #endif /* #ifndef EXCLUDE_WARPCORE */ 11033 11034 #if !defined(EXCLUDE_BCM8481) || !defined(EXCLUDE_BCM84833) 11035 #define PHY84833_CONSTANT_LATENCY 1193 11036 static elink_status_t 11037 elink_848x3_config_init(struct elink_phy *phy, struct elink_params *params, 11038 struct elink_vars *vars) 11039 { 11040 struct elink_dev *cb = params->cb; 11041 u8 port, initialize = 1; 11042 u16 val; 11043 u32 actual_phy_selection; 11044 #ifndef EXCLUDE_BCM84833 11045 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 11046 #endif // EXCLUDE_BCM84833 11047 elink_status_t rc = ELINK_STATUS_OK; 11048 11049 MSLEEP(cb, 1); 11050 11051 if (!(CHIP_IS_E1X(params->chip_id))) 11052 port = PATH_ID(cb); 11053 else 11054 port = params->port; 11055 11056 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11057 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11058 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 11059 port); 11060 } else { 11061 /* MDIO reset */ 11062 elink_cl45_write(cb, phy, 11063 MDIO_PMA_DEVAD, 11064 MDIO_PMA_REG_CTRL, 0x8000); 11065 } 11066 11067 elink_wait_reset_complete(cb, phy, params); 11068 11069 /* Wait for GPHY to come out of reset */ 11070 MSLEEP(cb, 50); 11071 #ifndef EXCLUDE_BCM84833 11072 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11073 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11074 #endif // EXCLUDE_BCM84833 11075 #ifndef EXCLUDE_BCM8481 11076 /* BCM84823 requires that XGXS links up first @ 10G for normal 11077 * behavior. 11078 */ 11079 u16 temp; 11080 temp = vars->line_speed; 11081 vars->line_speed = ELINK_SPEED_10000; 11082 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); 11083 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); 11084 vars->line_speed = temp; 11085 #endif // EXCLUDE_BCM8481 11086 #ifndef EXCLUDE_BCM84833 11087 } 11088 #endif /* Set dual-media configuration according to configuration */ 11089 11090 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11091 MDIO_CTL_REG_84823_MEDIA, &val); 11092 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11093 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 11094 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 11095 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 11096 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 11097 11098 if (CHIP_IS_E3(params->chip_id)) { 11099 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 11100 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 11101 } else { 11102 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 11103 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 11104 } 11105 11106 actual_phy_selection = elink_phy_selection(params); 11107 11108 switch (actual_phy_selection) { 11109 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 11110 /* Do nothing. Essentially this is like the priority copper */ 11111 break; 11112 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11113 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 11114 break; 11115 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11116 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 11117 break; 11118 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11119 /* Do nothing here. The first PHY won't be initialized at all */ 11120 break; 11121 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11122 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 11123 initialize = 0; 11124 break; 11125 } 11126 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) 11127 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 11128 11129 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11130 MDIO_CTL_REG_84823_MEDIA, val); 11131 ELINK_DEBUG_P2(cb, "Multi_phy config = 0x%x, Media control = 0x%x\n", 11132 params->multi_phy_config, val); 11133 11134 #ifndef EXCLUDE_BCM84833 11135 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11136 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11137 elink_84833_pair_swap_cfg(phy, params, vars); 11138 11139 /* Keep AutogrEEEn disabled. */ 11140 cmd_args[0] = 0x0; 11141 cmd_args[1] = 0x0; 11142 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 11143 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 11144 rc = elink_84833_cmd_hdlr(phy, params, 11145 PHY84833_CMD_SET_EEE_MODE, cmd_args, 11146 PHY84833_CMDHDLR_MAX_ARGS); 11147 if (rc != ELINK_STATUS_OK) 11148 ELINK_DEBUG_P0(cb, "Cfg AutogrEEEn failed.\n"); 11149 } 11150 #endif // #ifndef EXCLUDE_BCM84833 11151 if (initialize) 11152 rc = elink_848xx_cmn_config_init(phy, params, vars); 11153 #ifdef ELINK_ENHANCEMENTS 11154 else 11155 elink_save_848xx_spirom_version(phy, cb, params->port); 11156 #endif // ELINK_ENHANCEMENTS 11157 /* 84833 PHY has a better feature and doesn't need to support this. */ 11158 #ifndef EXCLUDE_BCM8481 11159 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11160 u32 cms_enable = REG_RD(cb, params->shmem_base + 11161 OFFSETOF(struct shmem_region, 11162 dev_info.port_hw_config[params->port].default_cfg)) & 11163 PORT_HW_CFG_ENABLE_CMS_MASK; 11164 11165 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11166 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 11167 if (cms_enable) 11168 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 11169 else 11170 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 11171 elink_cl45_write(cb, phy, MDIO_CTL_DEVAD, 11172 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 11173 } 11174 #endif /* EXCLUDE_BCM8481 */ 11175 11176 #ifndef EXCLUDE_WARPCORE 11177 elink_cl45_read(cb, phy, MDIO_CTL_DEVAD, 11178 MDIO_84833_TOP_CFG_FW_REV, &val); 11179 11180 /* Configure EEE support */ 11181 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 11182 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 11183 elink_eee_has_cap(params)) { 11184 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 11185 if (rc != ELINK_STATUS_OK) { 11186 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 11187 elink_8483x_disable_eee(phy, params, vars); 11188 return rc; 11189 } 11190 11191 if ((phy->req_duplex == DUPLEX_FULL) && 11192 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11193 (elink_eee_calc_timer(params) || 11194 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) 11195 rc = elink_8483x_enable_eee(phy, params, vars); 11196 else 11197 rc = elink_8483x_disable_eee(phy, params, vars); 11198 if (rc != ELINK_STATUS_OK) { 11199 ELINK_DEBUG_P0(cb, "Failed to set EEE advertisement\n"); 11200 return rc; 11201 } 11202 } else { 11203 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 11204 } 11205 #endif /* #ifndef EXCLUDE_WARPCORE */ 11206 11207 #ifndef EXCLUDE_BCM84833 11208 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11209 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11210 /* Bring PHY out of super isolate mode as the final step. */ 11211 elink_cl45_read_and_write(cb, phy, 11212 MDIO_CTL_DEVAD, 11213 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 11214 (u16)~MDIO_84833_SUPER_ISOLATE); 11215 } 11216 #endif /* #ifndef EXCLUDE_BCM84833 */ 11217 return rc; 11218 } 11219 11220 static elink_status_t 11221 elink_848xx_read_status(struct elink_phy *phy, struct elink_params *params, 11222 struct elink_vars *vars) 11223 { 11224 struct elink_dev *cb = params->cb; 11225 u16 val, val1, val2; 11226 u8 link_up = 0; 11227 11228 11229 /* Check 10G-BaseT link status */ 11230 /* Check PMD signal ok */ 11231 elink_cl45_read(cb, phy, 11232 MDIO_AN_DEVAD, 0xFFFA, &val1); 11233 elink_cl45_read(cb, phy, 11234 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 11235 &val2); 11236 ELINK_DEBUG_P1(cb, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 11237 11238 /* Check link 10G */ 11239 if (val2 & (1<<11)) { 11240 vars->line_speed = ELINK_SPEED_10000; 11241 vars->duplex = DUPLEX_FULL; 11242 link_up = 1; 11243 elink_ext_phy_10G_an_resolve(cb, phy, vars); 11244 } else { /* Check Legacy speed link */ 11245 u16 legacy_status, legacy_speed; 11246 11247 /* Enable expansion register 0x42 (Operation mode status) */ 11248 elink_cl45_write(cb, phy, 11249 MDIO_AN_DEVAD, 11250 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 11251 11252 /* Get legacy speed operation status */ 11253 elink_cl45_read(cb, phy, 11254 MDIO_AN_DEVAD, 11255 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 11256 &legacy_status); 11257 11258 ELINK_DEBUG_P1(cb, "Legacy speed status = 0x%x\n", 11259 legacy_status); 11260 link_up = ((legacy_status & (1<<11)) == (1<<11)); 11261 legacy_speed = (legacy_status & (3<<9)); 11262 if (legacy_speed == (0<<9)) 11263 vars->line_speed = ELINK_SPEED_10; 11264 else if (legacy_speed == (1<<9)) 11265 vars->line_speed = ELINK_SPEED_100; 11266 else if (legacy_speed == (2<<9)) 11267 vars->line_speed = ELINK_SPEED_1000; 11268 else { /* Should not happen: Treat as link down */ 11269 vars->line_speed = 0; 11270 link_up = 0; 11271 } 11272 11273 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */ 11274 if (params->feature_config_flags & 11275 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { 11276 u16 mii_ctrl; 11277 11278 elink_cl45_read(cb, phy, 11279 MDIO_AN_DEVAD, 11280 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 11281 &mii_ctrl); 11282 /* For IEEE testing, check for a fake link. */ 11283 link_up |= ((mii_ctrl & 0x3040) == 0x40); 11284 } 11285 #endif 11286 11287 if (link_up) { 11288 if (legacy_status & (1<<8)) 11289 vars->duplex = DUPLEX_FULL; 11290 else 11291 vars->duplex = DUPLEX_HALF; 11292 11293 ELINK_DEBUG_P2(cb, 11294 "Link is up in %dMbps, is_duplex_full= %d\n", 11295 vars->line_speed, 11296 (vars->duplex == DUPLEX_FULL)); 11297 /* Check legacy speed AN resolution */ 11298 elink_cl45_read(cb, phy, 11299 MDIO_AN_DEVAD, 11300 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 11301 &val); 11302 if (val & (1<<5)) 11303 vars->link_status |= 11304 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11305 elink_cl45_read(cb, phy, 11306 MDIO_AN_DEVAD, 11307 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 11308 &val); 11309 if ((val & (1<<0)) == 0) 11310 vars->link_status |= 11311 LINK_STATUS_PARALLEL_DETECTION_USED; 11312 } 11313 } 11314 if (link_up) { 11315 ELINK_DEBUG_P1(cb, "BCM848x3: link speed is %d\n", 11316 vars->line_speed); 11317 elink_ext_phy_resolve_fc(phy, params, vars); 11318 11319 /* Read LP advertised speeds */ 11320 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11321 MDIO_AN_REG_CL37_FC_LP, &val); 11322 if (val & (1<<5)) 11323 vars->link_status |= 11324 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11325 if (val & (1<<6)) 11326 vars->link_status |= 11327 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11328 if (val & (1<<7)) 11329 vars->link_status |= 11330 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11331 if (val & (1<<8)) 11332 vars->link_status |= 11333 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11334 if (val & (1<<9)) 11335 vars->link_status |= 11336 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11337 11338 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11339 MDIO_AN_REG_1000T_STATUS, &val); 11340 11341 if (val & (1<<10)) 11342 vars->link_status |= 11343 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11344 if (val & (1<<11)) 11345 vars->link_status |= 11346 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11347 11348 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 11349 MDIO_AN_REG_MASTER_STATUS, &val); 11350 11351 if (val & (1<<11)) 11352 vars->link_status |= 11353 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11354 11355 #if (!defined EXCLUDE_BCM84833) && (!defined EXCLUDE_WARPCORE) 11356 /* Determine if EEE was negotiated */ 11357 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11358 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 11359 elink_eee_an_resolve(phy, params, vars); 11360 #endif /* #ifndef EXCLUDE_WARPCORE */ 11361 } 11362 11363 return link_up; 11364 } 11365 11366 static elink_status_t 11367 elink_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len) 11368 { 11369 elink_status_t status = ELINK_STATUS_OK; 11370 #ifdef ELINK_ENHANCEMENTS 11371 u32 spirom_ver; 11372 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 11373 status = elink_format_ver(spirom_ver, str, len); 11374 #endif // ELINK_ENHANCEMENTS 11375 return status; 11376 } 11377 11378 #ifndef EXCLUDE_BCM8481 11379 static void elink_8481_hw_reset(struct elink_phy *phy, 11380 struct elink_params *params) 11381 { 11382 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11383 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 11384 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 11385 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 11386 } 11387 11388 static void elink_8481_link_reset(struct elink_phy *phy, 11389 struct elink_params *params) 11390 { 11391 #ifndef EXCLUDE_LINK_RESET 11392 elink_cl45_write(params->cb, phy, 11393 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 11394 elink_cl45_write(params->cb, phy, 11395 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 11396 #endif // EXCLUDE_LINK_RESET 11397 } 11398 #endif // #ifndef EXCLUDE_8481 11399 11400 static void elink_848x3_link_reset(struct elink_phy *phy, 11401 struct elink_params *params) 11402 { 11403 struct elink_dev *cb = params->cb; 11404 u8 port; 11405 u16 val16; 11406 11407 if (!(CHIP_IS_E1X(params->chip_id))) 11408 port = PATH_ID(cb); 11409 else 11410 port = params->port; 11411 11412 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11413 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_3, 11414 MISC_REGISTERS_GPIO_OUTPUT_LOW, 11415 port); 11416 } else { 11417 elink_cl45_read(cb, phy, 11418 MDIO_CTL_DEVAD, 11419 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 11420 val16 |= MDIO_84833_SUPER_ISOLATE; 11421 elink_cl45_write(cb, phy, 11422 MDIO_CTL_DEVAD, 11423 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 11424 } 11425 } 11426 11427 static void elink_848xx_set_link_led(struct elink_phy *phy, 11428 struct elink_params *params, u8 mode) 11429 { 11430 struct elink_dev *cb = params->cb; 11431 u16 val; 11432 #ifndef ELINK_AUX_POWER 11433 u8 port; 11434 11435 if (!(CHIP_IS_E1X(params->chip_id))) 11436 port = PATH_ID(cb); 11437 else 11438 port = params->port; 11439 #endif 11440 switch (mode) { 11441 case ELINK_LED_MODE_OFF: 11442 11443 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OFF\n", port); 11444 11445 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11446 SHARED_HW_CFG_LED_EXTPHY1) { 11447 11448 /* Set LED masks */ 11449 elink_cl45_write(cb, phy, 11450 MDIO_PMA_DEVAD, 11451 MDIO_PMA_REG_8481_LED1_MASK, 11452 0x0); 11453 11454 elink_cl45_write(cb, phy, 11455 MDIO_PMA_DEVAD, 11456 MDIO_PMA_REG_8481_LED2_MASK, 11457 0x0); 11458 11459 elink_cl45_write(cb, phy, 11460 MDIO_PMA_DEVAD, 11461 MDIO_PMA_REG_8481_LED3_MASK, 11462 0x0); 11463 11464 elink_cl45_write(cb, phy, 11465 MDIO_PMA_DEVAD, 11466 MDIO_PMA_REG_8481_LED5_MASK, 11467 0x0); 11468 11469 } else { 11470 elink_cl45_write(cb, phy, 11471 MDIO_PMA_DEVAD, 11472 MDIO_PMA_REG_8481_LED1_MASK, 11473 0x0); 11474 } 11475 break; 11476 case ELINK_LED_MODE_FRONT_PANEL_OFF: 11477 11478 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 11479 port); 11480 11481 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11482 SHARED_HW_CFG_LED_EXTPHY1) { 11483 11484 /* Set LED masks */ 11485 elink_cl45_write(cb, phy, 11486 MDIO_PMA_DEVAD, 11487 MDIO_PMA_REG_8481_LED1_MASK, 11488 0x0); 11489 11490 elink_cl45_write(cb, phy, 11491 MDIO_PMA_DEVAD, 11492 MDIO_PMA_REG_8481_LED2_MASK, 11493 0x0); 11494 11495 elink_cl45_write(cb, phy, 11496 MDIO_PMA_DEVAD, 11497 MDIO_PMA_REG_8481_LED3_MASK, 11498 0x0); 11499 11500 elink_cl45_write(cb, phy, 11501 MDIO_PMA_DEVAD, 11502 MDIO_PMA_REG_8481_LED5_MASK, 11503 0x20); 11504 11505 } else { 11506 elink_cl45_write(cb, phy, 11507 MDIO_PMA_DEVAD, 11508 MDIO_PMA_REG_8481_LED1_MASK, 11509 0x0); 11510 if (phy->type == 11511 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11512 /* Disable MI_INT interrupt before setting LED4 11513 * source to constant off. 11514 */ 11515 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11516 params->port*4) & 11517 ELINK_NIG_MASK_MI_INT) { 11518 params->link_flags |= 11519 ELINK_LINK_FLAGS_INT_DISABLED; 11520 11521 elink_bits_dis( 11522 cb, 11523 NIG_REG_MASK_INTERRUPT_PORT0 + 11524 params->port*4, 11525 ELINK_NIG_MASK_MI_INT); 11526 } 11527 elink_cl45_write(cb, phy, 11528 MDIO_PMA_DEVAD, 11529 MDIO_PMA_REG_8481_SIGNAL_MASK, 11530 0x0); 11531 } 11532 } 11533 break; 11534 case ELINK_LED_MODE_ON: 11535 11536 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE ON\n", port); 11537 11538 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11539 SHARED_HW_CFG_LED_EXTPHY1) { 11540 /* Set control reg */ 11541 elink_cl45_read(cb, phy, 11542 MDIO_PMA_DEVAD, 11543 MDIO_PMA_REG_8481_LINK_SIGNAL, 11544 &val); 11545 val &= 0x8000; 11546 val |= 0x2492; 11547 11548 elink_cl45_write(cb, phy, 11549 MDIO_PMA_DEVAD, 11550 MDIO_PMA_REG_8481_LINK_SIGNAL, 11551 val); 11552 11553 /* Set LED masks */ 11554 elink_cl45_write(cb, phy, 11555 MDIO_PMA_DEVAD, 11556 MDIO_PMA_REG_8481_LED1_MASK, 11557 0x0); 11558 11559 elink_cl45_write(cb, phy, 11560 MDIO_PMA_DEVAD, 11561 MDIO_PMA_REG_8481_LED2_MASK, 11562 0x20); 11563 11564 elink_cl45_write(cb, phy, 11565 MDIO_PMA_DEVAD, 11566 MDIO_PMA_REG_8481_LED3_MASK, 11567 0x20); 11568 11569 elink_cl45_write(cb, phy, 11570 MDIO_PMA_DEVAD, 11571 MDIO_PMA_REG_8481_LED5_MASK, 11572 0x0); 11573 } else { 11574 elink_cl45_write(cb, phy, 11575 MDIO_PMA_DEVAD, 11576 MDIO_PMA_REG_8481_LED1_MASK, 11577 0x20); 11578 if (phy->type == 11579 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11580 /* Disable MI_INT interrupt before setting LED4 11581 * source to constant on. 11582 */ 11583 if (REG_RD(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 11584 params->port*4) & 11585 ELINK_NIG_MASK_MI_INT) { 11586 params->link_flags |= 11587 ELINK_LINK_FLAGS_INT_DISABLED; 11588 11589 elink_bits_dis( 11590 cb, 11591 NIG_REG_MASK_INTERRUPT_PORT0 + 11592 params->port*4, 11593 ELINK_NIG_MASK_MI_INT); 11594 } 11595 elink_cl45_write(cb, phy, 11596 MDIO_PMA_DEVAD, 11597 MDIO_PMA_REG_8481_SIGNAL_MASK, 11598 0x20); 11599 } 11600 } 11601 break; 11602 11603 case ELINK_LED_MODE_OPER: 11604 11605 ELINK_DEBUG_P1(cb, "Port 0x%x: LED MODE OPER\n", port); 11606 11607 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11608 SHARED_HW_CFG_LED_EXTPHY1) { 11609 11610 /* Set control reg */ 11611 elink_cl45_read(cb, phy, 11612 MDIO_PMA_DEVAD, 11613 MDIO_PMA_REG_8481_LINK_SIGNAL, 11614 &val); 11615 11616 if (!((val & 11617 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 11618 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 11619 ELINK_DEBUG_P0(cb, "Setting LINK_SIGNAL\n"); 11620 elink_cl45_write(cb, phy, 11621 MDIO_PMA_DEVAD, 11622 MDIO_PMA_REG_8481_LINK_SIGNAL, 11623 0xa492); 11624 } 11625 11626 /* Set LED masks */ 11627 elink_cl45_write(cb, phy, 11628 MDIO_PMA_DEVAD, 11629 MDIO_PMA_REG_8481_LED1_MASK, 11630 0x10); 11631 11632 elink_cl45_write(cb, phy, 11633 MDIO_PMA_DEVAD, 11634 MDIO_PMA_REG_8481_LED2_MASK, 11635 0x80); 11636 11637 elink_cl45_write(cb, phy, 11638 MDIO_PMA_DEVAD, 11639 MDIO_PMA_REG_8481_LED3_MASK, 11640 0x98); 11641 11642 elink_cl45_write(cb, phy, 11643 MDIO_PMA_DEVAD, 11644 MDIO_PMA_REG_8481_LED5_MASK, 11645 0x40); 11646 11647 } else { 11648 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 11649 * sources are all wired through LED1, rather than only 11650 * 10G in other modes. 11651 */ 11652 val = ((params->hw_led_mode << 11653 SHARED_HW_CFG_LED_MODE_SHIFT) == 11654 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 11655 11656 elink_cl45_write(cb, phy, 11657 MDIO_PMA_DEVAD, 11658 MDIO_PMA_REG_8481_LED1_MASK, 11659 val); 11660 11661 /* Tell LED3 to blink on source */ 11662 elink_cl45_read(cb, phy, 11663 MDIO_PMA_DEVAD, 11664 MDIO_PMA_REG_8481_LINK_SIGNAL, 11665 &val); 11666 val &= ~(7<<6); 11667 val |= (1<<6); /* A83B[8:6]= 1 */ 11668 elink_cl45_write(cb, phy, 11669 MDIO_PMA_DEVAD, 11670 MDIO_PMA_REG_8481_LINK_SIGNAL, 11671 val); 11672 if (phy->type == 11673 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11674 /* Restore LED4 source to external link, 11675 * and re-enable interrupts. 11676 */ 11677 elink_cl45_write(cb, phy, 11678 MDIO_PMA_DEVAD, 11679 MDIO_PMA_REG_8481_SIGNAL_MASK, 11680 0x40); 11681 if (params->link_flags & 11682 ELINK_LINK_FLAGS_INT_DISABLED) { 11683 elink_link_int_enable(params); 11684 params->link_flags &= 11685 ~ELINK_LINK_FLAGS_INT_DISABLED; 11686 } 11687 } 11688 } 11689 break; 11690 } 11691 11692 /* This is a workaround for E3+84833 until autoneg 11693 * restart is fixed in f/w 11694 */ 11695 if (CHIP_IS_E3(params->chip_id)) { 11696 elink_cl45_read(cb, phy, MDIO_WC_DEVAD, 11697 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11698 } 11699 } 11700 #endif /* EXCLUDE_BCM8481 / EXCLUDE_BCM8481 */ 11701 #endif // EXCLUDE_NON_COMMON_INIT 11702 11703 /******************************************************************/ 11704 /* 54618SE PHY SECTION */ 11705 /******************************************************************/ 11706 #if (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 11707 #ifdef ELINK_AUX_POWER 11708 static int elink_54618se_init_required(struct elink_phy *phy, 11709 struct elink_params *params) 11710 { 11711 u16 autoneg_val, an_1000_val, an_10_100_val, ctrl, legacy_status; 11712 struct elink_dev *cb = params->cb; 11713 /* read all advertisement */ 11714 elink_cl22_read(cb, phy, 11715 MDIO_PMA_REG_CTRL, &ctrl); 11716 /* In case PHY is in reset */ 11717 if (ctrl & (1<<15)) 11718 return 1; 11719 11720 elink_cl22_read(cb, phy, 11721 0x09, 11722 &an_1000_val); 11723 elink_cl22_read(cb, phy, 11724 0x04, 11725 &an_10_100_val); 11726 elink_cl22_read(cb, phy, 11727 MDIO_PMA_REG_CTRL, 11728 &autoneg_val); 11729 elink_cl22_read(cb, phy, 11730 0x19, 11731 &legacy_status); 11732 /* Check conditions to avoid link reset in case link was 11733 * already initialized and up 11734 */ 11735 if ((an_1000_val & 0x300) && 11736 (an_10_100_val & 0x1e0) && 11737 (autoneg_val & 0x1000) && 11738 (legacy_status & (1<<2))) 11739 return 0; 11740 return 1; 11741 } 11742 #endif // ELINK_AUX_POWER 11743 static void elink_54618se_specific_func(struct elink_phy *phy, 11744 struct elink_params *params, 11745 u32 action) 11746 { 11747 struct elink_dev *cb = params->cb; 11748 u16 temp; 11749 switch (action) { 11750 case ELINK_PHY_INIT: 11751 /* Configure LED4: set to INTR (0x6). */ 11752 /* Accessing shadow register 0xe. */ 11753 elink_cl22_write(cb, phy, 11754 MDIO_REG_GPHY_SHADOW, 11755 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11756 elink_cl22_read(cb, phy, 11757 MDIO_REG_GPHY_SHADOW, 11758 &temp); 11759 temp &= ~(0xf << 4); 11760 temp |= (0x6 << 4); 11761 elink_cl22_write(cb, phy, 11762 MDIO_REG_GPHY_SHADOW, 11763 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11764 /* Configure INTR based on link status change. */ 11765 elink_cl22_write(cb, phy, 11766 MDIO_REG_INTR_MASK, 11767 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11768 break; 11769 } 11770 } 11771 11772 static elink_status_t 11773 elink_54618se_config_init(struct elink_phy *phy, 11774 struct elink_params *params, struct elink_vars *vars) 11775 { 11776 struct elink_dev *cb = params->cb; 11777 u8 port; 11778 u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11779 u32 cfg_pin; 11780 #ifdef ELINK_AUX_POWER 11781 u32 link_init_required = 1; 11782 if (!elink_54618se_init_required(phy, params)) 11783 link_init_required = 0; 11784 if (link_init_required) { 11785 #endif 11786 11787 ELINK_DEBUG_P0(cb, "54618SE cfg init\n"); 11788 MSLEEP(cb, 1); 11789 11790 /* This works with E3 only, no need to check the chip 11791 * before determining the port. 11792 */ 11793 port = params->port; 11794 11795 cfg_pin = (REG_RD(cb, params->shmem_base + 11796 OFFSETOF(struct shmem_region, 11797 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11798 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11799 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11800 11801 /* Drive pin high to bring the GPHY out of reset. */ 11802 elink_set_cfg_pin(cb, cfg_pin, 1); 11803 11804 /* wait for GPHY to reset */ 11805 MSLEEP(cb, 50); 11806 11807 /* reset phy */ 11808 elink_cl22_write(cb, phy, 11809 MDIO_PMA_REG_CTRL, 0x8000); 11810 elink_wait_reset_complete(cb, phy, params); 11811 11812 /* Wait for GPHY to reset */ 11813 MSLEEP(cb, 50); 11814 11815 #ifdef ELINK_AUX_POWER 11816 } // If init required 11817 #endif 11818 11819 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); 11820 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11821 elink_cl22_write(cb, phy, 11822 MDIO_REG_GPHY_SHADOW, 11823 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11824 elink_cl22_read(cb, phy, 11825 MDIO_REG_GPHY_SHADOW, 11826 &temp); 11827 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11828 elink_cl22_write(cb, phy, 11829 MDIO_REG_GPHY_SHADOW, 11830 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11831 11832 /* Set up fc */ 11833 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11834 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11835 #ifdef ELINK_AUX_POWER 11836 if (!link_init_required) 11837 return ELINK_STATUS_OK; 11838 #endif 11839 fc_val = 0; 11840 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11841 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11842 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11843 11844 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11845 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11846 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11847 11848 /* Read all advertisement */ 11849 elink_cl22_read(cb, phy, 11850 0x09, 11851 &an_1000_val); 11852 11853 elink_cl22_read(cb, phy, 11854 0x04, 11855 &an_10_100_val); 11856 11857 elink_cl22_read(cb, phy, 11858 MDIO_PMA_REG_CTRL, 11859 &autoneg_val); 11860 11861 /* Disable forced speed */ 11862 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11863 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11864 (1<<11)); 11865 11866 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 11867 (phy->speed_cap_mask & 11868 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11869 (phy->req_line_speed == ELINK_SPEED_1000)) { 11870 an_1000_val |= (1<<8); 11871 autoneg_val |= (1<<9 | 1<<12); 11872 if (phy->req_duplex == DUPLEX_FULL) 11873 an_1000_val |= (1<<9); 11874 ELINK_DEBUG_P0(cb, "Advertising 1G\n"); 11875 } else 11876 an_1000_val &= ~((1<<8) | (1<<9)); 11877 11878 elink_cl22_write(cb, phy, 11879 0x09, 11880 an_1000_val); 11881 elink_cl22_read(cb, phy, 11882 0x09, 11883 &an_1000_val); 11884 11885 /* Advertise 10/100 link speed */ 11886 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 11887 if (phy->speed_cap_mask & 11888 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11889 an_10_100_val |= (1<<5); 11890 autoneg_val |= (1<<9 | 1<<12); 11891 ELINK_DEBUG_P0(cb, "Advertising 10M-HD\n"); 11892 } 11893 if (phy->speed_cap_mask & 11894 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) { 11895 an_10_100_val |= (1<<6); 11896 autoneg_val |= (1<<9 | 1<<12); 11897 ELINK_DEBUG_P0(cb, "Advertising 10M-FD\n"); 11898 } 11899 if (phy->speed_cap_mask & 11900 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 11901 an_10_100_val |= (1<<7); 11902 autoneg_val |= (1<<9 | 1<<12); 11903 ELINK_DEBUG_P0(cb, "Advertising 100M-HD\n"); 11904 } 11905 if (phy->speed_cap_mask & 11906 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 11907 an_10_100_val |= (1<<8); 11908 autoneg_val |= (1<<9 | 1<<12); 11909 ELINK_DEBUG_P0(cb, "Advertising 100M-FD\n"); 11910 } 11911 } 11912 11913 /* Only 10/100 are allowed to work in FORCE mode */ 11914 if (phy->req_line_speed == ELINK_SPEED_100) { 11915 autoneg_val |= (1<<13); 11916 /* Enabled AUTO-MDIX when autoneg is disabled */ 11917 elink_cl22_write(cb, phy, 11918 0x18, 11919 (1<<15 | 1<<9 | 7<<0)); 11920 ELINK_DEBUG_P0(cb, "Setting 100M force\n"); 11921 } 11922 if (phy->req_line_speed == ELINK_SPEED_10) { 11923 /* Enabled AUTO-MDIX when autoneg is disabled */ 11924 elink_cl22_write(cb, phy, 11925 0x18, 11926 (1<<15 | 1<<9 | 7<<0)); 11927 ELINK_DEBUG_P0(cb, "Setting 10M force\n"); 11928 } 11929 11930 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { 11931 elink_status_t rc; 11932 11933 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS, 11934 MDIO_REG_GPHY_EXP_ACCESS_TOP | 11935 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 11936 elink_cl22_read(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 11937 temp &= 0xfffe; 11938 elink_cl22_write(cb, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 11939 11940 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 11941 if (rc != ELINK_STATUS_OK) { 11942 ELINK_DEBUG_P0(cb, "Failed to configure EEE timers\n"); 11943 elink_eee_disable(phy, params, vars); 11944 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11945 (phy->req_duplex == DUPLEX_FULL) && 11946 (elink_eee_calc_timer(params) || 11947 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { 11948 /* Need to advertise EEE only when requested, 11949 * and either no LPI assertion was requested, 11950 * or it was requested and a valid timer was set. 11951 * Also notice full duplex is required for EEE. 11952 */ 11953 elink_eee_advertise(phy, params, vars, 11954 SHMEM_EEE_1G_ADV); 11955 } else { 11956 ELINK_DEBUG_P0(cb, "Don't Advertise 1GBase-T EEE\n"); 11957 elink_eee_disable(phy, params, vars); 11958 } 11959 } else { 11960 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 11961 SHMEM_EEE_SUPPORTED_SHIFT; 11962 11963 if (phy->flags & ELINK_FLAGS_EEE) { 11964 /* Handle legacy auto-grEEEn */ 11965 if (params->feature_config_flags & 11966 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 11967 temp = 6; 11968 ELINK_DEBUG_P0(cb, "Enabling Auto-GrEEEn\n"); 11969 } else { 11970 temp = 0; 11971 ELINK_DEBUG_P0(cb, "Don't Adv. EEE\n"); 11972 } 11973 elink_cl45_write(cb, phy, MDIO_AN_DEVAD, 11974 MDIO_AN_REG_EEE_ADV, temp); 11975 } 11976 } 11977 11978 elink_cl22_write(cb, phy, 11979 0x04, 11980 an_10_100_val | fc_val); 11981 11982 if (phy->req_duplex == DUPLEX_FULL) 11983 autoneg_val |= (1<<8); 11984 11985 elink_cl22_write(cb, phy, 11986 MDIO_PMA_REG_CTRL, autoneg_val); 11987 11988 return ELINK_STATUS_OK; 11989 } 11990 11991 11992 static void elink_5461x_set_link_led(struct elink_phy *phy, 11993 struct elink_params *params, u8 mode) 11994 { 11995 #ifdef ELINK_ENHANCEMENTS 11996 struct elink_dev *cb = params->cb; 11997 u16 temp; 11998 11999 elink_cl22_write(cb, phy, 12000 MDIO_REG_GPHY_SHADOW, 12001 MDIO_REG_GPHY_SHADOW_LED_SEL1); 12002 elink_cl22_read(cb, phy, 12003 MDIO_REG_GPHY_SHADOW, 12004 &temp); 12005 temp &= 0xff00; 12006 12007 ELINK_DEBUG_P1(cb, "54618x set link led (mode=%x)\n", mode); 12008 switch (mode) { 12009 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12010 case ELINK_LED_MODE_OFF: 12011 temp |= 0x00ee; 12012 break; 12013 case ELINK_LED_MODE_OPER: 12014 temp |= 0x0001; 12015 break; 12016 case ELINK_LED_MODE_ON: 12017 temp |= 0x00ff; 12018 break; 12019 default: 12020 break; 12021 } 12022 elink_cl22_write(cb, phy, 12023 MDIO_REG_GPHY_SHADOW, 12024 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 12025 return; 12026 #endif // ELINK_ENHANCEMENTS 12027 } 12028 12029 12030 static void elink_54618se_link_reset(struct elink_phy *phy, 12031 struct elink_params *params) 12032 { 12033 struct elink_dev *cb = params->cb; 12034 u32 cfg_pin; 12035 u8 port; 12036 12037 #ifdef ELINK_AUX_POWER 12038 if (!elink_54618se_init_required(phy, params)) 12039 return; 12040 #endif // ELINK_AUX_POWER 12041 /* In case of no EPIO routed to reset the GPHY, put it 12042 * in low power mode. 12043 */ 12044 elink_cl22_write(cb, phy, MDIO_PMA_REG_CTRL, 0x800); 12045 /* This works with E3 only, no need to check the chip 12046 * before determining the port. 12047 */ 12048 port = params->port; 12049 cfg_pin = (REG_RD(cb, params->shmem_base + 12050 OFFSETOF(struct shmem_region, 12051 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 12052 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 12053 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 12054 12055 /* Drive pin low to put GPHY in reset. */ 12056 elink_set_cfg_pin(cb, cfg_pin, 0); 12057 } 12058 12059 static elink_status_t 12060 elink_54618se_read_status(struct elink_phy *phy, struct elink_params *params, 12061 struct elink_vars *vars) 12062 { 12063 struct elink_dev *cb = params->cb; 12064 u16 val; 12065 u8 link_up = 0; 12066 u16 legacy_status, legacy_speed; 12067 12068 /* Get speed operation status */ 12069 elink_cl22_read(cb, phy, 12070 MDIO_REG_GPHY_AUX_STATUS, 12071 &legacy_status); 12072 ELINK_DEBUG_P1(cb, "54618SE read_status: 0x%x\n", legacy_status); 12073 12074 /* Read status to clear the PHY interrupt. */ 12075 elink_cl22_read(cb, phy, 12076 MDIO_REG_INTR_STATUS, 12077 &val); 12078 12079 link_up = ((legacy_status & (1<<2)) == (1<<2)); 12080 12081 if (link_up) { 12082 legacy_speed = (legacy_status & (7<<8)); 12083 if (legacy_speed == (7<<8)) { 12084 vars->line_speed = ELINK_SPEED_1000; 12085 vars->duplex = DUPLEX_FULL; 12086 } else if (legacy_speed == (6<<8)) { 12087 vars->line_speed = ELINK_SPEED_1000; 12088 vars->duplex = DUPLEX_HALF; 12089 } else if (legacy_speed == (5<<8)) { 12090 vars->line_speed = ELINK_SPEED_100; 12091 vars->duplex = DUPLEX_FULL; 12092 } 12093 /* Omitting 100Base-T4 for now */ 12094 else if (legacy_speed == (3<<8)) { 12095 vars->line_speed = ELINK_SPEED_100; 12096 vars->duplex = DUPLEX_HALF; 12097 } else if (legacy_speed == (2<<8)) { 12098 vars->line_speed = ELINK_SPEED_10; 12099 vars->duplex = DUPLEX_FULL; 12100 } else if (legacy_speed == (1<<8)) { 12101 vars->line_speed = ELINK_SPEED_10; 12102 vars->duplex = DUPLEX_HALF; 12103 } else /* Should not happen */ 12104 vars->line_speed = 0; 12105 12106 ELINK_DEBUG_P2(cb, 12107 "Link is up in %dMbps, is_duplex_full= %d\n", 12108 vars->line_speed, 12109 (vars->duplex == DUPLEX_FULL)); 12110 12111 /* Check legacy speed AN resolution */ 12112 elink_cl22_read(cb, phy, 12113 0x01, 12114 &val); 12115 if (val & (1<<5)) 12116 vars->link_status |= 12117 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 12118 elink_cl22_read(cb, phy, 12119 0x06, 12120 &val); 12121 if ((val & (1<<0)) == 0) 12122 vars->link_status |= 12123 LINK_STATUS_PARALLEL_DETECTION_USED; 12124 12125 ELINK_DEBUG_P1(cb, "BCM54618SE: link speed is %d\n", 12126 vars->line_speed); 12127 12128 elink_ext_phy_resolve_fc(phy, params, vars); 12129 12130 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 12131 /* Report LP advertised speeds */ 12132 elink_cl22_read(cb, phy, 0x5, &val); 12133 12134 if (val & (1<<5)) 12135 vars->link_status |= 12136 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 12137 if (val & (1<<6)) 12138 vars->link_status |= 12139 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 12140 if (val & (1<<7)) 12141 vars->link_status |= 12142 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 12143 if (val & (1<<8)) 12144 vars->link_status |= 12145 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 12146 if (val & (1<<9)) 12147 vars->link_status |= 12148 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 12149 12150 elink_cl22_read(cb, phy, 0xa, &val); 12151 if (val & (1<<10)) 12152 vars->link_status |= 12153 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 12154 if (val & (1<<11)) 12155 vars->link_status |= 12156 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 12157 12158 if ((phy->flags & ELINK_FLAGS_EEE) && 12159 elink_eee_has_cap(params)) 12160 elink_eee_an_resolve(phy, params, vars); 12161 } 12162 } 12163 return link_up; 12164 } 12165 12166 static void elink_54618se_config_loopback(struct elink_phy *phy, 12167 struct elink_params *params) 12168 { 12169 #ifdef ELINK_INCLUDE_LOOPBACK 12170 struct elink_dev *cb = params->cb; 12171 u16 val; 12172 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 12173 12174 ELINK_DEBUG_P0(cb, "2PMA/PMD ext_phy_loopback: 54618se\n"); 12175 12176 /* Enable master/slave manual mmode and set to master */ 12177 /* mii write 9 [bits set 11 12] */ 12178 elink_cl22_write(cb, phy, 0x09, 3<<11); 12179 12180 /* forced 1G and disable autoneg */ 12181 /* set val [mii read 0] */ 12182 /* set val [expr $val & [bits clear 6 12 13]] */ 12183 /* set val [expr $val | [bits set 6 8]] */ 12184 /* mii write 0 $val */ 12185 elink_cl22_read(cb, phy, 0x00, &val); 12186 val &= ~((1<<6) | (1<<12) | (1<<13)); 12187 val |= (1<<6) | (1<<8); 12188 elink_cl22_write(cb, phy, 0x00, val); 12189 12190 /* Set external loopback and Tx using 6dB coding */ 12191 /* mii write 0x18 7 */ 12192 /* set val [mii read 0x18] */ 12193 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 12194 elink_cl22_write(cb, phy, 0x18, 7); 12195 elink_cl22_read(cb, phy, 0x18, &val); 12196 elink_cl22_write(cb, phy, 0x18, val | (1<<10) | (1<<15)); 12197 12198 /* This register opens the gate for the UMAC despite its name */ 12199 REG_WR(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 12200 12201 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 12202 * length used by the MAC receive logic to check frames. 12203 */ 12204 REG_WR(cb, umac_base + UMAC_REG_MAXFR, 0x2710); 12205 #endif // ELINK_INCLUDE_LOOPBACK 12206 } 12207 12208 #endif // (!defined EXCLUDE_NON_COMMON_INIT) && (!defined EXCLUDE_BCM54618SE) 12209 /******************************************************************/ 12210 /* SFX7101 PHY SECTION */ 12211 /******************************************************************/ 12212 #ifndef EXCLUDE_SFX7101 12213 static void elink_7101_config_loopback(struct elink_phy *phy, 12214 struct elink_params *params) 12215 { 12216 struct elink_dev *cb = params->cb; 12217 /* SFX7101_XGXS_TEST1 */ 12218 elink_cl45_write(cb, phy, 12219 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 12220 } 12221 12222 static elink_status_t elink_7101_config_init(struct elink_phy *phy, 12223 struct elink_params *params, 12224 struct elink_vars *vars) 12225 { 12226 u16 fw_ver1, fw_ver2, val; 12227 struct elink_dev *cb = params->cb; 12228 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LASI indication\n"); 12229 12230 /* Restore normal power mode*/ 12231 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 12232 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 12233 /* HW reset */ 12234 elink_ext_phy_hw_reset(cb, params->port); 12235 elink_wait_reset_complete(cb, phy, params); 12236 12237 elink_cl45_write(cb, phy, 12238 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 12239 ELINK_DEBUG_P0(cb, "Setting the SFX7101 LED to blink on traffic\n"); 12240 elink_cl45_write(cb, phy, 12241 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 12242 12243 elink_ext_phy_set_pause(params, phy, vars); 12244 /* Restart autoneg */ 12245 elink_cl45_read(cb, phy, 12246 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 12247 val |= 0x200; 12248 elink_cl45_write(cb, phy, 12249 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 12250 12251 /* Save spirom version */ 12252 elink_cl45_read(cb, phy, 12253 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 12254 12255 elink_cl45_read(cb, phy, 12256 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 12257 elink_save_spirom_version(cb, params->port, 12258 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 12259 return ELINK_STATUS_OK; 12260 } 12261 12262 static elink_status_t 12263 elink_7101_read_status(struct elink_phy *phy, struct elink_params *params, 12264 struct elink_vars *vars) 12265 { 12266 struct elink_dev *cb = params->cb; 12267 u8 link_up; 12268 u16 val1, val2; 12269 elink_cl45_read(cb, phy, 12270 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 12271 elink_cl45_read(cb, phy, 12272 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 12273 ELINK_DEBUG_P2(cb, "10G-base-T LASI status 0x%x->0x%x\n", 12274 val2, val1); 12275 elink_cl45_read(cb, phy, 12276 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 12277 elink_cl45_read(cb, phy, 12278 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 12279 ELINK_DEBUG_P2(cb, "10G-base-T PMA status 0x%x->0x%x\n", 12280 val2, val1); 12281 link_up = ((val1 & 4) == 4); 12282 /* If link is up print the AN outcome of the SFX7101 PHY */ 12283 if (link_up) { 12284 elink_cl45_read(cb, phy, 12285 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 12286 &val2); 12287 vars->line_speed = ELINK_SPEED_10000; 12288 vars->duplex = DUPLEX_FULL; 12289 ELINK_DEBUG_P2(cb, "SFX7101 AN status 0x%x->Master=%x\n", 12290 val2, (val2 & (1<<14))); 12291 elink_ext_phy_10G_an_resolve(cb, phy, vars); 12292 elink_ext_phy_resolve_fc(phy, params, vars); 12293 12294 /* Read LP advertised speeds */ 12295 if (val2 & (1<<11)) 12296 vars->link_status |= 12297 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 12298 } 12299 return link_up; 12300 } 12301 12302 static elink_status_t 12303 elink_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len) 12304 { 12305 if (*len < 5) 12306 return ELINK_STATUS_ERROR; 12307 str[0] = (spirom_ver & 0xFF); 12308 str[1] = (spirom_ver & 0xFF00) >> 8; 12309 str[2] = (spirom_ver & 0xFF0000) >> 16; 12310 str[3] = (spirom_ver & 0xFF000000) >> 24; 12311 str[4] = '\0'; 12312 *len -= 5; 12313 return ELINK_STATUS_OK; 12314 } 12315 12316 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy) 12317 { 12318 u16 val, cnt; 12319 12320 elink_cl45_read(cb, phy, 12321 MDIO_PMA_DEVAD, 12322 MDIO_PMA_REG_7101_RESET, &val); 12323 12324 for (cnt = 0; cnt < 10; cnt++) { 12325 MSLEEP(cb, 50); 12326 /* Writes a self-clearing reset */ 12327 elink_cl45_write(cb, phy, 12328 MDIO_PMA_DEVAD, 12329 MDIO_PMA_REG_7101_RESET, 12330 (val | (1<<15))); 12331 /* Wait for clear */ 12332 elink_cl45_read(cb, phy, 12333 MDIO_PMA_DEVAD, 12334 MDIO_PMA_REG_7101_RESET, &val); 12335 12336 if ((val & (1<<15)) == 0) 12337 break; 12338 } 12339 } 12340 12341 static void elink_7101_hw_reset(struct elink_phy *phy, 12342 struct elink_params *params) { 12343 #ifdef ELINK_ENHANCEMENTS 12344 /* Low power mode is controlled by GPIO 2 */ 12345 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_2, 12346 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12347 /* The PHY reset is controlled by GPIO 1 */ 12348 ELINK_SET_GPIO(params->cb, MISC_REGISTERS_GPIO_1, 12349 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12350 #endif // ELINK_ENHANCEMENTS 12351 } 12352 12353 static void elink_7101_set_link_led(struct elink_phy *phy, 12354 struct elink_params *params, u8 mode) 12355 { 12356 u16 val = 0; 12357 struct elink_dev *cb = params->cb; 12358 switch (mode) { 12359 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12360 case ELINK_LED_MODE_OFF: 12361 val = 2; 12362 break; 12363 case ELINK_LED_MODE_ON: 12364 val = 1; 12365 break; 12366 case ELINK_LED_MODE_OPER: 12367 val = 0; 12368 break; 12369 } 12370 elink_cl45_write(cb, phy, 12371 MDIO_PMA_DEVAD, 12372 MDIO_PMA_REG_7107_LINK_LED_CNTL, 12373 val); 12374 } 12375 #endif /* EXCLUDE_SFX7101 */ 12376 #endif /* ELINK_EMUL_ONLY */ 12377 12378 /******************************************************************/ 12379 /* STATIC PHY DECLARATION */ 12380 /******************************************************************/ 12381 12382 static const struct elink_phy phy_null = { 12383 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 12384 /*.addr = */0, 12385 /*.def_md_devad = */0, 12386 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12387 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12388 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12389 /*.mdio_ctrl = */0, 12390 /*.supported = */0, 12391 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12392 /*.ver_addr = */0, 12393 /*.req_flow_ctrl = */0, 12394 /*.req_line_speed = */0, 12395 /*.speed_cap_mask = */0, 12396 /*.req_duplex = */0, 12397 /*.rsrv = */0, 12398 /*.config_init = */(config_init_t)NULL, 12399 /*.read_status = */(read_status_t)NULL, 12400 /*.link_reset = */(link_reset_t)NULL, 12401 /*.config_loopback = */(config_loopback_t)NULL, 12402 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12403 /*.hw_reset = */(hw_reset_t)NULL, 12404 /*.set_link_led = */(set_link_led_t)NULL, 12405 /*.phy_specific_func = */(phy_specific_func_t)NULL 12406 }; 12407 12408 #ifndef EXCLUDE_SERDES 12409 static const struct elink_phy phy_serdes = { 12410 /*.type = */PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 12411 /*.addr = */0xff, 12412 /*.def_md_devad = */0, 12413 /*.flags = */0, 12414 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12415 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12416 /*.mdio_ctrl = */0, 12417 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12418 ELINK_SUPPORTED_10baseT_Full | 12419 ELINK_SUPPORTED_100baseT_Half | 12420 ELINK_SUPPORTED_100baseT_Full | 12421 ELINK_SUPPORTED_1000baseT_Full | 12422 ELINK_SUPPORTED_2500baseX_Full | 12423 ELINK_SUPPORTED_TP | 12424 ELINK_SUPPORTED_Autoneg | 12425 ELINK_SUPPORTED_Pause | 12426 ELINK_SUPPORTED_Asym_Pause), 12427 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12428 /*.ver_addr = */0, 12429 /*.req_flow_ctrl = */0, 12430 /*.req_line_speed = */0, 12431 /*.speed_cap_mask = */0, 12432 /*.req_duplex = */0, 12433 /*.rsrv = */0, 12434 /*.config_init = */elink_xgxs_config_init, 12435 /*.read_status = */elink_link_settings_status, 12436 /*.link_reset = */elink_int_link_reset, 12437 /*.config_loopback = */(config_loopback_t)NULL, 12438 /*.format_fw_ver = */(format_fw_ver_t)NULL, 12439 /*.hw_reset = */(hw_reset_t)NULL, 12440 /*.set_link_led = */(set_link_led_t)NULL, 12441 /*.phy_specific_func = */(phy_specific_func_t)NULL 12442 }; 12443 12444 #endif /* #ifndef EXCLUDE_SERDES */ 12445 #ifndef EXCLUDE_XGXS 12446 static const struct elink_phy phy_xgxs = { 12447 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12448 /*.addr = */0xff, 12449 /*.def_md_devad = */0, 12450 /*.flags = */0, 12451 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12452 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12453 /*.mdio_ctrl = */0, 12454 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12455 ELINK_SUPPORTED_10baseT_Full | 12456 ELINK_SUPPORTED_100baseT_Half | 12457 ELINK_SUPPORTED_100baseT_Full | 12458 ELINK_SUPPORTED_1000baseT_Full | 12459 ELINK_SUPPORTED_2500baseX_Full | 12460 ELINK_SUPPORTED_10000baseT_Full | 12461 ELINK_SUPPORTED_FIBRE | 12462 ELINK_SUPPORTED_Autoneg | 12463 ELINK_SUPPORTED_Pause | 12464 ELINK_SUPPORTED_Asym_Pause), 12465 /*.media_type = */ELINK_ETH_PHY_CX4, 12466 /*.ver_addr = */0, 12467 /*.req_flow_ctrl = */0, 12468 /*.req_line_speed = */0, 12469 /*.speed_cap_mask = */0, 12470 /*.req_duplex = */0, 12471 /*.rsrv = */0, 12472 #ifndef EXCLUDE_NON_COMMON_INIT 12473 /*.config_init = */elink_xgxs_config_init, 12474 /*.read_status = */elink_link_settings_status, 12475 /*.link_reset = */elink_int_link_reset, 12476 /*.config_loopback = */elink_set_xgxs_loopback, 12477 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12478 /*.hw_reset = */(hw_reset_t)NULL, 12479 /*.set_link_led = */(set_link_led_t)NULL, 12480 /*.phy_specific_func = */elink_xgxs_specific_func 12481 #endif 12482 }; 12483 #endif 12484 #ifndef EXCLUDE_WARPCORE 12485 static const struct elink_phy phy_warpcore = { 12486 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12487 /*.addr = */0xff, 12488 /*.def_md_devad = */0, 12489 /*.flags = */ELINK_FLAGS_TX_ERROR_CHECK, 12490 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12491 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12492 /*.mdio_ctrl = */0, 12493 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12494 ELINK_SUPPORTED_10baseT_Full | 12495 ELINK_SUPPORTED_100baseT_Half | 12496 ELINK_SUPPORTED_100baseT_Full | 12497 ELINK_SUPPORTED_1000baseT_Full | 12498 ELINK_SUPPORTED_10000baseT_Full | 12499 ELINK_SUPPORTED_20000baseKR2_Full | 12500 ELINK_SUPPORTED_20000baseMLD2_Full | 12501 ELINK_SUPPORTED_FIBRE | 12502 ELINK_SUPPORTED_Autoneg | 12503 ELINK_SUPPORTED_Pause | 12504 ELINK_SUPPORTED_Asym_Pause), 12505 /*.media_type = */ELINK_ETH_PHY_UNSPECIFIED, 12506 /*.ver_addr = */0, 12507 /*.req_flow_ctrl = */0, 12508 /*.req_line_speed = */0, 12509 /*.speed_cap_mask = */0, 12510 /* req_duplex = */0, 12511 /* rsrv = */0, 12512 #ifndef EXCLUDE_NON_COMMON_INIT 12513 /*.config_init = */elink_warpcore_config_init, 12514 /*.read_status = */elink_warpcore_read_status, 12515 /*.link_reset = */elink_warpcore_link_reset, 12516 /*.config_loopback = */elink_set_warpcore_loopback, 12517 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12518 /*.hw_reset = */elink_warpcore_hw_reset, 12519 /*.set_link_led = */(set_link_led_t)NULL, 12520 /*.phy_specific_func = */(phy_specific_func_t)NULL 12521 #endif 12522 }; 12523 12524 #endif /* #ifndef EXCLUDE_WARPCORE */ 12525 12526 #ifndef ELINK_EMUL_ONLY 12527 #ifndef EXCLUDE_SFX7101 12528 static const struct elink_phy phy_7101 = { 12529 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 12530 /*.addr = */0xff, 12531 /*.def_md_devad = */0, 12532 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ, 12533 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12534 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12535 /*.mdio_ctrl = */0, 12536 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12537 ELINK_SUPPORTED_TP | 12538 ELINK_SUPPORTED_Autoneg | 12539 ELINK_SUPPORTED_Pause | 12540 ELINK_SUPPORTED_Asym_Pause), 12541 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12542 /*.ver_addr = */0, 12543 /*.req_flow_ctrl = */0, 12544 /*.req_line_speed = */0, 12545 /*.speed_cap_mask = */0, 12546 /*.req_duplex = */0, 12547 /*.rsrv = */0, 12548 /*.config_init = */elink_7101_config_init, 12549 /*.read_status = */elink_7101_read_status, 12550 /*.link_reset = */elink_common_ext_link_reset, 12551 /*.config_loopback = */elink_7101_config_loopback, 12552 /*.format_fw_ver= */elink_7101_format_ver, 12553 /*.hw_reset = */elink_7101_hw_reset, 12554 /*.set_link_led = */elink_7101_set_link_led, 12555 /*.phy_specific_func = */(phy_specific_func_t)NULL 12556 }; 12557 #endif /* EXCLUDE_SFX7101 */ 12558 #ifndef EXCLUDE_BCM8727_BCM8073 12559 static const struct elink_phy phy_8073 = { 12560 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 12561 /*.addr = */0xff, 12562 /*.def_md_devad = */0, 12563 /*.flags = */0, 12564 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12565 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12566 /*.mdio_ctrl = */0, 12567 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12568 ELINK_SUPPORTED_2500baseX_Full | 12569 ELINK_SUPPORTED_1000baseT_Full | 12570 ELINK_SUPPORTED_FIBRE | 12571 ELINK_SUPPORTED_Autoneg | 12572 ELINK_SUPPORTED_Pause | 12573 ELINK_SUPPORTED_Asym_Pause), 12574 /*.media_type = */ELINK_ETH_PHY_KR, 12575 /*.ver_addr = */0, 12576 /*.req_flow_ctrl = */0, 12577 /*.req_line_speed = */0, 12578 /*.speed_cap_mask = */0, 12579 /*.req_duplex = */0, 12580 /*.rsrv = */0, 12581 #ifndef EXCLUDE_NON_COMMON_INIT 12582 /*.config_init = */elink_8073_config_init, 12583 /*.read_status = */elink_8073_read_status, 12584 /*.link_reset = */elink_8073_link_reset, 12585 /*.config_loopback = */(config_loopback_t)NULL, 12586 /*.format_fw_ver= */elink_format_ver, 12587 /*.hw_reset = */(hw_reset_t)NULL, 12588 /*.set_link_led = */(set_link_led_t)NULL, 12589 /*.phy_specific_func = */elink_8073_specific_func 12590 #endif 12591 }; 12592 #endif 12593 #ifndef EXCLUDE_BCM8705 12594 static const struct elink_phy phy_8705 = { 12595 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 12596 /*.addr = */0xff, 12597 /*.def_md_devad = */0, 12598 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12599 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12600 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12601 /*.mdio_ctrl = */0, 12602 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12603 ELINK_SUPPORTED_FIBRE | 12604 ELINK_SUPPORTED_Pause | 12605 ELINK_SUPPORTED_Asym_Pause), 12606 /*.media_type = */ELINK_ETH_PHY_XFP_FIBER, 12607 /*.ver_addr = */0, 12608 /*.req_flow_ctrl = */0, 12609 /*.req_line_speed = */0, 12610 /*.speed_cap_mask = */0, 12611 /*.req_duplex = */0, 12612 /*.rsrv = */0, 12613 /*.config_init = */elink_8705_config_init, 12614 /*.read_status = */elink_8705_read_status, 12615 /*.link_reset = */elink_common_ext_link_reset, 12616 /*.config_loopback = */(config_loopback_t)NULL, 12617 /*.format_fw_ver= */elink_null_format_ver, 12618 /*.hw_reset = */(hw_reset_t)NULL, 12619 /*.set_link_led = */(set_link_led_t)NULL, 12620 /*.phy_specific_func = */(phy_specific_func_t)NULL 12621 }; 12622 #endif /* EXCLUDE_BCM8705 */ 12623 #ifndef EXCLUDE_BCM87x6 12624 static const struct elink_phy phy_8706 = { 12625 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 12626 /*.addr = */0xff, 12627 /*.def_md_devad = */0, 12628 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12629 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12630 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12631 /*.mdio_ctrl = */0, 12632 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12633 ELINK_SUPPORTED_1000baseT_Full | 12634 ELINK_SUPPORTED_FIBRE | 12635 ELINK_SUPPORTED_Pause | 12636 ELINK_SUPPORTED_Asym_Pause), 12637 /*.media_type = */ELINK_ETH_PHY_SFPP_10G_FIBER, 12638 /*.ver_addr = */0, 12639 /*.req_flow_ctrl = */0, 12640 /*.req_line_speed = */0, 12641 /*.speed_cap_mask = */0, 12642 /*.req_duplex = */0, 12643 /*.rsrv = */0, 12644 /*.config_init = */elink_8706_config_init, 12645 /*.read_status = */elink_8706_read_status, 12646 /*.link_reset = */elink_common_ext_link_reset, 12647 /*.config_loopback = */(config_loopback_t)NULL, 12648 /*.format_fw_ver= */elink_format_ver, 12649 /*.hw_reset = */(hw_reset_t)NULL, 12650 /*.set_link_led = */(set_link_led_t)NULL, 12651 /*.phy_specific_func = */(phy_specific_func_t)NULL 12652 }; 12653 12654 static const struct elink_phy phy_8726 = { 12655 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 12656 /*.addr = */0xff, 12657 /*.def_md_devad = */0, 12658 /*.flags = */(ELINK_FLAGS_INIT_XGXS_FIRST | 12659 ELINK_FLAGS_TX_ERROR_CHECK), 12660 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12661 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12662 /*.mdio_ctrl = */0, 12663 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12664 ELINK_SUPPORTED_1000baseT_Full | 12665 ELINK_SUPPORTED_Autoneg | 12666 ELINK_SUPPORTED_FIBRE | 12667 ELINK_SUPPORTED_Pause | 12668 ELINK_SUPPORTED_Asym_Pause), 12669 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12670 /*.ver_addr = */0, 12671 /*.req_flow_ctrl = */0, 12672 /*.req_line_speed = */0, 12673 /*.speed_cap_mask = */0, 12674 /*.req_duplex = */0, 12675 /*.rsrv = */0, 12676 /*.config_init = */elink_8726_config_init, 12677 /*.read_status = */elink_8726_read_status, 12678 /*.link_reset = */elink_8726_link_reset, 12679 /*.config_loopback = */elink_8726_config_loopback, 12680 /*.format_fw_ver= */elink_format_ver, 12681 /*.hw_reset = */(hw_reset_t)NULL, 12682 /*.set_link_led = */(set_link_led_t)NULL, 12683 /*.phy_specific_func = */(phy_specific_func_t)NULL 12684 }; 12685 #endif /* #ifndef EXCLUDE_BCM87x6 */ 12686 12687 #ifndef EXCLUDE_BCM8727_BCM8073 12688 static const struct elink_phy phy_8727 = { 12689 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 12690 /*.addr = */0xff, 12691 /*.def_md_devad = */0, 12692 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12693 ELINK_FLAGS_TX_ERROR_CHECK), 12694 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12695 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12696 /*.mdio_ctrl = */0, 12697 /*.supported = */(ELINK_SUPPORTED_10000baseT_Full | 12698 ELINK_SUPPORTED_1000baseT_Full | 12699 ELINK_SUPPORTED_FIBRE | 12700 ELINK_SUPPORTED_Pause | 12701 ELINK_SUPPORTED_Asym_Pause), 12702 /*.media_type = */ELINK_ETH_PHY_NOT_PRESENT, 12703 /*.ver_addr = */0, 12704 /*.req_flow_ctrl = */0, 12705 /*.req_line_speed = */0, 12706 /*.speed_cap_mask = */0, 12707 /*.req_duplex = */0, 12708 /*.rsrv = */0, 12709 #ifndef EXCLUDE_NON_COMMON_INIT 12710 /*.config_init = */elink_8727_config_init, 12711 /*.read_status = */elink_8727_read_status, 12712 /*.link_reset = */elink_8727_link_reset, 12713 /*.config_loopback = */(config_loopback_t)NULL, 12714 /*.format_fw_ver= */elink_format_ver, 12715 /*.hw_reset = */elink_8727_hw_reset, 12716 /*.set_link_led = */elink_8727_set_link_led, 12717 /*.phy_specific_func = */elink_8727_specific_func 12718 #endif 12719 }; 12720 #endif 12721 #ifndef EXCLUDE_BCM8481 12722 static const struct elink_phy phy_8481 = { 12723 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 12724 /*.addr = */0xff, 12725 /*.def_md_devad = */0, 12726 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12727 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12728 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12729 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12730 /*.mdio_ctrl = */0, 12731 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12732 ELINK_SUPPORTED_10baseT_Full | 12733 ELINK_SUPPORTED_100baseT_Half | 12734 ELINK_SUPPORTED_100baseT_Full | 12735 ELINK_SUPPORTED_1000baseT_Full | 12736 ELINK_SUPPORTED_10000baseT_Full | 12737 ELINK_SUPPORTED_TP | 12738 ELINK_SUPPORTED_Autoneg | 12739 ELINK_SUPPORTED_Pause | 12740 ELINK_SUPPORTED_Asym_Pause), 12741 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12742 /*.ver_addr = */0, 12743 /*.req_flow_ctrl = */0, 12744 /*.req_line_speed = */0, 12745 /*.speed_cap_mask = */0, 12746 /*.req_duplex = */0, 12747 /*.rsrv = */0, 12748 #ifndef EXCLUDE_NON_COMMON_INIT 12749 /*.config_init = */elink_8481_config_init, 12750 /*.read_status = */elink_848xx_read_status, 12751 /*.link_reset = */elink_8481_link_reset, 12752 /*.config_loopback = */(config_loopback_t)NULL, 12753 /*.format_fw_ver= */elink_848xx_format_ver, 12754 /*.hw_reset = */elink_8481_hw_reset, 12755 /*.set_link_led = */elink_848xx_set_link_led, 12756 /*.phy_specific_func = */(phy_specific_func_t)NULL 12757 #endif 12758 }; 12759 12760 static const struct elink_phy phy_84823 = { 12761 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 12762 /*.addr = */0xff, 12763 /*.def_md_devad = */0, 12764 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12765 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12766 ELINK_FLAGS_TX_ERROR_CHECK), 12767 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12768 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12769 /*.mdio_ctrl = */0, 12770 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12771 ELINK_SUPPORTED_10baseT_Full | 12772 ELINK_SUPPORTED_100baseT_Half | 12773 ELINK_SUPPORTED_100baseT_Full | 12774 ELINK_SUPPORTED_1000baseT_Full | 12775 ELINK_SUPPORTED_10000baseT_Full | 12776 ELINK_SUPPORTED_TP | 12777 ELINK_SUPPORTED_Autoneg | 12778 ELINK_SUPPORTED_Pause | 12779 ELINK_SUPPORTED_Asym_Pause), 12780 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12781 /*.ver_addr = */0, 12782 /*.req_flow_ctrl = */0, 12783 /*.req_line_speed = */0, 12784 /*.speed_cap_mask = */0, 12785 /*.req_duplex = */0, 12786 /*.rsrv = */0, 12787 #ifndef EXCLUDE_NON_COMMON_INIT 12788 /*.config_init = */elink_848x3_config_init, 12789 /*.read_status = */elink_848xx_read_status, 12790 /*.link_reset = */elink_848x3_link_reset, 12791 /*.config_loopback = */(config_loopback_t)NULL, 12792 /*.format_fw_ver= */elink_848xx_format_ver, 12793 /*.hw_reset = */(hw_reset_t)NULL, 12794 /*.set_link_led = */elink_848xx_set_link_led, 12795 /*.phy_specific_func = */elink_848xx_specific_func 12796 #endif // #ifndef EXCLUDE_NON_COMMON_INIT 12797 }; 12798 #endif /* EXCLUDE_BCM8481 */ 12799 12800 #ifndef EXCLUDE_BCM84833 12801 static const struct elink_phy phy_84833 = { 12802 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12803 /*.addr = */0xff, 12804 /*.def_md_devad = */0, 12805 /*.flags = */(ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12806 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12807 ELINK_FLAGS_TX_ERROR_CHECK | 12808 ELINK_FLAGS_TEMPERATURE), 12809 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12810 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12811 /*.mdio_ctrl = */0, 12812 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12813 ELINK_SUPPORTED_100baseT_Full | 12814 ELINK_SUPPORTED_1000baseT_Full | 12815 ELINK_SUPPORTED_10000baseT_Full | 12816 ELINK_SUPPORTED_TP | 12817 ELINK_SUPPORTED_Autoneg | 12818 ELINK_SUPPORTED_Pause | 12819 ELINK_SUPPORTED_Asym_Pause), 12820 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12821 /*.ver_addr = */0, 12822 /*.req_flow_ctrl = */0, 12823 /*.req_line_speed = */0, 12824 /*.speed_cap_mask = */0, 12825 /*.req_duplex = */0, 12826 /*.rsrv = */0, 12827 #ifndef EXCLUDE_NON_COMMON_INIT 12828 /*.config_init = */elink_848x3_config_init, 12829 /*.read_status = */elink_848xx_read_status, 12830 /*.link_reset = */elink_848x3_link_reset, 12831 /*.config_loopback = */(config_loopback_t)NULL, 12832 /*.format_fw_ver= */elink_848xx_format_ver, 12833 /*.hw_reset = */elink_84833_hw_reset_phy, 12834 /*.set_link_led = */elink_848xx_set_link_led, 12835 /*.phy_specific_func = */elink_848xx_specific_func 12836 #endif 12837 }; 12838 12839 static const struct elink_phy phy_84834 = { 12840 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12841 /*.addr = */0xff, 12842 /*.def_md_devad = */0, 12843 /*.flags = */ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12844 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12845 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12846 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12847 /*.mdio_ctrl = */0, 12848 /*.supported = */(ELINK_SUPPORTED_100baseT_Half | 12849 ELINK_SUPPORTED_100baseT_Full | 12850 ELINK_SUPPORTED_1000baseT_Full | 12851 ELINK_SUPPORTED_10000baseT_Full | 12852 ELINK_SUPPORTED_TP | 12853 ELINK_SUPPORTED_Autoneg | 12854 ELINK_SUPPORTED_Pause | 12855 ELINK_SUPPORTED_Asym_Pause), 12856 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12857 /*.ver_addr = */0, 12858 /*.req_flow_ctrl = */0, 12859 /*.req_line_speed = */0, 12860 /*.speed_cap_mask = */0, 12861 /*.req_duplex = */0, 12862 /*.rsrv = */0, 12863 #ifndef EXCLUDE_NON_COMMON_INIT 12864 /*.config_init = */elink_848x3_config_init, 12865 /*.read_status = */elink_848xx_read_status, 12866 /*.link_reset = */elink_848x3_link_reset, 12867 /*.config_loopback = */(config_loopback_t)NULL, 12868 /*.format_fw_ver= */elink_848xx_format_ver, 12869 /*.hw_reset = */elink_84833_hw_reset_phy, 12870 /*.set_link_led = */elink_848xx_set_link_led, 12871 /*.phy_specific_func = */elink_848xx_specific_func 12872 #endif 12873 }; 12874 #endif // #ifndef EXCLUDE_BCM84833 12875 12876 #ifndef EXCLUDE_BCM54618SE 12877 static const struct elink_phy phy_54618se = { 12878 /*.type = */PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12879 /*.addr = */0xff, 12880 /*.def_md_devad = */0, 12881 /*.flags = */ELINK_FLAGS_INIT_XGXS_FIRST, 12882 /*.rx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12883 /*.tx_preemphasis = */{0xffff, 0xffff, 0xffff, 0xffff}, 12884 /*.mdio_ctrl = */0, 12885 /*.supported = */(ELINK_SUPPORTED_10baseT_Half | 12886 ELINK_SUPPORTED_10baseT_Full | 12887 ELINK_SUPPORTED_100baseT_Half | 12888 ELINK_SUPPORTED_100baseT_Full | 12889 ELINK_SUPPORTED_1000baseT_Full | 12890 ELINK_SUPPORTED_TP | 12891 ELINK_SUPPORTED_Autoneg | 12892 ELINK_SUPPORTED_Pause | 12893 ELINK_SUPPORTED_Asym_Pause), 12894 /*.media_type = */ELINK_ETH_PHY_BASE_T, 12895 /*.ver_addr = */0, 12896 /*.req_flow_ctrl = */0, 12897 /*.req_line_speed = */0, 12898 /*.speed_cap_mask = */0, 12899 /* req_duplex = */0, 12900 /* rsrv = */0, 12901 #ifndef EXCLUDE_NON_COMMON_INIT 12902 /*.config_init = */elink_54618se_config_init, 12903 /*.read_status = */elink_54618se_read_status, 12904 /*.link_reset = */elink_54618se_link_reset, 12905 /*.config_loopback = */elink_54618se_config_loopback, 12906 /*.format_fw_ver= */(format_fw_ver_t)NULL, 12907 /*.hw_reset = */(hw_reset_t)NULL, 12908 /*.set_link_led = */elink_5461x_set_link_led, 12909 /*.phy_specific_func = */elink_54618se_specific_func 12910 #endif 12911 }; 12912 #endif 12913 #endif /* ELINK_EMUL_ONLY */ 12914 /*****************************************************************/ 12915 /* */ 12916 /* Populate the phy according. Main function: elink_populate_phy */ 12917 /* */ 12918 /*****************************************************************/ 12919 12920 #ifndef EXCLUDE_COMMON_INIT 12921 static void elink_populate_preemphasis(struct elink_dev *cb, u32 shmem_base, 12922 struct elink_phy *phy, u8 port, 12923 u8 phy_index) 12924 { 12925 /* Get the 4 lanes xgxs config rx and tx */ 12926 u32 rx = 0, tx = 0, i; 12927 for (i = 0; i < 2; i++) { 12928 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in 12929 * the shmem. When num_phys is greater than 1, than this value 12930 * applies only to ELINK_EXT_PHY1 12931 */ 12932 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { 12933 rx = REG_RD(cb, shmem_base + 12934 OFFSETOF(struct shmem_region, 12935 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 12936 12937 tx = REG_RD(cb, shmem_base + 12938 OFFSETOF(struct shmem_region, 12939 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 12940 } else { 12941 rx = REG_RD(cb, shmem_base + 12942 OFFSETOF(struct shmem_region, 12943 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12944 12945 tx = REG_RD(cb, shmem_base + 12946 OFFSETOF(struct shmem_region, 12947 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12948 } 12949 12950 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 12951 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 12952 12953 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 12954 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 12955 } 12956 } 12957 12958 #ifndef ELINK_EMUL_ONLY 12959 static u32 elink_get_ext_phy_config(struct elink_dev *cb, u32 shmem_base, 12960 u8 phy_index, u8 port) 12961 { 12962 u32 ext_phy_config = 0; 12963 switch (phy_index) { 12964 case ELINK_EXT_PHY1: 12965 ext_phy_config = REG_RD(cb, shmem_base + 12966 OFFSETOF(struct shmem_region, 12967 dev_info.port_hw_config[port].external_phy_config)); 12968 break; 12969 case ELINK_EXT_PHY2: 12970 ext_phy_config = REG_RD(cb, shmem_base + 12971 OFFSETOF(struct shmem_region, 12972 dev_info.port_hw_config[port].external_phy_config2)); 12973 break; 12974 default: 12975 ELINK_DEBUG_P1(cb, "Invalid phy_index %d\n", phy_index); 12976 return ELINK_STATUS_ERROR; 12977 } 12978 12979 return ext_phy_config; 12980 } 12981 #endif /* ELINK_EMUL_ONLY */ 12982 static elink_status_t elink_populate_int_phy(struct elink_dev *cb, u32 shmem_base, u8 port, 12983 struct elink_phy *phy) 12984 { 12985 u32 phy_addr; 12986 u32 chip_id; 12987 u32 switch_cfg = (REG_RD(cb, shmem_base + 12988 OFFSETOF(struct shmem_region, 12989 dev_info.port_feature_config[port].link_config)) & 12990 PORT_FEATURE_CONNECTED_SWITCH_MASK); 12991 chip_id = (REG_RD(cb, MISC_REG_CHIP_NUM) << 16) | 12992 ((REG_RD(cb, MISC_REG_CHIP_REV) & 0xf) << 12); 12993 12994 ELINK_DEBUG_P1(cb, ":chip_id = 0x%x\n", chip_id); 12995 #ifndef EXCLUDE_WARPCORE 12996 if (ELINK_USES_WARPCORE(chip_id)) { 12997 u32 serdes_net_if; 12998 phy_addr = REG_RD(cb, 12999 MISC_REG_WC0_CTRL_PHY_ADDR); 13000 *phy = phy_warpcore; 13001 if (REG_RD(cb, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 13002 phy->flags |= ELINK_FLAGS_4_PORT_MODE; 13003 else 13004 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; 13005 /* Check Dual mode */ 13006 serdes_net_if = (REG_RD(cb, shmem_base + 13007 OFFSETOF(struct shmem_region, dev_info. 13008 port_hw_config[port].default_cfg)) & 13009 PORT_HW_CFG_NET_SERDES_IF_MASK); 13010 /* Set the appropriate supported and flags indications per 13011 * interface type of the chip 13012 */ 13013 switch (serdes_net_if) { 13014 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 13015 phy->supported &= (ELINK_SUPPORTED_10baseT_Half | 13016 ELINK_SUPPORTED_10baseT_Full | 13017 ELINK_SUPPORTED_100baseT_Half | 13018 ELINK_SUPPORTED_100baseT_Full | 13019 ELINK_SUPPORTED_1000baseT_Full | 13020 ELINK_SUPPORTED_FIBRE | 13021 ELINK_SUPPORTED_Autoneg | 13022 ELINK_SUPPORTED_Pause | 13023 ELINK_SUPPORTED_Asym_Pause); 13024 phy->media_type = ELINK_ETH_PHY_BASE_T; 13025 break; 13026 case PORT_HW_CFG_NET_SERDES_IF_XFI: 13027 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13028 ELINK_SUPPORTED_10000baseT_Full | 13029 ELINK_SUPPORTED_FIBRE | 13030 ELINK_SUPPORTED_Pause | 13031 ELINK_SUPPORTED_Asym_Pause); 13032 phy->media_type = ELINK_ETH_PHY_XFP_FIBER; 13033 break; 13034 case PORT_HW_CFG_NET_SERDES_IF_SFI: 13035 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13036 ELINK_SUPPORTED_10000baseT_Full | 13037 ELINK_SUPPORTED_FIBRE | 13038 ELINK_SUPPORTED_Pause | 13039 ELINK_SUPPORTED_Asym_Pause); 13040 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 13041 break; 13042 case PORT_HW_CFG_NET_SERDES_IF_KR: 13043 phy->media_type = ELINK_ETH_PHY_KR; 13044 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 13045 ELINK_SUPPORTED_10000baseT_Full | 13046 ELINK_SUPPORTED_FIBRE | 13047 ELINK_SUPPORTED_Autoneg | 13048 ELINK_SUPPORTED_Pause | 13049 ELINK_SUPPORTED_Asym_Pause); 13050 break; 13051 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 13052 phy->media_type = ELINK_ETH_PHY_KR; 13053 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13054 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | 13055 ELINK_SUPPORTED_FIBRE | 13056 ELINK_SUPPORTED_Pause | 13057 ELINK_SUPPORTED_Asym_Pause); 13058 break; 13059 case PORT_HW_CFG_NET_SERDES_IF_KR2: 13060 phy->media_type = ELINK_ETH_PHY_KR; 13061 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 13062 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | 13063 ELINK_SUPPORTED_10000baseT_Full | 13064 ELINK_SUPPORTED_1000baseT_Full | 13065 ELINK_SUPPORTED_Autoneg | 13066 ELINK_SUPPORTED_FIBRE | 13067 ELINK_SUPPORTED_Pause | 13068 ELINK_SUPPORTED_Asym_Pause); 13069 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13070 break; 13071 default: 13072 ELINK_DEBUG_P1(cb, "Unknown WC interface type 0x%x\n", 13073 serdes_net_if); 13074 break; 13075 } 13076 13077 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 13078 * was not set as expected. For B0, ECO will be enabled so there 13079 * won't be an issue there 13080 */ 13081 if (CHIP_REV(chip_id) == CHIP_REV_Ax) 13082 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; 13083 else 13084 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; 13085 } else 13086 #endif 13087 { 13088 switch (switch_cfg) { 13089 #ifndef EXCLUDE_SERDES 13090 case ELINK_SWITCH_CFG_1G: 13091 phy_addr = REG_RD(cb, 13092 NIG_REG_SERDES0_CTRL_PHY_ADDR + 13093 port * 0x10); 13094 *phy = phy_serdes; 13095 break; 13096 #endif /* #ifndef EXCLUDE_SERDES */ 13097 #ifndef EXCLUDE_XGXS 13098 case ELINK_SWITCH_CFG_10G: 13099 phy_addr = REG_RD(cb, 13100 NIG_REG_XGXS0_CTRL_PHY_ADDR + 13101 port * 0x18); 13102 *phy = phy_xgxs; 13103 break; 13104 #endif /* EXCLUDE_XGXS */ 13105 default: 13106 ELINK_DEBUG_P0(cb, "Invalid switch_cfg\n"); 13107 return ELINK_STATUS_ERROR; 13108 } 13109 } 13110 phy->addr = (u8)phy_addr; 13111 phy->mdio_ctrl = elink_get_emac_base(cb, 13112 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 13113 port); 13114 if (CHIP_IS_E2(chip_id)) 13115 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; 13116 else 13117 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; 13118 13119 ELINK_DEBUG_P3(cb, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 13120 port, phy->addr, phy->mdio_ctrl); 13121 13122 elink_populate_preemphasis(cb, shmem_base, phy, port, ELINK_INT_PHY); 13123 return ELINK_STATUS_OK; 13124 } 13125 13126 #ifndef ELINK_EMUL_ONLY 13127 static elink_status_t elink_populate_ext_phy(struct elink_dev *cb, 13128 u8 phy_index, 13129 u32 shmem_base, 13130 u32 shmem2_base, 13131 u8 port, 13132 struct elink_phy *phy) 13133 { 13134 u32 ext_phy_config, phy_type, config2; 13135 u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 13136 ext_phy_config = elink_get_ext_phy_config(cb, shmem_base, 13137 phy_index, port); 13138 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 13139 /* Select the phy type */ 13140 switch (phy_type) { 13141 #ifndef EXCLUDE_BCM8727_BCM8073 13142 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 13143 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 13144 *phy = phy_8073; 13145 break; 13146 #endif 13147 #ifndef EXCLUDE_BCM8705 13148 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 13149 *phy = phy_8705; 13150 break; 13151 #endif 13152 #ifndef EXCLUDE_BCM87x6 13153 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 13154 *phy = phy_8706; 13155 break; 13156 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 13157 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13158 *phy = phy_8726; 13159 break; 13160 #endif /* EXCLUDE_BCM87x6 */ 13161 #ifndef EXCLUDE_BCM8727_BCM8073 13162 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 13163 /* BCM8727_NOC => BCM8727 no over current */ 13164 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13165 *phy = phy_8727; 13166 phy->flags |= ELINK_FLAGS_NOC; 13167 break; 13168 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 13169 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 13170 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 13171 *phy = phy_8727; 13172 break; 13173 #endif 13174 #ifndef EXCLUDE_BCM8481 13175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 13176 *phy = phy_8481; 13177 break; 13178 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 13179 *phy = phy_84823; 13180 break; 13181 #endif 13182 #ifndef EXCLUDE_BCM84833 13183 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 13184 *phy = phy_84833; 13185 break; 13186 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 13187 *phy = phy_84834; 13188 break; 13189 #endif 13190 #ifndef EXCLUDE_BCM54618SE 13191 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 13192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 13193 *phy = phy_54618se; 13194 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 13195 phy->flags |= ELINK_FLAGS_EEE; 13196 break; 13197 #endif 13198 #ifndef EXCLUDE_SFX7101 13199 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 13200 *phy = phy_7101; 13201 break; 13202 #endif 13203 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 13204 *phy = phy_null; 13205 return ELINK_STATUS_ERROR; 13206 default: 13207 *phy = phy_null; 13208 /* In case external PHY wasn't found */ 13209 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 13210 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 13211 return ELINK_STATUS_ERROR; 13212 return ELINK_STATUS_OK; 13213 } 13214 13215 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); 13216 elink_populate_preemphasis(cb, shmem_base, phy, port, phy_index); 13217 13218 /* The shmem address of the phy version is located on different 13219 * structures. In case this structure is too old, do not set 13220 * the address 13221 */ 13222 config2 = REG_RD(cb, shmem_base + OFFSETOF(struct shmem_region, 13223 dev_info.shared_hw_config.config2)); 13224 if (phy_index == ELINK_EXT_PHY1) { 13225 phy->ver_addr = shmem_base + OFFSETOF(struct shmem_region, 13226 port_mb[port].ext_phy_fw_version); 13227 13228 /* Check specific mdc mdio settings */ 13229 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 13230 mdc_mdio_access = config2 & 13231 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 13232 } else { 13233 u32 size = REG_RD(cb, shmem2_base); 13234 13235 if (size > 13236 OFFSETOF(struct shmem2_region, ext_phy_fw_version2)) { 13237 phy->ver_addr = shmem2_base + 13238 OFFSETOF(struct shmem2_region, 13239 ext_phy_fw_version2[port]); 13240 } 13241 /* Check specific mdc mdio settings */ 13242 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 13243 mdc_mdio_access = (config2 & 13244 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 13245 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 13246 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 13247 } 13248 phy->mdio_ctrl = elink_get_emac_base(cb, mdc_mdio_access, port); 13249 13250 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 13251 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 13252 (phy->ver_addr)) { 13253 /* Remove 100Mb link supported for BCM84833/4 when phy fw 13254 * version lower than or equal to 1.39 13255 */ 13256 u32 raw_ver = REG_RD(cb, phy->ver_addr); 13257 if (((raw_ver & 0x7F) <= 39) && 13258 (((raw_ver & 0xF80) >> 7) <= 1)) 13259 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | 13260 ELINK_SUPPORTED_100baseT_Full); 13261 } 13262 13263 ELINK_DEBUG_P3(cb, "phy_type 0x%x port %d found in index %d\n", 13264 phy_type, port, phy_index); 13265 ELINK_DEBUG_P2(cb, " addr=0x%x, mdio_ctl=0x%x\n", 13266 phy->addr, phy->mdio_ctrl); 13267 return ELINK_STATUS_OK; 13268 } 13269 #endif /* ELINK_EMUL_ONLY */ 13270 13271 static elink_status_t elink_populate_phy(struct elink_dev *cb, u8 phy_index, u32 shmem_base, 13272 u32 shmem2_base, u8 port, struct elink_phy *phy) 13273 { 13274 elink_status_t status = ELINK_STATUS_OK; 13275 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 13276 if (phy_index == ELINK_INT_PHY) 13277 return elink_populate_int_phy(cb, shmem_base, port, phy); 13278 #ifndef ELINK_EMUL_ONLY 13279 status = elink_populate_ext_phy(cb, phy_index, shmem_base, shmem2_base, 13280 port, phy); 13281 #endif /* ELINK_EMUL_ONLY */ 13282 return status; 13283 } 13284 13285 static void elink_phy_def_cfg(struct elink_params *params, 13286 struct elink_phy *phy, 13287 u8 phy_index) 13288 { 13289 struct elink_dev *cb = params->cb; 13290 u32 link_config; 13291 /* Populate the default phy configuration for MF mode */ 13292 if (phy_index == ELINK_EXT_PHY2) { 13293 link_config = REG_RD(cb, params->shmem_base + 13294 OFFSETOF(struct shmem_region, dev_info. 13295 port_feature_config[params->port].link_config2)); 13296 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13297 OFFSETOF(struct shmem_region, 13298 dev_info. 13299 port_hw_config[params->port].speed_capability_mask2)); 13300 } else { 13301 link_config = REG_RD(cb, params->shmem_base + 13302 OFFSETOF(struct shmem_region, dev_info. 13303 port_feature_config[params->port].link_config)); 13304 phy->speed_cap_mask = REG_RD(cb, params->shmem_base + 13305 OFFSETOF(struct shmem_region, 13306 dev_info. 13307 port_hw_config[params->port].speed_capability_mask)); 13308 } 13309 ELINK_DEBUG_P3(cb, 13310 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 13311 phy_index, link_config, phy->speed_cap_mask); 13312 13313 phy->req_duplex = DUPLEX_FULL; 13314 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 13315 case PORT_FEATURE_LINK_SPEED_10M_HALF: 13316 phy->req_duplex = DUPLEX_HALF; 13317 /* FALLTHROUGH */ 13318 case PORT_FEATURE_LINK_SPEED_10M_FULL: 13319 phy->req_line_speed = ELINK_SPEED_10; 13320 break; 13321 case PORT_FEATURE_LINK_SPEED_100M_HALF: 13322 phy->req_duplex = DUPLEX_HALF; 13323 /* FALLTHROUGH */ 13324 case PORT_FEATURE_LINK_SPEED_100M_FULL: 13325 phy->req_line_speed = ELINK_SPEED_100; 13326 break; 13327 case PORT_FEATURE_LINK_SPEED_1G: 13328 phy->req_line_speed = ELINK_SPEED_1000; 13329 break; 13330 case PORT_FEATURE_LINK_SPEED_2_5G: 13331 phy->req_line_speed = ELINK_SPEED_2500; 13332 break; 13333 case PORT_FEATURE_LINK_SPEED_10G_CX4: 13334 phy->req_line_speed = ELINK_SPEED_10000; 13335 break; 13336 default: 13337 phy->req_line_speed = ELINK_SPEED_AUTO_NEG; 13338 break; 13339 } 13340 13341 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 13342 case PORT_FEATURE_FLOW_CONTROL_AUTO: 13343 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; 13344 break; 13345 case PORT_FEATURE_FLOW_CONTROL_TX: 13346 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; 13347 break; 13348 case PORT_FEATURE_FLOW_CONTROL_RX: 13349 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; 13350 break; 13351 case PORT_FEATURE_FLOW_CONTROL_BOTH: 13352 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; 13353 break; 13354 default: 13355 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; 13356 break; 13357 } 13358 } 13359 #endif /* EXCLUDE_COMMON_INIT */ 13360 13361 u32 elink_phy_selection(struct elink_params *params) 13362 { 13363 u32 phy_config_swapped, prio_cfg; 13364 u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 13365 13366 phy_config_swapped = params->multi_phy_config & 13367 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13368 13369 prio_cfg = params->multi_phy_config & 13370 PORT_HW_CFG_PHY_SELECTION_MASK; 13371 13372 if (phy_config_swapped) { 13373 switch (prio_cfg) { 13374 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 13375 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 13376 break; 13377 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 13378 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 13379 break; 13380 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 13381 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 13382 break; 13383 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 13384 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 13385 break; 13386 } 13387 } else 13388 return_cfg = prio_cfg; 13389 13390 return return_cfg; 13391 } 13392 13393 #ifndef EXCLUDE_COMMON_INIT 13394 elink_status_t elink_phy_probe(struct elink_params *params) 13395 { 13396 u8 phy_index, actual_phy_idx; 13397 u32 phy_config_swapped, sync_offset, media_types; 13398 struct elink_dev *cb = params->cb; 13399 struct elink_phy *phy; 13400 params->num_phys = 0; 13401 ELINK_DEBUG_P0(cb, "Begin phy probe\n"); 13402 #ifdef ELINK_INCLUDE_EMUL 13403 if (CHIP_REV_IS_EMUL(params->chip_id)) 13404 return ELINK_STATUS_OK; 13405 #endif 13406 phy_config_swapped = params->multi_phy_config & 13407 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13408 13409 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 13410 phy_index++) { 13411 actual_phy_idx = phy_index; 13412 if (phy_config_swapped) { 13413 if (phy_index == ELINK_EXT_PHY1) 13414 actual_phy_idx = ELINK_EXT_PHY2; 13415 else if (phy_index == ELINK_EXT_PHY2) 13416 actual_phy_idx = ELINK_EXT_PHY1; 13417 } 13418 ELINK_DEBUG_P3(cb, "phy_config_swapped %x, phy_index %x," 13419 " actual_phy_idx %x\n", phy_config_swapped, 13420 phy_index, actual_phy_idx); 13421 phy = ¶ms->phy[actual_phy_idx]; 13422 if (elink_populate_phy(cb, phy_index, params->shmem_base, 13423 params->shmem2_base, params->port, 13424 phy) != ELINK_STATUS_OK) { 13425 params->num_phys = 0; 13426 ELINK_DEBUG_P1(cb, "phy probe failed in phy index %d\n", 13427 phy_index); 13428 for (phy_index = ELINK_INT_PHY; 13429 phy_index < ELINK_MAX_PHYS; 13430 phy_index++) 13431 *phy = phy_null; 13432 return ELINK_STATUS_ERROR; 13433 } 13434 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 13435 break; 13436 13437 if (params->feature_config_flags & 13438 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 13439 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13440 13441 if (!(params->feature_config_flags & 13442 ELINK_FEATURE_CONFIG_MT_SUPPORT)) 13443 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; 13444 13445 sync_offset = params->shmem_base + 13446 OFFSETOF(struct shmem_region, 13447 dev_info.port_hw_config[params->port].media_type); 13448 media_types = REG_RD(cb, sync_offset); 13449 13450 /* Update media type for non-PMF sync only for the first time 13451 * In case the media type changes afterwards, it will be updated 13452 * using the update_status function 13453 */ 13454 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 13455 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13456 actual_phy_idx))) == 0) { 13457 media_types |= ((phy->media_type & 13458 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 13459 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13460 actual_phy_idx)); 13461 } 13462 REG_WR(cb, sync_offset, media_types); 13463 13464 elink_phy_def_cfg(params, phy, phy_index); 13465 params->num_phys++; 13466 } 13467 13468 ELINK_DEBUG_P1(cb, "End phy probe. #phys found %x\n", params->num_phys); 13469 return ELINK_STATUS_OK; 13470 } 13471 #endif /* EXCLUDE_COMMON_INIT */ 13472 13473 #ifdef ELINK_AUX_POWER 13474 u8 elink_phy_is_temperature_support(struct elink_params *params) 13475 { 13476 u8 phy_index; 13477 struct elink_phy *phy; 13478 13479 /* This function check that at least one of the phy's supports 13480 * temperature read. 13481 */ 13482 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 13483 phy_index++) { 13484 phy = ¶ms->phy[phy_index]; 13485 if (phy->flags & ELINK_FLAGS_TEMPERATURE) 13486 return 1; 13487 } 13488 return 0; 13489 } 13490 #endif /* ELINK_AUX_POWER */ 13491 #ifdef ELINK_INCLUDE_EMUL 13492 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, 13493 struct elink_vars *vars) 13494 { 13495 struct elink_dev *cb = params->cb; 13496 vars->line_speed = params->req_line_speed[0]; 13497 /* In case link speed is auto, set speed the highest as possible */ 13498 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { 13499 if (params->feature_config_flags & 13500 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) 13501 vars->line_speed = ELINK_SPEED_2500; 13502 else if (elink_is_4_port_mode(cb)) 13503 vars->line_speed = ELINK_SPEED_10000; 13504 else 13505 vars->line_speed = ELINK_SPEED_20000; 13506 } 13507 if (vars->line_speed < ELINK_SPEED_10000) { 13508 if ((params->feature_config_flags & 13509 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { 13510 ELINK_DEBUG_P1(cb, "Invalid line speed %d while UMAC is" 13511 " disabled!\n", params->req_line_speed[0]); 13512 return ELINK_STATUS_ERROR; 13513 } 13514 switch (vars->line_speed) { 13515 case ELINK_SPEED_10: 13516 vars->link_status = ELINK_LINK_10TFD; 13517 break; 13518 case ELINK_SPEED_100: 13519 vars->link_status = ELINK_LINK_100TXFD; 13520 break; 13521 case ELINK_SPEED_1000: 13522 vars->link_status = ELINK_LINK_1000TFD; 13523 break; 13524 case ELINK_SPEED_2500: 13525 vars->link_status = ELINK_LINK_2500TFD; 13526 break; 13527 default: 13528 ELINK_DEBUG_P1(cb, "Invalid line speed %d for UMAC\n", 13529 vars->line_speed); 13530 return ELINK_STATUS_ERROR; 13531 } 13532 vars->link_status |= LINK_STATUS_LINK_UP; 13533 13534 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13535 elink_umac_enable(params, vars, 1); 13536 else 13537 elink_umac_enable(params, vars, 0); 13538 } else { 13539 /* Link speed >= 10000 requires XMAC enabled */ 13540 if (params->feature_config_flags & 13541 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { 13542 ELINK_DEBUG_P1(cb, "Invalid line speed %d while XMAC is" 13543 " disabled!\n", params->req_line_speed[0]); 13544 return ELINK_STATUS_ERROR; 13545 } 13546 /* Check link speed */ 13547 switch (vars->line_speed) { 13548 case ELINK_SPEED_10000: 13549 vars->link_status = ELINK_LINK_10GTFD; 13550 break; 13551 case ELINK_SPEED_20000: 13552 vars->link_status = ELINK_LINK_20GTFD; 13553 break; 13554 default: 13555 ELINK_DEBUG_P1(cb, "Invalid line speed %d for XMAC\n", 13556 vars->line_speed); 13557 return ELINK_STATUS_ERROR; 13558 } 13559 vars->link_status |= LINK_STATUS_LINK_UP; 13560 if (params->loopback_mode == ELINK_LOOPBACK_XMAC) 13561 elink_xmac_enable(params, vars, 1); 13562 else 13563 elink_xmac_enable(params, vars, 0); 13564 } 13565 return ELINK_STATUS_OK; 13566 } 13567 13568 static elink_status_t elink_init_emul(struct elink_params *params, 13569 struct elink_vars *vars) 13570 { 13571 struct elink_dev *cb = params->cb; 13572 if (CHIP_IS_E3(params->chip_id)) { 13573 if (elink_init_e3_emul_mac(params, vars) != 13574 ELINK_STATUS_OK) 13575 return ELINK_STATUS_ERROR; 13576 } else { 13577 if (params->feature_config_flags & 13578 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { 13579 vars->line_speed = ELINK_SPEED_1000; 13580 vars->link_status = (LINK_STATUS_LINK_UP | 13581 ELINK_LINK_1000XFD); 13582 if (params->loopback_mode == 13583 ELINK_LOOPBACK_EMAC) 13584 elink_emac_enable(params, vars, 1); 13585 else 13586 elink_emac_enable(params, vars, 0); 13587 } else { 13588 vars->line_speed = ELINK_SPEED_10000; 13589 vars->link_status = (LINK_STATUS_LINK_UP | 13590 ELINK_LINK_10GTFD); 13591 if (params->loopback_mode == 13592 ELINK_LOOPBACK_BMAC) 13593 elink_bmac_enable(params, vars, 1, 1); 13594 else 13595 elink_bmac_enable(params, vars, 0, 1); 13596 } 13597 } 13598 vars->link_up = 1; 13599 vars->duplex = DUPLEX_FULL; 13600 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13601 13602 #ifndef ELINK_AUX_POWER 13603 if (CHIP_IS_E1X(params->chip_id)) 13604 elink_pbf_update(params, vars->flow_ctrl, 13605 vars->line_speed); 13606 #endif /* ELINK_AUX_POWER */ 13607 /* Disable drain */ 13608 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13609 13610 /* update shared memory */ 13611 elink_update_mng(params, vars->link_status); 13612 return ELINK_STATUS_OK; 13613 } 13614 #endif // ELINK_INCLUDE_EMUL 13615 #ifdef ELINK_INCLUDE_FPGA 13616 static elink_status_t elink_init_fpga(struct elink_params *params, 13617 struct elink_vars *vars) 13618 { 13619 /* Enable on E1.5 FPGA */ 13620 struct elink_dev *cb = params->cb; 13621 vars->duplex = DUPLEX_FULL; 13622 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13623 if (!(CHIP_IS_E1(params->chip_id))) { 13624 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | 13625 ELINK_FLOW_CTRL_RX); 13626 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | 13627 LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 13628 } 13629 if (CHIP_IS_E3(params->chip_id)) { 13630 vars->line_speed = params->req_line_speed[0]; 13631 switch (vars->line_speed) { 13632 case ELINK_SPEED_AUTO_NEG: 13633 vars->line_speed = ELINK_SPEED_2500; 13634 case ELINK_SPEED_2500: 13635 vars->link_status = ELINK_LINK_2500TFD; 13636 break; 13637 case ELINK_SPEED_1000: 13638 vars->link_status = ELINK_LINK_1000XFD; 13639 break; 13640 case ELINK_SPEED_100: 13641 vars->link_status = ELINK_LINK_100TXFD; 13642 break; 13643 case ELINK_SPEED_10: 13644 vars->link_status = ELINK_LINK_10TFD; 13645 break; 13646 default: 13647 ELINK_DEBUG_P1(cb, "Invalid link speed %d\n", 13648 params->req_line_speed[0]); 13649 return ELINK_STATUS_ERROR; 13650 } 13651 vars->link_status |= LINK_STATUS_LINK_UP; 13652 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13653 elink_umac_enable(params, vars, 1); 13654 else 13655 elink_umac_enable(params, vars, 0); 13656 } else { 13657 vars->line_speed = ELINK_SPEED_10000; 13658 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); 13659 if (params->loopback_mode == ELINK_LOOPBACK_EMAC) 13660 elink_emac_enable(params, vars, 1); 13661 else 13662 elink_emac_enable(params, vars, 0); 13663 } 13664 vars->link_up = 1; 13665 13666 #ifndef ELINK_AUX_POWER 13667 if (CHIP_IS_E1X(params->chip_id)) 13668 elink_pbf_update(params, vars->flow_ctrl, 13669 vars->line_speed); 13670 #endif /* ELINK_AUX_POWER */ 13671 /* Disable drain */ 13672 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13673 13674 /* Update shared memory */ 13675 elink_update_mng(params, vars->link_status); 13676 return ELINK_STATUS_OK; 13677 } 13678 #endif // #ifdef ELINK_INCLUDE_FPGA 13679 #ifdef ELINK_INCLUDE_LOOPBACK 13680 static void elink_init_bmac_loopback(struct elink_params *params, 13681 struct elink_vars *vars) 13682 { 13683 struct elink_dev *cb = params->cb; 13684 vars->link_up = 1; 13685 vars->line_speed = ELINK_SPEED_10000; 13686 vars->duplex = DUPLEX_FULL; 13687 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13688 vars->mac_type = ELINK_MAC_TYPE_BMAC; 13689 13690 vars->phy_flags = PHY_XGXS_FLAG; 13691 13692 elink_xgxs_deassert(params); 13693 13694 /* Set bmac loopback */ 13695 elink_bmac_enable(params, vars, 1, 1); 13696 13697 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13698 } 13699 13700 static void elink_init_emac_loopback(struct elink_params *params, 13701 struct elink_vars *vars) 13702 { 13703 struct elink_dev *cb = params->cb; 13704 vars->link_up = 1; 13705 vars->line_speed = ELINK_SPEED_1000; 13706 vars->duplex = DUPLEX_FULL; 13707 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13708 vars->mac_type = ELINK_MAC_TYPE_EMAC; 13709 13710 vars->phy_flags = PHY_XGXS_FLAG; 13711 13712 elink_xgxs_deassert(params); 13713 /* Set bmac loopback */ 13714 elink_emac_enable(params, vars, 1); 13715 elink_emac_program(params, vars); 13716 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13717 } 13718 13719 static void elink_init_xmac_loopback(struct elink_params *params, 13720 struct elink_vars *vars) 13721 { 13722 struct elink_dev *cb = params->cb; 13723 vars->link_up = 1; 13724 if (!params->req_line_speed[0]) 13725 vars->line_speed = ELINK_SPEED_10000; 13726 else 13727 vars->line_speed = params->req_line_speed[0]; 13728 vars->duplex = DUPLEX_FULL; 13729 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13730 vars->mac_type = ELINK_MAC_TYPE_XMAC; 13731 vars->phy_flags = PHY_XGXS_FLAG; 13732 /* Set WC to loopback mode since link is required to provide clock 13733 * to the XMAC in 20G mode 13734 */ 13735 elink_set_aer_mmd(params, ¶ms->phy[0]); 13736 elink_warpcore_reset_lane(cb, ¶ms->phy[0], 0); 13737 params->phy[ELINK_INT_PHY].config_loopback( 13738 ¶ms->phy[ELINK_INT_PHY], 13739 params); 13740 13741 elink_xmac_enable(params, vars, 1); 13742 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13743 } 13744 13745 static void elink_init_umac_loopback(struct elink_params *params, 13746 struct elink_vars *vars) 13747 { 13748 struct elink_dev *cb = params->cb; 13749 vars->link_up = 1; 13750 vars->line_speed = ELINK_SPEED_1000; 13751 vars->duplex = DUPLEX_FULL; 13752 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13753 vars->mac_type = ELINK_MAC_TYPE_UMAC; 13754 vars->phy_flags = PHY_XGXS_FLAG; 13755 elink_umac_enable(params, vars, 1); 13756 13757 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13758 } 13759 13760 static void elink_init_xgxs_loopback(struct elink_params *params, 13761 struct elink_vars *vars) 13762 { 13763 struct elink_dev *cb = params->cb; 13764 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 13765 vars->link_up = 1; 13766 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13767 vars->duplex = DUPLEX_FULL; 13768 if (params->req_line_speed[0] == ELINK_SPEED_1000) 13769 vars->line_speed = ELINK_SPEED_1000; 13770 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || 13771 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) 13772 vars->line_speed = ELINK_SPEED_20000; 13773 else 13774 vars->line_speed = ELINK_SPEED_10000; 13775 13776 if (!ELINK_USES_WARPCORE(params->chip_id)) 13777 elink_xgxs_deassert(params); 13778 elink_link_initialize(params, vars); 13779 13780 if (params->req_line_speed[0] == ELINK_SPEED_1000) { 13781 if (ELINK_USES_WARPCORE(params->chip_id)) 13782 elink_umac_enable(params, vars, 0); 13783 else { 13784 elink_emac_program(params, vars); 13785 elink_emac_enable(params, vars, 0); 13786 } 13787 } else { 13788 if (ELINK_USES_WARPCORE(params->chip_id)) 13789 elink_xmac_enable(params, vars, 0); 13790 else 13791 elink_bmac_enable(params, vars, 0, 1); 13792 } 13793 13794 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { 13795 /* Set 10G XGXS loopback */ 13796 int_phy->config_loopback(int_phy, params); 13797 } else { 13798 /* Set external phy loopback */ 13799 u8 phy_index; 13800 for (phy_index = ELINK_EXT_PHY1; 13801 phy_index < params->num_phys; phy_index++) 13802 if (params->phy[phy_index].config_loopback) 13803 params->phy[phy_index].config_loopback( 13804 ¶ms->phy[phy_index], 13805 params); 13806 } 13807 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13808 13809 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 13810 } 13811 #endif // #ifdef ELINK_INCLUDE_LOOPBACK 13812 13813 #ifdef ELINK_ENHANCEMENTS 13814 void elink_set_rx_filter(struct elink_params *params, u8 en) 13815 { 13816 struct elink_dev *cb = params->cb; 13817 u8 val = en * 0x1F; 13818 13819 /* Open / close the gate between the NIG and the BRB */ 13820 if (!CHIP_IS_E1X(params->chip_id)) 13821 val |= en * 0x20; 13822 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 13823 13824 if (!CHIP_IS_E1(params->chip_id)) { 13825 REG_WR(cb, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 13826 en*0x3); 13827 } 13828 13829 REG_WR(cb, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 13830 NIG_REG_LLH0_BRB1_NOT_MCP), en); 13831 } 13832 #endif /* #ifdef ELINK_ENHANCEMENTS */ 13833 #ifndef EXCLUDE_NON_COMMON_INIT 13834 static elink_status_t elink_avoid_link_flap(struct elink_params *params, 13835 struct elink_vars *vars) 13836 { 13837 u32 phy_idx; 13838 u32 dont_clear_stat, lfa_sts; 13839 struct elink_dev *cb = params->cb; 13840 13841 elink_set_mdio_emac_per_phy(cb, params); 13842 /* Sync the link parameters */ 13843 elink_link_status_update(params, vars); 13844 13845 /* 13846 * The module verification was already done by previous link owner, 13847 * so this call is meant only to get warning message 13848 */ 13849 13850 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { 13851 struct elink_phy *phy = ¶ms->phy[phy_idx]; 13852 if (phy->phy_specific_func) { 13853 ELINK_DEBUG_P0(cb, "Calling PHY specific func\n"); 13854 phy->phy_specific_func(phy, params, ELINK_PHY_INIT); 13855 } 13856 #ifdef ELINK_ENHANCEMENTS 13857 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || 13858 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || 13859 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) 13860 elink_verify_sfp_module(phy, params); 13861 #endif 13862 } 13863 lfa_sts = REG_RD(cb, params->lfa_base + 13864 OFFSETOF(struct shmem_lfa, 13865 lfa_sts)); 13866 13867 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 13868 13869 /* Re-enable the NIG/MAC */ 13870 if (CHIP_IS_E3(params->chip_id)) { 13871 #ifndef EXCLUDE_WARPCORE 13872 if (!dont_clear_stat) { 13873 REG_WR(cb, GRCBASE_MISC + 13874 MISC_REGISTERS_RESET_REG_2_CLEAR, 13875 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13876 params->port)); 13877 REG_WR(cb, GRCBASE_MISC + 13878 MISC_REGISTERS_RESET_REG_2_SET, 13879 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13880 params->port)); 13881 } 13882 if (vars->line_speed < ELINK_SPEED_10000) 13883 elink_umac_enable(params, vars, 0); 13884 else 13885 elink_xmac_enable(params, vars, 0); 13886 #endif 13887 } else { 13888 #ifndef EXCLUDE_BMAC2 13889 if (vars->line_speed < ELINK_SPEED_10000) 13890 elink_emac_enable(params, vars, 0); 13891 else 13892 elink_bmac_enable(params, vars, 0, !dont_clear_stat); 13893 #endif 13894 } 13895 13896 /* Increment LFA count */ 13897 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 13898 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 13899 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 13900 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 13901 /* Clear link flap reason */ 13902 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13903 13904 REG_WR(cb, params->lfa_base + 13905 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 13906 13907 /* Disable NIG DRAIN */ 13908 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13909 13910 /* Enable interrupts */ 13911 elink_link_int_enable(params); 13912 return ELINK_STATUS_OK; 13913 } 13914 13915 static void elink_cannot_avoid_link_flap(struct elink_params *params, 13916 struct elink_vars *vars, 13917 int lfa_status) 13918 { 13919 u32 lfa_sts, cfg_idx, tmp_val; 13920 struct elink_dev *cb = params->cb; 13921 13922 elink_link_reset(params, vars, 1); 13923 13924 if (!params->lfa_base) 13925 return; 13926 /* Store the new link parameters */ 13927 REG_WR(cb, params->lfa_base + 13928 OFFSETOF(struct shmem_lfa, req_duplex), 13929 params->req_duplex[0] | (params->req_duplex[1] << 16)); 13930 13931 REG_WR(cb, params->lfa_base + 13932 OFFSETOF(struct shmem_lfa, req_flow_ctrl), 13933 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 13934 13935 REG_WR(cb, params->lfa_base + 13936 OFFSETOF(struct shmem_lfa, req_line_speed), 13937 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 13938 13939 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 13940 REG_WR(cb, params->lfa_base + 13941 OFFSETOF(struct shmem_lfa, 13942 speed_cap_mask[cfg_idx]), 13943 params->speed_cap_mask[cfg_idx]); 13944 } 13945 13946 tmp_val = REG_RD(cb, params->lfa_base + 13947 OFFSETOF(struct shmem_lfa, additional_config)); 13948 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 13949 tmp_val |= params->req_fc_auto_adv; 13950 13951 REG_WR(cb, params->lfa_base + 13952 OFFSETOF(struct shmem_lfa, additional_config), tmp_val); 13953 13954 lfa_sts = REG_RD(cb, params->lfa_base + 13955 OFFSETOF(struct shmem_lfa, lfa_sts)); 13956 13957 /* Clear the "Don't Clear Statistics" bit, and set reason */ 13958 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 13959 13960 /* Set link flap reason */ 13961 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13962 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 13963 LFA_LINK_FLAP_REASON_OFFSET); 13964 13965 /* Increment link flap counter */ 13966 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 13967 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 13968 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 13969 << LINK_FLAP_COUNT_OFFSET)); 13970 REG_WR(cb, params->lfa_base + 13971 OFFSETOF(struct shmem_lfa, lfa_sts), lfa_sts); 13972 /* Proceed with regular link initialization */ 13973 } 13974 13975 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars) 13976 { 13977 int lfa_status; 13978 struct elink_dev *cb = params->cb; 13979 ELINK_DEBUG_P0(cb, "Phy Initialization started\n"); 13980 ELINK_DEBUG_P2(cb, "(1) req_speed %d, req_flowctrl %d\n", 13981 params->req_line_speed[0], params->req_flow_ctrl[0]); 13982 ELINK_DEBUG_P2(cb, "(2) req_speed %d, req_flowctrl %d\n", 13983 params->req_line_speed[1], params->req_flow_ctrl[1]); 13984 ELINK_DEBUG_P1(cb, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 13985 vars->link_status = 0; 13986 vars->phy_link_up = 0; 13987 vars->link_up = 0; 13988 vars->line_speed = 0; 13989 vars->duplex = DUPLEX_FULL; 13990 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13991 vars->mac_type = ELINK_MAC_TYPE_NONE; 13992 vars->phy_flags = 0; 13993 vars->check_kr2_recovery_cnt = 0; 13994 params->link_flags = ELINK_PHY_INITIALIZED; 13995 #ifdef ELINK_ENHANCEMENTS 13996 /* Driver opens NIG-BRB filters */ 13997 elink_set_rx_filter(params, 1); 13998 #endif 13999 elink_chng_link_count(params, 1); 14000 /* Check if link flap can be avoided */ 14001 lfa_status = elink_check_lfa(params); 14002 14003 if (lfa_status == 0) { 14004 ELINK_DEBUG_P0(cb, "Link Flap Avoidance in progress\n"); 14005 return elink_avoid_link_flap(params, vars); 14006 } 14007 14008 ELINK_DEBUG_P1(cb, "Cannot avoid link flap lfa_sta=0x%x\n", 14009 lfa_status); 14010 elink_cannot_avoid_link_flap(params, vars, lfa_status); 14011 14012 /* Disable attentions */ 14013 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 14014 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14015 ELINK_NIG_MASK_XGXS0_LINK10G | 14016 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14017 ELINK_NIG_MASK_MI_INT)); 14018 #ifdef ELINK_INCLUDE_EMUL 14019 if (!(params->feature_config_flags & 14020 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) 14021 #endif //ELINK_INCLUDE_EMUL 14022 14023 elink_emac_init(params, vars); 14024 14025 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 14026 vars->link_status |= LINK_STATUS_PFC_ENABLED; 14027 14028 if ((params->num_phys == 0) && 14029 !CHIP_REV_IS_SLOW(params->chip_id)) { 14030 ELINK_DEBUG_P0(cb, "No phy found for initialization !!\n"); 14031 return ELINK_STATUS_ERROR; 14032 } 14033 set_phy_vars(params, vars); 14034 14035 ELINK_DEBUG_P1(cb, "Num of phys on board: %d\n", params->num_phys); 14036 #ifdef ELINK_INCLUDE_FPGA 14037 if (CHIP_REV_IS_FPGA(params->chip_id)) { 14038 return elink_init_fpga(params, vars); 14039 } else 14040 #endif /* ELINK_INCLUDE_FPGA */ 14041 #ifdef ELINK_INCLUDE_EMUL 14042 if (CHIP_REV_IS_EMUL(params->chip_id)) { 14043 return elink_init_emul(params, vars); 14044 } else 14045 #endif /* ELINK_INCLUDE_EMUL */ 14046 #ifdef ELINK_INCLUDE_LOOPBACK 14047 switch (params->loopback_mode) { 14048 case ELINK_LOOPBACK_BMAC: 14049 elink_init_bmac_loopback(params, vars); 14050 break; 14051 case ELINK_LOOPBACK_EMAC: 14052 elink_init_emac_loopback(params, vars); 14053 break; 14054 case ELINK_LOOPBACK_XMAC: 14055 elink_init_xmac_loopback(params, vars); 14056 break; 14057 case ELINK_LOOPBACK_UMAC: 14058 elink_init_umac_loopback(params, vars); 14059 break; 14060 case ELINK_LOOPBACK_XGXS: 14061 case ELINK_LOOPBACK_EXT_PHY: 14062 elink_init_xgxs_loopback(params, vars); 14063 break; 14064 default: 14065 #endif /* ELINK_INCLUDE_LOOPBACK */ 14066 #ifndef EXCLUDE_XGXS 14067 if (!CHIP_IS_E3(params->chip_id)) { 14068 if (params->switch_cfg == ELINK_SWITCH_CFG_10G) 14069 elink_xgxs_deassert(params); 14070 #ifndef EXCLUDE_SERDES 14071 else 14072 elink_serdes_deassert(cb, params->port); 14073 #endif // EXCLUDE_SERDES 14074 } 14075 #endif /* EXCLUDE_XGXS */ 14076 elink_link_initialize(params, vars); 14077 MSLEEP(cb, 30); 14078 elink_link_int_enable(params); 14079 #ifdef ELINK_INCLUDE_LOOPBACK 14080 break; 14081 } 14082 #endif // ELINK_INCLUDE_LOOPBACK 14083 elink_update_mng(params, vars->link_status); 14084 14085 #ifndef EXCLUDE_WARPCORE 14086 elink_update_mng_eee(params, vars->eee_status); 14087 #endif /* #ifndef EXCLUDE_BCM84833 */ 14088 return ELINK_STATUS_OK; 14089 } 14090 14091 #ifndef EXCLUDE_LINK_RESET 14092 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 14093 u8 reset_ext_phy) 14094 { 14095 struct elink_dev *cb = params->cb; 14096 u8 phy_index, port = params->port, clear_latch_ind = 0; 14097 ELINK_DEBUG_P1(cb, "Resetting the link of port %d\n", port); 14098 /* Disable attentions */ 14099 vars->link_status = 0; 14100 elink_chng_link_count(params, 1); 14101 elink_update_mng(params, vars->link_status); 14102 #ifndef EXCLUDE_WARPCORE 14103 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 14104 SHMEM_EEE_ACTIVE_BIT); 14105 elink_update_mng_eee(params, vars->eee_status); 14106 #endif /* #ifndef EXCLUDE_BCM84833 */ 14107 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 14108 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14109 ELINK_NIG_MASK_XGXS0_LINK10G | 14110 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14111 ELINK_NIG_MASK_MI_INT)); 14112 14113 /* Activate nig drain */ 14114 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 14115 14116 /* Disable nig egress interface */ 14117 if (!CHIP_IS_E3(params->chip_id)) { 14118 REG_WR(cb, NIG_REG_BMAC0_OUT_EN + port*4, 0); 14119 REG_WR(cb, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 14120 } 14121 14122 #ifdef ELINK_INCLUDE_EMUL 14123 /* Stop BigMac rx */ 14124 if (!(params->feature_config_flags & 14125 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) 14126 #endif // ELINK_INCLUDE_EMUL 14127 #if !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14128 if (!CHIP_IS_E3(params->chip_id)) 14129 elink_set_bmac_rx(cb, params->chip_id, port, 0); 14130 #endif // !defined(EXCLUDE_BMAC2) && !defined(EXCLUDE_BMAC1) 14131 #ifndef EXCLUDE_WARPCORE 14132 #ifdef ELINK_INCLUDE_EMUL 14133 /* Stop XMAC/UMAC rx */ 14134 if (!(params->feature_config_flags & 14135 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) 14136 #endif // ELINK_INCLUDE_EMUL 14137 if (CHIP_IS_E3(params->chip_id) && 14138 !CHIP_REV_IS_FPGA(params->chip_id)) { 14139 elink_set_xmac_rxtx(params, 0); 14140 elink_set_umac_rxtx(params, 0); 14141 } 14142 #endif // EXCLUDE_WARPCORE 14143 /* Disable emac */ 14144 if (!CHIP_IS_E3(params->chip_id)) 14145 REG_WR(cb, NIG_REG_NIG_EMAC0_EN + port*4, 0); 14146 14147 MSLEEP(cb, 10); 14148 /* The PHY reset is controlled by GPIO 1 14149 * Hold it as vars low 14150 */ 14151 /* Clear link led */ 14152 elink_set_mdio_emac_per_phy(cb, params); 14153 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 14154 14155 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(params->chip_id))) { 14156 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 14157 phy_index++) { 14158 if (params->phy[phy_index].link_reset) { 14159 elink_set_aer_mmd(params, 14160 ¶ms->phy[phy_index]); 14161 params->phy[phy_index].link_reset( 14162 ¶ms->phy[phy_index], 14163 params); 14164 } 14165 if (params->phy[phy_index].flags & 14166 ELINK_FLAGS_REARM_LATCH_SIGNAL) 14167 clear_latch_ind = 1; 14168 } 14169 } 14170 14171 if (clear_latch_ind) { 14172 /* Clear latching indication */ 14173 elink_rearm_latch_signal(cb, port, 0); 14174 elink_bits_dis(cb, NIG_REG_LATCH_BC_0 + port*4, 14175 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 14176 } 14177 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14178 if (!CHIP_REV_IS_SLOW(params->chip_id)) 14179 #endif 14180 if (params->phy[ELINK_INT_PHY].link_reset) 14181 params->phy[ELINK_INT_PHY].link_reset( 14182 ¶ms->phy[ELINK_INT_PHY], params); 14183 14184 /* Disable nig ingress interface */ 14185 if (!CHIP_IS_E3(params->chip_id)) { 14186 /* Reset BigMac */ 14187 REG_WR(cb, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 14188 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 14189 REG_WR(cb, NIG_REG_BMAC0_IN_EN + port*4, 0); 14190 REG_WR(cb, NIG_REG_EMAC0_IN_EN + port*4, 0); 14191 } else { 14192 #ifndef EXCLUDE_WARPCORE 14193 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 14194 elink_set_xumac_nig(params, 0, 0); 14195 if (REG_RD(cb, MISC_REG_RESET_REG_2) & 14196 MISC_REGISTERS_RESET_REG_2_XMAC) 14197 REG_WR(cb, xmac_base + XMAC_REG_CTRL, 14198 XMAC_CTRL_REG_SOFT_RESET); 14199 #endif // EXCLUDE_WARPCORE 14200 } 14201 vars->link_up = 0; 14202 vars->phy_flags = 0; 14203 return ELINK_STATUS_OK; 14204 } 14205 #endif // EXCLUDE_LINK_RESET 14206 #ifndef ELINK_AUX_POWER 14207 elink_status_t elink_lfa_reset(struct elink_params *params, 14208 struct elink_vars *vars) 14209 { 14210 struct elink_dev *cb = params->cb; 14211 vars->link_up = 0; 14212 vars->phy_flags = 0; 14213 params->link_flags &= ~ELINK_PHY_INITIALIZED; 14214 if (!params->lfa_base) 14215 return elink_link_reset(params, vars, 1); 14216 /* 14217 * Activate NIG drain so that during this time the device won't send 14218 * anything while it is unable to response. 14219 */ 14220 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14221 14222 /* 14223 * Close gracefully the gate from BMAC to NIG such that no half packets 14224 * are passed. 14225 */ 14226 if (!CHIP_IS_E3(params->chip_id)) 14227 elink_set_bmac_rx(cb, params->chip_id, params->port, 0); 14228 14229 if (CHIP_IS_E3(params->chip_id)) { 14230 elink_set_xmac_rxtx(params, 0); 14231 elink_set_umac_rxtx(params, 0); 14232 } 14233 /* Wait 10ms for the pipe to clean up*/ 14234 MSLEEP(cb, 10); 14235 14236 #ifdef ELINK_ENHANCEMENTS 14237 /* Clean the NIG-BRB using the network filters in a way that will 14238 * not cut a packet in the middle. 14239 */ 14240 elink_set_rx_filter(params, 0); 14241 #endif 14242 14243 /* 14244 * Re-open the gate between the BMAC and the NIG, after verifying the 14245 * gate to the BRB is closed, otherwise packets may arrive to the 14246 * firmware before driver had initialized it. The target is to achieve 14247 * minimum management protocol down time. 14248 */ 14249 if (!CHIP_IS_E3(params->chip_id)) 14250 elink_set_bmac_rx(cb, params->chip_id, params->port, 1); 14251 14252 if (CHIP_IS_E3(params->chip_id)) { 14253 elink_set_xmac_rxtx(params, 1); 14254 elink_set_umac_rxtx(params, 1); 14255 } 14256 /* Disable NIG drain */ 14257 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14258 return ELINK_STATUS_OK; 14259 } 14260 #endif /* ELINK_AUX_POWER */ 14261 #endif // EXCLUDE_NON_COMMON_INIT 14262 14263 /****************************************************************************/ 14264 /* Common function */ 14265 /****************************************************************************/ 14266 #ifndef EXCLUDE_COMMON_INIT 14267 #ifndef ELINK_EMUL_ONLY 14268 #ifndef EXCLUDE_BCM8727_BCM8073 14269 static elink_status_t elink_8073_common_init_phy(struct elink_dev *cb, 14270 u32 shmem_base_path[], 14271 u32 shmem2_base_path[], u8 phy_index, 14272 u32 chip_id) 14273 { 14274 struct elink_phy phy[PORT_MAX]; 14275 struct elink_phy *phy_blk[PORT_MAX]; 14276 u16 val; 14277 s8 port = 0; 14278 s8 port_of_path = 0; 14279 u32 swap_val, swap_override; 14280 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14281 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14282 port ^= (swap_val && swap_override); 14283 elink_ext_phy_hw_reset(cb, port); 14284 /* PART1 - Reset both phys */ 14285 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14286 u32 shmem_base, shmem2_base; 14287 /* In E2, same phy is using for port0 of the two paths */ 14288 if (CHIP_IS_E1X(chip_id)) { 14289 shmem_base = shmem_base_path[0]; 14290 shmem2_base = shmem2_base_path[0]; 14291 port_of_path = port; 14292 } else { 14293 shmem_base = shmem_base_path[port]; 14294 shmem2_base = shmem2_base_path[port]; 14295 port_of_path = 0; 14296 } 14297 14298 /* Extract the ext phy address for the port */ 14299 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14300 port_of_path, &phy[port]) != 14301 ELINK_STATUS_OK) { 14302 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14303 return ELINK_STATUS_ERROR; 14304 } 14305 /* Disable attentions */ 14306 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14307 port_of_path*4, 14308 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14309 ELINK_NIG_MASK_XGXS0_LINK10G | 14310 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14311 ELINK_NIG_MASK_MI_INT)); 14312 14313 /* Need to take the phy out of low power mode in order 14314 * to write to access its registers 14315 */ 14316 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14317 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14318 port); 14319 14320 /* Reset the phy */ 14321 elink_cl45_write(cb, &phy[port], 14322 MDIO_PMA_DEVAD, 14323 MDIO_PMA_REG_CTRL, 14324 1<<15); 14325 } 14326 14327 /* Add delay of 150ms after reset */ 14328 MSLEEP(cb, 150); 14329 14330 if (phy[PORT_0].addr & 0x1) { 14331 phy_blk[PORT_0] = &(phy[PORT_1]); 14332 phy_blk[PORT_1] = &(phy[PORT_0]); 14333 } else { 14334 phy_blk[PORT_0] = &(phy[PORT_0]); 14335 phy_blk[PORT_1] = &(phy[PORT_1]); 14336 } 14337 14338 /* PART2 - Download firmware to both phys */ 14339 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14340 if (CHIP_IS_E1X(chip_id)) 14341 port_of_path = port; 14342 else 14343 port_of_path = 0; 14344 14345 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14346 phy_blk[port]->addr); 14347 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14348 port_of_path)) 14349 return ELINK_STATUS_ERROR; 14350 14351 /* Only set bit 10 = 1 (Tx power down) */ 14352 elink_cl45_read(cb, phy_blk[port], 14353 MDIO_PMA_DEVAD, 14354 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14355 14356 /* Phase1 of TX_POWER_DOWN reset */ 14357 elink_cl45_write(cb, phy_blk[port], 14358 MDIO_PMA_DEVAD, 14359 MDIO_PMA_REG_TX_POWER_DOWN, 14360 (val | 1<<10)); 14361 } 14362 14363 /* Toggle Transmitter: Power down and then up with 600ms delay 14364 * between 14365 */ 14366 MSLEEP(cb, 600); 14367 14368 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 14369 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14370 /* Phase2 of POWER_DOWN_RESET */ 14371 /* Release bit 10 (Release Tx power down) */ 14372 elink_cl45_read(cb, phy_blk[port], 14373 MDIO_PMA_DEVAD, 14374 MDIO_PMA_REG_TX_POWER_DOWN, &val); 14375 14376 elink_cl45_write(cb, phy_blk[port], 14377 MDIO_PMA_DEVAD, 14378 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 14379 MSLEEP(cb, 15); 14380 14381 /* Read modify write the SPI-ROM version select register */ 14382 elink_cl45_read(cb, phy_blk[port], 14383 MDIO_PMA_DEVAD, 14384 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 14385 elink_cl45_write(cb, phy_blk[port], 14386 MDIO_PMA_DEVAD, 14387 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 14388 14389 /* set GPIO2 back to LOW */ 14390 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_2, 14391 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 14392 } 14393 return ELINK_STATUS_OK; 14394 } 14395 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14396 #ifndef EXCLUDE_BCM87x6 14397 static elink_status_t elink_8726_common_init_phy(struct elink_dev *cb, 14398 u32 shmem_base_path[], 14399 u32 shmem2_base_path[], u8 phy_index, 14400 u32 chip_id) 14401 { 14402 u32 val; 14403 s8 port; 14404 struct elink_phy phy; 14405 /* Use port1 because of the static port-swap */ 14406 /* Enable the module detection interrupt */ 14407 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 14408 val |= ((1<<MISC_REGISTERS_GPIO_3)| 14409 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 14410 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 14411 14412 elink_ext_phy_hw_reset(cb, 0); 14413 MSLEEP(cb, 5); 14414 for (port = 0; port < PORT_MAX; port++) { 14415 u32 shmem_base, shmem2_base; 14416 14417 /* In E2, same phy is using for port0 of the two paths */ 14418 if (CHIP_IS_E1X(chip_id)) { 14419 shmem_base = shmem_base_path[0]; 14420 shmem2_base = shmem2_base_path[0]; 14421 } else { 14422 shmem_base = shmem_base_path[port]; 14423 shmem2_base = shmem2_base_path[port]; 14424 } 14425 /* Extract the ext phy address for the port */ 14426 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14427 port, &phy) != 14428 ELINK_STATUS_OK) { 14429 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14430 return ELINK_STATUS_ERROR; 14431 } 14432 14433 /* Reset phy*/ 14434 elink_cl45_write(cb, &phy, 14435 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 14436 14437 14438 /* Set fault module detected LED on */ 14439 ELINK_SET_GPIO(cb, MISC_REGISTERS_GPIO_0, 14440 MISC_REGISTERS_GPIO_HIGH, 14441 port); 14442 } 14443 14444 return ELINK_STATUS_OK; 14445 } 14446 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14447 #ifndef EXCLUDE_BCM8727_BCM8073 14448 static void elink_get_ext_phy_reset_gpio(struct elink_dev *cb, u32 shmem_base, 14449 u8 *io_gpio, u8 *io_port) 14450 { 14451 14452 u32 phy_gpio_reset = REG_RD(cb, shmem_base + 14453 OFFSETOF(struct shmem_region, 14454 dev_info.port_hw_config[PORT_0].default_cfg)); 14455 switch (phy_gpio_reset) { 14456 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 14457 *io_gpio = 0; 14458 *io_port = 0; 14459 break; 14460 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 14461 *io_gpio = 1; 14462 *io_port = 0; 14463 break; 14464 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 14465 *io_gpio = 2; 14466 *io_port = 0; 14467 break; 14468 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 14469 *io_gpio = 3; 14470 *io_port = 0; 14471 break; 14472 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 14473 *io_gpio = 0; 14474 *io_port = 1; 14475 break; 14476 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 14477 *io_gpio = 1; 14478 *io_port = 1; 14479 break; 14480 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 14481 *io_gpio = 2; 14482 *io_port = 1; 14483 break; 14484 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 14485 *io_gpio = 3; 14486 *io_port = 1; 14487 break; 14488 default: 14489 /* Don't override the io_gpio and io_port */ 14490 break; 14491 } 14492 } 14493 14494 static elink_status_t elink_8727_common_init_phy(struct elink_dev *cb, 14495 u32 shmem_base_path[], 14496 u32 shmem2_base_path[], u8 phy_index, 14497 u32 chip_id) 14498 { 14499 s8 port, reset_gpio; 14500 u32 swap_val, swap_override; 14501 struct elink_phy phy[PORT_MAX]; 14502 struct elink_phy *phy_blk[PORT_MAX]; 14503 s8 port_of_path; 14504 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 14505 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 14506 14507 reset_gpio = MISC_REGISTERS_GPIO_1; 14508 port = 1; 14509 14510 /* Retrieve the reset gpio/port which control the reset. 14511 * Default is GPIO1, PORT1 14512 */ 14513 elink_get_ext_phy_reset_gpio(cb, shmem_base_path[0], 14514 (u8 *)&reset_gpio, (u8 *)&port); 14515 14516 /* Calculate the port based on port swap */ 14517 port ^= (swap_val && swap_override); 14518 14519 /* Initiate PHY reset*/ 14520 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 14521 port); 14522 MSLEEP(cb, 1); 14523 ELINK_SET_GPIO(cb, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14524 port); 14525 14526 MSLEEP(cb, 5); 14527 14528 /* PART1 - Reset both phys */ 14529 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14530 u32 shmem_base, shmem2_base; 14531 14532 /* In E2, same phy is using for port0 of the two paths */ 14533 if (CHIP_IS_E1X(chip_id)) { 14534 shmem_base = shmem_base_path[0]; 14535 shmem2_base = shmem2_base_path[0]; 14536 port_of_path = port; 14537 } else { 14538 shmem_base = shmem_base_path[port]; 14539 shmem2_base = shmem2_base_path[port]; 14540 port_of_path = 0; 14541 } 14542 14543 /* Extract the ext phy address for the port */ 14544 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 14545 port_of_path, &phy[port]) != 14546 ELINK_STATUS_OK) { 14547 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14548 return ELINK_STATUS_ERROR; 14549 } 14550 /* disable attentions */ 14551 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + 14552 port_of_path*4, 14553 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14554 ELINK_NIG_MASK_XGXS0_LINK10G | 14555 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14556 ELINK_NIG_MASK_MI_INT)); 14557 14558 14559 /* Reset the phy */ 14560 elink_cl45_write(cb, &phy[port], 14561 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 14562 } 14563 14564 /* Add delay of 150ms after reset */ 14565 MSLEEP(cb, 150); 14566 if (phy[PORT_0].addr & 0x1) { 14567 phy_blk[PORT_0] = &(phy[PORT_1]); 14568 phy_blk[PORT_1] = &(phy[PORT_0]); 14569 } else { 14570 phy_blk[PORT_0] = &(phy[PORT_0]); 14571 phy_blk[PORT_1] = &(phy[PORT_1]); 14572 } 14573 /* PART2 - Download firmware to both phys */ 14574 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14575 if (CHIP_IS_E1X(chip_id)) 14576 port_of_path = port; 14577 else 14578 port_of_path = 0; 14579 ELINK_DEBUG_P1(cb, "Loading spirom for phy address 0x%x\n", 14580 phy_blk[port]->addr); 14581 if (elink_8073_8727_external_rom_boot(cb, phy_blk[port], 14582 port_of_path)) 14583 return ELINK_STATUS_ERROR; 14584 /* Disable PHY transmitter output */ 14585 elink_cl45_write(cb, phy_blk[port], 14586 MDIO_PMA_DEVAD, 14587 MDIO_PMA_REG_TX_DISABLE, 1); 14588 14589 } 14590 return ELINK_STATUS_OK; 14591 } 14592 #endif /* EXCLUDE_BCM8727_BCM8073 */ 14593 14594 #ifndef EXCLUDE_BCM84833 14595 static elink_status_t elink_84833_common_init_phy(struct elink_dev *cb, 14596 u32 shmem_base_path[], 14597 u32 shmem2_base_path[], 14598 u8 phy_index, 14599 u32 chip_id) 14600 { 14601 u8 reset_gpios; 14602 reset_gpios = elink_84833_get_reset_gpios(cb, shmem_base_path, chip_id); 14603 #ifndef EDEBUG 14604 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 14605 USLEEP(cb, 10); 14606 ELINK_SET_MULT_GPIO(cb, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 14607 ELINK_DEBUG_P1(cb, "84833 reset pulse on pin values 0x%x\n", 14608 reset_gpios); 14609 #endif 14610 return ELINK_STATUS_OK; 14611 } 14612 #ifndef EXCLUDE_FROM_BNX2X 14613 static elink_status_t elink_84833_pre_init_phy(struct elink_dev *cb, 14614 struct elink_phy *phy, 14615 u8 port) 14616 { 14617 u16 val, cnt; 14618 /* Wait for FW completing its initialization. */ 14619 for (cnt = 0; cnt < 1500; cnt++) { 14620 elink_cl45_read(cb, phy, 14621 MDIO_PMA_DEVAD, 14622 MDIO_PMA_REG_CTRL, &val); 14623 if (!(val & (1<<15))) 14624 break; 14625 MSLEEP(cb, 1); 14626 } 14627 if (cnt >= 1500) { 14628 ELINK_DEBUG_P0(cb, "84833 reset timeout\n"); 14629 return ELINK_STATUS_ERROR; 14630 } 14631 14632 /* Put the port in super isolate mode. */ 14633 elink_cl45_read(cb, phy, 14634 MDIO_CTL_DEVAD, 14635 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val); 14636 val |= MDIO_84833_SUPER_ISOLATE; 14637 elink_cl45_write(cb, phy, 14638 MDIO_CTL_DEVAD, 14639 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val); 14640 14641 /* Save spirom version */ 14642 elink_save_848xx_spirom_version(phy, cb, port); 14643 return ELINK_STATUS_OK; 14644 } 14645 14646 elink_status_t elink_pre_init_phy(struct elink_dev *cb, 14647 u32 shmem_base, 14648 u32 shmem2_base, 14649 u32 chip_id, 14650 u8 port) 14651 { 14652 elink_status_t rc = ELINK_STATUS_OK; 14653 struct elink_phy phy; 14654 if (elink_populate_phy(cb, ELINK_EXT_PHY1, shmem_base, shmem2_base, 14655 port, &phy) != ELINK_STATUS_OK) { 14656 ELINK_DEBUG_P0(cb, "populate_phy failed\n"); 14657 return ELINK_STATUS_ERROR; 14658 } 14659 elink_set_mdio_clk(cb, chip_id, phy.mdio_ctrl); 14660 switch (phy.type) { 14661 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14662 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14663 rc = elink_84833_pre_init_phy(cb, &phy, port); 14664 break; 14665 default: 14666 break; 14667 } 14668 return rc; 14669 } 14670 #endif /* EXCLUDE_FROM_BNX2X */ 14671 #endif /* EXCLUDE_BCM84833 */ 14672 static elink_status_t elink_ext_phy_common_init(struct elink_dev *cb, u32 shmem_base_path[], 14673 u32 shmem2_base_path[], u8 phy_index, 14674 u32 ext_phy_type, u32 chip_id) 14675 { 14676 elink_status_t rc = ELINK_STATUS_OK; 14677 14678 switch (ext_phy_type) { 14679 #ifndef EXCLUDE_BCM8727_BCM8073 14680 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 14681 rc = elink_8073_common_init_phy(cb, shmem_base_path, 14682 shmem2_base_path, 14683 phy_index, chip_id); 14684 break; 14685 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 14686 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 14687 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 14688 rc = elink_8727_common_init_phy(cb, shmem_base_path, 14689 shmem2_base_path, 14690 phy_index, chip_id); 14691 break; 14692 14693 #endif 14694 #ifndef EXCLUDE_BCM87x6 14695 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 14696 /* GPIO1 affects both ports, so there's need to pull 14697 * it for single port alone 14698 */ 14699 rc = elink_8726_common_init_phy(cb, shmem_base_path, 14700 shmem2_base_path, 14701 phy_index, chip_id); 14702 break; 14703 #endif /* #ifndef EXCLUDE_BCM87x6 */ 14704 #ifndef EXCLUDE_BCM84833 14705 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14706 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14707 /* GPIO3's are linked, and so both need to be toggled 14708 * to obtain required 2us pulse. 14709 */ 14710 rc = elink_84833_common_init_phy(cb, shmem_base_path, 14711 shmem2_base_path, 14712 phy_index, chip_id); 14713 break; 14714 #endif 14715 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 14716 rc = ELINK_STATUS_ERROR; 14717 break; 14718 default: 14719 ELINK_DEBUG_P1(cb, 14720 "ext_phy 0x%x common init not required\n", 14721 ext_phy_type); 14722 break; 14723 } 14724 14725 if (rc != ELINK_STATUS_OK) 14726 elink_cb_event_log(cb, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," 14727 // " Port %d\n", 14728 14729 return rc; 14730 } 14731 14732 #ifdef INCLUDE_WARPCORE_UC_LOAD 14733 static elink_status_t elink_warpcore_common_init(struct elink_dev *cb, 14734 u32 shmem_base_path[], 14735 u32 shmem2_base_path[], 14736 u8 phy_index, 14737 u32 chip_id, 14738 u8 one_port_enabled) 14739 { 14740 struct elink_phy phy; 14741 u32 wc_lane_config; 14742 u16 val; 14743 elink_status_t rc; 14744 14745 REG_WR(cb, MISC_REG_LCPLL_E40_PWRDWN, 0); 14746 /* Procedure to bring the LCPLL out of reset. */ 14747 MSLEEP(cb, 1); 14748 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_ANA, 1); 14749 MSLEEP(cb, 1); 14750 REG_WR(cb, MISC_REG_LCPLL_E40_RESETB_DIG, 1); 14751 14752 ELINK_DEBUG_P0(cb, "Resetting Warpcore\n"); 14753 14754 if (elink_reset_warpcore(cb) != ELINK_STATUS_OK) 14755 return ELINK_STATUS_ERROR; 14756 14757 /* Extract the ext phy address for the port */ 14758 if (elink_populate_phy(cb, phy_index, shmem_base_path[0], 14759 shmem2_base_path[0], 14760 0, &phy) != ELINK_STATUS_OK) { 14761 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 14762 return ELINK_STATUS_ERROR; 14763 } 14764 14765 /* Set WC to use CL45 */ 14766 REG_WR(cb, MISC_REG_WC0_CTRL_MD_ST, 0); 14767 /* Set swap lanes and polarity */ 14768 wc_lane_config = REG_RD(cb, shmem_base_path[0] + 14769 OFFSETOF(struct shmem_region, dev_info. 14770 shared_hw_config.wc_lane_config)); 14771 14772 /* Power down warpcore lanes */ 14773 if (one_port_enabled) 14774 elink_warpcore_powerdown_secondport_lanes(cb, &phy); 14775 14776 /* Disable sequencer */ 14777 elink_warpcore_sequencer(cb, &phy, 0); 14778 14779 elink_warpcore_set_lane_swap(cb, &phy, wc_lane_config); 14780 elink_warpcore_set_lane_polarity(cb, &phy, wc_lane_config); 14781 14782 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) 14783 elink_warpcore_set_dual_mode(cb, &phy, shmem_base_path[0]); 14784 else 14785 elink_warpcore_set_quad_mode(cb, &phy); 14786 14787 /* Load Warpcore microcode */ 14788 rc = elink_warpcore_load_uc(cb, &phy); 14789 if (rc != ELINK_STATUS_OK) 14790 return rc; 14791 14792 /* RX traffic and TX traffic requires clock sync. 14793 * When transmiting we send data + clock to the Warpcore. 14794 * This clock is provided by lane 0 of the Warpcore. 14795 * So we need to configure this lane to supply us the correct clock 14796 * which will be use for transmit on all lanes 14797 */ 14798 14799 CL22_WR_OVER_CL45(cb, &phy, MDIO_REG_BANK_AER_BLOCK, 14800 MDIO_AER_BLOCK_AER_REG, 0); 14801 elink_cl45_read(cb, &phy, MDIO_WC_DEVAD, 14802 MDIO_WC_REG_XGXS_X2_CONTROL2, &val); 14803 val &= 0xDE1F; 14804 if (phy.flags & ELINK_FLAGS_WC_DUAL_MODE) { 14805 val |= (1<<11); 14806 val |= (9<<5); 14807 /* To force tx_wclk33 to txckp[0] */ 14808 if (phy.supported & ELINK_SUPPORTED_20000baseKR2_Full) 14809 val |= (1<<13); 14810 14811 /* Dual mode - lanes 0,1 use same clocks/resets - from lane 0 14812 * Lanes 2,3 use same clocks/resets - from lane 2 14813 */ 14814 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14815 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 14816 } else 14817 val |= 0x2800; 14818 14819 elink_cl45_write(cb, &phy, MDIO_WC_DEVAD, 14820 MDIO_WC_REG_XGXS_X2_CONTROL2, val); 14821 14822 /* Enable sequencer */ 14823 elink_warpcore_sequencer(cb, &phy, 1); 14824 14825 return ELINK_STATUS_OK; 14826 } 14827 14828 #endif /* INCLUDE_WARPCORE_UC_LOAD */ 14829 #endif /* ELINK_EMUL_ONLY */ 14830 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[], 14831 u32 shmem2_base_path[], u32 chip_id, 14832 u8 one_port_enabled) 14833 { 14834 elink_status_t rc = ELINK_STATUS_OK; 14835 u32 phy_ver, val; 14836 #ifndef ELINK_EMUL_ONLY 14837 u8 phy_index = 0; 14838 u32 ext_phy_type, ext_phy_config; 14839 #endif 14840 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14841 if (CHIP_REV_IS_EMUL(chip_id) || CHIP_REV_IS_FPGA(chip_id)) 14842 return ELINK_STATUS_OK; 14843 #endif 14844 14845 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC0); 14846 elink_set_mdio_clk(cb, chip_id, GRCBASE_EMAC1); 14847 ELINK_DEBUG_P0(cb, "Begin common phy init\n"); 14848 if (CHIP_IS_E3(chip_id)) { 14849 /* Enable EPIO */ 14850 val = REG_RD(cb, MISC_REG_GEN_PURP_HWG); 14851 REG_WR(cb, MISC_REG_GEN_PURP_HWG, val | 1); 14852 } 14853 #ifndef ELINK_EMUL_ONLY 14854 /* Check if common init was already done */ 14855 phy_ver = REG_RD(cb, shmem_base_path[0] + 14856 OFFSETOF(struct shmem_region, 14857 port_mb[PORT_0].ext_phy_fw_version)); 14858 if (phy_ver) { 14859 ELINK_DEBUG_P1(cb, "Not doing common init; phy ver is 0x%x\n", 14860 phy_ver); 14861 return ELINK_STATUS_OK; 14862 } 14863 14864 #ifdef INCLUDE_WARPCORE_UC_LOAD 14865 if (ELINK_USES_WARPCORE(chip_id)) { 14866 rc |= elink_warpcore_common_init(cb, shmem_base_path, 14867 shmem2_base_path, phy_index, 14868 chip_id, one_port_enabled); 14869 } 14870 #endif 14871 /* Read the ext_phy_type for arbitrary port(0) */ 14872 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14873 phy_index++) { 14874 ext_phy_config = elink_get_ext_phy_config(cb, 14875 shmem_base_path[0], 14876 phy_index, 0); 14877 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 14878 rc |= elink_ext_phy_common_init(cb, shmem_base_path, 14879 shmem2_base_path, 14880 phy_index, ext_phy_type, 14881 chip_id); 14882 } 14883 #endif /* ELINK_EMUL_ONLY */ 14884 return rc; 14885 } 14886 #endif // #ifndef EXCLUDE_COMMON_INIT 14887 14888 #ifndef EXCLUDE_NON_COMMON_INIT 14889 #ifndef EXCLUDE_WARPCORE 14890 static void elink_check_over_curr(struct elink_params *params, 14891 struct elink_vars *vars) 14892 { 14893 struct elink_dev *cb = params->cb; 14894 u32 cfg_pin; 14895 u8 port = params->port; 14896 u32 pin_val; 14897 14898 cfg_pin = (REG_RD(cb, params->shmem_base + 14899 OFFSETOF(struct shmem_region, 14900 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 14901 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 14902 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 14903 14904 /* Ignore check if no external input PIN available */ 14905 if (elink_get_cfg_pin(cb, cfg_pin, &pin_val) != ELINK_STATUS_OK) 14906 return; 14907 14908 if (!pin_val) { 14909 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 14910 #ifndef ELINK_AUX_POWER 14911 elink_cb_event_log(cb, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" 14912 // " been detected and the power to " 14913 // "that SFP+ module has been removed" 14914 // " to prevent failure of the card." 14915 // " Please remove the SFP+ module and" 14916 // " restart the system to clear this" 14917 // " error.\n", 14918 #endif /* ELINK_AUX_POWER */ 14919 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 14920 elink_warpcore_power_module(params, 0); 14921 } 14922 } else 14923 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 14924 } 14925 #endif // EXCLUDE_WARPCORE 14926 14927 /* Returns 0 if no change occured since last check; 1 otherwise. */ 14928 static u8 elink_analyze_link_error(struct elink_params *params, 14929 struct elink_vars *vars, u32 status, 14930 u32 phy_flag, u32 link_flag, u8 notify) 14931 { 14932 struct elink_dev *cb = params->cb; 14933 /* Compare new value with previous value */ 14934 u8 led_mode; 14935 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 14936 14937 if ((status ^ old_status) == 0) 14938 return 0; 14939 14940 /* If values differ */ 14941 switch (phy_flag) { 14942 case PHY_HALF_OPEN_CONN_FLAG: 14943 ELINK_DEBUG_P0(cb, "Analyze Remote Fault\n"); 14944 break; 14945 case PHY_SFP_TX_FAULT_FLAG: 14946 ELINK_DEBUG_P0(cb, "Analyze TX Fault\n"); 14947 break; 14948 default: 14949 ELINK_DEBUG_P0(cb, "Analyze UNKNOWN\n"); 14950 } 14951 ELINK_DEBUG_P3(cb, "Link changed:[%x %x]->%x\n", vars->link_up, 14952 old_status, status); 14953 14954 /* Do not touch the link in case physical link down */ 14955 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) 14956 return 1; 14957 14958 /* a. Update shmem->link_status accordingly 14959 * b. Update elink_vars->link_up 14960 */ 14961 if (status) { 14962 vars->link_status &= ~LINK_STATUS_LINK_UP; 14963 vars->link_status |= link_flag; 14964 vars->link_up = 0; 14965 vars->phy_flags |= phy_flag; 14966 14967 /* activate nig drain */ 14968 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14969 /* Set LED mode to off since the PHY doesn't know about these 14970 * errors 14971 */ 14972 led_mode = ELINK_LED_MODE_OFF; 14973 } else { 14974 vars->link_status |= LINK_STATUS_LINK_UP; 14975 vars->link_status &= ~link_flag; 14976 vars->link_up = 1; 14977 vars->phy_flags &= ~phy_flag; 14978 led_mode = ELINK_LED_MODE_OPER; 14979 14980 /* Clear nig drain */ 14981 REG_WR(cb, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14982 } 14983 #ifndef ELINK_AUX_POWER 14984 #ifdef ELINK_57711E_SUPPORT 14985 elink_sync_link(params, vars); 14986 #endif // ELINK_57711E_SUPPORT 14987 #endif // ELINK_AUX_POWER 14988 /* Update the LED according to the link state */ 14989 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); 14990 14991 /* Update link status in the shared memory */ 14992 elink_update_mng(params, vars->link_status); 14993 14994 /* C. Trigger General Attention */ 14995 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; 14996 #ifndef EDEBUG 14997 if (notify) 14998 elink_cb_notify_link_changed(cb); 14999 #endif // EDEBUG 15000 15001 return 1; 15002 } 15003 15004 /****************************************************************************** 15005 * Description: 15006 * This function checks for half opened connection change indication. 15007 * When such change occurs, it calls the elink_analyze_link_error 15008 * to check if Remote Fault is set or cleared. Reception of remote fault 15009 * status message in the MAC indicates that the peer's MAC has detected 15010 * a fault, for example, due to break in the TX side of fiber. 15011 * 15012 ******************************************************************************/ 15013 #ifdef BNX2X_ADD /* BNX2X_ADD */ 15014 static 15015 #endif 15016 elink_status_t elink_check_half_open_conn(struct elink_params *params, 15017 struct elink_vars *vars, 15018 u8 notify) 15019 { 15020 struct elink_dev *cb = params->cb; 15021 u32 lss_status = 0; 15022 u32 mac_base; 15023 /* In case link status is physically up @ 10G do */ 15024 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 15025 (REG_RD(cb, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 15026 return ELINK_STATUS_OK; 15027 15028 if (CHIP_IS_E3(params->chip_id) && 15029 (REG_RD(cb, MISC_REG_RESET_REG_2) & 15030 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 15031 /* Check E3 XMAC */ 15032 /* Note that link speed cannot be queried here, since it may be 15033 * zero while link is down. In case UMAC is active, LSS will 15034 * simply not be set 15035 */ 15036 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15037 15038 /* Clear stick bits (Requires rising edge) */ 15039 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 15040 REG_WR(cb, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 15041 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 15042 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 15043 if (REG_RD(cb, mac_base + XMAC_REG_RX_LSS_STATUS)) 15044 lss_status = 1; 15045 15046 elink_analyze_link_error(params, vars, lss_status, 15047 PHY_HALF_OPEN_CONN_FLAG, 15048 LINK_STATUS_NONE, notify); 15049 } else if (REG_RD(cb, MISC_REG_RESET_REG_2) & 15050 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 15051 /* Check E1X / E2 BMAC */ 15052 u32 lss_status_reg; 15053 u32 wb_data[2]; 15054 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 15055 NIG_REG_INGRESS_BMAC0_MEM; 15056 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 15057 if (CHIP_IS_E2(params->chip_id)) 15058 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 15059 else 15060 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 15061 15062 REG_RD_DMAE(cb, mac_base + lss_status_reg, wb_data, 2); 15063 lss_status = (wb_data[0] > 0); 15064 15065 elink_analyze_link_error(params, vars, lss_status, 15066 PHY_HALF_OPEN_CONN_FLAG, 15067 LINK_STATUS_NONE, notify); 15068 } 15069 return ELINK_STATUS_OK; 15070 } 15071 #ifdef ELINK_ENHANCEMENTS 15072 static void elink_sfp_tx_fault_detection(struct elink_phy *phy, 15073 struct elink_params *params, 15074 struct elink_vars *vars) 15075 { 15076 struct elink_dev *cb = params->cb; 15077 u32 cfg_pin, value = 0; 15078 u8 led_change, port = params->port; 15079 15080 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 15081 cfg_pin = (REG_RD(cb, params->shmem_base + OFFSETOF(struct shmem_region, 15082 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 15083 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 15084 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 15085 15086 if (elink_get_cfg_pin(cb, cfg_pin, &value)) { 15087 ELINK_DEBUG_P1(cb, "Failed to read pin 0x%02x\n", cfg_pin); 15088 return; 15089 } 15090 15091 led_change = elink_analyze_link_error(params, vars, value, 15092 PHY_SFP_TX_FAULT_FLAG, 15093 LINK_STATUS_SFP_TX_FAULT, 1); 15094 15095 if (led_change) { 15096 /* Change TX_Fault led, set link status for further syncs */ 15097 u8 led_mode; 15098 15099 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 15100 led_mode = MISC_REGISTERS_GPIO_HIGH; 15101 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 15102 } else { 15103 led_mode = MISC_REGISTERS_GPIO_LOW; 15104 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15105 } 15106 15107 /* If module is unapproved, led should be on regardless */ 15108 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 15109 ELINK_DEBUG_P1(cb, "Change TX_Fault LED: ->%x\n", 15110 led_mode); 15111 elink_set_e3_module_fault_led(params, led_mode); 15112 } 15113 } 15114 } 15115 #endif 15116 #ifndef EXCLUDE_WARPCORE 15117 static void elink_kr2_recovery(struct elink_params *params, 15118 struct elink_vars *vars, 15119 struct elink_phy *phy) 15120 { 15121 #ifdef ELINK_DEBUG 15122 struct elink_dev *cb = params->cb; 15123 ELINK_DEBUG_P0(cb, "KR2 recovery\n"); 15124 #endif // ELINK_DEBUG 15125 elink_warpcore_enable_AN_KR2(phy, params, vars); 15126 elink_warpcore_restart_AN_KR(phy, params); 15127 } 15128 15129 static void elink_check_kr2_wa(struct elink_params *params, 15130 struct elink_vars *vars, 15131 struct elink_phy *phy) 15132 { 15133 struct elink_dev *cb = params->cb; 15134 u16 base_page, next_page, not_kr2_device, lane; 15135 int sigdet; 15136 15137 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 15138 * Since some switches tend to reinit the AN process and clear the 15139 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 15140 * and recovered many times 15141 */ 15142 if (vars->check_kr2_recovery_cnt > 0) { 15143 vars->check_kr2_recovery_cnt--; 15144 return; 15145 } 15146 15147 sigdet = elink_warpcore_get_sigdet(phy, params); 15148 if (!sigdet) { 15149 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15150 elink_kr2_recovery(params, vars, phy); 15151 ELINK_DEBUG_P0(cb, "No sigdet\n"); 15152 } 15153 return; 15154 } 15155 15156 lane = elink_get_warpcore_lane(phy, params); 15157 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15158 MDIO_AER_BLOCK_AER_REG, lane); 15159 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15160 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 15161 elink_cl45_read(cb, phy, MDIO_AN_DEVAD, 15162 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 15163 elink_set_aer_mmd(params, phy); 15164 15165 /* CL73 has not begun yet */ 15166 if (base_page == 0) { 15167 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15168 elink_kr2_recovery(params, vars, phy); 15169 ELINK_DEBUG_P0(cb, "No BP\n"); 15170 } 15171 return; 15172 } 15173 15174 /* In case NP bit is not set in the BasePage, or it is set, 15175 * but only KX is advertised, declare this link partner as non-KR2 15176 * device. 15177 */ 15178 not_kr2_device = (((base_page & 0x8000) == 0) || 15179 (((base_page & 0x8000) && 15180 ((next_page & 0xe0) == 0x20)))); 15181 15182 /* In case KR2 is already disabled, check if we need to re-enable it */ 15183 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 15184 if (!not_kr2_device) { 15185 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, 15186 next_page); 15187 elink_kr2_recovery(params, vars, phy); 15188 } 15189 return; 15190 } 15191 /* KR2 is enabled, but not KR2 device */ 15192 if (not_kr2_device) { 15193 /* Disable KR2 on both lanes */ 15194 ELINK_DEBUG_P2(cb, "BP=0x%x, NP=0x%x\n", base_page, next_page); 15195 elink_disable_kr2(params, vars, phy); 15196 /* Restart AN on leading lane */ 15197 elink_warpcore_restart_AN_KR(phy, params); 15198 return; 15199 } 15200 } 15201 #endif 15202 15203 void elink_period_func(struct elink_params *params, struct elink_vars *vars) 15204 { 15205 u16 phy_idx; 15206 #if defined(ELINK_DEBUG) || defined(ELINK_ENHANCEMENTS) 15207 struct elink_dev *cb = params->cb; 15208 #endif 15209 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15210 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 15211 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); 15212 if (elink_check_half_open_conn(params, vars, 1) != 15213 ELINK_STATUS_OK) 15214 ELINK_DEBUG_P0(cb, "Fault detection failed\n"); 15215 break; 15216 } 15217 } 15218 15219 #ifndef EXCLUDE_WARPCORE 15220 if (CHIP_IS_E3(params->chip_id)) { 15221 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15222 elink_set_aer_mmd(params, phy); 15223 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && 15224 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 15225 elink_check_kr2_wa(params, vars, phy); 15226 #ifdef ELINK_AUX_POWER 15227 if ((phy->flags & ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC) == 0) { 15228 if (elink_is_sfp_module_plugged(phy, params)) { 15229 phy->flags |= 15230 ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15231 elink_sfp_module_detection(phy, params); 15232 } 15233 } else { 15234 if (!elink_is_sfp_module_plugged(phy, params)) { 15235 elink_sfp_set_transmitter(params, phy, 1); 15236 phy->flags &= 15237 ~ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC; 15238 } 15239 } 15240 #endif // ELINK_AUX_POWER 15241 elink_check_over_curr(params, vars); 15242 #ifdef ELINK_ENHANCEMENTS 15243 if (vars->rx_tx_asic_rst) 15244 elink_warpcore_config_runtime(phy, params, vars); 15245 15246 if ((REG_RD(cb, params->shmem_base + 15247 OFFSETOF(struct shmem_region, dev_info. 15248 port_hw_config[params->port].default_cfg)) 15249 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 15250 PORT_HW_CFG_NET_SERDES_IF_SFI) { 15251 if (elink_is_sfp_module_plugged(phy, params)) { 15252 elink_sfp_tx_fault_detection(phy, params, vars); 15253 } else if (vars->link_status & 15254 LINK_STATUS_SFP_TX_FAULT) { 15255 /* Clean trail, interrupt corrects the leds */ 15256 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 15257 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 15258 /* Update link status in the shared memory */ 15259 elink_update_mng(params, vars->link_status); 15260 } 15261 } 15262 #endif // ELINK_ENHANCEMENTS 15263 } 15264 #endif /* EXCLUDE_WARPCORE */ 15265 } 15266 15267 #ifdef ELINK_ENHANCEMENTS 15268 u8 elink_fan_failure_det_req(struct elink_dev *cb, 15269 u32 shmem_base, 15270 u32 shmem2_base, 15271 u8 port) 15272 { 15273 u8 phy_index, fan_failure_det_req = 0; 15274 struct elink_phy phy; 15275 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15276 phy_index++) { 15277 if (elink_populate_phy(cb, phy_index, shmem_base, shmem2_base, 15278 port, &phy) 15279 != ELINK_STATUS_OK) { 15280 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15281 return 0; 15282 } 15283 fan_failure_det_req |= (phy.flags & 15284 ELINK_FLAGS_FAN_FAILURE_DET_REQ); 15285 } 15286 return fan_failure_det_req; 15287 } 15288 #endif // ELINK_ENHANCEMENTS 15289 #ifdef ELINK_AUX_POWER 15290 void elink_enable_pmd_tx(struct elink_params *params) 15291 { 15292 u8 phy_index; 15293 elink_set_mdio_emac_per_phy(params->cb, params); 15294 15295 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15296 phy_index++) { 15297 switch (params->phy[phy_index].type) { 15298 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15299 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 15300 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 15301 elink_cl45_write(params->cb, ¶ms->phy[phy_index], 15302 MDIO_PMA_DEVAD, 15303 MDIO_PMA_REG_TX_DISABLE, 0); 15304 default: 15305 break; 15306 } 15307 } 15308 } 15309 #endif // ELINK_AUX_POWER 15310 15311 void elink_hw_reset_phy(struct elink_params *params) 15312 { 15313 u8 phy_index; 15314 struct elink_dev *cb = params->cb; 15315 elink_update_mng(params, 0); 15316 elink_bits_dis(cb, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 15317 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 15318 ELINK_NIG_MASK_XGXS0_LINK10G | 15319 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 15320 ELINK_NIG_MASK_MI_INT)); 15321 15322 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 15323 phy_index++) { 15324 if (params->phy[phy_index].hw_reset) { 15325 params->phy[phy_index].hw_reset( 15326 ¶ms->phy[phy_index], 15327 params); 15328 params->phy[phy_index] = phy_null; 15329 } 15330 } 15331 } 15332 15333 #ifdef ELINK_ENHANCEMENTS 15334 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars, 15335 u32 chip_id, u32 shmem_base, u32 shmem2_base, 15336 u8 port) 15337 { 15338 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; 15339 u32 val; 15340 u32 offset, aeu_mask, swap_val, swap_override, sync_offset; 15341 if (CHIP_IS_E3(chip_id)) { 15342 if (elink_get_mod_abs_int_cfg(cb, chip_id, 15343 shmem_base, 15344 port, 15345 &gpio_num, 15346 &gpio_port) != ELINK_STATUS_OK) 15347 return; 15348 } else { 15349 struct elink_phy phy; 15350 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 15351 phy_index++) { 15352 if (elink_populate_phy(cb, phy_index, shmem_base, 15353 shmem2_base, port, &phy) 15354 != ELINK_STATUS_OK) { 15355 ELINK_DEBUG_P0(cb, "populate phy failed\n"); 15356 return; 15357 } 15358 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 15359 gpio_num = MISC_REGISTERS_GPIO_3; 15360 gpio_port = port; 15361 break; 15362 } 15363 } 15364 } 15365 15366 if (gpio_num == 0xff) 15367 return; 15368 15369 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 15370 ELINK_SET_GPIO(cb, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 15371 15372 swap_val = REG_RD(cb, NIG_REG_PORT_SWAP); 15373 swap_override = REG_RD(cb, NIG_REG_STRAP_OVERRIDE); 15374 gpio_port ^= (swap_val && swap_override); 15375 15376 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 15377 (gpio_num + (gpio_port << 2)); 15378 15379 sync_offset = shmem_base + 15380 OFFSETOF(struct shmem_region, 15381 dev_info.port_hw_config[port].aeu_int_mask); 15382 REG_WR(cb, sync_offset, vars->aeu_int_mask); 15383 15384 ELINK_DEBUG_P3(cb, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 15385 gpio_num, gpio_port, vars->aeu_int_mask); 15386 15387 if (port == 0) 15388 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 15389 else 15390 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 15391 15392 /* Open appropriate AEU for interrupts */ 15393 aeu_mask = REG_RD(cb, offset); 15394 aeu_mask |= vars->aeu_int_mask; 15395 REG_WR(cb, offset, aeu_mask); 15396 15397 /* Enable the GPIO to trigger interrupt */ 15398 val = REG_RD(cb, MISC_REG_GPIO_EVENT_EN); 15399 val |= 1 << (gpio_num + (gpio_port << 2)); 15400 REG_WR(cb, MISC_REG_GPIO_EVENT_EN, val); 15401 } 15402 #endif // ELINK_ENHANCEMENTS 15403 #endif // EXCLUDE_NON_COMMON_INIT 15404 15405 #ifdef ELINK_AUX_POWER 15406 void elink_adjust_phy_func_ptr(struct elink_params *params) 15407 { 15408 u32 phy_idx; 15409 struct elink_phy phy, *cur_phy; 15410 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 15411 cur_phy = ¶ms->phy[phy_idx]; 15412 /* Select the phy type */ 15413 switch (cur_phy->type) { 15414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 15415 #ifndef EXCLUDE_WARPCORE 15416 phy = phy_warpcore; 15417 #else 15418 phy = phy_xgxs; 15419 #endif 15420 break; 15421 #ifndef EXCLUDE_BCM8727_BCM8073 15422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 15423 phy = phy_8073; 15424 break; 15425 #endif 15426 #ifndef EXCLUDE_BCM8705 15427 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 15428 phy = phy_8705; 15429 break; 15430 #endif 15431 #ifndef EXCLUDE_BCM87x6 15432 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 15433 phy = phy_8706; 15434 break; 15435 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 15436 phy = phy_8726; 15437 break; 15438 #endif /* EXCLUDE_BCM87x6 */ 15439 #ifndef EXCLUDE_BCM8727_BCM8073 15440 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 15441 phy = phy_8727; 15442 break; 15443 #endif 15444 #ifndef EXCLUDE_BCM8481 15445 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 15446 phy = phy_8481; 15447 break; 15448 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 15449 phy = phy_84823; 15450 break; 15451 #endif 15452 #ifndef EXCLUDE_BCM84833 15453 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 15454 phy = phy_84833; 15455 break; 15456 #endif 15457 #ifndef EXCLUDE_BCM54618SE 15458 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 15459 phy = phy_54618se; 15460 break; 15461 #endif 15462 #ifndef EXCLUDE_SFX7101 15463 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 15464 phy = phy_7101; 15465 break; 15466 #endif 15467 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 15468 phy = phy_null; 15469 return; 15470 default: 15471 phy = phy_null; 15472 continue; 15473 } 15474 cur_phy->config_init = phy.config_init; 15475 cur_phy->read_status = phy.read_status; 15476 cur_phy->link_reset = phy.link_reset; 15477 cur_phy->config_loopback = phy.config_loopback; 15478 cur_phy->format_fw_ver = phy.format_fw_ver; 15479 cur_phy->hw_reset = phy.hw_reset; 15480 cur_phy->set_link_led = phy.set_link_led; 15481 cur_phy->phy_specific_func = phy.phy_specific_func; 15482 } 15483 } 15484 15485 #ifndef EXCLUDE_COMMON_INIT 15486 elink_status_t elink_get_phy_temperature(struct elink_params *params, 15487 u32 *temp_reading, u8 path, u8 port) 15488 { 15489 /* The temperature returned from this function is expected 15490 * to be degree C. Any conversion from hardware value to 15491 * degree C will be performed here. 15492 */ 15493 15494 struct elink_phy *phy; 15495 u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 15496 elink_status_t rc; 15497 u8 idx; 15498 15499 for (idx = 0; idx < PHY84833_CMDHDLR_MAX_ARGS; idx++) 15500 cmd_args[idx] = 0; 15501 for (idx = 0; idx < params->num_phys; idx++) { 15502 phy = ¶ms->phy[idx]; 15503 if (phy->flags & ELINK_FLAGS_TEMPERATURE) { 15504 rc = elink_84833_cmd_hdlr(phy, params, 15505 PHY84833_CMD_GET_CURRENT_TEMP, 15506 cmd_args, 15507 PHY84833_CMDHDLR_MAX_ARGS); 15508 if ((path == 0) && (cmd_args[1] == 0)) 15509 cmd_args[1] = cmd_args[0] + 5; 15510 if (cmd_args[0] > cmd_args[1]) 15511 *temp_reading = (u32)cmd_args[0]; 15512 else 15513 *temp_reading = (u32)cmd_args[1]; 15514 15515 return rc; 15516 } 15517 } 15518 15519 return ELINK_STATUS_ERROR; 15520 } 15521 #ifndef EXCLUDE_WARPCORE 15522 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val) 15523 { 15524 elink_set_cfg_pin(cb, pin_cfg, val); 15525 } 15526 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val) 15527 { 15528 return elink_get_cfg_pin(cb, pin_cfg, val); 15529 } 15530 15531 void elink_force_link(struct elink_params *params, int enable) { 15532 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 15533 struct elink_dev *cb = params->cb; 15534 u8 lane = elink_get_warpcore_lane(phy, params); 15535 u16 val; 15536 15537 /* Global register - operate on lane 0 */ 15538 CL22_WR_OVER_CL45(cb, phy, MDIO_REG_BANK_AER_BLOCK, 15539 MDIO_AER_BLOCK_AER_REG, 0); 15540 15541 elink_cl45_read(cb, phy, MDIO_PMA_DEVAD, 15542 MDIO_WC_REG_XGXSBLK2_LANE_RESET, &val); 15543 if (enable) 15544 val &= ~(0x11 << lane); 15545 else 15546 val |= (0x11 << lane); 15547 elink_cl45_write(cb, phy, MDIO_PMA_DEVAD, 15548 MDIO_WC_REG_XGXSBLK2_LANE_RESET, 15549 val); 15550 15551 /* Restore AER */ 15552 elink_set_aer_mmd(params, phy); 15553 } 15554 15555 #endif /* EXCLUDE_WARPCORE */ 15556 #endif /* #ifndef EXCLUDE_COMMON_INIT */ 15557 #endif 15558