17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 567f02347Srandyf * Common Development and Distribution License (the "License"). 667f02347Srandyf * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 2167f02347Srandyf 227c478bd9Sstevel@tonic-gate /* 23087a28d1SDavid Gwynne * Copyright (c) 2010-2013, by Broadcom, Inc. 24087a28d1SDavid Gwynne * All Rights Reserved. 25087a28d1SDavid Gwynne */ 26087a28d1SDavid Gwynne 27087a28d1SDavid Gwynne /* 28087a28d1SDavid Gwynne * Copyright (c) 2002, 2010, Oracle and/or its affiliates. 29087a28d1SDavid Gwynne * All rights reserved. 307c478bd9Sstevel@tonic-gate */ 317c478bd9Sstevel@tonic-gate 32542d98abSzh #ifndef _BGE_HW_H 33542d98abSzh #define _BGE_HW_H 347c478bd9Sstevel@tonic-gate 357c478bd9Sstevel@tonic-gate #ifdef __cplusplus 367c478bd9Sstevel@tonic-gate extern "C" { 377c478bd9Sstevel@tonic-gate #endif 387c478bd9Sstevel@tonic-gate 397c478bd9Sstevel@tonic-gate #include <sys/types.h> 407c478bd9Sstevel@tonic-gate 417c478bd9Sstevel@tonic-gate 427c478bd9Sstevel@tonic-gate /* 437c478bd9Sstevel@tonic-gate * First section: 447c478bd9Sstevel@tonic-gate * Identification of the various Broadcom chips 457c478bd9Sstevel@tonic-gate * 467c478bd9Sstevel@tonic-gate * Note: the various ID values are *not* all unique ;-( 477c478bd9Sstevel@tonic-gate * 487c478bd9Sstevel@tonic-gate * Note: the presence of an ID here does *not* imply that the chip is 497c478bd9Sstevel@tonic-gate * supported. At this time, only the 5703C, 5704C, and 5704S devices 507c478bd9Sstevel@tonic-gate * used on the motherboards of certain Sun products are supported. 517c478bd9Sstevel@tonic-gate * 527c478bd9Sstevel@tonic-gate * Note: the revision-id values in the PCI revision ID register are 537c478bd9Sstevel@tonic-gate * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 547c478bd9Sstevel@tonic-gate */ 557c478bd9Sstevel@tonic-gate 567c478bd9Sstevel@tonic-gate #define VENDOR_ID_BROADCOM 0x14e4 577c478bd9Sstevel@tonic-gate #define VENDOR_ID_SUN 0x108e 587c478bd9Sstevel@tonic-gate 597c478bd9Sstevel@tonic-gate #define DEVICE_ID_5700 0x1644 607c478bd9Sstevel@tonic-gate #define DEVICE_ID_5700x 0x0003 617c478bd9Sstevel@tonic-gate #define DEVICE_ID_5701 0x1645 627c478bd9Sstevel@tonic-gate #define DEVICE_ID_5702 0x16a6 637c478bd9Sstevel@tonic-gate #define DEVICE_ID_5702fe 0x164d 644d6eaea5Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5703C 0x16a7 654d6eaea5Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5703S 0x1647 667c478bd9Sstevel@tonic-gate #define DEVICE_ID_5703 0x16c7 677c478bd9Sstevel@tonic-gate #define DEVICE_ID_5704C 0x1648 687c478bd9Sstevel@tonic-gate #define DEVICE_ID_5704S 0x16a8 691de7668bSly #define DEVICE_ID_5704 0x1649 707c478bd9Sstevel@tonic-gate #define DEVICE_ID_5705C 0x1653 717c966ec8Sml #define DEVICE_ID_5705_2 0x1654 72224ef589Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5717 0x1655 73087a28d1SDavid Gwynne #define DEVICE_ID_5717_C0 0x1665 74dc3f9a75Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5718 0x1656 75087a28d1SDavid Gwynne #define DEVICE_ID_5719 0x1657 76087a28d1SDavid Gwynne #define DEVICE_ID_5720 0x165f 77224ef589Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5724 0x165c 78087a28d1SDavid Gwynne #define DEVICE_ID_5725 0x1643 79087a28d1SDavid Gwynne #define DEVICE_ID_5727 0x16f3 807c478bd9Sstevel@tonic-gate #define DEVICE_ID_5705M 0x165d 817c478bd9Sstevel@tonic-gate #define DEVICE_ID_5705MA3 0x165e 82fbdb9ef6Sly #define DEVICE_ID_5705F 0x166e 83feb48d62SGarrett D'Amore #define DEVICE_ID_5780 0x166a 847c478bd9Sstevel@tonic-gate #define DEVICE_ID_5782 0x1696 85652b4801Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5785 0x1699 867f7c96a6Sml #define DEVICE_ID_5787 0x169b 877f7c96a6Sml #define DEVICE_ID_5787M 0x1693 887c478bd9Sstevel@tonic-gate #define DEVICE_ID_5788 0x169c 89256e438eSzh #define DEVICE_ID_5789 0x169d 907c478bd9Sstevel@tonic-gate #define DEVICE_ID_5751 0x1677 917c478bd9Sstevel@tonic-gate #define DEVICE_ID_5751M 0x167d 92f724721bSzh #define DEVICE_ID_5752 0x1600 93f724721bSzh #define DEVICE_ID_5752M 0x1601 94a0a6bf1cSml #define DEVICE_ID_5753 0x16fd 95ebd66af9Sml #define DEVICE_ID_5754 0x167a 9603a69b52Sml #define DEVICE_ID_5755 0x167b 97dca582a1Sgh #define DEVICE_ID_5755M 0x1673 9867f41d5aSGordon Ross #define DEVICE_ID_5756M 0x1674 997c478bd9Sstevel@tonic-gate #define DEVICE_ID_5721 0x1659 100f0a5c2e3SCrisson Guanghao Hu #define DEVICE_ID_5722 0x165a 10100d84294Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5723 0x165b 1027c478bd9Sstevel@tonic-gate #define DEVICE_ID_5714C 0x1668 1037c478bd9Sstevel@tonic-gate #define DEVICE_ID_5714S 0x1669 10410843bc4Sly #define DEVICE_ID_5715C 0x1678 1057c966ec8Sml #define DEVICE_ID_5715S 0x1679 1067e420006Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5761E 0x1680 1077e420006Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5761 0x1681 108d7441963Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5764 0x1684 1095a506a18Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5906 0x1712 1105a506a18Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_5906M 0x1713 111224ef589Syong tan - Sun Microsystems - Beijing China #define DEVICE_ID_57780 0x1692 112*a2876d03SRobert Mustacchi #define DEVICE_ID_57761 0x16b0 113*a2876d03SRobert Mustacchi #define DEVICE_ID_57762 0x1682 114*a2876d03SRobert Mustacchi #define DEVICE_ID_57765 0x16b4 115*a2876d03SRobert Mustacchi #define DEVICE_ID_57766 0x1686 116*a2876d03SRobert Mustacchi #define DEVICE_ID_57781 0x16b1 117*a2876d03SRobert Mustacchi #define DEVICE_ID_57782 0x16b7 118*a2876d03SRobert Mustacchi #define DEVICE_ID_57785 0x16b5 119*a2876d03SRobert Mustacchi #define DEVICE_ID_57786 0x16b3 120*a2876d03SRobert Mustacchi #define DEVICE_ID_57791 0x16b2 121*a2876d03SRobert Mustacchi #define DEVICE_ID_57795 0x16b6 1227c478bd9Sstevel@tonic-gate 1237c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_B0 0x10 1247c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_B2 0x12 1257c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_B3 0x13 1267c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_C0 0x20 1277c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_C1 0x21 1287c478bd9Sstevel@tonic-gate #define REVISION_ID_5700_C2 0x22 1297c478bd9Sstevel@tonic-gate 1307c478bd9Sstevel@tonic-gate #define REVISION_ID_5701_A0 0x08 1317c478bd9Sstevel@tonic-gate #define REVISION_ID_5701_A2 0x12 1327c478bd9Sstevel@tonic-gate #define REVISION_ID_5701_A3 0x15 1337c478bd9Sstevel@tonic-gate 1347c478bd9Sstevel@tonic-gate #define REVISION_ID_5702_A0 0x00 1357c478bd9Sstevel@tonic-gate 1367c478bd9Sstevel@tonic-gate #define REVISION_ID_5703_A0 0x00 1377c478bd9Sstevel@tonic-gate #define REVISION_ID_5703_A1 0x01 1387c478bd9Sstevel@tonic-gate #define REVISION_ID_5703_A2 0x02 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate #define REVISION_ID_5704_A0 0x00 1417c478bd9Sstevel@tonic-gate #define REVISION_ID_5704_A1 0x01 1427c478bd9Sstevel@tonic-gate #define REVISION_ID_5704_A2 0x02 1437c478bd9Sstevel@tonic-gate #define REVISION_ID_5704_A3 0x03 1447c478bd9Sstevel@tonic-gate #define REVISION_ID_5704_B0 0x10 1457c478bd9Sstevel@tonic-gate 1467c478bd9Sstevel@tonic-gate #define REVISION_ID_5705_A0 0x00 1477c478bd9Sstevel@tonic-gate #define REVISION_ID_5705_A1 0x01 1487c478bd9Sstevel@tonic-gate #define REVISION_ID_5705_A2 0x02 1497c478bd9Sstevel@tonic-gate #define REVISION_ID_5705_A3 0x03 1507c478bd9Sstevel@tonic-gate 1517c478bd9Sstevel@tonic-gate #define REVISION_ID_5721_A0 0x00 1527c478bd9Sstevel@tonic-gate #define REVISION_ID_5721_A1 0x01 1537c478bd9Sstevel@tonic-gate 1547c478bd9Sstevel@tonic-gate #define REVISION_ID_5751_A0 0x00 1557c478bd9Sstevel@tonic-gate #define REVISION_ID_5751_A1 0x01 1567c478bd9Sstevel@tonic-gate 1577c478bd9Sstevel@tonic-gate #define REVISION_ID_5714_A0 0x00 1588eb6c4f9Sly #define REVISION_ID_5714_A1 0x01 1598eb6c4f9Sly #define REVISION_ID_5714_A2 0xA2 1603c46fd93Szh #define REVISION_ID_5714_A3 0xA3 1618eb6c4f9Sly 1628eb6c4f9Sly #define REVISION_ID_5715_A0 0x00 1638eb6c4f9Sly #define REVISION_ID_5715_A1 0x01 1648eb6c4f9Sly #define REVISION_ID_5715_A2 0xA2 1658eb6c4f9Sly 1667c966ec8Sml #define REVISION_ID_5715S_A0 0x00 1677c966ec8Sml #define REVISION_ID_5715S_A1 0x01 1687c966ec8Sml 169ebd66af9Sml #define REVISION_ID_5754_A0 0x00 170ebd66af9Sml #define REVISION_ID_5754_A1 0x01 171ebd66af9Sml 1728eb6c4f9Sly #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 1738eb6c4f9Sly ((bgep->chipid.device == DEVICE_ID_5700) ||\ 1748eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5701) ||\ 1758eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5702) ||\ 1768eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5702fe)||\ 1778eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5703C) ||\ 1788eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5703S) ||\ 1798eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5703) ||\ 1808eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5704C) ||\ 1818eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5704S) ||\ 1828eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5704)) 1838eb6c4f9Sly 1848eb6c4f9Sly #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 1858eb6c4f9Sly ((bgep->chipid.device == DEVICE_ID_5702) ||\ 1868eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5702fe)) 1878eb6c4f9Sly 1888eb6c4f9Sly #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 1898eb6c4f9Sly ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 1908eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5705M) ||\ 1918eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 192fbdb9ef6Sly (bgep->chipid.device == DEVICE_ID_5705F) ||\ 193feb48d62SGarrett D'Amore (bgep->chipid.device == DEVICE_ID_5780) ||\ 1948eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5782) ||\ 1957c966ec8Sml (bgep->chipid.device == DEVICE_ID_5788) ||\ 196ebd66af9Sml (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 19703a69b52Sml (bgep->chipid.device == DEVICE_ID_5754) ||\ 198a0a6bf1cSml (bgep->chipid.device == DEVICE_ID_5755) ||\ 19967f41d5aSGordon Ross (bgep->chipid.device == DEVICE_ID_5756M) ||\ 200a0a6bf1cSml (bgep->chipid.device == DEVICE_ID_5753)) 2018eb6c4f9Sly 2028eb6c4f9Sly #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 2038eb6c4f9Sly ((bgep->chipid.device == DEVICE_ID_5721) ||\ 2048eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5751) ||\ 205256e438eSzh (bgep->chipid.device == DEVICE_ID_5751M) ||\ 206f724721bSzh (bgep->chipid.device == DEVICE_ID_5752) ||\ 207f724721bSzh (bgep->chipid.device == DEVICE_ID_5752M) ||\ 208256e438eSzh (bgep->chipid.device == DEVICE_ID_5789)) 2098eb6c4f9Sly 210dc3f9a75Syong tan - Sun Microsystems - Beijing China #define DEVICE_5717_SERIES_CHIPSETS(bgep) \ 211087a28d1SDavid Gwynne ((bgep->chipid.device == DEVICE_ID_5717) ||\ 212224ef589Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5718) ||\ 213087a28d1SDavid Gwynne (bgep->chipid.device == DEVICE_ID_5719) ||\ 214087a28d1SDavid Gwynne (bgep->chipid.device == DEVICE_ID_5720) ||\ 215087a28d1SDavid Gwynne (bgep->chipid.device == DEVICE_ID_5724)) 216087a28d1SDavid Gwynne 217087a28d1SDavid Gwynne #define DEVICE_5725_SERIES_CHIPSETS(bgep) \ 218087a28d1SDavid Gwynne ((bgep->chipid.device == DEVICE_ID_5725) ||\ 219087a28d1SDavid Gwynne (bgep->chipid.device == DEVICE_ID_5727)) 220dc3f9a75Syong tan - Sun Microsystems - Beijing China 22100d84294Syong tan - Sun Microsystems - Beijing China #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 2227e420006Syong tan - Sun Microsystems - Beijing China ((bgep->chipid.device == DEVICE_ID_5723) ||\ 2237e420006Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5761) ||\ 224d7441963Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5761E) ||\ 225652b4801Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5764) ||\ 226224ef589Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5785) ||\ 227224ef589Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_57780)) 22800d84294Syong tan - Sun Microsystems - Beijing China 2298eb6c4f9Sly #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 2308eb6c4f9Sly ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 2318eb6c4f9Sly (bgep->chipid.device == DEVICE_ID_5714S) ||\ 2327c966ec8Sml (bgep->chipid.device == DEVICE_ID_5715C) ||\ 2337c966ec8Sml (bgep->chipid.device == DEVICE_ID_5715S)) 2347c478bd9Sstevel@tonic-gate 2355a506a18Syong tan - Sun Microsystems - Beijing China #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 2365a506a18Syong tan - Sun Microsystems - Beijing China ((bgep->chipid.device == DEVICE_ID_5906) ||\ 2375a506a18Syong tan - Sun Microsystems - Beijing China (bgep->chipid.device == DEVICE_ID_5906M)) 2385a506a18Syong tan - Sun Microsystems - Beijing China 239*a2876d03SRobert Mustacchi /* 240*a2876d03SRobert Mustacchi * Even though the hardware register calls this the 57785 family, all of the 241*a2876d03SRobert Mustacchi * BSDs call this the 57765 series, so we call it that way to make it more 242*a2876d03SRobert Mustacchi * similar. 243*a2876d03SRobert Mustacchi */ 244*a2876d03SRobert Mustacchi #define DEVICE_57765_SERIES_CHIPSETS(bgep) \ 245*a2876d03SRobert Mustacchi ((bgep->chipid.device == DEVICE_ID_57761) || \ 246*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57762) || \ 247*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57765) || \ 248*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57766) || \ 249*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57781) || \ 250*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57782) || \ 251*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57785) || \ 252*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57786) || \ 253*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57791) || \ 254*a2876d03SRobert Mustacchi (bgep->chipid.device == DEVICE_ID_57795)) 255*a2876d03SRobert Mustacchi 2567c478bd9Sstevel@tonic-gate /* 2577c478bd9Sstevel@tonic-gate * Second section: 2587c478bd9Sstevel@tonic-gate * Offsets of important registers & definitions for bits therein 2597c478bd9Sstevel@tonic-gate */ 2607c478bd9Sstevel@tonic-gate 2617c478bd9Sstevel@tonic-gate /* 2627c478bd9Sstevel@tonic-gate * PCI-X registers & bits 2637c478bd9Sstevel@tonic-gate */ 2647c478bd9Sstevel@tonic-gate #define PCIX_CONF_COMM 0x42 2657c478bd9Sstevel@tonic-gate #define PCIX_COMM_RELAXED 0x0002 2667c478bd9Sstevel@tonic-gate 2677c478bd9Sstevel@tonic-gate /* 2687c478bd9Sstevel@tonic-gate * Miscellaneous Host Control Register, in PCI config space 2697c478bd9Sstevel@tonic-gate */ 2707c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_MHCR 0x68 2717c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_MASK 0xffff0000 2727c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 2737c478bd9Sstevel@tonic-gate #define MHCR_MASK_INTERRUPT_MODE 0x00000100 2747c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 2757c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 2767c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 277087a28d1SDavid Gwynne #define MHCR_ENABLE_PCI_STATE_RW 0x00000010 2787c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 2797c478bd9Sstevel@tonic-gate #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 2807c478bd9Sstevel@tonic-gate #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 2817c478bd9Sstevel@tonic-gate #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 282087a28d1SDavid Gwynne #define MHCR_BOUNDARY_CHECK 0x00002000 283087a28d1SDavid Gwynne #define MHCR_TLP_MINOR_ERR_TOLERANCE 0x00008000 2847c478bd9Sstevel@tonic-gate 2857c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_B0 0x71000000 2867c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_B2 0x71020000 2877c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_B3 0x71030000 2887c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_C0 0x72000000 2897c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_C1 0x72010000 2907c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5700_C2 0x72020000 2917c478bd9Sstevel@tonic-gate 2927c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5701_A0 0x00000000 2938eb6c4f9Sly #define MHCR_CHIP_REV_5701_A2 0x00020000 2948eb6c4f9Sly #define MHCR_CHIP_REV_5701_A3 0x00030000 2958eb6c4f9Sly #define MHCR_CHIP_REV_5701_A5 0x01050000 2967c478bd9Sstevel@tonic-gate 2978eb6c4f9Sly #define MHCR_CHIP_REV_5702_A0 0x10000000 2988eb6c4f9Sly #define MHCR_CHIP_REV_5702_A1 0x10010000 2998eb6c4f9Sly #define MHCR_CHIP_REV_5702_A2 0x10020000 3007c478bd9Sstevel@tonic-gate 3017c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5703_A0 0x10000000 3027c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5703_A1 0x10010000 3037c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5703_A2 0x10020000 3048eb6c4f9Sly #define MHCR_CHIP_REV_5703_B0 0x11000000 3058eb6c4f9Sly #define MHCR_CHIP_REV_5703_B1 0x11010000 3067c478bd9Sstevel@tonic-gate 3077c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5704_A0 0x20000000 3087c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5704_A1 0x20010000 3097c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5704_A2 0x20020000 3107c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5704_A3 0x20030000 3117c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5704_B0 0x21000000 3127c478bd9Sstevel@tonic-gate 3137c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5705_A0 0x30000000 3147c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5705_A1 0x30010000 3158eb6c4f9Sly #define MHCR_CHIP_REV_5705_A2 0x30020000 3168eb6c4f9Sly #define MHCR_CHIP_REV_5705_A3 0x30030000 3178eb6c4f9Sly #define MHCR_CHIP_REV_5705_A5 0x30050000 3187c478bd9Sstevel@tonic-gate 3197c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5782_A0 0x30030000 3207c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5782_A1 0x30030088 3217c478bd9Sstevel@tonic-gate 3228eb6c4f9Sly #define MHCR_CHIP_REV_5788_A1 0x30050000 3238eb6c4f9Sly 3247c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5751_A0 0x40000000 3257c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5751_A1 0x40010000 3267c478bd9Sstevel@tonic-gate 3277c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5721_A0 0x41000000 3287c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5721_A1 0x41010000 3297c478bd9Sstevel@tonic-gate 3307c478bd9Sstevel@tonic-gate #define MHCR_CHIP_REV_5714_A0 0x50000000 3318eb6c4f9Sly #define MHCR_CHIP_REV_5714_A1 0x90010000 3328eb6c4f9Sly 3338eb6c4f9Sly #define MHCR_CHIP_REV_5715_A0 0x50000000 3348eb6c4f9Sly #define MHCR_CHIP_REV_5715_A1 0x90010000 3357c478bd9Sstevel@tonic-gate 3367c966ec8Sml #define MHCR_CHIP_REV_5715S_A0 0x50000000 3377c966ec8Sml #define MHCR_CHIP_REV_5715S_A1 0x90010000 3387c966ec8Sml 339ebd66af9Sml #define MHCR_CHIP_REV_5754_A0 0xb0000000 340ebd66af9Sml #define MHCR_CHIP_REV_5754_A1 0xb0010000 341ebd66af9Sml 3427f7c96a6Sml #define MHCR_CHIP_REV_5787_A0 0xb0000000 3437f7c96a6Sml #define MHCR_CHIP_REV_5787_A1 0xb0010000 3447f7c96a6Sml #define MHCR_CHIP_REV_5787_A2 0xb0020000 3457f7c96a6Sml 34603a69b52Sml #define MHCR_CHIP_REV_5755_A0 0xa0000000 34703a69b52Sml #define MHCR_CHIP_REV_5755_A1 0xa0010000 34803a69b52Sml 3495a506a18Syong tan - Sun Microsystems - Beijing China #define MHCR_CHIP_REV_5906_A0 0xc0000000 3505a506a18Syong tan - Sun Microsystems - Beijing China #define MHCR_CHIP_REV_5906_A1 0xc0010000 3515a506a18Syong tan - Sun Microsystems - Beijing China #define MHCR_CHIP_REV_5906_A2 0xc0020000 3525a506a18Syong tan - Sun Microsystems - Beijing China 353087a28d1SDavid Gwynne #define CHIP_ASIC_REV_USE_PROD_ID_REG 0xf0000000 354087a28d1SDavid Gwynne #define MHCR_CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev & 0xf0000000) 355087a28d1SDavid Gwynne #define CHIP_ASIC_REV_PROD_ID(bgep) ((bgep)->chipid.asic_rev_prod_id) 356087a28d1SDavid Gwynne #define CHIP_ASIC_REV(bgep) ((bgep)->chipid.asic_rev_prod_id >> 12) 35700d84294Syong tan - Sun Microsystems - Beijing China 3587c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 3597c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 3607c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 3617c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 3627c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 3637c478bd9Sstevel@tonic-gate #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 364*a2876d03SRobert Mustacchi #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 365f724721bSzh #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 366ebd66af9Sml #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 3677f7c96a6Sml #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 36803a69b52Sml #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 369*a2876d03SRobert Mustacchi #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 3705a506a18Syong tan - Sun Microsystems - Beijing China #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 371087a28d1SDavid Gwynne /* (0xf << 28) touches all 5717 and 5725 series as well (OK) */ 37200d84294Syong tan - Sun Microsystems - Beijing China #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 3737c478bd9Sstevel@tonic-gate 374087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5723 0x5784 375087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5761 0x5761 376087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5785 0x5785 377087a28d1SDavid Gwynne #define CHIP_ASIC_REV_57780 0x57780 378*a2876d03SRobert Mustacchi #define CHIP_ASIC_REV_57785 0x57785 379087a28d1SDavid Gwynne 380087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5717 0x5717 381087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5719 0x5719 382087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5720 0x5720 383087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5762 0x5762 /* 5725/5727 */ 384087a28d1SDavid Gwynne 385087a28d1SDavid Gwynne #define CHIP_ASIC_REV_PROD_ID_REG 0x000000bc 386087a28d1SDavid Gwynne #define CHIP_ASIC_REV_PROD_ID_GEN2_REG 0x000000f4 387*a2876d03SRobert Mustacchi #define CHIP_ASIC_REV_PROD_ID_GEN15_REG 0x000000fc 388087a28d1SDavid Gwynne 389087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5717_B0 0x05717100 390087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5717_C0 0x05717200 391087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5718_B0 0x05717100 392087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5719_A0 0x05719000 393087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5719_A1 0x05719001 394087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5720_A0 0x05720000 395087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5725_A0 0x05762000 396087a28d1SDavid Gwynne #define CHIP_ASIC_REV_5727_B0 0x05762100 3977c478bd9Sstevel@tonic-gate 398*a2876d03SRobert Mustacchi /* 399*a2876d03SRobert Mustacchi * Match any Metal Layer Revision. 400*a2876d03SRobert Mustacchi */ 401*a2876d03SRobert Mustacchi #define CHIP_ASIC_REV_57765_AX 0x577850 402*a2876d03SRobert Mustacchi 4037c478bd9Sstevel@tonic-gate /* 4047c478bd9Sstevel@tonic-gate * PCI DMA read/write Control Register, in PCI config space 4057c478bd9Sstevel@tonic-gate * 4067c478bd9Sstevel@tonic-gate * Note that several fields previously defined here have been deleted 4077c478bd9Sstevel@tonic-gate * as they are not implemented in the 5703/4. 4087c478bd9Sstevel@tonic-gate * 4097c478bd9Sstevel@tonic-gate * Note: the value of this register is critical. It is possible to 4107c478bd9Sstevel@tonic-gate * cause various unpleasant effects (DTOs, transaction deadlock, etc) 4117c478bd9Sstevel@tonic-gate * by programming the wrong value. The value #defined below has been 4127c478bd9Sstevel@tonic-gate * tested and shown to avoid all known problems. If it is to be changed, 4137c478bd9Sstevel@tonic-gate * correct operation must be reverified on all supported platforms. 4147c478bd9Sstevel@tonic-gate * 4157c478bd9Sstevel@tonic-gate * In particular, we set both watermark fields to 2xCacheLineSize (128) 4167c478bd9Sstevel@tonic-gate * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 4177c478bd9Sstevel@tonic-gate * with Tomatillo's internal pipelines, that otherwise result in stalls, 4187c478bd9Sstevel@tonic-gate * repeated retries, and DTOs. 4197c478bd9Sstevel@tonic-gate */ 4207c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_PDRWCR 0x6c 4217c478bd9Sstevel@tonic-gate #define PDRWCR_RWCMD_MASK 0xFF000000 4227c478bd9Sstevel@tonic-gate #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 4237c478bd9Sstevel@tonic-gate #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 4247c478bd9Sstevel@tonic-gate #define PDRWCR_READ_WATERMARK_MASK 0x00070000 4257c478bd9Sstevel@tonic-gate #define PDRWCR_CONCURRENCY_MASK 0x0000c000 4267c478bd9Sstevel@tonic-gate #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 4277c478bd9Sstevel@tonic-gate #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 4287c478bd9Sstevel@tonic-gate #define PDRWCR_MIN_BEAT_MASK 0x000000ff 4297c478bd9Sstevel@tonic-gate 4307c478bd9Sstevel@tonic-gate /* 4317c478bd9Sstevel@tonic-gate * These are the actual values to be put into the fields shown above 4327c478bd9Sstevel@tonic-gate */ 4337c478bd9Sstevel@tonic-gate #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 4347c478bd9Sstevel@tonic-gate #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 4357c478bd9Sstevel@tonic-gate #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 4367c478bd9Sstevel@tonic-gate #define PDRWCR_MIN_BEATS 0x00000000 4377c478bd9Sstevel@tonic-gate 4387c478bd9Sstevel@tonic-gate #define PDRWCR_VAR_DEFAULT 0x761b0000 4397c478bd9Sstevel@tonic-gate #define PDRWCR_VAR_5721 0x76180000 4408eb6c4f9Sly #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 4418eb6c4f9Sly #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 442dc3f9a75Syong tan - Sun Microsystems - Beijing China #define PDRWCR_VAR_5717 0x00380000 4437c478bd9Sstevel@tonic-gate 4447c478bd9Sstevel@tonic-gate /* 4457c478bd9Sstevel@tonic-gate * PCI State Register, in PCI config space 4467c478bd9Sstevel@tonic-gate * 4477c478bd9Sstevel@tonic-gate * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 4487c478bd9Sstevel@tonic-gate * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 4497c478bd9Sstevel@tonic-gate */ 4507c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_PCISTATE 0x70 451087a28d1SDavid Gwynne #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 452087a28d1SDavid Gwynne #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 453087a28d1SDavid Gwynne #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 4547c478bd9Sstevel@tonic-gate #define PCISTATE_RETRY_SAME_DMA 0x00002000 4557c478bd9Sstevel@tonic-gate #define PCISTATE_FLAT_VIEW 0x00000100 4567c478bd9Sstevel@tonic-gate #define PCISTATE_EXT_ROM_RETRY 0x00000040 4577c478bd9Sstevel@tonic-gate #define PCISTATE_EXT_ROM_ENABLE 0x00000020 4587c478bd9Sstevel@tonic-gate #define PCISTATE_BUS_IS_32_BIT 0x00000010 4597c478bd9Sstevel@tonic-gate #define PCISTATE_BUS_IS_FAST 0x00000008 4607c478bd9Sstevel@tonic-gate #define PCISTATE_BUS_IS_PCI 0x00000004 4617c478bd9Sstevel@tonic-gate #define PCISTATE_INTA_STATE 0x00000002 4627c478bd9Sstevel@tonic-gate #define PCISTATE_FORCE_RESET 0x00000001 4637c478bd9Sstevel@tonic-gate 4647c478bd9Sstevel@tonic-gate /* 4657c478bd9Sstevel@tonic-gate * PCI Clock Control Register, in PCI config space 4667c478bd9Sstevel@tonic-gate */ 4677c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_CLKCTL 0x74 4687c478bd9Sstevel@tonic-gate #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 4697c478bd9Sstevel@tonic-gate #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 4707c478bd9Sstevel@tonic-gate #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 4717c478bd9Sstevel@tonic-gate #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 4727c478bd9Sstevel@tonic-gate #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 4737c478bd9Sstevel@tonic-gate #define CLKCTL_PCIE_A0_FIX 0x00101000 4747c478bd9Sstevel@tonic-gate 4757c478bd9Sstevel@tonic-gate /* 4767c478bd9Sstevel@tonic-gate * Dual MAC Control Register, in PCI config space 4777c478bd9Sstevel@tonic-gate */ 4787c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 4797c478bd9Sstevel@tonic-gate #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 4807c478bd9Sstevel@tonic-gate #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 4817c478bd9Sstevel@tonic-gate 4827c478bd9Sstevel@tonic-gate /* 4837c478bd9Sstevel@tonic-gate * Register Indirect Access Address Register, 0x78 in PCI config 4847c478bd9Sstevel@tonic-gate * space. Once this is set, accesses to the Register Indirect 4857c478bd9Sstevel@tonic-gate * Access Data Register (0x80) refer to the register whose address 4867c478bd9Sstevel@tonic-gate * is given by *this* register. This allows access to all the 4877c478bd9Sstevel@tonic-gate * operating registers, while using only config space accesses. 4887c478bd9Sstevel@tonic-gate * 4897c478bd9Sstevel@tonic-gate * Note that the address written to the RIIAR should lie in one 4907c478bd9Sstevel@tonic-gate * of the following ranges: 4917c478bd9Sstevel@tonic-gate * 0x00000000 <= address < 0x00008000 (regular registers) 4927c478bd9Sstevel@tonic-gate * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 4937c478bd9Sstevel@tonic-gate * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 4947c478bd9Sstevel@tonic-gate * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 4957c478bd9Sstevel@tonic-gate */ 4967c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_RIAAR 0x78 4977c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_RIADR 0x80 4987c478bd9Sstevel@tonic-gate 4997c478bd9Sstevel@tonic-gate #define RIAAR_REGISTER_MIN 0x00000000 5007c478bd9Sstevel@tonic-gate #define RIAAR_REGISTER_MAX 0x00008000 5017c478bd9Sstevel@tonic-gate #define RIAAR_RX_SCRATCH_MIN 0x00030000 5027c478bd9Sstevel@tonic-gate #define RIAAR_RX_SCRATCH_MAX 0x00034000 5037c478bd9Sstevel@tonic-gate #define RIAAR_TX_SCRATCH_MIN 0x00034000 5047c478bd9Sstevel@tonic-gate #define RIAAR_TX_SCRATCH_MAX 0x00038000 5057c478bd9Sstevel@tonic-gate #define RIAAR_RXROM_MIN 0x00038000 5067c478bd9Sstevel@tonic-gate #define RIAAR_RXROM_MAX 0x00038800 5077c478bd9Sstevel@tonic-gate 5087c478bd9Sstevel@tonic-gate /* 5097c478bd9Sstevel@tonic-gate * Memory Window Base Address Register, 0x7c in PCI config space 5107c478bd9Sstevel@tonic-gate * Once this is set, accesses to the Memory Window Data Access Register 5117c478bd9Sstevel@tonic-gate * (0x84) refer to the word of NIC-local memory whose address is given 5127c478bd9Sstevel@tonic-gate * by this register. When used in this way, the whole of the address 5137c478bd9Sstevel@tonic-gate * written to this register is significant. 5147c478bd9Sstevel@tonic-gate * 5157c478bd9Sstevel@tonic-gate * This register also provides the 32K-aligned base address for a 32K 5167c478bd9Sstevel@tonic-gate * region of NIC-local memory that the host can directly address in 5177c478bd9Sstevel@tonic-gate * the upper 32K of the 64K of PCI memory space allocated to the chip. 5187c478bd9Sstevel@tonic-gate * In this case, the bottom 15 bits of the register are ignored. 5197c478bd9Sstevel@tonic-gate * 5207c478bd9Sstevel@tonic-gate * Note that the address written to the MWBAR should lie in the range 5217c478bd9Sstevel@tonic-gate * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 5227c478bd9Sstevel@tonic-gate * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 5237c478bd9Sstevel@tonic-gate * memory were present, but it's only supported on the 5700, not the 5247c478bd9Sstevel@tonic-gate * 5701/5703/5704. 5257c478bd9Sstevel@tonic-gate */ 5267c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_MWBAR 0x7c 5277c478bd9Sstevel@tonic-gate #define PCI_CONF_BGE_MWDAR 0x84 5287c478bd9Sstevel@tonic-gate #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 5297c478bd9Sstevel@tonic-gate #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 5307c478bd9Sstevel@tonic-gate #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 5317c478bd9Sstevel@tonic-gate 5327c478bd9Sstevel@tonic-gate /* 5337c478bd9Sstevel@tonic-gate * The PCI express device control register and device status register 5347c478bd9Sstevel@tonic-gate * which are only applicable on BCM5751 and BCM5721. 5357c478bd9Sstevel@tonic-gate */ 5367c478bd9Sstevel@tonic-gate #define PCI_CONF_DEV_CTRL 0xd8 53700d84294Syong tan - Sun Microsystems - Beijing China #define PCI_CONF_DEV_CTRL_5723 0xd4 538087a28d1SDavid Gwynne #define PCI_CONF_DEV_CTRL_5717 0xb4 539087a28d1SDavid Gwynne #define READ_REQ_SIZE_MASK 0x7000 5407c478bd9Sstevel@tonic-gate #define READ_REQ_SIZE_MAX 0x5000 541*a2876d03SRobert Mustacchi #define READ_REQ_SIZE_2K 0x4000 542256e438eSzh #define DEV_CTRL_NO_SNOOP 0x0800 543256e438eSzh #define DEV_CTRL_RELAXED 0x0010 544256e438eSzh 545256e438eSzh #define PCI_CONF_DEV_STUS 0xda 54600d84294Syong tan - Sun Microsystems - Beijing China #define PCI_CONF_DEV_STUS_5723 0xd6 5477c478bd9Sstevel@tonic-gate #define DEVICE_ERROR_STUS 0xf 5487c478bd9Sstevel@tonic-gate 5497c478bd9Sstevel@tonic-gate #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 5507c478bd9Sstevel@tonic-gate 5517c478bd9Sstevel@tonic-gate /* 5527c478bd9Sstevel@tonic-gate * Where to find things in NIC-local (on-chip) memory 5537c478bd9Sstevel@tonic-gate */ 5547c478bd9Sstevel@tonic-gate #define NIC_MEM_SEND_RINGS 0x0100 5557c478bd9Sstevel@tonic-gate #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 5567c478bd9Sstevel@tonic-gate #define NIC_MEM_RECV_RINGS 0x0200 5577c478bd9Sstevel@tonic-gate #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 5587c478bd9Sstevel@tonic-gate #define NIC_MEM_STATISTICS 0x0300 5597c478bd9Sstevel@tonic-gate #define NIC_MEM_STATISTICS_SIZE 0x0800 5607c478bd9Sstevel@tonic-gate #define NIC_MEM_STATUS_BLOCK 0x0b00 5617c478bd9Sstevel@tonic-gate #define NIC_MEM_STATUS_SIZE 0x0050 5627c478bd9Sstevel@tonic-gate #define NIC_MEM_GENCOMM 0x0b50 5637c478bd9Sstevel@tonic-gate 5647c478bd9Sstevel@tonic-gate 5657c478bd9Sstevel@tonic-gate /* 5667c478bd9Sstevel@tonic-gate * Note: the (non-bogus) values below are appropriate for systems 5677c478bd9Sstevel@tonic-gate * without external memory. They would be different on a 5700 with 5687c478bd9Sstevel@tonic-gate * external memory. 5697c478bd9Sstevel@tonic-gate * 5707c478bd9Sstevel@tonic-gate * Note: The higher send ring addresses and the mini ring shadow 5717c478bd9Sstevel@tonic-gate * buffer address are dummies - systems without external memory 5727c478bd9Sstevel@tonic-gate * are limited to 4 send rings and no mini receive ring. 5737c478bd9Sstevel@tonic-gate */ 5747c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_DMA 0x2000 5757c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_SEND_1_4 0x4000 5767c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 5777c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 5787c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 5797c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_BUFF_STD 0x6000 580087a28d1SDavid Gwynne #define NIC_MEM_SHADOW_BUFF_STD_5717 0x40000 5817c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 5827c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 5837c478bd9Sstevel@tonic-gate #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 5847c478bd9Sstevel@tonic-gate 5857c478bd9Sstevel@tonic-gate /* 5867c478bd9Sstevel@tonic-gate * Put this in the GENCOMM port to tell the firmware not to run PXE 5877c478bd9Sstevel@tonic-gate */ 5887c478bd9Sstevel@tonic-gate #define T3_MAGIC_NUMBER 0x4b657654u 5897c478bd9Sstevel@tonic-gate 5907c478bd9Sstevel@tonic-gate /* 5917c478bd9Sstevel@tonic-gate * The remaining registers appear in the low 32K of regular 5927c478bd9Sstevel@tonic-gate * PCI Memory Address Space 5937c478bd9Sstevel@tonic-gate */ 5947c478bd9Sstevel@tonic-gate 5957c478bd9Sstevel@tonic-gate /* 5967c478bd9Sstevel@tonic-gate * All the state machine control registers below have at least a 5977c478bd9Sstevel@tonic-gate * <RESET> bit and an <ENABLE> bit as defined below. Some also 5987c478bd9Sstevel@tonic-gate * have an <ATTN_ENABLE> bit. 5997c478bd9Sstevel@tonic-gate */ 6007c478bd9Sstevel@tonic-gate #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 6017c478bd9Sstevel@tonic-gate #define STATE_MACHINE_ENABLE_BIT 0x00000002 6027c478bd9Sstevel@tonic-gate #define STATE_MACHINE_RESET_BIT 0x00000001 6037c478bd9Sstevel@tonic-gate 6047c478bd9Sstevel@tonic-gate #define TRANSMIT_MAC_MODE_REG 0x045c 6057c478bd9Sstevel@tonic-gate #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 6067c478bd9Sstevel@tonic-gate #define SEND_DATA_COMPLETION_MODE_REG 0x1000 6077c478bd9Sstevel@tonic-gate #define SEND_BD_SELECTOR_MODE_REG 0x1400 6087c478bd9Sstevel@tonic-gate #define SEND_BD_INITIATOR_MODE_REG 0x1800 6097c478bd9Sstevel@tonic-gate #define SEND_BD_COMPLETION_MODE_REG 0x1c00 6107c478bd9Sstevel@tonic-gate 6117c478bd9Sstevel@tonic-gate #define RECEIVE_MAC_MODE_REG 0x0468 6127c478bd9Sstevel@tonic-gate #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 6137c478bd9Sstevel@tonic-gate #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 6147c478bd9Sstevel@tonic-gate #define RCV_DATA_COMPLETION_MODE_REG 0x2800 6157c478bd9Sstevel@tonic-gate #define RCV_BD_INITIATOR_MODE_REG 0x2c00 6167c478bd9Sstevel@tonic-gate #define RCV_BD_COMPLETION_MODE_REG 0x3000 6177c478bd9Sstevel@tonic-gate #define RCV_LIST_SELECTOR_MODE_REG 0x3400 6187c478bd9Sstevel@tonic-gate 6197c478bd9Sstevel@tonic-gate #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 6207c478bd9Sstevel@tonic-gate #define HOST_COALESCE_MODE_REG 0x3c00 6217c478bd9Sstevel@tonic-gate #define MEMORY_ARBITER_MODE_REG 0x4000 6227c478bd9Sstevel@tonic-gate #define BUFFER_MANAGER_MODE_REG 0x4400 623087a28d1SDavid Gwynne #define BUFFER_MANAGER_MODE_NO_TX_UNDERRUN 0x80000000 624087a28d1SDavid Gwynne #define BUFFER_MANAGER_MODE_MBLOW_ATTN_ENABLE 0x00000010 6257c478bd9Sstevel@tonic-gate #define READ_DMA_MODE_REG 0x4800 6267c478bd9Sstevel@tonic-gate #define WRITE_DMA_MODE_REG 0x4c00 6277c478bd9Sstevel@tonic-gate #define DMA_COMPLETION_MODE_REG 0x6400 628087a28d1SDavid Gwynne #define FAST_BOOT_PC 0x6894 629087a28d1SDavid Gwynne 630087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_REG 0x4900 631087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_REG2 0x4890 632087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_FIFO_OFLW_FIX 0x00000004 633087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_FIFO_LWM_1_5K 0x00000c00 634087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_FIFO_LWM_MASK 0x00000ff0 635087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_FIFO_HWM_1_5K 0x000c0000 636087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_FIFO_HWM_MASK 0x000ff000 637087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_TXMRGN_320B 0x28000000 638087a28d1SDavid Gwynne #define RDMA_RSRV_CTRL_TXMRGN_MASK 0xffe00000 639087a28d1SDavid Gwynne 640087a28d1SDavid Gwynne #define RDMA_CORR_CTRL_REG 0x4910 641087a28d1SDavid Gwynne #define RDMA_CORR_CTRL_REG2 0x48a0 642087a28d1SDavid Gwynne #define RDMA_CORR_CTRL_BLEN_BD_4K 0x00030000 643087a28d1SDavid Gwynne #define RDMA_CORR_CTRL_BLEN_LSO_4K 0x000c0000 644087a28d1SDavid Gwynne #define RDMA_CORR_CTRL_TX_LENGTH_WA 0x02000000 645087a28d1SDavid Gwynne 646087a28d1SDavid Gwynne #define BGE_NUM_RDMA_CHANNELS 4 647087a28d1SDavid Gwynne #define BGE_RDMA_LENGTH 0x4be0 6487c478bd9Sstevel@tonic-gate 6497c478bd9Sstevel@tonic-gate /* 6507c478bd9Sstevel@tonic-gate * Other bits in some of the above state machine control registers 6517c478bd9Sstevel@tonic-gate */ 6527c478bd9Sstevel@tonic-gate 6537c478bd9Sstevel@tonic-gate /* 6547c478bd9Sstevel@tonic-gate * Transmit MAC Mode Register 6557c478bd9Sstevel@tonic-gate * (TRANSMIT_MAC_MODE_REG, 0x045c) 6567c478bd9Sstevel@tonic-gate */ 657087a28d1SDavid Gwynne #define TRANSMIT_MODE_MBUF_LOCKUP_FIX 0x00000100 6587c478bd9Sstevel@tonic-gate #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 6597c478bd9Sstevel@tonic-gate #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 6607c478bd9Sstevel@tonic-gate #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 6617c478bd9Sstevel@tonic-gate 6627c478bd9Sstevel@tonic-gate /* 6637c478bd9Sstevel@tonic-gate * Receive MAC Mode Register 6647c478bd9Sstevel@tonic-gate * (RECEIVE_MAC_MODE_REG, 0x0468) 6657c478bd9Sstevel@tonic-gate */ 6667c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 6677c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 6687c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_PROMISCUOUS 0x00000100 6697c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 6707c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 6717c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 6727c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 6737c478bd9Sstevel@tonic-gate #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 6747c478bd9Sstevel@tonic-gate 6757c478bd9Sstevel@tonic-gate /* 6767c478bd9Sstevel@tonic-gate * Receive BD Initiator Mode Register 6777c478bd9Sstevel@tonic-gate * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 6787c478bd9Sstevel@tonic-gate * 6797c478bd9Sstevel@tonic-gate * Each of these bits controls whether ATTN is asserted 6807c478bd9Sstevel@tonic-gate * on a particular condition 6817c478bd9Sstevel@tonic-gate */ 6827c478bd9Sstevel@tonic-gate #define RCV_BD_DISABLED_RING_ATTN 0x00000004 6837c478bd9Sstevel@tonic-gate 6847c478bd9Sstevel@tonic-gate /* 6857c478bd9Sstevel@tonic-gate * Receive Data & Receive BD Initiator Mode Register 6867c478bd9Sstevel@tonic-gate * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 6877c478bd9Sstevel@tonic-gate * 6887c478bd9Sstevel@tonic-gate * Each of these bits controls whether ATTN is asserted 6897c478bd9Sstevel@tonic-gate * on a particular condition 6907c478bd9Sstevel@tonic-gate */ 6917c478bd9Sstevel@tonic-gate #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 6927c478bd9Sstevel@tonic-gate #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 6937c478bd9Sstevel@tonic-gate #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 6947c478bd9Sstevel@tonic-gate 6957c478bd9Sstevel@tonic-gate #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 6967c478bd9Sstevel@tonic-gate 6977c478bd9Sstevel@tonic-gate /* 6987c478bd9Sstevel@tonic-gate * Host Coalescing Mode Control Register 6997c478bd9Sstevel@tonic-gate * (HOST_COALESCE_MODE_REG, 0x3c00) 7007c478bd9Sstevel@tonic-gate */ 7017c478bd9Sstevel@tonic-gate #define COALESCE_64_BYTE_RINGS 12 7027c478bd9Sstevel@tonic-gate #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 7037c478bd9Sstevel@tonic-gate #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 7047c478bd9Sstevel@tonic-gate #define COALESCE_CLR_TICKS_TX 0x00000400 7057c478bd9Sstevel@tonic-gate #define COALESCE_CLR_TICKS_RX 0x00000200 7067c478bd9Sstevel@tonic-gate #define COALESCE_32_BYTE_STATUS 0x00000100 7077c478bd9Sstevel@tonic-gate #define COALESCE_64_BYTE_STATUS 0x00000080 7087c478bd9Sstevel@tonic-gate #define COALESCE_NOW 0x00000008 7097c478bd9Sstevel@tonic-gate 710a4de4ba2Sml /* 711a4de4ba2Sml * Memory Arbiter Mode Register 712a4de4ba2Sml * (MEMORY_ARBITER_MODE_REG, 0x4000) 713a4de4ba2Sml */ 714a4de4ba2Sml #define MEMORY_ARBITER_ENABLE 0x00000002 715a4de4ba2Sml 7167c478bd9Sstevel@tonic-gate /* 7177c478bd9Sstevel@tonic-gate * Buffer Manager Mode Register 7187c478bd9Sstevel@tonic-gate * (BUFFER_MANAGER_MODE_REG, 0x4400) 7197c478bd9Sstevel@tonic-gate * 7207c478bd9Sstevel@tonic-gate * In addition to the usual error-attn common to most state machines 7217c478bd9Sstevel@tonic-gate * this register has a separate bit for attn on running-low-on-mbufs 7227c478bd9Sstevel@tonic-gate */ 7237c478bd9Sstevel@tonic-gate #define BUFF_MGR_TEST_MODE 0x00000008 7247c478bd9Sstevel@tonic-gate #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 7257c478bd9Sstevel@tonic-gate 7267c478bd9Sstevel@tonic-gate #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 7277c478bd9Sstevel@tonic-gate 7287c478bd9Sstevel@tonic-gate /* 7297c478bd9Sstevel@tonic-gate * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 7307c478bd9Sstevel@tonic-gate * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 7317c478bd9Sstevel@tonic-gate * 7327c478bd9Sstevel@tonic-gate * These registers each contain a 2-bit priority field, which controls 7337c478bd9Sstevel@tonic-gate * the relative priority of that type of DMA (read vs. write vs. MSI), 7347c478bd9Sstevel@tonic-gate * and a set of bits that control whether ATTN is asserted on each 7357c478bd9Sstevel@tonic-gate * particular condition 7367c478bd9Sstevel@tonic-gate */ 7377c478bd9Sstevel@tonic-gate #define DMA_PRIORITY_MASK 0xc0000000 7387c478bd9Sstevel@tonic-gate #define DMA_PRIORITY_SHIFT 30 7397c478bd9Sstevel@tonic-gate #define ALL_DMA_ATTN_BITS 0x000003fc 7407c478bd9Sstevel@tonic-gate 74103a69b52Sml /* 74203a69b52Sml * BCM5755, 5755M, 5906, 5906M only 74303a69b52Sml * 1 - Enable Fix. Device will send out the status block before 74403a69b52Sml * the interrupt message 74503a69b52Sml * 0 - Disable fix. Device will send out the interrupt message 74603a69b52Sml * before the status block 74703a69b52Sml */ 74803a69b52Sml #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 74903a69b52Sml 7507c478bd9Sstevel@tonic-gate /* 7517c478bd9Sstevel@tonic-gate * End of state machine control register definitions 7527c478bd9Sstevel@tonic-gate */ 7537c478bd9Sstevel@tonic-gate 7547c478bd9Sstevel@tonic-gate 7557c478bd9Sstevel@tonic-gate /* 7565a506a18Syong tan - Sun Microsystems - Beijing China * High priority mailbox registers. 7577c478bd9Sstevel@tonic-gate * Mailbox Registers (8 bytes each, but high half unused) 7587c478bd9Sstevel@tonic-gate */ 7597c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_0_REG 0x0200 7607c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_1_REG 0x0208 7617c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_2_REG 0x0210 7627c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_3_REG 0x0218 7637c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 7647c478bd9Sstevel@tonic-gate 7655a506a18Syong tan - Sun Microsystems - Beijing China /* 7665a506a18Syong tan - Sun Microsystems - Beijing China * Low priority mailbox registers, for BCM5906, BCM5906M. 7675a506a18Syong tan - Sun Microsystems - Beijing China */ 7685a506a18Syong tan - Sun Microsystems - Beijing China #define INTERRUPT_LP_MBOX_0_REG 0x5800 7695a506a18Syong tan - Sun Microsystems - Beijing China 7707c478bd9Sstevel@tonic-gate /* 7717c478bd9Sstevel@tonic-gate * Ring Producer/Consumer Index (Mailbox) Registers 7727c478bd9Sstevel@tonic-gate */ 7737c478bd9Sstevel@tonic-gate #define RECV_STD_PROD_INDEX_REG 0x0268 7747c478bd9Sstevel@tonic-gate #define RECV_JUMBO_PROD_INDEX_REG 0x0270 7757c478bd9Sstevel@tonic-gate #define RECV_MINI_PROD_INDEX_REG 0x0278 7767c478bd9Sstevel@tonic-gate #define RECV_RING_CONS_INDEX_REGS 0x0280 7777c478bd9Sstevel@tonic-gate #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 7787c478bd9Sstevel@tonic-gate #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 7797c478bd9Sstevel@tonic-gate 7807c478bd9Sstevel@tonic-gate #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 7817c478bd9Sstevel@tonic-gate #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 7827c478bd9Sstevel@tonic-gate #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 7837c478bd9Sstevel@tonic-gate 7847c478bd9Sstevel@tonic-gate /* 7857c478bd9Sstevel@tonic-gate * Ethernet MAC Mode Register 7867c478bd9Sstevel@tonic-gate */ 7877c478bd9Sstevel@tonic-gate #define ETHERNET_MAC_MODE_REG 0x0400 788087a28d1SDavid Gwynne #define ETHERNET_MODE_APE_TX_EN 0x10000000 789087a28d1SDavid Gwynne #define ETHERNET_MODE_APE_RX_EN 0x08000000 7907c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 7917c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_RDE 0x00400000 7927c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_TDE 0x00200000 7937c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_MIP 0x00100000 7947c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 7957c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 7967c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_SEND_CFGS 0x00020000 7977c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 7987c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 7997c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 8007c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 8017c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 8027c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 8037c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_LINK_POLARITY 0x00000400 8047c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_MAX_DEFER 0x00000200 8057c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 8067c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_TAGGED_MODE 0x00000080 8077c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 8087c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 8097c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 8107c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 8117c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_PORTMODE_MII 0x00000004 8127c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 8137c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 8147c478bd9Sstevel@tonic-gate #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 8157c478bd9Sstevel@tonic-gate 8167c478bd9Sstevel@tonic-gate /* 8177c478bd9Sstevel@tonic-gate * Ethernet MAC Status & Event Registers 8187c478bd9Sstevel@tonic-gate */ 8197c478bd9Sstevel@tonic-gate #define ETHERNET_MAC_STATUS_REG 0x0404 8207c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_MI_INT 0x00800000 8217c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 8227c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 8237c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_PCS_ERROR 0x00000400 8247c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 8257c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 8267c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 8277c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 8287c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 8297c478bd9Sstevel@tonic-gate 8307c478bd9Sstevel@tonic-gate #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 8317c478bd9Sstevel@tonic-gate #define ETHERNET_EVENT_MI_INT 0x00800000 8327c478bd9Sstevel@tonic-gate #define ETHERNET_EVENT_LINK_INT 0x00001000 8337c478bd9Sstevel@tonic-gate #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 8347c478bd9Sstevel@tonic-gate 8357c478bd9Sstevel@tonic-gate /* 8367c478bd9Sstevel@tonic-gate * Ethernet MAC LED Control Register 8377c478bd9Sstevel@tonic-gate * 8387c478bd9Sstevel@tonic-gate * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 8397c478bd9Sstevel@tonic-gate * the external LED driver circuitry is wired up to assume that this mode 8407c478bd9Sstevel@tonic-gate * will always be selected. Software must not change it! 8417c478bd9Sstevel@tonic-gate */ 8427c478bd9Sstevel@tonic-gate #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 8437c478bd9Sstevel@tonic-gate #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 8447c478bd9Sstevel@tonic-gate #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 8457c478bd9Sstevel@tonic-gate #define LED_CONTROL_LED_MODE_MASK 0x00001800 8467c478bd9Sstevel@tonic-gate #define LED_CONTROL_LED_MODE_5700 0x00000000 8477c478bd9Sstevel@tonic-gate #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 8487c478bd9Sstevel@tonic-gate #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 8497c478bd9Sstevel@tonic-gate #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 8507c478bd9Sstevel@tonic-gate #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 8517c478bd9Sstevel@tonic-gate #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 8527c478bd9Sstevel@tonic-gate #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 8537c478bd9Sstevel@tonic-gate #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 8547c478bd9Sstevel@tonic-gate #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 8557c478bd9Sstevel@tonic-gate #define LED_CONTROL_TRAFFIC_LED 0x00000020 8567c478bd9Sstevel@tonic-gate #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 8577c478bd9Sstevel@tonic-gate #define LED_CONTROL_10MBPS_LED 0x00000008 8587c478bd9Sstevel@tonic-gate #define LED_CONTROL_100MBPS_LED 0x00000004 8597c478bd9Sstevel@tonic-gate #define LED_CONTROL_1000MBPS_LED 0x00000002 8607c478bd9Sstevel@tonic-gate #define LED_CONTROL_OVERRIDE_LINK 0x00000001 8617c478bd9Sstevel@tonic-gate #define LED_CONTROL_DEFAULT 0x02000800 8627c478bd9Sstevel@tonic-gate 8637c478bd9Sstevel@tonic-gate /* 8647c478bd9Sstevel@tonic-gate * MAC Address registers 8657c478bd9Sstevel@tonic-gate * 8667c478bd9Sstevel@tonic-gate * These four eight-byte registers each hold one unicast address 8677c478bd9Sstevel@tonic-gate * (six bytes), right justified & zero-filled on the left. 8687c478bd9Sstevel@tonic-gate * They will normally all be set to the same value, as a station 8697c478bd9Sstevel@tonic-gate * usually only has one h/w address. The value in register 0 is 8707c478bd9Sstevel@tonic-gate * used for pause packets; any of the four can be specified for 8717c478bd9Sstevel@tonic-gate * substitution into other transmitted packets if required. 8727c478bd9Sstevel@tonic-gate */ 8737c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_0_REG 0x0410 8747c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_1_REG 0x0418 8757c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_2_REG 0x0420 8767c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_3_REG 0x0428 8777c478bd9Sstevel@tonic-gate 8787c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 8797c478bd9Sstevel@tonic-gate #define MAC_ADDRESS_REGS_MAX 4 8807c478bd9Sstevel@tonic-gate 8817c478bd9Sstevel@tonic-gate /* 8827c478bd9Sstevel@tonic-gate * More MAC Registers ... 8837c478bd9Sstevel@tonic-gate */ 8847c478bd9Sstevel@tonic-gate #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 8857c478bd9Sstevel@tonic-gate #define MAC_RX_MTU_SIZE_REG 0x043c 8867c478bd9Sstevel@tonic-gate #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 8877c478bd9Sstevel@tonic-gate #define MAC_TX_LENGTHS_REG 0x0464 8887c478bd9Sstevel@tonic-gate #define MAC_TX_LENGTHS_DEFAULT 0x00002620 8897c478bd9Sstevel@tonic-gate 8907c478bd9Sstevel@tonic-gate /* 8917c478bd9Sstevel@tonic-gate * MII access registers 8927c478bd9Sstevel@tonic-gate */ 8937c478bd9Sstevel@tonic-gate #define MI_COMMS_REG 0x044c 8947c478bd9Sstevel@tonic-gate #define MI_COMMS_START 0x20000000 8957c478bd9Sstevel@tonic-gate #define MI_COMMS_READ_FAILED 0x10000000 8967c478bd9Sstevel@tonic-gate #define MI_COMMS_COMMAND_MASK 0x0c000000 8977c478bd9Sstevel@tonic-gate #define MI_COMMS_COMMAND_READ 0x08000000 8987c478bd9Sstevel@tonic-gate #define MI_COMMS_COMMAND_WRITE 0x04000000 8997c478bd9Sstevel@tonic-gate #define MI_COMMS_ADDRESS_MASK 0x03e00000 9007c478bd9Sstevel@tonic-gate #define MI_COMMS_ADDRESS_SHIFT 21 9017c478bd9Sstevel@tonic-gate #define MI_COMMS_REGISTER_MASK 0x001f0000 9027c478bd9Sstevel@tonic-gate #define MI_COMMS_REGISTER_SHIFT 16 9037c478bd9Sstevel@tonic-gate #define MI_COMMS_DATA_MASK 0x0000ffff 9047c478bd9Sstevel@tonic-gate #define MI_COMMS_DATA_SHIFT 0 9057c478bd9Sstevel@tonic-gate 9067c478bd9Sstevel@tonic-gate #define MI_STATUS_REG 0x0450 9077c478bd9Sstevel@tonic-gate #define MI_STATUS_10MBPS 0x00000002 9087c478bd9Sstevel@tonic-gate #define MI_STATUS_LINK 0x00000001 9097c478bd9Sstevel@tonic-gate 9107c478bd9Sstevel@tonic-gate #define MI_MODE_REG 0x0454 9117c478bd9Sstevel@tonic-gate #define MI_MODE_CLOCK_MASK 0x001f0000 9127c478bd9Sstevel@tonic-gate #define MI_MODE_AUTOPOLL 0x00000010 9137c478bd9Sstevel@tonic-gate #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 9147c478bd9Sstevel@tonic-gate #define MI_MODE_DEFAULT 0x000c0000 9157c478bd9Sstevel@tonic-gate 9167c478bd9Sstevel@tonic-gate #define MI_AUTOPOLL_STATUS_REG 0x0458 9177c478bd9Sstevel@tonic-gate #define MI_AUTOPOLL_ERROR 0x00000001 9187c478bd9Sstevel@tonic-gate 9197c478bd9Sstevel@tonic-gate #define TRANSMIT_MAC_STATUS_REG 0x0460 9207c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 9217c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 9227c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_LINK_UP 0x00000008 9237c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_SENT_XON 0x00000004 9247c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 9257c478bd9Sstevel@tonic-gate #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 9267c478bd9Sstevel@tonic-gate 9277c478bd9Sstevel@tonic-gate #define RECEIVE_MAC_STATUS_REG 0x046c 9287c478bd9Sstevel@tonic-gate #define RECEIVE_STATUS_RCVD_XON 0x00000004 9297c478bd9Sstevel@tonic-gate #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 9307c478bd9Sstevel@tonic-gate #define RECEIVE_STATUS_SENT_XOFF 0x00000001 9317c478bd9Sstevel@tonic-gate 9327c478bd9Sstevel@tonic-gate /* 933256e438eSzh * These four-byte registers constitute a hash table for deciding 9347c478bd9Sstevel@tonic-gate * whether to accept incoming multicast packets. The bits are 9357c478bd9Sstevel@tonic-gate * numbered in big-endian fashion, from hash 0 => the MSB of 9367c478bd9Sstevel@tonic-gate * register 0 to hash 127 => the LSB of the highest-numbered 9377c478bd9Sstevel@tonic-gate * register. 9387c478bd9Sstevel@tonic-gate * 9397c478bd9Sstevel@tonic-gate * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 9407c478bd9Sstevel@tonic-gate * enabled by setting the appropriate bit in the Rx MAC mode 9417c478bd9Sstevel@tonic-gate * register. Otherwise, and on all earlier chips, the table 9427c478bd9Sstevel@tonic-gate * is only 128 bits (registers 0-3). 9437c478bd9Sstevel@tonic-gate */ 9447c478bd9Sstevel@tonic-gate #define MAC_HASH_0_REG 0x0470 9457c478bd9Sstevel@tonic-gate #define MAC_HASH_1_REG 0x0474 9467c478bd9Sstevel@tonic-gate #define MAC_HASH_2_REG 0x0478 9477c478bd9Sstevel@tonic-gate #define MAC_HASH_3_REG 0x047c 9487c478bd9Sstevel@tonic-gate #define MAC_HASH_4_REG 0x???? 9497c478bd9Sstevel@tonic-gate #define MAC_HASH_5_REG 0x???? 9507c478bd9Sstevel@tonic-gate #define MAC_HASH_6_REG 0x???? 9517c478bd9Sstevel@tonic-gate #define MAC_HASH_7_REG 0x???? 9527c478bd9Sstevel@tonic-gate #define MAC_HASH_REG(n) (0x470+4*(n)) 9537c478bd9Sstevel@tonic-gate 9547c478bd9Sstevel@tonic-gate /* 9557c478bd9Sstevel@tonic-gate * Receive Rules Registers: 16 pairs of control+mask/value pairs 9567c478bd9Sstevel@tonic-gate */ 9577c478bd9Sstevel@tonic-gate #define RCV_RULES_CONTROL_0_REG 0x0480 9587c478bd9Sstevel@tonic-gate #define RCV_RULES_MASK_0_REG 0x0484 9597c478bd9Sstevel@tonic-gate #define RCV_RULES_CONTROL_15_REG 0x04f8 9607c478bd9Sstevel@tonic-gate #define RCV_RULES_MASK_15_REG 0x04fc 9617c478bd9Sstevel@tonic-gate #define RCV_RULES_CONFIG_REG 0x0500 9627c478bd9Sstevel@tonic-gate #define RCV_RULES_CONFIG_DEFAULT 0x00000008 9637c478bd9Sstevel@tonic-gate 9647c478bd9Sstevel@tonic-gate #define RECV_RULES_NUM_MAX 16 9657c478bd9Sstevel@tonic-gate #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 9667c478bd9Sstevel@tonic-gate #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 9677c478bd9Sstevel@tonic-gate 9687c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_ENABLE 0x80000000 9697c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_AND 0x40000000 9707c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_P1 0x20000000 9717c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_P2 0x10000000 9727c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_P3 0x08000000 9737c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_MASK 0x04000000 9747c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_DISCARD 0x02000000 9757c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_MAP 0x01000000 9767c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 9777c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OP 0x00030000 9787c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OP_EQ 0x00000000 9797c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OP_NEQ 0x00010000 9807c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OP_GREAT 0x00020000 9817c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OP_LESS 0x00030000 9827c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER 0x0000e000 9837c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 9847c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER_IP 0x00002000 9857c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER_TCP 0x00004000 9867c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER_UDP 0x00006000 9877c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_HEADER_DATA 0x00008000 9887c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 9897c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 9907c478bd9Sstevel@tonic-gate RECV_RULE_CTL_CLASS_BITS) 9917c478bd9Sstevel@tonic-gate #define RECV_RULE_CTL_OFFSET 0x000000ff 9927c478bd9Sstevel@tonic-gate 9937c478bd9Sstevel@tonic-gate /* 9947c478bd9Sstevel@tonic-gate * Receive Rules definition 9957c478bd9Sstevel@tonic-gate */ 996da14cebeSEric Cheng #define ETHERHEADER_DEST_OFFSET 0x00 9977c478bd9Sstevel@tonic-gate #define IPHEADER_PROTO_OFFSET 0x08 9987c478bd9Sstevel@tonic-gate #define IPHEADER_SIP_OFFSET 0x0c 999da14cebeSEric Cheng #define IPHEADER_DIP_OFFSET 0x10 1000da14cebeSEric Cheng #define TCPHEADER_SPORT_OFFSET 0x00 1001da14cebeSEric Cheng #define TCPHEADER_DPORT_OFFSET 0x02 1002da14cebeSEric Cheng #define UDPHEADER_SPORT_OFFSET 0x00 1003da14cebeSEric Cheng #define UDPHEADER_DPORT_OFFSET 0x02 1004da14cebeSEric Cheng 1005da14cebeSEric Cheng #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 1006da14cebeSEric Cheng RECV_RULE_CTL_CLASS((ring))) 1007da14cebeSEric Cheng 1008da14cebeSEric Cheng #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 1009da14cebeSEric Cheng 1010da14cebeSEric Cheng #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 1011da14cebeSEric Cheng RECV_RULE_CTL_HEADER_FRAME | \ 1012da14cebeSEric Cheng ETHERHEADER_DEST_OFFSET) 1013da14cebeSEric Cheng 1014da14cebeSEric Cheng #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 1015da14cebeSEric Cheng RECV_RULE_CTL_HEADER_FRAME | \ 1016da14cebeSEric Cheng ETHERHEADER_DEST_OFFSET + 4) 1017da14cebeSEric Cheng 1018da14cebeSEric Cheng #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 1019da14cebeSEric Cheng IPHEADER_DIP_OFFSET) 1020da14cebeSEric Cheng 1021da14cebeSEric Cheng #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 1022da14cebeSEric Cheng IPHEADER_SIP_OFFSET) 10237c478bd9Sstevel@tonic-gate 1024da14cebeSEric Cheng #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 10257c478bd9Sstevel@tonic-gate RECV_RULE_CTL_HEADER_IP | \ 10267c478bd9Sstevel@tonic-gate IPHEADER_PROTO_OFFSET) 10277c478bd9Sstevel@tonic-gate 1028da14cebeSEric Cheng #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 1029da14cebeSEric Cheng RECV_RULE_CTL_HEADER_TCP | \ 1030da14cebeSEric Cheng TCPHEADER_SPORT_OFFSET) 10317c478bd9Sstevel@tonic-gate 1032da14cebeSEric Cheng #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 1033da14cebeSEric Cheng RECV_RULE_CTL_HEADER_TCP | \ 1034da14cebeSEric Cheng TCPHEADER_DPORT_OFFSET) 1035da14cebeSEric Cheng 1036da14cebeSEric Cheng #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 1037da14cebeSEric Cheng RECV_RULE_CTL_HEADER_UDP | \ 1038da14cebeSEric Cheng UDPHEADER_SPORT_OFFSET) 1039da14cebeSEric Cheng 1040da14cebeSEric Cheng #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 1041da14cebeSEric Cheng RECV_RULE_CTL_HEADER_UDP | \ 1042da14cebeSEric Cheng UDPHEADER_DPORT_OFFSET) 10437c478bd9Sstevel@tonic-gate 10447c478bd9Sstevel@tonic-gate /* 10457c478bd9Sstevel@tonic-gate * 1000BaseX low-level access registers 10467c478bd9Sstevel@tonic-gate */ 10477c478bd9Sstevel@tonic-gate #define MAC_GIGABIT_PCS_TEST_REG 0x0440 10487c478bd9Sstevel@tonic-gate #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 10497c478bd9Sstevel@tonic-gate #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 10507c478bd9Sstevel@tonic-gate #define TX_1000BASEX_AUTONEG_REG 0x0444 10517c478bd9Sstevel@tonic-gate #define RX_1000BASEX_AUTONEG_REG 0x0448 10527c478bd9Sstevel@tonic-gate 10537c478bd9Sstevel@tonic-gate /* 10547c478bd9Sstevel@tonic-gate * Autoneg code bits for the 1000BASE-X AUTONEG registers 10557c478bd9Sstevel@tonic-gate */ 10567c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_PAUSE 0x00008000 10577c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 10587c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 10597c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_NEXT_PAGE 0x00000080 10607c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 10617c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_FAULT_MASK 0x00000030 10627c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 10637c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 10647c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 10657c478bd9Sstevel@tonic-gate #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 10667c478bd9Sstevel@tonic-gate 10677c478bd9Sstevel@tonic-gate /* 10687c478bd9Sstevel@tonic-gate * SerDes Registers (5703S/5704S only) 10697c478bd9Sstevel@tonic-gate */ 10707c478bd9Sstevel@tonic-gate #define SERDES_CONTROL_REG 0x0590 10717c478bd9Sstevel@tonic-gate #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 10727c478bd9Sstevel@tonic-gate #define SERDES_CONTROL_COMMA_DETECT 0x00010000 10737c478bd9Sstevel@tonic-gate #define SERDES_CONTROL_TX_DISABLE 0x00004000 10747c478bd9Sstevel@tonic-gate #define SERDES_STATUS_REG 0x0594 10757c478bd9Sstevel@tonic-gate #define SERDES_STATUS_COMMA_DETECTED 0x00000100 10767c478bd9Sstevel@tonic-gate #define SERDES_STATUS_RXSTAT 0x000000ff 10777c478bd9Sstevel@tonic-gate 1078087a28d1SDavid Gwynne /* 5780/5714 only */ 1079087a28d1SDavid Gwynne #define SERDES_RX_CONTROL 0x000005b0 1080087a28d1SDavid Gwynne #define SERDES_RX_CONTROL_SIG_DETECT 0x00000400 1081087a28d1SDavid Gwynne 1082dc3f9a75Syong tan - Sun Microsystems - Beijing China /* 1083087a28d1SDavid Gwynne * SGMII Status Register (5717/18/19/20 only) 1084dc3f9a75Syong tan - Sun Microsystems - Beijing China */ 1085dc3f9a75Syong tan - Sun Microsystems - Beijing China #define SGMII_STATUS_REG 0x5B4 1086dc3f9a75Syong tan - Sun Microsystems - Beijing China #define MEDIA_SELECTION_MODE 0x00000100 1087dc3f9a75Syong tan - Sun Microsystems - Beijing China 10888eb6c4f9Sly /* 10898eb6c4f9Sly * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 10908eb6c4f9Sly */ 10918eb6c4f9Sly #define STAT_IFHCOUT_OCTETS_REG 0x0800 10928eb6c4f9Sly #define STAT_ETHER_COLLIS_REG 0x0808 10938eb6c4f9Sly #define STAT_OUTXON_SENT_REG 0x080c 10948eb6c4f9Sly #define STAT_OUTXOFF_SENT_REG 0x0810 10958eb6c4f9Sly #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 10968eb6c4f9Sly #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 10978eb6c4f9Sly #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 10988eb6c4f9Sly #define STAT_DOT3_DEFERED_TX_REG 0x0824 10998eb6c4f9Sly #define STAT_DOT3_EXCE_COLLI_REG 0x082c 11008eb6c4f9Sly #define STAT_DOT3_LATE_COLLI_REG 0x0830 11018eb6c4f9Sly #define STAT_IFHCOUT_UPKGS_REG 0x086c 11028eb6c4f9Sly #define STAT_IFHCOUT_MPKGS_REG 0x0870 11038eb6c4f9Sly #define STAT_IFHCOUT_BPKGS_REG 0x0874 11048eb6c4f9Sly 11058eb6c4f9Sly #define STAT_IFHCIN_OCTETS_REG 0x0880 11068eb6c4f9Sly #define STAT_ETHER_FRAGMENT_REG 0x0888 11078eb6c4f9Sly #define STAT_IFHCIN_UPKGS_REG 0x088c 11088eb6c4f9Sly #define STAT_IFHCIN_MPKGS_REG 0x0890 11098eb6c4f9Sly #define STAT_IFHCIN_BPKGS_REG 0x0894 11108eb6c4f9Sly 11118eb6c4f9Sly #define STAT_DOT3_FCS_ERR_REG 0x0898 11128eb6c4f9Sly #define STAT_DOT3_ALIGN_ERR_REG 0x089c 11138eb6c4f9Sly #define STAT_XON_PAUSE_RX_REG 0x08a0 11148eb6c4f9Sly #define STAT_XOFF_PAUSE_RX_REG 0x08a4 11158eb6c4f9Sly #define STAT_MAC_CTRL_RX_REG 0x08a8 11168eb6c4f9Sly #define STAT_XOFF_STATE_ENTER_REG 0x08ac 11178eb6c4f9Sly #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 11188eb6c4f9Sly #define STAT_ETHER_JABBERS_REG 0x08b4 11198eb6c4f9Sly #define STAT_ETHER_UNDERSIZE_REG 0x08b8 11208eb6c4f9Sly #define SIZE_OF_STATISTIC_REG 0x1B 11217c478bd9Sstevel@tonic-gate /* 11227c478bd9Sstevel@tonic-gate * Send Data Initiator Registers 11237c478bd9Sstevel@tonic-gate */ 11247c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_CONTROL_REG 0x0c08 11257c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_ZERO 0x00000010 11267c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_FLUSH 0x00000008 11277c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_CLEAR 0x00000004 11287c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_FASTER 0x00000002 11297c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_ENABLE 0x00000001 11307c478bd9Sstevel@tonic-gate 11317c478bd9Sstevel@tonic-gate #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 11327c478bd9Sstevel@tonic-gate 11337c478bd9Sstevel@tonic-gate /* 11347c478bd9Sstevel@tonic-gate * Send Buffer Descriptor Selector Control Registers 11357c478bd9Sstevel@tonic-gate */ 11367c478bd9Sstevel@tonic-gate #define SEND_BD_SELECTOR_STATUS_REG 0x1404 11377c478bd9Sstevel@tonic-gate #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 11387c478bd9Sstevel@tonic-gate #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 11397c478bd9Sstevel@tonic-gate 11407c478bd9Sstevel@tonic-gate /* 11417c478bd9Sstevel@tonic-gate * Receive List Placement Registers 11427c478bd9Sstevel@tonic-gate */ 11437c478bd9Sstevel@tonic-gate #define RCV_LP_CONFIG_REG 0x2010 11447c478bd9Sstevel@tonic-gate #define RCV_LP_CONFIG_DEFAULT 0x00000009 11457c478bd9Sstevel@tonic-gate #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 11467c478bd9Sstevel@tonic-gate 11477c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_CONTROL_REG 0x2014 11487c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_ZERO 0x00000010 11497c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_FLUSH 0x00000008 11507c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_CLEAR 0x00000004 11517c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_FASTER 0x00000002 11527c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_ENABLE 0x00000001 11537c478bd9Sstevel@tonic-gate 11547c478bd9Sstevel@tonic-gate #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1155542d98abSzh #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 11567c478bd9Sstevel@tonic-gate 11577c478bd9Sstevel@tonic-gate /* 11587c478bd9Sstevel@tonic-gate * Receive Data & BD Initiator Registers 11597c478bd9Sstevel@tonic-gate */ 11607c478bd9Sstevel@tonic-gate #define RCV_INITIATOR_STATUS_REG 0x2404 11617c478bd9Sstevel@tonic-gate 11627c478bd9Sstevel@tonic-gate /* 11637c478bd9Sstevel@tonic-gate * Receive Buffer Descriptor Ring Control Block Registers 11647c478bd9Sstevel@tonic-gate * NB: sixteen bytes (128 bits) each 11657c478bd9Sstevel@tonic-gate */ 11667c478bd9Sstevel@tonic-gate #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 11677c478bd9Sstevel@tonic-gate #define STD_RCV_BD_RING_RCB_REG 0x2450 11687c478bd9Sstevel@tonic-gate #define MINI_RCV_BD_RING_RCB_REG 0x2460 11697c478bd9Sstevel@tonic-gate 11707c478bd9Sstevel@tonic-gate /* 11717c478bd9Sstevel@tonic-gate * Receive Buffer Descriptor Ring Replenish Threshold Registers 11727c478bd9Sstevel@tonic-gate */ 11737c478bd9Sstevel@tonic-gate #define MINI_RCV_BD_REPLENISH_REG 0x2c14 11747c478bd9Sstevel@tonic-gate #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 11757c478bd9Sstevel@tonic-gate #define STD_RCV_BD_REPLENISH_REG 0x2c18 11767c478bd9Sstevel@tonic-gate #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 11777c478bd9Sstevel@tonic-gate #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 11787c478bd9Sstevel@tonic-gate #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 11797c478bd9Sstevel@tonic-gate 1180dc3f9a75Syong tan - Sun Microsystems - Beijing China /* 1181*a2876d03SRobert Mustacchi * CPMU registers (5717/18/19/20/57765 only) 1182087a28d1SDavid Gwynne */ 1183087a28d1SDavid Gwynne #define CPMU_CLCK_ORIDE_REG 0x3624 1184087a28d1SDavid Gwynne #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1185087a28d1SDavid Gwynne #define CPMU_STATUS_REG 0x362c 1186087a28d1SDavid Gwynne #define CPMU_STATUS_FUNC_NUM 0x20000000 1187087a28d1SDavid Gwynne #define CPMU_STATUS_FUNC_NUM_SHIFT 29 1188*a2876d03SRobert Mustacchi #define CPMU_STATUS_FUNC_NUM_5719 0xc0000000 1189087a28d1SDavid Gwynne #define CPMU_STATUS_FUNC_NUM_5719_SHIFT 30 1190*a2876d03SRobert Mustacchi #define CPMU_PADRNG_CTL_REG 0x3668 1191*a2876d03SRobert Mustacchi #define CPMU_PADRNG_CTL_RDIV2 0x00040000 1192087a28d1SDavid Gwynne 1193087a28d1SDavid Gwynne /* 1194087a28d1SDavid Gwynne * EEE registers (5718/19/20 only) 1195dc3f9a75Syong tan - Sun Microsystems - Beijing China */ 1196087a28d1SDavid Gwynne #define EEE_MODE_REG 0x36b0 1197087a28d1SDavid Gwynne #define EEE_MODE_APE_TX_DET_EN 0x00000004 1198087a28d1SDavid Gwynne #define EEE_MODE_ERLY_L1_XIT_DET 0x00000008 1199087a28d1SDavid Gwynne #define EEE_MODE_SND_IDX_DET_EN 0x00000040 1200087a28d1SDavid Gwynne #define EEE_MODE_LPI_ENABLE 0x00000080 1201087a28d1SDavid Gwynne #define EEE_MODE_LPI_IN_TX 0x00000100 1202087a28d1SDavid Gwynne #define EEE_MODE_LPI_IN_RX 0x00000200 1203087a28d1SDavid Gwynne #define EEE_MODE_EEE_ENABLE 0x00100000 1204087a28d1SDavid Gwynne 1205087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T1_CONTROL_REG 0x36b4 1206087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T1_PCIEXIT_2047US 0x07ff0000 1207087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T1_LNKIDLE_2047US 0x000007ff 1208087a28d1SDavid Gwynne 1209087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T2_CONTROL_REG 0x36b8 1210087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T2_APE_TX_2047US 0x07ff0000 1211087a28d1SDavid Gwynne #define EEE_DEBOUNCE_T2_TXIDXEQ_2047US 0x000007ff 1212087a28d1SDavid Gwynne 1213087a28d1SDavid Gwynne #define EEE_LINK_IDLE_CONTROL_REG 0x36bc 1214087a28d1SDavid Gwynne #define EEE_LINK_IDLE_PCIE_NL0 0x01000000 1215087a28d1SDavid Gwynne #define EEE_LINK_IDLE_UART_IDL 0x00000004 1216087a28d1SDavid Gwynne #define EEE_LINK_IDLE_APE_TX_MT 0x00000002 1217087a28d1SDavid Gwynne 1218087a28d1SDavid Gwynne #define EEE_CONTROL_REG 0x36d0 1219087a28d1SDavid Gwynne #define EEE_CONTROL_EXIT_16_5_US 0x0000019d 1220087a28d1SDavid Gwynne #define EEE_CONTROL_EXIT_36_US 0x00000384 1221087a28d1SDavid Gwynne #define EEE_CONTROL_EXIT_20_1_US 0x000001f8 1222087a28d1SDavid Gwynne 1223087a28d1SDavid Gwynne /* Clause 45 expansion registers */ 1224087a28d1SDavid Gwynne #define EEE_CL45_D7_RESULT_STAT 0x803e 1225087a28d1SDavid Gwynne #define EEE_CL45_D7_RESULT_STAT_LP_100TX 0x0002 1226087a28d1SDavid Gwynne #define EEE_CL45_D7_RESULT_STAT_LP_1000T 0x0004 1227087a28d1SDavid Gwynne 1228087a28d1SDavid Gwynne #define MDIO_MMD_AN 0x0007 1229087a28d1SDavid Gwynne #define MDIO_AN_EEE_ADV 0x003c 1230dc3f9a75Syong tan - Sun Microsystems - Beijing China 12317c478bd9Sstevel@tonic-gate /* 12327c478bd9Sstevel@tonic-gate * Host Coalescing Engine Control Registers 12337c478bd9Sstevel@tonic-gate */ 12347c478bd9Sstevel@tonic-gate #define RCV_COALESCE_TICKS_REG 0x3c08 12357c478bd9Sstevel@tonic-gate #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 12367c478bd9Sstevel@tonic-gate #define SEND_COALESCE_TICKS_REG 0x3c0c 12377c478bd9Sstevel@tonic-gate #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 12387c478bd9Sstevel@tonic-gate #define RCV_COALESCE_MAX_BD_REG 0x3c10 12397c478bd9Sstevel@tonic-gate #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 12407c478bd9Sstevel@tonic-gate #define SEND_COALESCE_MAX_BD_REG 0x3c14 12417c478bd9Sstevel@tonic-gate #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 12427c478bd9Sstevel@tonic-gate #define RCV_COALESCE_INT_TICKS_REG 0x3c18 12437c478bd9Sstevel@tonic-gate #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 12447c478bd9Sstevel@tonic-gate #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 12457c478bd9Sstevel@tonic-gate #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 12467c478bd9Sstevel@tonic-gate #define RCV_COALESCE_INT_BD_REG 0x3c20 12477c478bd9Sstevel@tonic-gate #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 12487c478bd9Sstevel@tonic-gate #define SEND_COALESCE_INT_BD_REG 0x3c24 12497c478bd9Sstevel@tonic-gate #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 12507c478bd9Sstevel@tonic-gate #define STATISTICS_TICKS_REG 0x3c28 12517c478bd9Sstevel@tonic-gate #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 12527c478bd9Sstevel@tonic-gate #define STATISTICS_HOST_ADDR_REG 0x3c30 12537c478bd9Sstevel@tonic-gate #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 12547c478bd9Sstevel@tonic-gate #define STATISTICS_BASE_ADDR_REG 0x3c40 12557c478bd9Sstevel@tonic-gate #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 12567c478bd9Sstevel@tonic-gate #define FLOW_ATTN_REG 0x3c48 12577c478bd9Sstevel@tonic-gate 12587c478bd9Sstevel@tonic-gate #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 12597c478bd9Sstevel@tonic-gate #define NIC_STD_RECV_INDEX_REG 0x3c54 12607c478bd9Sstevel@tonic-gate #define NIC_MINI_RECV_INDEX_REG 0x3c58 12617c478bd9Sstevel@tonic-gate #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 12627c478bd9Sstevel@tonic-gate #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 12637c478bd9Sstevel@tonic-gate 12647c478bd9Sstevel@tonic-gate /* 12657c478bd9Sstevel@tonic-gate * Mbuf Pool Initialisation & Watermark Registers 12667c478bd9Sstevel@tonic-gate * 12677c478bd9Sstevel@tonic-gate * There are some conflicts in the PRM; compare the recommendations 12687c478bd9Sstevel@tonic-gate * on pp. 115, 236, and 339. The values here were recommended by 12697c478bd9Sstevel@tonic-gate * dkim@broadcom.com (and the PRM should be corrected soon ;-) 12707c478bd9Sstevel@tonic-gate */ 12717c478bd9Sstevel@tonic-gate #define BUFFER_MANAGER_STATUS_REG 0x4404 12727c478bd9Sstevel@tonic-gate #define MBUF_POOL_BASE_REG 0x4408 12737c478bd9Sstevel@tonic-gate #define MBUF_POOL_BASE_DEFAULT 0x00008000 12747c478bd9Sstevel@tonic-gate #define MBUF_POOL_BASE_5721 0x00010000 12758eb6c4f9Sly #define MBUF_POOL_BASE_5704 0x00010000 12767c478bd9Sstevel@tonic-gate #define MBUF_POOL_BASE_5705 0x00010000 12777c478bd9Sstevel@tonic-gate #define MBUF_POOL_LENGTH_REG 0x440c 12787c478bd9Sstevel@tonic-gate #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 12797c478bd9Sstevel@tonic-gate #define MBUF_POOL_LENGTH_5704 0x00010000 12807c478bd9Sstevel@tonic-gate #define MBUF_POOL_LENGTH_5705 0x00008000 12817c478bd9Sstevel@tonic-gate #define MBUF_POOL_LENGTH_5721 0x00008000 12827c478bd9Sstevel@tonic-gate #define RDMA_MBUF_LOWAT_REG 0x4410 12831b5c96f3Sly #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 12841b5c96f3Sly #define RDMA_MBUF_LOWAT_5705 0x00000000 12855a506a18Syong tan - Sun Microsystems - Beijing China #define RDMA_MBUF_LOWAT_5906 0x00000000 12867c478bd9Sstevel@tonic-gate #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 12871b5c96f3Sly #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 12887c478bd9Sstevel@tonic-gate #define MAC_RX_MBUF_LOWAT_REG 0x4414 12891b5c96f3Sly #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 12901b5c96f3Sly #define MAC_RX_MBUF_LOWAT_5705 0x00000010 12915a506a18Syong tan - Sun Microsystems - Beijing China #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1292dc3f9a75Syong tan - Sun Microsystems - Beijing China #define MAC_RX_MBUF_LOWAT_5717 0x0000002a 12937c478bd9Sstevel@tonic-gate #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 12941b5c96f3Sly #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 12957c478bd9Sstevel@tonic-gate #define MBUF_HIWAT_REG 0x4418 12961b5c96f3Sly #define MBUF_HIWAT_DEFAULT 0x00000060 12971b5c96f3Sly #define MBUF_HIWAT_5705 0x00000060 12985a506a18Syong tan - Sun Microsystems - Beijing China #define MBUF_HIWAT_5906 0x00000010 1299dc3f9a75Syong tan - Sun Microsystems - Beijing China #define MBUF_HIWAT_5717 0x000000a0 13007c478bd9Sstevel@tonic-gate #define MBUF_HIWAT_JUMBO 0x0000017c 13011b5c96f3Sly #define MBUF_HIWAT_5714_JUMBO 0x00000096 13027c478bd9Sstevel@tonic-gate 13037c478bd9Sstevel@tonic-gate /* 13047c478bd9Sstevel@tonic-gate * DMA Descriptor Pool Initialisation & Watermark Registers 13057c478bd9Sstevel@tonic-gate */ 13067c478bd9Sstevel@tonic-gate #define DMAD_POOL_BASE_REG 0x442c 13077c478bd9Sstevel@tonic-gate #define DMAD_POOL_BASE_DEFAULT 0x00002000 13087c478bd9Sstevel@tonic-gate #define DMAD_POOL_LENGTH_REG 0x4430 13097c478bd9Sstevel@tonic-gate #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 13107c478bd9Sstevel@tonic-gate #define DMAD_POOL_LOWAT_REG 0x4434 13117c478bd9Sstevel@tonic-gate #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 13127c478bd9Sstevel@tonic-gate #define DMAD_POOL_HIWAT_REG 0x4438 13137c478bd9Sstevel@tonic-gate #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 13147c478bd9Sstevel@tonic-gate 13157c478bd9Sstevel@tonic-gate /* 13167c478bd9Sstevel@tonic-gate * More threshold/watermark registers ... 13177c478bd9Sstevel@tonic-gate */ 13187c478bd9Sstevel@tonic-gate #define RECV_FLOW_THRESHOLD_REG 0x4458 13197c478bd9Sstevel@tonic-gate #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 13207c478bd9Sstevel@tonic-gate #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 13217c478bd9Sstevel@tonic-gate 13227c478bd9Sstevel@tonic-gate /* 13237c478bd9Sstevel@tonic-gate * Read/Write DMA Status Registers 13247c478bd9Sstevel@tonic-gate */ 13257c478bd9Sstevel@tonic-gate #define READ_DMA_STATUS_REG 0x4804 13267c478bd9Sstevel@tonic-gate #define WRITE_DMA_STATUS_REG 0x4c04 13277c478bd9Sstevel@tonic-gate 13287c478bd9Sstevel@tonic-gate /* 13297c478bd9Sstevel@tonic-gate * RX/TX RISC Registers 13307c478bd9Sstevel@tonic-gate */ 13317c478bd9Sstevel@tonic-gate #define RX_RISC_MODE_REG 0x5000 13327c478bd9Sstevel@tonic-gate #define RX_RISC_STATE_REG 0x5004 13337c478bd9Sstevel@tonic-gate #define RX_RISC_PC_REG 0x501c 13347c478bd9Sstevel@tonic-gate #define TX_RISC_MODE_REG 0x5400 13357c478bd9Sstevel@tonic-gate #define TX_RISC_STATE_REG 0x5404 13367c478bd9Sstevel@tonic-gate #define TX_RISC_PC_REG 0x541c 13377c478bd9Sstevel@tonic-gate 13385a506a18Syong tan - Sun Microsystems - Beijing China /* 13395a506a18Syong tan - Sun Microsystems - Beijing China * V? RISC Registerss 13405a506a18Syong tan - Sun Microsystems - Beijing China */ 13415a506a18Syong tan - Sun Microsystems - Beijing China #define VCPU_STATUS_REG 0x5100 13425a506a18Syong tan - Sun Microsystems - Beijing China #define VCPU_INIT_DONE 0x04000000 13435a506a18Syong tan - Sun Microsystems - Beijing China #define VCPU_DRV_RESET 0x08000000 13445a506a18Syong tan - Sun Microsystems - Beijing China 13455a506a18Syong tan - Sun Microsystems - Beijing China #define VCPU_EXT_CTL 0x6890 13465a506a18Syong tan - Sun Microsystems - Beijing China #define VCPU_EXT_CTL_HALF 0x00400000 13475a506a18Syong tan - Sun Microsystems - Beijing China 13487c478bd9Sstevel@tonic-gate #define FTQ_RESET_REG 0x5c00 13497c478bd9Sstevel@tonic-gate 13508eb6c4f9Sly #define MSI_MODE_REG 0x6000 13518eb6c4f9Sly #define MSI_PRI_HIGHEST 0xc0000000 13528eb6c4f9Sly #define MSI_MSI_ENABLE 0x00000002 13535952d588Szh #define MSI_ERROR_ATTENTION 0x0000001c 13545952d588Szh 13555952d588Szh #define MSI_STATUS_REG 0x6004 13568eb6c4f9Sly 13577c478bd9Sstevel@tonic-gate #define MODE_CONTROL_REG 0x6800 13587c478bd9Sstevel@tonic-gate #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 13597c478bd9Sstevel@tonic-gate #define MODE_4X_NIC_SEND_RINGS 0x20000000 13607c478bd9Sstevel@tonic-gate #define MODE_INT_ON_FLOW_ATTN 0x10000000 13617c478bd9Sstevel@tonic-gate #define MODE_INT_ON_DMA_ATTN 0x08000000 13627c478bd9Sstevel@tonic-gate #define MODE_INT_ON_MAC_ATTN 0x04000000 13637c478bd9Sstevel@tonic-gate #define MODE_INT_ON_RXRISC_ATTN 0x02000000 13647c478bd9Sstevel@tonic-gate #define MODE_INT_ON_TXRISC_ATTN 0x01000000 13657c478bd9Sstevel@tonic-gate #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 13667c478bd9Sstevel@tonic-gate #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 13677c478bd9Sstevel@tonic-gate #define MODE_HOST_SEND_BDS 0x00020000 13687c478bd9Sstevel@tonic-gate #define MODE_HOST_STACK_UP 0x00010000 13697c478bd9Sstevel@tonic-gate #define MODE_FORCE_32_BIT_PCI 0x00008000 13707c478bd9Sstevel@tonic-gate #define MODE_NO_INT_ON_RECV 0x00004000 13717c478bd9Sstevel@tonic-gate #define MODE_NO_INT_ON_SEND 0x00002000 13727c478bd9Sstevel@tonic-gate #define MODE_ALLOW_BAD_FRAMES 0x00000800 13737c478bd9Sstevel@tonic-gate #define MODE_NO_CRC 0x00000400 13747c478bd9Sstevel@tonic-gate #define MODE_NO_FRAME_CRACKING 0x00000200 13757c478bd9Sstevel@tonic-gate #define MODE_WORD_SWAP_FRAME 0x00000020 13767c478bd9Sstevel@tonic-gate #define MODE_BYTE_SWAP_FRAME 0x00000010 13777c478bd9Sstevel@tonic-gate #define MODE_WORD_SWAP_NONFRAME 0x00000004 13787c478bd9Sstevel@tonic-gate #define MODE_BYTE_SWAP_NONFRAME 0x00000002 13797c478bd9Sstevel@tonic-gate #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 13807c478bd9Sstevel@tonic-gate 13817c478bd9Sstevel@tonic-gate /* 13827c478bd9Sstevel@tonic-gate * Miscellaneous Configuration Register 13837c478bd9Sstevel@tonic-gate * 13847c478bd9Sstevel@tonic-gate * This contains various bits relating to power control (which differ 13857c478bd9Sstevel@tonic-gate * among different members of the chip family), but the important bits 13867c478bd9Sstevel@tonic-gate * for our purposes are the RESET bit and the Timer Prescaler field. 13877c478bd9Sstevel@tonic-gate * 13887c478bd9Sstevel@tonic-gate * The RESET bit in this register serves to reset the whole chip, even 13897c478bd9Sstevel@tonic-gate * including the PCI interface(!) Once it's set, the chip will not 13907c478bd9Sstevel@tonic-gate * respond to ANY accesses -- not even CONFIG space -- until the reset 13917c478bd9Sstevel@tonic-gate * completes internally. According to the PRM, this should take less 13927c478bd9Sstevel@tonic-gate * than 100us. Any access during this period will get a bus error. 13937c478bd9Sstevel@tonic-gate * 13947c478bd9Sstevel@tonic-gate * The Timer Prescaler field must be programmed so that the timer period 13957c478bd9Sstevel@tonic-gate * is as near as possible to 1us. The value in this field should be 13967c478bd9Sstevel@tonic-gate * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 13977c478bd9Sstevel@tonic-gate * the Core Clock should always be 66MHz (independently of the bus speed, 13987c478bd9Sstevel@tonic-gate * at least for PCI rather than PCI-X), so this register must be set to 13997c478bd9Sstevel@tonic-gate * the value 0x82 ((66-1) << 1). 14007c478bd9Sstevel@tonic-gate */ 14017c478bd9Sstevel@tonic-gate #define CORE_CLOCK_MHZ 66 14027c478bd9Sstevel@tonic-gate #define MISC_CONFIG_REG 0x6804 14037c478bd9Sstevel@tonic-gate #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 14048eb6c4f9Sly #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 14057c478bd9Sstevel@tonic-gate #define MISC_CONFIG_POWERDOWN 0x00100000 14067c478bd9Sstevel@tonic-gate #define MISC_CONFIG_POWER_STATE 0x00060000 14077c478bd9Sstevel@tonic-gate #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 14087c478bd9Sstevel@tonic-gate #define MISC_CONFIG_RESET_BIT 0x00000001 14097c478bd9Sstevel@tonic-gate #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 14105a506a18Syong tan - Sun Microsystems - Beijing China #define MISC_CONFIG_EPHY_IDDQ 0x00200000 14117c478bd9Sstevel@tonic-gate 14127c478bd9Sstevel@tonic-gate /* 14137c478bd9Sstevel@tonic-gate * Miscellaneous Local Control Register (MLCR) 14147c478bd9Sstevel@tonic-gate */ 14157c478bd9Sstevel@tonic-gate #define MISC_LOCAL_CONTROL_REG 0x6808 1416087a28d1SDavid Gwynne 14177c478bd9Sstevel@tonic-gate #define MLCR_PCI_CTRL_SELECT 0x10000000 14187c478bd9Sstevel@tonic-gate #define MLCR_LEGACY_PCI_MODE 0x08000000 14197c478bd9Sstevel@tonic-gate #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 14207c478bd9Sstevel@tonic-gate #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 14217c478bd9Sstevel@tonic-gate #define MLCR_SSRAM_TYPE 0x00400000 14227c478bd9Sstevel@tonic-gate #define MLCR_BANK_SELECT 0x00200000 1423087a28d1SDavid Gwynne 1424087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_16M 0x00180000 1425087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_8M 0x00140000 1426087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_4M 0x00100000 1427087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_2M 0x000c0000 1428087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_1M 0x00080000 1429087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_512K 0x00040000 1430087a28d1SDavid Gwynne #define MLCR_SRAM_SIZE_256K 0x00000000 14317c478bd9Sstevel@tonic-gate #define MLCR_SRAM_SIZE_MASK 0x001c0000 14327c478bd9Sstevel@tonic-gate 1433087a28d1SDavid Gwynne #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 14347c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1435087a28d1SDavid Gwynne 14367c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 14377c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 14387c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 14397c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1440087a28d1SDavid Gwynne 14417c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 14427c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 14437c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 14447c478bd9Sstevel@tonic-gate #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 14457c478bd9Sstevel@tonic-gate 1446087a28d1SDavid Gwynne #define MLCR_GPIO_OUTPUT3 0x00000080 1447087a28d1SDavid Gwynne #define MLCR_GPIO_OE3 0x00000040 1448087a28d1SDavid Gwynne #define MLCR_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1449087a28d1SDavid Gwynne #define MLCR_GPIO_INPUT3 0x00000020 1450087a28d1SDavid Gwynne #define MLCR_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1451087a28d1SDavid Gwynne #define MLCR_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1452087a28d1SDavid Gwynne 14537c478bd9Sstevel@tonic-gate #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 14547c478bd9Sstevel@tonic-gate #define MLCR_SET_INT 0x00000004 /* W/O */ 14557c478bd9Sstevel@tonic-gate #define MLCR_CLR_INT 0x00000002 /* W/O */ 14567c478bd9Sstevel@tonic-gate #define MLCR_INTA_STATE 0x00000001 /* R/O */ 14577c478bd9Sstevel@tonic-gate 14587c478bd9Sstevel@tonic-gate /* 14597c478bd9Sstevel@tonic-gate * This value defines all GPIO bits as INPUTS, but sets their default 14607c478bd9Sstevel@tonic-gate * values as outputs to HIGH, on the assumption that external circuits 14617c478bd9Sstevel@tonic-gate * (if any) will probably be active-LOW with passive pullups. 14627c478bd9Sstevel@tonic-gate * 14637c478bd9Sstevel@tonic-gate * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 14647c478bd9Sstevel@tonic-gate * just this fashion. It has to be set as an OUTPUT and driven LOW to 14657c478bd9Sstevel@tonic-gate * enable writing. Otherwise, the SEEPROM is protected. 14667c478bd9Sstevel@tonic-gate */ 1467087a28d1SDavid Gwynne #define MLCR_DEFAULT (MLCR_AUTO_SEEPROM_ACCESS | \ 1468087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_2 | \ 1469087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_1 | \ 1470087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_0) 1471087a28d1SDavid Gwynne 1472087a28d1SDavid Gwynne #define MLCR_DEFAULT_5714 (MLCR_PCI_CTRL_SELECT | \ 1473087a28d1SDavid Gwynne MLCR_LEGACY_PCI_MODE | \ 1474087a28d1SDavid Gwynne MLCR_AUTO_SEEPROM_ACCESS | \ 1475087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_2 | \ 1476087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_1 | \ 1477087a28d1SDavid Gwynne MLCR_MISC_PINS_OUTPUT_0 | \ 1478087a28d1SDavid Gwynne MLCR_USE_SIG_DETECT) 1479087a28d1SDavid Gwynne 1480087a28d1SDavid Gwynne #define MLCR_DEFAULT_5717 (MLCR_AUTO_SEEPROM_ACCESS) 14817c478bd9Sstevel@tonic-gate 1482*a2876d03SRobert Mustacchi /* 1483*a2876d03SRobert Mustacchi * MLCR_AUTO_SEEPROM_ACCESS is marked reserved in the 57765 family, so we don't 1484*a2876d03SRobert Mustacchi * try to enable it like on the 5717. 1485*a2876d03SRobert Mustacchi */ 1486*a2876d03SRobert Mustacchi #define MLCR_DEFAULT_57765 0 1487*a2876d03SRobert Mustacchi 14887c478bd9Sstevel@tonic-gate /* 14897c478bd9Sstevel@tonic-gate * Serial EEPROM Data/Address Registers (auto-access mode) 14907c478bd9Sstevel@tonic-gate */ 14917c478bd9Sstevel@tonic-gate #define SERIAL_EEPROM_DATA_REG 0x683c 14927c478bd9Sstevel@tonic-gate #define SERIAL_EEPROM_ADDRESS_REG 0x6838 14937c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_READ 0x80000000 14947c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_WRITE 0x00000000 14957c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_COMPLETE 0x40000000 14967c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_RESET 0x20000000 14977c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 14987c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_START 0x02000000 14997c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 15007c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 15017c478bd9Sstevel@tonic-gate 15027c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 15037c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 15047c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 15057c478bd9Sstevel@tonic-gate 15067c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 15077c478bd9Sstevel@tonic-gate #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 15087c478bd9Sstevel@tonic-gate 15097c478bd9Sstevel@tonic-gate /* 15107c478bd9Sstevel@tonic-gate * "Linearised" address mask, treating multiple devices as consecutive 15117c478bd9Sstevel@tonic-gate */ 15127c478bd9Sstevel@tonic-gate #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 15137c478bd9Sstevel@tonic-gate 15147c478bd9Sstevel@tonic-gate /* 15157c478bd9Sstevel@tonic-gate * Non-Volatile Memory Interface Registers 15167c478bd9Sstevel@tonic-gate * Note: on chips that support the flash interface (5702+), flash is the 15177c478bd9Sstevel@tonic-gate * default and the legacy seeprom interface must be explicitly enabled 15187c478bd9Sstevel@tonic-gate * if required. On older chips (5700/01), SEEPROM is the default (and 15197c478bd9Sstevel@tonic-gate * only) non-volatile memory available, and these registers don't exist! 15207c478bd9Sstevel@tonic-gate */ 15217c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_REG 0x7000 15227c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_LAST 0x00000100 15237c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_FIRST 0x00000080 15247c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_RD 0x00000000 15257c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_WR 0x00000020 15267c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_DOIT 0x00000010 15277c478bd9Sstevel@tonic-gate #define NVM_FLASH_CMD_DONE 0x00000008 15287c478bd9Sstevel@tonic-gate 15297c478bd9Sstevel@tonic-gate #define NVM_FLASH_WRITE_REG 0x7008 15307c478bd9Sstevel@tonic-gate #define NVM_FLASH_READ_REG 0x7010 15317c478bd9Sstevel@tonic-gate 15327c478bd9Sstevel@tonic-gate #define NVM_FLASH_ADDR_REG 0x700c 15337c478bd9Sstevel@tonic-gate #define NVM_FLASH_ADDR_MASK 0x00fffffc 15347c478bd9Sstevel@tonic-gate 15357c478bd9Sstevel@tonic-gate #define NVM_CONFIG1_REG 0x7014 15367c478bd9Sstevel@tonic-gate #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 15377c478bd9Sstevel@tonic-gate #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 15387c478bd9Sstevel@tonic-gate #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 15397c478bd9Sstevel@tonic-gate #define NVM_CFG1_BUFFERED_MODE 0x00000002 15407c478bd9Sstevel@tonic-gate #define NVM_CFG1_FLASH_MODE 0x00000001 15417c478bd9Sstevel@tonic-gate 15427c478bd9Sstevel@tonic-gate #define NVM_SW_ARBITRATION_REG 0x7020 1543087a28d1SDavid Gwynne #define NVM_READ_REQ3 0x00008000 1544087a28d1SDavid Gwynne #define NVM_READ_REQ2 0x00004000 1545087a28d1SDavid Gwynne #define NVM_READ_REQ1 0x00002000 1546087a28d1SDavid Gwynne #define NVM_READ_REQ0 0x00001000 1547087a28d1SDavid Gwynne #define NVM_WON_REQ3 0x00000800 1548087a28d1SDavid Gwynne #define NVM_WON_REQ2 0x00000400 1549087a28d1SDavid Gwynne #define NVM_WON_REQ1 0x00000200 1550087a28d1SDavid Gwynne #define NVM_WON_REQ0 0x00000100 1551087a28d1SDavid Gwynne #define NVM_RESET_REQ3 0x00000080 1552087a28d1SDavid Gwynne #define NVM_RESET_REQ2 0x00000040 1553087a28d1SDavid Gwynne #define NVM_RESET_REQ1 0x00000020 1554087a28d1SDavid Gwynne #define NVM_RESET_REQ0 0x00000010 1555087a28d1SDavid Gwynne #define NVM_SET_REQ3 0x00000008 1556087a28d1SDavid Gwynne #define NVM_SET_REQ2 0x00000004 1557087a28d1SDavid Gwynne #define NVM_SET_REQ1 0x00000002 1558087a28d1SDavid Gwynne #define NVM_SET_REQ0 0x00000001 1559087a28d1SDavid Gwynne 1560087a28d1SDavid Gwynne #define EEPROM_MAGIC 0x669955aa 1561087a28d1SDavid Gwynne #define EEPROM_MAGIC_FW 0xa5000000 1562087a28d1SDavid Gwynne #define EEPROM_MAGIC_FW_MSK 0xff000000 1563087a28d1SDavid Gwynne #define EEPROM_SB_FORMAT_MASK 0x00e00000 1564087a28d1SDavid Gwynne #define EEPROM_SB_FORMAT_1 0x00200000 1565087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_MASK 0x001f0000 1566087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_0 0x00000000 1567087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_2 0x00020000 1568087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_3 0x00030000 1569087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_4 0x00040000 1570087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_5 0x00050000 1571087a28d1SDavid Gwynne #define EEPROM_SB_REVISION_6 0x00060000 1572087a28d1SDavid Gwynne #define EEPROM_MAGIC_HW 0xabcd 1573087a28d1SDavid Gwynne #define EEPROM_MAGIC_HW_MSK 0xffff 1574087a28d1SDavid Gwynne 1575087a28d1SDavid Gwynne #define NVM_DIR_START 0x18 1576087a28d1SDavid Gwynne #define NVM_DIR_END 0x78 1577087a28d1SDavid Gwynne #define NVM_DIRENT_SIZE 0xc 1578087a28d1SDavid Gwynne #define NVM_DIRTYPE_SHIFT 24 1579087a28d1SDavid Gwynne #define NVM_DIRTYPE_LENMSK 0x003fffff 1580087a28d1SDavid Gwynne #define NVM_DIRTYPE_ASFINI 1 1581087a28d1SDavid Gwynne #define NVM_DIRTYPE_EXTVPD 20 1582087a28d1SDavid Gwynne #define NVM_PTREV_BCVER 0x94 1583087a28d1SDavid Gwynne #define NVM_BCVER_MAJMSK 0x0000ff00 1584087a28d1SDavid Gwynne #define NVM_BCVER_MAJSFT 8 1585087a28d1SDavid Gwynne #define NVM_BCVER_MINMSK 0x000000ff 15867c478bd9Sstevel@tonic-gate 15878eb6c4f9Sly /* 15888eb6c4f9Sly * NVM access register 1589*a2876d03SRobert Mustacchi * Applicable to BCM5721,BCM5751,BCM5752,BCM5714,BCM57725 15908eb6c4f9Sly * and BCM5715 only. 15918eb6c4f9Sly */ 1592087a28d1SDavid Gwynne #define NVM_ACCESS_REG 0x7024 1593087a28d1SDavid Gwynne #define NVM_WRITE_ENABLE 0x00000002 1594087a28d1SDavid Gwynne #define NVM_ACCESS_ENABLE 0x00000001 15958eb6c4f9Sly 15967c478bd9Sstevel@tonic-gate /* 15977c478bd9Sstevel@tonic-gate * TLP Control Register 15987c478bd9Sstevel@tonic-gate * Applicable to BCM5721 and BCM5751 only 15997c478bd9Sstevel@tonic-gate */ 16007c478bd9Sstevel@tonic-gate #define TLP_CONTROL_REG 0x7c00 16017c478bd9Sstevel@tonic-gate #define TLP_DATA_FIFO_PROTECT 0x02000000 16027c478bd9Sstevel@tonic-gate 16037c478bd9Sstevel@tonic-gate /* 16047c478bd9Sstevel@tonic-gate * PHY Test Control Register 16057c478bd9Sstevel@tonic-gate * Applicable to BCM5721 and BCM5751 only 16067c478bd9Sstevel@tonic-gate */ 16077c478bd9Sstevel@tonic-gate #define PHY_TEST_CTRL_REG 0x7e2c 16087c478bd9Sstevel@tonic-gate #define PHY_PCIE_SCRAM_MODE 0x20 16097c478bd9Sstevel@tonic-gate #define PHY_PCIE_LTASS_MODE 0x40 16107c478bd9Sstevel@tonic-gate 16117c478bd9Sstevel@tonic-gate /* 16127c478bd9Sstevel@tonic-gate * The internal firmware expects a certain layout of the non-volatile 16137c478bd9Sstevel@tonic-gate * memory (if fitted), and will check for it during startup, and use the 16147c478bd9Sstevel@tonic-gate * contents to initialise various internal parameters if it looks good. 16157c478bd9Sstevel@tonic-gate * 16167c478bd9Sstevel@tonic-gate * The offsets and field definitions below refer to where to find some 16177c478bd9Sstevel@tonic-gate * important values, and how to interpret them ... 16187c478bd9Sstevel@tonic-gate */ 16197c478bd9Sstevel@tonic-gate #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 16205a506a18Syong tan - Sun Microsystems - Beijing China #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 16217c478bd9Sstevel@tonic-gate 16227c478bd9Sstevel@tonic-gate /* 16237c478bd9Sstevel@tonic-gate * Vendor-specific MII registers 16247c478bd9Sstevel@tonic-gate */ 1625087a28d1SDavid Gwynne 1626087a28d1SDavid Gwynne #define MII_MMD_CTRL 0x0d /* MMD Access Control register */ 1627087a28d1SDavid Gwynne #define MII_MMD_CTRL_DATA_NOINC 0x4000 1628087a28d1SDavid Gwynne #define MII_MMD_ADDRESS_DATA 0x0e /* MMD Address Data register */ 1629087a28d1SDavid Gwynne 1630087a28d1SDavid Gwynne #define MII_RXR_COUNTERS 0x14 /* Local/Remote Rx Counts */ 1631087a28d1SDavid Gwynne #define MII_DSP_RW_PORT 0x15 /* DSP read/write port */ 1632087a28d1SDavid Gwynne #define MII_DSP_CONTROL 0x16 /* DSP control register */ 1633087a28d1SDavid Gwynne #define MII_DSP_ADDRESS 0x17 /* DSP address register */ 1634087a28d1SDavid Gwynne 1635087a28d1SDavid Gwynne #define MII_DSP_TAP26 0x001a 1636087a28d1SDavid Gwynne #define MII_DSP_TAP26_ALNOKO 0x0001 1637087a28d1SDavid Gwynne #define MII_DSP_TAP26_RMRXSTO 0x0002 1638087a28d1SDavid Gwynne #define MII_DSP_TAP26_OPCSINPT 0x0004 1639087a28d1SDavid Gwynne 1640087a28d1SDavid Gwynne #define MII_DSP_CH34TP2 0x4022 1641087a28d1SDavid Gwynne #define MII_DSP_CH34TP2_HIBW01 0x017b 1642087a28d1SDavid Gwynne 16437c478bd9Sstevel@tonic-gate #define MII_EXT_CONTROL MII_VENDOR(0) 16447c478bd9Sstevel@tonic-gate #define MII_EXT_STATUS MII_VENDOR(1) 16457c478bd9Sstevel@tonic-gate #define MII_RCV_ERR_COUNT MII_VENDOR(2) 16467c478bd9Sstevel@tonic-gate #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 16477c478bd9Sstevel@tonic-gate #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 16487c478bd9Sstevel@tonic-gate #define MII_AUX_CONTROL MII_VENDOR(8) 16497c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS MII_VENDOR(9) 16507c478bd9Sstevel@tonic-gate #define MII_INTR_STATUS MII_VENDOR(10) 16517c478bd9Sstevel@tonic-gate #define MII_INTR_MASK MII_VENDOR(11) 16527c478bd9Sstevel@tonic-gate #define MII_HCD_STATUS MII_VENDOR(13) 16537c478bd9Sstevel@tonic-gate 16547c478bd9Sstevel@tonic-gate #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 16557c478bd9Sstevel@tonic-gate 16567c478bd9Sstevel@tonic-gate /* 16577c478bd9Sstevel@tonic-gate * Bits in the MII_EXT_CONTROL register 16587c478bd9Sstevel@tonic-gate */ 16597c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 16607c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 16617c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 16627c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 16637c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 16647c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 16657c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 16667c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 16677c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 16687c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 16697c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 16707c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 16717c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 16727c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 16737c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 16747c478bd9Sstevel@tonic-gate #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 16757c478bd9Sstevel@tonic-gate 16767c478bd9Sstevel@tonic-gate /* 16777c478bd9Sstevel@tonic-gate * Bits in the MII_EXT_STATUS register 16787c478bd9Sstevel@tonic-gate */ 16797c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 16807c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 16817c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_MDIX_STATE 0x2000 16827c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 16837c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 16847c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 16857c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 16867c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_LINK_STATUS 0x0100 16877c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_CRC_ERROR 0x0080 16887c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 16897c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 16907c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 16917c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 16927c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 16937c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_LOCK_ERROR 0x0002 16947c478bd9Sstevel@tonic-gate #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 16957c478bd9Sstevel@tonic-gate 16967c478bd9Sstevel@tonic-gate /* 1697256e438eSzh * The AUX CONTROL register is seriously weird! 16987c478bd9Sstevel@tonic-gate * 16997c478bd9Sstevel@tonic-gate * It hides (up to) eight 'shadow' registers. When writing, which one 17007c478bd9Sstevel@tonic-gate * of them is written is determined by the low-order bits of the data 17017c478bd9Sstevel@tonic-gate * written(!), but when reading, which one is read is determined by the 17027c478bd9Sstevel@tonic-gate * value previously written to (part of) one of the shadow registers!!! 17037c478bd9Sstevel@tonic-gate */ 17047c478bd9Sstevel@tonic-gate 17057c478bd9Sstevel@tonic-gate /* 17067c478bd9Sstevel@tonic-gate * Shadow register numbers 17077c478bd9Sstevel@tonic-gate */ 17087c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORMAL 0 17097c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_10BASE_T 1 17107c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_POWER 2 17117c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_TEST_1 4 17127c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_MISC 7 17137c478bd9Sstevel@tonic-gate 17147c478bd9Sstevel@tonic-gate /* 17157c478bd9Sstevel@tonic-gate * Selected bits in some of the shadow registers ... 17167c478bd9Sstevel@tonic-gate */ 17177c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 17187c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 17197c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 17207c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 17217c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 17227c478bd9Sstevel@tonic-gate 17237c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 17247c478bd9Sstevel@tonic-gate 17257c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 17267c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 17277c478bd9Sstevel@tonic-gate 1728087a28d1SDavid Gwynne #define MII_AUX_CTRL_TX_6DB 0x0400 1729087a28d1SDavid Gwynne #define MII_AUX_CTRL_SMDSP_ENA 0x0800 1730087a28d1SDavid Gwynne 17317c478bd9Sstevel@tonic-gate /* 17327c478bd9Sstevel@tonic-gate * Write this value to the AUX control register 17337c478bd9Sstevel@tonic-gate * to select which shadow register will be read 17347c478bd9Sstevel@tonic-gate */ 17357c478bd9Sstevel@tonic-gate #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 17367c478bd9Sstevel@tonic-gate 17377c478bd9Sstevel@tonic-gate /* 17387c478bd9Sstevel@tonic-gate * Bits in the MII_AUX_STATUS register 17397c478bd9Sstevel@tonic-gate */ 17407c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_MASK 0x0700 17417c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_1000_F 0x0700 17427c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_1000_H 0x0600 17437c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_100_F 0x0500 17447c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_100_4 0x0400 17457c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_100_H 0x0300 17467c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_10_F 0x0200 17477c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_10_H 0x0100 17487c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_NONE 0x0000 17497c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_MODE_SHIFT 8 17507c478bd9Sstevel@tonic-gate 17517c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_PAR_FAULT 0x0080 17527c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_REM_FAULT 0x0040 17537c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 17547c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 17557c478bd9Sstevel@tonic-gate 17567c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_LINKUP 0x0004 17577c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_RX_PAUSE 0x0002 17587c478bd9Sstevel@tonic-gate #define MII_AUX_STATUS_TX_PAUSE 0x0001 17597c478bd9Sstevel@tonic-gate 17605a506a18Syong tan - Sun Microsystems - Beijing China #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 17615a506a18Syong tan - Sun Microsystems - Beijing China #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 17625a506a18Syong tan - Sun Microsystems - Beijing China #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 17635a506a18Syong tan - Sun Microsystems - Beijing China 17647c478bd9Sstevel@tonic-gate /* 17657c478bd9Sstevel@tonic-gate * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 17667c478bd9Sstevel@tonic-gate */ 17677c478bd9Sstevel@tonic-gate #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 17687c478bd9Sstevel@tonic-gate #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 17697c478bd9Sstevel@tonic-gate #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 17707c478bd9Sstevel@tonic-gate #define MII_INTR_LINK_SPEED_CHANGE 0x0004 17717c478bd9Sstevel@tonic-gate #define MII_INTR_LINK_STATUS_CHANGE 0x0002 17727c478bd9Sstevel@tonic-gate 17737c478bd9Sstevel@tonic-gate 17747c478bd9Sstevel@tonic-gate /* 17757c478bd9Sstevel@tonic-gate * Third section: 1776*a2876d03SRobert Mustacchi * Hardware-defined data structures 17777c478bd9Sstevel@tonic-gate * 17787c478bd9Sstevel@tonic-gate * Note that the chip is naturally BIG-endian, so, for a big-endian 1779256e438eSzh * host, the structures defined below match those described in the PRM. 17807c478bd9Sstevel@tonic-gate * For little-endian hosts, some structures have to be swapped around. 17817c478bd9Sstevel@tonic-gate */ 17827c478bd9Sstevel@tonic-gate 17837c478bd9Sstevel@tonic-gate #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 17847c478bd9Sstevel@tonic-gate #error Host endianness not defined 17857c478bd9Sstevel@tonic-gate #endif 17867c478bd9Sstevel@tonic-gate 17877c478bd9Sstevel@tonic-gate /* 17887c478bd9Sstevel@tonic-gate * Architectural constants: absolute maximum numbers of each type of ring 17897c478bd9Sstevel@tonic-gate */ 17907c478bd9Sstevel@tonic-gate #ifdef BGE_EXT_MEM 17917c478bd9Sstevel@tonic-gate #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 17927c478bd9Sstevel@tonic-gate #else 17937c478bd9Sstevel@tonic-gate #define BGE_SEND_RINGS_MAX 4 17947c478bd9Sstevel@tonic-gate #endif 17957c478bd9Sstevel@tonic-gate #define BGE_SEND_RINGS_MAX_5705 1 17967c478bd9Sstevel@tonic-gate #define BGE_RECV_RINGS_MAX 16 17977c478bd9Sstevel@tonic-gate #define BGE_RECV_RINGS_MAX_5705 1 17987c478bd9Sstevel@tonic-gate #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 17997c478bd9Sstevel@tonic-gate /* only with ext mem) */ 18007c478bd9Sstevel@tonic-gate 18017c478bd9Sstevel@tonic-gate #define BGE_SEND_SLOTS_MAX 512 18027c478bd9Sstevel@tonic-gate #define BGE_STD_SLOTS_MAX 512 18037c478bd9Sstevel@tonic-gate #define BGE_JUMBO_SLOTS_MAX 256 18047c478bd9Sstevel@tonic-gate #define BGE_MINI_SLOTS_MAX 1024 18057c478bd9Sstevel@tonic-gate #define BGE_RECV_SLOTS_MAX 2048 18067c478bd9Sstevel@tonic-gate #define BGE_RECV_SLOTS_5705 512 18077c478bd9Sstevel@tonic-gate #define BGE_RECV_SLOTS_5782 512 18087c478bd9Sstevel@tonic-gate #define BGE_RECV_SLOTS_5721 512 18097c478bd9Sstevel@tonic-gate 18107c478bd9Sstevel@tonic-gate /* 18117c478bd9Sstevel@tonic-gate * Hardware-defined Ring Control Block 18127c478bd9Sstevel@tonic-gate */ 18137c478bd9Sstevel@tonic-gate typedef struct { 18147c478bd9Sstevel@tonic-gate uint64_t host_ring_addr; 18157c478bd9Sstevel@tonic-gate #ifdef _BIG_ENDIAN 18167c478bd9Sstevel@tonic-gate uint16_t max_len; 18177c478bd9Sstevel@tonic-gate uint16_t flags; 18187c478bd9Sstevel@tonic-gate uint32_t nic_ring_addr; 18197c478bd9Sstevel@tonic-gate #else 18207c478bd9Sstevel@tonic-gate uint32_t nic_ring_addr; 18217c478bd9Sstevel@tonic-gate uint16_t flags; 18227c478bd9Sstevel@tonic-gate uint16_t max_len; 18237c478bd9Sstevel@tonic-gate #endif /* _BIG_ENDIAN */ 18247c478bd9Sstevel@tonic-gate } bge_rcb_t; 18257c478bd9Sstevel@tonic-gate 18267c478bd9Sstevel@tonic-gate #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 18277c478bd9Sstevel@tonic-gate #define RCB_FLAG_RING_DISABLED 0x0002 18287c478bd9Sstevel@tonic-gate 18297c478bd9Sstevel@tonic-gate /* 18307c478bd9Sstevel@tonic-gate * Hardware-defined Send Buffer Descriptor 18317c478bd9Sstevel@tonic-gate */ 18327c478bd9Sstevel@tonic-gate typedef struct { 18337c478bd9Sstevel@tonic-gate uint64_t host_buf_addr; 18347c478bd9Sstevel@tonic-gate #ifdef _BIG_ENDIAN 18357c478bd9Sstevel@tonic-gate uint16_t len; 18367c478bd9Sstevel@tonic-gate uint16_t flags; 18377c478bd9Sstevel@tonic-gate uint16_t reserved; 18387c478bd9Sstevel@tonic-gate uint16_t vlan_tci; 18397c478bd9Sstevel@tonic-gate #else 18407c478bd9Sstevel@tonic-gate uint16_t vlan_tci; 18417c478bd9Sstevel@tonic-gate uint16_t reserved; 18427c478bd9Sstevel@tonic-gate uint16_t flags; 18437c478bd9Sstevel@tonic-gate uint16_t len; 18447c478bd9Sstevel@tonic-gate #endif /* _BIG_ENDIAN */ 18457c478bd9Sstevel@tonic-gate } bge_sbd_t; 18467c478bd9Sstevel@tonic-gate 18477c478bd9Sstevel@tonic-gate #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 18487c478bd9Sstevel@tonic-gate #define SBD_FLAG_IP_CKSUM 0x0002 18497c478bd9Sstevel@tonic-gate #define SBD_FLAG_PACKET_END 0x0004 18507c478bd9Sstevel@tonic-gate #define SBD_FLAG_IP_FRAG 0x0008 1851087a28d1SDavid Gwynne #define SBD_FLAG_JMB_PKT 0x0008 18527c478bd9Sstevel@tonic-gate #define SBD_FLAG_IP_FRAG_END 0x0010 18537c478bd9Sstevel@tonic-gate 18547c478bd9Sstevel@tonic-gate #define SBD_FLAG_VLAN_TAG 0x0040 18557c478bd9Sstevel@tonic-gate #define SBD_FLAG_COAL_NOW 0x0080 18567c478bd9Sstevel@tonic-gate #define SBD_FLAG_CPU_PRE_DMA 0x0100 18577c478bd9Sstevel@tonic-gate #define SBD_FLAG_CPU_POST_DMA 0x0200 18587c478bd9Sstevel@tonic-gate 18597c478bd9Sstevel@tonic-gate #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 18607c478bd9Sstevel@tonic-gate #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 18617c478bd9Sstevel@tonic-gate #define SBD_FLAG_DONT_GEN_CRC 0x8000 18627c478bd9Sstevel@tonic-gate 18637c478bd9Sstevel@tonic-gate /* 18647c478bd9Sstevel@tonic-gate * Hardware-defined Receive Buffer Descriptor 18657c478bd9Sstevel@tonic-gate */ 18667c478bd9Sstevel@tonic-gate typedef struct { 18677c478bd9Sstevel@tonic-gate uint64_t host_buf_addr; 18687c478bd9Sstevel@tonic-gate #ifdef _BIG_ENDIAN 18697c478bd9Sstevel@tonic-gate uint16_t index; 18707c478bd9Sstevel@tonic-gate uint16_t len; 18717c478bd9Sstevel@tonic-gate uint16_t type; 18727c478bd9Sstevel@tonic-gate uint16_t flags; 18737c478bd9Sstevel@tonic-gate uint16_t ip_cksum; 18747c478bd9Sstevel@tonic-gate uint16_t tcp_udp_cksum; 18757c478bd9Sstevel@tonic-gate uint16_t error_flag; 18767c478bd9Sstevel@tonic-gate uint16_t vlan_tci; 18777c478bd9Sstevel@tonic-gate uint32_t reserved; 18787c478bd9Sstevel@tonic-gate uint32_t opaque; 18797c478bd9Sstevel@tonic-gate #else 18807c478bd9Sstevel@tonic-gate uint16_t flags; 18817c478bd9Sstevel@tonic-gate uint16_t type; 18827c478bd9Sstevel@tonic-gate uint16_t len; 18837c478bd9Sstevel@tonic-gate uint16_t index; 18847c478bd9Sstevel@tonic-gate uint16_t vlan_tci; 18857c478bd9Sstevel@tonic-gate uint16_t error_flag; 18867c478bd9Sstevel@tonic-gate uint16_t tcp_udp_cksum; 18877c478bd9Sstevel@tonic-gate uint16_t ip_cksum; 18887c478bd9Sstevel@tonic-gate uint32_t opaque; 18897c478bd9Sstevel@tonic-gate uint32_t reserved; 18907c478bd9Sstevel@tonic-gate #endif /* _BIG_ENDIAN */ 18917c478bd9Sstevel@tonic-gate } bge_rbd_t; 18927c478bd9Sstevel@tonic-gate 18937c478bd9Sstevel@tonic-gate #define RBD_FLAG_STD_RING 0x0000 18947c478bd9Sstevel@tonic-gate #define RBD_FLAG_PACKET_END 0x0004 18957c478bd9Sstevel@tonic-gate 18967c478bd9Sstevel@tonic-gate #define RBD_FLAG_JUMBO_RING 0x0020 18977c478bd9Sstevel@tonic-gate #define RBD_FLAG_VLAN_TAG 0x0040 18987c478bd9Sstevel@tonic-gate 18997c478bd9Sstevel@tonic-gate #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 19007c478bd9Sstevel@tonic-gate #define RBD_FLAG_MINI_RING 0x0800 19017c478bd9Sstevel@tonic-gate #define RBD_FLAG_IP_CHECKSUM 0x1000 19027c478bd9Sstevel@tonic-gate #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 19037c478bd9Sstevel@tonic-gate #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 19047c478bd9Sstevel@tonic-gate 19057c478bd9Sstevel@tonic-gate #define RBD_FLAG_DEFAULT 0x0000 19067c478bd9Sstevel@tonic-gate 19077c478bd9Sstevel@tonic-gate #define RBD_ERROR_BAD_CRC 0x00010000 19087c478bd9Sstevel@tonic-gate #define RBD_ERROR_COLL_DETECT 0x00020000 19097c478bd9Sstevel@tonic-gate #define RBD_ERROR_LINK_LOST 0x00040000 19107c478bd9Sstevel@tonic-gate #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 19117c478bd9Sstevel@tonic-gate #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 19127c478bd9Sstevel@tonic-gate #define RBD_ERROR_MAC_ABORT 0x00200000 19137c478bd9Sstevel@tonic-gate #define RBD_ERROR_LEN_LESS_64 0x00400000 19147c478bd9Sstevel@tonic-gate #define RBD_ERROR_TRUNC_NO_RES 0x00800000 19157c478bd9Sstevel@tonic-gate #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 19167c478bd9Sstevel@tonic-gate 19177c478bd9Sstevel@tonic-gate /* 19188eb6c4f9Sly * Hardware-defined Status Block,Size of status block 19198eb6c4f9Sly * is actually 0x50 bytes.Use 0x80 bytes for cache line 19208eb6c4f9Sly * alignment.For BCM5705/5788/5721/5751/5752/5714 19218eb6c4f9Sly * and 5715,there is only 1 recv and send ring index,but 19228eb6c4f9Sly * driver defined 16 indexs here,please pay attention only 19238eb6c4f9Sly * one ring is enabled in these chipsets. 19247c478bd9Sstevel@tonic-gate */ 19257c478bd9Sstevel@tonic-gate typedef struct { 19267c478bd9Sstevel@tonic-gate uint64_t flags_n_tag; 19277c478bd9Sstevel@tonic-gate uint16_t buff_cons_index[4]; 19287c478bd9Sstevel@tonic-gate struct { 19297c478bd9Sstevel@tonic-gate #ifdef _BIG_ENDIAN 19307c478bd9Sstevel@tonic-gate uint16_t send_cons_index; 19317c478bd9Sstevel@tonic-gate uint16_t recv_prod_index; 19327c478bd9Sstevel@tonic-gate #else 19337c478bd9Sstevel@tonic-gate uint16_t recv_prod_index; 19347c478bd9Sstevel@tonic-gate uint16_t send_cons_index; 19357c478bd9Sstevel@tonic-gate #endif /* _BIG_ENDIAN */ 19367c478bd9Sstevel@tonic-gate } index[16]; 19377c478bd9Sstevel@tonic-gate } bge_status_t; 19387c478bd9Sstevel@tonic-gate 19397c478bd9Sstevel@tonic-gate /* 19407c478bd9Sstevel@tonic-gate * Hardware-defined Receive BD Rule 19417c478bd9Sstevel@tonic-gate */ 19427c478bd9Sstevel@tonic-gate typedef struct { 19437c478bd9Sstevel@tonic-gate uint32_t control; 19447c478bd9Sstevel@tonic-gate uint32_t mask_value; 19457c478bd9Sstevel@tonic-gate } bge_recv_rule_t; 19467c478bd9Sstevel@tonic-gate 1947da14cebeSEric Cheng /* 1948da14cebeSEric Cheng * This describes which sub-rule slots are used by a particular rule. 1949da14cebeSEric Cheng */ 1950da14cebeSEric Cheng typedef struct { 1951da14cebeSEric Cheng int start; 1952da14cebeSEric Cheng int count; 1953da14cebeSEric Cheng } bge_rule_info_t; 1954da14cebeSEric Cheng 19557c478bd9Sstevel@tonic-gate /* 19567c478bd9Sstevel@tonic-gate * Indexes into the <buff_cons_index> array 19577c478bd9Sstevel@tonic-gate */ 19587c478bd9Sstevel@tonic-gate #ifdef _BIG_ENDIAN 19597c478bd9Sstevel@tonic-gate #define STATUS_STD_BUFF_CONS_INDEX 0 19607c478bd9Sstevel@tonic-gate #define STATUS_JUMBO_BUFF_CONS_INDEX 1 19617c478bd9Sstevel@tonic-gate #define STATUS_MINI_BUFF_CONS_INDEX 3 19627c478bd9Sstevel@tonic-gate #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 19637c478bd9Sstevel@tonic-gate #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 19647c478bd9Sstevel@tonic-gate #else 19657c478bd9Sstevel@tonic-gate #define STATUS_STD_BUFF_CONS_INDEX 3 19667c478bd9Sstevel@tonic-gate #define STATUS_JUMBO_BUFF_CONS_INDEX 2 19677c478bd9Sstevel@tonic-gate #define STATUS_MINI_BUFF_CONS_INDEX 0 19687c478bd9Sstevel@tonic-gate #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 19697c478bd9Sstevel@tonic-gate #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 19707c478bd9Sstevel@tonic-gate #endif /* _BIG_ENDIAN */ 19717c478bd9Sstevel@tonic-gate 19727c478bd9Sstevel@tonic-gate /* 19737c478bd9Sstevel@tonic-gate * Bits in the <flags_n_tag> word 19747c478bd9Sstevel@tonic-gate */ 19757c478bd9Sstevel@tonic-gate #define STATUS_FLAG_UPDATED 0x0000000100000000ull 19767c478bd9Sstevel@tonic-gate #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 19777c478bd9Sstevel@tonic-gate #define STATUS_FLAG_ERROR 0x0000000400000000ull 19787c478bd9Sstevel@tonic-gate #define STATUS_TAG_MASK 0x00000000000000FFull 19797c478bd9Sstevel@tonic-gate 19807c478bd9Sstevel@tonic-gate /* 19817c478bd9Sstevel@tonic-gate * The tag from the status block is fed back to Interrupt Mailbox 0 19827c478bd9Sstevel@tonic-gate * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 19837c478bd9Sstevel@tonic-gate * lets the chip know what updates have been processed, so it can 19847c478bd9Sstevel@tonic-gate * reassert its interrupt if more updates have occurred since. 19857c478bd9Sstevel@tonic-gate * 19867c478bd9Sstevel@tonic-gate * These macros extract the tag from the <flags_n_tag> word, shift 19877c478bd9Sstevel@tonic-gate * it to the proper position in the Mailbox register, and provide 19887c478bd9Sstevel@tonic-gate * the complete values to write to INTERRUPT_MBOX_0_REG to disable 19897c478bd9Sstevel@tonic-gate * or enable interrupts 19907c478bd9Sstevel@tonic-gate */ 19917c478bd9Sstevel@tonic-gate #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 19927c478bd9Sstevel@tonic-gate #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 19937c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 19947c478bd9Sstevel@tonic-gate #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 19957c478bd9Sstevel@tonic-gate 19967c478bd9Sstevel@tonic-gate /* 19977c478bd9Sstevel@tonic-gate * Hardware-defined Statistics Block Offsets 19987c478bd9Sstevel@tonic-gate * 19997c478bd9Sstevel@tonic-gate * These are given in the manual as addresses in NIC memory, starting 20007c478bd9Sstevel@tonic-gate * from the NIC statistics area base address of 0x300; but here we 20017c478bd9Sstevel@tonic-gate * convert them into indexes into an array of (uint64_t)s, so we can 20027c478bd9Sstevel@tonic-gate * use them directly for accessing the copy of the statistics block 20037c478bd9Sstevel@tonic-gate * that the chip DMAs into main memory ... 20047c478bd9Sstevel@tonic-gate */ 20057c478bd9Sstevel@tonic-gate 20067c478bd9Sstevel@tonic-gate #define KS_BASE 0x300 20077c478bd9Sstevel@tonic-gate #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 20087c478bd9Sstevel@tonic-gate 20097c478bd9Sstevel@tonic-gate typedef enum { 20107c478bd9Sstevel@tonic-gate KS_ifHCInOctets = KS_ADDR(0x400), 20117c478bd9Sstevel@tonic-gate KS_etherStatsFragments = KS_ADDR(0x410), 20127c478bd9Sstevel@tonic-gate KS_ifHCInUcastPkts, 20137c478bd9Sstevel@tonic-gate KS_ifHCInMulticastPkts, 20147c478bd9Sstevel@tonic-gate KS_ifHCInBroadcastPkts, 20157c478bd9Sstevel@tonic-gate KS_dot3StatsFCSErrors, 20167c478bd9Sstevel@tonic-gate KS_dot3StatsAlignmentErrors, 20177c478bd9Sstevel@tonic-gate KS_xonPauseFramesReceived, 20187c478bd9Sstevel@tonic-gate KS_xoffPauseFramesReceived, 20197c478bd9Sstevel@tonic-gate KS_macControlFramesReceived, 20207c478bd9Sstevel@tonic-gate KS_xoffStateEntered, 20217c478bd9Sstevel@tonic-gate KS_dot3StatsFrameTooLongs, 20227c478bd9Sstevel@tonic-gate KS_etherStatsJabbers, 20237c478bd9Sstevel@tonic-gate KS_etherStatsUndersizePkts, 20247c478bd9Sstevel@tonic-gate KS_inRangeLengthError, 20257c478bd9Sstevel@tonic-gate KS_outRangeLengthError, 20267c478bd9Sstevel@tonic-gate KS_etherStatsPkts64Octets, 20277c478bd9Sstevel@tonic-gate KS_etherStatsPkts65to127Octets, 20287c478bd9Sstevel@tonic-gate KS_etherStatsPkts128to255Octets, 20297c478bd9Sstevel@tonic-gate KS_etherStatsPkts256to511Octets, 20307c478bd9Sstevel@tonic-gate KS_etherStatsPkts512to1023Octets, 20317c478bd9Sstevel@tonic-gate KS_etherStatsPkts1024to1518Octets, 20327c478bd9Sstevel@tonic-gate KS_etherStatsPkts1519to2047Octets, 20337c478bd9Sstevel@tonic-gate KS_etherStatsPkts2048to4095Octets, 20347c478bd9Sstevel@tonic-gate KS_etherStatsPkts4096to8191Octets, 20357c478bd9Sstevel@tonic-gate KS_etherStatsPkts8192to9022Octets, 20367c478bd9Sstevel@tonic-gate 20377c478bd9Sstevel@tonic-gate KS_ifHCOutOctets = KS_ADDR(0x600), 20387c478bd9Sstevel@tonic-gate KS_etherStatsCollisions = KS_ADDR(0x610), 20397c478bd9Sstevel@tonic-gate KS_outXonSent, 20407c478bd9Sstevel@tonic-gate KS_outXoffSent, 20417c478bd9Sstevel@tonic-gate KS_flowControlDone, 20427c478bd9Sstevel@tonic-gate KS_dot3StatsInternalMacTransmitErrors, 20437c478bd9Sstevel@tonic-gate KS_dot3StatsSingleCollisionFrames, 20447c478bd9Sstevel@tonic-gate KS_dot3StatsMultipleCollisionFrames, 20457c478bd9Sstevel@tonic-gate KS_dot3StatsDeferredTransmissions, 20467c478bd9Sstevel@tonic-gate KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 20477c478bd9Sstevel@tonic-gate KS_dot3StatsLateCollisions, 20487c478bd9Sstevel@tonic-gate KS_dot3Collided2Times, 20497c478bd9Sstevel@tonic-gate KS_dot3Collided3Times, 20507c478bd9Sstevel@tonic-gate KS_dot3Collided4Times, 20517c478bd9Sstevel@tonic-gate KS_dot3Collided5Times, 20527c478bd9Sstevel@tonic-gate KS_dot3Collided6Times, 20537c478bd9Sstevel@tonic-gate KS_dot3Collided7Times, 20547c478bd9Sstevel@tonic-gate KS_dot3Collided8Times, 20557c478bd9Sstevel@tonic-gate KS_dot3Collided9Times, 20567c478bd9Sstevel@tonic-gate KS_dot3Collided10Times, 20577c478bd9Sstevel@tonic-gate KS_dot3Collided11Times, 20587c478bd9Sstevel@tonic-gate KS_dot3Collided12Times, 20597c478bd9Sstevel@tonic-gate KS_dot3Collided13Times, 20607c478bd9Sstevel@tonic-gate KS_dot3Collided14Times, 20617c478bd9Sstevel@tonic-gate KS_dot3Collided15Times, 20627c478bd9Sstevel@tonic-gate KS_ifHCOutUcastPkts, 20637c478bd9Sstevel@tonic-gate KS_ifHCOutMulticastPkts, 20647c478bd9Sstevel@tonic-gate KS_ifHCOutBroadcastPkts, 20657c478bd9Sstevel@tonic-gate KS_dot3StatsCarrierSenseErrors, 20667c478bd9Sstevel@tonic-gate KS_ifOutDiscards, 20677c478bd9Sstevel@tonic-gate KS_ifOutErrors, 20687c478bd9Sstevel@tonic-gate 20697c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 20707c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_2, 20717c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_3, 20727c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_4, 20737c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_5, 20747c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_6, 20757c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_7, 20767c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_8, 20777c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_9, 20787c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_10, 20797c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_11, 20807c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_12, 20817c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_13, 20827c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_14, 20837c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_15, 20847c478bd9Sstevel@tonic-gate KS_COSIfHCInPkts_16, 20857c478bd9Sstevel@tonic-gate KS_COSFramesDroppedDueToFilters, 20867c478bd9Sstevel@tonic-gate KS_nicDmaWriteQueueFull, 20877c478bd9Sstevel@tonic-gate KS_nicDmaWriteHighPriQueueFull, 20887c478bd9Sstevel@tonic-gate KS_nicNoMoreRxBDs, 20897c478bd9Sstevel@tonic-gate KS_ifInDiscards, 20907c478bd9Sstevel@tonic-gate KS_ifInErrors, 20917c478bd9Sstevel@tonic-gate KS_nicRecvThresholdHit, 20927c478bd9Sstevel@tonic-gate 20937c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 20947c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_2, 20957c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_3, 20967c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_4, 20977c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_5, 20987c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_6, 20997c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_7, 21007c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_8, 21017c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_9, 21027c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_10, 21037c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_11, 21047c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_12, 21057c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_13, 21067c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_14, 21077c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_15, 21087c478bd9Sstevel@tonic-gate KS_COSIfHCOutPkts_16, 21097c478bd9Sstevel@tonic-gate KS_nicDmaReadQueueFull, 21107c478bd9Sstevel@tonic-gate KS_nicDmaReadHighPriQueueFull, 21117c478bd9Sstevel@tonic-gate KS_nicSendDataCompQueueFull, 21127c478bd9Sstevel@tonic-gate KS_nicRingSetSendProdIndex, 21137c478bd9Sstevel@tonic-gate KS_nicRingStatusUpdate, 21147c478bd9Sstevel@tonic-gate KS_nicInterrupts, 21157c478bd9Sstevel@tonic-gate KS_nicAvoidedInterrupts, 21167c478bd9Sstevel@tonic-gate KS_nicSendThresholdHit, 21177c478bd9Sstevel@tonic-gate 21187c478bd9Sstevel@tonic-gate KS_STATS_SIZE = KS_ADDR(0xb00) 21197c478bd9Sstevel@tonic-gate } bge_stats_offset_t; 21207c478bd9Sstevel@tonic-gate 21217c478bd9Sstevel@tonic-gate /* 21227c478bd9Sstevel@tonic-gate * Hardware-defined Statistics Block 21237c478bd9Sstevel@tonic-gate * 21247c478bd9Sstevel@tonic-gate * Another view of the statistic block, as a array and a structure ... 21257c478bd9Sstevel@tonic-gate */ 21267c478bd9Sstevel@tonic-gate 21277c478bd9Sstevel@tonic-gate typedef union { 21287c478bd9Sstevel@tonic-gate uint64_t a[KS_STATS_SIZE]; 21297c478bd9Sstevel@tonic-gate struct { 21307c478bd9Sstevel@tonic-gate uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 21317c478bd9Sstevel@tonic-gate 21327c478bd9Sstevel@tonic-gate uint64_t ifHCInOctets; /* 0x0400 */ 21337c478bd9Sstevel@tonic-gate uint64_t spare2[1]; 21347c478bd9Sstevel@tonic-gate uint64_t etherStatsFragments; 21357c478bd9Sstevel@tonic-gate uint64_t ifHCInUcastPkts; 21367c478bd9Sstevel@tonic-gate uint64_t ifHCInMulticastPkts; 21377c478bd9Sstevel@tonic-gate uint64_t ifHCInBroadcastPkts; 21387c478bd9Sstevel@tonic-gate uint64_t dot3StatsFCSErrors; 21397c478bd9Sstevel@tonic-gate uint64_t dot3StatsAlignmentErrors; 21407c478bd9Sstevel@tonic-gate uint64_t xonPauseFramesReceived; 21417c478bd9Sstevel@tonic-gate uint64_t xoffPauseFramesReceived; 21427c478bd9Sstevel@tonic-gate uint64_t macControlFramesReceived; 21437c478bd9Sstevel@tonic-gate uint64_t xoffStateEntered; 21447c478bd9Sstevel@tonic-gate uint64_t dot3StatsFrameTooLongs; 21457c478bd9Sstevel@tonic-gate uint64_t etherStatsJabbers; 21467c478bd9Sstevel@tonic-gate uint64_t etherStatsUndersizePkts; 21477c478bd9Sstevel@tonic-gate uint64_t inRangeLengthError; 21487c478bd9Sstevel@tonic-gate uint64_t outRangeLengthError; 21497c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts64Octets; 21507c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts65to127Octets; 21517c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts128to255Octets; 21527c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts256to511Octets; 21537c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts512to1023Octets; 21547c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts1024to1518Octets; 21557c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts1519to2047Octets; 21567c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts2048to4095Octets; 21577c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts4096to8191Octets; 21587c478bd9Sstevel@tonic-gate uint64_t etherStatsPkts8192to9022Octets; 21597c478bd9Sstevel@tonic-gate uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 21607c478bd9Sstevel@tonic-gate 21617c478bd9Sstevel@tonic-gate uint64_t ifHCOutOctets; /* 0x0600 */ 21627c478bd9Sstevel@tonic-gate uint64_t spare4[1]; 21637c478bd9Sstevel@tonic-gate uint64_t etherStatsCollisions; 21647c478bd9Sstevel@tonic-gate uint64_t outXonSent; 21657c478bd9Sstevel@tonic-gate uint64_t outXoffSent; 21667c478bd9Sstevel@tonic-gate uint64_t flowControlDone; 21677c478bd9Sstevel@tonic-gate uint64_t dot3StatsInternalMacTransmitErrors; 21687c478bd9Sstevel@tonic-gate uint64_t dot3StatsSingleCollisionFrames; 21697c478bd9Sstevel@tonic-gate uint64_t dot3StatsMultipleCollisionFrames; 21707c478bd9Sstevel@tonic-gate uint64_t dot3StatsDeferredTransmissions; 21717c478bd9Sstevel@tonic-gate uint64_t spare5[1]; 21727c478bd9Sstevel@tonic-gate uint64_t dot3StatsExcessiveCollisions; 21737c478bd9Sstevel@tonic-gate uint64_t dot3StatsLateCollisions; 21747c478bd9Sstevel@tonic-gate uint64_t dot3Collided2Times; 21757c478bd9Sstevel@tonic-gate uint64_t dot3Collided3Times; 21767c478bd9Sstevel@tonic-gate uint64_t dot3Collided4Times; 21777c478bd9Sstevel@tonic-gate uint64_t dot3Collided5Times; 21787c478bd9Sstevel@tonic-gate uint64_t dot3Collided6Times; 21797c478bd9Sstevel@tonic-gate uint64_t dot3Collided7Times; 21807c478bd9Sstevel@tonic-gate uint64_t dot3Collided8Times; 21817c478bd9Sstevel@tonic-gate uint64_t dot3Collided9Times; 21827c478bd9Sstevel@tonic-gate uint64_t dot3Collided10Times; 21837c478bd9Sstevel@tonic-gate uint64_t dot3Collided11Times; 21847c478bd9Sstevel@tonic-gate uint64_t dot3Collided12Times; 21857c478bd9Sstevel@tonic-gate uint64_t dot3Collided13Times; 21867c478bd9Sstevel@tonic-gate uint64_t dot3Collided14Times; 21877c478bd9Sstevel@tonic-gate uint64_t dot3Collided15Times; 21887c478bd9Sstevel@tonic-gate uint64_t ifHCOutUcastPkts; 21897c478bd9Sstevel@tonic-gate uint64_t ifHCOutMulticastPkts; 21907c478bd9Sstevel@tonic-gate uint64_t ifHCOutBroadcastPkts; 21917c478bd9Sstevel@tonic-gate uint64_t dot3StatsCarrierSenseErrors; 21927c478bd9Sstevel@tonic-gate uint64_t ifOutDiscards; 21937c478bd9Sstevel@tonic-gate uint64_t ifOutErrors; 21947c478bd9Sstevel@tonic-gate uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 21957c478bd9Sstevel@tonic-gate 21967c478bd9Sstevel@tonic-gate uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 21977c478bd9Sstevel@tonic-gate uint64_t COSFramesDroppedDueToFilters; 21987c478bd9Sstevel@tonic-gate uint64_t nicDmaWriteQueueFull; 21997c478bd9Sstevel@tonic-gate uint64_t nicDmaWriteHighPriQueueFull; 22007c478bd9Sstevel@tonic-gate uint64_t nicNoMoreRxBDs; 22017c478bd9Sstevel@tonic-gate uint64_t ifInDiscards; 22027c478bd9Sstevel@tonic-gate uint64_t ifInErrors; 22037c478bd9Sstevel@tonic-gate uint64_t nicRecvThresholdHit; 22047c478bd9Sstevel@tonic-gate uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 22057c478bd9Sstevel@tonic-gate 22067c478bd9Sstevel@tonic-gate uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 22077c478bd9Sstevel@tonic-gate uint64_t nicDmaReadQueueFull; 22087c478bd9Sstevel@tonic-gate uint64_t nicDmaReadHighPriQueueFull; 22097c478bd9Sstevel@tonic-gate uint64_t nicSendDataCompQueueFull; 22107c478bd9Sstevel@tonic-gate uint64_t nicRingSetSendProdIndex; 22117c478bd9Sstevel@tonic-gate uint64_t nicRingStatusUpdate; 22127c478bd9Sstevel@tonic-gate uint64_t nicInterrupts; 22137c478bd9Sstevel@tonic-gate uint64_t nicAvoidedInterrupts; 22147c478bd9Sstevel@tonic-gate uint64_t nicSendThresholdHit; 22157c478bd9Sstevel@tonic-gate uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 22167c478bd9Sstevel@tonic-gate } s; 22177c478bd9Sstevel@tonic-gate } bge_statistics_t; 22187c478bd9Sstevel@tonic-gate 22198eb6c4f9Sly #define KS_STAT_REG_SIZE (0x1B) 22208eb6c4f9Sly #define KS_STAT_REG_BASE (0x800) 22218eb6c4f9Sly 22228eb6c4f9Sly typedef struct { 22238eb6c4f9Sly uint32_t ifHCOutOctets; 22248eb6c4f9Sly uint32_t etherStatsCollisions; 22258eb6c4f9Sly uint32_t outXonSent; 22268eb6c4f9Sly uint32_t outXoffSent; 22278eb6c4f9Sly uint32_t dot3StatsInternalMacTransmitErrors; 22288eb6c4f9Sly uint32_t dot3StatsSingleCollisionFrames; 22298eb6c4f9Sly uint32_t dot3StatsMultipleCollisionFrames; 22308eb6c4f9Sly uint32_t dot3StatsDeferredTransmissions; 22318eb6c4f9Sly uint32_t dot3StatsExcessiveCollisions; 22328eb6c4f9Sly uint32_t dot3StatsLateCollisions; 22338eb6c4f9Sly uint32_t ifHCOutUcastPkts; 22348eb6c4f9Sly uint32_t ifHCOutMulticastPkts; 22358eb6c4f9Sly uint32_t ifHCOutBroadcastPkts; 22368eb6c4f9Sly uint32_t ifHCInOctets; 22378eb6c4f9Sly uint32_t etherStatsFragments; 22388eb6c4f9Sly uint32_t ifHCInUcastPkts; 22398eb6c4f9Sly uint32_t ifHCInMulticastPkts; 22408eb6c4f9Sly uint32_t ifHCInBroadcastPkts; 22418eb6c4f9Sly uint32_t dot3StatsFCSErrors; 22428eb6c4f9Sly uint32_t dot3StatsAlignmentErrors; 22438eb6c4f9Sly uint32_t xonPauseFramesReceived; 22448eb6c4f9Sly uint32_t xoffPauseFramesReceived; 22458eb6c4f9Sly uint32_t macControlFramesReceived; 22468eb6c4f9Sly uint32_t xoffStateEntered; 22478eb6c4f9Sly uint32_t dot3StatsFrameTooLongs; 22488eb6c4f9Sly uint32_t etherStatsJabbers; 22498eb6c4f9Sly uint32_t etherStatsUndersizePkts; 22508eb6c4f9Sly } bge_statistics_reg_t; 22517c478bd9Sstevel@tonic-gate 225267f02347Srandyf 225367f02347Srandyf #ifdef BGE_IPMI_ASF 225467f02347Srandyf 225567f02347Srandyf /* 225667f02347Srandyf * Device internal memory entries 225767f02347Srandyf */ 225867f02347Srandyf 225967f02347Srandyf #define BGE_FIRMWARE_MAILBOX 0x0b50 226067f02347Srandyf #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 226167f02347Srandyf #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 226267f02347Srandyf 226367f02347Srandyf 226467f02347Srandyf #define BGE_NIC_DATA_SIG_ADDR 0x0b54 226567f02347Srandyf #define BGE_NIC_DATA_SIG 0x4b657654 226667f02347Srandyf 226767f02347Srandyf 226867f02347Srandyf #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 226967f02347Srandyf 227067f02347Srandyf #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 227167f02347Srandyf #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 227267f02347Srandyf #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 227367f02347Srandyf #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 227467f02347Srandyf #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 227567f02347Srandyf 227667f02347Srandyf #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 227767f02347Srandyf #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 227867f02347Srandyf #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 227967f02347Srandyf #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 228067f02347Srandyf 228167f02347Srandyf #define BGE_NIC_CFG_ENABLE_WOL 0x000040 228267f02347Srandyf #define BGE_NIC_CFG_ENABLE_ASF 0x000080 228367f02347Srandyf #define BGE_NIC_CFG_EEPROM_WP 0x000100 228467f02347Srandyf #define BGE_NIC_CFG_POWER_SAVING 0x000200 228567f02347Srandyf #define BGE_NIC_CFG_SWAP_PORT 0x000800 228667f02347Srandyf #define BGE_NIC_CFG_MINI_PCI 0x001000 228767f02347Srandyf #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 228867f02347Srandyf #define BGE_NIC_CFG_5753_12x12 0x100000 228967f02347Srandyf 229067f02347Srandyf 229167f02347Srandyf #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 229267f02347Srandyf 229367f02347Srandyf 229467f02347Srandyf #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 229567f02347Srandyf #define BGE_NIC_PHY_ID1_MASK 0xffff0000 229667f02347Srandyf #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 229767f02347Srandyf 229867f02347Srandyf 229967f02347Srandyf #define BGE_CMD_MAILBOX 0x0b78 230067f02347Srandyf #define BGE_CMD_NICDRV_ALIVE 0x00000001 230167f02347Srandyf #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 230267f02347Srandyf #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 230367f02347Srandyf #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 230467f02347Srandyf 230567f02347Srandyf 230667f02347Srandyf #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 230767f02347Srandyf #define BGE_CMD_DATA_MAILBOX 0x0b80 230867f02347Srandyf #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 230967f02347Srandyf 231067f02347Srandyf #define BGE_DRV_STATE_MAILBOX 0x0c04 231167f02347Srandyf #define BGE_DRV_STATE_START 0x00000001 231267f02347Srandyf #define BGE_DRV_STATE_START_DONE 0x80000001 231367f02347Srandyf #define BGE_DRV_STATE_UNLOAD 0x00000002 231467f02347Srandyf #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 231567f02347Srandyf #define BGE_DRV_STATE_WOL 0x00000003 231667f02347Srandyf #define BGE_DRV_STATE_SUSPEND 0x00000004 231767f02347Srandyf 231867f02347Srandyf 231967f02347Srandyf #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 232067f02347Srandyf #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 232167f02347Srandyf #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 232267f02347Srandyf 232367f02347Srandyf 232467f02347Srandyf #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 232567f02347Srandyf #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 232667f02347Srandyf 232767f02347Srandyf 232867f02347Srandyf /* 232967f02347Srandyf * RX-RISC event register 233067f02347Srandyf */ 233167f02347Srandyf #define RX_RISC_EVENT_REG 0x6810 233267f02347Srandyf #define RRER_ASF_EVENT 0x4000 233367f02347Srandyf 233467f02347Srandyf #endif /* BGE_IPMI_ASF */ 233567f02347Srandyf 2336087a28d1SDavid Gwynne /* APE registers. Accessible through BAR1 */ 2337087a28d1SDavid Gwynne #define BGE_APE_GPIO_MSG 0x0008 2338087a28d1SDavid Gwynne #define BGE_APE_GPIO_MSG_SHIFT 4 2339087a28d1SDavid Gwynne #define BGE_APE_EVENT 0x000c 2340087a28d1SDavid Gwynne #define APE_EVENT_1 0x00000001 2341087a28d1SDavid Gwynne #define BGE_APE_LOCK_REQ 0x002c 2342087a28d1SDavid Gwynne #define APE_LOCK_REQ_DRIVER 0x00001000 2343087a28d1SDavid Gwynne #define BGE_APE_LOCK_GRANT 0x004c 2344087a28d1SDavid Gwynne #define APE_LOCK_GRANT_DRIVER 0x00001000 2345087a28d1SDavid Gwynne #define BGE_APE_STICKY_TMR 0x00b0 2346087a28d1SDavid Gwynne 2347087a28d1SDavid Gwynne /* APE shared memory. Accessible through BAR1 */ 2348087a28d1SDavid Gwynne #define BGE_APE_SHMEM_BASE 0x4000 2349087a28d1SDavid Gwynne #define BGE_APE_SEG_SIG 0x4000 2350087a28d1SDavid Gwynne #define APE_SEG_SIG_MAGIC 0x41504521 2351087a28d1SDavid Gwynne #define BGE_APE_FW_STATUS 0x400c 2352087a28d1SDavid Gwynne #define APE_FW_STATUS_READY 0x00000100 2353087a28d1SDavid Gwynne #define BGE_APE_FW_FEATURES 0x4010 2354087a28d1SDavid Gwynne #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2355087a28d1SDavid Gwynne #define BGE_APE_FW_VERSION 0x4018 2356087a28d1SDavid Gwynne #define APE_FW_VERSION_MAJMSK 0xff000000 2357087a28d1SDavid Gwynne #define APE_FW_VERSION_MAJSFT 24 2358087a28d1SDavid Gwynne #define APE_FW_VERSION_MINMSK 0x00ff0000 2359087a28d1SDavid Gwynne #define APE_FW_VERSION_MINSFT 16 2360087a28d1SDavid Gwynne #define APE_FW_VERSION_REVMSK 0x0000ff00 2361087a28d1SDavid Gwynne #define APE_FW_VERSION_REVSFT 8 2362087a28d1SDavid Gwynne #define APE_FW_VERSION_BLDMSK 0x000000ff 2363087a28d1SDavid Gwynne #define BGE_APE_SEG_MSG_BUF_OFF 0x401c 2364087a28d1SDavid Gwynne #define BGE_APE_SEG_MSG_BUF_LEN 0x4020 2365087a28d1SDavid Gwynne #define BGE_APE_HOST_SEG_SIG 0x4200 2366087a28d1SDavid Gwynne #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2367087a28d1SDavid Gwynne #define BGE_APE_HOST_SEG_LEN 0x4204 2368087a28d1SDavid Gwynne #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2369087a28d1SDavid Gwynne #define BGE_APE_HOST_INIT_COUNT 0x4208 2370087a28d1SDavid Gwynne #define BGE_APE_HOST_DRIVER_ID 0x420c 2371087a28d1SDavid Gwynne #define APE_HOST_DRIVER_ID_SOLARIS 0xf4000000 2372087a28d1SDavid Gwynne #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2373087a28d1SDavid Gwynne (APE_HOST_DRIVER_ID_SOLARIS | (maj & 0xff) << 16 | (min & 0xff) << 8) 2374087a28d1SDavid Gwynne #define BGE_APE_HOST_BEHAVIOR 0x4210 2375087a28d1SDavid Gwynne #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2376087a28d1SDavid Gwynne #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2377087a28d1SDavid Gwynne #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2378087a28d1SDavid Gwynne #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2379087a28d1SDavid Gwynne #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2380087a28d1SDavid Gwynne #define BGE_APE_HOST_DRVR_STATE 0x421c 2381087a28d1SDavid Gwynne #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2382087a28d1SDavid Gwynne #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2383087a28d1SDavid Gwynne #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2384087a28d1SDavid Gwynne #define BGE_APE_HOST_WOL_SPEED 0x4224 2385087a28d1SDavid Gwynne #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2386087a28d1SDavid Gwynne 2387087a28d1SDavid Gwynne #define BGE_APE_EVENT_STATUS 0x4300 2388087a28d1SDavid Gwynne 2389087a28d1SDavid Gwynne #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2390087a28d1SDavid Gwynne #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2391087a28d1SDavid Gwynne #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2392087a28d1SDavid Gwynne #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2393087a28d1SDavid Gwynne #define APE_EVENT_STATUS_STATE_START 0x00010000 2394087a28d1SDavid Gwynne #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2395087a28d1SDavid Gwynne #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2396087a28d1SDavid Gwynne #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2397087a28d1SDavid Gwynne #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2398087a28d1SDavid Gwynne 2399087a28d1SDavid Gwynne #define BGE_APE_PER_LOCK_REQ 0x8400 2400087a28d1SDavid Gwynne #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2401087a28d1SDavid Gwynne #define BGE_APE_PER_LOCK_GRANT 0x8420 2402087a28d1SDavid Gwynne #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2403087a28d1SDavid Gwynne 2404087a28d1SDavid Gwynne /* APE convenience enumerations. */ 2405087a28d1SDavid Gwynne #define BGE_APE_LOCK_PHY0 0 2406087a28d1SDavid Gwynne #define BGE_APE_LOCK_GRC 1 2407087a28d1SDavid Gwynne #define BGE_APE_LOCK_PHY1 2 2408087a28d1SDavid Gwynne #define BGE_APE_LOCK_PHY2 3 2409087a28d1SDavid Gwynne #define BGE_APE_LOCK_MEM 4 2410087a28d1SDavid Gwynne #define BGE_APE_LOCK_PHY3 5 2411087a28d1SDavid Gwynne #define BGE_APE_LOCK_GPIO 7 2412087a28d1SDavid Gwynne 24137c478bd9Sstevel@tonic-gate #ifdef __cplusplus 24147c478bd9Sstevel@tonic-gate } 24157c478bd9Sstevel@tonic-gate #endif 24167c478bd9Sstevel@tonic-gate 2417542d98abSzh #endif /* _BGE_HW_H */ 2418