188447a05SGarrett D'Amore /* 288447a05SGarrett D'Amore * CDDL HEADER START 388447a05SGarrett D'Amore * 488447a05SGarrett D'Amore * The contents of this file are subject to the terms of the 588447a05SGarrett D'Amore * Common Development and Distribution License (the "License"). 688447a05SGarrett D'Amore * You may not use this file except in compliance with the License. 788447a05SGarrett D'Amore * 888447a05SGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 988447a05SGarrett D'Amore * or http://www.opensolaris.org/os/licensing. 1088447a05SGarrett D'Amore * See the License for the specific language governing permissions 1188447a05SGarrett D'Amore * and limitations under the License. 1288447a05SGarrett D'Amore * 1388447a05SGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each 1488447a05SGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1588447a05SGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the 1688447a05SGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying 1788447a05SGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner] 1888447a05SGarrett D'Amore * 1988447a05SGarrett D'Amore * CDDL HEADER END 2088447a05SGarrett D'Amore */ 2188447a05SGarrett D'Amore /* 22*68c47f65SGarrett D'Amore * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 2388447a05SGarrett D'Amore * Use is subject to license terms. 2488447a05SGarrett D'Amore */ 2588447a05SGarrett D'Amore 2688447a05SGarrett D'Amore #ifndef AUDIO1575_H 2788447a05SGarrett D'Amore #define AUDIO1575_H 2888447a05SGarrett D'Amore 2988447a05SGarrett D'Amore /* 3088447a05SGarrett D'Amore * Header file for the audio1575 device driver 3188447a05SGarrett D'Amore */ 3288447a05SGarrett D'Amore 3388447a05SGarrett D'Amore /* 3488447a05SGarrett D'Amore * Driver supported configuration information 3588447a05SGarrett D'Amore */ 3688447a05SGarrett D'Amore #define M1575_NAME "audio1575" 3788447a05SGarrett D'Amore #define M1575_MOD_NAME "M1575 audio driver" 3888447a05SGarrett D'Amore 3988447a05SGarrett D'Amore /* 4088447a05SGarrett D'Amore * Implementation specific header file for the audio1575 device driver. 4188447a05SGarrett D'Amore */ 4288447a05SGarrett D'Amore 4388447a05SGarrett D'Amore /* Misc. defines */ 4488447a05SGarrett D'Amore #define M1575_AUDIO_IO_SPACE (1) 4588447a05SGarrett D'Amore 4688447a05SGarrett D'Amore #define M1575_LOOP_CTR (100) 4788447a05SGarrett D'Amore 4888447a05SGarrett D'Amore /* audio direction */ 4988447a05SGarrett D'Amore #define M1575_PLAY (0) 5088447a05SGarrett D'Amore #define M1575_REC (1) 5188447a05SGarrett D'Amore 5288447a05SGarrett D'Amore /* Buffer Descriptor List defines */ 5388447a05SGarrett D'Amore #define M1575_BD_NUMS (32) 5488447a05SGarrett D'Amore #define M1575_NUM_PORTS (2) 5588447a05SGarrett D'Amore #define M1575_MOD_SIZE (16) 5688447a05SGarrett D'Amore 5788447a05SGarrett D'Amore /* kstat interrupt counter define */ 5888447a05SGarrett D'Amore #define M1575_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1)) 5988447a05SGarrett D'Amore 6088447a05SGarrett D'Amore /* PCI CFG SPACE REGISTERS for Audio (Device 29, Function 0) */ 6188447a05SGarrett D'Amore #define M1575_PCIPMR_REG 0x42 /* Power Capabilities 16 */ 6288447a05SGarrett D'Amore #define M1575_PCIPMCSR_REG 0x44 /* Power Cmd & Status 16 */ 6388447a05SGarrett D'Amore #define M1575_PCISCCR_REG 0x48 /* System Cfg Cntrl 16 */ 6488447a05SGarrett D'Amore #define M1575_PCIAPMUCR1_REG 0x54 /* Add. PMU Cntrl Reg 8 */ 6588447a05SGarrett D'Amore #define M1575_PCISCRR_REG 0x57 /* Scratch Reg 8 */ 6688447a05SGarrett D'Amore #define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 6788447a05SGarrett D'Amore #define M1575_PCIGCC_REG 0x59 /* Global Clk Control 16 */ 6888447a05SGarrett D'Amore #define M1575_PCIACD_REG 0x5C /* AC97 Codec Detect 8 */ 6988447a05SGarrett D'Amore #define M1575_PCIMISC_REG 0x58 /* Misc Reg 8 */ 7088447a05SGarrett D'Amore #define M1575_PCIGCLK_REG 0x59 /* Misc Reg 8 */ 7188447a05SGarrett D'Amore #define M1575_PCIMSICTRL_REG 0x62 /* MSI Control Reg 16 */ 7288447a05SGarrett D'Amore #define M1575_PCIMSIADDR_REG 0x64 /* MSI Address Reg 32 */ 7388447a05SGarrett D'Amore #define M1575_PCIMSIDATA_REG 0x68 /* MSI Data Reg 16 */ 7488447a05SGarrett D'Amore #define M1575_PCIMSIMASK_REG 0x6C /* MSI Data Reg 32 */ 7588447a05SGarrett D'Amore #define M1575_PCIMSIPEND_REG 0x70 /* MSI Pend Reg 32 */ 7688447a05SGarrett D'Amore 7788447a05SGarrett D'Amore /* Bit definitions for PCI AC97 Clk detect Reg */ 7888447a05SGarrett D'Amore #define M1575_PCIACD_CLKDET 0x01 7988447a05SGarrett D'Amore #define M1575_PCIMISC_INTENB 0x40 8088447a05SGarrett D'Amore #define M1575_PCIINT_LINE 0x05 8188447a05SGarrett D'Amore 8288447a05SGarrett D'Amore /* Base Line Audio I/O Memory Registers */ 8388447a05SGarrett D'Amore #define M1575_SCR_REG 0x00 /* System Control Reg 32 */ 8488447a05SGarrett D'Amore #define M1575_SSR_REG 0x04 /* System System Reg 32 */ 8588447a05SGarrett D'Amore #define M1575_DMACR_REG 0x08 /* DMA Control Reg 32 */ 8688447a05SGarrett D'Amore #define M1575_FIFOCR1_REG 0x0C /* FIFO 1 Control Reg 32 */ 8788447a05SGarrett D'Amore #define M1575_INTFCR_REG 0x10 /* Interface Ctrl Reg 32 */ 8888447a05SGarrett D'Amore #define M1575_INTRCR_REG 0x14 /* Interrupt Ctrl Reg 32 */ 8988447a05SGarrett D'Amore #define M1575_INTRSR_REG 0x18 /* Interrupt Status Reg 32 */ 9088447a05SGarrett D'Amore #define M1575_FIFOCR2_REG 0x1C /* FIFO 2 Control Reg 32 */ 9188447a05SGarrett D'Amore #define M1575_CPR_REG 0x20 /* Cmd Port Reg 32 */ 9288447a05SGarrett D'Amore #define M1575_SPR_REG 0x24 /* Status Port Reg 32 */ 9388447a05SGarrett D'Amore #define M1575_FIFOCR3_REG 0x2C /* FIFO 3 Control Reg 32 */ 9488447a05SGarrett D'Amore #define M1575_TTSR_REG 0x30 /* Tx Tag Slot Reg 32 */ 9588447a05SGarrett D'Amore #define M1575_RTSR_REG 0x34 /* Rx Tag Slot Reg 32 */ 9688447a05SGarrett D'Amore #define M1575_CSPSR_REG 0x38 /* CSP Status Reg 32 */ 9788447a05SGarrett D'Amore #define M1575_CASR_REG 0x3C /* Codec Access Sem Reg 32 */ 9888447a05SGarrett D'Amore 9988447a05SGarrett D'Amore /* PCM IN Registers */ 10088447a05SGarrett D'Amore #define M1575_PCMIBDBAR_REG 0x40 /* 32 */ 10188447a05SGarrett D'Amore #define M1575_PCMICIV_REG 0x44 /* 8 */ 10288447a05SGarrett D'Amore #define M1575_PCMILVIV_REG 0x45 /* 8 */ 10388447a05SGarrett D'Amore #define M1575_PCMISR_REG 0x46 /* 16 */ 10488447a05SGarrett D'Amore #define M1575_PCMIPICB_REG 0x48 /* 16 */ 10588447a05SGarrett D'Amore #define M1575_PCMICR_REG 0x4B /* 8 */ 10688447a05SGarrett D'Amore 10788447a05SGarrett D'Amore /* PCM OUT Registers */ 10888447a05SGarrett D'Amore #define M1575_PCMOBDBAR_REG 0x50 /* 32 */ 10988447a05SGarrett D'Amore #define M1575_PCMOCIV_REG 0x54 /* 8 */ 11088447a05SGarrett D'Amore #define M1575_PCMOLVIV_REG 0x55 /* 8 */ 11188447a05SGarrett D'Amore #define M1575_PCMOSR_REG 0x56 /* 16 */ 11288447a05SGarrett D'Amore #define M1575_PCMOPICB_REG 0x58 /* 16 */ 11388447a05SGarrett D'Amore #define M1575_PCMOCR_REG 0x5B /* 8 */ 11488447a05SGarrett D'Amore 11588447a05SGarrett D'Amore /* MIC In Registers */ 11688447a05SGarrett D'Amore #define M1575_MICIBDBAR_REG 0x60 /* 32 */ 11788447a05SGarrett D'Amore #define M1575_MICICIV_REG 0x64 /* 8 */ 11888447a05SGarrett D'Amore #define M1575_MICILVIV_REG 0x65 /* 8 */ 11988447a05SGarrett D'Amore #define M1575_MICISR_REG 0x66 /* 16 */ 12088447a05SGarrett D'Amore #define M1575_MICIPICB_REG 0x68 /* 16 */ 12188447a05SGarrett D'Amore #define M1575_MICICR_REG 0x6B /* 8 */ 12288447a05SGarrett D'Amore 12388447a05SGarrett D'Amore /* SPIDOF Registers */ 12488447a05SGarrett D'Amore #define M1575_CSPOBDBAR_REG 0x70 /* 32 */ 12588447a05SGarrett D'Amore #define M1575_CSPOCIV_REG 0x74 /* 8 */ 12688447a05SGarrett D'Amore #define M1575_CSPOLVIV_REG 0x75 /* 8 */ 12788447a05SGarrett D'Amore #define M1575_CSPOSR_REG 0x76 /* 16 */ 12888447a05SGarrett D'Amore #define M1575_CSPOPICB_REG 0x78 /* 16 */ 12988447a05SGarrett D'Amore #define M1575_CSPOCR_REG 0x7B /* 8 */ 13088447a05SGarrett D'Amore 13188447a05SGarrett D'Amore /* PCM IN2 Registers */ 13288447a05SGarrett D'Amore #define M1575_PCMI2BDBAR_REG 0xd0 /* 32 */ 13388447a05SGarrett D'Amore #define M1575_PCMI2CIV_REG 0xd4 /* 8 */ 13488447a05SGarrett D'Amore #define M1575_PCMI2LVIV_REG 0xd5 /* 8 */ 13588447a05SGarrett D'Amore #define M1575_PCMI2SR_REG 0xd6 /* 16 */ 13688447a05SGarrett D'Amore #define M1575_PCMI2PICB_REG 0xd8 /* 16 */ 13788447a05SGarrett D'Amore #define M1575_PCMI2CR_REG 0xdB /* 8 */ 13888447a05SGarrett D'Amore 13988447a05SGarrett D'Amore /* MIC2 IN2 Registers */ 14088447a05SGarrett D'Amore #define M1575_MICI2BDBAR_REG 0xe0 /* 32 */ 14188447a05SGarrett D'Amore #define M1575_MICI2CIV_REG 0xe4 /* 8 */ 14288447a05SGarrett D'Amore #define M1575_MICI2LVIV_REG 0xe5 /* 8 */ 14388447a05SGarrett D'Amore #define M1575_MICI2SR_REG 0xe6 /* 16 */ 14488447a05SGarrett D'Amore #define M1575_MICI2PICB_REG 0xe8 /* 16 */ 14588447a05SGarrett D'Amore #define M1575_MICI2CR_REG 0xeB /* 8 */ 14688447a05SGarrett D'Amore 14788447a05SGarrett D'Amore /* Bits of FIFO Control Register1 */ 14888447a05SGarrett D'Amore #define M1575_FIFOCR1_CSPORST 0x80000000 /* SPDIF Out Reset */ 14988447a05SGarrett D'Amore #define M1575_FIFOCR1_MICIRST 0x00800000 /* MIC In Reset */ 15088447a05SGarrett D'Amore #define M1575_FIFOCR1_PCMORST 0x00008000 /* PCM Out Reset */ 15188447a05SGarrett D'Amore #define M1575_FIFOCR1_PCMIRST 0x00000080 /* PCM In Reset */ 15288447a05SGarrett D'Amore 15388447a05SGarrett D'Amore /* Bits of FIFO Control Register2 */ 15488447a05SGarrett D'Amore #define M1575_FIFOCR2_SPORST 0x80000000 /* SPDIF Out FIFO Reset */ 15588447a05SGarrett D'Amore #define M1575_FIFOCR2_SPIRST 0x00800000 /* SPDIF In FIFO Reset */ 15688447a05SGarrett D'Amore #define M1575_FIFOCR2_LFEORST 0x00008000 /* LFE Out FIFO Reset */ 15788447a05SGarrett D'Amore #define M1575_FIFOCR2_CENORST 0x00000080 /* CENTER Out Reset */ 15888447a05SGarrett D'Amore 15988447a05SGarrett D'Amore /* Bits of FIFO Control Register3 */ 16088447a05SGarrett D'Amore #define M1575_FIFOCR3_PCMI2RST 0x00800000 /* PCM In2 FIFO Reset */ 16188447a05SGarrett D'Amore #define M1575_FIFOCR3_MICI2RST 0x00008000 /* MIC In2 FIFO Reset */ 16288447a05SGarrett D'Amore #define M1575_FIFOCR3_I2SIRST 0x00000080 /* I2S In FIFO Reset */ 16388447a05SGarrett D'Amore 16488447a05SGarrett D'Amore /* Bits of DMA Control Register */ 16588447a05SGarrett D'Amore #define M1575_DMACR_PCMISTART 0x00000001 16688447a05SGarrett D'Amore #define M1575_DMACR_PCMOSTART 0x00000002 16788447a05SGarrett D'Amore #define M1575_DMACR_MICISTART 0x00000004 16888447a05SGarrett D'Amore #define M1575_DMACR_CSPOSTART 0x00000008 16988447a05SGarrett D'Amore #define M1575_DMACR_CENOSTART 0x00000010 17088447a05SGarrett D'Amore #define M1575_DMACR_LFEOSTART 0x00000020 17188447a05SGarrett D'Amore #define M1575_DMACR_SPISTART 0x00000040 17288447a05SGarrett D'Amore #define M1575_DMACR_SPOSTART 0x00000080 17388447a05SGarrett D'Amore #define M1575_DMACR_I2SISTART 0x00000100 17488447a05SGarrett D'Amore #define M1575_DMACR_PCMI2START 0x00000200 17588447a05SGarrett D'Amore #define M1575_DMACR_MICI2START 0x00000400 17688447a05SGarrett D'Amore #define M1575_DMACR_PCMIPAUSE 0x00010000 17788447a05SGarrett D'Amore #define M1575_DMACR_PCMOPAUSE 0x00020000 17888447a05SGarrett D'Amore #define M1575_DMACR_MICIPAUSE 0x00040000 17988447a05SGarrett D'Amore #define M1575_DMACR_CSPOPAUSE 0x00080000 18088447a05SGarrett D'Amore #define M1575_DMACR_CENOPAUSE 0x00100000 18188447a05SGarrett D'Amore #define M1575_DMACR_LFEOPAUSE 0x00200000 18288447a05SGarrett D'Amore #define M1575_DMACR_SPIPAUSE 0x00400000 18388447a05SGarrett D'Amore #define M1575_DMACR_SPOPAUSE 0x00800000 18488447a05SGarrett D'Amore #define M1575_DMACR_I2SIPAUSE 0x01000000 18588447a05SGarrett D'Amore #define M1575_DMACR_PCMI2PAUSE 0x02000000 18688447a05SGarrett D'Amore #define M1575_DMACR_MICI2PAUSE 0x04000000 18788447a05SGarrett D'Amore 18888447a05SGarrett D'Amore #define M1575_DMACR_PAUSE_ALL 0x07ff0000 18988447a05SGarrett D'Amore 19088447a05SGarrett D'Amore /* Bits of INTRSR Interrupt Status Register */ 19188447a05SGarrett D'Amore #define M1575_INTRSR_GPIOINTR 0x0000002 19288447a05SGarrett D'Amore #define M1575_INTRSR_SPRINTR 0x0000020 19388447a05SGarrett D'Amore #define M1575_INTRSR_CPRINTR 0x0000080 19488447a05SGarrett D'Amore #define M1575_INTRSR_PCMIINTR 0x0010000 19588447a05SGarrett D'Amore #define M1575_INTRSR_PCMOINTR 0x0020000 19688447a05SGarrett D'Amore #define M1575_INTRSR_MICIINTR 0x0040000 19788447a05SGarrett D'Amore #define M1575_INTRSR_CSPOINTR 0x0080000 19888447a05SGarrett D'Amore #define M1575_INTRSR_CENOINTR 0x0100000 19988447a05SGarrett D'Amore #define M1575_INTRSR_LFEOINTR 0x0200000 20088447a05SGarrett D'Amore #define M1575_INTRSR_SPIINTR 0x0400000 20188447a05SGarrett D'Amore #define M1575_INTRSR_SPOINTR 0x0800000 20288447a05SGarrett D'Amore #define M1575_INTRSR_I2SIINTR 0x1000000 20388447a05SGarrett D'Amore #define M1575_INTRSR_PCMI2INTR 0x2000000 20488447a05SGarrett D'Amore #define M1575_INTRSR_MICI2INTR 0x4000000 20588447a05SGarrett D'Amore 20688447a05SGarrett D'Amore #define M1575_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 20788447a05SGarrett D'Amore M1575_INTRSR_SPRINTR |\ 20888447a05SGarrett D'Amore M1575_INTRSR_CPRINTR |\ 20988447a05SGarrett D'Amore M1575_INTRSR_PCMIINTR |\ 21088447a05SGarrett D'Amore M1575_INTRSR_PCMOINTR |\ 21188447a05SGarrett D'Amore M1575_INTRSR_MICIINTR |\ 21288447a05SGarrett D'Amore M1575_INTRSR_CSPOINTR |\ 21388447a05SGarrett D'Amore M1575_INTRSR_CENOINTR |\ 21488447a05SGarrett D'Amore M1575_INTRSR_LFEOINTR |\ 21588447a05SGarrett D'Amore M1575_INTRSR_SPIINTR |\ 21688447a05SGarrett D'Amore M1575_INTRSR_SPOINTR |\ 21788447a05SGarrett D'Amore M1575_INTRSR_I2SIINTR |\ 21888447a05SGarrett D'Amore M1575_INTRSR_PCMI2INTR|\ 21988447a05SGarrett D'Amore M1575_INTRSR_MICI2INTR) 22088447a05SGarrett D'Amore 22188447a05SGarrett D'Amore #define M1575_UNUSED_INTR_MASK (M1575_INTRSR_GPIOINTR |\ 22288447a05SGarrett D'Amore M1575_INTRSR_SPRINTR |\ 22388447a05SGarrett D'Amore M1575_INTRSR_CPRINTR |\ 22488447a05SGarrett D'Amore M1575_INTRSR_MICIINTR |\ 22588447a05SGarrett D'Amore M1575_INTRSR_CSPOINTR |\ 22688447a05SGarrett D'Amore M1575_INTRSR_CENOINTR |\ 22788447a05SGarrett D'Amore M1575_INTRSR_LFEOINTR |\ 22888447a05SGarrett D'Amore M1575_INTRSR_SPIINTR |\ 22988447a05SGarrett D'Amore M1575_INTRSR_SPOINTR |\ 23088447a05SGarrett D'Amore M1575_INTRSR_I2SIINTR |\ 23188447a05SGarrett D'Amore M1575_INTRSR_PCMI2INTR|\ 23288447a05SGarrett D'Amore M1575_INTRSR_MICI2INTR) 23388447a05SGarrett D'Amore 23488447a05SGarrett D'Amore /* Defines a generic clear for all MIC and PCM Status Registers */ 23588447a05SGarrett D'Amore #define M1575_SR_CLR 0x001e 23688447a05SGarrett D'Amore #define M1575_SR_DMACS 0x0001 23788447a05SGarrett D'Amore 23888447a05SGarrett D'Amore /* Defines a generic RESET for all MIC and PCM Control Registers */ 23988447a05SGarrett D'Amore #define M1575_CR_IOCE 0x10 24088447a05SGarrett D'Amore #define M1575_CR_RR 0x02 24188447a05SGarrett D'Amore 24288447a05SGarrett D'Amore /* Bits of PCM In Status Register */ 24388447a05SGarrett D'Amore #define M1575_PCMISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 24488447a05SGarrett D'Amore #define M1575_PCMISR_CELV 0x02 24588447a05SGarrett D'Amore #define M1575_PCMISR_LVBCI 0x04 24688447a05SGarrett D'Amore #define M1575_PCMISR_BCIS 0x08 24788447a05SGarrett D'Amore #define M1575_PCMISR_FIFOE 0x10 24888447a05SGarrett D'Amore 24988447a05SGarrett D'Amore /* Bits in PCM In Control Register */ 25088447a05SGarrett D'Amore #define M1575_PCMICR_RR 0x02 /* Reset */ 25188447a05SGarrett D'Amore #define M1575_PCMICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 25288447a05SGarrett D'Amore #define M1575_PCMICR_IOCE 0x10 /* Intr On Completion Enable */ 25388447a05SGarrett D'Amore 25488447a05SGarrett D'Amore /* Bits of PCM Out Status Register */ 25588447a05SGarrett D'Amore #define M1575_PCMOSR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 25688447a05SGarrett D'Amore #define M1575_PCMOSR_CELV 0x02 25788447a05SGarrett D'Amore #define M1575_PCMOSR_LVBCI 0x04 25888447a05SGarrett D'Amore #define M1575_PCMOSR_BCIS 0x08 25988447a05SGarrett D'Amore #define M1575_PCMOSR_FIFOE 0x10 26088447a05SGarrett D'Amore 26188447a05SGarrett D'Amore /* Bits in PCM Out Control Register */ 26288447a05SGarrett D'Amore #define M1575_PCMOCR_RR 0x02 /* Reset */ 26388447a05SGarrett D'Amore #define M1575_PCMOCR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 26488447a05SGarrett D'Amore #define M1575_PCMOCR_IOCE 0x10 /* Intr On Completion Enable */ 26588447a05SGarrett D'Amore 26688447a05SGarrett D'Amore /* Bits of MIC In Status Register */ 26788447a05SGarrett D'Amore #define M1575_MICISR_DMACS 0x01 /* DMACS=0 if DMA Engine is IDLE */ 26888447a05SGarrett D'Amore #define M1575_MICISR_CELV 0x02 26988447a05SGarrett D'Amore #define M1575_MICISR_LVBCI 0x04 27088447a05SGarrett D'Amore #define M1575_MICISR_BCIS 0x08 27188447a05SGarrett D'Amore #define M1575_MICISR_FIFOE 0x10 27288447a05SGarrett D'Amore 27388447a05SGarrett D'Amore /* Bits in PCM In Control Register */ 27488447a05SGarrett D'Amore #define M1575_MICICR_RR 0x02 /* Reset */ 27588447a05SGarrett D'Amore #define M1575_MICICR_LVBIE 0x04 /* Last valid Buffer Intr Enable */ 27688447a05SGarrett D'Amore #define M1575_MICICR_IOCE 0x10 /* Intr On Completion Enable */ 27788447a05SGarrett D'Amore 27888447a05SGarrett D'Amore /* Bits in System Control Register */ 27988447a05SGarrett D'Amore #define M1575_SCR_WARMRST 0x00000001 28088447a05SGarrett D'Amore #define M1575_SCR_COLDRST 0x00000002 2810e7a77f3SGarrett D'Amore #define M1575_SCR_SPDIF_SLOT 0x00300000 /* 1=7/8, 2=6/9, 3=10/11 */ 2820e7a77f3SGarrett D'Amore #define M1575_SCR_RECMOD 0x000c0000 /* 0 = 16bit, 1=20 bit */ 2830e7a77f3SGarrett D'Amore #define M1575_SCR_PCMMOD 0x00030000 /* 0 = 16bit, 1=20 bit */ 2840e7a77f3SGarrett D'Amore #define M1575_SCR_6CHL_MASK 0x0000c000 /* FL, FR, C, BL, BR, LFE */ 2850e7a77f3SGarrett D'Amore #define M1575_SCR_6CHL_0 0x00000000 /* channel ordering */ 2860e7a77f3SGarrett D'Amore #define M1575_SCR_6CHL_1 0x00004000 /* FL, C, FR, BL, BR, LFE */ 2870e7a77f3SGarrett D'Amore #define M1575_SCR_6CHL_2 0x00008000 /* FL, FR, C, LFE, BL, BR */ 2880e7a77f3SGarrett D'Amore #define M1575_SCR_6CHL_3 0x0000c000 /* FL, C, FR, LFE, BL, BR */ 2890e7a77f3SGarrett D'Amore #define M1575_SCR_CHAMOD_MASK 0x00000300 /* 2, 4, or 6 channel */ 2900e7a77f3SGarrett D'Amore #define M1575_SCR_CHAMOD_2 0x00000000 /* 2 channel */ 2910e7a77f3SGarrett D'Amore #define M1575_SCR_CHAMOD_4 0x00000100 /* 4 channel surround */ 2920e7a77f3SGarrett D'Amore #define M1575_SCR_CHAMOD_6 0x00000200 /* 6 channel (5.1) surround */ 29388447a05SGarrett D'Amore #define M1575_SCR_DRENT 0x40000000 29488447a05SGarrett D'Amore #define M1575_SCR_MSTRST 0x80000000 29588447a05SGarrett D'Amore 29688447a05SGarrett D'Amore /* Bits in System Status Register */ 29788447a05SGarrett D'Amore #define M1575_SSR_RSTBLK 0x00000002 29888447a05SGarrett D'Amore #define M1575_SSR_FACCS_MSK 0x00000018 29988447a05SGarrett D'Amore #define M1575_SSR_SCID 0x00000040 30088447a05SGarrett D'Amore 30188447a05SGarrett D'Amore /* Bits in Command Port Register */ 30288447a05SGarrett D'Amore #define M1575_CPR_ACSCS 0x0100 /* Audio Codec for cmd 1=codec 2 */ 30388447a05SGarrett D'Amore #define M1575_CPR_READ 0x0080 30488447a05SGarrett D'Amore 30588447a05SGarrett D'Amore /* Bits in Cmd Status Port Register */ 30688447a05SGarrett D'Amore #define M1575_CSPSR_SUCC 0x08 /* cmd successful */ 30788447a05SGarrett D'Amore #define M1575_CSPSR_RDRDY 0x02 /* ready for read cmd */ 30888447a05SGarrett D'Amore #define M1575_CSPSR_WRRDY 0x01 /* ready for write cmd */ 30988447a05SGarrett D'Amore #define M1575_PCMI2CR_RR 0x02 /* Reset */ 31088447a05SGarrett D'Amore #define M1575_MICI2CR_RR 0x02 /* Reset */ 31188447a05SGarrett D'Amore #define M1575_CSPOCR_RR 0x02 /* Reset */ 31288447a05SGarrett D'Amore 31388447a05SGarrett D'Amore /* Bits in Interface Control Register */ 31488447a05SGarrett D'Amore #define M1575_INTFCR_RSTREL 0x02000000 31588447a05SGarrett D'Amore #define M1575_INTFCR_RSTBLK 0x00200000 31688447a05SGarrett D'Amore #define M1575_INTFCR_MICENB 0x00100000 31788447a05SGarrett D'Amore #define M1575_INTFCR_PCMIENB 0x00080000 31888447a05SGarrett D'Amore #define M1575_INTFCR_MICI2ENB 0x00040000 31988447a05SGarrett D'Amore #define M1575_INTFCR_PCMI2ENB 0x00020000 32088447a05SGarrett D'Amore #define M1575_INTFCR_MICI2SEL 0x00008000 32188447a05SGarrett D'Amore #define M1575_INTFCR_MICISEL 0x00004000 32288447a05SGarrett D'Amore #define M1575_INTFCR_PCMOENB 0x00000002 32388447a05SGarrett D'Amore 32488447a05SGarrett D'Amore #define M1575_INTRCR_CPRINTR 0x00000080 32588447a05SGarrett D'Amore #define M1575_INTRCR_SPRINTR 0x00000020 32688447a05SGarrett D'Amore #define M1575_INTRCR_GPIOINTR 0x00000002 32788447a05SGarrett D'Amore 32888447a05SGarrett D'Amore /* Bits of Recv Tag Slot Register */ 32988447a05SGarrett D'Amore #define M1575_RTSR_SACRDY 0x20u /* 2nd Audio Codec Rdy */ 33088447a05SGarrett D'Amore #define M1575_RTSR_FACRDY 0x80u /* 1st Audio Codec Rdy */ 33188447a05SGarrett D'Amore 33288447a05SGarrett D'Amore /* Semaphore busy */ 33388447a05SGarrett D'Amore #define M1575_CASR_SEMBSY 0x80000000 33488447a05SGarrett D'Amore 33588447a05SGarrett D'Amore /* 33688447a05SGarrett D'Amore * buffer descripter list entry, see M1575 datasheet 33788447a05SGarrett D'Amore */ 33888447a05SGarrett D'Amore #define IOC 0x8000 33988447a05SGarrett D'Amore #define BUP 0x4000 34088447a05SGarrett D'Amore 34188447a05SGarrett D'Amore struct m1575_bd_entry { 34288447a05SGarrett D'Amore uint32_t buf_base; /* the address of the buffer */ 34388447a05SGarrett D'Amore uint16_t buf_len; /* the number of samples */ 34488447a05SGarrett D'Amore uint16_t buf_cmd; 34588447a05SGarrett D'Amore }; 34688447a05SGarrett D'Amore typedef struct m1575_bd_entry m1575_bd_entry_t; 34788447a05SGarrett D'Amore 34888447a05SGarrett D'Amore struct audio1575_port { 34988447a05SGarrett D'Amore struct audio1575_state *statep; 35088447a05SGarrett D'Amore ddi_dma_handle_t samp_dmah; 35188447a05SGarrett D'Amore ddi_acc_handle_t samp_acch; 35288447a05SGarrett D'Amore size_t samp_size; 35388447a05SGarrett D'Amore caddr_t samp_kaddr; 35488447a05SGarrett D'Amore uint32_t samp_paddr; 35588447a05SGarrett D'Amore 35688447a05SGarrett D'Amore ddi_dma_handle_t bdl_dmah; 35788447a05SGarrett D'Amore ddi_acc_handle_t bdl_acch; 35888447a05SGarrett D'Amore size_t bdl_size; 35988447a05SGarrett D'Amore caddr_t bdl_kaddr; 36088447a05SGarrett D'Amore uint32_t bdl_paddr; 36188447a05SGarrett D'Amore 36288447a05SGarrett D'Amore int num; 363*68c47f65SGarrett D'Amore unsigned nframes; 364*68c47f65SGarrett D'Amore uint32_t offset; 36588447a05SGarrett D'Amore uint64_t count; 36688447a05SGarrett D'Amore uint8_t nchan; 36788447a05SGarrett D'Amore 36888447a05SGarrett D'Amore unsigned sync_dir; 36988447a05SGarrett D'Amore 37088447a05SGarrett D'Amore audio_engine_t *engine; 37188447a05SGarrett D'Amore }; 37288447a05SGarrett D'Amore typedef struct audio1575_port audio1575_port_t; 37388447a05SGarrett D'Amore 37488447a05SGarrett D'Amore 37588447a05SGarrett D'Amore /* 37688447a05SGarrett D'Amore * audio1575_state_t per instance state and operation data 37788447a05SGarrett D'Amore */ 37888447a05SGarrett D'Amore struct audio1575_state { 37988447a05SGarrett D'Amore kmutex_t lock; /* intr mutex */ 38088447a05SGarrett D'Amore dev_info_t *dip; /* dev instance ptr */ 38188447a05SGarrett D'Amore audio_dev_t *adev; /* audio handle */ 38288447a05SGarrett D'Amore ac97_t *ac97; /* ac'97 handle */ 38388447a05SGarrett D'Amore audio1575_port_t *ports[2]; /* DMA engines */ 38488447a05SGarrett D'Amore 38588447a05SGarrett D'Amore ddi_acc_handle_t pcih; /* pci config space */ 38688447a05SGarrett D'Amore 38788447a05SGarrett D'Amore ddi_acc_handle_t regsh; /* audio i/o regs */ 38888447a05SGarrett D'Amore caddr_t regsp; /* base of i/o regs */ 38988447a05SGarrett D'Amore 3900e7a77f3SGarrett D'Amore uint8_t maxch; /* maximum channels */ 39188447a05SGarrett D'Amore }; 39288447a05SGarrett D'Amore typedef struct audio1575_state audio1575_state_t; 39388447a05SGarrett D'Amore 39488447a05SGarrett D'Amore /* audio i/o register macros */ 39588447a05SGarrett D'Amore #define GET8(reg) \ 39688447a05SGarrett D'Amore ddi_get8(statep->regsh, (void *)(statep->regsp + (reg))) 39788447a05SGarrett D'Amore 39888447a05SGarrett D'Amore #define GET16(reg) \ 39988447a05SGarrett D'Amore ddi_get16(statep->regsh, (void *)(statep->regsp + (reg))) 40088447a05SGarrett D'Amore 40188447a05SGarrett D'Amore #define GET32(reg) \ 40288447a05SGarrett D'Amore ddi_get32(statep->regsh, (void *)(statep->regsp + (reg))) 40388447a05SGarrett D'Amore 40488447a05SGarrett D'Amore #define PUT8(reg, val) \ 40588447a05SGarrett D'Amore ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 40688447a05SGarrett D'Amore 40788447a05SGarrett D'Amore #define PUT16(reg, val) \ 40888447a05SGarrett D'Amore ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 40988447a05SGarrett D'Amore 41088447a05SGarrett D'Amore #define PUT32(reg, val) \ 41188447a05SGarrett D'Amore ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val)) 41288447a05SGarrett D'Amore 41388447a05SGarrett D'Amore #define SET8(reg, bit) PUT8(reg, GET8(reg) | (bit)) 41488447a05SGarrett D'Amore #define SET16(reg, bit) PUT16(reg, GET16(reg) | (bit)) 41588447a05SGarrett D'Amore #define SET32(reg, bit) PUT32(reg, GET32(reg) | (bit)) 41688447a05SGarrett D'Amore #define CLR8(reg, bit) PUT8(reg, GET8(reg) & ~(bit)) 41788447a05SGarrett D'Amore #define CLR16(reg, bit) PUT16(reg, GET16(reg) & ~(bit)) 41888447a05SGarrett D'Amore #define CLR32(reg, bit) PUT32(reg, GET32(reg) & ~(bit)) 41988447a05SGarrett D'Amore 42088447a05SGarrett D'Amore 42188447a05SGarrett D'Amore #endif /* AUDIO1575_H */ 422