1015a6ef6SSaurabh Misra /* 2015a6ef6SSaurabh Misra * CDDL HEADER START 3015a6ef6SSaurabh Misra * 4015a6ef6SSaurabh Misra * The contents of this file are subject to the terms of the 5015a6ef6SSaurabh Misra * Common Development and Distribution License (the "License"). 6015a6ef6SSaurabh Misra * You may not use this file except in compliance with the License. 7015a6ef6SSaurabh Misra * 8015a6ef6SSaurabh Misra * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9015a6ef6SSaurabh Misra * or http://www.opensolaris.org/os/licensing. 10015a6ef6SSaurabh Misra * See the License for the specific language governing permissions 11015a6ef6SSaurabh Misra * and limitations under the License. 12015a6ef6SSaurabh Misra * 13015a6ef6SSaurabh Misra * When distributing Covered Code, include this CDDL HEADER in each 14015a6ef6SSaurabh Misra * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15015a6ef6SSaurabh Misra * If applicable, add the following below this CDDL HEADER, with the 16015a6ef6SSaurabh Misra * fields enclosed by brackets "[]" replaced with your own identifying 17015a6ef6SSaurabh Misra * information: Portions Copyright [yyyy] [name of copyright owner] 18015a6ef6SSaurabh Misra * 19015a6ef6SSaurabh Misra * CDDL HEADER END 20015a6ef6SSaurabh Misra */ 21015a6ef6SSaurabh Misra /* 22*5e8715b9SGary Mills * Copyright (c) 2012 Gary Mills 23*5e8715b9SGary Mills * 24015a6ef6SSaurabh Misra * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25015a6ef6SSaurabh Misra * Use is subject to license terms. 26015a6ef6SSaurabh Misra */ 27015a6ef6SSaurabh Misra 28015a6ef6SSaurabh Misra #ifndef _ATGE_L1E_REG_H 29015a6ef6SSaurabh Misra #define _ATGE_L1E_REG_H 30015a6ef6SSaurabh Misra 31015a6ef6SSaurabh Misra #ifdef __cplusplus 32015a6ef6SSaurabh Misra extern "C" { 33015a6ef6SSaurabh Misra #endif 34015a6ef6SSaurabh Misra 35015a6ef6SSaurabh Misra /* 36015a6ef6SSaurabh Misra * Number of RX Rings (or pages) we use. 37015a6ef6SSaurabh Misra */ 38015a6ef6SSaurabh Misra #define L1E_RX_PAGES 2 39015a6ef6SSaurabh Misra 40015a6ef6SSaurabh Misra #pragma pack(1) 41015a6ef6SSaurabh Misra typedef struct rx_rs { 42015a6ef6SSaurabh Misra uint32_t seqno; 43015a6ef6SSaurabh Misra uint32_t length; 44015a6ef6SSaurabh Misra uint32_t flags; 45015a6ef6SSaurabh Misra uint32_t vtags; 46015a6ef6SSaurabh Misra } rx_rs_t; 47015a6ef6SSaurabh Misra 48015a6ef6SSaurabh Misra typedef struct rx_cmb { 49015a6ef6SSaurabh Misra uint32_t cmb[L1E_RX_PAGES]; 50015a6ef6SSaurabh Misra } rx_cmb_t; 51015a6ef6SSaurabh Misra #pragma pack() 52015a6ef6SSaurabh Misra 53*5e8715b9SGary Mills /* Master configuration */ 54*5e8715b9SGary Mills #define L1E_MASTER_CFG 0x1400 55*5e8715b9SGary Mills #define L1E_MASTER_RESET 0x00000001 56*5e8715b9SGary Mills #define L1E_MASTER_MTIMER_ENB 0x00000002 57*5e8715b9SGary Mills #define L1E_MASTER_IM_TX_TIMER_ENB 0x00000004 58*5e8715b9SGary Mills #define L1E_MASTER_MANUAL_INT_ENB 0x00000008 59*5e8715b9SGary Mills #define L1E_MASTER_IM_RX_TIMER_ENB 0x00000020 60*5e8715b9SGary Mills #define L1E_MASTER_CHIP_REV_MASK 0x00FF0000 61*5e8715b9SGary Mills #define L1E_MASTER_CHIP_ID_MASK 0xFF000000 62*5e8715b9SGary Mills #define L1E_MASTER_CHIP_REV_SHIFT 16 63*5e8715b9SGary Mills #define L1E_MASTER_CHIP_ID_SHIFT 24 64*5e8715b9SGary Mills 65*5e8715b9SGary Mills 66015a6ef6SSaurabh Misra /* 67015a6ef6SSaurabh Misra * DMA CFG registers (L1E specific). 68015a6ef6SSaurabh Misra */ 69015a6ef6SSaurabh Misra #define DMA_CFG_RD_REQ_PRI 0x00000400 70015a6ef6SSaurabh Misra #define DMA_CFG_TXCMB_ENB 0x00100000 71015a6ef6SSaurabh Misra #define DMA_CFG_RD_BURST_MASK 0x07 72015a6ef6SSaurabh Misra #define DMA_CFG_RD_BURST_SHIFT 4 73015a6ef6SSaurabh Misra #define DMA_CFG_WR_BURST_MASK 0x07 74015a6ef6SSaurabh Misra #define DMA_CFG_WR_BURST_SHIFT 7 75015a6ef6SSaurabh Misra 76015a6ef6SSaurabh Misra #define L1E_TX_RING_CNT_MIN 32 77015a6ef6SSaurabh Misra #define L1E_TX_RING_CNT_MAX 1020 78015a6ef6SSaurabh Misra #define L1E_TX_RING_ALIGN 8 79015a6ef6SSaurabh Misra #define L1E_RX_PAGE_ALIGN 32 80015a6ef6SSaurabh Misra #define L1E_CMB_ALIGN 32 81015a6ef6SSaurabh Misra #define L1E_MAX_FRAMELEN ETHERMAX 82015a6ef6SSaurabh Misra 83015a6ef6SSaurabh Misra #define L1E_RX_PAGE_SZ_MIN (8 * 1024) 84015a6ef6SSaurabh Misra #define L1E_RX_PAGE_SZ_MAX (1024 * 1024) 85015a6ef6SSaurabh Misra #define L1E_RX_FRAMES_PAGE 128 86015a6ef6SSaurabh Misra #define L1E_RX_PAGE_SZ \ 87015a6ef6SSaurabh Misra (ROUNDUP(L1E_MAX_FRAMELEN, L1E_RX_PAGE_ALIGN) * L1E_RX_FRAMES_PAGE) 88015a6ef6SSaurabh Misra #define L1E_TX_CMB_SZ (sizeof (uint32_t)) 89015a6ef6SSaurabh Misra #define L1E_RX_CMB_SZ (sizeof (uint32_t)) 90015a6ef6SSaurabh Misra 91015a6ef6SSaurabh Misra #define L1E_PROC_MAX \ 92015a6ef6SSaurabh Misra ((L1E_RX_PAGE_SZ * L1E_RX_PAGES) / ETHERMAX) 93015a6ef6SSaurabh Misra #define L1E_PROC_DEFAULT (L1E_PROC_MAX / 4) 94015a6ef6SSaurabh Misra 95015a6ef6SSaurabh Misra #define L1E_INTRS \ 96015a6ef6SSaurabh Misra (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 97015a6ef6SSaurabh Misra INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ 98015a6ef6SSaurabh Misra INTR_TX_FIFO_UNDERRUN | INTR_SMB) 99015a6ef6SSaurabh Misra 100015a6ef6SSaurabh Misra #define L1E_RSS_IDT_TABLE0 0x1560 101015a6ef6SSaurabh Misra #define L1E_RSS_CPU 0x157C 102015a6ef6SSaurabh Misra 103015a6ef6SSaurabh Misra #define L1E_SRAM_RX_FIFO_LEN 0x1524 104015a6ef6SSaurabh Misra 105015a6ef6SSaurabh Misra #define L1E_PHY_STATUS 0x1418 106015a6ef6SSaurabh Misra #define PHY_STATUS_100M 0x00020000 107015a6ef6SSaurabh Misra 108015a6ef6SSaurabh Misra #define L1E_SMB_STAT_TIMER 0x15C4 109015a6ef6SSaurabh Misra 110015a6ef6SSaurabh Misra #define GPHY_CTRL_EXT_RESET 0x0001 111015a6ef6SSaurabh Misra #define GPHY_CTRL_PIPE_MOD 0x0002 112015a6ef6SSaurabh Misra #define GPHY_CTRL_BERT_START 0x0010 113015a6ef6SSaurabh Misra #define GPHY_CTRL_GL1E_25M_ENB 0x0020 114015a6ef6SSaurabh Misra #define GPHY_CTRL_LPW_EXIT 0x0040 115015a6ef6SSaurabh Misra #define GPHY_CTRL_PHY_IDDQ 0x0080 116015a6ef6SSaurabh Misra #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 117015a6ef6SSaurabh Misra #define GPHY_CTRL_PCLK_SEL_DIS 0x0200 118015a6ef6SSaurabh Misra #define GPHY_CTRL_HIB_EN 0x0400 119015a6ef6SSaurabh Misra #define GPHY_CTRL_HIB_PULSE 0x0800 120015a6ef6SSaurabh Misra #define GPHY_CTRL_SEL_ANA_RESET 0x1000 121015a6ef6SSaurabh Misra #define GPHY_CTRL_PHY_PLL_ON 0x2000 122015a6ef6SSaurabh Misra #define GPHY_CTRL_PWDOWN_HW 0x4000 123015a6ef6SSaurabh Misra 124015a6ef6SSaurabh Misra #define RXF_VALID 0x01 125015a6ef6SSaurabh Misra 126015a6ef6SSaurabh Misra #define L1E_RXF0_PAGE0 0x15F4 127015a6ef6SSaurabh Misra #define L1E_RXF0_PAGE1 0x15F5 128015a6ef6SSaurabh Misra 129015a6ef6SSaurabh Misra #define L1E_RXF0_PAGE0_ADDR_LO 0x1544 130015a6ef6SSaurabh Misra #define L1E_RXF0_PAGE1_ADDR_LO 0x1548 131015a6ef6SSaurabh Misra 132015a6ef6SSaurabh Misra #define L1E_RXF_PAGE_SIZE 0x1558 133015a6ef6SSaurabh Misra 134015a6ef6SSaurabh Misra #define L1E_INT_TRIG_THRESH 0x15C8 135015a6ef6SSaurabh Misra #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF 136015a6ef6SSaurabh Misra #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 137015a6ef6SSaurabh Misra #define INT_TRIG_TX_THRESH_SHIFT 0 138015a6ef6SSaurabh Misra #define INT_TRIG_RX_THRESH_SHIFT 16 139015a6ef6SSaurabh Misra 140015a6ef6SSaurabh Misra #define L1E_INT_TRIG_TIMER 0x15CC 141015a6ef6SSaurabh Misra #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF 142015a6ef6SSaurabh Misra #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF 143015a6ef6SSaurabh Misra #define INT_TRIG_TX_TIMER_SHIFT 0 144015a6ef6SSaurabh Misra #define INT_TRIG_RX_TIMER_SHIFT 16 145015a6ef6SSaurabh Misra 146015a6ef6SSaurabh Misra #define TX_COALSC_PKT_1e 0x15C8 /* W: L1E */ 147015a6ef6SSaurabh Misra #define RX_COALSC_PKT_1e 0x15CA /* W: L1E */ 148015a6ef6SSaurabh Misra #define TX_COALSC_TO_1e 0x15CC /* W: L1E */ 149015a6ef6SSaurabh Misra #define RX_COALSC_TO_1e 0x15CE /* W: L1E */ 150015a6ef6SSaurabh Misra 151015a6ef6SSaurabh Misra #define L1E_HOST_RXF0_PAGEOFF 0x1800 152015a6ef6SSaurabh Misra #define L1E_TPD_CONS_IDX 0x1804 153015a6ef6SSaurabh Misra #define L1E_HOST_RXF1_PAGEOFF 0x1808 154015a6ef6SSaurabh Misra #define L1E_HOST_RXF2_PAGEOFF 0x180C 155015a6ef6SSaurabh Misra #define L1E_HOST_RXF3_PAGEOFF 0x1810 156015a6ef6SSaurabh Misra #define L1E_RXF0_CMB0_ADDR_LO 0x1820 157015a6ef6SSaurabh Misra #define L1E_RXF0_CMB1_ADDR_LO 0x1824 158015a6ef6SSaurabh Misra #define L1E_RXF1_CMB0_ADDR_LO 0x1828 159015a6ef6SSaurabh Misra #define L1E_RXF1_CMB1_ADDR_LO 0x182C 160015a6ef6SSaurabh Misra #define L1E_RXF2_CMB0_ADDR_LO 0x1830 161015a6ef6SSaurabh Misra #define L1E_RXF2_CMB1_ADDR_LO 0x1834 162015a6ef6SSaurabh Misra #define L1E_RXF3_CMB0_ADDR_LO 0x1838 163015a6ef6SSaurabh Misra #define L1E_RXF3_CMB1_ADDR_LO 0x183C 164015a6ef6SSaurabh Misra #define L1E_TX_CMB_ADDR_LO 0x1840 165015a6ef6SSaurabh Misra #define L1E_SMB_ADDR_LO 0x1844 166015a6ef6SSaurabh Misra 167015a6ef6SSaurabh Misra #define L1E_RD_SEQNO_MASK 0x0000FFFF 168015a6ef6SSaurabh Misra #define L1E_RD_HASH_MASK 0xFFFF0000 169015a6ef6SSaurabh Misra #define L1E_RD_SEQNO_SHIFT 0 170015a6ef6SSaurabh Misra #define L1E_RD_HASH_SHIFT 16 171015a6ef6SSaurabh Misra #define L1E_RX_SEQNO(x) \ 172015a6ef6SSaurabh Misra (((x) & L1E_RD_SEQNO_MASK) >> L1E_RD_SEQNO_SHIFT) 173015a6ef6SSaurabh Misra #define L1E_RD_CSUM_MASK 0x0000FFFF 174015a6ef6SSaurabh Misra #define L1E_RD_LEN_MASK 0x3FFF0000 175015a6ef6SSaurabh Misra #define L1E_RD_CPU_MASK 0xC0000000 176015a6ef6SSaurabh Misra #define L1E_RD_CSUM_SHIFT 0 177015a6ef6SSaurabh Misra #define L1E_RD_LEN_SHIFT 16 178015a6ef6SSaurabh Misra #define L1E_RD_CPU_SHIFT 30 179015a6ef6SSaurabh Misra #define L1E_RX_CSUM(x) \ 180015a6ef6SSaurabh Misra (((x) & L1E_RD_CSUM_MASK) >> L1E_RD_CSUM_SHIFT) 181015a6ef6SSaurabh Misra #define L1E_RX_BYTES(x) \ 182015a6ef6SSaurabh Misra (((x) & L1E_RD_LEN_MASK) >> L1E_RD_LEN_SHIFT) 183015a6ef6SSaurabh Misra #define L1E_RX_CPU(x) \ 184015a6ef6SSaurabh Misra (((x) & L1E_RD_CPU_MASK) >> L1E_RD_CPU_SHIFT) 185015a6ef6SSaurabh Misra 186015a6ef6SSaurabh Misra #define L1E_RD_RSS_IPV4 0x00000001 187015a6ef6SSaurabh Misra #define L1E_RD_RSS_IPV4_TCP 0x00000002 188015a6ef6SSaurabh Misra #define L1E_RD_RSS_IPV6 0x00000004 189015a6ef6SSaurabh Misra #define L1E_RD_RSS_IPV6_TCP 0x00000008 190015a6ef6SSaurabh Misra #define L1E_RD_IPV6 0x00000010 191015a6ef6SSaurabh Misra #define L1E_RD_IPV4_FRAG 0x00000020 192015a6ef6SSaurabh Misra #define L1E_RD_IPV4_DF 0x00000040 193015a6ef6SSaurabh Misra #define L1E_RD_802_3 0x00000080 194015a6ef6SSaurabh Misra #define L1E_RD_VLAN 0x00000100 195015a6ef6SSaurabh Misra #define L1E_RD_ERROR 0x00000200 196015a6ef6SSaurabh Misra #define L1E_RD_IPV4 0x00000400 197015a6ef6SSaurabh Misra #define L1E_RD_UDP 0x00000800 198015a6ef6SSaurabh Misra #define L1E_RD_TCP 0x00001000 199015a6ef6SSaurabh Misra #define L1E_RD_BCAST 0x00002000 200015a6ef6SSaurabh Misra #define L1E_RD_MCAST 0x00004000 201015a6ef6SSaurabh Misra #define L1E_RD_PAUSE 0x00008000 202015a6ef6SSaurabh Misra #define L1E_RD_CRC 0x00010000 203015a6ef6SSaurabh Misra #define L1E_RD_CODE 0x00020000 204015a6ef6SSaurabh Misra #define L1E_RD_DRIBBLE 0x00040000 205015a6ef6SSaurabh Misra #define L1E_RD_RUNT 0x00080000 206015a6ef6SSaurabh Misra #define L1E_RD_OFLOW 0x00100000 207015a6ef6SSaurabh Misra #define L1E_RD_TRUNC 0x00200000 208015a6ef6SSaurabh Misra #define L1E_RD_IPCSUM_NOK 0x00400000 209015a6ef6SSaurabh Misra #define L1E_RD_TCP_UDPCSUM_NOK 0x00800000 210015a6ef6SSaurabh Misra #define L1E_RD_LENGTH_NOK 0x01000000 211015a6ef6SSaurabh Misra #define L1E_RD_DES_ADDR_FILTERED 0x02000000 212015a6ef6SSaurabh Misra 213015a6ef6SSaurabh Misra /* TX descriptor fields */ 214015a6ef6SSaurabh Misra #define L1E_TD_VLAN_MASK 0xFFFF0000 215015a6ef6SSaurabh Misra #define L1E_TD_PKT_INT 0x00008000 216015a6ef6SSaurabh Misra #define L1E_TD_DMA_INT 0x00004000 217015a6ef6SSaurabh Misra #define L1E_TD_VLAN_SHIFT 16 218015a6ef6SSaurabh Misra #define L1E_TX_VLAN_TAG(x) \ 219015a6ef6SSaurabh Misra (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 220015a6ef6SSaurabh Misra #define L1E_TD_BUFLEN_SHIFT 0 221015a6ef6SSaurabh Misra #define L1E_TD_MSS 0xFFF80000 222015a6ef6SSaurabh Misra #define L1E_TD_TSO_HDR 0x00040000 223015a6ef6SSaurabh Misra #define L1E_TD_TCPHDR_LEN 0x0003C000 224015a6ef6SSaurabh Misra #define L1E_TD_IPHDR_LEN 0x00003C00 225015a6ef6SSaurabh Misra #define L1E_TD_IPV6HDR_LEN2 0x00003C00 226015a6ef6SSaurabh Misra #define L1E_TD_LLC_SNAP 0x00000200 227015a6ef6SSaurabh Misra #define L1E_TD_VLAN_TAGGED 0x00000100 228015a6ef6SSaurabh Misra #define L1E_TD_UDPCSUM 0x00000080 229015a6ef6SSaurabh Misra #define L1E_TD_TCPCSUM 0x00000040 230015a6ef6SSaurabh Misra #define L1E_TD_IPCSUM 0x00000020 231015a6ef6SSaurabh Misra #define L1E_TD_IPV6HDR_LEN1 0x000000E0 232015a6ef6SSaurabh Misra #define L1E_TD_TSO 0x00000010 233015a6ef6SSaurabh Misra #define L1E_TD_CXSUM 0x00000008 234015a6ef6SSaurabh Misra #define L1E_TD_INSERT_VLAN_TAG 0x00000004 235015a6ef6SSaurabh Misra #define L1E_TD_IPV6 0x00000002 236015a6ef6SSaurabh Misra 237015a6ef6SSaurabh Misra #define L1E_TD_CSUM_PLOADOFFSET 0x00FF0000 238015a6ef6SSaurabh Misra #define L1E_TD_CSUM_XSUMOFFSET 0xFF000000 239015a6ef6SSaurabh Misra #define L1E_TD_CSUM_XSUMOFFSET_SHIFT 24 240015a6ef6SSaurabh Misra #define L1E_TD_CSUM_PLOADOFFSET_SHIFT 16 241015a6ef6SSaurabh Misra #define L1E_TD_MSS_SHIFT 19 242015a6ef6SSaurabh Misra #define L1E_TD_TCPHDR_LEN_SHIFT 14 243015a6ef6SSaurabh Misra #define L1E_TD_IPHDR_LEN_SHIFT 10 244015a6ef6SSaurabh Misra 245015a6ef6SSaurabh Misra #define L1E_JUMBO_FRAMELEN 8132 246015a6ef6SSaurabh Misra 247015a6ef6SSaurabh Misra #define L1E_TX_JUMBO_THRESH 0x1584 248015a6ef6SSaurabh Misra #define TX_JUMBO_THRESH_MASK 0x000007FF 249015a6ef6SSaurabh Misra #define TX_JUMBO_THRESH_SHIFT 0 250015a6ef6SSaurabh Misra #define TX_JUMBO_THRESH_UNIT 8 251015a6ef6SSaurabh Misra #define TX_JUMBO_THRESH_UNIT_SHIFT 3 252015a6ef6SSaurabh Misra 253015a6ef6SSaurabh Misra /* 254015a6ef6SSaurabh Misra * Statistics counters collected by the MAC. 255015a6ef6SSaurabh Misra * AR81xx requires register access to get MAC statistics 256015a6ef6SSaurabh Misra * and the format of statistics seems to be the same of L1 257015a6ef6SSaurabh Misra * except for tx_abort field in TX stats. So keep it separate for simplicity. 258015a6ef6SSaurabh Misra */ 259015a6ef6SSaurabh Misra #define L1E_RX_MIB_BASE 0x1700 260015a6ef6SSaurabh Misra #define L1E_TX_MIB_BASE 0x1760 261015a6ef6SSaurabh Misra 262015a6ef6SSaurabh Misra #pragma pack(1) 263015a6ef6SSaurabh Misra typedef struct smb { 264015a6ef6SSaurabh Misra /* Rx stats. */ 265015a6ef6SSaurabh Misra uint32_t rx_frames; 266015a6ef6SSaurabh Misra uint32_t rx_bcast_frames; 267015a6ef6SSaurabh Misra uint32_t rx_mcast_frames; 268015a6ef6SSaurabh Misra uint32_t rx_pause_frames; 269015a6ef6SSaurabh Misra uint32_t rx_control_frames; 270015a6ef6SSaurabh Misra uint32_t rx_crcerrs; 271015a6ef6SSaurabh Misra uint32_t rx_lenerrs; 272015a6ef6SSaurabh Misra uint32_t rx_bytes; 273015a6ef6SSaurabh Misra uint32_t rx_runts; 274015a6ef6SSaurabh Misra uint32_t rx_fragments; 275015a6ef6SSaurabh Misra uint32_t rx_pkts_64; 276015a6ef6SSaurabh Misra uint32_t rx_pkts_65_127; 277015a6ef6SSaurabh Misra uint32_t rx_pkts_128_255; 278015a6ef6SSaurabh Misra uint32_t rx_pkts_256_511; 279015a6ef6SSaurabh Misra uint32_t rx_pkts_512_1023; 280015a6ef6SSaurabh Misra uint32_t rx_pkts_1024_1518; 281015a6ef6SSaurabh Misra uint32_t rx_pkts_1519_max; 282015a6ef6SSaurabh Misra uint32_t rx_pkts_truncated; 283015a6ef6SSaurabh Misra uint32_t rx_fifo_oflows; 284015a6ef6SSaurabh Misra uint32_t rx_rrs_errs; 285015a6ef6SSaurabh Misra uint32_t rx_alignerrs; 286015a6ef6SSaurabh Misra uint32_t rx_bcast_bytes; 287015a6ef6SSaurabh Misra uint32_t rx_mcast_bytes; 288015a6ef6SSaurabh Misra uint32_t rx_pkts_filtered; 289015a6ef6SSaurabh Misra /* Tx stats. */ 290015a6ef6SSaurabh Misra uint32_t tx_frames; 291015a6ef6SSaurabh Misra uint32_t tx_bcast_frames; 292015a6ef6SSaurabh Misra uint32_t tx_mcast_frames; 293015a6ef6SSaurabh Misra uint32_t tx_pause_frames; 294015a6ef6SSaurabh Misra uint32_t tx_excess_defer; 295015a6ef6SSaurabh Misra uint32_t tx_control_frames; 296015a6ef6SSaurabh Misra uint32_t tx_deferred; 297015a6ef6SSaurabh Misra uint32_t tx_bytes; 298015a6ef6SSaurabh Misra uint32_t tx_pkts_64; 299015a6ef6SSaurabh Misra uint32_t tx_pkts_65_127; 300015a6ef6SSaurabh Misra uint32_t tx_pkts_128_255; 301015a6ef6SSaurabh Misra uint32_t tx_pkts_256_511; 302015a6ef6SSaurabh Misra uint32_t tx_pkts_512_1023; 303015a6ef6SSaurabh Misra uint32_t tx_pkts_1024_1518; 304015a6ef6SSaurabh Misra uint32_t tx_pkts_1519_max; 305015a6ef6SSaurabh Misra uint32_t tx_single_colls; 306015a6ef6SSaurabh Misra uint32_t tx_multi_colls; 307015a6ef6SSaurabh Misra uint32_t tx_late_colls; 308015a6ef6SSaurabh Misra uint32_t tx_excess_colls; 309015a6ef6SSaurabh Misra uint32_t tx_abort; 310015a6ef6SSaurabh Misra uint32_t tx_underrun; 311015a6ef6SSaurabh Misra uint32_t tx_desc_underrun; 312015a6ef6SSaurabh Misra uint32_t tx_lenerrs; 313015a6ef6SSaurabh Misra uint32_t tx_pkts_truncated; 314015a6ef6SSaurabh Misra uint32_t tx_bcast_bytes; 315015a6ef6SSaurabh Misra uint32_t tx_mcast_bytes; 316015a6ef6SSaurabh Misra } atge_l1e_smb_t; 317015a6ef6SSaurabh Misra #pragma pack() 318015a6ef6SSaurabh Misra 319015a6ef6SSaurabh Misra #ifdef __cplusplus 320015a6ef6SSaurabh Misra } 321015a6ef6SSaurabh Misra #endif 322015a6ef6SSaurabh Misra 323015a6ef6SSaurabh Misra #endif /* _ATGE_L1E_REG_H */ 324